system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void block_normalization_kernel(float* histograms, float* descriptor, int histograms_step, int block_grid_width, int block_grid_height, int block_width, int block_height, int num_bins, int cell_grid_width, int block_stride_x, int block_stride_y)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block will process 8 hog blocks. Each hog block has 4 cells.
// Each cell has 9 bins.
__shared__ float s_blocks[9 * 4 * 8];
__shared__ float L1_norm[8];
int block_x = blockIdx.x * 8 + threadIdx.z;
if(block_x >= block_grid_width)
{
return;
}
int block_y = blockIdx.y;
if(block_y >= block_grid_height)
{
return;
}
int block_idx = block_y * blockDim.y + block_x;
int cell_x = block_x * block_stride_x + threadIdx.y % 2;
int cell_y = block_y * block_stride_y + threadIdx.y / 2;
int hist_idx = histograms_step * cell_y + num_bins * (cell_x) + threadIdx.x;
int s_blocks_idx = 9 * threadIdx.y + threadIdx.x;
s_blocks[s_blocks_idx] = histograms[hist_idx];
__syncthreads();
int thread_id = 36 * threadIdx.z + 9 * threadIdx.y + threadIdx.x;
int elements_per_block = block_height * block_width * num_bins;
if(thread_id < 8)
{
L1_norm[thread_id] = 0.0f;
for(int i = 0; i < elements_per_block; ++i)
{
L1_norm[thread_id] += s_blocks[elements_per_block * thread_id + i];
}
}
__syncthreads();
descriptor[elements_per_block * block_idx + s_blocks_idx] =
s_blocks[s_blocks_idx] / L1_norm[threadIdx.z];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void block_normalization_kernel(float* histograms, float* descriptor, int histograms_step, int block_grid_width, int block_grid_height, int block_width, int block_height, int num_bins, int cell_grid_width, int block_stride_x, int block_stride_y)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block will process 8 hog blocks. Each hog block has 4 cells.
// Each cell has 9 bins.
__shared__ float s_blocks[9 * 4 * 8];
__shared__ float L1_norm[8];
int block_x = blockIdx.x * 8 + threadIdx.z;
if(block_x >= block_grid_width)
{
return;
}
int block_y = blockIdx.y;
if(block_y >= block_grid_height)
{
return;
}
int block_idx = block_y * blockDim.y + block_x;
int cell_x = block_x * block_stride_x + threadIdx.y % 2;
int cell_y = block_y * block_stride_y + threadIdx.y / 2;
int hist_idx = histograms_step * cell_y + num_bins * (cell_x) + threadIdx.x;
int s_blocks_idx = 9 * threadIdx.y + threadIdx.x;
s_blocks[s_blocks_idx] = histograms[hist_idx];
__syncthreads();
int thread_id = 36 * threadIdx.z + 9 * threadIdx.y + threadIdx.x;
int elements_per_block = block_height * block_width * num_bins;
if(thread_id < 8)
{
L1_norm[thread_id] = 0.0f;
for(int i = 0; i < elements_per_block; ++i)
{
L1_norm[thread_id] += s_blocks[elements_per_block * thread_id + i];
}
}
__syncthreads();
descriptor[elements_per_block * block_idx + s_blocks_idx] =
s_blocks[s_blocks_idx] / L1_norm[threadIdx.z];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void block_normalization_kernel(float* histograms, float* descriptor, int histograms_step, int block_grid_width, int block_grid_height, int block_width, int block_height, int num_bins, int cell_grid_width, int block_stride_x, int block_stride_y)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block will process 8 hog blocks. Each hog block has 4 cells.
// Each cell has 9 bins.
__shared__ float s_blocks[9 * 4 * 8];
__shared__ float L1_norm[8];
int block_x = blockIdx.x * 8 + threadIdx.z;
if(block_x >= block_grid_width)
{
return;
}
int block_y = blockIdx.y;
if(block_y >= block_grid_height)
{
return;
}
int block_idx = block_y * blockDim.y + block_x;
int cell_x = block_x * block_stride_x + threadIdx.y % 2;
int cell_y = block_y * block_stride_y + threadIdx.y / 2;
int hist_idx = histograms_step * cell_y + num_bins * (cell_x) + threadIdx.x;
int s_blocks_idx = 9 * threadIdx.y + threadIdx.x;
s_blocks[s_blocks_idx] = histograms[hist_idx];
__syncthreads();
int thread_id = 36 * threadIdx.z + 9 * threadIdx.y + threadIdx.x;
int elements_per_block = block_height * block_width * num_bins;
if(thread_id < 8)
{
L1_norm[thread_id] = 0.0f;
for(int i = 0; i < elements_per_block; ++i)
{
L1_norm[thread_id] += s_blocks[elements_per_block * thread_id + i];
}
}
__syncthreads();
descriptor[elements_per_block * block_idx + s_blocks_idx] =
s_blocks[s_blocks_idx] / L1_norm[threadIdx.z];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26block_normalization_kernelPfS_iiiiiiiii
.globl _Z26block_normalization_kernelPfS_iiiiiiiii
.p2align 8
.type _Z26block_normalization_kernelPfS_iiiiiiiii,@function
_Z26block_normalization_kernelPfS_iiiiiiiii:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v2, v0, 20, 10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s14, 3, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB0_8
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
v_bfe_u32 v8, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b32 s7, s[0:1], 0x44
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 1, v8
v_and_b32_e32 v4, 1, v8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v1, s2, v[4:5]
s_load_b64 s[2:3], s[0:1], 0x1c
v_mul_lo_u32 v3, v5, s4
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v4, v6, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v3, v4, v0, v3
v_mad_u32_u24 v0, v8, 9, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mul_i32 s4, s3, s2
s_lshr_b32 s5, s7, 16
s_mul_i32 s4, s4, s6
global_load_b32 v5, v[3:4], off
v_mad_u32_u24 v4, v2, 36, v0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v4
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v5, 2, v4
s_cmp_lt_i32 s4, 1
ds_store_b32 v5, v6 offset:1152
s_cbranch_scc1 .LBB0_7
v_add_nc_u32_e32 v5, 0x480, v5
s_mul_i32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s3, s3, s2
s_mov_b32 s2, s4
ds_load_b32 v6, v5
v_mul_lo_u32 v4, s3, v4
v_lshlrev_b32_e32 v4, 2, v4
.LBB0_5:
ds_load_b32 v7, v4
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v7, v6
s_cbranch_scc1 .LBB0_5
ds_store_b32 v5, v6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v3
ds_load_b32 v6, v2 offset:1152
s_and_b32 s2, 0xffff, s5
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v7, null, v6, v6, v5
v_div_scale_f32 v9, vcc_lo, v5, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v7, v8, 1.0
v_fmac_f32_e32 v8, v2, v8
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v9, v8
v_fma_f32 v10, -v7, v1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
v_fmac_f32_e32 v1, v10, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_fma_f32 v0, -v7, v1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v2, v0, v8, v1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v2, v6, v5
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26block_normalization_kernelPfS_iiiiiiiii
.amdhsa_group_segment_fixed_size 1184
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26block_normalization_kernelPfS_iiiiiiiii, .Lfunc_end0-_Z26block_normalization_kernelPfS_iiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1184
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26block_normalization_kernelPfS_iiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26block_normalization_kernelPfS_iiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void block_normalization_kernel(float* histograms, float* descriptor, int histograms_step, int block_grid_width, int block_grid_height, int block_width, int block_height, int num_bins, int cell_grid_width, int block_stride_x, int block_stride_y)
{
//TODO: make the buffer sizes dependent on an input or template parameter.
// Each thread block will process 8 hog blocks. Each hog block has 4 cells.
// Each cell has 9 bins.
__shared__ float s_blocks[9 * 4 * 8];
__shared__ float L1_norm[8];
int block_x = blockIdx.x * 8 + threadIdx.z;
if(block_x >= block_grid_width)
{
return;
}
int block_y = blockIdx.y;
if(block_y >= block_grid_height)
{
return;
}
int block_idx = block_y * blockDim.y + block_x;
int cell_x = block_x * block_stride_x + threadIdx.y % 2;
int cell_y = block_y * block_stride_y + threadIdx.y / 2;
int hist_idx = histograms_step * cell_y + num_bins * (cell_x) + threadIdx.x;
int s_blocks_idx = 9 * threadIdx.y + threadIdx.x;
s_blocks[s_blocks_idx] = histograms[hist_idx];
__syncthreads();
int thread_id = 36 * threadIdx.z + 9 * threadIdx.y + threadIdx.x;
int elements_per_block = block_height * block_width * num_bins;
if(thread_id < 8)
{
L1_norm[thread_id] = 0.0f;
for(int i = 0; i < elements_per_block; ++i)
{
L1_norm[thread_id] += s_blocks[elements_per_block * thread_id + i];
}
}
__syncthreads();
descriptor[elements_per_block * block_idx + s_blocks_idx] =
s_blocks[s_blocks_idx] / L1_norm[threadIdx.z];
} | .text
.file "block_normalization_kernel.hip"
.globl _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii # -- Begin function _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.p2align 4, 0x90
.type _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii,@function
_Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii: # @_Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26block_normalization_kernelPfS_iiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii, .Lfunc_end0-_Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26block_normalization_kernelPfS_iiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26block_normalization_kernelPfS_iiiiiiiii,@object # @_Z26block_normalization_kernelPfS_iiiiiiiii
.section .rodata,"a",@progbits
.globl _Z26block_normalization_kernelPfS_iiiiiiiii
.p2align 3, 0x0
_Z26block_normalization_kernelPfS_iiiiiiiii:
.quad _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.size _Z26block_normalization_kernelPfS_iiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26block_normalization_kernelPfS_iiiiiiiii"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26block_normalization_kernelPfS_iiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26block_normalization_kernelPfS_iiiiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000e240000002300 */
/*0030*/ IMAD R2, R3, 0x8, R0 ; /* 0x0000000803027824 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e240000002600 */
/*0070*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x001fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*00d0*/ LOP3.LUT R3, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105037812 */
/* 0x001fe400078ec0ff */
/*00e0*/ SHF.R.U32.HI R4, RZ, 0x1, R5 ; /* 0x00000001ff047819 */
/* 0x000fc60000011605 */
/*00f0*/ IMAD R3, R2, c[0x0][0x18c], R3 ; /* 0x0000630002037a24 */
/* 0x000fe400078e0203 */
/*0100*/ IMAD R4, R7, c[0x0][0x190], R4 ; /* 0x0000640007047a24 */
/* 0x000fe400078e0204 */
/*0110*/ IMAD R3, R3, c[0x0][0x184], R6 ; /* 0x0000610003037a24 */
/* 0x002fc800078e0206 */
/*0120*/ IMAD R3, R4, c[0x0][0x170], R3 ; /* 0x00005c0004037a24 */
/* 0x000fc800078e0203 */
/*0130*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fcc00078e0208 */
/*0140*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD R3, R5, 0x9, R6 ; /* 0x0000000905037824 */
/* 0x000fe200078e0206 */
/*0160*/ BSSY B0, 0x8e0 ; /* 0x0000077000007945 */
/* 0x000fe20003800000 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD R5, R0, 0x24, R3 ; /* 0x0000002400057824 */
/* 0x000fe400078e0203 */
/*0190*/ IMAD R4, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006047a24 */
/* 0x000fe400078e02ff */
/*01a0*/ IMAD R2, R7, c[0x0][0x4], R2 ; /* 0x0000010007027a24 */
/* 0x000fe200078e0202 */
/*01b0*/ ISETP.GT.AND P0, PT, R5, 0x7, PT ; /* 0x000000070500780c */
/* 0x000fe20003f04270 */
/*01c0*/ IMAD R4, R4, c[0x0][0x184], RZ ; /* 0x0000610004047a24 */
/* 0x000fe200078e02ff */
/*01d0*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x0041e80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*01f0*/ @P0 BRA 0x8d0 ; /* 0x000006d000000947 */
/* 0x000fea0003800000 */
/*0200*/ STS [R5.X4+0x480], RZ ; /* 0x000480ff05007388 */
/* 0x0011e20000004800 */
/*0210*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0220*/ @!P0 BRA 0x8d0 ; /* 0x000006a000008947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R7, R4.reuse, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x041fe20007ffe0ff */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0250*/ LOP3.LUT R9, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304097812 */
/* 0x000fe200078ec0ff */
/*0260*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 BRA 0x800 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R7, R4, -R9, RZ ; /* 0x8000000904077210 */
/* 0x000fe20007ffe0ff */
/*02a0*/ IMAD R8, R6, c[0x0][0x184], RZ ; /* 0x0000610006087a24 */
/* 0x000fe200078e02ff */
/*02b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*02c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f04270 */
/*02e0*/ IMAD R8, R8, c[0x0][0x17c], RZ ; /* 0x00005f0008087a24 */
/* 0x000fc800078e02ff */
/*02f0*/ IMAD R8, R5, R8, RZ ; /* 0x0000000805087224 */
/* 0x000fca00078e02ff */
/*0300*/ LEA R8, R8, 0x8, 0x2 ; /* 0x0000000808087811 */
/* 0x000fc600078e10ff */
/*0310*/ @!P0 BRA 0x730 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fe40003f24270 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0340*/ @!P1 BRA 0x5b0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ LDS R15, [R8+-0x8] ; /* 0xfffff800080f7984 */
/* 0x000e220000000800 */
/*0370*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*0380*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0390*/ LDS R17, [R8+-0x4] ; /* 0xfffffc0008117984 */
/* 0x000e620000000800 */
/*03a0*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fc60003f24270 */
/*03b0*/ LDS R18, [R8] ; /* 0x0000000008127984 */
/* 0x000ea80000000800 */
/*03c0*/ LDS R19, [R8+0x4] ; /* 0x0000040008137984 */
/* 0x000ee80000000800 */
/*03d0*/ LDS R20, [R8+0x8] ; /* 0x0000080008147984 */
/* 0x000f280000000800 */
/*03e0*/ LDS R11, [R8+0xc] ; /* 0x00000c00080b7984 */
/* 0x000f680000000800 */
/*03f0*/ LDS R10, [R8+0x10] ; /* 0x00001000080a7984 */
/* 0x000f680000000800 */
/*0400*/ LDS R14, [R8+0x14] ; /* 0x00001400080e7984 */
/* 0x000f680000000800 */
/*0410*/ LDS R13, [R8+0x18] ; /* 0x00001800080d7984 */
/* 0x000f680000000800 */
/*0420*/ LDS R12, [R8+0x1c] ; /* 0x00001c00080c7984 */
/* 0x000f620000000800 */
/*0430*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x001fc60000000000 */
/*0440*/ LDS R21, [R8+0x34] ; /* 0x0000340008157984 */
/* 0x000fe20000000800 */
/*0450*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x002fc60000000000 */
/*0460*/ LDS R15, [R8+0x20] ; /* 0x00002000080f7984 */
/* 0x000e220000000800 */
/*0470*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x004fc60000000000 */
/*0480*/ LDS R16, [R8+0x24] ; /* 0x0000240008107984 */
/* 0x000e620000000800 */
/*0490*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x008fc60000000000 */
/*04a0*/ LDS R17, [R8+0x28] ; /* 0x0000280008117984 */
/* 0x000ea20000000800 */
/*04b0*/ FADD R20, R19, R20 ; /* 0x0000001413147221 */
/* 0x010fc60000000000 */
/*04c0*/ LDS R18, [R8+0x2c] ; /* 0x00002c0008127984 */
/* 0x000ee20000000800 */
/*04d0*/ FADD R11, R20, R11 ; /* 0x0000000b140b7221 */
/* 0x020fc60000000000 */
/*04e0*/ LDS R19, [R8+0x30] ; /* 0x0000300008137984 */
/* 0x0009620000000800 */
/*04f0*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x000fc80000000000 */
/*0500*/ FADD R14, R11, R14 ; /* 0x0000000e0b0e7221 */
/* 0x000fe20000000000 */
/*0510*/ IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x010fc60007ffe0ff */
/*0520*/ FADD R13, R14, R13 ; /* 0x0000000d0e0d7221 */
/* 0x000fc80000000000 */
/*0530*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x000fc80000000000 */
/*0540*/ FADD R15, R12, R15 ; /* 0x0000000f0c0f7221 */
/* 0x001fc80000000000 */
/*0550*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x002fc80000000000 */
/*0560*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x004fc80000000000 */
/*0570*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x008fc80000000000 */
/*0580*/ FADD R18, R18, R19 ; /* 0x0000001312127221 */
/* 0x020fc80000000000 */
/*0590*/ FADD R16, R18, R21 ; /* 0x0000001512107221 */
/* 0x000fe20000000000 */
/*05a0*/ @P1 BRA 0x360 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*05b0*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*05c0*/ @!P1 BRA 0x710 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*05d0*/ LDS R11, [R8+-0x8] ; /* 0xfffff800080b7984 */
/* 0x000e220000000800 */
/*05e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*05f0*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0600*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0610*/ LDS R10, [R8+-0x4] ; /* 0xfffffc00080a7984 */
/* 0x000e680000000800 */
/*0620*/ LDS R13, [R8] ; /* 0x00000000080d7984 */
/* 0x000ea80000000800 */
/*0630*/ LDS R15, [R8+0x4] ; /* 0x00000400080f7984 */
/* 0x000ee80000000800 */
/*0640*/ LDS R17, [R8+0x8] ; /* 0x0000080008117984 */
/* 0x000f280000000800 */
/*0650*/ LDS R19, [R8+0xc] ; /* 0x00000c0008137984 */
/* 0x000f680000000800 */
/*0660*/ LDS R21, [R8+0x10] ; /* 0x0000100008157984 */
/* 0x000f680000000800 */
/*0670*/ LDS R23, [R8+0x14] ; /* 0x0000140008177984 */
/* 0x0001640000000800 */
/*0680*/ IADD3 R8, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x001fe20007ffe0ff */
/*0690*/ FADD R11, R16, R11 ; /* 0x0000000b100b7221 */
/* 0x000fc80000000000 */
/*06a0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x002fc80000000000 */
/*06b0*/ FADD R10, R10, R13 ; /* 0x0000000d0a0a7221 */
/* 0x004fc80000000000 */
/*06c0*/ FADD R10, R10, R15 ; /* 0x0000000f0a0a7221 */
/* 0x008fc80000000000 */
/*06d0*/ FADD R10, R10, R17 ; /* 0x000000110a0a7221 */
/* 0x010fc80000000000 */
/*06e0*/ FADD R10, R10, R19 ; /* 0x000000130a0a7221 */
/* 0x020fc80000000000 */
/*06f0*/ FADD R10, R10, R21 ; /* 0x000000150a0a7221 */
/* 0x000fc80000000000 */
/*0700*/ FADD R16, R10, R23 ; /* 0x000000170a107221 */
/* 0x000fe40000000000 */
/*0710*/ ISETP.NE.OR P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705670 */
/*0720*/ @!P0 BRA 0x800 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0730*/ LDS R11, [R8+-0x8] ; /* 0xfffff800080b7984 */
/* 0x000e220000000800 */
/*0740*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0750*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0760*/ LDS R10, [R8+-0x4] ; /* 0xfffffc00080a7984 */
/* 0x000e620000000800 */
/*0770*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003f05270 */
/*0780*/ LDS R13, [R8] ; /* 0x00000000080d7984 */
/* 0x000ea80000000800 */
/*0790*/ LDS R15, [R8+0x4] ; /* 0x00000400080f7984 */
/* 0x0007240000000800 */
/*07a0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x008fe20007ffe0ff */
/*07b0*/ FADD R11, R11, R16 ; /* 0x000000100b0b7221 */
/* 0x001fc80000000000 */
/*07c0*/ FADD R10, R11, R10 ; /* 0x0000000a0b0a7221 */
/* 0x002fc80000000000 */
/*07d0*/ FADD R10, R10, R13 ; /* 0x0000000d0a0a7221 */
/* 0x004fc80000000000 */
/*07e0*/ FADD R16, R10, R15 ; /* 0x0000000f0a107221 */
/* 0x010fe20000000000 */
/*07f0*/ @P0 BRA 0x730 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0800*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0810*/ @!P0 BRA 0x8c0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD R6, R6, c[0x0][0x184], RZ ; /* 0x0000610006067a24 */
/* 0x000fc800078e02ff */
/*0830*/ IMAD R6, R6, c[0x0][0x17c], RZ ; /* 0x00005f0006067a24 */
/* 0x000fc800078e02ff */
/*0840*/ IMAD R6, R5, R6, UR4 ; /* 0x0000000405067e24 */
/* 0x000fc8000f8e0206 */
/*0850*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*0860*/ LDS R7, [R6] ; /* 0x0000000006077984 */
/* 0x0000620000000800 */
/*0870*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fc80007ffe0ff */
/*0880*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0890*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe20007ffe0ff */
/*08a0*/ FADD R16, R7, R16 ; /* 0x0000001007107221 */
/* 0x002fd40000000000 */
/*08b0*/ @P0 BRA 0x860 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*08c0*/ STS [R5.X4+0x480], R16 ; /* 0x0004801005007388 */
/* 0x0001e40000004800 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*08e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08f0*/ BSSY B0, 0x9e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0900*/ LDS R5, [R0.X4+0x480] ; /* 0x0004800000057984 */
/* 0x000e280000004800 */
/*0910*/ LDS R8, [R3.X4] ; /* 0x0000000003087984 */
/* 0x000e620000004800 */
/*0920*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e300000001000 */
/*0930*/ FCHK P0, R8, R5 ; /* 0x0000000508007302 */
/* 0x002e620000000000 */
/*0940*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0950*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc80000000006 */
/*0960*/ FFMA R6, R8, R7, RZ ; /* 0x0000000708067223 */
/* 0x000fc800000000ff */
/*0970*/ FFMA R9, -R5, R6, R8 ; /* 0x0000000605097223 */
/* 0x000fc80000000108 */
/*0980*/ FFMA R7, R7, R9, R6 ; /* 0x0000000907077223 */
/* 0x000fe20000000006 */
/*0990*/ @!P0 BRA 0x9d0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*09a0*/ MOV R0, 0x9c0 ; /* 0x000009c000007802 */
/* 0x000fe40000000f00 */
/*09b0*/ CALL.REL.NOINC 0xa30 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*09c0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0005 */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*09f0*/ IMAD R2, R2, R4, R3 ; /* 0x0000000402027224 */
/* 0x000fc800078e0203 */
/*0a00*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0205 */
/*0a10*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0a20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a30*/ SHF.R.U32.HI R7, RZ, 0x17, R5.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011605 */
/*0a40*/ BSSY B1, 0x1090 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0a50*/ SHF.R.U32.HI R6, RZ, 0x17, R8 ; /* 0x00000017ff067819 */
/* 0x000fe20000011608 */
/*0a60*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0a70*/ LOP3.LUT R9, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07097812 */
/* 0x000fe400078ec0ff */
/*0a80*/ LOP3.LUT R7, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06077812 */
/* 0x000fe400078ec0ff */
/*0a90*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fe40007ffe0ff */
/*0aa0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*0ab0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fe40003f04070 */
/*0ac0*/ MOV R10, R8 ; /* 0x00000008000a7202 */
/* 0x000fe40000000f00 */
/*0ad0*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0ae0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0af0*/ @!P0 BRA 0xc70 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0b00*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0b10*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0b20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0b30*/ @P0 BRA 0x1070 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, R10, 0xc8, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c80a */
/*0b50*/ @!P0 BRA 0x1050 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b60*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*0b70*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0b80*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0b90*/ @!P1 BRA !P2, 0x1050 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0ba0*/ LOP3.LUT P2, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000784c0ff */
/*0bb0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0bc0*/ @P1 BRA 0x1030 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0bd0*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*0be0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0bf0*/ @P0 BRA 0x1000 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0c10*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0c20*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0c30*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0c40*/ @!P0 FFMA R10, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f800000080a8823 */
/* 0x000fe400000000ff */
/*0c50*/ @!P1 FFMA R11, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f800000050b9823 */
/* 0x000fe200000000ff */
/*0c60*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0c70*/ LEA R8, R9, 0xc0800000, 0x17 ; /* 0xc080000009087811 */
/* 0x000fe200078eb8ff */
/*0c80*/ BSSY B2, 0xff0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0c90*/ IADD3 R7, R7, -0x7f, RZ ; /* 0xffffff8107077810 */
/* 0x000fe40007ffe0ff */
/*0ca0*/ IADD3 R8, -R8, R11, RZ ; /* 0x0000000b08087210 */
/* 0x000fc40007ffe1ff */
/*0cb0*/ IADD3 R9, R7.reuse, 0x7f, -R9 ; /* 0x0000007f07097810 */
/* 0x040fe20007ffe809 */
/*0cc0*/ IMAD R10, R7, -0x800000, R10 ; /* 0xff800000070a7824 */
/* 0x000fe200078e020a */
/*0cd0*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e220000001000 */
/*0ce0*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*0cf0*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fe400078e0206 */
/*0d00*/ FFMA R12, R5, R11, 1 ; /* 0x3f800000050c7423 */
/* 0x001fc8000000000b */
/*0d10*/ FFMA R13, R5, R12, R5 ; /* 0x0000000c050d7223 */
/* 0x000fc80000000005 */
/*0d20*/ FFMA R5, R10, R13, RZ ; /* 0x0000000d0a057223 */
/* 0x000fc800000000ff */
/*0d30*/ FFMA R12, R11, R5, R10 ; /* 0x000000050b0c7223 */
/* 0x000fc8000000000a */
/*0d40*/ FFMA R12, R13, R12, R5 ; /* 0x0000000c0d0c7223 */
/* 0x000fc80000000005 */
/*0d50*/ FFMA R10, R11, R12, R10 ; /* 0x0000000c0b0a7223 */
/* 0x000fc8000000000a */
/*0d60*/ FFMA R5, R13, R10, R12 ; /* 0x0000000a0d057223 */
/* 0x000fca000000000c */
/*0d70*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*0d80*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0d90*/ IMAD.IADD R11, R7, 0x1, R6 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0206 */
/*0da0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0dc0*/ @!P0 BRA 0xfd0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0dd0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0de0*/ @P0 BRA 0xfa0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0df0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0e00*/ @P0 BRA 0xfe0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0e10*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0e20*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0e30*/ @!P0 BRA 0xfe0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e40*/ FFMA.RZ R6, R13, R10.reuse, R12.reuse ; /* 0x0000000a0d067223 */
/* 0x180fe2000000c00c */
/*0e50*/ IADD3 R9, R11, 0x20, RZ ; /* 0x000000200b097810 */
/* 0x000fe20007ffe0ff */
/*0e60*/ FFMA.RM R7, R13, R10.reuse, R12.reuse ; /* 0x0000000a0d077223 */
/* 0x180fe2000000400c */
/*0e70*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0e80*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0e90*/ FFMA.RP R6, R13, R10, R12 ; /* 0x0000000a0d067223 */
/* 0x000fe2000000800c */
/*0ea0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0eb0*/ IMAD.MOV R10, RZ, RZ, -R11 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0b */
/*0ec0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0ed0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*0ee0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0ef0*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0f00*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0f10*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0f20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0f30*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0f40*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0f50*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0f60*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0f70*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0f80*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0f90*/ BRA 0xfe0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0fa0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*0fb0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0fc0*/ BRA 0xfe0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fd0*/ LEA R5, R6, R5, 0x17 ; /* 0x0000000506057211 */
/* 0x000fe400078eb8ff */
/*0fe0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ff0*/ BRA 0x1080 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R5, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b057812 */
/* 0x000fc800078e480a */
/*1010*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*1020*/ BRA 0x1080 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R5, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b057812 */
/* 0x000fe200078e480a */
/*1040*/ BRA 0x1080 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1050*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*1060*/ BRA 0x1080 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1070*/ FADD.FTZ R5, R8, R5 ; /* 0x0000000508057221 */
/* 0x000fe40000010000 */
/*1080*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1090*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*10a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*10b0*/ RET.REL.NODEC R6 0x0 ; /* 0xffffef4006007950 */
/* 0x000fea0003c3ffff */
/*10c0*/ BRA 0x10c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26block_normalization_kernelPfS_iiiiiiiii
.globl _Z26block_normalization_kernelPfS_iiiiiiiii
.p2align 8
.type _Z26block_normalization_kernelPfS_iiiiiiiii,@function
_Z26block_normalization_kernelPfS_iiiiiiiii:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v2, v0, 20, 10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s14, 3, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB0_8
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x24
v_bfe_u32 v8, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b32 s7, s[0:1], 0x44
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 1, v8
v_and_b32_e32 v4, 1, v8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v1, s2, v[4:5]
s_load_b64 s[2:3], s[0:1], 0x1c
v_mul_lo_u32 v3, v5, s4
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v4, v6, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v3, v4, v0, v3
v_mad_u32_u24 v0, v8, 9, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mul_i32 s4, s3, s2
s_lshr_b32 s5, s7, 16
s_mul_i32 s4, s4, s6
global_load_b32 v5, v[3:4], off
v_mad_u32_u24 v4, v2, 36, v0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 8, v4
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v5, 2, v4
s_cmp_lt_i32 s4, 1
ds_store_b32 v5, v6 offset:1152
s_cbranch_scc1 .LBB0_7
v_add_nc_u32_e32 v5, 0x480, v5
s_mul_i32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s3, s3, s2
s_mov_b32 s2, s4
ds_load_b32 v6, v5
v_mul_lo_u32 v4, s3, v4
v_lshlrev_b32_e32 v4, 2, v4
.LBB0_5:
ds_load_b32 v7, v4
v_add_nc_u32_e32 v4, 4, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v7, v6
s_cbranch_scc1 .LBB0_5
ds_store_b32 v5, v6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v3
ds_load_b32 v6, v2 offset:1152
s_and_b32 s2, 0xffff, s5
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v7, null, v6, v6, v5
v_div_scale_f32 v9, vcc_lo, v5, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v7, v8, 1.0
v_fmac_f32_e32 v8, v2, v8
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v9, v8
v_fma_f32 v10, -v7, v1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
v_fmac_f32_e32 v1, v10, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_fma_f32 v0, -v7, v1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v2, v0, v8, v1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v2, v6, v5
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26block_normalization_kernelPfS_iiiiiiiii
.amdhsa_group_segment_fixed_size 1184
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26block_normalization_kernelPfS_iiiiiiiii, .Lfunc_end0-_Z26block_normalization_kernelPfS_iiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1184
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26block_normalization_kernelPfS_iiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26block_normalization_kernelPfS_iiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016fb48_00000000-6_block_normalization_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii
.type _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii, @function
_Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 216
pushq 40(%rsp)
.cfi_def_cfa_offset 224
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26block_normalization_kernelPfS_iiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii, .-_Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii
.globl _Z26block_normalization_kernelPfS_iiiiiiiii
.type _Z26block_normalization_kernelPfS_iiiiiiiii, @function
_Z26block_normalization_kernelPfS_iiiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z57__device_stub__Z26block_normalization_kernelPfS_iiiiiiiiiPfS_iiiiiiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26block_normalization_kernelPfS_iiiiiiiii, .-_Z26block_normalization_kernelPfS_iiiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26block_normalization_kernelPfS_iiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26block_normalization_kernelPfS_iiiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "block_normalization_kernel.hip"
.globl _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii # -- Begin function _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.p2align 4, 0x90
.type _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii,@function
_Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii: # @_Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26block_normalization_kernelPfS_iiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii, .Lfunc_end0-_Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26block_normalization_kernelPfS_iiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26block_normalization_kernelPfS_iiiiiiiii,@object # @_Z26block_normalization_kernelPfS_iiiiiiiii
.section .rodata,"a",@progbits
.globl _Z26block_normalization_kernelPfS_iiiiiiiii
.p2align 3, 0x0
_Z26block_normalization_kernelPfS_iiiiiiiii:
.quad _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.size _Z26block_normalization_kernelPfS_iiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26block_normalization_kernelPfS_iiiiiiiii"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__block_normalization_kernelPfS_iiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26block_normalization_kernelPfS_iiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
const int N = 600;
const int D = 2;
const int blocksize = 4;
const int gridsize = 4;
struct timeval startwtime, endwtime;
double seq_time;
double **alloc_2d_init(int rows, int cols);
double **init();
__shared__ double a_shared[600*2];
__shared__ double b_shared[600*2];
__shared__ double c_shared[600*2];
__device__
void findNext(int index){
double numinator;
double denuminator;
double distance;
double sigma = 1.0;
double c1;
int j,k,d;
for(j=0; j<D; j++){
numinator = 0.0;
denuminator = 0.0;
for(k=0; k<N; k++){
distance = 0.0;
for(d=0; d<D; d++){
distance += (b_shared[index*D+d]-a_shared[k*D+d])*(b_shared[index*D+d]-a_shared[k*D+d]);
}
if(distance<sigma*sigma){
c1 = exp(-distance/(2*sigma*sigma));
denuminator += c1;
numinator += c1*a_shared[k*D+j];
}
}
c_shared[index*D+j] = numinator/denuminator;
}
}
__global__
void meanshiftShared(double *a, double *b, double *c){
int index = blockIdx.x*blockDim.x + threadIdx.x;
int i,j;
memcpy(a_shared,a,N*D);
memcpy(b_shared,b,N*D);
double abs_m;
double epsilon = 0.0001;
for(i=index*N/(blockDim.x*blockDim.x); i<(index+1)*N/(blockDim.x*blockDim.x); i++){
abs_m = 1.0;
while(abs_m > epsilon){
findNext(i);
abs_m = 0.0;
for(j=0; j<D; j++){
abs_m += (c_shared[i*D+j]-b_shared[i*D+j])*(c_shared[i*D+j]-b_shared[i*D+j]);
b_shared[i*D+j] = c_shared[i*D+j];
}
}
}
memcpy(c,c_shared,N*D);
}
int main(){
double **points;
double **new_points;
double *lin_points, *lin_prev, *lin_next;
lin_points = (double *)malloc(N*D*sizeof(double));
lin_prev = (double *)malloc(N*D*sizeof(double));
lin_next = (double *)malloc(N*D*sizeof(double));
new_points = alloc_2d_init(N,D);
points = init();
int i,j,index;
for(i=0; i<N; i++){
for(j=0; j<D; j++){
index = j+i*D;
lin_points[index] = points[i][j];
lin_prev[index] = points[i][j];
}
}
double *ad, *bd, *cd;
const int size = N*D*sizeof(double);
cudaMalloc((void **)&ad,size);
cudaMalloc((void **)&bd,size);
cudaMalloc((void **)&cd,size);
cudaMemcpy(ad,lin_points,size,cudaMemcpyHostToDevice);
cudaMemcpy(bd,lin_prev,size,cudaMemcpyHostToDevice);
dim3 dimBlock(blocksize);
dim3 dimGrid(gridsize);
gettimeofday (&startwtime, NULL);
meanshiftShared<<<dimGrid,dimBlock>>>(ad,bd,cd);
cudaDeviceSynchronize();
gettimeofday (&endwtime, NULL);
seq_time = (double)((endwtime.tv_usec - startwtime.tv_usec)/1.0e6
+ endwtime.tv_sec - startwtime.tv_sec);
printf("Meanshift Shared wall clock time = %f\n\n", seq_time);
cudaMemcpy(lin_next,cd,size,cudaMemcpyDeviceToHost);
for(i=0; i<N; i++){
for(j=0; j<D; j++){
new_points[i][j] = lin_next[j+i*D];
}
}
cudaFree(ad);
cudaFree(bd);
cudaFree(cd);
return EXIT_SUCCESS;
}
double **init(){
FILE *fp;
double *buffer;
double **ret_buf;
int size,number_of_elements;
int i,j,counter;
fp = fopen("data.bin","rb");
fseek(fp, 0, SEEK_END);
size = ftell(fp); //total size in bytes
number_of_elements = size/8; //total number of elements
buffer = (double *)malloc(number_of_elements*sizeof(double));
ret_buf = alloc_2d_init(N,D);
fseek(fp, 0, SEEK_SET);
fread(buffer,sizeof(buffer),number_of_elements,fp);
fclose(fp);
counter = 0;
for(j=0; j<D; j++){
for(i=0; i<N; i++){
ret_buf[i][j] = buffer[counter];
counter++;
}
}
return ret_buf;
}
double **alloc_2d_init(int rows, int cols){
double *data = (double *)malloc(rows*cols*sizeof(double));
double **array= (double **)malloc(rows*sizeof(double*));
int i;
for (i=0; i<rows; i++)
array[i] = &(data[cols*i]);
return array;
} | .file "tmpxft_0005a979_00000000-6_cuda_meanshift_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8findNexti
.type _Z8findNexti, @function
_Z8findNexti:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8findNexti, .-_Z8findNexti
.globl _Z13alloc_2d_initii
.type _Z13alloc_2d_initii, @function
_Z13alloc_2d_initii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r13d
movl %esi, %ebp
imull %esi, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rbx
movslq %r13d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
testl %r13d, %r13d
jle .L5
movslq %ebp, %rsi
salq $3, %rsi
movq %rbx, %rcx
movq %rax, %rdx
addq %rax, %r12
.L7:
movq %rcx, (%rdx)
addq %rsi, %rcx
addq $8, %rdx
cmpq %r12, %rdx
jne .L7
.L5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z13alloc_2d_initii, .-_Z13alloc_2d_initii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "data.bin"
.text
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %r13, %rdi
call ftell@PLT
leal 7(%rax), %r12d
testl %eax, %eax
cmovns %eax, %r12d
sarl $3, %r12d
movslq %r12d, %r12
leaq 0(,%r12,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %esi
movl $600, %edi
call _Z13alloc_2d_initii
movq %rax, %rbx
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
movq %r13, %r8
movq %r12, %rcx
movl $8, %edx
movq %r14, %rsi
movq %rbp, %rdi
call __fread_chk@PLT
movq %r13, %rdi
call fclose@PLT
movl $0, %eax
.L11:
movq (%rbx,%rax), %rdx
movsd 0(%rbp,%rax), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $4800, %rax
jne .L11
movl $0, %eax
.L12:
movq (%rbx,%rax), %rdx
movsd 4800(%rbp,%rax), %xmm0
movsd %xmm0, 8(%rdx)
addq $8, %rax
cmpq $4800, %rax
jne .L12
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z4initv, .-_Z4initv
.globl _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
.type _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_, @function
_Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15meanshiftSharedPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_, .-_Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
.globl _Z15meanshiftSharedPdS_S_
.type _Z15meanshiftSharedPdS_S_, @function
_Z15meanshiftSharedPdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15meanshiftSharedPdS_S_, .-_Z15meanshiftSharedPdS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Meanshift Shared wall clock time = %f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $9600, %edi
call malloc@PLT
movq %rax, %r12
movl $9600, %edi
call malloc@PLT
movq %rax, %rbp
movl $9600, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %esi
movl $600, %edi
call _Z13alloc_2d_initii
movq %rax, %rbx
call _Z4initv
movl $0, %edx
.L25:
movq (%rax), %rcx
movsd (%rcx), %xmm0
movsd %xmm0, (%r12,%rdx)
movq (%rax), %rcx
movsd (%rcx), %xmm0
movsd %xmm0, 0(%rbp,%rdx)
movq (%rax), %rcx
movsd 8(%rcx), %xmm0
movsd %xmm0, 8(%r12,%rdx)
movq (%rax), %rcx
movsd 8(%rcx), %xmm0
movsd %xmm0, 8(%rbp,%rdx)
addq $8, %rax
addq $16, %rdx
cmpq $9600, %rdx
jne .L25
leaq 8(%rsp), %rdi
movl $9600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $9600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $9600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $9600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $9600, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
leaq startwtime(%rip), %rdi
call gettimeofday@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
call cudaDeviceSynchronize@PLT
movl $0, %esi
leaq endwtime(%rip), %rdi
call gettimeofday@PLT
movq 8+endwtime(%rip), %rax
subq 8+startwtime(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq endwtime(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq startwtime(%rip), %xmm1
subsd %xmm1, %xmm0
movsd %xmm0, seq_time(%rip)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $9600, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rax
addq $9600, %r13
.L27:
movq (%rbx), %rdx
movsd (%rax), %xmm0
movsd %xmm0, (%rdx)
movq (%rbx), %rdx
movsd 8(%rax), %xmm0
movsd %xmm0, 8(%rdx)
addq $8, %rbx
addq $16, %rax
cmpq %r13, %rax
jne .L27
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
jmp .L26
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z15meanshiftSharedPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15meanshiftSharedPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl seq_time
.bss
.align 8
.type seq_time, @object
.size seq_time, 8
seq_time:
.zero 8
.globl endwtime
.align 16
.type endwtime, @object
.size endwtime, 16
endwtime:
.zero 16
.globl startwtime
.align 16
.type startwtime, @object
.size startwtime, 16
startwtime:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
const int N = 600;
const int D = 2;
const int blocksize = 4;
const int gridsize = 4;
struct timeval startwtime, endwtime;
double seq_time;
double **alloc_2d_init(int rows, int cols);
double **init();
__shared__ double a_shared[600*2];
__shared__ double b_shared[600*2];
__shared__ double c_shared[600*2];
__device__
void findNext(int index){
double numinator;
double denuminator;
double distance;
double sigma = 1.0;
double c1;
int j,k,d;
for(j=0; j<D; j++){
numinator = 0.0;
denuminator = 0.0;
for(k=0; k<N; k++){
distance = 0.0;
for(d=0; d<D; d++){
distance += (b_shared[index*D+d]-a_shared[k*D+d])*(b_shared[index*D+d]-a_shared[k*D+d]);
}
if(distance<sigma*sigma){
c1 = exp(-distance/(2*sigma*sigma));
denuminator += c1;
numinator += c1*a_shared[k*D+j];
}
}
c_shared[index*D+j] = numinator/denuminator;
}
}
__global__
void meanshiftShared(double *a, double *b, double *c){
int index = blockIdx.x*blockDim.x + threadIdx.x;
int i,j;
memcpy(a_shared,a,N*D);
memcpy(b_shared,b,N*D);
double abs_m;
double epsilon = 0.0001;
for(i=index*N/(blockDim.x*blockDim.x); i<(index+1)*N/(blockDim.x*blockDim.x); i++){
abs_m = 1.0;
while(abs_m > epsilon){
findNext(i);
abs_m = 0.0;
for(j=0; j<D; j++){
abs_m += (c_shared[i*D+j]-b_shared[i*D+j])*(c_shared[i*D+j]-b_shared[i*D+j]);
b_shared[i*D+j] = c_shared[i*D+j];
}
}
}
memcpy(c,c_shared,N*D);
}
int main(){
double **points;
double **new_points;
double *lin_points, *lin_prev, *lin_next;
lin_points = (double *)malloc(N*D*sizeof(double));
lin_prev = (double *)malloc(N*D*sizeof(double));
lin_next = (double *)malloc(N*D*sizeof(double));
new_points = alloc_2d_init(N,D);
points = init();
int i,j,index;
for(i=0; i<N; i++){
for(j=0; j<D; j++){
index = j+i*D;
lin_points[index] = points[i][j];
lin_prev[index] = points[i][j];
}
}
double *ad, *bd, *cd;
const int size = N*D*sizeof(double);
cudaMalloc((void **)&ad,size);
cudaMalloc((void **)&bd,size);
cudaMalloc((void **)&cd,size);
cudaMemcpy(ad,lin_points,size,cudaMemcpyHostToDevice);
cudaMemcpy(bd,lin_prev,size,cudaMemcpyHostToDevice);
dim3 dimBlock(blocksize);
dim3 dimGrid(gridsize);
gettimeofday (&startwtime, NULL);
meanshiftShared<<<dimGrid,dimBlock>>>(ad,bd,cd);
cudaDeviceSynchronize();
gettimeofday (&endwtime, NULL);
seq_time = (double)((endwtime.tv_usec - startwtime.tv_usec)/1.0e6
+ endwtime.tv_sec - startwtime.tv_sec);
printf("Meanshift Shared wall clock time = %f\n\n", seq_time);
cudaMemcpy(lin_next,cd,size,cudaMemcpyDeviceToHost);
for(i=0; i<N; i++){
for(j=0; j<D; j++){
new_points[i][j] = lin_next[j+i*D];
}
}
cudaFree(ad);
cudaFree(bd);
cudaFree(cd);
return EXIT_SUCCESS;
}
double **init(){
FILE *fp;
double *buffer;
double **ret_buf;
int size,number_of_elements;
int i,j,counter;
fp = fopen("data.bin","rb");
fseek(fp, 0, SEEK_END);
size = ftell(fp); //total size in bytes
number_of_elements = size/8; //total number of elements
buffer = (double *)malloc(number_of_elements*sizeof(double));
ret_buf = alloc_2d_init(N,D);
fseek(fp, 0, SEEK_SET);
fread(buffer,sizeof(buffer),number_of_elements,fp);
fclose(fp);
counter = 0;
for(j=0; j<D; j++){
for(i=0; i<N; i++){
ret_buf[i][j] = buffer[counter];
counter++;
}
}
return ret_buf;
}
double **alloc_2d_init(int rows, int cols){
double *data = (double *)malloc(rows*cols*sizeof(double));
double **array= (double **)malloc(rows*sizeof(double*));
int i;
for (i=0; i<rows; i++)
array[i] = &(data[cols*i]);
return array;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
const int N = 600;
const int D = 2;
const int blocksize = 4;
const int gridsize = 4;
struct timeval startwtime, endwtime;
double seq_time;
double **alloc_2d_init(int rows, int cols);
double **init();
__shared__ double a_shared[600*2];
__shared__ double b_shared[600*2];
__shared__ double c_shared[600*2];
__device__
void findNext(int index){
double numinator;
double denuminator;
double distance;
double sigma = 1.0;
double c1;
int j,k,d;
for(j=0; j<D; j++){
numinator = 0.0;
denuminator = 0.0;
for(k=0; k<N; k++){
distance = 0.0;
for(d=0; d<D; d++){
distance += (b_shared[index*D+d]-a_shared[k*D+d])*(b_shared[index*D+d]-a_shared[k*D+d]);
}
if(distance<sigma*sigma){
c1 = exp(-distance/(2*sigma*sigma));
denuminator += c1;
numinator += c1*a_shared[k*D+j];
}
}
c_shared[index*D+j] = numinator/denuminator;
}
}
__global__
void meanshiftShared(double *a, double *b, double *c){
int index = blockIdx.x*blockDim.x + threadIdx.x;
int i,j;
memcpy(a_shared,a,N*D);
memcpy(b_shared,b,N*D);
double abs_m;
double epsilon = 0.0001;
for(i=index*N/(blockDim.x*blockDim.x); i<(index+1)*N/(blockDim.x*blockDim.x); i++){
abs_m = 1.0;
while(abs_m > epsilon){
findNext(i);
abs_m = 0.0;
for(j=0; j<D; j++){
abs_m += (c_shared[i*D+j]-b_shared[i*D+j])*(c_shared[i*D+j]-b_shared[i*D+j]);
b_shared[i*D+j] = c_shared[i*D+j];
}
}
}
memcpy(c,c_shared,N*D);
}
int main(){
double **points;
double **new_points;
double *lin_points, *lin_prev, *lin_next;
lin_points = (double *)malloc(N*D*sizeof(double));
lin_prev = (double *)malloc(N*D*sizeof(double));
lin_next = (double *)malloc(N*D*sizeof(double));
new_points = alloc_2d_init(N,D);
points = init();
int i,j,index;
for(i=0; i<N; i++){
for(j=0; j<D; j++){
index = j+i*D;
lin_points[index] = points[i][j];
lin_prev[index] = points[i][j];
}
}
double *ad, *bd, *cd;
const int size = N*D*sizeof(double);
hipMalloc((void **)&ad,size);
hipMalloc((void **)&bd,size);
hipMalloc((void **)&cd,size);
hipMemcpy(ad,lin_points,size,hipMemcpyHostToDevice);
hipMemcpy(bd,lin_prev,size,hipMemcpyHostToDevice);
dim3 dimBlock(blocksize);
dim3 dimGrid(gridsize);
gettimeofday (&startwtime, NULL);
meanshiftShared<<<dimGrid,dimBlock>>>(ad,bd,cd);
hipDeviceSynchronize();
gettimeofday (&endwtime, NULL);
seq_time = (double)((endwtime.tv_usec - startwtime.tv_usec)/1.0e6
+ endwtime.tv_sec - startwtime.tv_sec);
printf("Meanshift Shared wall clock time = %f\n\n", seq_time);
hipMemcpy(lin_next,cd,size,hipMemcpyDeviceToHost);
for(i=0; i<N; i++){
for(j=0; j<D; j++){
new_points[i][j] = lin_next[j+i*D];
}
}
hipFree(ad);
hipFree(bd);
hipFree(cd);
return EXIT_SUCCESS;
}
double **init(){
FILE *fp;
double *buffer;
double **ret_buf;
int size,number_of_elements;
int i,j,counter;
fp = fopen("data.bin","rb");
fseek(fp, 0, SEEK_END);
size = ftell(fp); //total size in bytes
number_of_elements = size/8; //total number of elements
buffer = (double *)malloc(number_of_elements*sizeof(double));
ret_buf = alloc_2d_init(N,D);
fseek(fp, 0, SEEK_SET);
fread(buffer,sizeof(buffer),number_of_elements,fp);
fclose(fp);
counter = 0;
for(j=0; j<D; j++){
for(i=0; i<N; i++){
ret_buf[i][j] = buffer[counter];
counter++;
}
}
return ret_buf;
}
double **alloc_2d_init(int rows, int cols){
double *data = (double *)malloc(rows*cols*sizeof(double));
double **array= (double **)malloc(rows*sizeof(double*));
int i;
for (i=0; i<rows; i++)
array[i] = &(data[cols*i]);
return array;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
const int N = 600;
const int D = 2;
const int blocksize = 4;
const int gridsize = 4;
struct timeval startwtime, endwtime;
double seq_time;
double **alloc_2d_init(int rows, int cols);
double **init();
__shared__ double a_shared[600*2];
__shared__ double b_shared[600*2];
__shared__ double c_shared[600*2];
__device__
void findNext(int index){
double numinator;
double denuminator;
double distance;
double sigma = 1.0;
double c1;
int j,k,d;
for(j=0; j<D; j++){
numinator = 0.0;
denuminator = 0.0;
for(k=0; k<N; k++){
distance = 0.0;
for(d=0; d<D; d++){
distance += (b_shared[index*D+d]-a_shared[k*D+d])*(b_shared[index*D+d]-a_shared[k*D+d]);
}
if(distance<sigma*sigma){
c1 = exp(-distance/(2*sigma*sigma));
denuminator += c1;
numinator += c1*a_shared[k*D+j];
}
}
c_shared[index*D+j] = numinator/denuminator;
}
}
__global__
void meanshiftShared(double *a, double *b, double *c){
int index = blockIdx.x*blockDim.x + threadIdx.x;
int i,j;
memcpy(a_shared,a,N*D);
memcpy(b_shared,b,N*D);
double abs_m;
double epsilon = 0.0001;
for(i=index*N/(blockDim.x*blockDim.x); i<(index+1)*N/(blockDim.x*blockDim.x); i++){
abs_m = 1.0;
while(abs_m > epsilon){
findNext(i);
abs_m = 0.0;
for(j=0; j<D; j++){
abs_m += (c_shared[i*D+j]-b_shared[i*D+j])*(c_shared[i*D+j]-b_shared[i*D+j]);
b_shared[i*D+j] = c_shared[i*D+j];
}
}
}
memcpy(c,c_shared,N*D);
}
int main(){
double **points;
double **new_points;
double *lin_points, *lin_prev, *lin_next;
lin_points = (double *)malloc(N*D*sizeof(double));
lin_prev = (double *)malloc(N*D*sizeof(double));
lin_next = (double *)malloc(N*D*sizeof(double));
new_points = alloc_2d_init(N,D);
points = init();
int i,j,index;
for(i=0; i<N; i++){
for(j=0; j<D; j++){
index = j+i*D;
lin_points[index] = points[i][j];
lin_prev[index] = points[i][j];
}
}
double *ad, *bd, *cd;
const int size = N*D*sizeof(double);
hipMalloc((void **)&ad,size);
hipMalloc((void **)&bd,size);
hipMalloc((void **)&cd,size);
hipMemcpy(ad,lin_points,size,hipMemcpyHostToDevice);
hipMemcpy(bd,lin_prev,size,hipMemcpyHostToDevice);
dim3 dimBlock(blocksize);
dim3 dimGrid(gridsize);
gettimeofday (&startwtime, NULL);
meanshiftShared<<<dimGrid,dimBlock>>>(ad,bd,cd);
hipDeviceSynchronize();
gettimeofday (&endwtime, NULL);
seq_time = (double)((endwtime.tv_usec - startwtime.tv_usec)/1.0e6
+ endwtime.tv_sec - startwtime.tv_sec);
printf("Meanshift Shared wall clock time = %f\n\n", seq_time);
hipMemcpy(lin_next,cd,size,hipMemcpyDeviceToHost);
for(i=0; i<N; i++){
for(j=0; j<D; j++){
new_points[i][j] = lin_next[j+i*D];
}
}
hipFree(ad);
hipFree(bd);
hipFree(cd);
return EXIT_SUCCESS;
}
double **init(){
FILE *fp;
double *buffer;
double **ret_buf;
int size,number_of_elements;
int i,j,counter;
fp = fopen("data.bin","rb");
fseek(fp, 0, SEEK_END);
size = ftell(fp); //total size in bytes
number_of_elements = size/8; //total number of elements
buffer = (double *)malloc(number_of_elements*sizeof(double));
ret_buf = alloc_2d_init(N,D);
fseek(fp, 0, SEEK_SET);
fread(buffer,sizeof(buffer),number_of_elements,fp);
fclose(fp);
counter = 0;
for(j=0; j<D; j++){
for(i=0; i<N; i++){
ret_buf[i][j] = buffer[counter];
counter++;
}
}
return ret_buf;
}
double **alloc_2d_init(int rows, int cols){
double *data = (double *)malloc(rows*cols*sizeof(double));
double **array= (double **)malloc(rows*sizeof(double*));
int i;
for (i=0; i<rows; i++)
array[i] = &(data[cols*i]);
return array;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15meanshiftSharedPdS_S_
.globl _Z15meanshiftSharedPdS_S_
.p2align 8
.type _Z15meanshiftSharedPdS_S_,@function
_Z15meanshiftSharedPdS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x24
v_mov_b32_e32 v1, 0
s_mov_b32 s7, 0
s_mov_b64 s[4:5], 0
.p2align 6
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
v_mov_b32_e32 v6, s7
s_clause 0x3
global_load_u8 v2, v1, s[8:9]
global_load_u8 v3, v1, s[8:9] offset:1
global_load_u8 v4, v1, s[8:9] offset:2
global_load_u8 v5, v1, s[8:9] offset:3
s_add_i32 s7, s7, 4
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(3)
ds_store_b8 v6, v2
s_waitcnt vmcnt(2)
ds_store_b8 v6, v3 offset:1
s_waitcnt vmcnt(1)
ds_store_b8 v6, v4 offset:2
s_waitcnt vmcnt(0)
ds_store_b8 v6, v5 offset:3
s_cmp_lg_u64 s[4:5], 0x4b0
s_cbranch_scc1 .LBB0_1
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v1, 0
s_movk_i32 s7, 0x2580
s_mov_b64 s[4:5], 0
.p2align 6
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
v_mov_b32_e32 v6, s7
s_clause 0x3
global_load_u8 v2, v1, s[8:9]
global_load_u8 v3, v1, s[8:9] offset:1
global_load_u8 v4, v1, s[8:9] offset:2
global_load_u8 v5, v1, s[8:9] offset:3
s_add_i32 s7, s7, 4
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt vmcnt(3)
ds_store_b8 v6, v2
s_waitcnt vmcnt(2)
ds_store_b8 v6, v3 offset:1
s_waitcnt vmcnt(1)
ds_store_b8 v6, v4 offset:2
s_waitcnt vmcnt(0)
ds_store_b8 v6, v5 offset:3
s_cmp_lg_u64 s[4:5], 0x4b0
s_cbranch_scc1 .LBB0_3
s_and_b32 s2, 0xffff, s6
s_mov_b32 s33, 0
s_mul_i32 s3, s2, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mul_lo_u32 v4, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v1, 0x258
v_mul_hi_u32 v0, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v3, v1, v0
v_add_nc_u32_e32 v2, 0x258, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v3, s3
v_sub_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_mul_hi_u32 v0, v2, v0
v_subrev_nc_u32_e32 v4, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_add_nc_u32 v4, 1, v3
v_mul_lo_u32 v5, v0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_sub_nc_u32_e32 v2, v2, v5
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e64 s2, s3, v2
v_cndmask_b32_e64 v0, v0, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v6, s2
v_cndmask_b32_e32 v6, v3, v4, vcc_lo
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_mov_b32 s3, exec_lo
v_cndmask_b32_e32 v7, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e64 v6, v7
s_cbranch_execz .LBB0_19
v_lshl_add_u32 v8, v6, 4, 0x2580
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_mov_b32 s7, 0xbfe62e42
s_mov_b32 s6, 0xfefa39ef
s_mov_b32 s9, 0xbc7abc9e
s_mov_b32 s8, 0x3b39803f
s_mov_b32 s11, 0x3e928af3
s_mov_b32 s10, 0xfca7ab0c
s_mov_b32 s13, 0x3e5ade15
s_mov_b32 s12, 0x6a5dcb37
s_mov_b32 s15, 0x3ec71dee
s_mov_b32 s14, 0x623fde64
s_mov_b32 s17, 0x3efa0199
s_mov_b32 s16, 0x7c89e6b0
s_mov_b32 s19, 0x3f2a01a0
s_mov_b32 s18, 0x14761f6e
s_mov_b32 s21, 0x3f56c16c
s_mov_b32 s20, 0x1852b7b0
s_mov_b32 s23, 0x3f811111
s_mov_b32 s22, 0x11122322
s_mov_b32 s25, 0x3fa55555
s_mov_b32 s24, 0x555502a1
s_mov_b32 s27, 0x3fc55555
s_mov_b32 s26, 0x55555511
s_mov_b32 s29, 0x3fe00000
s_mov_b32 s28, 11
s_mov_b32 s31, 0x3f1a36e2
s_mov_b32 s30, 0xeb1c432d
.LBB0_6:
v_lshlrev_b32_e32 v9, 1, v6
s_mov_b32 s34, 0
s_mov_b32 s35, 0
s_branch .LBB0_8
.LBB0_7:
s_mov_b32 s35, s2
.LBB0_8:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s36, 0
s_mov_b32 s37, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_branch .LBB0_10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s38
s_add_i32 s36, s36, 1
s_add_i32 s37, s37, 16
s_cmpk_lg_i32 s36, 0x258
s_cbranch_scc0 .LBB0_14
.LBB0_10:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s2, 0
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s38, s37, s2
v_add_nc_u32_e32 v10, s2, v8
v_mov_b32_e32 v12, s38
s_add_i32 s2, s2, 8
ds_load_b64 v[10:11], v10
ds_load_b64 v[12:13], v12
s_cmp_eq_u32 s2, 8
s_waitcnt lgkmcnt(0)
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[10:11], v[4:5]
s_cbranch_scc1 .LBB0_11
s_mov_b32 s38, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f64_e32 1.0, v[4:5]
s_cbranch_execz .LBB0_9
v_mul_f64 v[4:5], v[4:5], -0.5
s_lshl_b32 s39, s36, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s39, s39, s35
s_lshl_b32 s39, s39, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[10:11], v[4:5], s[4:5]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[4:5]
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[4:5]
v_rndne_f64_e32 v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], s[6:7], v[4:5]
v_cvt_i32_f64_e32 v16, v[10:11]
v_mov_b32_e32 v4, s39
ds_load_b64 v[4:5], v4
v_fma_f64 v[12:13], v[10:11], s[8:9], v[12:13]
v_fma_f64 v[14:15], v[12:13], s[12:13], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[14:15]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[26:27]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
v_fma_f64 v[10:11], v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[10:11], v[10:11], v16
v_cndmask_b32_e32 v11, 0x7ff00000, v11, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cndmask_b32_e64 v11, 0, v11, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[10:11]
s_waitcnt lgkmcnt(0)
v_fma_f64 v[0:1], v[10:11], v[4:5], v[0:1]
s_branch .LBB0_9
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
s_add_i32 s2, s35, 1
s_cmp_eq_u32 s35, 0
v_rcp_f64_e32 v[10:11], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[4:5], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[4:5], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[0:1], v[2:3], v[0:1]
v_mul_f64 v[14:15], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[14:15], v[12:13]
v_div_fmas_f64 v[4:5], v[4:5], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
v_add_lshl_u32 v2, s35, v9, 3
ds_store_b64 v2, v[0:1] offset:19200
s_cbranch_scc1 .LBB0_7
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v10, s2, v8
s_add_i32 s2, s2, 8
ds_load_b64 v[2:3], v10 offset:9600
ds_load_b64 v[4:5], v10
s_cmp_lg_u32 s2, 8
s_waitcnt lgkmcnt(1)
ds_store_b64 v10, v[2:3]
s_waitcnt lgkmcnt(1)
v_add_f64 v[4:5], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], v[4:5], v[4:5], v[0:1]
s_cbranch_scc0 .LBB0_16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_nlt_f64_e32 vcc_lo, s[30:31], v[0:1]
s_mov_b32 s35, 0
s_or_b32 s34, vcc_lo, s34
s_and_not1_b32 exec_lo, exec_lo, s34
s_cbranch_execnz .LBB0_8
s_or_b32 exec_lo, exec_lo, s34
v_add_nc_u32_e32 v6, 1, v6
v_add_nc_u32_e32 v8, 16, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, v6, v7
s_or_b32 s33, vcc_lo, s33
s_and_not1_b32 exec_lo, exec_lo, s33
s_cbranch_execnz .LBB0_6
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_movk_i32 s4, 0x4b00
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_20:
v_mov_b32_e32 v1, s4
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s0, s2
s_addc_u32 s7, s1, s3
s_add_i32 s4, s4, 4
s_add_u32 s2, s2, 4
ds_load_u8 v2, v1
ds_load_u8 v3, v1 offset:1
ds_load_u8 v4, v1 offset:2
ds_load_u8 v1, v1 offset:3
s_addc_u32 s3, s3, 0
s_waitcnt lgkmcnt(3)
global_store_b8 v0, v2, s[6:7]
s_waitcnt lgkmcnt(2)
global_store_b8 v0, v3, s[6:7] offset:1
s_waitcnt lgkmcnt(1)
global_store_b8 v0, v4, s[6:7] offset:2
s_waitcnt lgkmcnt(0)
global_store_b8 v0, v1, s[6:7] offset:3
s_cmp_lg_u64 s[2:3], 0x4b0
s_cbranch_scc1 .LBB0_20
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15meanshiftSharedPdS_S_
.amdhsa_group_segment_fixed_size 28800
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 40
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15meanshiftSharedPdS_S_, .Lfunc_end0-_Z15meanshiftSharedPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 28800
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15meanshiftSharedPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z15meanshiftSharedPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
const int N = 600;
const int D = 2;
const int blocksize = 4;
const int gridsize = 4;
struct timeval startwtime, endwtime;
double seq_time;
double **alloc_2d_init(int rows, int cols);
double **init();
__shared__ double a_shared[600*2];
__shared__ double b_shared[600*2];
__shared__ double c_shared[600*2];
__device__
void findNext(int index){
double numinator;
double denuminator;
double distance;
double sigma = 1.0;
double c1;
int j,k,d;
for(j=0; j<D; j++){
numinator = 0.0;
denuminator = 0.0;
for(k=0; k<N; k++){
distance = 0.0;
for(d=0; d<D; d++){
distance += (b_shared[index*D+d]-a_shared[k*D+d])*(b_shared[index*D+d]-a_shared[k*D+d]);
}
if(distance<sigma*sigma){
c1 = exp(-distance/(2*sigma*sigma));
denuminator += c1;
numinator += c1*a_shared[k*D+j];
}
}
c_shared[index*D+j] = numinator/denuminator;
}
}
__global__
void meanshiftShared(double *a, double *b, double *c){
int index = blockIdx.x*blockDim.x + threadIdx.x;
int i,j;
memcpy(a_shared,a,N*D);
memcpy(b_shared,b,N*D);
double abs_m;
double epsilon = 0.0001;
for(i=index*N/(blockDim.x*blockDim.x); i<(index+1)*N/(blockDim.x*blockDim.x); i++){
abs_m = 1.0;
while(abs_m > epsilon){
findNext(i);
abs_m = 0.0;
for(j=0; j<D; j++){
abs_m += (c_shared[i*D+j]-b_shared[i*D+j])*(c_shared[i*D+j]-b_shared[i*D+j]);
b_shared[i*D+j] = c_shared[i*D+j];
}
}
}
memcpy(c,c_shared,N*D);
}
int main(){
double **points;
double **new_points;
double *lin_points, *lin_prev, *lin_next;
lin_points = (double *)malloc(N*D*sizeof(double));
lin_prev = (double *)malloc(N*D*sizeof(double));
lin_next = (double *)malloc(N*D*sizeof(double));
new_points = alloc_2d_init(N,D);
points = init();
int i,j,index;
for(i=0; i<N; i++){
for(j=0; j<D; j++){
index = j+i*D;
lin_points[index] = points[i][j];
lin_prev[index] = points[i][j];
}
}
double *ad, *bd, *cd;
const int size = N*D*sizeof(double);
hipMalloc((void **)&ad,size);
hipMalloc((void **)&bd,size);
hipMalloc((void **)&cd,size);
hipMemcpy(ad,lin_points,size,hipMemcpyHostToDevice);
hipMemcpy(bd,lin_prev,size,hipMemcpyHostToDevice);
dim3 dimBlock(blocksize);
dim3 dimGrid(gridsize);
gettimeofday (&startwtime, NULL);
meanshiftShared<<<dimGrid,dimBlock>>>(ad,bd,cd);
hipDeviceSynchronize();
gettimeofday (&endwtime, NULL);
seq_time = (double)((endwtime.tv_usec - startwtime.tv_usec)/1.0e6
+ endwtime.tv_sec - startwtime.tv_sec);
printf("Meanshift Shared wall clock time = %f\n\n", seq_time);
hipMemcpy(lin_next,cd,size,hipMemcpyDeviceToHost);
for(i=0; i<N; i++){
for(j=0; j<D; j++){
new_points[i][j] = lin_next[j+i*D];
}
}
hipFree(ad);
hipFree(bd);
hipFree(cd);
return EXIT_SUCCESS;
}
double **init(){
FILE *fp;
double *buffer;
double **ret_buf;
int size,number_of_elements;
int i,j,counter;
fp = fopen("data.bin","rb");
fseek(fp, 0, SEEK_END);
size = ftell(fp); //total size in bytes
number_of_elements = size/8; //total number of elements
buffer = (double *)malloc(number_of_elements*sizeof(double));
ret_buf = alloc_2d_init(N,D);
fseek(fp, 0, SEEK_SET);
fread(buffer,sizeof(buffer),number_of_elements,fp);
fclose(fp);
counter = 0;
for(j=0; j<D; j++){
for(i=0; i<N; i++){
ret_buf[i][j] = buffer[counter];
counter++;
}
}
return ret_buf;
}
double **alloc_2d_init(int rows, int cols){
double *data = (double *)malloc(rows*cols*sizeof(double));
double **array= (double **)malloc(rows*sizeof(double*));
int i;
for (i=0; i<rows; i++)
array[i] = &(data[cols*i]);
return array;
} | .text
.file "cuda_meanshift_shared.hip"
.globl _Z30__device_stub__meanshiftSharedPdS_S_ # -- Begin function _Z30__device_stub__meanshiftSharedPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__meanshiftSharedPdS_S_,@function
_Z30__device_stub__meanshiftSharedPdS_S_: # @_Z30__device_stub__meanshiftSharedPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15meanshiftSharedPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__meanshiftSharedPdS_S_, .Lfunc_end0-_Z30__device_stub__meanshiftSharedPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r12
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r15
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %rbx
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r13
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r13, (%r14,%rax,8)
incq %rax
addq $16, %r13
cmpq $600, %rax # imm = 0x258
jne .LBB1_1
# %bb.2: # %_Z13alloc_2d_initii.exit
xorl %r13d, %r13d
callq _Z4initv
movq %r12, %rcx
movq %r15, %rdx
.p2align 4, 0x90
.LBB1_3: # %.preheader38
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq (%rax,%r13,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rcx,%rdi,8)
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdx,%rdi,8)
incq %rdi
cmpq $1, %rdi
je .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
incq %r13
addq $16, %rdx
addq $16, %rcx
cmpq $600, %r13 # imm = 0x258
jne .LBB1_3
# %bb.6:
leaq 16(%rsp), %rdi
movl $9600, %esi # imm = 0x2580
callq hipMalloc
leaq 8(%rsp), %rdi
movl $9600, %esi # imm = 0x2580
callq hipMalloc
movq %rsp, %rdi
movl $9600, %esi # imm = 0x2580
callq hipMalloc
movq 16(%rsp), %rdi
movl $9600, %edx # imm = 0x2580
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $9600, %edx # imm = 0x2580
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $startwtime, %edi
xorl %esi, %esi
callq gettimeofday
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15meanshiftSharedPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
xorl %r15d, %r15d
movl $endwtime, %edi
xorl %esi, %esi
callq gettimeofday
movq endwtime+8(%rip), %rax
subq startwtime+8(%rip), %rax
cvtsi2sd %rax, %xmm1
divsd .LCPI1_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq endwtime(%rip), %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq startwtime(%rip), %xmm1
subsd %xmm1, %xmm0
movsd %xmm0, seq_time(%rip)
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movl $9600, %edx # imm = 0x2580
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movq (%r14,%r15,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rax,%rcx,8)
incq %rcx
cmpq $1, %rcx
je .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
incq %r15
addq $16, %rbx
cmpq $600, %r15 # imm = 0x258
jne .LBB1_9
# %bb.12:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z13alloc_2d_initii # -- Begin function _Z13alloc_2d_initii
.p2align 4, 0x90
.type _Z13alloc_2d_initii,@function
_Z13alloc_2d_initii: # @_Z13alloc_2d_initii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
movl %esi, %eax
imull %edi, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %rbx
movslq %ebp, %r15
leaq (,%r15,8), %rdi
callq malloc
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movslq %r14d, %rcx
movl %ebp, %edx
shlq $3, %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, (%rax,%rsi,8)
incq %rsi
addq %rcx, %rbx
cmpq %rsi, %rdx
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13alloc_2d_initii, .Lfunc_end2-_Z13alloc_2d_initii
.cfi_endproc
# -- End function
.globl _Z4initv # -- Begin function _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
xorl %ebp, %ebp
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r14, %rdi
callq ftell
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
movslq %ecx, %r12
leaq (,%r12,8), %rdi
callq malloc
movq %rax, %rbx
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r13
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r13, (%r15,%rbp,8)
incq %rbp
addq $16, %r13
cmpq $600, %rbp # imm = 0x258
jne .LBB3_1
# %bb.2: # %_Z13alloc_2d_initii.exit
xorl %r13d, %r13d
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $8, %esi
movq %rbx, %rdi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movq %r14, %rdi
callq fclose
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cltq
leaq (%rbx,%rax,8), %rdx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movq (%r15,%rcx,8), %rsi
movsd %xmm0, (%rsi,%r13,8)
incq %rcx
cmpq $600, %rcx # imm = 0x258
jne .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=1
leaq 1(%r13), %rdx
addq %rcx, %rax
testq %r13, %r13
movq %rdx, %r13
je .LBB3_3
# %bb.6:
movq %r15, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z4initv, .Lfunc_end3-_Z4initv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15meanshiftSharedPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type startwtime,@object # @startwtime
.bss
.globl startwtime
.p2align 3, 0x0
startwtime:
.zero 16
.size startwtime, 16
.type endwtime,@object # @endwtime
.globl endwtime
.p2align 3, 0x0
endwtime:
.zero 16
.size endwtime, 16
.type seq_time,@object # @seq_time
.globl seq_time
.p2align 3, 0x0
seq_time:
.quad 0x0000000000000000 # double 0
.size seq_time, 8
.type _Z15meanshiftSharedPdS_S_,@object # @_Z15meanshiftSharedPdS_S_
.section .rodata,"a",@progbits
.globl _Z15meanshiftSharedPdS_S_
.p2align 3, 0x0
_Z15meanshiftSharedPdS_S_:
.quad _Z30__device_stub__meanshiftSharedPdS_S_
.size _Z15meanshiftSharedPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Meanshift Shared wall clock time = %f\n\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "data.bin"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "rb"
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15meanshiftSharedPdS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__meanshiftSharedPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym startwtime
.addrsig_sym endwtime
.addrsig_sym _Z15meanshiftSharedPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005a979_00000000-6_cuda_meanshift_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8findNexti
.type _Z8findNexti, @function
_Z8findNexti:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8findNexti, .-_Z8findNexti
.globl _Z13alloc_2d_initii
.type _Z13alloc_2d_initii, @function
_Z13alloc_2d_initii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %r13d
movl %esi, %ebp
imull %esi, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %rbx
movslq %r13d, %r12
salq $3, %r12
movq %r12, %rdi
call malloc@PLT
testl %r13d, %r13d
jle .L5
movslq %ebp, %rsi
salq $3, %rsi
movq %rbx, %rcx
movq %rax, %rdx
addq %rax, %r12
.L7:
movq %rcx, (%rdx)
addq %rsi, %rcx
addq $8, %rdx
cmpq %r12, %rdx
jne .L7
.L5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z13alloc_2d_initii, .-_Z13alloc_2d_initii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "data.bin"
.text
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $2, %edx
movl $0, %esi
movq %rax, %rdi
call fseek@PLT
movq %r13, %rdi
call ftell@PLT
leal 7(%rax), %r12d
testl %eax, %eax
cmovns %eax, %r12d
sarl $3, %r12d
movslq %r12d, %r12
leaq 0(,%r12,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %esi
movl $600, %edi
call _Z13alloc_2d_initii
movq %rax, %rbx
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
movq %r13, %r8
movq %r12, %rcx
movl $8, %edx
movq %r14, %rsi
movq %rbp, %rdi
call __fread_chk@PLT
movq %r13, %rdi
call fclose@PLT
movl $0, %eax
.L11:
movq (%rbx,%rax), %rdx
movsd 0(%rbp,%rax), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $4800, %rax
jne .L11
movl $0, %eax
.L12:
movq (%rbx,%rax), %rdx
movsd 4800(%rbp,%rax), %xmm0
movsd %xmm0, 8(%rdx)
addq $8, %rax
cmpq $4800, %rax
jne .L12
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z4initv, .-_Z4initv
.globl _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
.type _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_, @function
_Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15meanshiftSharedPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_, .-_Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
.globl _Z15meanshiftSharedPdS_S_
.type _Z15meanshiftSharedPdS_S_, @function
_Z15meanshiftSharedPdS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15meanshiftSharedPdS_S_, .-_Z15meanshiftSharedPdS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Meanshift Shared wall clock time = %f\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $9600, %edi
call malloc@PLT
movq %rax, %r12
movl $9600, %edi
call malloc@PLT
movq %rax, %rbp
movl $9600, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %esi
movl $600, %edi
call _Z13alloc_2d_initii
movq %rax, %rbx
call _Z4initv
movl $0, %edx
.L25:
movq (%rax), %rcx
movsd (%rcx), %xmm0
movsd %xmm0, (%r12,%rdx)
movq (%rax), %rcx
movsd (%rcx), %xmm0
movsd %xmm0, 0(%rbp,%rdx)
movq (%rax), %rcx
movsd 8(%rcx), %xmm0
movsd %xmm0, 8(%r12,%rdx)
movq (%rax), %rcx
movsd 8(%rcx), %xmm0
movsd %xmm0, 8(%rbp,%rdx)
addq $8, %rax
addq $16, %rdx
cmpq $9600, %rdx
jne .L25
leaq 8(%rsp), %rdi
movl $9600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $9600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $9600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $9600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $9600, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
leaq startwtime(%rip), %rdi
call gettimeofday@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
call cudaDeviceSynchronize@PLT
movl $0, %esi
leaq endwtime(%rip), %rdi
call gettimeofday@PLT
movq 8+endwtime(%rip), %rax
subq 8+startwtime(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq endwtime(%rip), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq startwtime(%rip), %xmm1
subsd %xmm1, %xmm0
movsd %xmm0, seq_time(%rip)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $9600, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rax
addq $9600, %r13
.L27:
movq (%rbx), %rdx
movsd (%rax), %xmm0
movsd %xmm0, (%rdx)
movq (%rbx), %rdx
movsd 8(%rax), %xmm0
movsd %xmm0, 8(%rdx)
addq $8, %rbx
addq $16, %rax
cmpq %r13, %rax
jne .L27
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z15meanshiftSharedPdS_S_PdS_S_
jmp .L26
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z15meanshiftSharedPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15meanshiftSharedPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl seq_time
.bss
.align 8
.type seq_time, @object
.size seq_time, 8
seq_time:
.zero 8
.globl endwtime
.align 16
.type endwtime, @object
.size endwtime, 16
endwtime:
.zero 16
.globl startwtime
.align 16
.type startwtime, @object
.size startwtime, 16
startwtime:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_meanshift_shared.hip"
.globl _Z30__device_stub__meanshiftSharedPdS_S_ # -- Begin function _Z30__device_stub__meanshiftSharedPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__meanshiftSharedPdS_S_,@function
_Z30__device_stub__meanshiftSharedPdS_S_: # @_Z30__device_stub__meanshiftSharedPdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15meanshiftSharedPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__meanshiftSharedPdS_S_, .Lfunc_end0-_Z30__device_stub__meanshiftSharedPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r12
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r15
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %rbx
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r13
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r13, (%r14,%rax,8)
incq %rax
addq $16, %r13
cmpq $600, %rax # imm = 0x258
jne .LBB1_1
# %bb.2: # %_Z13alloc_2d_initii.exit
xorl %r13d, %r13d
callq _Z4initv
movq %r12, %rcx
movq %r15, %rdx
.p2align 4, 0x90
.LBB1_3: # %.preheader38
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movq (%rax,%r13,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rcx,%rdi,8)
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rdx,%rdi,8)
incq %rdi
cmpq $1, %rdi
je .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
incq %r13
addq $16, %rdx
addq $16, %rcx
cmpq $600, %r13 # imm = 0x258
jne .LBB1_3
# %bb.6:
leaq 16(%rsp), %rdi
movl $9600, %esi # imm = 0x2580
callq hipMalloc
leaq 8(%rsp), %rdi
movl $9600, %esi # imm = 0x2580
callq hipMalloc
movq %rsp, %rdi
movl $9600, %esi # imm = 0x2580
callq hipMalloc
movq 16(%rsp), %rdi
movl $9600, %edx # imm = 0x2580
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $9600, %edx # imm = 0x2580
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $startwtime, %edi
xorl %esi, %esi
callq gettimeofday
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15meanshiftSharedPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
xorl %r15d, %r15d
movl $endwtime, %edi
xorl %esi, %esi
callq gettimeofday
movq endwtime+8(%rip), %rax
subq startwtime+8(%rip), %rax
cvtsi2sd %rax, %xmm1
divsd .LCPI1_0(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq endwtime(%rip), %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq startwtime(%rip), %xmm1
subsd %xmm1, %xmm0
movsd %xmm0, seq_time(%rip)
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movl $9600, %edx # imm = 0x2580
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
movq (%r14,%r15,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rax,%rcx,8)
incq %rcx
cmpq $1, %rcx
je .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
incq %r15
addq $16, %rbx
cmpq $600, %r15 # imm = 0x258
jne .LBB1_9
# %bb.12:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z13alloc_2d_initii # -- Begin function _Z13alloc_2d_initii
.p2align 4, 0x90
.type _Z13alloc_2d_initii,@function
_Z13alloc_2d_initii: # @_Z13alloc_2d_initii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r14d
movl %edi, %ebp
movl %esi, %eax
imull %edi, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %rbx
movslq %ebp, %r15
leaq (,%r15,8), %rdi
callq malloc
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movslq %r14d, %rcx
movl %ebp, %edx
shlq $3, %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rbx, (%rax,%rsi,8)
incq %rsi
addq %rcx, %rbx
cmpq %rsi, %rdx
jne .LBB2_2
.LBB2_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13alloc_2d_initii, .Lfunc_end2-_Z13alloc_2d_initii
.cfi_endproc
# -- End function
.globl _Z4initv # -- Begin function _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
xorl %ebp, %ebp
movq %rax, %rdi
xorl %esi, %esi
movl $2, %edx
callq fseek
movq %r14, %rdi
callq ftell
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
movslq %ecx, %r12
leaq (,%r12,8), %rdi
callq malloc
movq %rax, %rbx
movl $9600, %edi # imm = 0x2580
callq malloc
movq %rax, %r13
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r13, (%r15,%rbp,8)
incq %rbp
addq $16, %r13
cmpq $600, %rbp # imm = 0x258
jne .LBB3_1
# %bb.2: # %_Z13alloc_2d_initii.exit
xorl %r13d, %r13d
movq %r14, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $8, %esi
movq %rbx, %rdi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movq %r14, %rdi
callq fclose
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cltq
leaq (%rbx,%rax,8), %rdx
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
movq (%r15,%rcx,8), %rsi
movsd %xmm0, (%rsi,%r13,8)
incq %rcx
cmpq $600, %rcx # imm = 0x258
jne .LBB3_4
# %bb.5: # in Loop: Header=BB3_3 Depth=1
leaq 1(%r13), %rdx
addq %rcx, %rax
testq %r13, %r13
movq %rdx, %r13
je .LBB3_3
# %bb.6:
movq %r15, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z4initv, .Lfunc_end3-_Z4initv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15meanshiftSharedPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type startwtime,@object # @startwtime
.bss
.globl startwtime
.p2align 3, 0x0
startwtime:
.zero 16
.size startwtime, 16
.type endwtime,@object # @endwtime
.globl endwtime
.p2align 3, 0x0
endwtime:
.zero 16
.size endwtime, 16
.type seq_time,@object # @seq_time
.globl seq_time
.p2align 3, 0x0
seq_time:
.quad 0x0000000000000000 # double 0
.size seq_time, 8
.type _Z15meanshiftSharedPdS_S_,@object # @_Z15meanshiftSharedPdS_S_
.section .rodata,"a",@progbits
.globl _Z15meanshiftSharedPdS_S_
.p2align 3, 0x0
_Z15meanshiftSharedPdS_S_:
.quad _Z30__device_stub__meanshiftSharedPdS_S_
.size _Z15meanshiftSharedPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Meanshift Shared wall clock time = %f\n\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "data.bin"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "rb"
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15meanshiftSharedPdS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__meanshiftSharedPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym startwtime
.addrsig_sym endwtime
.addrsig_sym _Z15meanshiftSharedPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int translate_idx_inv( int ii, int d1, int d2, int d3, int scale_factor, int off_x, int off_y) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w*scale_factor+off_x;
z = z*scale_factor+off_y;
d2 *= scale_factor;
d3 *= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int scale_factor) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor;
z = z/scale_factor;
d2 /= scale_factor;
d3 /= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ __forceinline__ size_t idx(const size_t nc, const size_t height, const size_t width, const size_t y, const size_t x) {
return (nc * height + y) * width + x;
}
__global__ void downscale(float *gradInput_data, const float *gradOutput_data, long no_elements, int scale_factor, int d1, int d2, int d3) {
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor; i++){
for(int j=0; j < scale_factor; j++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, scale_factor, i, j);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
} | code for sm_80
Function : _Z9downscalePfPKfliiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, UR4, R5 ; /* 0x0000000402037c24 */
/* 0x002fe4000f8e0205 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3 R9, P2, R0, R3, RZ ; /* 0x0000000300097210 */
/* 0x000fe40007f5e0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f06270 */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fe40003f26070 */
/*00f0*/ IADD3.X R8, RZ, RZ, RZ, P2, !PT ; /* 0x000000ffff087210 */
/* 0x000fc800017fe4ff */
/*0100*/ ISETP.GE.OR.EX P0, PT, R8, c[0x0][0x174], !P0, P1 ; /* 0x00005d0008007a0c */
/* 0x000fda0004706710 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ IABS R4, c[0x0][0x184] ; /* 0x0000610000047a13 */
/* 0x000fe20000000000 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IABS R6, R9 ; /* 0x0000000900067213 */
/* 0x000fe40000000000 */
/*0150*/ I2F.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e220000209400 */
/*0160*/ LOP3.LUT R20, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305147812 */
/* 0x000fce00078ec0ff */
/*0170*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0180*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*01b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*01c0*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x000fca00078e02ff */
/*01d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*01e0*/ LOP3.LUT R2, R9, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610009027a12 */
/* 0x000fe400078e3cff */
/*01f0*/ IADD3 R7, R20, -c[0x0][0x178], RZ ; /* 0x80005e0014077a10 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0210*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R2, R5, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x000fc60007ffe0ff */
/*0230*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a00 */
/*0240*/ IMAD R5, R5, c[0x0][0x184], RZ ; /* 0x0000610005057a24 */
/* 0x000fe400078e02ff */
/*0250*/ IMAD R3, R4, R3, R6 ; /* 0x0000000304037224 */
/* 0x000fe200078e0206 */
/*0260*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc80000000f00 */
/*0270*/ ISETP.GT.U32.AND P2, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f44070 */
/*0280*/ @!P2 IADD3 R3, R3, -R4.reuse, RZ ; /* 0x800000040303a210 */
/* 0x080fe40007ffe0ff */
/*0290*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe40003f06070 */
/*02b0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fd60003f45270 */
/*02c0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fc60003f06070 */
/*02e0*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*02f0*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff00aa12 */
/* 0x000fe400078e33ff */
/*0300*/ LEA R2, P1, R9, c[0x0][0x160], 0x2 ; /* 0x0000580009027a11 */
/* 0x000fc600078210ff */
/*0310*/ IMAD R4, R0, c[0x0][0x184], RZ ; /* 0x0000610000047a24 */
/* 0x000fe200078e02ff */
/*0320*/ LEA.HI.X R3, R9, c[0x0][0x164], R8, 0x2, P1 ; /* 0x0000590009037a11 */
/* 0x000fc600008f1408 */
/*0330*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe400078e0a04 */
/*0340*/ ISETP.NE.AND P2, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f45270 */
/*0350*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0360*/ @!P0 BRA 0x510 ; /* 0x000001a000008947 */
/* 0x007ff40003800000 */
/*0370*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000162000c1e1900 */
/*0380*/ IMAD R11, R4, c[0x0][0x178], R9 ; /* 0x00005e00040b7a24 */
/* 0x000fe400078e0209 */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*03a0*/ IMAD R18, R11, c[0x0][0x178], R6 ; /* 0x00005e000b127a24 */
/* 0x000fe400078e0206 */
/*03b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fd400000001ff */
/*03c0*/ IMAD.WIDE R10, R18, R11, c[0x0][0x168] ; /* 0x00005a00120a7625 */
/* 0x000fca00078e020b */
/*03d0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FADD R21, R12, R19 ; /* 0x000000130c157221 */
/* 0x026fe40000000000 */
/*03f0*/ IMAD.WIDE R12, R5, 0x4, R10 ; /* 0x00000004050c7825 */
/* 0x000fc600078e020a */
/*0400*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea4000c1e1900 */
/*0420*/ FADD R23, R21, R14 ; /* 0x0000000e15177221 */
/* 0x004fe40000000000 */
/*0430*/ IMAD.WIDE R14, R5, 0x4, R12 ; /* 0x00000004050e7825 */
/* 0x000fc600078e020c */
/*0440*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0450*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1900 */
/*0460*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0470*/ FADD R25, R23, R16 ; /* 0x0000001017197221 */
/* 0x004fe40000000000 */
/*0480*/ IMAD.WIDE R16, R5, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x000fc600078e020e */
/*0490*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.IADD R10, R7, 0x1, R8 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0208 */
/*04c0*/ LEA R18, R5, R18, 0x2 ; /* 0x0000001205127211 */
/* 0x000fc800078e10ff */
/*04d0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*04e0*/ FADD R19, R25, R16 ; /* 0x0000001019137221 */
/* 0x004fca0000000000 */
/*04f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003ee000c101904 */
/*0500*/ @P1 BRA 0x3b0 ; /* 0xfffffea000001947 */
/* 0x000fea000383ffff */
/*0510*/ @!P2 BRA 0x6d0 ; /* 0x000001b00000a947 */
/* 0x000fea0003800000 */
/*0520*/ IMAD R12, R0, c[0x0][0x178], R8 ; /* 0x00005e00000c7a24 */
/* 0x000fe200078e0208 */
/*0530*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x000fe20000000f00 */
/*0540*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0550*/ IMAD R11, R12, c[0x0][0x184], R9 ; /* 0x000061000c0b7a24 */
/* 0x000fc800078e0209 */
/*0560*/ IMAD R11, R11, c[0x0][0x178], R6 ; /* 0x00005e000b0b7a24 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD.WIDE R10, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e020e */
/*0580*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ ISETP.NE.AND P1, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe20003f25270 */
/*05a0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*05b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005ee000c101904 */
/*05c0*/ @!P1 BRA 0x6d0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R8, R12, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x000fca0007ffe0ff */
/*05e0*/ IMAD R11, R8, c[0x0][0x184], R9 ; /* 0x00006100080b7a24 */
/* 0x000fc800078e0209 */
/*05f0*/ IMAD R11, R11, c[0x0][0x178], R6 ; /* 0x00005e000b0b7a24 */
/* 0x000fc800078e0206 */
/*0600*/ IMAD.WIDE R10, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e020e */
/*0610*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0620*/ ISETP.NE.AND P1, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe20003f25270 */
/*0630*/ FADD R13, R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x00cfca0000000000 */
/*0640*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005ee000c101904 */
/*0650*/ @!P1 BRA 0x6d0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0660*/ IADD3 R8, R12, 0x2, RZ ; /* 0x000000020c087810 */
/* 0x000fca0007ffe0ff */
/*0670*/ IMAD R11, R8, c[0x0][0x184], R9 ; /* 0x00006100080b7a24 */
/* 0x000fc800078e0209 */
/*0680*/ IMAD R11, R11, c[0x0][0x178], R6 ; /* 0x00005e000b0b7a24 */
/* 0x000fc800078e0206 */
/*0690*/ IMAD.WIDE R10, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e020e */
/*06a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1900 */
/*06b0*/ FADD R13, R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x00cfca0000000000 */
/*06c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e4000c101904 */
/*06d0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f26270 */
/*06f0*/ @!P1 BRA 0x340 ; /* 0xfffffc4000009947 */
/* 0x000fea000383ffff */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x710; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int translate_idx_inv( int ii, int d1, int d2, int d3, int scale_factor, int off_x, int off_y) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w*scale_factor+off_x;
z = z*scale_factor+off_y;
d2 *= scale_factor;
d3 *= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int scale_factor) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor;
z = z/scale_factor;
d2 /= scale_factor;
d3 /= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ __forceinline__ size_t idx(const size_t nc, const size_t height, const size_t width, const size_t y, const size_t x) {
return (nc * height + y) * width + x;
}
__global__ void downscale(float *gradInput_data, const float *gradOutput_data, long no_elements, int scale_factor, int d1, int d2, int d3) {
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor; i++){
for(int j=0; j < scale_factor; j++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, scale_factor, i, j);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
} | .file "tmpxft_0012cc8b_00000000-6_downscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17translate_idx_inviiiiiii
.type _Z17translate_idx_inviiiiiii, @function
_Z17translate_idx_inviiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17translate_idx_inviiiiiii, .-_Z17translate_idx_inviiiiiii
.globl _Z13translate_idxiiiii
.type _Z13translate_idxiiiii, @function
_Z13translate_idxiiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z13translate_idxiiiii, .-_Z13translate_idxiiiii
.globl _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii
.type _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii, @function
_Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9downscalePfPKfliiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii, .-_Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii
.globl _Z9downscalePfPKfliiii
.type _Z9downscalePfPKfliiii, @function
_Z9downscalePfPKfliiii:
.LFB2055:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z9downscalePfPKfliiii, .-_Z9downscalePfPKfliiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9downscalePfPKfliiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9downscalePfPKfliiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int translate_idx_inv( int ii, int d1, int d2, int d3, int scale_factor, int off_x, int off_y) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w*scale_factor+off_x;
z = z*scale_factor+off_y;
d2 *= scale_factor;
d3 *= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int scale_factor) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor;
z = z/scale_factor;
d2 /= scale_factor;
d3 /= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ __forceinline__ size_t idx(const size_t nc, const size_t height, const size_t width, const size_t y, const size_t x) {
return (nc * height + y) * width + x;
}
__global__ void downscale(float *gradInput_data, const float *gradOutput_data, long no_elements, int scale_factor, int d1, int d2, int d3) {
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor; i++){
for(int j=0; j < scale_factor; j++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, scale_factor, i, j);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx_inv( int ii, int d1, int d2, int d3, int scale_factor, int off_x, int off_y) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w*scale_factor+off_x;
z = z*scale_factor+off_y;
d2 *= scale_factor;
d3 *= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int scale_factor) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor;
z = z/scale_factor;
d2 /= scale_factor;
d3 /= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ __forceinline__ size_t idx(const size_t nc, const size_t height, const size_t width, const size_t y, const size_t x) {
return (nc * height + y) * width + x;
}
__global__ void downscale(float *gradInput_data, const float *gradOutput_data, long no_elements, int scale_factor, int d1, int d2, int d3) {
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor; i++){
for(int j=0; j < scale_factor; j++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, scale_factor, i, j);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx_inv( int ii, int d1, int d2, int d3, int scale_factor, int off_x, int off_y) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w*scale_factor+off_x;
z = z*scale_factor+off_y;
d2 *= scale_factor;
d3 *= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int scale_factor) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor;
z = z/scale_factor;
d2 /= scale_factor;
d3 /= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ __forceinline__ size_t idx(const size_t nc, const size_t height, const size_t width, const size_t y, const size_t x) {
return (nc * height + y) * width + x;
}
__global__ void downscale(float *gradInput_data, const float *gradOutput_data, long no_elements, int scale_factor, int d1, int d2, int d3) {
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor; i++){
for(int j=0; j < scale_factor; j++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, scale_factor, i, j);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9downscalePfPKfliiii
.globl _Z9downscalePfPKfliiii
.p2align 8
.type _Z9downscalePfPKfliiii,@function
_Z9downscalePfPKfliiii:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s3, 0xffff
s_mul_i32 s6, s6, s15
s_lshr_b32 s3, s3, 16
s_mul_i32 s6, s6, s7
v_mad_u64_u32 v[2:3], null, s14, s7, v[1:2]
v_mad_u64_u32 v[3:4], null, s6, s3, v[0:1]
s_cmp_gt_i32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s3, v3, v2
v_add_co_ci_u32_e64 v3, null, 0, 0, s3
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[2:3]
s_cselect_b32 s4, -1, 0
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_load_b32 s0, s[0:1], 0x24
v_ashrrev_i32_e32 v6, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v2, v6
v_xor_b32_e32 v7, v7, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s0, s1
global_load_b32 v4, v[0:1], off
s_xor_b32 s4, s4, s1
v_xor_b32_e32 v6, s1, v6
v_cvt_f32_u32_e32 v3, s4
s_sub_i32 s5, 0, s4
s_add_i32 s1, s2, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s5, v3
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v5
v_mul_hi_u32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v3, s4
v_sub_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v8, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
v_add_nc_u32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v6
v_sub_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s0, v3
s_mul_i32 s0, s0, s2
v_mad_u64_u32 v[5:6], null, v3, s1, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v5, s2, v5
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v5
s_mov_b32 s1, s2
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s1, s1, -1
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, s0, v2
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v3, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, s2
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9downscalePfPKfliiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9downscalePfPKfliiii, .Lfunc_end0-_Z9downscalePfPKfliiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9downscalePfPKfliiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9downscalePfPKfliiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int translate_idx_inv( int ii, int d1, int d2, int d3, int scale_factor, int off_x, int off_y) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w*scale_factor+off_x;
z = z*scale_factor+off_y;
d2 *= scale_factor;
d3 *= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ int translate_idx(int ii, int d1, int d2, int d3, int scale_factor) {
int x, y, z, w;
w = ii % d3;
ii = ii/d3;
z = ii % d2;
ii = ii/d2;
y = ii % d1;
ii = ii/d1;
x = ii;
w = w/scale_factor;
z = z/scale_factor;
d2 /= scale_factor;
d3 /= scale_factor;
return (((x*d1+y)*d2)+z)*d3+w;
}
__device__ __forceinline__ size_t idx(const size_t nc, const size_t height, const size_t width, const size_t y, const size_t x) {
return (nc * height + y) * width + x;
}
__global__ void downscale(float *gradInput_data, const float *gradOutput_data, long no_elements, int scale_factor, int d1, int d2, int d3) {
long ii = threadIdx.x + blockDim.x * blockIdx.x;
ii += threadIdx.y + blockDim.y * (blockDim.x * gridDim.x) * blockIdx.y;
if (ii >= no_elements) return;
for (int i=0; i < scale_factor; i++){
for(int j=0; j < scale_factor; j++){
int ipidx = translate_idx_inv(ii, d1, d2, d3, scale_factor, i, j);
gradInput_data[ii] += gradOutput_data[ipidx];
}
}
} | .text
.file "downscale.hip"
.globl _Z24__device_stub__downscalePfPKfliiii # -- Begin function _Z24__device_stub__downscalePfPKfliiii
.p2align 4, 0x90
.type _Z24__device_stub__downscalePfPKfliiii,@function
_Z24__device_stub__downscalePfPKfliiii: # @_Z24__device_stub__downscalePfPKfliiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9downscalePfPKfliiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__downscalePfPKfliiii, .Lfunc_end0-_Z24__device_stub__downscalePfPKfliiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9downscalePfPKfliiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9downscalePfPKfliiii,@object # @_Z9downscalePfPKfliiii
.section .rodata,"a",@progbits
.globl _Z9downscalePfPKfliiii
.p2align 3, 0x0
_Z9downscalePfPKfliiii:
.quad _Z24__device_stub__downscalePfPKfliiii
.size _Z9downscalePfPKfliiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9downscalePfPKfliiii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__downscalePfPKfliiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9downscalePfPKfliiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9downscalePfPKfliiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC.64 UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR6, URZ ; /* 0x00000006040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ IMAD R3, R2, UR4, R5 ; /* 0x0000000402037c24 */
/* 0x002fe4000f8e0205 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff057624 */
/* 0x000fc600078e00ff */
/*00c0*/ IADD3 R9, P2, R0, R3, RZ ; /* 0x0000000300097210 */
/* 0x000fe40007f5e0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f06270 */
/*00e0*/ ISETP.GE.U32.AND P1, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fe40003f26070 */
/*00f0*/ IADD3.X R8, RZ, RZ, RZ, P2, !PT ; /* 0x000000ffff087210 */
/* 0x000fc800017fe4ff */
/*0100*/ ISETP.GE.OR.EX P0, PT, R8, c[0x0][0x174], !P0, P1 ; /* 0x00005d0008007a0c */
/* 0x000fda0004706710 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ IABS R4, c[0x0][0x184] ; /* 0x0000610000047a13 */
/* 0x000fe20000000000 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IABS R6, R9 ; /* 0x0000000900067213 */
/* 0x000fe40000000000 */
/*0150*/ I2F.RP R0, R4 ; /* 0x0000000400007306 */
/* 0x000e220000209400 */
/*0160*/ LOP3.LUT R20, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305147812 */
/* 0x000fce00078ec0ff */
/*0170*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0180*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*01a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*01b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*01c0*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x000fca00078e02ff */
/*01d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*01e0*/ LOP3.LUT R2, R9, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610009027a12 */
/* 0x000fe400078e3cff */
/*01f0*/ IADD3 R7, R20, -c[0x0][0x178], RZ ; /* 0x80005e0014077a10 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0210*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R2, R5, -0x1, RZ ; /* 0xffffffff05027810 */
/* 0x000fc60007ffe0ff */
/*0230*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a00 */
/*0240*/ IMAD R5, R5, c[0x0][0x184], RZ ; /* 0x0000610005057a24 */
/* 0x000fe400078e02ff */
/*0250*/ IMAD R3, R4, R3, R6 ; /* 0x0000000304037224 */
/* 0x000fe200078e0206 */
/*0260*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc80000000f00 */
/*0270*/ ISETP.GT.U32.AND P2, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x000fda0003f44070 */
/*0280*/ @!P2 IADD3 R3, R3, -R4.reuse, RZ ; /* 0x800000040303a210 */
/* 0x080fe40007ffe0ff */
/*0290*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fe40003f06070 */
/*02b0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fd60003f45270 */
/*02c0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fc60003f06070 */
/*02e0*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*02f0*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff00aa12 */
/* 0x000fe400078e33ff */
/*0300*/ LEA R2, P1, R9, c[0x0][0x160], 0x2 ; /* 0x0000580009027a11 */
/* 0x000fc600078210ff */
/*0310*/ IMAD R4, R0, c[0x0][0x184], RZ ; /* 0x0000610000047a24 */
/* 0x000fe200078e02ff */
/*0320*/ LEA.HI.X R3, R9, c[0x0][0x164], R8, 0x2, P1 ; /* 0x0000590009037a11 */
/* 0x000fc600008f1408 */
/*0330*/ IMAD.IADD R9, R9, 0x1, -R4 ; /* 0x0000000109097824 */
/* 0x000fe400078e0a04 */
/*0340*/ ISETP.NE.AND P2, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f45270 */
/*0350*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe20000000f00 */
/*0360*/ @!P0 BRA 0x510 ; /* 0x000001a000008947 */
/* 0x007ff40003800000 */
/*0370*/ LDG.E R19, [R2.64] ; /* 0x0000000402137981 */
/* 0x000162000c1e1900 */
/*0380*/ IMAD R11, R4, c[0x0][0x178], R9 ; /* 0x00005e00040b7a24 */
/* 0x000fe400078e0209 */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*03a0*/ IMAD R18, R11, c[0x0][0x178], R6 ; /* 0x00005e000b127a24 */
/* 0x000fe400078e0206 */
/*03b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fd400000001ff */
/*03c0*/ IMAD.WIDE R10, R18, R11, c[0x0][0x168] ; /* 0x00005a00120a7625 */
/* 0x000fca00078e020b */
/*03d0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FADD R21, R12, R19 ; /* 0x000000130c157221 */
/* 0x026fe40000000000 */
/*03f0*/ IMAD.WIDE R12, R5, 0x4, R10 ; /* 0x00000004050c7825 */
/* 0x000fc600078e020a */
/*0400*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea4000c1e1900 */
/*0420*/ FADD R23, R21, R14 ; /* 0x0000000e15177221 */
/* 0x004fe40000000000 */
/*0430*/ IMAD.WIDE R14, R5, 0x4, R12 ; /* 0x00000004050e7825 */
/* 0x000fc600078e020c */
/*0440*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0450*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1900 */
/*0460*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0470*/ FADD R25, R23, R16 ; /* 0x0000001017197221 */
/* 0x004fe40000000000 */
/*0480*/ IMAD.WIDE R16, R5, 0x4, R14 ; /* 0x0000000405107825 */
/* 0x000fc600078e020e */
/*0490*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.IADD R10, R7, 0x1, R8 ; /* 0x00000001070a7824 */
/* 0x000fe200078e0208 */
/*04c0*/ LEA R18, R5, R18, 0x2 ; /* 0x0000001205127211 */
/* 0x000fc800078e10ff */
/*04d0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*04e0*/ FADD R19, R25, R16 ; /* 0x0000001019137221 */
/* 0x004fca0000000000 */
/*04f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003ee000c101904 */
/*0500*/ @P1 BRA 0x3b0 ; /* 0xfffffea000001947 */
/* 0x000fea000383ffff */
/*0510*/ @!P2 BRA 0x6d0 ; /* 0x000001b00000a947 */
/* 0x000fea0003800000 */
/*0520*/ IMAD R12, R0, c[0x0][0x178], R8 ; /* 0x00005e00000c7a24 */
/* 0x000fe200078e0208 */
/*0530*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x000fe20000000f00 */
/*0540*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0550*/ IMAD R11, R12, c[0x0][0x184], R9 ; /* 0x000061000c0b7a24 */
/* 0x000fc800078e0209 */
/*0560*/ IMAD R11, R11, c[0x0][0x178], R6 ; /* 0x00005e000b0b7a24 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD.WIDE R10, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e020e */
/*0580*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ ISETP.NE.AND P1, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe20003f25270 */
/*05a0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*05b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005ee000c101904 */
/*05c0*/ @!P1 BRA 0x6d0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R8, R12, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x000fca0007ffe0ff */
/*05e0*/ IMAD R11, R8, c[0x0][0x184], R9 ; /* 0x00006100080b7a24 */
/* 0x000fc800078e0209 */
/*05f0*/ IMAD R11, R11, c[0x0][0x178], R6 ; /* 0x00005e000b0b7a24 */
/* 0x000fc800078e0206 */
/*0600*/ IMAD.WIDE R10, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e020e */
/*0610*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*0620*/ ISETP.NE.AND P1, PT, R20, 0x2, PT ; /* 0x000000021400780c */
/* 0x000fe20003f25270 */
/*0630*/ FADD R13, R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x00cfca0000000000 */
/*0640*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005ee000c101904 */
/*0650*/ @!P1 BRA 0x6d0 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0660*/ IADD3 R8, R12, 0x2, RZ ; /* 0x000000020c087810 */
/* 0x000fca0007ffe0ff */
/*0670*/ IMAD R11, R8, c[0x0][0x184], R9 ; /* 0x00006100080b7a24 */
/* 0x000fc800078e0209 */
/*0680*/ IMAD R11, R11, c[0x0][0x178], R6 ; /* 0x00005e000b0b7a24 */
/* 0x000fc800078e0206 */
/*0690*/ IMAD.WIDE R10, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e020e */
/*06a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1900 */
/*06b0*/ FADD R13, R13, R10 ; /* 0x0000000a0d0d7221 */
/* 0x00cfca0000000000 */
/*06c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e4000c101904 */
/*06d0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc80007ffe0ff */
/*06e0*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f26270 */
/*06f0*/ @!P1 BRA 0x340 ; /* 0xfffffc4000009947 */
/* 0x000fea000383ffff */
/*0700*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x710; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9downscalePfPKfliiii
.globl _Z9downscalePfPKfliiii
.p2align 8
.type _Z9downscalePfPKfliiii,@function
_Z9downscalePfPKfliiii:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s6, s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s3, 0xffff
s_mul_i32 s6, s6, s15
s_lshr_b32 s3, s3, 16
s_mul_i32 s6, s6, s7
v_mad_u64_u32 v[2:3], null, s14, s7, v[1:2]
v_mad_u64_u32 v[3:4], null, s6, s3, v[0:1]
s_cmp_gt_i32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s3, v3, v2
v_add_co_ci_u32_e64 v3, null, 0, 0, s3
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[2:3]
s_cselect_b32 s4, -1, 0
s_and_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_5
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_load_b32 s0, s[0:1], 0x24
v_ashrrev_i32_e32 v6, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, v2, v6
v_xor_b32_e32 v7, v7, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s4, s0, s1
global_load_b32 v4, v[0:1], off
s_xor_b32 s4, s4, s1
v_xor_b32_e32 v6, s1, v6
v_cvt_f32_u32_e32 v3, s4
s_sub_i32 s5, 0, s4
s_add_i32 s1, s2, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s5, v3
v_mul_hi_u32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v5
v_mul_hi_u32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v3, s4
v_sub_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v8, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
v_add_nc_u32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v3, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v6
v_sub_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s0, v3
s_mul_i32 s0, s0, s2
v_mad_u64_u32 v[5:6], null, v3, s1, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v5, s2, v5
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v5
s_mov_b32 s1, s2
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s1, s1, -1
s_cmp_eq_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, s0, v2
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v3, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, s2
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9downscalePfPKfliiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9downscalePfPKfliiii, .Lfunc_end0-_Z9downscalePfPKfliiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9downscalePfPKfliiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9downscalePfPKfliiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012cc8b_00000000-6_downscale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17translate_idx_inviiiiiii
.type _Z17translate_idx_inviiiiiii, @function
_Z17translate_idx_inviiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z17translate_idx_inviiiiiii, .-_Z17translate_idx_inviiiiiii
.globl _Z13translate_idxiiiii
.type _Z13translate_idxiiiii, @function
_Z13translate_idxiiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z13translate_idxiiiii, .-_Z13translate_idxiiiii
.globl _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii
.type _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii, @function
_Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9downscalePfPKfliiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii, .-_Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii
.globl _Z9downscalePfPKfliiii
.type _Z9downscalePfPKfliiii, @function
_Z9downscalePfPKfliiii:
.LFB2055:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9downscalePfPKfliiiiPfPKfliiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z9downscalePfPKfliiii, .-_Z9downscalePfPKfliiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9downscalePfPKfliiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9downscalePfPKfliiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "downscale.hip"
.globl _Z24__device_stub__downscalePfPKfliiii # -- Begin function _Z24__device_stub__downscalePfPKfliiii
.p2align 4, 0x90
.type _Z24__device_stub__downscalePfPKfliiii,@function
_Z24__device_stub__downscalePfPKfliiii: # @_Z24__device_stub__downscalePfPKfliiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9downscalePfPKfliiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__downscalePfPKfliiii, .Lfunc_end0-_Z24__device_stub__downscalePfPKfliiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9downscalePfPKfliiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9downscalePfPKfliiii,@object # @_Z9downscalePfPKfliiii
.section .rodata,"a",@progbits
.globl _Z9downscalePfPKfliiii
.p2align 3, 0x0
_Z9downscalePfPKfliiii:
.quad _Z24__device_stub__downscalePfPKfliiii
.size _Z9downscalePfPKfliiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9downscalePfPKfliiii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__downscalePfPKfliiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9downscalePfPKfliiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#include <cuda.h>
typedef unsigned char BYTE; // 8-bit byte
typedef unsigned int WORD; // 32-bit word, change to "long" for 16-bit machines
typedef struct {
BYTE data[64];
WORD datalen;
unsigned long long bitlen;
WORD state[5];
WORD k[4];
} SHA1_CTX;
#define ROTLEFT(a, b) ((a << b) | (a >> (32 - b)))
#define SHA1_BLOCK_SIZE 20 // SHA1 outputs a 20 byte digest
#define PAGE_SIZE 4096
__device__ void sha1_init(SHA1_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen = 0;
ctx->state[0] = 0x67452301;
ctx->state[1] = 0xEFCDAB89;
ctx->state[2] = 0x98BADCFE;
ctx->state[3] = 0x10325476;
ctx->state[4] = 0xc3d2e1f0;
ctx->k[0] = 0x5a827999;
ctx->k[1] = 0x6ed9eba1;
ctx->k[2] = 0x8f1bbcdc;
ctx->k[3] = 0xca62c1d6;
}
__device__ void sha1_transform(SHA1_CTX *ctx, const BYTE data[])
{
WORD a, b, c, d, e, i, j, t, m[80];
for (i = 0, j = 0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) + (data[j + 1] << 16) + (data[j + 2] << 8) + (data[j + 3]);
for ( ; i < 80; ++i) {
m[i] = (m[i - 3] ^ m[i - 8] ^ m[i - 14] ^ m[i - 16]);
m[i] = (m[i] << 1) | (m[i] >> 31);
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
for (i = 0; i < 20; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (~b & d)) + e + ctx->k[0] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 40; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[1] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 60; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (b & d) ^ (c & d)) + e + ctx->k[2] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 80; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[3] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
}
__device__ void sha1_update(SHA1_CTX *ctx, const BYTE data[], size_t len)
{
size_t i;
for (i = 0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha1_transform(ctx, ctx->data);
ctx->bitlen += 512;
ctx->datalen = 0;
}
}
}
__device__ void sha1_final(SHA1_CTX *ctx, BYTE hash[])
{
WORD i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha1_transform(ctx, ctx->data);
while (i < 7)
ctx->data[i++] = 0x00;
}
// Append to the padding the total message's length in bits and transform.
ctx->bitlen += ctx->datalen * 8;
ctx->data[63] = ctx->bitlen;
ctx->data[62] = ctx->bitlen >> 8;
ctx->data[61] = ctx->bitlen >> 16;
ctx->data[60] = ctx->bitlen >> 24;
ctx->data[59] = ctx->bitlen >> 32;
ctx->data[58] = ctx->bitlen >> 40;
ctx->data[57] = ctx->bitlen >> 48;
ctx->data[56] = ctx->bitlen >> 56;
sha1_transform(ctx, ctx->data);
// Since this implementation uses little endian byte ordering and MD uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i = 0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
}
}
extern "C" __global__
void gpusha1(unsigned char* text1, unsigned char* hashval, int text_num) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
SHA1_CTX ctx;
unsigned char text_dev[PAGE_SIZE];
unsigned char hashval_dev[SHA1_BLOCK_SIZE];
int i;
if (thx < text_num) {
for (i = 0; i < PAGE_SIZE; ++i) {
text_dev[i] = text1[i + thx*PAGE_SIZE];
}
sha1_init(&ctx);
sha1_update(&ctx, text_dev, PAGE_SIZE);
sha1_final(&ctx, hashval_dev);
for (i = 0; i < SHA1_BLOCK_SIZE; ++i) {
hashval[i + thx*SHA1_BLOCK_SIZE] = hashval_dev[i];
}
}
} | .file "tmpxft_0004bd29_00000000-6_gpusha1cuda_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9sha1_initP8SHA1_CTX
.type _Z9sha1_initP8SHA1_CTX, @function
_Z9sha1_initP8SHA1_CTX:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9sha1_initP8SHA1_CTX, .-_Z9sha1_initP8SHA1_CTX
.globl _Z14sha1_transformP8SHA1_CTXPKh
.type _Z14sha1_transformP8SHA1_CTXPKh, @function
_Z14sha1_transformP8SHA1_CTXPKh:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z14sha1_transformP8SHA1_CTXPKh, .-_Z14sha1_transformP8SHA1_CTXPKh
.globl _Z11sha1_updateP8SHA1_CTXPKhm
.type _Z11sha1_updateP8SHA1_CTXPKhm, @function
_Z11sha1_updateP8SHA1_CTXPKhm:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11sha1_updateP8SHA1_CTXPKhm, .-_Z11sha1_updateP8SHA1_CTXPKhm
.globl _Z10sha1_finalP8SHA1_CTXPh
.type _Z10sha1_finalP8SHA1_CTXPh, @function
_Z10sha1_finalP8SHA1_CTXPh:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z10sha1_finalP8SHA1_CTXPh, .-_Z10sha1_finalP8SHA1_CTXPh
.globl _Z29__device_stub__Z7gpusha1PhS_iPhS_i
.type _Z29__device_stub__Z7gpusha1PhS_iPhS_i, @function
_Z29__device_stub__Z7gpusha1PhS_iPhS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gpusha1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z7gpusha1PhS_iPhS_i, .-_Z29__device_stub__Z7gpusha1PhS_iPhS_i
.globl gpusha1
.type gpusha1, @function
gpusha1:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7gpusha1PhS_iPhS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size gpusha1, .-gpusha1
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gpusha1"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gpusha1(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <cuda.h>
typedef unsigned char BYTE; // 8-bit byte
typedef unsigned int WORD; // 32-bit word, change to "long" for 16-bit machines
typedef struct {
BYTE data[64];
WORD datalen;
unsigned long long bitlen;
WORD state[5];
WORD k[4];
} SHA1_CTX;
#define ROTLEFT(a, b) ((a << b) | (a >> (32 - b)))
#define SHA1_BLOCK_SIZE 20 // SHA1 outputs a 20 byte digest
#define PAGE_SIZE 4096
__device__ void sha1_init(SHA1_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen = 0;
ctx->state[0] = 0x67452301;
ctx->state[1] = 0xEFCDAB89;
ctx->state[2] = 0x98BADCFE;
ctx->state[3] = 0x10325476;
ctx->state[4] = 0xc3d2e1f0;
ctx->k[0] = 0x5a827999;
ctx->k[1] = 0x6ed9eba1;
ctx->k[2] = 0x8f1bbcdc;
ctx->k[3] = 0xca62c1d6;
}
__device__ void sha1_transform(SHA1_CTX *ctx, const BYTE data[])
{
WORD a, b, c, d, e, i, j, t, m[80];
for (i = 0, j = 0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) + (data[j + 1] << 16) + (data[j + 2] << 8) + (data[j + 3]);
for ( ; i < 80; ++i) {
m[i] = (m[i - 3] ^ m[i - 8] ^ m[i - 14] ^ m[i - 16]);
m[i] = (m[i] << 1) | (m[i] >> 31);
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
for (i = 0; i < 20; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (~b & d)) + e + ctx->k[0] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 40; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[1] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 60; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (b & d) ^ (c & d)) + e + ctx->k[2] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 80; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[3] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
}
__device__ void sha1_update(SHA1_CTX *ctx, const BYTE data[], size_t len)
{
size_t i;
for (i = 0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha1_transform(ctx, ctx->data);
ctx->bitlen += 512;
ctx->datalen = 0;
}
}
}
__device__ void sha1_final(SHA1_CTX *ctx, BYTE hash[])
{
WORD i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha1_transform(ctx, ctx->data);
while (i < 7)
ctx->data[i++] = 0x00;
}
// Append to the padding the total message's length in bits and transform.
ctx->bitlen += ctx->datalen * 8;
ctx->data[63] = ctx->bitlen;
ctx->data[62] = ctx->bitlen >> 8;
ctx->data[61] = ctx->bitlen >> 16;
ctx->data[60] = ctx->bitlen >> 24;
ctx->data[59] = ctx->bitlen >> 32;
ctx->data[58] = ctx->bitlen >> 40;
ctx->data[57] = ctx->bitlen >> 48;
ctx->data[56] = ctx->bitlen >> 56;
sha1_transform(ctx, ctx->data);
// Since this implementation uses little endian byte ordering and MD uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i = 0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
}
}
extern "C" __global__
void gpusha1(unsigned char* text1, unsigned char* hashval, int text_num) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
SHA1_CTX ctx;
unsigned char text_dev[PAGE_SIZE];
unsigned char hashval_dev[SHA1_BLOCK_SIZE];
int i;
if (thx < text_num) {
for (i = 0; i < PAGE_SIZE; ++i) {
text_dev[i] = text1[i + thx*PAGE_SIZE];
}
sha1_init(&ctx);
sha1_update(&ctx, text_dev, PAGE_SIZE);
sha1_final(&ctx, hashval_dev);
for (i = 0; i < SHA1_BLOCK_SIZE; ++i) {
hashval[i + thx*SHA1_BLOCK_SIZE] = hashval_dev[i];
}
}
} | #include <stdint.h>
#include <hip/hip_runtime.h>
typedef unsigned char BYTE; // 8-bit byte
typedef unsigned int WORD; // 32-bit word, change to "long" for 16-bit machines
typedef struct {
BYTE data[64];
WORD datalen;
unsigned long long bitlen;
WORD state[5];
WORD k[4];
} SHA1_CTX;
#define ROTLEFT(a, b) ((a << b) | (a >> (32 - b)))
#define SHA1_BLOCK_SIZE 20 // SHA1 outputs a 20 byte digest
#define PAGE_SIZE 4096
__device__ void sha1_init(SHA1_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen = 0;
ctx->state[0] = 0x67452301;
ctx->state[1] = 0xEFCDAB89;
ctx->state[2] = 0x98BADCFE;
ctx->state[3] = 0x10325476;
ctx->state[4] = 0xc3d2e1f0;
ctx->k[0] = 0x5a827999;
ctx->k[1] = 0x6ed9eba1;
ctx->k[2] = 0x8f1bbcdc;
ctx->k[3] = 0xca62c1d6;
}
__device__ void sha1_transform(SHA1_CTX *ctx, const BYTE data[])
{
WORD a, b, c, d, e, i, j, t, m[80];
for (i = 0, j = 0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) + (data[j + 1] << 16) + (data[j + 2] << 8) + (data[j + 3]);
for ( ; i < 80; ++i) {
m[i] = (m[i - 3] ^ m[i - 8] ^ m[i - 14] ^ m[i - 16]);
m[i] = (m[i] << 1) | (m[i] >> 31);
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
for (i = 0; i < 20; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (~b & d)) + e + ctx->k[0] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 40; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[1] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 60; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (b & d) ^ (c & d)) + e + ctx->k[2] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 80; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[3] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
}
__device__ void sha1_update(SHA1_CTX *ctx, const BYTE data[], size_t len)
{
size_t i;
for (i = 0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha1_transform(ctx, ctx->data);
ctx->bitlen += 512;
ctx->datalen = 0;
}
}
}
__device__ void sha1_final(SHA1_CTX *ctx, BYTE hash[])
{
WORD i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha1_transform(ctx, ctx->data);
while (i < 7)
ctx->data[i++] = 0x00;
}
// Append to the padding the total message's length in bits and transform.
ctx->bitlen += ctx->datalen * 8;
ctx->data[63] = ctx->bitlen;
ctx->data[62] = ctx->bitlen >> 8;
ctx->data[61] = ctx->bitlen >> 16;
ctx->data[60] = ctx->bitlen >> 24;
ctx->data[59] = ctx->bitlen >> 32;
ctx->data[58] = ctx->bitlen >> 40;
ctx->data[57] = ctx->bitlen >> 48;
ctx->data[56] = ctx->bitlen >> 56;
sha1_transform(ctx, ctx->data);
// Since this implementation uses little endian byte ordering and MD uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i = 0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
}
}
extern "C" __global__
void gpusha1(unsigned char* text1, unsigned char* hashval, int text_num) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
SHA1_CTX ctx;
unsigned char text_dev[PAGE_SIZE];
unsigned char hashval_dev[SHA1_BLOCK_SIZE];
int i;
if (thx < text_num) {
for (i = 0; i < PAGE_SIZE; ++i) {
text_dev[i] = text1[i + thx*PAGE_SIZE];
}
sha1_init(&ctx);
sha1_update(&ctx, text_dev, PAGE_SIZE);
sha1_final(&ctx, hashval_dev);
for (i = 0; i < SHA1_BLOCK_SIZE; ++i) {
hashval[i + thx*SHA1_BLOCK_SIZE] = hashval_dev[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdint.h>
#include <hip/hip_runtime.h>
typedef unsigned char BYTE; // 8-bit byte
typedef unsigned int WORD; // 32-bit word, change to "long" for 16-bit machines
typedef struct {
BYTE data[64];
WORD datalen;
unsigned long long bitlen;
WORD state[5];
WORD k[4];
} SHA1_CTX;
#define ROTLEFT(a, b) ((a << b) | (a >> (32 - b)))
#define SHA1_BLOCK_SIZE 20 // SHA1 outputs a 20 byte digest
#define PAGE_SIZE 4096
__device__ void sha1_init(SHA1_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen = 0;
ctx->state[0] = 0x67452301;
ctx->state[1] = 0xEFCDAB89;
ctx->state[2] = 0x98BADCFE;
ctx->state[3] = 0x10325476;
ctx->state[4] = 0xc3d2e1f0;
ctx->k[0] = 0x5a827999;
ctx->k[1] = 0x6ed9eba1;
ctx->k[2] = 0x8f1bbcdc;
ctx->k[3] = 0xca62c1d6;
}
__device__ void sha1_transform(SHA1_CTX *ctx, const BYTE data[])
{
WORD a, b, c, d, e, i, j, t, m[80];
for (i = 0, j = 0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) + (data[j + 1] << 16) + (data[j + 2] << 8) + (data[j + 3]);
for ( ; i < 80; ++i) {
m[i] = (m[i - 3] ^ m[i - 8] ^ m[i - 14] ^ m[i - 16]);
m[i] = (m[i] << 1) | (m[i] >> 31);
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
for (i = 0; i < 20; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (~b & d)) + e + ctx->k[0] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 40; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[1] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 60; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (b & d) ^ (c & d)) + e + ctx->k[2] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 80; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[3] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
}
__device__ void sha1_update(SHA1_CTX *ctx, const BYTE data[], size_t len)
{
size_t i;
for (i = 0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha1_transform(ctx, ctx->data);
ctx->bitlen += 512;
ctx->datalen = 0;
}
}
}
__device__ void sha1_final(SHA1_CTX *ctx, BYTE hash[])
{
WORD i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha1_transform(ctx, ctx->data);
while (i < 7)
ctx->data[i++] = 0x00;
}
// Append to the padding the total message's length in bits and transform.
ctx->bitlen += ctx->datalen * 8;
ctx->data[63] = ctx->bitlen;
ctx->data[62] = ctx->bitlen >> 8;
ctx->data[61] = ctx->bitlen >> 16;
ctx->data[60] = ctx->bitlen >> 24;
ctx->data[59] = ctx->bitlen >> 32;
ctx->data[58] = ctx->bitlen >> 40;
ctx->data[57] = ctx->bitlen >> 48;
ctx->data[56] = ctx->bitlen >> 56;
sha1_transform(ctx, ctx->data);
// Since this implementation uses little endian byte ordering and MD uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i = 0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
}
}
extern "C" __global__
void gpusha1(unsigned char* text1, unsigned char* hashval, int text_num) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
SHA1_CTX ctx;
unsigned char text_dev[PAGE_SIZE];
unsigned char hashval_dev[SHA1_BLOCK_SIZE];
int i;
if (thx < text_num) {
for (i = 0; i < PAGE_SIZE; ++i) {
text_dev[i] = text1[i + thx*PAGE_SIZE];
}
sha1_init(&ctx);
sha1_update(&ctx, text_dev, PAGE_SIZE);
sha1_final(&ctx, hashval_dev);
for (i = 0; i < SHA1_BLOCK_SIZE; ++i) {
hashval[i + thx*SHA1_BLOCK_SIZE] = hashval_dev[i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected gpusha1
.globl gpusha1
.p2align 8
.type gpusha1,@function
gpusha1:
s_clause 0x1
s_load_b32 s4, s[2:3], 0x24
s_load_b32 s5, s[2:3], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_57
s_load_b64 s[4:5], s[2:3], 0x0
v_lshlrev_b32_e32 v2, 12, v1
v_mov_b32_e32 v4, 0x1d0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_mov_b64 s[4:5], 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v2, s4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmpk_lg_i32 s4, 0x1000
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
scratch_store_b8 v4, v5, off
v_add_nc_u32_e32 v4, 1, v4
s_cbranch_scc1 .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0xefcdab89
v_mov_b32_e32 v4, 0x67452301
v_mov_b32_e32 v6, 0x98badcfe
v_mov_b32_e32 v7, 0x10325476
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v12, 0xca62c1d6
v_mov_b32_e32 v8, 0xc3d2e1f0
v_mov_b32_e32 v9, 0x5a827999
v_mov_b32_e32 v10, 0x6ed9eba1
s_clause 0x1
scratch_store_b32 off, v2, off offset:400
scratch_store_b64 off, v[2:3], off offset:408
v_dual_mov_b32 v2, 16 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v11, 0x8f1bbcdc
s_mov_b64 s[4:5], 0
s_clause 0x2
scratch_store_b128 off, v[4:7], off offset:416
scratch_store_b128 off, v[8:11], off offset:432
scratch_store_b32 off, v12, off offset:448
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[4:5], 0x1000
s_cbranch_scc0 .LBB0_19
.LBB0_5:
scratch_load_b32 v4, off, off offset:400
s_add_i32 s6, s4, 0x1d0
scratch_load_u8 v5, off, s6
s_mov_b32 s6, exec_lo
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v4, 0x150, v4
s_waitcnt vmcnt(0)
scratch_store_b8 v4, v5, off
scratch_load_b32 v4, off, off offset:400
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, 1, v4
scratch_store_b32 off, v4, off offset:400
v_cmpx_eq_u32_e32 64, v4
s_cbranch_execz .LBB0_4
s_mov_b32 s7, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s7, 0x150
scratch_load_b32 v4, off, s8
s_add_i32 s8, s7, 16
s_add_i32 s7, s7, 4
s_cmp_lg_u32 s7, 64
s_waitcnt vmcnt(0)
v_perm_b32 v4, 0, v4, 0x10203
scratch_store_b32 off, v4, s8
s_cbranch_scc1 .LBB0_7
s_mov_b32 s7, 0
.p2align 6
.LBB0_9:
v_readfirstlane_b32 s8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, s7
s_add_i32 s9, s8, 52
s_add_i32 s10, s8, 32
s_clause 0x1
scratch_load_b32 v4, off, s9
scratch_load_b32 v5, off, s10
s_add_i32 s10, s8, 8
s_add_i32 s9, s7, 16
s_clause 0x1
scratch_load_b32 v6, off, s10
scratch_load_b32 v7, off, s9
s_add_i32 s7, s7, 4
s_add_i32 s8, s8, 64
s_cmpk_lg_i32 s7, 0x100
s_waitcnt vmcnt(2)
v_xor_b32_e32 v4, v5, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v4, v4, v6, v7
v_alignbit_b32 v4, v4, v4, 31
scratch_store_b32 off, v4, s8
s_cbranch_scc1 .LBB0_9
s_clause 0x5
scratch_load_b32 v4, off, off offset:432
scratch_load_b32 v5, off, off offset:428
scratch_load_b32 v6, off, off offset:424
scratch_load_b32 v7, off, off offset:420
scratch_load_b32 v8, off, off offset:416
scratch_load_b32 v12, off, off offset:436
s_mov_b32 s7, 0
s_waitcnt vmcnt(4)
v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v16, v5
s_waitcnt vmcnt(2)
v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v7
s_waitcnt vmcnt(1)
v_mov_b32_e32 v11, v8
.p2align 6
.LBB0_11:
s_add_i32 s8, s7, 16
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v13, v16
scratch_load_b32 v17, off, s8
v_dual_mov_b32 v14, v10 :: v_dual_mov_b32 v9, v11
v_not_b32_e32 v10, v18
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v11, v15, v12
s_add_i32 s7, s7, 4
v_and_b32_e32 v15, v18, v14
v_alignbit_b32 v19, v9, v9, 27
v_and_b32_e32 v10, v13, v10
s_cmpk_eq_i32 s7, 0x50
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v11, v11, v15, v10
v_mov_b32_e32 v15, v16
v_alignbit_b32 v10, v18, v18, 2
v_mov_b32_e32 v16, v14
s_waitcnt vmcnt(0)
v_add3_u32 v11, v11, v19, v17
s_cbranch_scc0 .LBB0_11
scratch_load_b32 v16, off, off offset:440
s_movk_i32 s7, 0x50
.p2align 6
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s8, s7, 16
v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v15, v10
scratch_load_b32 v17, off, s8
v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v9, v11
s_add_i32 s7, s7, 4
v_mov_b32_e32 v14, v15
s_cmpk_eq_i32 s7, 0xa0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v15, v12, v18
v_alignbit_b32 v11, v9, v9, 27
s_waitcnt vmcnt(1)
v_add3_u32 v19, v13, v16, v10
v_mov_b32_e32 v13, v12
v_alignbit_b32 v10, v18, v18, 2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v11, v19, v11, v17
s_cbranch_scc0 .LBB0_13
scratch_load_b32 v16, off, off offset:444
s_movk_i32 s7, 0xa0
.p2align 6
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s8, s7, 16
v_dual_mov_b32 v14, v10 :: v_dual_mov_b32 v13, v15
scratch_load_b32 v17, off, s8
v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v9, v11
s_add_i32 s7, s7, 4
v_xor_b32_e32 v11, v14, v13
v_and_b32_e32 v18, v14, v13
s_cmpk_eq_i32 s7, 0xf0
v_alignbit_b32 v15, v9, v9, 27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_and_b32_e32 v11, v11, v10
v_alignbit_b32 v10, v10, v10, 2
s_waitcnt vmcnt(1)
v_add3_u32 v19, v12, v16, v15
v_mov_b32_e32 v12, v13
v_xor_b32_e32 v11, v11, v18
v_mov_b32_e32 v15, v14
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v11, v19, v11, v17
s_cbranch_scc0 .LBB0_15
scratch_load_b32 v12, off, off offset:448
s_movk_i32 s7, 0xf0
.p2align 6
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s7, 16
v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v15, v14
scratch_load_b32 v17, off, s8
v_dual_mov_b32 v16, v10 :: v_dual_mov_b32 v9, v11
s_add_i32 s7, s7, 4
s_cmpk_lg_i32 s7, 0x140
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v10, v16, v15, v18
v_alignbit_b32 v11, v9, v9, 27
v_mov_b32_e32 v14, v16
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v19, v13, v12, v10
v_mov_b32_e32 v13, v15
v_alignbit_b32 v10, v18, v18, 2
s_waitcnt vmcnt(0)
v_add3_u32 v11, v19, v11, v17
s_cbranch_scc1 .LBB0_17
scratch_load_b64 v[12:13], off, off offset:408
v_add_nc_u32_e32 v7, v9, v7
v_add_nc_u32_e32 v6, v10, v6
v_add_nc_u32_e32 v9, v16, v5
v_add_nc_u32_e32 v10, v15, v4
v_add_nc_u32_e32 v8, v11, v8
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v12, 0x200
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v13, vcc_lo
s_clause 0x6
scratch_store_b32 off, v7, off offset:420
scratch_store_b32 off, v6, off offset:424
scratch_store_b32 off, v9, off offset:428
scratch_store_b32 off, v10, off offset:432
scratch_store_b32 off, v8, off offset:416
scratch_store_b64 off, v[4:5], off offset:408
scratch_store_b32 off, v3, off offset:400
s_branch .LBB0_4
.LBB0_19:
scratch_load_b32 v2, off, off offset:400
v_mov_b32_e32 v4, 0x80
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x150, v2
scratch_store_b8 v3, v4, off
v_cmpx_lt_u32_e32 55, v2
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_36
v_add_nc_u32_e32 v3, 1, v2
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 64, v3
s_cbranch_execz .LBB0_23
v_or_b32_e64 v3, 0x150, 1
v_mov_b32_e32 v4, 0
s_mov_b32 s6, 0
.LBB0_22:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, v3, v2
v_add_nc_u32_e32 v2, 1, v2
scratch_store_b8 v5, v4, off
v_cmp_lt_u32_e32 vcc_lo, 62, v2
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_22
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s5, 0
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s5, 0x150
scratch_load_b32 v2, off, s6
s_add_i32 s6, s5, 16
s_add_i32 s5, s5, 4
s_cmp_lg_u32 s5, 64
s_waitcnt vmcnt(0)
v_perm_b32 v2, 0, v2, 0x10203
scratch_store_b32 off, v2, s6
s_cbranch_scc1 .LBB0_24
v_mov_b32_e32 v2, 16
s_mov_b32 s5, 0
.p2align 6
.LBB0_26:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v2
s_add_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s7, s6, 52
s_add_i32 s8, s6, 32
s_clause 0x1
scratch_load_b32 v3, off, s7
scratch_load_b32 v4, off, s8
s_add_i32 s8, s6, 8
s_add_i32 s7, s5, 16
s_clause 0x1
scratch_load_b32 v5, off, s8
scratch_load_b32 v6, off, s7
s_add_i32 s5, s5, 4
s_add_i32 s6, s6, 64
s_cmpk_lg_i32 s5, 0x100
s_waitcnt vmcnt(2)
v_xor_b32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v3, v3, v5, v6
v_alignbit_b32 v3, v3, v3, 31
scratch_store_b32 off, v3, s6
s_cbranch_scc1 .LBB0_26
s_clause 0x5
scratch_load_b32 v2, off, off offset:432
scratch_load_b32 v3, off, off offset:428
scratch_load_b32 v4, off, off offset:424
scratch_load_b32 v5, off, off offset:420
scratch_load_b32 v6, off, off offset:416
scratch_load_b32 v10, off, off offset:436
s_mov_b32 s5, 0
s_waitcnt vmcnt(4)
v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v14, v3
s_waitcnt vmcnt(2)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
v_mov_b32_e32 v9, v6
.p2align 6
.LBB0_28:
s_add_i32 s6, s5, 16
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v11, v14
scratch_load_b32 v15, off, s6
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v7, v9
v_not_b32_e32 v8, v16
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v9, v13, v10
s_add_i32 s5, s5, 4
v_and_b32_e32 v13, v16, v12
v_alignbit_b32 v17, v7, v7, 27
v_and_b32_e32 v8, v11, v8
s_cmpk_eq_i32 s5, 0x50
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v9, v9, v13, v8
v_mov_b32_e32 v13, v14
v_alignbit_b32 v8, v16, v16, 2
v_mov_b32_e32 v14, v12
s_waitcnt vmcnt(0)
v_add3_u32 v9, v9, v17, v15
s_cbranch_scc0 .LBB0_28
scratch_load_b32 v14, off, off offset:440
s_movk_i32 s5, 0x50
.p2align 6
.LBB0_30:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s5, 16
v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v13, v8
scratch_load_b32 v15, off, s6
v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v7, v9
s_add_i32 s5, s5, 4
v_mov_b32_e32 v12, v13
s_cmpk_eq_i32 s5, 0xa0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor3_b32 v8, v13, v10, v16
v_alignbit_b32 v9, v7, v7, 27
s_waitcnt vmcnt(1)
v_add3_u32 v17, v11, v14, v8
v_mov_b32_e32 v11, v10
v_alignbit_b32 v8, v16, v16, 2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v9, v17, v9, v15
s_cbranch_scc0 .LBB0_30
scratch_load_b32 v14, off, off offset:444
s_movk_i32 s5, 0xa0
.p2align 6
.LBB0_32:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s5, 16
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v13
scratch_load_b32 v15, off, s6
v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v7, v9
s_add_i32 s5, s5, 4
v_xor_b32_e32 v9, v12, v11
v_and_b32_e32 v16, v12, v11
s_cmpk_eq_i32 s5, 0xf0
v_alignbit_b32 v13, v7, v7, 27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_and_b32_e32 v9, v9, v8
v_alignbit_b32 v8, v8, v8, 2
s_waitcnt vmcnt(1)
v_add3_u32 v17, v10, v14, v13
v_mov_b32_e32 v10, v11
v_xor_b32_e32 v9, v9, v16
v_mov_b32_e32 v13, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v17, v9, v15
s_cbranch_scc0 .LBB0_32
scratch_load_b32 v10, off, off offset:448
s_movk_i32 s5, 0xf0
.p2align 6
.LBB0_34:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s5, 16
v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v13, v12
scratch_load_b32 v15, off, s6
v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v7, v9
s_add_i32 s5, s5, 4
s_cmpk_lg_i32 s5, 0x140
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v8, v14, v13, v16
v_alignbit_b32 v9, v7, v7, 27
v_mov_b32_e32 v12, v14
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v17, v11, v10, v8
v_mov_b32_e32 v11, v13
v_alignbit_b32 v8, v16, v16, 2
s_waitcnt vmcnt(0)
v_add3_u32 v9, v17, v9, v15
s_cbranch_scc1 .LBB0_34
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v6, v9, v6
v_add_nc_u32_e32 v5, v7, v5
v_add_nc_u32_e32 v4, v8, v4
v_add_nc_u32_e32 v3, v14, v3
v_add_nc_u32_e32 v2, v13, v2
s_clause 0x4
scratch_store_b32 off, v6, off offset:416
scratch_store_b32 off, v5, off offset:420
scratch_store_b32 off, v4, off offset:424
scratch_store_b32 off, v3, off offset:428
scratch_store_b32 off, v2, off offset:432
.LBB0_36:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_41
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 55, v2
s_cbranch_execz .LBB0_40
v_or_b32_e64 v3, 0x150, 1
v_mov_b32_e32 v4, 0
s_mov_b32 s6, 0
.LBB0_39:
v_add_nc_u32_e32 v5, 1, v2
v_cmp_lt_u32_e32 vcc_lo, 53, v2
v_add_nc_u32_e32 v6, v3, v2
s_delay_alu instid0(VALU_DEP_3)
v_mov_b32_e32 v2, v5
s_or_b32 s6, vcc_lo, s6
scratch_store_b8 v6, v4, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_39
.LBB0_40:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_41:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
scratch_load_b32 v4, off, off offset:400
scratch_load_b64 v[2:3], off, off offset:408
s_mov_b32 s4, 0
s_waitcnt vmcnt(1)
v_lshlrev_b32_e32 v4, 3, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_lshrrev_b32_e32 v4, 8, v2
v_lshrrev_b32_e32 v5, 24, v2
scratch_store_b64 off, v[2:3], off offset:408
v_lshrrev_b32_e32 v6, 8, v3
v_lshrrev_b32_e32 v7, 24, v3
s_clause 0x7
scratch_store_b8 off, v2, off offset:399
scratch_store_b8 off, v4, off offset:398
scratch_store_d16_hi_b8 off, v2, off offset:397
scratch_store_b8 off, v5, off offset:396
scratch_store_b8 off, v3, off offset:395
scratch_store_b8 off, v6, off offset:394
scratch_store_d16_hi_b8 off, v3, off offset:393
scratch_store_b8 off, v7, off offset:392
.LBB0_42:
s_add_i32 s5, s4, 0x150
scratch_load_b32 v2, off, s5
s_add_i32 s5, s4, 16
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 64
s_waitcnt vmcnt(0)
v_perm_b32 v2, 0, v2, 0x10203
scratch_store_b32 off, v2, s5
s_cbranch_scc1 .LBB0_42
v_mov_b32_e32 v2, 16
s_mov_b32 s4, 0
.p2align 6
.LBB0_44:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v2
s_add_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s5, 52
s_add_i32 s7, s5, 32
s_clause 0x1
scratch_load_b32 v3, off, s6
scratch_load_b32 v4, off, s7
s_add_i32 s7, s5, 8
s_add_i32 s6, s4, 16
s_clause 0x1
scratch_load_b32 v5, off, s7
scratch_load_b32 v6, off, s6
s_add_i32 s4, s4, 4
s_add_i32 s5, s5, 64
s_cmpk_lg_i32 s4, 0x100
s_waitcnt vmcnt(2)
v_xor_b32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v3, v3, v5, v6
v_alignbit_b32 v3, v3, v3, 31
scratch_store_b32 off, v3, s5
s_cbranch_scc1 .LBB0_44
s_clause 0x5
scratch_load_b32 v2, off, off offset:432
scratch_load_b32 v3, off, off offset:428
scratch_load_b32 v4, off, off offset:424
scratch_load_b32 v5, off, off offset:420
scratch_load_b32 v6, off, off offset:416
scratch_load_b32 v10, off, off offset:436
s_mov_b32 s4, 0
s_waitcnt vmcnt(4)
v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v14, v3
s_waitcnt vmcnt(2)
v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
v_mov_b32_e32 v9, v6
.p2align 6
.LBB0_46:
s_add_i32 s5, s4, 16
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v11, v14
scratch_load_b32 v15, off, s5
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v7, v9
v_not_b32_e32 v8, v16
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v9, v13, v10
s_add_i32 s4, s4, 4
v_and_b32_e32 v13, v16, v12
v_alignbit_b32 v17, v7, v7, 27
v_and_b32_e32 v8, v11, v8
s_cmpk_eq_i32 s4, 0x50
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v9, v9, v13, v8
v_mov_b32_e32 v13, v14
v_alignbit_b32 v8, v16, v16, 2
v_mov_b32_e32 v14, v12
s_waitcnt vmcnt(0)
v_add3_u32 v9, v9, v17, v15
s_cbranch_scc0 .LBB0_46
scratch_load_b32 v14, off, off offset:440
s_movk_i32 s4, 0x50
.p2align 6
.LBB0_48:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s5, s4, 16
v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v13, v8
scratch_load_b32 v15, off, s5
v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v7, v9
s_add_i32 s4, s4, 4
v_mov_b32_e32 v12, v13
s_cmpk_eq_i32 s4, 0xa0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor3_b32 v8, v13, v10, v16
v_alignbit_b32 v9, v7, v7, 27
s_waitcnt vmcnt(1)
v_add3_u32 v17, v11, v14, v8
v_mov_b32_e32 v11, v10
v_alignbit_b32 v8, v16, v16, 2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v9, v17, v9, v15
s_cbranch_scc0 .LBB0_48
scratch_load_b32 v14, off, off offset:444
s_movk_i32 s4, 0xa0
.p2align 6
.LBB0_50:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s5, s4, 16
v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v13
scratch_load_b32 v15, off, s5
v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v7, v9
s_add_i32 s4, s4, 4
v_xor_b32_e32 v9, v12, v11
v_and_b32_e32 v16, v12, v11
s_cmpk_eq_i32 s4, 0xf0
v_alignbit_b32 v13, v7, v7, 27
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_and_b32_e32 v9, v9, v8
v_alignbit_b32 v8, v8, v8, 2
s_waitcnt vmcnt(1)
v_add3_u32 v17, v10, v14, v13
v_mov_b32_e32 v10, v11
v_xor_b32_e32 v9, v9, v16
v_mov_b32_e32 v13, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v17, v9, v15
s_cbranch_scc0 .LBB0_50
scratch_load_b32 v10, off, off offset:448
s_movk_i32 s4, 0xf0
.p2align 6
.LBB0_52:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, 16
v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v13, v12
scratch_load_b32 v15, off, s5
v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v7, v9
s_add_i32 s4, s4, 4
s_cmpk_lg_i32 s4, 0x140
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor3_b32 v8, v14, v13, v16
v_alignbit_b32 v9, v7, v7, 27
v_mov_b32_e32 v12, v14
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add3_u32 v17, v11, v10, v8
v_mov_b32_e32 v11, v13
v_alignbit_b32 v8, v16, v16, 2
s_waitcnt vmcnt(0)
v_add3_u32 v9, v17, v9, v15
s_cbranch_scc1 .LBB0_52
s_load_b64 s[0:1], s[0:1], 0x4
v_and_b32_e32 v10, 0x3ff, v0
v_bfe_u32 v11, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
v_add_nc_u32_e32 v4, v8, v4
v_add_nc_u32_e32 v3, v14, v3
v_add_nc_u32_e32 v2, v13, v2
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
v_mul_u32_u24_e32 v11, s1, v11
s_mul_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, s0, v10
s_mov_b32 s0, 24
v_add3_u32 v0, v10, v11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v0, 20
v_add_nc_u32_e32 v0, v9, v6
v_dual_mov_b32 v6, v10 :: v_dual_add_nc_u32 v5, v7, v5
s_clause 0x4
scratch_store_b32 off, v0, off offset:416
scratch_store_b32 off, v5, off offset:420
scratch_store_b32 off, v4, off offset:424
scratch_store_b32 off, v3, off offset:428
scratch_store_b32 off, v2, off offset:432
.p2align 6
.LBB0_54:
v_lshrrev_b32_e32 v7, s0, v0
v_lshrrev_b32_e32 v8, s0, v5
v_lshrrev_b32_e32 v9, s0, v4
v_lshrrev_b32_e32 v11, s0, v3
v_lshrrev_b32_e32 v12, s0, v2
ds_store_b8 v6, v7
ds_store_b8 v6, v8 offset:4
ds_store_b8 v6, v9 offset:8
ds_store_b8 v6, v11 offset:12
ds_store_b8 v6, v12 offset:16
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s0, s0, -8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, -8
s_cbranch_scc1 .LBB0_54
s_load_b64 s[0:1], s[2:3], 0x8
v_mul_lo_u32 v0, v1, 20
v_mov_b32_e32 v2, 0xffffffec
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
.LBB0_56:
v_add_nc_u32_e32 v3, v10, v2
v_add_co_u32 v2, s0, v2, 1
ds_load_u8 v3, v3 offset:20
s_waitcnt lgkmcnt(0)
global_store_b8 v[0:1], v3, off
v_add_co_u32 v0, vcc_lo, v0, 1
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_56
.LBB0_57:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel gpusha1
.amdhsa_group_segment_fixed_size 20480
.amdhsa_private_segment_fixed_size 4560
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size gpusha1, .Lfunc_end0-gpusha1
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 20480
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: gpusha1
.private_segment_fixed_size: 4560
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: gpusha1.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdint.h>
#include <hip/hip_runtime.h>
typedef unsigned char BYTE; // 8-bit byte
typedef unsigned int WORD; // 32-bit word, change to "long" for 16-bit machines
typedef struct {
BYTE data[64];
WORD datalen;
unsigned long long bitlen;
WORD state[5];
WORD k[4];
} SHA1_CTX;
#define ROTLEFT(a, b) ((a << b) | (a >> (32 - b)))
#define SHA1_BLOCK_SIZE 20 // SHA1 outputs a 20 byte digest
#define PAGE_SIZE 4096
__device__ void sha1_init(SHA1_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen = 0;
ctx->state[0] = 0x67452301;
ctx->state[1] = 0xEFCDAB89;
ctx->state[2] = 0x98BADCFE;
ctx->state[3] = 0x10325476;
ctx->state[4] = 0xc3d2e1f0;
ctx->k[0] = 0x5a827999;
ctx->k[1] = 0x6ed9eba1;
ctx->k[2] = 0x8f1bbcdc;
ctx->k[3] = 0xca62c1d6;
}
__device__ void sha1_transform(SHA1_CTX *ctx, const BYTE data[])
{
WORD a, b, c, d, e, i, j, t, m[80];
for (i = 0, j = 0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) + (data[j + 1] << 16) + (data[j + 2] << 8) + (data[j + 3]);
for ( ; i < 80; ++i) {
m[i] = (m[i - 3] ^ m[i - 8] ^ m[i - 14] ^ m[i - 16]);
m[i] = (m[i] << 1) | (m[i] >> 31);
}
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
for (i = 0; i < 20; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (~b & d)) + e + ctx->k[0] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 40; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[1] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 60; ++i) {
t = ROTLEFT(a, 5) + ((b & c) ^ (b & d) ^ (c & d)) + e + ctx->k[2] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
for ( ; i < 80; ++i) {
t = ROTLEFT(a, 5) + (b ^ c ^ d) + e + ctx->k[3] + m[i];
e = d;
d = c;
c = ROTLEFT(b, 30);
b = a;
a = t;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
}
__device__ void sha1_update(SHA1_CTX *ctx, const BYTE data[], size_t len)
{
size_t i;
for (i = 0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha1_transform(ctx, ctx->data);
ctx->bitlen += 512;
ctx->datalen = 0;
}
}
}
__device__ void sha1_final(SHA1_CTX *ctx, BYTE hash[])
{
WORD i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha1_transform(ctx, ctx->data);
while (i < 7)
ctx->data[i++] = 0x00;
}
// Append to the padding the total message's length in bits and transform.
ctx->bitlen += ctx->datalen * 8;
ctx->data[63] = ctx->bitlen;
ctx->data[62] = ctx->bitlen >> 8;
ctx->data[61] = ctx->bitlen >> 16;
ctx->data[60] = ctx->bitlen >> 24;
ctx->data[59] = ctx->bitlen >> 32;
ctx->data[58] = ctx->bitlen >> 40;
ctx->data[57] = ctx->bitlen >> 48;
ctx->data[56] = ctx->bitlen >> 56;
sha1_transform(ctx, ctx->data);
// Since this implementation uses little endian byte ordering and MD uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i = 0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
}
}
extern "C" __global__
void gpusha1(unsigned char* text1, unsigned char* hashval, int text_num) {
int thx = blockIdx.x * blockDim.x + threadIdx.x;
SHA1_CTX ctx;
unsigned char text_dev[PAGE_SIZE];
unsigned char hashval_dev[SHA1_BLOCK_SIZE];
int i;
if (thx < text_num) {
for (i = 0; i < PAGE_SIZE; ++i) {
text_dev[i] = text1[i + thx*PAGE_SIZE];
}
sha1_init(&ctx);
sha1_update(&ctx, text_dev, PAGE_SIZE);
sha1_final(&ctx, hashval_dev);
for (i = 0; i < SHA1_BLOCK_SIZE; ++i) {
hashval[i + thx*SHA1_BLOCK_SIZE] = hashval_dev[i];
}
}
} | .text
.file "gpusha1cuda_test.hip"
.globl __device_stub__gpusha1 # -- Begin function __device_stub__gpusha1
.p2align 4, 0x90
.type __device_stub__gpusha1,@function
__device_stub__gpusha1: # @__device_stub__gpusha1
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gpusha1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__gpusha1, .Lfunc_end0-__device_stub__gpusha1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gpusha1, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gpusha1,@object # @gpusha1
.section .rodata,"a",@progbits
.globl gpusha1
.p2align 3, 0x0
gpusha1:
.quad __device_stub__gpusha1
.size gpusha1, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gpusha1"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gpusha1
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gpusha1
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004bd29_00000000-6_gpusha1cuda_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9sha1_initP8SHA1_CTX
.type _Z9sha1_initP8SHA1_CTX, @function
_Z9sha1_initP8SHA1_CTX:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9sha1_initP8SHA1_CTX, .-_Z9sha1_initP8SHA1_CTX
.globl _Z14sha1_transformP8SHA1_CTXPKh
.type _Z14sha1_transformP8SHA1_CTXPKh, @function
_Z14sha1_transformP8SHA1_CTXPKh:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z14sha1_transformP8SHA1_CTXPKh, .-_Z14sha1_transformP8SHA1_CTXPKh
.globl _Z11sha1_updateP8SHA1_CTXPKhm
.type _Z11sha1_updateP8SHA1_CTXPKhm, @function
_Z11sha1_updateP8SHA1_CTXPKhm:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z11sha1_updateP8SHA1_CTXPKhm, .-_Z11sha1_updateP8SHA1_CTXPKhm
.globl _Z10sha1_finalP8SHA1_CTXPh
.type _Z10sha1_finalP8SHA1_CTXPh, @function
_Z10sha1_finalP8SHA1_CTXPh:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z10sha1_finalP8SHA1_CTXPh, .-_Z10sha1_finalP8SHA1_CTXPh
.globl _Z29__device_stub__Z7gpusha1PhS_iPhS_i
.type _Z29__device_stub__Z7gpusha1PhS_iPhS_i, @function
_Z29__device_stub__Z7gpusha1PhS_iPhS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq gpusha1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z7gpusha1PhS_iPhS_i, .-_Z29__device_stub__Z7gpusha1PhS_iPhS_i
.globl gpusha1
.type gpusha1, @function
gpusha1:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7gpusha1PhS_iPhS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size gpusha1, .-gpusha1
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "gpusha1"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq gpusha1(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpusha1cuda_test.hip"
.globl __device_stub__gpusha1 # -- Begin function __device_stub__gpusha1
.p2align 4, 0x90
.type __device_stub__gpusha1,@function
__device_stub__gpusha1: # @__device_stub__gpusha1
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $gpusha1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__gpusha1, .Lfunc_end0-__device_stub__gpusha1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $gpusha1, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type gpusha1,@object # @gpusha1
.section .rodata,"a",@progbits
.globl gpusha1
.p2align 3, 0x0
gpusha1:
.quad __device_stub__gpusha1
.size gpusha1, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "gpusha1"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__gpusha1
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym gpusha1
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__device__
int MAP_MP(int n){
return n*(n-1)/2;
}
__device__
void LISprintMP(char* mat,int tam){
int i, j;
int pos = 0;
for(i = 1 ; i<tam+1 ; i++){
for(j = 0; j < i; j++, pos++){
printf("%d |",mat[pos]);
}
printf("\n");
//if(mat[i]== -1){
// break;
//}
//else
// printf("%d -",mat[i]);
}
printf("\n");
}
//pega o menor valor do vetor last que seja maior do que x
__device__
char LISgetLast(char* last,char x,int tam){
int i;
for(i=0; i < tam ;i++){
if(last[i] > x ){
return i+1;
}
}
//Nunca deve chegar aqui
return 0;
}
//pega a posicao valida para inserir um elemento no vetor vet
__device__
int LISgetPos(char vet[],int tam){
int i;
for(i =0;i < tam;i++){
if(vet[i] == -1){
return i;
}
}
return -1;
}
//copia um vetor para outro
__device__
void LISVetCopy(char* dest, char* in,int tam){
for(int i = 0; i<tam-1;i++){
dest[i] = in[i];
}
dest[tam-1] = -1;
}
__device__
unsigned char LIS(char* vet, char* last, char* MP, int tam){
//inicializa o vetor com os ultimos elementos de MP
for(int i =0;i<tam;i++){
last[i] = 127;
}
char lmax = 1; //maior tamanho de subsequencia
for(int i = 1, pos = 0;i <= tam; i++){
for(int j = 0; j < i; j++, pos++){
MP[pos] = -1;
}
}
MP[0] = vet[0];
last[0] = vet[0];
for(int i=1; i < tam; i++){
int l = LISgetLast(last,vet[i],tam); //pega valor de l
//atualiza o valor de lmax
if(l > lmax){
lmax ++;
}
last[l-1] = vet[i]; //atualiza o vetor last
//concatena os vetores de MP
LISVetCopy(MP+l,MP+l-1,l);
int pos = LISgetPos(MP+l,tam);
MP[l+pos] = last[l-1];
//LISprintMP(MP, tam);
}
return lmax;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__device__
int MAP_MP(int n){
return n*(n-1)/2;
}
__device__
void LISprintMP(char* mat,int tam){
int i, j;
int pos = 0;
for(i = 1 ; i<tam+1 ; i++){
for(j = 0; j < i; j++, pos++){
printf("%d |",mat[pos]);
}
printf("\n");
//if(mat[i]== -1){
// break;
//}
//else
// printf("%d -",mat[i]);
}
printf("\n");
}
//pega o menor valor do vetor last que seja maior do que x
__device__
char LISgetLast(char* last,char x,int tam){
int i;
for(i=0; i < tam ;i++){
if(last[i] > x ){
return i+1;
}
}
//Nunca deve chegar aqui
return 0;
}
//pega a posicao valida para inserir um elemento no vetor vet
__device__
int LISgetPos(char vet[],int tam){
int i;
for(i =0;i < tam;i++){
if(vet[i] == -1){
return i;
}
}
return -1;
}
//copia um vetor para outro
__device__
void LISVetCopy(char* dest, char* in,int tam){
for(int i = 0; i<tam-1;i++){
dest[i] = in[i];
}
dest[tam-1] = -1;
}
__device__
unsigned char LIS(char* vet, char* last, char* MP, int tam){
//inicializa o vetor com os ultimos elementos de MP
for(int i =0;i<tam;i++){
last[i] = 127;
}
char lmax = 1; //maior tamanho de subsequencia
for(int i = 1, pos = 0;i <= tam; i++){
for(int j = 0; j < i; j++, pos++){
MP[pos] = -1;
}
}
MP[0] = vet[0];
last[0] = vet[0];
for(int i=1; i < tam; i++){
int l = LISgetLast(last,vet[i],tam); //pega valor de l
//atualiza o valor de lmax
if(l > lmax){
lmax ++;
}
last[l-1] = vet[i]; //atualiza o vetor last
//concatena os vetores de MP
LISVetCopy(MP+l,MP+l-1,l);
int pos = LISgetPos(MP+l,tam);
MP[l+pos] = last[l-1];
//LISprintMP(MP, tam);
}
return lmax;
} | .file "tmpxft_0018de99_00000000-6_LIS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6MAP_MPi
.type _Z6MAP_MPi, @function
_Z6MAP_MPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6MAP_MPi, .-_Z6MAP_MPi
.globl _Z10LISprintMPPci
.type _Z10LISprintMPPci, @function
_Z10LISprintMPPci:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10LISprintMPPci, .-_Z10LISprintMPPci
.globl _Z10LISgetLastPcci
.type _Z10LISgetLastPcci, @function
_Z10LISgetLastPcci:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10LISgetLastPcci, .-_Z10LISgetLastPcci
.globl _Z9LISgetPosPci
.type _Z9LISgetPosPci, @function
_Z9LISgetPosPci:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z9LISgetPosPci, .-_Z9LISgetPosPci
.globl _Z10LISVetCopyPcS_i
.type _Z10LISVetCopyPcS_i, @function
_Z10LISVetCopyPcS_i:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z10LISVetCopyPcS_i, .-_Z10LISVetCopyPcS_i
.globl _Z3LISPcS_S_i
.type _Z3LISPcS_S_i, @function
_Z3LISPcS_S_i:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z3LISPcS_S_i, .-_Z3LISPcS_S_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__device__
int MAP_MP(int n){
return n*(n-1)/2;
}
__device__
void LISprintMP(char* mat,int tam){
int i, j;
int pos = 0;
for(i = 1 ; i<tam+1 ; i++){
for(j = 0; j < i; j++, pos++){
printf("%d |",mat[pos]);
}
printf("\n");
//if(mat[i]== -1){
// break;
//}
//else
// printf("%d -",mat[i]);
}
printf("\n");
}
//pega o menor valor do vetor last que seja maior do que x
__device__
char LISgetLast(char* last,char x,int tam){
int i;
for(i=0; i < tam ;i++){
if(last[i] > x ){
return i+1;
}
}
//Nunca deve chegar aqui
return 0;
}
//pega a posicao valida para inserir um elemento no vetor vet
__device__
int LISgetPos(char vet[],int tam){
int i;
for(i =0;i < tam;i++){
if(vet[i] == -1){
return i;
}
}
return -1;
}
//copia um vetor para outro
__device__
void LISVetCopy(char* dest, char* in,int tam){
for(int i = 0; i<tam-1;i++){
dest[i] = in[i];
}
dest[tam-1] = -1;
}
__device__
unsigned char LIS(char* vet, char* last, char* MP, int tam){
//inicializa o vetor com os ultimos elementos de MP
for(int i =0;i<tam;i++){
last[i] = 127;
}
char lmax = 1; //maior tamanho de subsequencia
for(int i = 1, pos = 0;i <= tam; i++){
for(int j = 0; j < i; j++, pos++){
MP[pos] = -1;
}
}
MP[0] = vet[0];
last[0] = vet[0];
for(int i=1; i < tam; i++){
int l = LISgetLast(last,vet[i],tam); //pega valor de l
//atualiza o valor de lmax
if(l > lmax){
lmax ++;
}
last[l-1] = vet[i]; //atualiza o vetor last
//concatena os vetores de MP
LISVetCopy(MP+l,MP+l-1,l);
int pos = LISgetPos(MP+l,tam);
MP[l+pos] = last[l-1];
//LISprintMP(MP, tam);
}
return lmax;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__
int MAP_MP(int n){
return n*(n-1)/2;
}
__device__
void LISprintMP(char* mat,int tam){
int i, j;
int pos = 0;
for(i = 1 ; i<tam+1 ; i++){
for(j = 0; j < i; j++, pos++){
printf("%d |",mat[pos]);
}
printf("\n");
//if(mat[i]== -1){
// break;
//}
//else
// printf("%d -",mat[i]);
}
printf("\n");
}
//pega o menor valor do vetor last que seja maior do que x
__device__
char LISgetLast(char* last,char x,int tam){
int i;
for(i=0; i < tam ;i++){
if(last[i] > x ){
return i+1;
}
}
//Nunca deve chegar aqui
return 0;
}
//pega a posicao valida para inserir um elemento no vetor vet
__device__
int LISgetPos(char vet[],int tam){
int i;
for(i =0;i < tam;i++){
if(vet[i] == -1){
return i;
}
}
return -1;
}
//copia um vetor para outro
__device__
void LISVetCopy(char* dest, char* in,int tam){
for(int i = 0; i<tam-1;i++){
dest[i] = in[i];
}
dest[tam-1] = -1;
}
__device__
unsigned char LIS(char* vet, char* last, char* MP, int tam){
//inicializa o vetor com os ultimos elementos de MP
for(int i =0;i<tam;i++){
last[i] = 127;
}
char lmax = 1; //maior tamanho de subsequencia
for(int i = 1, pos = 0;i <= tam; i++){
for(int j = 0; j < i; j++, pos++){
MP[pos] = -1;
}
}
MP[0] = vet[0];
last[0] = vet[0];
for(int i=1; i < tam; i++){
int l = LISgetLast(last,vet[i],tam); //pega valor de l
//atualiza o valor de lmax
if(l > lmax){
lmax ++;
}
last[l-1] = vet[i]; //atualiza o vetor last
//concatena os vetores de MP
LISVetCopy(MP+l,MP+l-1,l);
int pos = LISgetPos(MP+l,tam);
MP[l+pos] = last[l-1];
//LISprintMP(MP, tam);
}
return lmax;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__
int MAP_MP(int n){
return n*(n-1)/2;
}
__device__
void LISprintMP(char* mat,int tam){
int i, j;
int pos = 0;
for(i = 1 ; i<tam+1 ; i++){
for(j = 0; j < i; j++, pos++){
printf("%d |",mat[pos]);
}
printf("\n");
//if(mat[i]== -1){
// break;
//}
//else
// printf("%d -",mat[i]);
}
printf("\n");
}
//pega o menor valor do vetor last que seja maior do que x
__device__
char LISgetLast(char* last,char x,int tam){
int i;
for(i=0; i < tam ;i++){
if(last[i] > x ){
return i+1;
}
}
//Nunca deve chegar aqui
return 0;
}
//pega a posicao valida para inserir um elemento no vetor vet
__device__
int LISgetPos(char vet[],int tam){
int i;
for(i =0;i < tam;i++){
if(vet[i] == -1){
return i;
}
}
return -1;
}
//copia um vetor para outro
__device__
void LISVetCopy(char* dest, char* in,int tam){
for(int i = 0; i<tam-1;i++){
dest[i] = in[i];
}
dest[tam-1] = -1;
}
__device__
unsigned char LIS(char* vet, char* last, char* MP, int tam){
//inicializa o vetor com os ultimos elementos de MP
for(int i =0;i<tam;i++){
last[i] = 127;
}
char lmax = 1; //maior tamanho de subsequencia
for(int i = 1, pos = 0;i <= tam; i++){
for(int j = 0; j < i; j++, pos++){
MP[pos] = -1;
}
}
MP[0] = vet[0];
last[0] = vet[0];
for(int i=1; i < tam; i++){
int l = LISgetLast(last,vet[i],tam); //pega valor de l
//atualiza o valor de lmax
if(l > lmax){
lmax ++;
}
last[l-1] = vet[i]; //atualiza o vetor last
//concatena os vetores de MP
LISVetCopy(MP+l,MP+l-1,l);
int pos = LISgetPos(MP+l,tam);
MP[l+pos] = last[l-1];
//LISprintMP(MP, tam);
}
return lmax;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__device__
int MAP_MP(int n){
return n*(n-1)/2;
}
__device__
void LISprintMP(char* mat,int tam){
int i, j;
int pos = 0;
for(i = 1 ; i<tam+1 ; i++){
for(j = 0; j < i; j++, pos++){
printf("%d |",mat[pos]);
}
printf("\n");
//if(mat[i]== -1){
// break;
//}
//else
// printf("%d -",mat[i]);
}
printf("\n");
}
//pega o menor valor do vetor last que seja maior do que x
__device__
char LISgetLast(char* last,char x,int tam){
int i;
for(i=0; i < tam ;i++){
if(last[i] > x ){
return i+1;
}
}
//Nunca deve chegar aqui
return 0;
}
//pega a posicao valida para inserir um elemento no vetor vet
__device__
int LISgetPos(char vet[],int tam){
int i;
for(i =0;i < tam;i++){
if(vet[i] == -1){
return i;
}
}
return -1;
}
//copia um vetor para outro
__device__
void LISVetCopy(char* dest, char* in,int tam){
for(int i = 0; i<tam-1;i++){
dest[i] = in[i];
}
dest[tam-1] = -1;
}
__device__
unsigned char LIS(char* vet, char* last, char* MP, int tam){
//inicializa o vetor com os ultimos elementos de MP
for(int i =0;i<tam;i++){
last[i] = 127;
}
char lmax = 1; //maior tamanho de subsequencia
for(int i = 1, pos = 0;i <= tam; i++){
for(int j = 0; j < i; j++, pos++){
MP[pos] = -1;
}
}
MP[0] = vet[0];
last[0] = vet[0];
for(int i=1; i < tam; i++){
int l = LISgetLast(last,vet[i],tam); //pega valor de l
//atualiza o valor de lmax
if(l > lmax){
lmax ++;
}
last[l-1] = vet[i]; //atualiza o vetor last
//concatena os vetores de MP
LISVetCopy(MP+l,MP+l-1,l);
int pos = LISgetPos(MP+l,tam);
MP[l+pos] = last[l-1];
//LISprintMP(MP, tam);
}
return lmax;
} | .text
.file "LIS.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018de99_00000000-6_LIS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6MAP_MPi
.type _Z6MAP_MPi, @function
_Z6MAP_MPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6MAP_MPi, .-_Z6MAP_MPi
.globl _Z10LISprintMPPci
.type _Z10LISprintMPPci, @function
_Z10LISprintMPPci:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z10LISprintMPPci, .-_Z10LISprintMPPci
.globl _Z10LISgetLastPcci
.type _Z10LISgetLastPcci, @function
_Z10LISgetLastPcci:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10LISgetLastPcci, .-_Z10LISgetLastPcci
.globl _Z9LISgetPosPci
.type _Z9LISgetPosPci, @function
_Z9LISgetPosPci:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z9LISgetPosPci, .-_Z9LISgetPosPci
.globl _Z10LISVetCopyPcS_i
.type _Z10LISVetCopyPcS_i, @function
_Z10LISVetCopyPcS_i:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z10LISVetCopyPcS_i, .-_Z10LISVetCopyPcS_i
.globl _Z3LISPcS_S_i
.type _Z3LISPcS_S_i, @function
_Z3LISPcS_S_i:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z3LISPcS_S_i, .-_Z3LISPcS_S_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LIS.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#include <cuda.h>
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
ui origSize, TgtSize;
ui xshrink, yshrink;
ui origVpixels, origHpixels, origHbytes;
uch *TheImage, *NewImage; // Where images are stored in CPU
uch *GPUSrcImage, *GPUTgtImage, *GPUResult; // Where images are stored in GPU
struct ImgProp{
int Hpixels;
int Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
*(int*)&ip.HeaderInfo[2] = ip.Hbytes*ip.Vpixels+54;
*(int*)&ip.HeaderInfo[18] = ip.Hpixels;
*(int*)&ip.HeaderInfo[22] = ip.Vpixels;
*(int*)&ip.HeaderInfo[34] = ip.Hbytes*ip.Vpixels;
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u\n\n", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
__global__
void ImShrunk(uch *TgtImg, uch *SrcImg, ui TgtHpixels, ui xshrink, ui yshrink, ui origHpixels, ui origHbytes)
{
ui ThrPerBlk = blockDim.x;
ui TgtBid = blockIdx.x;
ui TgtTid = threadIdx.x;
ui TgtGtid = ThrPerBlk * TgtBid + TgtTid;
ui BlkPerRow = (TgtHpixels + ThrPerBlk - 1) / ThrPerBlk; // ceil
ui TgtRowBytes = (TgtHpixels * 3 + 3) & (~3);
// ui SrcRowBytes = (origHpixels * 3 + 3) & (~3);
ui SrcRowBytes = origHbytes;
ui Tgtrow = TgtBid / BlkPerRow;
ui TgtCol = TgtGtid - Tgtrow*BlkPerRow*ThrPerBlk;
if(TgtCol >= TgtHpixels) return;
ui SrcRow = Tgtrow * yshrink;
ui SrcCol = TgtCol * xshrink;
// if(SrcCol >= origHpixels) return;
///////////////
ui TgtOffset = Tgtrow * TgtRowBytes;
ui SrcOffset = SrcRow * SrcRowBytes;
ui TgtIndex = TgtOffset + 3*TgtCol;
ui SrcIndex = SrcOffset + 3*SrcCol;
TgtImg[TgtIndex] = SrcImg[SrcIndex];
TgtImg[TgtIndex+1] = SrcImg[SrcIndex+1];
TgtImg[TgtIndex+2] = SrcImg[SrcIndex+2];
}
int main(int argc, char** argv){
float totalTime, tfrCPUtoGPU, tfrGPUtoCPU, kernelExecutionTime; // GPU code run times
cudaError_t cudaStatus, cudaStatus2;
cudaEvent_t time1, time2, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks, GPUDataTransfer;
cudaDeviceProp GPUprop;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imShrunk");
if(argc!=5){
printf("\n\nUsage: imshrunk input output xshrink yshrink");
return 0;
}
xshrink = atoi(argv[3]);
yshrink = atoi(argv[4]);
strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
TheImage = ReadBMPlin(argv[1]);
if (TheImage == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
origHpixels = ip.Hpixels;
origVpixels = ip.Vpixels;
origHbytes = ip.Hbytes;
origSize = origHbytes * origVpixels;
ip.Hpixels = ip.Hpixels/xshrink;
ip.Hbytes = (ip.Hpixels*3 + 3) & (~3);
ip.Vpixels = ip.Vpixels/yshrink;
// TgtSize = ip.Hbytes * ip.Vpixels;
// printf("\n new Hpixels %u", ip.Hpixels);
// printf("\n new Vpixels %u", ip.Vpixels);
NewImage = (uch *)malloc(IMAGESIZE);
if (NewImage == NULL){
free(NewImage);
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
cudaGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
exit(EXIT_FAILURE);
}
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
exit(EXIT_FAILURE);
}
cudaGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
cudaEventCreate(&time1);
cudaEventCreate(&time2);
cudaEventCreate(&time3);
cudaEventCreate(&time4);
cudaEventRecord(time1, 0);
// allocate GPU buffer
cudaStatus = cudaMalloc((void**)&GPUSrcImage, origSize);
cudaStatus2 = cudaMalloc((void**)&GPUTgtImage, IMAGESIZE);
if ((cudaStatus != cudaSuccess) || (cudaStatus2 != cudaSuccess)){
fprintf(stderr, "cudaMalloc failed! Can't allocate GPU memory");
exit(EXIT_FAILURE);
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(GPUSrcImage, TheImage, origSize, cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy CPU to GPU failed!");
exit(EXIT_FAILURE);
}
cudaEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
BlkPerRow = (IPH + ThrPerBlk -1 ) / ThrPerBlk;
NumBlocks = IPV*BlkPerRow;
ImShrunk <<< NumBlocks, ThrPerBlk>>> (GPUTgtImage, GPUSrcImage, IPH, xshrink, yshrink, origHpixels, origHbytes);
GPUResult = GPUTgtImage;
GPUDataTransfer = origSize + IMAGESIZE;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n\ncudaDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
exit(EXIT_FAILURE);
}
cudaEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = cudaMemcpy(NewImage, GPUResult, IMAGESIZE, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy GPU to CPU failed!");
exit(EXIT_FAILURE);
}
cudaEventRecord(time4, 0);
cudaEventSynchronize(time1);
cudaEventSynchronize(time2);
cudaEventSynchronize(time3);
cudaEventSynchronize(time4);
cudaEventElapsedTime(&totalTime, time1, time4);
cudaEventElapsedTime(&tfrCPUtoGPU, time1, time2);
cudaEventElapsedTime(&kernelExecutionTime, time2, time3);
cudaEventElapsedTime(&tfrGPUtoCPU, time3, time4);
cudaStatus = cudaDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
WriteBMPlin(NewImage, argv[2]); // Write the flipped image back to disk
////////////////// change from here
printf("\n\n--------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("--------------------------------------------------------------------------\n");
printf("%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
ThrPerBlk, NumBlocks, BlkPerRow);
printf("--------------------------------------------------------------------------\n");
printf("CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(origSize), DATABW(origSize, tfrCPUtoGPU));
printf("Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecutionTime, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));
printf("GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("--------------------------------------------------------------------------\n");
printf("Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n", totalTime, DATAMB((origSize + IMAGESIZE + GPUDataTransfer)), DATABW((origSize + IMAGESIZE+ GPUDataTransfer), totalTime));
printf("--------------------------------------------------------------------------\n\n");
// Deallocate CPU, GPU memory and destroy events.
cudaFree(GPUSrcImage);
cudaFree(GPUTgtImage);
cudaEventDestroy(time1);
cudaEventDestroy(time2);
cudaEventDestroy(time3);
cudaEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
free(TheImage);
free(NewImage);
return(EXIT_SUCCESS);
} | code for sm_80
Function : _Z8ImShrunkPhS_jjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e660000002500 */
/*0050*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0060*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x004fc800078e0a03 */
/*00c0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0100*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff05aa12 */
/* 0x000fc800078e33ff */
/*0170*/ I2F.U32.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209000 */
/*0180*/ ISETP.NE.U32.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f45070 */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fe40007ffe0ff */
/*01b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0004e4000021f000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x004fc400078e00ff */
/*01e0*/ IMAD R4, R5, R3, RZ ; /* 0x0000000305047224 */
/* 0x008fc800078e02ff */
/*01f0*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a04 */
/*0200*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0210*/ IMAD.HI.U32 R4, R3, UR4, RZ ; /* 0x0000000403047c27 */
/* 0x002fc8000f8e00ff */
/*0220*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R6, R5, R6, UR4 ; /* 0x0000000405067e24 */
/* 0x000fca000f8e0206 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R6, -R5, R6, RZ ; /* 0x0000000605060210 */
/* 0x000fe40007ffe1ff */
/*0260*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fda0003f26070 */
/*0280*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0290*/ @!P2 LOP3.LUT R4, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff04a212 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a04 */
/*02b0*/ IMAD R5, R5, R2, UR4 ; /* 0x0000000405057e24 */
/* 0x000fc8000f8e0202 */
/*02c0*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02f0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0300*/ IMAD R5, R5, 0x3, RZ ; /* 0x0000000305057824 */
/* 0x000fe200078e02ff */
/*0310*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0320*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0330*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0340*/ IMAD R0, R4, UR4, RZ ; /* 0x0000000404007c24 */
/* 0x000fc8000f8e02ff */
/*0350*/ IMAD R8, R5, c[0x0][0x174], R0 ; /* 0x00005d0005087a24 */
/* 0x000fca00078e0200 */
/*0360*/ IADD3 R2, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008027a10 */
/* 0x000fca0007f1e0ff */
/*0370*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0380*/ LDG.E.U8 R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea2000c1e1100 */
/*0390*/ UMOV UR4, 0x3 ; /* 0x0000000300047882 */
/* 0x000fe20000000000 */
/*03a0*/ IADD3 R6, R8, 0x1, RZ ; /* 0x0000000108067810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*03c0*/ UIMAD UR4, UR4, UR5, UR4 ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e0204 */
/*03d0*/ IADD3 R6, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc60007f3e0ff */
/*03e0*/ ULOP3.LUT UR4, UR4, 0xfffffffc, URZ, 0xc0, !UPT ; /* 0xfffffffc04047892 */
/* 0x000fe4000f8ec03f */
/*03f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff077624 */
/* 0x000fc800008e06ff */
/*0400*/ IMAD R0, R4, UR4, R5 ; /* 0x0000000404007c24 */
/* 0x000fca000f8e0205 */
/*0410*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fca0007f1e0ff */
/*0420*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0430*/ STG.E.U8 [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101106 */
/*0440*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1100 */
/*0450*/ IADD3 R8, R8, 0x2, RZ ; /* 0x0000000208087810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007f3e0ff */
/*0480*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc60007f1e0ff */
/*0490*/ IMAD.X R9, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff097624 */
/* 0x000fe200008e06ff */
/*04a0*/ IADD3.X R3, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff037a10 */
/* 0x000fe400007fe4ff */
/*04b0*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe8000c101106 */
/*04d0*/ LDG.E.U8 R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea2000c1e1100 */
/*04e0*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x001fca0007f1e0ff */
/*04f0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0500*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe2000c101106 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#include <cuda.h>
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
ui origSize, TgtSize;
ui xshrink, yshrink;
ui origVpixels, origHpixels, origHbytes;
uch *TheImage, *NewImage; // Where images are stored in CPU
uch *GPUSrcImage, *GPUTgtImage, *GPUResult; // Where images are stored in GPU
struct ImgProp{
int Hpixels;
int Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
*(int*)&ip.HeaderInfo[2] = ip.Hbytes*ip.Vpixels+54;
*(int*)&ip.HeaderInfo[18] = ip.Hpixels;
*(int*)&ip.HeaderInfo[22] = ip.Vpixels;
*(int*)&ip.HeaderInfo[34] = ip.Hbytes*ip.Vpixels;
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u\n\n", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
__global__
void ImShrunk(uch *TgtImg, uch *SrcImg, ui TgtHpixels, ui xshrink, ui yshrink, ui origHpixels, ui origHbytes)
{
ui ThrPerBlk = blockDim.x;
ui TgtBid = blockIdx.x;
ui TgtTid = threadIdx.x;
ui TgtGtid = ThrPerBlk * TgtBid + TgtTid;
ui BlkPerRow = (TgtHpixels + ThrPerBlk - 1) / ThrPerBlk; // ceil
ui TgtRowBytes = (TgtHpixels * 3 + 3) & (~3);
// ui SrcRowBytes = (origHpixels * 3 + 3) & (~3);
ui SrcRowBytes = origHbytes;
ui Tgtrow = TgtBid / BlkPerRow;
ui TgtCol = TgtGtid - Tgtrow*BlkPerRow*ThrPerBlk;
if(TgtCol >= TgtHpixels) return;
ui SrcRow = Tgtrow * yshrink;
ui SrcCol = TgtCol * xshrink;
// if(SrcCol >= origHpixels) return;
///////////////
ui TgtOffset = Tgtrow * TgtRowBytes;
ui SrcOffset = SrcRow * SrcRowBytes;
ui TgtIndex = TgtOffset + 3*TgtCol;
ui SrcIndex = SrcOffset + 3*SrcCol;
TgtImg[TgtIndex] = SrcImg[SrcIndex];
TgtImg[TgtIndex+1] = SrcImg[SrcIndex+1];
TgtImg[TgtIndex+2] = SrcImg[SrcIndex+2];
}
int main(int argc, char** argv){
float totalTime, tfrCPUtoGPU, tfrGPUtoCPU, kernelExecutionTime; // GPU code run times
cudaError_t cudaStatus, cudaStatus2;
cudaEvent_t time1, time2, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks, GPUDataTransfer;
cudaDeviceProp GPUprop;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imShrunk");
if(argc!=5){
printf("\n\nUsage: imshrunk input output xshrink yshrink");
return 0;
}
xshrink = atoi(argv[3]);
yshrink = atoi(argv[4]);
strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
TheImage = ReadBMPlin(argv[1]);
if (TheImage == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
origHpixels = ip.Hpixels;
origVpixels = ip.Vpixels;
origHbytes = ip.Hbytes;
origSize = origHbytes * origVpixels;
ip.Hpixels = ip.Hpixels/xshrink;
ip.Hbytes = (ip.Hpixels*3 + 3) & (~3);
ip.Vpixels = ip.Vpixels/yshrink;
// TgtSize = ip.Hbytes * ip.Vpixels;
// printf("\n new Hpixels %u", ip.Hpixels);
// printf("\n new Vpixels %u", ip.Vpixels);
NewImage = (uch *)malloc(IMAGESIZE);
if (NewImage == NULL){
free(NewImage);
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
cudaGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
exit(EXIT_FAILURE);
}
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
exit(EXIT_FAILURE);
}
cudaGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
cudaEventCreate(&time1);
cudaEventCreate(&time2);
cudaEventCreate(&time3);
cudaEventCreate(&time4);
cudaEventRecord(time1, 0);
// allocate GPU buffer
cudaStatus = cudaMalloc((void**)&GPUSrcImage, origSize);
cudaStatus2 = cudaMalloc((void**)&GPUTgtImage, IMAGESIZE);
if ((cudaStatus != cudaSuccess) || (cudaStatus2 != cudaSuccess)){
fprintf(stderr, "cudaMalloc failed! Can't allocate GPU memory");
exit(EXIT_FAILURE);
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(GPUSrcImage, TheImage, origSize, cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy CPU to GPU failed!");
exit(EXIT_FAILURE);
}
cudaEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
BlkPerRow = (IPH + ThrPerBlk -1 ) / ThrPerBlk;
NumBlocks = IPV*BlkPerRow;
ImShrunk <<< NumBlocks, ThrPerBlk>>> (GPUTgtImage, GPUSrcImage, IPH, xshrink, yshrink, origHpixels, origHbytes);
GPUResult = GPUTgtImage;
GPUDataTransfer = origSize + IMAGESIZE;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n\ncudaDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
exit(EXIT_FAILURE);
}
cudaEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = cudaMemcpy(NewImage, GPUResult, IMAGESIZE, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy GPU to CPU failed!");
exit(EXIT_FAILURE);
}
cudaEventRecord(time4, 0);
cudaEventSynchronize(time1);
cudaEventSynchronize(time2);
cudaEventSynchronize(time3);
cudaEventSynchronize(time4);
cudaEventElapsedTime(&totalTime, time1, time4);
cudaEventElapsedTime(&tfrCPUtoGPU, time1, time2);
cudaEventElapsedTime(&kernelExecutionTime, time2, time3);
cudaEventElapsedTime(&tfrGPUtoCPU, time3, time4);
cudaStatus = cudaDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
WriteBMPlin(NewImage, argv[2]); // Write the flipped image back to disk
////////////////// change from here
printf("\n\n--------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("--------------------------------------------------------------------------\n");
printf("%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
ThrPerBlk, NumBlocks, BlkPerRow);
printf("--------------------------------------------------------------------------\n");
printf("CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(origSize), DATABW(origSize, tfrCPUtoGPU));
printf("Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecutionTime, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));
printf("GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("--------------------------------------------------------------------------\n");
printf("Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n", totalTime, DATAMB((origSize + IMAGESIZE + GPUDataTransfer)), DATABW((origSize + IMAGESIZE+ GPUDataTransfer), totalTime));
printf("--------------------------------------------------------------------------\n\n");
// Deallocate CPU, GPU memory and destroy events.
cudaFree(GPUSrcImage);
cudaFree(GPUTgtImage);
cudaEventDestroy(time1);
cudaEventDestroy(time2);
cudaEventDestroy(time3);
cudaEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
free(TheImage);
free(NewImage);
return(EXIT_SUCCESS);
} | .file "tmpxft_0004d691_00000000-6_imshrunkG.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "\n\n%s NOT FOUND\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n Input File name: %17s (%u x %u) File Size=%u"
.text
.globl _Z10ReadBMPlinPc
.type _Z10ReadBMPlinPc, @function
_Z10ReadBMPlinPc:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L8
movq %rax, %rbx
movq %rsp, %rdi
movq %rax, %r8
movl $54, %ecx
movl $1, %edx
movl $54, %esi
call __fread_chk@PLT
movl 18(%rsp), %ecx
movl %ecx, ip(%rip)
movl 22(%rsp), %r8d
movl %r8d, 4+ip(%rip)
leal 3(%rcx,%rcx,2), %eax
andl $-4, %eax
cltq
movq %rax, 64+ip(%rip)
movdqa (%rsp), %xmm0
movups %xmm0, 8+ip(%rip)
movdqa 16(%rsp), %xmm1
movups %xmm1, 24+ip(%rip)
movdqa 32(%rsp), %xmm2
movups %xmm2, 40+ip(%rip)
movq 46(%rsp), %rdx
movq %rdx, 54+ip(%rip)
movslq %r8d, %r9
imulq %rax, %r9
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 4+ip(%rip), %rbp
imulq 64+ip(%rip), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, _ZZ10ReadBMPlinPcE3Img(%rip)
testq %rax, %rax
je .L3
movq %rbx, %r8
movq %rbp, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq _ZZ10ReadBMPlinPcE3Img(%rip), %rax
.L3:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movq %rbp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10ReadBMPlinPc, .-_Z10ReadBMPlinPc
.section .rodata.str1.1
.LC3:
.string "wb"
.LC4:
.string "\n\nFILE CREATION ERROR: %s\n\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "\nOutput File name: %17s (%u x %u) File Size=%u\n\n"
.text
.globl _Z11WriteBMPlinPhPc
.type _Z11WriteBMPlinPhPc, @function
_Z11WriteBMPlinPhPc:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
testq %rax, %rax
je .L13
movq %rax, %rbx
movl 4+ip(%rip), %edx
movl %edx, %eax
imull 64+ip(%rip), %eax
leal 54(%rax), %ecx
movl %ecx, 10+ip(%rip)
movl ip(%rip), %ecx
movl %ecx, 26+ip(%rip)
movl %edx, 30+ip(%rip)
movl %eax, 42+ip(%rip)
movq %rbx, %rcx
movl $54, %edx
movl $1, %esi
leaq 8+ip(%rip), %rdi
call fwrite@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
movq %rbx, %rcx
movl $1, %esi
movq %r12, %rdi
call fwrite@PLT
movl 4+ip(%rip), %r8d
movslq %r8d, %r9
imulq 64+ip(%rip), %r9
movl ip(%rip), %ecx
movq %rbp, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z11WriteBMPlinPhPc, .-_Z11WriteBMPlinPhPc
.globl _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
.type _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj, @function
_Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj:
.LFB3696:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8ImShrunkPhS_jjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj, .-_Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
.globl _Z8ImShrunkPhS_jjjjj
.type _Z8ImShrunkPhS_jjjjj, @function
_Z8ImShrunkPhS_jjjjj:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8ImShrunkPhS_jjjjj, .-_Z8ImShrunkPhS_jjjjj
.section .rodata.str1.8
.align 8
.LC6:
.string "\n\nUsage: imshrunk input output xshrink yshrink"
.align 8
.LC7:
.string "Cannot allocate memory for the input image...\n"
.section .rodata.str1.1
.LC8:
.string "\nNo CUDA Device is available\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC10:
.string "%u %c"
.section .rodata.str1.8
.align 8
.LC11:
.string "cudaMalloc failed! Can't allocate GPU memory"
.align 8
.LC12:
.string "cudaMemcpy CPU to GPU failed!"
.align 8
.LC13:
.string "\n\ncudaDeviceSynchronize returned error code %d after launching the kernel!\n"
.align 8
.LC14:
.string "cudaMemcpy GPU to CPU failed!"
.align 8
.LC15:
.string "\n Program failed after cudaDeviceSynchronize()!"
.align 8
.LC16:
.string "\n\n--------------------------------------------------------------------------\n"
.align 8
.LC17:
.string "%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n"
.align 8
.LC18:
.string "--------------------------------------------------------------------------\n"
.align 8
.LC19:
.string "%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n"
.align 8
.LC22:
.string "CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.align 8
.LC23:
.string "Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.align 8
.LC24:
.string "GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.align 8
.LC25:
.string "Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n"
.align 8
.LC26:
.string "--------------------------------------------------------------------------\n\n"
.section .rodata.str1.1
.LC27:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $2016, %rsp
.cfi_def_cfa_offset 2064
movq %fs:40, %rax
movq %rax, 2008(%rsp)
xorl %eax, %eax
movabsq $7741253943733480809, %rax
movq %rax, 1744(%rsp)
movb $0, 1752(%rsp)
cmpl $5, %edi
je .L23
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movq 2008(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $2016, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, xshrink(%rip)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, yshrink(%rip)
movq 8(%rbx), %rbp
leaq 1232(%rsp), %rdi
movl $255, %edx
movq %rbp, %rsi
call __strcpy_chk@PLT
movq 16(%rbx), %rsi
leaq 1488(%rsp), %rdi
movl $255, %edx
call __strcpy_chk@PLT
movq %rbp, %rdi
call _Z10ReadBMPlinPc
movq %rax, TheImage(%rip)
testq %rax, %rax
je .L49
movl ip(%rip), %eax
movl %eax, origHpixels(%rip)
movl 4+ip(%rip), %edi
movl %edi, origVpixels(%rip)
movq 64+ip(%rip), %rdx
movl %edx, origHbytes(%rip)
imull %edi, %edx
movl %edx, origSize(%rip)
movl $0, %edx
divl xshrink(%rip)
movl %eax, ip(%rip)
leal 1(%rax), %ecx
imull $3, %ecx, %ecx
andl $-4, %ecx
movslq %ecx, %rcx
movq %rcx, 64+ip(%rip)
movl %edi, %eax
movl $0, %edx
divl yshrink(%rip)
movl %eax, 4+ip(%rip)
movslq %eax, %rdi
imulq %rcx, %rdi
call malloc@PLT
movq %rax, NewImage(%rip)
testq %rax, %rax
je .L50
movl $0, 20(%rsp)
leaq 20(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 20(%rsp)
je .L51
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L52
leaq 80(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %eax
imull 420(%rsp), %eax
imull 424(%rsp), %eax
shrl $10, %eax
movl %eax, %r8d
movl $75, %r9d
cmpl $5119, %eax
jbe .L29
shrq $10, %r8
movl $77, %r9d
.L29:
leaq 1120(%rsp), %rdi
leaq .LC10(%rip), %rcx
movl $100, %edx
movl $2, %esi
movl $0, %eax
call __sprintf_chk@PLT
movl 400(%rsp), %r13d
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl origSize(%rip), %esi
leaq GPUSrcImage(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ebp
movslq 4+ip(%rip), %rsi
imulq 64+ip(%rip), %rsi
leaq GPUTgtImage(%rip), %rdi
call cudaMalloc@PLT
orl %ebp, %eax
jne .L53
movl origSize(%rip), %edx
movl $1, %ecx
movq TheImage(%rip), %rsi
movq GPUSrcImage(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L54
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl ip(%rip), %eax
leal 255(%rax), %r12d
shrl $8, %r12d
movl %r12d, %r14d
imull 4+ip(%rip), %r14d
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L32:
movq GPUTgtImage(%rip), %rax
movq %rax, GPUResult(%rip)
movl 4+ip(%rip), %ebp
imull 64+ip(%rip), %ebp
addl origSize(%rip), %ebp
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L56
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
movl $2, %ecx
movq GPUResult(%rip), %rsi
movq NewImage(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L57
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 16(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 68(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 56(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L58
movq 16(%rbx), %rsi
movq NewImage(%rip), %rdi
call _Z11WriteBMPlinPhPc
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 2072
pushq %r13
.cfi_def_cfa_offset 2080
leaq 1136(%rsp), %r9
movl 460(%rsp), %r8d
movl 456(%rsp), %ecx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 2064
leaq .LC18(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1232(%rsp), %rcx
leaq 1744(%rsp), %rdx
pushq %r12
.cfi_def_cfa_offset 2072
pushq %r14
.cfi_def_cfa_offset 2080
movl $256, %r9d
leaq 1504(%rsp), %r8
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 2064
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl origSize(%rip), %edx
pxor %xmm2, %xmm2
cvtss2sd 16(%rsp), %xmm2
movl %edx, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
shrl $20, %edx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm2, %xmm2
cvtss2sd 68(%rsp), %xmm2
movl %ebp, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
movl %ebp, %edx
shrl $20, %edx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
pxor %xmm2, %xmm2
cvtss2sd 56(%rsp), %xmm2
testq %rdx, %rdx
js .L40
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
.L41:
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
shrq $20, %rdx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
movl origSize(%rip), %eax
addq %rax, %rdx
movl %ebp, %ebp
pxor %xmm2, %xmm2
cvtss2sd 12(%rsp), %xmm2
addq %rbp, %rdx
js .L42
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
.L43:
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
shrq $20, %rdx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq GPUSrcImage(%rip), %rdi
call cudaFree@PLT
movq GPUTgtImage(%rip), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L59
movq TheImage(%rip), %rdi
call free@PLT
movq NewImage(%rip), %rdi
call free@PLT
jmp .L24
.L49:
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
subq $8, %rsp
.cfi_def_cfa_offset 2072
movl origHbytes(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 2080
movl origHpixels(%rip), %r9d
movl yshrink(%rip), %r8d
movl xshrink(%rip), %ecx
movl ip(%rip), %edx
movq GPUSrcImage(%rip), %rsi
movq GPUTgtImage(%rip), %rdi
call _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
addq $16, %rsp
.cfi_def_cfa_offset 2064
jmp .L32
.L56:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq TheImage(%rip), %rdi
call free@PLT
movq NewImage(%rip), %rdi
call free@PLT
movl $1, %edi
call exit@PLT
.L40:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L41
.L42:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L43
.L59:
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq TheImage(%rip), %rdi
call free@PLT
movq NewImage(%rip), %rdi
call free@PLT
movl $1, %edi
call exit@PLT
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z8ImShrunkPhS_jjjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z8ImShrunkPhS_jjjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ10ReadBMPlinPcE3Img
.comm _ZZ10ReadBMPlinPcE3Img,8,8
.globl ip
.bss
.align 32
.type ip, @object
.size ip, 72
ip:
.zero 72
.globl GPUResult
.align 8
.type GPUResult, @object
.size GPUResult, 8
GPUResult:
.zero 8
.globl GPUTgtImage
.align 8
.type GPUTgtImage, @object
.size GPUTgtImage, 8
GPUTgtImage:
.zero 8
.globl GPUSrcImage
.align 8
.type GPUSrcImage, @object
.size GPUSrcImage, 8
GPUSrcImage:
.zero 8
.globl NewImage
.align 8
.type NewImage, @object
.size NewImage, 8
NewImage:
.zero 8
.globl TheImage
.align 8
.type TheImage, @object
.size TheImage, 8
TheImage:
.zero 8
.globl origHbytes
.align 4
.type origHbytes, @object
.size origHbytes, 4
origHbytes:
.zero 4
.globl origHpixels
.align 4
.type origHpixels, @object
.size origHpixels, 4
origHpixels:
.zero 4
.globl origVpixels
.align 4
.type origVpixels, @object
.size origVpixels, 4
origVpixels:
.zero 4
.globl yshrink
.align 4
.type yshrink, @object
.size yshrink, 4
yshrink:
.zero 4
.globl xshrink
.align 4
.type xshrink, @object
.size xshrink, 4
xshrink:
.zero 4
.globl TgtSize
.align 4
.type TgtSize, @object
.size TgtSize, 4
TgtSize:
.zero 4
.globl origSize
.align 4
.type origSize, @object
.size origSize, 4
origSize:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC20:
.long -755914244
.long 1072718413
.align 8
.LC21:
.long 0
.long 1083179008
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#include <cuda.h>
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
ui origSize, TgtSize;
ui xshrink, yshrink;
ui origVpixels, origHpixels, origHbytes;
uch *TheImage, *NewImage; // Where images are stored in CPU
uch *GPUSrcImage, *GPUTgtImage, *GPUResult; // Where images are stored in GPU
struct ImgProp{
int Hpixels;
int Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
*(int*)&ip.HeaderInfo[2] = ip.Hbytes*ip.Vpixels+54;
*(int*)&ip.HeaderInfo[18] = ip.Hpixels;
*(int*)&ip.HeaderInfo[22] = ip.Vpixels;
*(int*)&ip.HeaderInfo[34] = ip.Hbytes*ip.Vpixels;
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u\n\n", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
__global__
void ImShrunk(uch *TgtImg, uch *SrcImg, ui TgtHpixels, ui xshrink, ui yshrink, ui origHpixels, ui origHbytes)
{
ui ThrPerBlk = blockDim.x;
ui TgtBid = blockIdx.x;
ui TgtTid = threadIdx.x;
ui TgtGtid = ThrPerBlk * TgtBid + TgtTid;
ui BlkPerRow = (TgtHpixels + ThrPerBlk - 1) / ThrPerBlk; // ceil
ui TgtRowBytes = (TgtHpixels * 3 + 3) & (~3);
// ui SrcRowBytes = (origHpixels * 3 + 3) & (~3);
ui SrcRowBytes = origHbytes;
ui Tgtrow = TgtBid / BlkPerRow;
ui TgtCol = TgtGtid - Tgtrow*BlkPerRow*ThrPerBlk;
if(TgtCol >= TgtHpixels) return;
ui SrcRow = Tgtrow * yshrink;
ui SrcCol = TgtCol * xshrink;
// if(SrcCol >= origHpixels) return;
///////////////
ui TgtOffset = Tgtrow * TgtRowBytes;
ui SrcOffset = SrcRow * SrcRowBytes;
ui TgtIndex = TgtOffset + 3*TgtCol;
ui SrcIndex = SrcOffset + 3*SrcCol;
TgtImg[TgtIndex] = SrcImg[SrcIndex];
TgtImg[TgtIndex+1] = SrcImg[SrcIndex+1];
TgtImg[TgtIndex+2] = SrcImg[SrcIndex+2];
}
int main(int argc, char** argv){
float totalTime, tfrCPUtoGPU, tfrGPUtoCPU, kernelExecutionTime; // GPU code run times
cudaError_t cudaStatus, cudaStatus2;
cudaEvent_t time1, time2, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks, GPUDataTransfer;
cudaDeviceProp GPUprop;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imShrunk");
if(argc!=5){
printf("\n\nUsage: imshrunk input output xshrink yshrink");
return 0;
}
xshrink = atoi(argv[3]);
yshrink = atoi(argv[4]);
strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
TheImage = ReadBMPlin(argv[1]);
if (TheImage == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
origHpixels = ip.Hpixels;
origVpixels = ip.Vpixels;
origHbytes = ip.Hbytes;
origSize = origHbytes * origVpixels;
ip.Hpixels = ip.Hpixels/xshrink;
ip.Hbytes = (ip.Hpixels*3 + 3) & (~3);
ip.Vpixels = ip.Vpixels/yshrink;
// TgtSize = ip.Hbytes * ip.Vpixels;
// printf("\n new Hpixels %u", ip.Hpixels);
// printf("\n new Vpixels %u", ip.Vpixels);
NewImage = (uch *)malloc(IMAGESIZE);
if (NewImage == NULL){
free(NewImage);
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
cudaGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
exit(EXIT_FAILURE);
}
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
exit(EXIT_FAILURE);
}
cudaGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
cudaEventCreate(&time1);
cudaEventCreate(&time2);
cudaEventCreate(&time3);
cudaEventCreate(&time4);
cudaEventRecord(time1, 0);
// allocate GPU buffer
cudaStatus = cudaMalloc((void**)&GPUSrcImage, origSize);
cudaStatus2 = cudaMalloc((void**)&GPUTgtImage, IMAGESIZE);
if ((cudaStatus != cudaSuccess) || (cudaStatus2 != cudaSuccess)){
fprintf(stderr, "cudaMalloc failed! Can't allocate GPU memory");
exit(EXIT_FAILURE);
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(GPUSrcImage, TheImage, origSize, cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy CPU to GPU failed!");
exit(EXIT_FAILURE);
}
cudaEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
BlkPerRow = (IPH + ThrPerBlk -1 ) / ThrPerBlk;
NumBlocks = IPV*BlkPerRow;
ImShrunk <<< NumBlocks, ThrPerBlk>>> (GPUTgtImage, GPUSrcImage, IPH, xshrink, yshrink, origHpixels, origHbytes);
GPUResult = GPUTgtImage;
GPUDataTransfer = origSize + IMAGESIZE;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n\ncudaDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
exit(EXIT_FAILURE);
}
cudaEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = cudaMemcpy(NewImage, GPUResult, IMAGESIZE, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy GPU to CPU failed!");
exit(EXIT_FAILURE);
}
cudaEventRecord(time4, 0);
cudaEventSynchronize(time1);
cudaEventSynchronize(time2);
cudaEventSynchronize(time3);
cudaEventSynchronize(time4);
cudaEventElapsedTime(&totalTime, time1, time4);
cudaEventElapsedTime(&tfrCPUtoGPU, time1, time2);
cudaEventElapsedTime(&kernelExecutionTime, time2, time3);
cudaEventElapsedTime(&tfrGPUtoCPU, time3, time4);
cudaStatus = cudaDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
WriteBMPlin(NewImage, argv[2]); // Write the flipped image back to disk
////////////////// change from here
printf("\n\n--------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("--------------------------------------------------------------------------\n");
printf("%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
ThrPerBlk, NumBlocks, BlkPerRow);
printf("--------------------------------------------------------------------------\n");
printf("CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(origSize), DATABW(origSize, tfrCPUtoGPU));
printf("Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecutionTime, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));
printf("GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("--------------------------------------------------------------------------\n");
printf("Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n", totalTime, DATAMB((origSize + IMAGESIZE + GPUDataTransfer)), DATABW((origSize + IMAGESIZE+ GPUDataTransfer), totalTime));
printf("--------------------------------------------------------------------------\n\n");
// Deallocate CPU, GPU memory and destroy events.
cudaFree(GPUSrcImage);
cudaFree(GPUTgtImage);
cudaEventDestroy(time1);
cudaEventDestroy(time2);
cudaEventDestroy(time3);
cudaEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
free(TheImage);
free(NewImage);
return(EXIT_SUCCESS);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
ui origSize, TgtSize;
ui xshrink, yshrink;
ui origVpixels, origHpixels, origHbytes;
uch *TheImage, *NewImage; // Where images are stored in CPU
uch *GPUSrcImage, *GPUTgtImage, *GPUResult; // Where images are stored in GPU
struct ImgProp{
int Hpixels;
int Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
*(int*)&ip.HeaderInfo[2] = ip.Hbytes*ip.Vpixels+54;
*(int*)&ip.HeaderInfo[18] = ip.Hpixels;
*(int*)&ip.HeaderInfo[22] = ip.Vpixels;
*(int*)&ip.HeaderInfo[34] = ip.Hbytes*ip.Vpixels;
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u\n\n", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
__global__
void ImShrunk(uch *TgtImg, uch *SrcImg, ui TgtHpixels, ui xshrink, ui yshrink, ui origHpixels, ui origHbytes)
{
ui ThrPerBlk = blockDim.x;
ui TgtBid = blockIdx.x;
ui TgtTid = threadIdx.x;
ui TgtGtid = ThrPerBlk * TgtBid + TgtTid;
ui BlkPerRow = (TgtHpixels + ThrPerBlk - 1) / ThrPerBlk; // ceil
ui TgtRowBytes = (TgtHpixels * 3 + 3) & (~3);
// ui SrcRowBytes = (origHpixels * 3 + 3) & (~3);
ui SrcRowBytes = origHbytes;
ui Tgtrow = TgtBid / BlkPerRow;
ui TgtCol = TgtGtid - Tgtrow*BlkPerRow*ThrPerBlk;
if(TgtCol >= TgtHpixels) return;
ui SrcRow = Tgtrow * yshrink;
ui SrcCol = TgtCol * xshrink;
// if(SrcCol >= origHpixels) return;
///////////////
ui TgtOffset = Tgtrow * TgtRowBytes;
ui SrcOffset = SrcRow * SrcRowBytes;
ui TgtIndex = TgtOffset + 3*TgtCol;
ui SrcIndex = SrcOffset + 3*SrcCol;
TgtImg[TgtIndex] = SrcImg[SrcIndex];
TgtImg[TgtIndex+1] = SrcImg[SrcIndex+1];
TgtImg[TgtIndex+2] = SrcImg[SrcIndex+2];
}
int main(int argc, char** argv){
float totalTime, tfrCPUtoGPU, tfrGPUtoCPU, kernelExecutionTime; // GPU code run times
hipError_t cudaStatus, cudaStatus2;
hipEvent_t time1, time2, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks, GPUDataTransfer;
hipDeviceProp_t GPUprop;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imShrunk");
if(argc!=5){
printf("\n\nUsage: imshrunk input output xshrink yshrink");
return 0;
}
xshrink = atoi(argv[3]);
yshrink = atoi(argv[4]);
strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
TheImage = ReadBMPlin(argv[1]);
if (TheImage == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
origHpixels = ip.Hpixels;
origVpixels = ip.Vpixels;
origHbytes = ip.Hbytes;
origSize = origHbytes * origVpixels;
ip.Hpixels = ip.Hpixels/xshrink;
ip.Hbytes = (ip.Hpixels*3 + 3) & (~3);
ip.Vpixels = ip.Vpixels/yshrink;
// TgtSize = ip.Hbytes * ip.Vpixels;
// printf("\n new Hpixels %u", ip.Hpixels);
// printf("\n new Vpixels %u", ip.Vpixels);
NewImage = (uch *)malloc(IMAGESIZE);
if (NewImage == NULL){
free(NewImage);
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
hipGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
exit(EXIT_FAILURE);
}
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
exit(EXIT_FAILURE);
}
hipGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
hipEventCreate(&time1);
hipEventCreate(&time2);
hipEventCreate(&time3);
hipEventCreate(&time4);
hipEventRecord(time1, 0);
// allocate GPU buffer
cudaStatus = hipMalloc((void**)&GPUSrcImage, origSize);
cudaStatus2 = hipMalloc((void**)&GPUTgtImage, IMAGESIZE);
if ((cudaStatus != hipSuccess) || (cudaStatus2 != hipSuccess)){
fprintf(stderr, "hipMalloc failed! Can't allocate GPU memory");
exit(EXIT_FAILURE);
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(GPUSrcImage, TheImage, origSize, hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy CPU to GPU failed!");
exit(EXIT_FAILURE);
}
hipEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
BlkPerRow = (IPH + ThrPerBlk -1 ) / ThrPerBlk;
NumBlocks = IPV*BlkPerRow;
ImShrunk <<< NumBlocks, ThrPerBlk>>> (GPUTgtImage, GPUSrcImage, IPH, xshrink, yshrink, origHpixels, origHbytes);
GPUResult = GPUTgtImage;
GPUDataTransfer = origSize + IMAGESIZE;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n\nhipDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
exit(EXIT_FAILURE);
}
hipEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = hipMemcpy(NewImage, GPUResult, IMAGESIZE, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy GPU to CPU failed!");
exit(EXIT_FAILURE);
}
hipEventRecord(time4, 0);
hipEventSynchronize(time1);
hipEventSynchronize(time2);
hipEventSynchronize(time3);
hipEventSynchronize(time4);
hipEventElapsedTime(&totalTime, time1, time4);
hipEventElapsedTime(&tfrCPUtoGPU, time1, time2);
hipEventElapsedTime(&kernelExecutionTime, time2, time3);
hipEventElapsedTime(&tfrGPUtoCPU, time3, time4);
cudaStatus = hipDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
WriteBMPlin(NewImage, argv[2]); // Write the flipped image back to disk
////////////////// change from here
printf("\n\n--------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("--------------------------------------------------------------------------\n");
printf("%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
ThrPerBlk, NumBlocks, BlkPerRow);
printf("--------------------------------------------------------------------------\n");
printf("CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(origSize), DATABW(origSize, tfrCPUtoGPU));
printf("Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecutionTime, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));
printf("GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("--------------------------------------------------------------------------\n");
printf("Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n", totalTime, DATAMB((origSize + IMAGESIZE + GPUDataTransfer)), DATABW((origSize + IMAGESIZE+ GPUDataTransfer), totalTime));
printf("--------------------------------------------------------------------------\n\n");
// Deallocate CPU, GPU memory and destroy events.
hipFree(GPUSrcImage);
hipFree(GPUTgtImage);
hipEventDestroy(time1);
hipEventDestroy(time2);
hipEventDestroy(time3);
hipEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
free(TheImage);
free(NewImage);
return(EXIT_SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
ui origSize, TgtSize;
ui xshrink, yshrink;
ui origVpixels, origHpixels, origHbytes;
uch *TheImage, *NewImage; // Where images are stored in CPU
uch *GPUSrcImage, *GPUTgtImage, *GPUResult; // Where images are stored in GPU
struct ImgProp{
int Hpixels;
int Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
*(int*)&ip.HeaderInfo[2] = ip.Hbytes*ip.Vpixels+54;
*(int*)&ip.HeaderInfo[18] = ip.Hpixels;
*(int*)&ip.HeaderInfo[22] = ip.Vpixels;
*(int*)&ip.HeaderInfo[34] = ip.Hbytes*ip.Vpixels;
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u\n\n", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
__global__
void ImShrunk(uch *TgtImg, uch *SrcImg, ui TgtHpixels, ui xshrink, ui yshrink, ui origHpixels, ui origHbytes)
{
ui ThrPerBlk = blockDim.x;
ui TgtBid = blockIdx.x;
ui TgtTid = threadIdx.x;
ui TgtGtid = ThrPerBlk * TgtBid + TgtTid;
ui BlkPerRow = (TgtHpixels + ThrPerBlk - 1) / ThrPerBlk; // ceil
ui TgtRowBytes = (TgtHpixels * 3 + 3) & (~3);
// ui SrcRowBytes = (origHpixels * 3 + 3) & (~3);
ui SrcRowBytes = origHbytes;
ui Tgtrow = TgtBid / BlkPerRow;
ui TgtCol = TgtGtid - Tgtrow*BlkPerRow*ThrPerBlk;
if(TgtCol >= TgtHpixels) return;
ui SrcRow = Tgtrow * yshrink;
ui SrcCol = TgtCol * xshrink;
// if(SrcCol >= origHpixels) return;
///////////////
ui TgtOffset = Tgtrow * TgtRowBytes;
ui SrcOffset = SrcRow * SrcRowBytes;
ui TgtIndex = TgtOffset + 3*TgtCol;
ui SrcIndex = SrcOffset + 3*SrcCol;
TgtImg[TgtIndex] = SrcImg[SrcIndex];
TgtImg[TgtIndex+1] = SrcImg[SrcIndex+1];
TgtImg[TgtIndex+2] = SrcImg[SrcIndex+2];
}
int main(int argc, char** argv){
float totalTime, tfrCPUtoGPU, tfrGPUtoCPU, kernelExecutionTime; // GPU code run times
hipError_t cudaStatus, cudaStatus2;
hipEvent_t time1, time2, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks, GPUDataTransfer;
hipDeviceProp_t GPUprop;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imShrunk");
if(argc!=5){
printf("\n\nUsage: imshrunk input output xshrink yshrink");
return 0;
}
xshrink = atoi(argv[3]);
yshrink = atoi(argv[4]);
strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
TheImage = ReadBMPlin(argv[1]);
if (TheImage == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
origHpixels = ip.Hpixels;
origVpixels = ip.Vpixels;
origHbytes = ip.Hbytes;
origSize = origHbytes * origVpixels;
ip.Hpixels = ip.Hpixels/xshrink;
ip.Hbytes = (ip.Hpixels*3 + 3) & (~3);
ip.Vpixels = ip.Vpixels/yshrink;
// TgtSize = ip.Hbytes * ip.Vpixels;
// printf("\n new Hpixels %u", ip.Hpixels);
// printf("\n new Vpixels %u", ip.Vpixels);
NewImage = (uch *)malloc(IMAGESIZE);
if (NewImage == NULL){
free(NewImage);
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
hipGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
exit(EXIT_FAILURE);
}
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
exit(EXIT_FAILURE);
}
hipGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
hipEventCreate(&time1);
hipEventCreate(&time2);
hipEventCreate(&time3);
hipEventCreate(&time4);
hipEventRecord(time1, 0);
// allocate GPU buffer
cudaStatus = hipMalloc((void**)&GPUSrcImage, origSize);
cudaStatus2 = hipMalloc((void**)&GPUTgtImage, IMAGESIZE);
if ((cudaStatus != hipSuccess) || (cudaStatus2 != hipSuccess)){
fprintf(stderr, "hipMalloc failed! Can't allocate GPU memory");
exit(EXIT_FAILURE);
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(GPUSrcImage, TheImage, origSize, hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy CPU to GPU failed!");
exit(EXIT_FAILURE);
}
hipEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
BlkPerRow = (IPH + ThrPerBlk -1 ) / ThrPerBlk;
NumBlocks = IPV*BlkPerRow;
ImShrunk <<< NumBlocks, ThrPerBlk>>> (GPUTgtImage, GPUSrcImage, IPH, xshrink, yshrink, origHpixels, origHbytes);
GPUResult = GPUTgtImage;
GPUDataTransfer = origSize + IMAGESIZE;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n\nhipDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
exit(EXIT_FAILURE);
}
hipEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = hipMemcpy(NewImage, GPUResult, IMAGESIZE, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy GPU to CPU failed!");
exit(EXIT_FAILURE);
}
hipEventRecord(time4, 0);
hipEventSynchronize(time1);
hipEventSynchronize(time2);
hipEventSynchronize(time3);
hipEventSynchronize(time4);
hipEventElapsedTime(&totalTime, time1, time4);
hipEventElapsedTime(&tfrCPUtoGPU, time1, time2);
hipEventElapsedTime(&kernelExecutionTime, time2, time3);
hipEventElapsedTime(&tfrGPUtoCPU, time3, time4);
cudaStatus = hipDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
WriteBMPlin(NewImage, argv[2]); // Write the flipped image back to disk
////////////////// change from here
printf("\n\n--------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("--------------------------------------------------------------------------\n");
printf("%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
ThrPerBlk, NumBlocks, BlkPerRow);
printf("--------------------------------------------------------------------------\n");
printf("CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(origSize), DATABW(origSize, tfrCPUtoGPU));
printf("Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecutionTime, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));
printf("GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("--------------------------------------------------------------------------\n");
printf("Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n", totalTime, DATAMB((origSize + IMAGESIZE + GPUDataTransfer)), DATABW((origSize + IMAGESIZE+ GPUDataTransfer), totalTime));
printf("--------------------------------------------------------------------------\n\n");
// Deallocate CPU, GPU memory and destroy events.
hipFree(GPUSrcImage);
hipFree(GPUTgtImage);
hipEventDestroy(time1);
hipEventDestroy(time2);
hipEventDestroy(time3);
hipEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
free(TheImage);
free(NewImage);
return(EXIT_SUCCESS);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8ImShrunkPhS_jjjjj
.globl _Z8ImShrunkPhS_jjjjj
.p2align 8
.type _Z8ImShrunkPhS_jjjjj,@function
_Z8ImShrunkPhS_jjjjj:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b32 s2, s[0:1], 0x10
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s2, s4
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s6, s6, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_mul_i32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s3, s5
s_add_i32 s3, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s6, s3
s_mul_i32 s5, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s5, s6, s5
s_add_i32 s6, s3, 1
s_sub_i32 s7, s5, s4
s_cmp_ge_u32 s5, s4
s_cselect_b32 s3, s6, s3
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s3, 1
s_cmp_ge_u32 s5, s4
s_cselect_b32 s5, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s6, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s3
s_mul_hi_u32 s6, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s6
s_mul_hi_u32 s3, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s3, s5
s_add_i32 s7, s3, 1
s_sub_i32 s6, s15, s6
s_sub_i32 s8, s6, s5
s_cmp_ge_u32 s6, s5
s_cselect_b32 s3, s7, s3
s_cselect_b32 s6, s8, s6
s_add_i32 s7, s3, 1
s_cmp_ge_u32 s6, s5
s_cselect_b32 s3, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s3, s5
s_sub_i32 s5, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x14
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, 3
s_mul_i32 s0, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s3
v_mad_u64_u32 v[2:3], null, s1, v1, s[0:1]
s_mul_i32 s0, s2, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, 3
s_and_b32 s0, s0, -4
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s0, s3, s0
global_load_u8 v0, v2, s[6:7]
v_mad_u64_u32 v[3:4], null, v1, 3, s[0:1]
v_add_nc_u32_e32 v1, 1, v2
v_add_nc_u32_e32 v2, 2, v2
s_waitcnt vmcnt(0)
global_store_b8 v3, v0, s[4:5]
global_load_u8 v0, v1, s[6:7]
v_add_nc_u32_e32 v1, 1, v3
s_waitcnt vmcnt(0)
global_store_b8 v1, v0, s[4:5]
global_load_u8 v0, v2, s[6:7]
v_add_nc_u32_e32 v1, 2, v3
s_waitcnt vmcnt(0)
global_store_b8 v1, v0, s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8ImShrunkPhS_jjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8ImShrunkPhS_jjjjj, .Lfunc_end0-_Z8ImShrunkPhS_jjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8ImShrunkPhS_jjjjj
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z8ImShrunkPhS_jjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
ui origSize, TgtSize;
ui xshrink, yshrink;
ui origVpixels, origHpixels, origHbytes;
uch *TheImage, *NewImage; // Where images are stored in CPU
uch *GPUSrcImage, *GPUTgtImage, *GPUResult; // Where images are stored in GPU
struct ImgProp{
int Hpixels;
int Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
*(int*)&ip.HeaderInfo[2] = ip.Hbytes*ip.Vpixels+54;
*(int*)&ip.HeaderInfo[18] = ip.Hpixels;
*(int*)&ip.HeaderInfo[22] = ip.Vpixels;
*(int*)&ip.HeaderInfo[34] = ip.Hbytes*ip.Vpixels;
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u\n\n", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
__global__
void ImShrunk(uch *TgtImg, uch *SrcImg, ui TgtHpixels, ui xshrink, ui yshrink, ui origHpixels, ui origHbytes)
{
ui ThrPerBlk = blockDim.x;
ui TgtBid = blockIdx.x;
ui TgtTid = threadIdx.x;
ui TgtGtid = ThrPerBlk * TgtBid + TgtTid;
ui BlkPerRow = (TgtHpixels + ThrPerBlk - 1) / ThrPerBlk; // ceil
ui TgtRowBytes = (TgtHpixels * 3 + 3) & (~3);
// ui SrcRowBytes = (origHpixels * 3 + 3) & (~3);
ui SrcRowBytes = origHbytes;
ui Tgtrow = TgtBid / BlkPerRow;
ui TgtCol = TgtGtid - Tgtrow*BlkPerRow*ThrPerBlk;
if(TgtCol >= TgtHpixels) return;
ui SrcRow = Tgtrow * yshrink;
ui SrcCol = TgtCol * xshrink;
// if(SrcCol >= origHpixels) return;
///////////////
ui TgtOffset = Tgtrow * TgtRowBytes;
ui SrcOffset = SrcRow * SrcRowBytes;
ui TgtIndex = TgtOffset + 3*TgtCol;
ui SrcIndex = SrcOffset + 3*SrcCol;
TgtImg[TgtIndex] = SrcImg[SrcIndex];
TgtImg[TgtIndex+1] = SrcImg[SrcIndex+1];
TgtImg[TgtIndex+2] = SrcImg[SrcIndex+2];
}
int main(int argc, char** argv){
float totalTime, tfrCPUtoGPU, tfrGPUtoCPU, kernelExecutionTime; // GPU code run times
hipError_t cudaStatus, cudaStatus2;
hipEvent_t time1, time2, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks, GPUDataTransfer;
hipDeviceProp_t GPUprop;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imShrunk");
if(argc!=5){
printf("\n\nUsage: imshrunk input output xshrink yshrink");
return 0;
}
xshrink = atoi(argv[3]);
yshrink = atoi(argv[4]);
strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
TheImage = ReadBMPlin(argv[1]);
if (TheImage == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
origHpixels = ip.Hpixels;
origVpixels = ip.Vpixels;
origHbytes = ip.Hbytes;
origSize = origHbytes * origVpixels;
ip.Hpixels = ip.Hpixels/xshrink;
ip.Hbytes = (ip.Hpixels*3 + 3) & (~3);
ip.Vpixels = ip.Vpixels/yshrink;
// TgtSize = ip.Hbytes * ip.Vpixels;
// printf("\n new Hpixels %u", ip.Hpixels);
// printf("\n new Vpixels %u", ip.Vpixels);
NewImage = (uch *)malloc(IMAGESIZE);
if (NewImage == NULL){
free(NewImage);
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
hipGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
exit(EXIT_FAILURE);
}
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
exit(EXIT_FAILURE);
}
hipGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui)GPUprop.maxGridSize[0] * (ui)GPUprop.maxGridSize[1] * (ui)GPUprop.maxGridSize[2] / 1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks >= 5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks >= 5) ? 'M' : 'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
hipEventCreate(&time1);
hipEventCreate(&time2);
hipEventCreate(&time3);
hipEventCreate(&time4);
hipEventRecord(time1, 0);
// allocate GPU buffer
cudaStatus = hipMalloc((void**)&GPUSrcImage, origSize);
cudaStatus2 = hipMalloc((void**)&GPUTgtImage, IMAGESIZE);
if ((cudaStatus != hipSuccess) || (cudaStatus2 != hipSuccess)){
fprintf(stderr, "hipMalloc failed! Can't allocate GPU memory");
exit(EXIT_FAILURE);
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(GPUSrcImage, TheImage, origSize, hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy CPU to GPU failed!");
exit(EXIT_FAILURE);
}
hipEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
BlkPerRow = (IPH + ThrPerBlk -1 ) / ThrPerBlk;
NumBlocks = IPV*BlkPerRow;
ImShrunk <<< NumBlocks, ThrPerBlk>>> (GPUTgtImage, GPUSrcImage, IPH, xshrink, yshrink, origHpixels, origHbytes);
GPUResult = GPUTgtImage;
GPUDataTransfer = origSize + IMAGESIZE;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n\nhipDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
exit(EXIT_FAILURE);
}
hipEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = hipMemcpy(NewImage, GPUResult, IMAGESIZE, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy GPU to CPU failed!");
exit(EXIT_FAILURE);
}
hipEventRecord(time4, 0);
hipEventSynchronize(time1);
hipEventSynchronize(time2);
hipEventSynchronize(time3);
hipEventSynchronize(time4);
hipEventElapsedTime(&totalTime, time1, time4);
hipEventElapsedTime(&tfrCPUtoGPU, time1, time2);
hipEventElapsedTime(&kernelExecutionTime, time2, time3);
hipEventElapsedTime(&tfrGPUtoCPU, time3, time4);
cudaStatus = hipDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
WriteBMPlin(NewImage, argv[2]); // Write the flipped image back to disk
////////////////// change from here
printf("\n\n--------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("--------------------------------------------------------------------------\n");
printf("%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName,
ThrPerBlk, NumBlocks, BlkPerRow);
printf("--------------------------------------------------------------------------\n");
printf("CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(origSize), DATABW(origSize, tfrCPUtoGPU));
printf("Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecutionTime, DATAMB(GPUDataTransfer), DATABW(GPUDataTransfer, kernelExecutionTime));
printf("GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("--------------------------------------------------------------------------\n");
printf("Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n", totalTime, DATAMB((origSize + IMAGESIZE + GPUDataTransfer)), DATABW((origSize + IMAGESIZE+ GPUDataTransfer), totalTime));
printf("--------------------------------------------------------------------------\n\n");
// Deallocate CPU, GPU memory and destroy events.
hipFree(GPUSrcImage);
hipFree(GPUTgtImage);
hipEventDestroy(time1);
hipEventDestroy(time2);
hipEventDestroy(time3);
hipEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
free(TheImage);
free(NewImage);
exit(EXIT_FAILURE);
}
free(TheImage);
free(NewImage);
return(EXIT_SUCCESS);
} | .text
.file "imshrunkG.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10ReadBMPlinPc # -- Begin function _Z10ReadBMPlinPc
.p2align 4, 0x90
.type _Z10ReadBMPlinPc,@function
_Z10ReadBMPlinPc: # @_Z10ReadBMPlinPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r14
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_4
# %bb.1:
movq %rax, %rbx
movq %rsp, %rdi
movl $1, %esi
movl $54, %edx
movq %rax, %rcx
callq fread
movslq 18(%rsp), %rdx
movl %edx, ip(%rip)
movslq 22(%rsp), %rcx
movl %ecx, ip+4(%rip)
leaq (%rdx,%rdx,2), %r8
addq $3, %r8
andq $-4, %r8
movq %r8, ip+64(%rip)
movaps (%rsp), %xmm0
movaps 16(%rsp), %xmm1
movaps 32(%rsp), %xmm2
movups %xmm0, ip+8(%rip)
movups %xmm1, ip+24(%rip)
movups %xmm2, ip+40(%rip)
movq 46(%rsp), %rax
movq %rax, ip+54(%rip)
imulq %rcx, %r8
xorl %r15d, %r15d
movl $.L.str.2, %edi
movq %r14, %rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movslq ip+4(%rip), %r14
imulq ip+64(%rip), %r14
movq %r14, %rdi
callq malloc
movq %rax, _ZZ10ReadBMPlinPcE3Img(%rip)
testq %rax, %rax
je .LBB0_3
# %bb.2:
movl $1, %esi
movq %rax, %rdi
movq %r14, %rdx
movq %rbx, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movq _ZZ10ReadBMPlinPcE3Img(%rip), %r15
.LBB0_3:
movq %r15, %rax
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_4:
.cfi_def_cfa_offset 96
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10ReadBMPlinPc, .Lfunc_end0-_Z10ReadBMPlinPc
.cfi_endproc
# -- End function
.globl _Z11WriteBMPlinPhPc # -- Begin function _Z11WriteBMPlinPhPc
.p2align 4, 0x90
.type _Z11WriteBMPlinPhPc,@function
_Z11WriteBMPlinPhPc: # @_Z11WriteBMPlinPhPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r15
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.2:
movq %rax, %r14
movl ip+4(%rip), %eax
movl ip+64(%rip), %ecx
imull %eax, %ecx
leal 54(%rcx), %edx
movl %edx, ip+10(%rip)
movl ip(%rip), %edx
movl %edx, ip+26(%rip)
movl %eax, ip+30(%rip)
movl %ecx, ip+42(%rip)
movl $ip+8, %edi
movl $1, %esi
movl $54, %edx
movq %r14, %rcx
callq fwrite
movslq ip+4(%rip), %rdx
imulq ip+64(%rip), %rdx
movl $1, %esi
movq %r15, %rdi
movq %r14, %rcx
callq fwrite
movl ip(%rip), %edx
movslq ip+4(%rip), %rcx
movq %rcx, %r8
imulq ip+64(%rip), %r8
movl $.L.str.5, %edi
movq %rbx, %rsi
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 32
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11WriteBMPlinPhPc, .Lfunc_end1-_Z11WriteBMPlinPhPc
.cfi_endproc
# -- End function
.globl _Z23__device_stub__ImShrunkPhS_jjjjj # -- Begin function _Z23__device_stub__ImShrunkPhS_jjjjj
.p2align 4, 0x90
.type _Z23__device_stub__ImShrunkPhS_jjjjj,@function
_Z23__device_stub__ImShrunkPhS_jjjjj: # @_Z23__device_stub__ImShrunkPhS_jjjjj
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8ImShrunkPhS_jjjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z23__device_stub__ImShrunkPhS_jjjjj, .Lfunc_end2-_Z23__device_stub__ImShrunkPhS_jjjjj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0624dd2f1a9fc # double 1.024
.LCPI3_1:
.quad 0x4090000000000000 # double 1024
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $2544, %rsp # imm = 0x9F0
.cfi_def_cfa_offset 2592
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $7741253943733480809, %rax # imm = 0x6B6E757268536D69
movq %rax, 304(%rsp)
movb $0, 312(%rsp)
cmpl $5, %edi
jne .LBB3_1
# %bb.2:
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, xshrink(%rip)
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, yshrink(%rip)
movq 8(%rbx), %r14
leaq 816(%rsp), %rdi
movq %r14, %rsi
callq strcpy
movq 16(%rbx), %rsi
leaq 560(%rsp), %rdi
callq strcpy
movq %r14, %rdi
callq _Z10ReadBMPlinPc
movq %rax, TheImage(%rip)
testq %rax, %rax
je .LBB3_3
# %bb.5:
movl ip(%rip), %eax
movl %eax, origHpixels(%rip)
movl ip+4(%rip), %ecx
movl %ecx, origVpixels(%rip)
movl ip+64(%rip), %edx
movl %edx, origHbytes(%rip)
imull %ecx, %edx
movl %edx, origSize(%rip)
xorl %edx, %edx
divl xshrink(%rip)
# kill: def $eax killed $eax def $rax
movl %eax, ip(%rip)
leal (%rax,%rax,2), %eax
addl $3, %eax
andl $-4, %eax
movslq %eax, %rsi
movq %rsi, ip+64(%rip)
movl %ecx, %eax
xorl %edx, %edx
divl yshrink(%rip)
movl %eax, ip+4(%rip)
movslq %eax, %rdi
imulq %rsi, %rdi
callq malloc
movq %rax, NewImage(%rip)
testq %rax, %rax
je .LBB3_3
# %bb.6:
movl $0, 36(%rsp)
leaq 36(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 36(%rsp)
je .LBB3_7
# %bb.8:
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB3_9
# %bb.11:
leaq 1072(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 1412(%rsp), %eax
imull 1408(%rsp), %eax
imull 1416(%rsp), %eax
movl %eax, %ecx
shrl $10, %ecx
movl %eax, %edx
shrl $20, %edx
xorl %esi, %esi
cmpl $5242880, %eax # imm = 0x500000
setae %sil
cmovbq %rcx, %rdx
leal 75(,%rsi,2), %ecx
leaq 192(%rsp), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq sprintf
movl 1392(%rsp), %r14d
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl origSize(%rip), %esi
movl $GPUSrcImage, %edi
callq hipMalloc
movl %eax, %ebp
movslq ip+4(%rip), %rsi
imulq ip+64(%rip), %rsi
movl $GPUTgtImage, %edi
callq hipMalloc
orl %ebp, %eax
jne .LBB3_12
# %bb.13:
movq GPUSrcImage(%rip), %rdi
movq TheImage(%rip), %rsi
movl origSize(%rip), %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_14
# %bb.15:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $255, %r12d
addl ip(%rip), %r12d
shrl $8, %r12d
movl ip+4(%rip), %r15d
imull %r12d, %r15d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%r15,%rdx), %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16:
movq GPUTgtImage(%rip), %rax
movq GPUSrcImage(%rip), %rcx
movl ip(%rip), %edx
movl xshrink(%rip), %esi
movl yshrink(%rip), %edi
movl origHpixels(%rip), %r8d
movl origHbytes(%rip), %r9d
movq %rax, 40(%rsp)
movq %rcx, 120(%rsp)
movl %edx, 68(%rsp)
movl %esi, 64(%rsp)
movl %edi, 60(%rsp)
movl %r8d, 56(%rsp)
movl %r9d, 52(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 68(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 60(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 52(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8ImShrunkPhS_jjjjj, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_17:
movq GPUTgtImage(%rip), %rax
movq %rax, GPUResult(%rip)
movl ip+4(%rip), %ebp
imull ip+64(%rip), %ebp
addl origSize(%rip), %ebp
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_33
# %bb.18:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq NewImage(%rip), %rdi
movq GPUResult(%rip), %rsi
movslq ip+4(%rip), %rdx
imulq ip+64(%rip), %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_19
# %bb.20:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 88(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_21
# %bb.23:
movq NewImage(%rip), %rdi
movq 16(%rbx), %rsi
callq _Z11WriteBMPlinPhPc
movl $.Lstr, %edi
callq puts@PLT
movl 1432(%rsp), %edx
movl 1436(%rsp), %ecx
leaq 1072(%rsp), %rsi
leaq 192(%rsp), %r8
movl $.L.str.18, %edi
movq %r14, %r9
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 312(%rsp), %rsi
leaq 824(%rsp), %rdx
leaq 568(%rsp), %rcx
movl $.L.str.20, %edi
movl $256, %r8d # imm = 0x100
movl %r15d, %r9d
xorl %eax, %eax
pushq %r12
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $.Lstr.3, %edi
callq puts@PLT
movl origSize(%rip), %eax
cvtsi2ss %rax, %xmm1
movss 88(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl %eax, %esi
shrl $20, %esi
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
mulsd .LCPI3_0(%rip), %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.21, %edi
movb $2, %al
callq printf
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %ebp, %ebx
xorps %xmm1, %xmm1
cvtsi2ss %rbx, %xmm1
cvtss2sd %xmm0, %xmm0
shrl $20, %ebp
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
mulsd .LCPI3_0(%rip), %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.22, %edi
movl %ebp, %esi
movb $2, %al
callq printf
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq ip+4(%rip), %rax
imulq ip+64(%rip), %rax
cvtss2sd %xmm0, %xmm0
movq %rax, %rsi
shrq $20, %rsi
testq %rax, %rax
js .LBB3_24
# %bb.25:
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
jmp .LBB3_26
.LBB3_1:
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_32
.LBB3_24:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB3_26:
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
mulsd .LCPI3_0(%rip), %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.23, %edi
movb $2, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl origSize(%rip), %ecx
movslq ip+4(%rip), %rax
imulq ip+64(%rip), %rax
addq %rcx, %rax
addq %rbx, %rax
movq %rax, %rsi
shrq $20, %rsi
testq %rax, %rax
js .LBB3_27
# %bb.28:
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
jmp .LBB3_29
.LBB3_27:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB3_29:
cvtss2sd %xmm1, %xmm1
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.24, %edi
movb $2, %al
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
movq GPUSrcImage(%rip), %rdi
callq hipFree
movq GPUTgtImage(%rip), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
callq hipDeviceReset
testl %eax, %eax
jne .LBB3_30
# %bb.31:
movq TheImage(%rip), %rdi
callq free
movq NewImage(%rip), %rdi
callq free
.LBB3_32:
xorl %eax, %eax
addq $2544, %rsp # imm = 0x9F0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 2592
movl $.Lstr.7, %edi
jmp .LBB3_4
.LBB3_7:
movl $.Lstr.5, %edi
.LBB3_4:
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_9:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $63, %esi
jmp .LBB3_10
.LBB3_12:
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $43, %esi
jmp .LBB3_10
.LBB3_14:
movq stderr(%rip), %rcx
movl $.L.str.13, %edi
movl $30, %esi
jmp .LBB3_10
.LBB3_33:
movq stderr(%rip), %rdi
movl $.L.str.14, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_19:
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $29, %esi
.LBB3_10:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB3_21:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $47, %esi
jmp .LBB3_22
.LBB3_30:
movq stderr(%rip), %rcx
movl $.L.str.26, %edi
movl $22, %esi
.LBB3_22:
movl $1, %edx
callq fwrite
movq TheImage(%rip), %rdi
callq free
movq NewImage(%rip), %rdi
callq free
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8ImShrunkPhS_jjjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type origSize,@object # @origSize
.bss
.globl origSize
.p2align 2, 0x0
origSize:
.long 0 # 0x0
.size origSize, 4
.type TgtSize,@object # @TgtSize
.globl TgtSize
.p2align 2, 0x0
TgtSize:
.long 0 # 0x0
.size TgtSize, 4
.type xshrink,@object # @xshrink
.globl xshrink
.p2align 2, 0x0
xshrink:
.long 0 # 0x0
.size xshrink, 4
.type yshrink,@object # @yshrink
.globl yshrink
.p2align 2, 0x0
yshrink:
.long 0 # 0x0
.size yshrink, 4
.type origVpixels,@object # @origVpixels
.globl origVpixels
.p2align 2, 0x0
origVpixels:
.long 0 # 0x0
.size origVpixels, 4
.type origHpixels,@object # @origHpixels
.globl origHpixels
.p2align 2, 0x0
origHpixels:
.long 0 # 0x0
.size origHpixels, 4
.type origHbytes,@object # @origHbytes
.globl origHbytes
.p2align 2, 0x0
origHbytes:
.long 0 # 0x0
.size origHbytes, 4
.type TheImage,@object # @TheImage
.globl TheImage
.p2align 3, 0x0
TheImage:
.quad 0
.size TheImage, 8
.type NewImage,@object # @NewImage
.globl NewImage
.p2align 3, 0x0
NewImage:
.quad 0
.size NewImage, 8
.type GPUSrcImage,@object # @GPUSrcImage
.globl GPUSrcImage
.p2align 3, 0x0
GPUSrcImage:
.quad 0
.size GPUSrcImage, 8
.type GPUTgtImage,@object # @GPUTgtImage
.globl GPUTgtImage
.p2align 3, 0x0
GPUTgtImage:
.quad 0
.size GPUTgtImage, 8
.type GPUResult,@object # @GPUResult
.globl GPUResult
.p2align 3, 0x0
GPUResult:
.quad 0
.size GPUResult, 8
.type ip,@object # @ip
.globl ip
.p2align 3, 0x0
ip:
.zero 72
.size ip, 72
.type _ZZ10ReadBMPlinPcE3Img,@object # @_ZZ10ReadBMPlinPcE3Img
.local _ZZ10ReadBMPlinPcE3Img
.comm _ZZ10ReadBMPlinPcE3Img,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n%s NOT FOUND\n\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n Input File name: %17s (%u x %u) File Size=%u"
.size .L.str.2, 50
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n\nFILE CREATION ERROR: %s\n\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nOutput File name: %17s (%u x %u) File Size=%u\n\n"
.size .L.str.5, 52
.type _Z8ImShrunkPhS_jjjjj,@object # @_Z8ImShrunkPhS_jjjjj
.section .rodata,"a",@progbits
.globl _Z8ImShrunkPhS_jjjjj
.p2align 3, 0x0
_Z8ImShrunkPhS_jjjjj:
.quad _Z23__device_stub__ImShrunkPhS_jjjjj
.size _Z8ImShrunkPhS_jjjjj, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "imShrunk"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n\nUsage: imshrunk input output xshrink yshrink"
.size .L.str.7, 47
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.10, 64
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%u %c"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipMalloc failed! Can't allocate GPU memory"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy CPU to GPU failed!"
.size .L.str.13, 31
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\n\nhipDeviceSynchronize returned error code %d after launching the kernel!\n"
.size .L.str.14, 75
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "hipMemcpy GPU to CPU failed!"
.size .L.str.15, 30
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "\n Program failed after cudaDeviceSynchronize()!"
.size .L.str.16, 48
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "%s ComputeCapab=%d.%d [max %s blocks
.size .L.str.18, 56
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n"
.size .L.str.20, 42
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.size .L.str.21, 61
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.size .L.str.22, 61
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.size .L.str.23, 61
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n"
.size .L.str.24, 61
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "hipDeviceReset failed!"
.size .L.str.26, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8ImShrunkPhS_jjjjj"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n--------------------------------------------------------------------------"
.size .Lstr, 77
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "--------------------------------------------------------------------------"
.size .Lstr.3, 75
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "--------------------------------------------------------------------------\n"
.size .Lstr.4, 76
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\nNo CUDA Device is available"
.size .Lstr.5, 29
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Cannot allocate memory for the input image..."
.size .Lstr.7, 46
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__ImShrunkPhS_jjjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym GPUSrcImage
.addrsig_sym GPUTgtImage
.addrsig_sym ip
.addrsig_sym _Z8ImShrunkPhS_jjjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8ImShrunkPhS_jjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e660000002500 */
/*0050*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0060*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x004fc800078e0a03 */
/*00c0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0100*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R0, R0, -c[0x0][0x0], RZ ; /* 0x8000000000000a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff05aa12 */
/* 0x000fc800078e33ff */
/*0170*/ I2F.U32.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209000 */
/*0180*/ ISETP.NE.U32.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f45070 */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fe40007ffe0ff */
/*01b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*01c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0004e4000021f000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x004fc400078e00ff */
/*01e0*/ IMAD R4, R5, R3, RZ ; /* 0x0000000305047224 */
/* 0x008fc800078e02ff */
/*01f0*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a04 */
/*0200*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0210*/ IMAD.HI.U32 R4, R3, UR4, RZ ; /* 0x0000000403047c27 */
/* 0x002fc8000f8e00ff */
/*0220*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*0230*/ IMAD R6, R5, R6, UR4 ; /* 0x0000000405067e24 */
/* 0x000fca000f8e0206 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R6, -R5, R6, RZ ; /* 0x0000000605060210 */
/* 0x000fe40007ffe1ff */
/*0260*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x000fda0003f26070 */
/*0280*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0290*/ @!P2 LOP3.LUT R4, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff04a212 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a04 */
/*02b0*/ IMAD R5, R5, R2, UR4 ; /* 0x0000000405057e24 */
/* 0x000fc8000f8e0202 */
/*02c0*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02f0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0300*/ IMAD R5, R5, 0x3, RZ ; /* 0x0000000305057824 */
/* 0x000fe200078e02ff */
/*0310*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0320*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0330*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0340*/ IMAD R0, R4, UR4, RZ ; /* 0x0000000404007c24 */
/* 0x000fc8000f8e02ff */
/*0350*/ IMAD R8, R5, c[0x0][0x174], R0 ; /* 0x00005d0005087a24 */
/* 0x000fca00078e0200 */
/*0360*/ IADD3 R2, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008027a10 */
/* 0x000fca0007f1e0ff */
/*0370*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fca00000e06ff */
/*0380*/ LDG.E.U8 R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea2000c1e1100 */
/*0390*/ UMOV UR4, 0x3 ; /* 0x0000000300047882 */
/* 0x000fe20000000000 */
/*03a0*/ IADD3 R6, R8, 0x1, RZ ; /* 0x0000000108067810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*03c0*/ UIMAD UR4, UR4, UR5, UR4 ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e0204 */
/*03d0*/ IADD3 R6, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a10 */
/* 0x000fc60007f3e0ff */
/*03e0*/ ULOP3.LUT UR4, UR4, 0xfffffffc, URZ, 0xc0, !UPT ; /* 0xfffffffc04047892 */
/* 0x000fe4000f8ec03f */
/*03f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff077624 */
/* 0x000fc800008e06ff */
/*0400*/ IMAD R0, R4, UR4, R5 ; /* 0x0000000404007c24 */
/* 0x000fca000f8e0205 */
/*0410*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fca0007f1e0ff */
/*0420*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0430*/ STG.E.U8 [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0041e8000c101106 */
/*0440*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1100 */
/*0450*/ IADD3 R8, R8, 0x2, RZ ; /* 0x0000000208087810 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R8, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007f3e0ff */
/*0480*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fc60007f1e0ff */
/*0490*/ IMAD.X R9, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff097624 */
/* 0x000fe200008e06ff */
/*04a0*/ IADD3.X R3, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff037a10 */
/* 0x000fe400007fe4ff */
/*04b0*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe8000c101106 */
/*04d0*/ LDG.E.U8 R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ea2000c1e1100 */
/*04e0*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x001fca0007f1e0ff */
/*04f0*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*0500*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe2000c101106 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8ImShrunkPhS_jjjjj
.globl _Z8ImShrunkPhS_jjjjj
.p2align 8
.type _Z8ImShrunkPhS_jjjjj,@function
_Z8ImShrunkPhS_jjjjj:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b32 s2, s[0:1], 0x10
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s2, s4
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s6, s6, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_mul_i32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s3, s5
s_add_i32 s3, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s6, s3
s_mul_i32 s5, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s5, s6, s5
s_add_i32 s6, s3, 1
s_sub_i32 s7, s5, s4
s_cmp_ge_u32 s5, s4
s_cselect_b32 s3, s6, s3
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s3, 1
s_cmp_ge_u32 s5, s4
s_cselect_b32 s5, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
s_sub_i32 s6, 0, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s6, s3
s_mul_hi_u32 s6, s3, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s6
s_mul_hi_u32 s3, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s3, s5
s_add_i32 s7, s3, 1
s_sub_i32 s6, s15, s6
s_sub_i32 s8, s6, s5
s_cmp_ge_u32 s6, s5
s_cselect_b32 s3, s7, s3
s_cselect_b32 s6, s8, s6
s_add_i32 s7, s3, 1
s_cmp_ge_u32 s6, s5
s_cselect_b32 s3, s7, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s3, s5
s_sub_i32 s5, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x14
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s8, 3
s_mul_i32 s0, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s0, s3
v_mad_u64_u32 v[2:3], null, s1, v1, s[0:1]
s_mul_i32 s0, s2, 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, 3
s_and_b32 s0, s0, -4
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s0, s3, s0
global_load_u8 v0, v2, s[6:7]
v_mad_u64_u32 v[3:4], null, v1, 3, s[0:1]
v_add_nc_u32_e32 v1, 1, v2
v_add_nc_u32_e32 v2, 2, v2
s_waitcnt vmcnt(0)
global_store_b8 v3, v0, s[4:5]
global_load_u8 v0, v1, s[6:7]
v_add_nc_u32_e32 v1, 1, v3
s_waitcnt vmcnt(0)
global_store_b8 v1, v0, s[4:5]
global_load_u8 v0, v2, s[6:7]
v_add_nc_u32_e32 v1, 2, v3
s_waitcnt vmcnt(0)
global_store_b8 v1, v0, s[4:5]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8ImShrunkPhS_jjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8ImShrunkPhS_jjjjj, .Lfunc_end0-_Z8ImShrunkPhS_jjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8ImShrunkPhS_jjjjj
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z8ImShrunkPhS_jjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d691_00000000-6_imshrunkG.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "\n\n%s NOT FOUND\n\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n Input File name: %17s (%u x %u) File Size=%u"
.text
.globl _Z10ReadBMPlinPc
.type _Z10ReadBMPlinPc, @function
_Z10ReadBMPlinPc:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L8
movq %rax, %rbx
movq %rsp, %rdi
movq %rax, %r8
movl $54, %ecx
movl $1, %edx
movl $54, %esi
call __fread_chk@PLT
movl 18(%rsp), %ecx
movl %ecx, ip(%rip)
movl 22(%rsp), %r8d
movl %r8d, 4+ip(%rip)
leal 3(%rcx,%rcx,2), %eax
andl $-4, %eax
cltq
movq %rax, 64+ip(%rip)
movdqa (%rsp), %xmm0
movups %xmm0, 8+ip(%rip)
movdqa 16(%rsp), %xmm1
movups %xmm1, 24+ip(%rip)
movdqa 32(%rsp), %xmm2
movups %xmm2, 40+ip(%rip)
movq 46(%rsp), %rdx
movq %rdx, 54+ip(%rip)
movslq %r8d, %r9
imulq %rax, %r9
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 4+ip(%rip), %rbp
imulq 64+ip(%rip), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, _ZZ10ReadBMPlinPcE3Img(%rip)
testq %rax, %rax
je .L3
movq %rbx, %r8
movq %rbp, %rcx
movl $1, %edx
movq %rbp, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq _ZZ10ReadBMPlinPcE3Img(%rip), %rax
.L3:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L9
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movq %rbp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10ReadBMPlinPc, .-_Z10ReadBMPlinPc
.section .rodata.str1.1
.LC3:
.string "wb"
.LC4:
.string "\n\nFILE CREATION ERROR: %s\n\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "\nOutput File name: %17s (%u x %u) File Size=%u\n\n"
.text
.globl _Z11WriteBMPlinPhPc
.type _Z11WriteBMPlinPhPc, @function
_Z11WriteBMPlinPhPc:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
testq %rax, %rax
je .L13
movq %rax, %rbx
movl 4+ip(%rip), %edx
movl %edx, %eax
imull 64+ip(%rip), %eax
leal 54(%rax), %ecx
movl %ecx, 10+ip(%rip)
movl ip(%rip), %ecx
movl %ecx, 26+ip(%rip)
movl %edx, 30+ip(%rip)
movl %eax, 42+ip(%rip)
movq %rbx, %rcx
movl $54, %edx
movl $1, %esi
leaq 8+ip(%rip), %rdi
call fwrite@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
movq %rbx, %rcx
movl $1, %esi
movq %r12, %rdi
call fwrite@PLT
movl 4+ip(%rip), %r8d
movslq %r8d, %r9
imulq 64+ip(%rip), %r9
movl ip(%rip), %ecx
movq %rbp, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z11WriteBMPlinPhPc, .-_Z11WriteBMPlinPhPc
.globl _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
.type _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj, @function
_Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj:
.LFB3696:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8ImShrunkPhS_jjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj, .-_Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
.globl _Z8ImShrunkPhS_jjjjj
.type _Z8ImShrunkPhS_jjjjj, @function
_Z8ImShrunkPhS_jjjjj:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8ImShrunkPhS_jjjjj, .-_Z8ImShrunkPhS_jjjjj
.section .rodata.str1.8
.align 8
.LC6:
.string "\n\nUsage: imshrunk input output xshrink yshrink"
.align 8
.LC7:
.string "Cannot allocate memory for the input image...\n"
.section .rodata.str1.1
.LC8:
.string "\nNo CUDA Device is available\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC10:
.string "%u %c"
.section .rodata.str1.8
.align 8
.LC11:
.string "cudaMalloc failed! Can't allocate GPU memory"
.align 8
.LC12:
.string "cudaMemcpy CPU to GPU failed!"
.align 8
.LC13:
.string "\n\ncudaDeviceSynchronize returned error code %d after launching the kernel!\n"
.align 8
.LC14:
.string "cudaMemcpy GPU to CPU failed!"
.align 8
.LC15:
.string "\n Program failed after cudaDeviceSynchronize()!"
.align 8
.LC16:
.string "\n\n--------------------------------------------------------------------------\n"
.align 8
.LC17:
.string "%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n"
.align 8
.LC18:
.string "--------------------------------------------------------------------------\n"
.align 8
.LC19:
.string "%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n"
.align 8
.LC22:
.string "CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.align 8
.LC23:
.string "Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.align 8
.LC24:
.string "GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.align 8
.LC25:
.string "Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n"
.align 8
.LC26:
.string "--------------------------------------------------------------------------\n\n"
.section .rodata.str1.1
.LC27:
.string "cudaDeviceReset failed!"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $2016, %rsp
.cfi_def_cfa_offset 2064
movq %fs:40, %rax
movq %rax, 2008(%rsp)
xorl %eax, %eax
movabsq $7741253943733480809, %rax
movq %rax, 1744(%rsp)
movb $0, 1752(%rsp)
cmpl $5, %edi
je .L23
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movq 2008(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $2016, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, xshrink(%rip)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, yshrink(%rip)
movq 8(%rbx), %rbp
leaq 1232(%rsp), %rdi
movl $255, %edx
movq %rbp, %rsi
call __strcpy_chk@PLT
movq 16(%rbx), %rsi
leaq 1488(%rsp), %rdi
movl $255, %edx
call __strcpy_chk@PLT
movq %rbp, %rdi
call _Z10ReadBMPlinPc
movq %rax, TheImage(%rip)
testq %rax, %rax
je .L49
movl ip(%rip), %eax
movl %eax, origHpixels(%rip)
movl 4+ip(%rip), %edi
movl %edi, origVpixels(%rip)
movq 64+ip(%rip), %rdx
movl %edx, origHbytes(%rip)
imull %edi, %edx
movl %edx, origSize(%rip)
movl $0, %edx
divl xshrink(%rip)
movl %eax, ip(%rip)
leal 1(%rax), %ecx
imull $3, %ecx, %ecx
andl $-4, %ecx
movslq %ecx, %rcx
movq %rcx, 64+ip(%rip)
movl %edi, %eax
movl $0, %edx
divl yshrink(%rip)
movl %eax, 4+ip(%rip)
movslq %eax, %rdi
imulq %rcx, %rdi
call malloc@PLT
movq %rax, NewImage(%rip)
testq %rax, %rax
je .L50
movl $0, 20(%rsp)
leaq 20(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 20(%rsp)
je .L51
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L52
leaq 80(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %eax
imull 420(%rsp), %eax
imull 424(%rsp), %eax
shrl $10, %eax
movl %eax, %r8d
movl $75, %r9d
cmpl $5119, %eax
jbe .L29
shrq $10, %r8
movl $77, %r9d
.L29:
leaq 1120(%rsp), %rdi
leaq .LC10(%rip), %rcx
movl $100, %edx
movl $2, %esi
movl $0, %eax
call __sprintf_chk@PLT
movl 400(%rsp), %r13d
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl origSize(%rip), %esi
leaq GPUSrcImage(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ebp
movslq 4+ip(%rip), %rsi
imulq 64+ip(%rip), %rsi
leaq GPUTgtImage(%rip), %rdi
call cudaMalloc@PLT
orl %ebp, %eax
jne .L53
movl origSize(%rip), %edx
movl $1, %ecx
movq TheImage(%rip), %rsi
movq GPUSrcImage(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L54
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl ip(%rip), %eax
leal 255(%rax), %r12d
shrl $8, %r12d
movl %r12d, %r14d
imull 4+ip(%rip), %r14d
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L55
.L32:
movq GPUTgtImage(%rip), %rax
movq %rax, GPUResult(%rip)
movl 4+ip(%rip), %ebp
imull 64+ip(%rip), %ebp
addl origSize(%rip), %ebp
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L56
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
movl $2, %ecx
movq GPUResult(%rip), %rsi
movq NewImage(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L57
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 16(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 68(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 56(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L58
movq 16(%rbx), %rsi
movq NewImage(%rip), %rdi
call _Z11WriteBMPlinPhPc
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 2072
pushq %r13
.cfi_def_cfa_offset 2080
leaq 1136(%rsp), %r9
movl 460(%rsp), %r8d
movl 456(%rsp), %ecx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 2064
leaq .LC18(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1232(%rsp), %rcx
leaq 1744(%rsp), %rdx
pushq %r12
.cfi_def_cfa_offset 2072
pushq %r14
.cfi_def_cfa_offset 2080
movl $256, %r9d
leaq 1504(%rsp), %r8
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 2064
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl origSize(%rip), %edx
pxor %xmm2, %xmm2
cvtss2sd 16(%rsp), %xmm2
movl %edx, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
shrl $20, %edx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
pxor %xmm2, %xmm2
cvtss2sd 68(%rsp), %xmm2
movl %ebp, %eax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
movl %ebp, %edx
shrl $20, %edx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
pxor %xmm2, %xmm2
cvtss2sd 56(%rsp), %xmm2
testq %rdx, %rdx
js .L40
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
.L41:
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
shrq $20, %rdx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 4+ip(%rip), %rdx
imulq 64+ip(%rip), %rdx
movl origSize(%rip), %eax
addq %rax, %rdx
movl %ebp, %ebp
pxor %xmm2, %xmm2
cvtss2sd 12(%rsp), %xmm2
addq %rbp, %rdx
js .L42
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
.L43:
cvtss2sd %xmm1, %xmm1
movapd %xmm2, %xmm0
mulsd .LC20(%rip), %xmm0
movsd .LC21(%rip), %xmm3
mulsd %xmm3, %xmm0
mulsd %xmm3, %xmm0
shrq $20, %rdx
divsd %xmm0, %xmm1
movapd %xmm2, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq GPUSrcImage(%rip), %rdi
call cudaFree@PLT
movq GPUTgtImage(%rip), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L59
movq TheImage(%rip), %rdi
call free@PLT
movq NewImage(%rip), %rdi
call free@PLT
jmp .L24
.L49:
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
subq $8, %rsp
.cfi_def_cfa_offset 2072
movl origHbytes(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 2080
movl origHpixels(%rip), %r9d
movl yshrink(%rip), %r8d
movl xshrink(%rip), %ecx
movl ip(%rip), %edx
movq GPUSrcImage(%rip), %rsi
movq GPUTgtImage(%rip), %rdi
call _Z34__device_stub__Z8ImShrunkPhS_jjjjjPhS_jjjjj
addq $16, %rsp
.cfi_def_cfa_offset 2064
jmp .L32
.L56:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq TheImage(%rip), %rdi
call free@PLT
movq NewImage(%rip), %rdi
call free@PLT
movl $1, %edi
call exit@PLT
.L40:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L41
.L42:
movq %rdx, %rax
shrq %rax
movq %rdx, %rcx
andl $1, %ecx
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
addss %xmm1, %xmm1
jmp .L43
.L59:
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq TheImage(%rip), %rdi
call free@PLT
movq NewImage(%rip), %rdi
call free@PLT
movl $1, %edi
call exit@PLT
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC28:
.string "_Z8ImShrunkPhS_jjjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z8ImShrunkPhS_jjjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ10ReadBMPlinPcE3Img
.comm _ZZ10ReadBMPlinPcE3Img,8,8
.globl ip
.bss
.align 32
.type ip, @object
.size ip, 72
ip:
.zero 72
.globl GPUResult
.align 8
.type GPUResult, @object
.size GPUResult, 8
GPUResult:
.zero 8
.globl GPUTgtImage
.align 8
.type GPUTgtImage, @object
.size GPUTgtImage, 8
GPUTgtImage:
.zero 8
.globl GPUSrcImage
.align 8
.type GPUSrcImage, @object
.size GPUSrcImage, 8
GPUSrcImage:
.zero 8
.globl NewImage
.align 8
.type NewImage, @object
.size NewImage, 8
NewImage:
.zero 8
.globl TheImage
.align 8
.type TheImage, @object
.size TheImage, 8
TheImage:
.zero 8
.globl origHbytes
.align 4
.type origHbytes, @object
.size origHbytes, 4
origHbytes:
.zero 4
.globl origHpixels
.align 4
.type origHpixels, @object
.size origHpixels, 4
origHpixels:
.zero 4
.globl origVpixels
.align 4
.type origVpixels, @object
.size origVpixels, 4
origVpixels:
.zero 4
.globl yshrink
.align 4
.type yshrink, @object
.size yshrink, 4
yshrink:
.zero 4
.globl xshrink
.align 4
.type xshrink, @object
.size xshrink, 4
xshrink:
.zero 4
.globl TgtSize
.align 4
.type TgtSize, @object
.size TgtSize, 4
TgtSize:
.zero 4
.globl origSize
.align 4
.type origSize, @object
.size origSize, 4
origSize:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC20:
.long -755914244
.long 1072718413
.align 8
.LC21:
.long 0
.long 1083179008
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "imshrunkG.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10ReadBMPlinPc # -- Begin function _Z10ReadBMPlinPc
.p2align 4, 0x90
.type _Z10ReadBMPlinPc,@function
_Z10ReadBMPlinPc: # @_Z10ReadBMPlinPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $64, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %r14
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB0_4
# %bb.1:
movq %rax, %rbx
movq %rsp, %rdi
movl $1, %esi
movl $54, %edx
movq %rax, %rcx
callq fread
movslq 18(%rsp), %rdx
movl %edx, ip(%rip)
movslq 22(%rsp), %rcx
movl %ecx, ip+4(%rip)
leaq (%rdx,%rdx,2), %r8
addq $3, %r8
andq $-4, %r8
movq %r8, ip+64(%rip)
movaps (%rsp), %xmm0
movaps 16(%rsp), %xmm1
movaps 32(%rsp), %xmm2
movups %xmm0, ip+8(%rip)
movups %xmm1, ip+24(%rip)
movups %xmm2, ip+40(%rip)
movq 46(%rsp), %rax
movq %rax, ip+54(%rip)
imulq %rcx, %r8
xorl %r15d, %r15d
movl $.L.str.2, %edi
movq %r14, %rsi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movslq ip+4(%rip), %r14
imulq ip+64(%rip), %r14
movq %r14, %rdi
callq malloc
movq %rax, _ZZ10ReadBMPlinPcE3Img(%rip)
testq %rax, %rax
je .LBB0_3
# %bb.2:
movl $1, %esi
movq %rax, %rdi
movq %r14, %rdx
movq %rbx, %rcx
callq fread
movq %rbx, %rdi
callq fclose
movq _ZZ10ReadBMPlinPcE3Img(%rip), %r15
.LBB0_3:
movq %r15, %rax
addq $64, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_4:
.cfi_def_cfa_offset 96
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10ReadBMPlinPc, .Lfunc_end0-_Z10ReadBMPlinPc
.cfi_endproc
# -- End function
.globl _Z11WriteBMPlinPhPc # -- Begin function _Z11WriteBMPlinPhPc
.p2align 4, 0x90
.type _Z11WriteBMPlinPhPc,@function
_Z11WriteBMPlinPhPc: # @_Z11WriteBMPlinPhPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r15
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB1_1
# %bb.2:
movq %rax, %r14
movl ip+4(%rip), %eax
movl ip+64(%rip), %ecx
imull %eax, %ecx
leal 54(%rcx), %edx
movl %edx, ip+10(%rip)
movl ip(%rip), %edx
movl %edx, ip+26(%rip)
movl %eax, ip+30(%rip)
movl %ecx, ip+42(%rip)
movl $ip+8, %edi
movl $1, %esi
movl $54, %edx
movq %r14, %rcx
callq fwrite
movslq ip+4(%rip), %rdx
imulq ip+64(%rip), %rdx
movl $1, %esi
movq %r15, %rdi
movq %r14, %rcx
callq fwrite
movl ip(%rip), %edx
movslq ip+4(%rip), %rcx
movq %rcx, %r8
imulq ip+64(%rip), %r8
movl $.L.str.5, %edi
movq %rbx, %rsi
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movq %r14, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 32
movl $.L.str.4, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z11WriteBMPlinPhPc, .Lfunc_end1-_Z11WriteBMPlinPhPc
.cfi_endproc
# -- End function
.globl _Z23__device_stub__ImShrunkPhS_jjjjj # -- Begin function _Z23__device_stub__ImShrunkPhS_jjjjj
.p2align 4, 0x90
.type _Z23__device_stub__ImShrunkPhS_jjjjj,@function
_Z23__device_stub__ImShrunkPhS_jjjjj: # @_Z23__device_stub__ImShrunkPhS_jjjjj
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8ImShrunkPhS_jjjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z23__device_stub__ImShrunkPhS_jjjjj, .Lfunc_end2-_Z23__device_stub__ImShrunkPhS_jjjjj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3ff0624dd2f1a9fc # double 1.024
.LCPI3_1:
.quad 0x4090000000000000 # double 1024
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $2544, %rsp # imm = 0x9F0
.cfi_def_cfa_offset 2592
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $7741253943733480809, %rax # imm = 0x6B6E757268536D69
movq %rax, 304(%rsp)
movb $0, 312(%rsp)
cmpl $5, %edi
jne .LBB3_1
# %bb.2:
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, xshrink(%rip)
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, yshrink(%rip)
movq 8(%rbx), %r14
leaq 816(%rsp), %rdi
movq %r14, %rsi
callq strcpy
movq 16(%rbx), %rsi
leaq 560(%rsp), %rdi
callq strcpy
movq %r14, %rdi
callq _Z10ReadBMPlinPc
movq %rax, TheImage(%rip)
testq %rax, %rax
je .LBB3_3
# %bb.5:
movl ip(%rip), %eax
movl %eax, origHpixels(%rip)
movl ip+4(%rip), %ecx
movl %ecx, origVpixels(%rip)
movl ip+64(%rip), %edx
movl %edx, origHbytes(%rip)
imull %ecx, %edx
movl %edx, origSize(%rip)
xorl %edx, %edx
divl xshrink(%rip)
# kill: def $eax killed $eax def $rax
movl %eax, ip(%rip)
leal (%rax,%rax,2), %eax
addl $3, %eax
andl $-4, %eax
movslq %eax, %rsi
movq %rsi, ip+64(%rip)
movl %ecx, %eax
xorl %edx, %edx
divl yshrink(%rip)
movl %eax, ip+4(%rip)
movslq %eax, %rdi
imulq %rsi, %rdi
callq malloc
movq %rax, NewImage(%rip)
testq %rax, %rax
je .LBB3_3
# %bb.6:
movl $0, 36(%rsp)
leaq 36(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 36(%rsp)
je .LBB3_7
# %bb.8:
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB3_9
# %bb.11:
leaq 1072(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl 1412(%rsp), %eax
imull 1408(%rsp), %eax
imull 1416(%rsp), %eax
movl %eax, %ecx
shrl $10, %ecx
movl %eax, %edx
shrl $20, %edx
xorl %esi, %esi
cmpl $5242880, %eax # imm = 0x500000
setae %sil
cmovbq %rcx, %rdx
leal 75(,%rsi,2), %ecx
leaq 192(%rsp), %rdi
movl $.L.str.11, %esi
xorl %eax, %eax
callq sprintf
movl 1392(%rsp), %r14d
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl origSize(%rip), %esi
movl $GPUSrcImage, %edi
callq hipMalloc
movl %eax, %ebp
movslq ip+4(%rip), %rsi
imulq ip+64(%rip), %rsi
movl $GPUTgtImage, %edi
callq hipMalloc
orl %ebp, %eax
jne .LBB3_12
# %bb.13:
movq GPUSrcImage(%rip), %rdi
movq TheImage(%rip), %rsi
movl origSize(%rip), %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_14
# %bb.15:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $255, %r12d
addl ip(%rip), %r12d
shrl $8, %r12d
movl ip+4(%rip), %r15d
imull %r12d, %r15d
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%r15,%rdx), %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16:
movq GPUTgtImage(%rip), %rax
movq GPUSrcImage(%rip), %rcx
movl ip(%rip), %edx
movl xshrink(%rip), %esi
movl yshrink(%rip), %edi
movl origHpixels(%rip), %r8d
movl origHbytes(%rip), %r9d
movq %rax, 40(%rsp)
movq %rcx, 120(%rsp)
movl %edx, 68(%rsp)
movl %esi, 64(%rsp)
movl %edi, 60(%rsp)
movl %r8d, 56(%rsp)
movl %r9d, 52(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 120(%rsp), %rax
movq %rax, 136(%rsp)
leaq 68(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 60(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
leaq 52(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8ImShrunkPhS_jjjjj, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_17:
movq GPUTgtImage(%rip), %rax
movq %rax, GPUResult(%rip)
movl ip+4(%rip), %ebp
imull ip+64(%rip), %ebp
addl origSize(%rip), %ebp
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_33
# %bb.18:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq NewImage(%rip), %rdi
movq GPUResult(%rip), %rsi
movslq ip+4(%rip), %rdx
imulq ip+64(%rip), %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_19
# %bb.20:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 88(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_21
# %bb.23:
movq NewImage(%rip), %rdi
movq 16(%rbx), %rsi
callq _Z11WriteBMPlinPhPc
movl $.Lstr, %edi
callq puts@PLT
movl 1432(%rsp), %edx
movl 1436(%rsp), %ecx
leaq 1072(%rsp), %rsi
leaq 192(%rsp), %r8
movl $.L.str.18, %edi
movq %r14, %r9
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 312(%rsp), %rsi
leaq 824(%rsp), %rdx
leaq 568(%rsp), %rcx
movl $.L.str.20, %edi
movl $256, %r8d # imm = 0x100
movl %r15d, %r9d
xorl %eax, %eax
pushq %r12
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $.Lstr.3, %edi
callq puts@PLT
movl origSize(%rip), %eax
cvtsi2ss %rax, %xmm1
movss 88(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl %eax, %esi
shrl $20, %esi
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
mulsd .LCPI3_0(%rip), %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.21, %edi
movb $2, %al
callq printf
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl %ebp, %ebx
xorps %xmm1, %xmm1
cvtsi2ss %rbx, %xmm1
cvtss2sd %xmm0, %xmm0
shrl $20, %ebp
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
mulsd .LCPI3_0(%rip), %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.22, %edi
movl %ebp, %esi
movb $2, %al
callq printf
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq ip+4(%rip), %rax
imulq ip+64(%rip), %rax
cvtss2sd %xmm0, %xmm0
movq %rax, %rsi
shrq $20, %rsi
testq %rax, %rax
js .LBB3_24
# %bb.25:
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
jmp .LBB3_26
.LBB3_1:
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
jmp .LBB3_32
.LBB3_24:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB3_26:
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
mulsd .LCPI3_0(%rip), %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.23, %edi
movb $2, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl origSize(%rip), %ecx
movslq ip+4(%rip), %rax
imulq ip+64(%rip), %rax
addq %rcx, %rax
addq %rbx, %rax
movq %rax, %rsi
shrq $20, %rsi
testq %rax, %rax
js .LBB3_27
# %bb.28:
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
jmp .LBB3_29
.LBB3_27:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
addss %xmm1, %xmm1
.LBB3_29:
cvtss2sd %xmm1, %xmm1
movsd .LCPI3_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm0, %xmm2
movsd .LCPI3_1(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
mulsd %xmm3, %xmm2
divsd %xmm2, %xmm1
movl $.L.str.24, %edi
movb $2, %al
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
movq GPUSrcImage(%rip), %rdi
callq hipFree
movq GPUTgtImage(%rip), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
callq hipDeviceReset
testl %eax, %eax
jne .LBB3_30
# %bb.31:
movq TheImage(%rip), %rdi
callq free
movq NewImage(%rip), %rdi
callq free
.LBB3_32:
xorl %eax, %eax
addq $2544, %rsp # imm = 0x9F0
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 2592
movl $.Lstr.7, %edi
jmp .LBB3_4
.LBB3_7:
movl $.Lstr.5, %edi
.LBB3_4:
callq puts@PLT
movl $1, %edi
callq exit
.LBB3_9:
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
movl $63, %esi
jmp .LBB3_10
.LBB3_12:
movq stderr(%rip), %rcx
movl $.L.str.12, %edi
movl $43, %esi
jmp .LBB3_10
.LBB3_14:
movq stderr(%rip), %rcx
movl $.L.str.13, %edi
movl $30, %esi
jmp .LBB3_10
.LBB3_33:
movq stderr(%rip), %rdi
movl $.L.str.14, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_19:
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
movl $29, %esi
.LBB3_10:
movl $1, %edx
callq fwrite
movl $1, %edi
callq exit
.LBB3_21:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $47, %esi
jmp .LBB3_22
.LBB3_30:
movq stderr(%rip), %rcx
movl $.L.str.26, %edi
movl $22, %esi
.LBB3_22:
movl $1, %edx
callq fwrite
movq TheImage(%rip), %rdi
callq free
movq NewImage(%rip), %rdi
callq free
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8ImShrunkPhS_jjjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type origSize,@object # @origSize
.bss
.globl origSize
.p2align 2, 0x0
origSize:
.long 0 # 0x0
.size origSize, 4
.type TgtSize,@object # @TgtSize
.globl TgtSize
.p2align 2, 0x0
TgtSize:
.long 0 # 0x0
.size TgtSize, 4
.type xshrink,@object # @xshrink
.globl xshrink
.p2align 2, 0x0
xshrink:
.long 0 # 0x0
.size xshrink, 4
.type yshrink,@object # @yshrink
.globl yshrink
.p2align 2, 0x0
yshrink:
.long 0 # 0x0
.size yshrink, 4
.type origVpixels,@object # @origVpixels
.globl origVpixels
.p2align 2, 0x0
origVpixels:
.long 0 # 0x0
.size origVpixels, 4
.type origHpixels,@object # @origHpixels
.globl origHpixels
.p2align 2, 0x0
origHpixels:
.long 0 # 0x0
.size origHpixels, 4
.type origHbytes,@object # @origHbytes
.globl origHbytes
.p2align 2, 0x0
origHbytes:
.long 0 # 0x0
.size origHbytes, 4
.type TheImage,@object # @TheImage
.globl TheImage
.p2align 3, 0x0
TheImage:
.quad 0
.size TheImage, 8
.type NewImage,@object # @NewImage
.globl NewImage
.p2align 3, 0x0
NewImage:
.quad 0
.size NewImage, 8
.type GPUSrcImage,@object # @GPUSrcImage
.globl GPUSrcImage
.p2align 3, 0x0
GPUSrcImage:
.quad 0
.size GPUSrcImage, 8
.type GPUTgtImage,@object # @GPUTgtImage
.globl GPUTgtImage
.p2align 3, 0x0
GPUTgtImage:
.quad 0
.size GPUTgtImage, 8
.type GPUResult,@object # @GPUResult
.globl GPUResult
.p2align 3, 0x0
GPUResult:
.quad 0
.size GPUResult, 8
.type ip,@object # @ip
.globl ip
.p2align 3, 0x0
ip:
.zero 72
.size ip, 72
.type _ZZ10ReadBMPlinPcE3Img,@object # @_ZZ10ReadBMPlinPcE3Img
.local _ZZ10ReadBMPlinPcE3Img
.comm _ZZ10ReadBMPlinPcE3Img,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n%s NOT FOUND\n\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n Input File name: %17s (%u x %u) File Size=%u"
.size .L.str.2, 50
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n\nFILE CREATION ERROR: %s\n\n"
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nOutput File name: %17s (%u x %u) File Size=%u\n\n"
.size .L.str.5, 52
.type _Z8ImShrunkPhS_jjjjj,@object # @_Z8ImShrunkPhS_jjjjj
.section .rodata,"a",@progbits
.globl _Z8ImShrunkPhS_jjjjj
.p2align 3, 0x0
_Z8ImShrunkPhS_jjjjj:
.quad _Z23__device_stub__ImShrunkPhS_jjjjj
.size _Z8ImShrunkPhS_jjjjj, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "imShrunk"
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\n\nUsage: imshrunk input output xshrink yshrink"
.size .L.str.7, 47
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.10, 64
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%u %c"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipMalloc failed! Can't allocate GPU memory"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy CPU to GPU failed!"
.size .L.str.13, 31
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\n\nhipDeviceSynchronize returned error code %d after launching the kernel!\n"
.size .L.str.14, 75
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "hipMemcpy GPU to CPU failed!"
.size .L.str.15, 30
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "\n Program failed after cudaDeviceSynchronize()!"
.size .L.str.16, 48
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "%s ComputeCapab=%d.%d [max %s blocks
.size .L.str.18, 56
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%s %s %s %u [%u BLOCKS, %u BLOCKS/ROW]\n"
.size .L.str.20, 42
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.size .L.str.21, 61
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Kernel Execution =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.size .L.str.22, 61
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n"
.size .L.str.23, 61
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Total time elapsed =%7.2f ms %4d MB ... %6.2f GB/s\n"
.size .L.str.24, 61
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "hipDeviceReset failed!"
.size .L.str.26, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8ImShrunkPhS_jjjjj"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n--------------------------------------------------------------------------"
.size .Lstr, 77
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "--------------------------------------------------------------------------"
.size .Lstr.3, 75
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "--------------------------------------------------------------------------\n"
.size .Lstr.4, 76
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\nNo CUDA Device is available"
.size .Lstr.5, 29
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Cannot allocate memory for the input image..."
.size .Lstr.7, 46
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__ImShrunkPhS_jjjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym GPUSrcImage
.addrsig_sym GPUTgtImage
.addrsig_sym ip
.addrsig_sym _Z8ImShrunkPhS_jjjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
#define TILE_WIDTH 16
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void computeHistogramGPU(PPMPixel *data, int *cols, int *rows, float *h){
/*
* Nós podemos pensar que cada pixel na imagem é uma thread.
* Então devemos calcular o indice da thread na imagem
* porem como eu coloquei um bloco de 16x16 é necessário checar a posição da thread
* esta contida na imagem.
*
*/
int row = blockIdx.y * blockDim.y + threadIdx.y; //coordenada vertical da thread na imagem
int col = blockIdx.x * blockDim.x + threadIdx.x; //coordenada horizontal da thread na imagem
if(threadIdx.x == 0 && threadIdx.y == 0){
printf("ro:%d co:%d rb:%d rc:%d \n",row,col,blockIdx.y,blockIdx.x);
}
__syncthreads();
if(row < *rows && col < *cols) {
int j, k, l;
int index = 0;
//eu percebi que estes 3 loops são desnecessarios, pois poderiamos atribuir o valor do pixel no posicao correta
//do histograma fazendo h[ (data.red*16) + (data.green*4) + data.blue] += 1.
//Entretanto, eu prefiri não modificar o codigo, pois assim eu consegui obter speedups melhores.
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[(row*(*cols)) + col].red == j && data[(row*(*cols)) + col].green == k && data[(row*(*cols)) + col].blue == l) {
atomicAdd(&h[index], 1.0);//tendo certeza que apenas uma thread por vez vai modificar essa variável (acesso atómico)
}
index++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
// host
int i, cols = image->x, rows = image->y;
float n = image->y * image->x;
// device
PPMPixel *d_data;
int *d_cols, *d_rows;
float *d_h;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//variáveis necessarias para medir o tempos pedidos na tarefa
// cudaEvent_t start, stop;
// cudaEventCreate(&start);
// cudaEventCreate(&stop);
// float milliseconds = 0;
//alocando memoria na GPU para a variáveis
// cudaEventRecord(start);
cudaMalloc( (void**)&d_data, sizeof(PPMPixel)*( (int)n) ) ;
cudaMalloc( (void**)&d_cols, sizeof(int));
cudaMalloc( (void**)&d_rows, sizeof(int));
cudaMalloc( (void**)&d_h, sizeof(float) * 64);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo alocar memoria: %0.6f\n",milliseconds);
//enviado os dados da CPU para a GPU
// cudaEventRecord(start);
cudaMemcpy(d_data, image->data, sizeof(PPMPixel)*( (int)n ) , cudaMemcpyHostToDevice);
cudaMemcpy(d_cols, &cols, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_rows, &rows, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_h, h, sizeof(float) * 64, cudaMemcpyHostToDevice);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo enviar: %0.6f\n",milliseconds);
dim3 numeroBlocosNaImagem(ceil((float)cols/TILE_WIDTH), ceil((float)rows/TILE_WIDTH), 1);
dim3 numeroThreadsPorBloco(TILE_WIDTH, TILE_WIDTH, 1);
// //realizando a computação na GPU
// cudaEventRecord(start);
computeHistogramGPU<<<numeroBlocosNaImagem,numeroThreadsPorBloco>>>(d_data, d_cols, d_rows, d_h);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo computar: %0.6f\n",milliseconds);
//recenbendo o resultado da GPU (GPU -> CPU)
// cudaEventRecord(start);
cudaMemcpy(h, d_h, sizeof(float) * 64, cudaMemcpyDeviceToHost);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo receber: %0.6f\n",milliseconds);
//liberando a memória alocada na GPU
cudaFree(d_data);
cudaFree(d_cols);
cudaFree(d_rows);
cudaFree(d_h);
/*
* Normalizando os valores do histograma.
* Infelizmente quando eu realizava a normalização na GPU
* eu obtinha um valor diferente na terceira casa decimal de precisão. O mais misterioso
* era que isso so ocorria no primeiro elemento do meu vetor h. Por isso resolvi fazer
* a normalização na CPU
* */
for (i = 0; i < 64; i++){
h[i] = h[i]/n;
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
//t_start = rtclock();
Histogram(image, h);
//t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]);
}
printf("\n");
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
}
/*
* como a normalização dos valores eu fiz na CPU então o considerei o meu tempo de GPU_total sendo como
* GPU_total = tempo_GPU_criar_buffer + tempo_GPU_offload_enviar + tempo_kernel + tempo_GPU_offload_receber + GPU_total + CPU_tempo_normalizar
*
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
* | Entrada | tempo_serial | tempo_GPU_criar_buffer | tempo_GPU_offload_enviar | tempo_kernel | tempo_GPU_offload_receber | GPU_total | speedup |
* ------------------------------------------------------------------------------------------------------------------------------------------------------------
* | ar1.ppm | 0.179675s | 0.321664ms | 0.852256ms | 2.844864ms | 0.025536ms | 0.092086s | 1.951165 |
* | ar2.ppm | 0.344623s | 0.385280ms | 1.608000ms | 7.420544ms | 0.025056ms | 0.110731s | 3.112254 |
* | ar3.ppm | 1.298848s | 0.343008ms | 5.551264ms | 32.017376ms | 0.021952ms | 0.235085s | 5.525014 |
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
*
*
* */ | .file "tmpxft_0003fff3_00000000-6_hist.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
.type _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf, @function
_Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19computeHistogramGPUP8PPMPixelPiS1_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf, .-_Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
.globl _Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.type _Z19computeHistogramGPUP8PPMPixelPiS1_Pf, @function
_Z19computeHistogramGPUP8PPMPixelPiS1_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19computeHistogramGPUP8PPMPixelPiS1_Pf, .-_Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.globl _Z9HistogramP8PPMImagePf
.type _Z9HistogramP8PPMImagePf, @function
_Z9HistogramP8PPMImagePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl (%rdi), %eax
movl %eax, 24(%rsp)
movl 4(%rdi), %edx
movl %edx, 28(%rsp)
imull %edx, %eax
pxor %xmm5, %xmm5
cvtsi2ssl %eax, %xmm5
movss %xmm5, 12(%rsp)
movl $0, %eax
movl $0, %edx
pxor %xmm0, %xmm0
comiss %xmm0, %xmm5
jbe .L18
.L20:
movq %rax, %rcx
addq 8(%rbp), %rcx
shrb $6, (%rcx)
movq %rax, %rcx
addq 8(%rbp), %rcx
shrb $6, 2(%rcx)
movq %rax, %rcx
addq 8(%rbp), %rcx
shrb $6, 1(%rcx)
addl $1, %edx
addq $3, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss 12(%rsp), %xmm7
comiss %xmm0, %xmm7
ja .L20
.L18:
cvttss2sil 12(%rsp), %eax
cltq
leaq (%rax,%rax,2), %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movq 8(%rbp), %rsi
movl $1, %ecx
movq %r12, %rdx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 28(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC7(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L21:
pxor %xmm0, %xmm0
cvtsi2ssl 24(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC7(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L22
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC6(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L22:
cvttss2siq %xmm4, %rax
movl %eax, 64(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 68(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
movl $2, %ecx
movl $256, %edx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 256(%rbx), %rdx
.L24:
movss (%rax), %xmm0
divss 12(%rsp), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
jmp .L23
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9HistogramP8PPMImagePf, .-_Z9HistogramP8PPMImagePf
.section .rodata.str1.8
.align 8
.LC8:
.string "Too many or no one arguments supplied.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "rb"
.LC10:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC12:
.string "Unable to allocate memory\n"
.LC13:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC14:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC15:
.string "%d"
.section .rodata.str1.8
.align 8
.LC16:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC17:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC18:
.string "Error loading image '%s'\n"
.LC19:
.string "%0.3f "
.LC20:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L57
.L34:
movq 8(%rbx), %rbp
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L58
leaq 16(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L59
cmpb $80, 16(%rsp)
jne .L37
cmpb $54, 17(%rsp)
jne .L37
movl $16, %edi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L60
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L40
.L41:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L41
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L41
.L40:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%r12), %rcx
movq %r12, %rdx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L61
leaq 12(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L62
cmpl $255, 12(%rsp)
jne .L63
.L45:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L45
movl (%r12), %r14d
movl 4(%r12), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%r12)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movq %rax, %rdx
movslq 4(%r12), %rax
cmpq %rax, %rdx
jne .L64
movq %rbx, %rdi
call fclose@PLT
movl $256, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 256(%rax), %rbp
.L47:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L47
movq %r13, %rsi
movq %r12, %rdi
call _Z9HistogramP8PPMImagePf
leaq .LC19(%rip), %r12
.L48:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L34
.L58:
movq %rbp, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movq %rbp, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L37:
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movq %rbp, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movq %rbp, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movq %rbp, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movq %rbp, %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC21:
.string "_Z19computeHistogramGPUP8PPMPixelPiS1_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z19computeHistogramGPUP8PPMPixelPiS1_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1031798784
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
#define TILE_WIDTH 16
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void computeHistogramGPU(PPMPixel *data, int *cols, int *rows, float *h){
/*
* Nós podemos pensar que cada pixel na imagem é uma thread.
* Então devemos calcular o indice da thread na imagem
* porem como eu coloquei um bloco de 16x16 é necessário checar a posição da thread
* esta contida na imagem.
*
*/
int row = blockIdx.y * blockDim.y + threadIdx.y; //coordenada vertical da thread na imagem
int col = blockIdx.x * blockDim.x + threadIdx.x; //coordenada horizontal da thread na imagem
if(threadIdx.x == 0 && threadIdx.y == 0){
printf("ro:%d co:%d rb:%d rc:%d \n",row,col,blockIdx.y,blockIdx.x);
}
__syncthreads();
if(row < *rows && col < *cols) {
int j, k, l;
int index = 0;
//eu percebi que estes 3 loops são desnecessarios, pois poderiamos atribuir o valor do pixel no posicao correta
//do histograma fazendo h[ (data.red*16) + (data.green*4) + data.blue] += 1.
//Entretanto, eu prefiri não modificar o codigo, pois assim eu consegui obter speedups melhores.
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[(row*(*cols)) + col].red == j && data[(row*(*cols)) + col].green == k && data[(row*(*cols)) + col].blue == l) {
atomicAdd(&h[index], 1.0);//tendo certeza que apenas uma thread por vez vai modificar essa variável (acesso atómico)
}
index++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
// host
int i, cols = image->x, rows = image->y;
float n = image->y * image->x;
// device
PPMPixel *d_data;
int *d_cols, *d_rows;
float *d_h;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//variáveis necessarias para medir o tempos pedidos na tarefa
// cudaEvent_t start, stop;
// cudaEventCreate(&start);
// cudaEventCreate(&stop);
// float milliseconds = 0;
//alocando memoria na GPU para a variáveis
// cudaEventRecord(start);
cudaMalloc( (void**)&d_data, sizeof(PPMPixel)*( (int)n) ) ;
cudaMalloc( (void**)&d_cols, sizeof(int));
cudaMalloc( (void**)&d_rows, sizeof(int));
cudaMalloc( (void**)&d_h, sizeof(float) * 64);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo alocar memoria: %0.6f\n",milliseconds);
//enviado os dados da CPU para a GPU
// cudaEventRecord(start);
cudaMemcpy(d_data, image->data, sizeof(PPMPixel)*( (int)n ) , cudaMemcpyHostToDevice);
cudaMemcpy(d_cols, &cols, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_rows, &rows, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_h, h, sizeof(float) * 64, cudaMemcpyHostToDevice);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo enviar: %0.6f\n",milliseconds);
dim3 numeroBlocosNaImagem(ceil((float)cols/TILE_WIDTH), ceil((float)rows/TILE_WIDTH), 1);
dim3 numeroThreadsPorBloco(TILE_WIDTH, TILE_WIDTH, 1);
// //realizando a computação na GPU
// cudaEventRecord(start);
computeHistogramGPU<<<numeroBlocosNaImagem,numeroThreadsPorBloco>>>(d_data, d_cols, d_rows, d_h);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo computar: %0.6f\n",milliseconds);
//recenbendo o resultado da GPU (GPU -> CPU)
// cudaEventRecord(start);
cudaMemcpy(h, d_h, sizeof(float) * 64, cudaMemcpyDeviceToHost);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo receber: %0.6f\n",milliseconds);
//liberando a memória alocada na GPU
cudaFree(d_data);
cudaFree(d_cols);
cudaFree(d_rows);
cudaFree(d_h);
/*
* Normalizando os valores do histograma.
* Infelizmente quando eu realizava a normalização na GPU
* eu obtinha um valor diferente na terceira casa decimal de precisão. O mais misterioso
* era que isso so ocorria no primeiro elemento do meu vetor h. Por isso resolvi fazer
* a normalização na CPU
* */
for (i = 0; i < 64; i++){
h[i] = h[i]/n;
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
//t_start = rtclock();
Histogram(image, h);
//t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]);
}
printf("\n");
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
}
/*
* como a normalização dos valores eu fiz na CPU então o considerei o meu tempo de GPU_total sendo como
* GPU_total = tempo_GPU_criar_buffer + tempo_GPU_offload_enviar + tempo_kernel + tempo_GPU_offload_receber + GPU_total + CPU_tempo_normalizar
*
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
* | Entrada | tempo_serial | tempo_GPU_criar_buffer | tempo_GPU_offload_enviar | tempo_kernel | tempo_GPU_offload_receber | GPU_total | speedup |
* ------------------------------------------------------------------------------------------------------------------------------------------------------------
* | ar1.ppm | 0.179675s | 0.321664ms | 0.852256ms | 2.844864ms | 0.025536ms | 0.092086s | 1.951165 |
* | ar2.ppm | 0.344623s | 0.385280ms | 1.608000ms | 7.420544ms | 0.025056ms | 0.110731s | 3.112254 |
* | ar3.ppm | 1.298848s | 0.343008ms | 5.551264ms | 32.017376ms | 0.021952ms | 0.235085s | 5.525014 |
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
*
*
* */ | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
#define TILE_WIDTH 16
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void computeHistogramGPU(PPMPixel *data, int *cols, int *rows, float *h){
/*
* Nós podemos pensar que cada pixel na imagem é uma thread.
* Então devemos calcular o indice da thread na imagem
* porem como eu coloquei um bloco de 16x16 é necessário checar a posição da thread
* esta contida na imagem.
*
*/
int row = blockIdx.y * blockDim.y + threadIdx.y; //coordenada vertical da thread na imagem
int col = blockIdx.x * blockDim.x + threadIdx.x; //coordenada horizontal da thread na imagem
if(threadIdx.x == 0 && threadIdx.y == 0){
printf("ro:%d co:%d rb:%d rc:%d \n",row,col,blockIdx.y,blockIdx.x);
}
__syncthreads();
if(row < *rows && col < *cols) {
int j, k, l;
int index = 0;
//eu percebi que estes 3 loops são desnecessarios, pois poderiamos atribuir o valor do pixel no posicao correta
//do histograma fazendo h[ (data.red*16) + (data.green*4) + data.blue] += 1.
//Entretanto, eu prefiri não modificar o codigo, pois assim eu consegui obter speedups melhores.
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[(row*(*cols)) + col].red == j && data[(row*(*cols)) + col].green == k && data[(row*(*cols)) + col].blue == l) {
atomicAdd(&h[index], 1.0);//tendo certeza que apenas uma thread por vez vai modificar essa variável (acesso atómico)
}
index++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
// host
int i, cols = image->x, rows = image->y;
float n = image->y * image->x;
// device
PPMPixel *d_data;
int *d_cols, *d_rows;
float *d_h;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//variáveis necessarias para medir o tempos pedidos na tarefa
// cudaEvent_t start, stop;
// cudaEventCreate(&start);
// cudaEventCreate(&stop);
// float milliseconds = 0;
//alocando memoria na GPU para a variáveis
// cudaEventRecord(start);
hipMalloc( (void**)&d_data, sizeof(PPMPixel)*( (int)n) ) ;
hipMalloc( (void**)&d_cols, sizeof(int));
hipMalloc( (void**)&d_rows, sizeof(int));
hipMalloc( (void**)&d_h, sizeof(float) * 64);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo alocar memoria: %0.6f\n",milliseconds);
//enviado os dados da CPU para a GPU
// cudaEventRecord(start);
hipMemcpy(d_data, image->data, sizeof(PPMPixel)*( (int)n ) , hipMemcpyHostToDevice);
hipMemcpy(d_cols, &cols, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_rows, &rows, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_h, h, sizeof(float) * 64, hipMemcpyHostToDevice);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo enviar: %0.6f\n",milliseconds);
dim3 numeroBlocosNaImagem(ceil((float)cols/TILE_WIDTH), ceil((float)rows/TILE_WIDTH), 1);
dim3 numeroThreadsPorBloco(TILE_WIDTH, TILE_WIDTH, 1);
// //realizando a computação na GPU
// cudaEventRecord(start);
computeHistogramGPU<<<numeroBlocosNaImagem,numeroThreadsPorBloco>>>(d_data, d_cols, d_rows, d_h);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo computar: %0.6f\n",milliseconds);
//recenbendo o resultado da GPU (GPU -> CPU)
// cudaEventRecord(start);
hipMemcpy(h, d_h, sizeof(float) * 64, hipMemcpyDeviceToHost);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo receber: %0.6f\n",milliseconds);
//liberando a memória alocada na GPU
hipFree(d_data);
hipFree(d_cols);
hipFree(d_rows);
hipFree(d_h);
/*
* Normalizando os valores do histograma.
* Infelizmente quando eu realizava a normalização na GPU
* eu obtinha um valor diferente na terceira casa decimal de precisão. O mais misterioso
* era que isso so ocorria no primeiro elemento do meu vetor h. Por isso resolvi fazer
* a normalização na CPU
* */
for (i = 0; i < 64; i++){
h[i] = h[i]/n;
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
//t_start = rtclock();
Histogram(image, h);
//t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]);
}
printf("\n");
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
}
/*
* como a normalização dos valores eu fiz na CPU então o considerei o meu tempo de GPU_total sendo como
* GPU_total = tempo_GPU_criar_buffer + tempo_GPU_offload_enviar + tempo_kernel + tempo_GPU_offload_receber + GPU_total + CPU_tempo_normalizar
*
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
* | Entrada | tempo_serial | tempo_GPU_criar_buffer | tempo_GPU_offload_enviar | tempo_kernel | tempo_GPU_offload_receber | GPU_total | speedup |
* ------------------------------------------------------------------------------------------------------------------------------------------------------------
* | ar1.ppm | 0.179675s | 0.321664ms | 0.852256ms | 2.844864ms | 0.025536ms | 0.092086s | 1.951165 |
* | ar2.ppm | 0.344623s | 0.385280ms | 1.608000ms | 7.420544ms | 0.025056ms | 0.110731s | 3.112254 |
* | ar3.ppm | 1.298848s | 0.343008ms | 5.551264ms | 32.017376ms | 0.021952ms | 0.235085s | 5.525014 |
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
*
*
* */ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
#define TILE_WIDTH 16
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void computeHistogramGPU(PPMPixel *data, int *cols, int *rows, float *h){
/*
* Nós podemos pensar que cada pixel na imagem é uma thread.
* Então devemos calcular o indice da thread na imagem
* porem como eu coloquei um bloco de 16x16 é necessário checar a posição da thread
* esta contida na imagem.
*
*/
int row = blockIdx.y * blockDim.y + threadIdx.y; //coordenada vertical da thread na imagem
int col = blockIdx.x * blockDim.x + threadIdx.x; //coordenada horizontal da thread na imagem
if(threadIdx.x == 0 && threadIdx.y == 0){
printf("ro:%d co:%d rb:%d rc:%d \n",row,col,blockIdx.y,blockIdx.x);
}
__syncthreads();
if(row < *rows && col < *cols) {
int j, k, l;
int index = 0;
//eu percebi que estes 3 loops são desnecessarios, pois poderiamos atribuir o valor do pixel no posicao correta
//do histograma fazendo h[ (data.red*16) + (data.green*4) + data.blue] += 1.
//Entretanto, eu prefiri não modificar o codigo, pois assim eu consegui obter speedups melhores.
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[(row*(*cols)) + col].red == j && data[(row*(*cols)) + col].green == k && data[(row*(*cols)) + col].blue == l) {
atomicAdd(&h[index], 1.0);//tendo certeza que apenas uma thread por vez vai modificar essa variável (acesso atómico)
}
index++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
// host
int i, cols = image->x, rows = image->y;
float n = image->y * image->x;
// device
PPMPixel *d_data;
int *d_cols, *d_rows;
float *d_h;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//variáveis necessarias para medir o tempos pedidos na tarefa
// cudaEvent_t start, stop;
// cudaEventCreate(&start);
// cudaEventCreate(&stop);
// float milliseconds = 0;
//alocando memoria na GPU para a variáveis
// cudaEventRecord(start);
hipMalloc( (void**)&d_data, sizeof(PPMPixel)*( (int)n) ) ;
hipMalloc( (void**)&d_cols, sizeof(int));
hipMalloc( (void**)&d_rows, sizeof(int));
hipMalloc( (void**)&d_h, sizeof(float) * 64);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo alocar memoria: %0.6f\n",milliseconds);
//enviado os dados da CPU para a GPU
// cudaEventRecord(start);
hipMemcpy(d_data, image->data, sizeof(PPMPixel)*( (int)n ) , hipMemcpyHostToDevice);
hipMemcpy(d_cols, &cols, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_rows, &rows, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_h, h, sizeof(float) * 64, hipMemcpyHostToDevice);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo enviar: %0.6f\n",milliseconds);
dim3 numeroBlocosNaImagem(ceil((float)cols/TILE_WIDTH), ceil((float)rows/TILE_WIDTH), 1);
dim3 numeroThreadsPorBloco(TILE_WIDTH, TILE_WIDTH, 1);
// //realizando a computação na GPU
// cudaEventRecord(start);
computeHistogramGPU<<<numeroBlocosNaImagem,numeroThreadsPorBloco>>>(d_data, d_cols, d_rows, d_h);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo computar: %0.6f\n",milliseconds);
//recenbendo o resultado da GPU (GPU -> CPU)
// cudaEventRecord(start);
hipMemcpy(h, d_h, sizeof(float) * 64, hipMemcpyDeviceToHost);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
// printf("\ntempo receber: %0.6f\n",milliseconds);
//liberando a memória alocada na GPU
hipFree(d_data);
hipFree(d_cols);
hipFree(d_rows);
hipFree(d_h);
/*
* Normalizando os valores do histograma.
* Infelizmente quando eu realizava a normalização na GPU
* eu obtinha um valor diferente na terceira casa decimal de precisão. O mais misterioso
* era que isso so ocorria no primeiro elemento do meu vetor h. Por isso resolvi fazer
* a normalização na CPU
* */
for (i = 0; i < 64; i++){
h[i] = h[i]/n;
}
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
//double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
//t_start = rtclock();
Histogram(image, h);
//t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]);
}
printf("\n");
//fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
}
/*
* como a normalização dos valores eu fiz na CPU então o considerei o meu tempo de GPU_total sendo como
* GPU_total = tempo_GPU_criar_buffer + tempo_GPU_offload_enviar + tempo_kernel + tempo_GPU_offload_receber + GPU_total + CPU_tempo_normalizar
*
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
* | Entrada | tempo_serial | tempo_GPU_criar_buffer | tempo_GPU_offload_enviar | tempo_kernel | tempo_GPU_offload_receber | GPU_total | speedup |
* ------------------------------------------------------------------------------------------------------------------------------------------------------------
* | ar1.ppm | 0.179675s | 0.321664ms | 0.852256ms | 2.844864ms | 0.025536ms | 0.092086s | 1.951165 |
* | ar2.ppm | 0.344623s | 0.385280ms | 1.608000ms | 7.420544ms | 0.025056ms | 0.110731s | 3.112254 |
* | ar3.ppm | 1.298848s | 0.343008ms | 5.551264ms | 32.017376ms | 0.021952ms | 0.235085s | 5.525014 |
* -----------------------------------------------------------------------------------------------------------------------------------------------------------
*
*
* */ | .text
.file "hist.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf # -- Begin function _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.p2align 4, 0x90
.type _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf,@function
_Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf: # @_Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19computeHistogramGPUP8PPMPixelPiS1_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf, .Lfunc_end1-_Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9HistogramP8PPMImagePf
.LCPI2_0:
.long 0x3d800000 # float 0.0625
.text
.globl _Z9HistogramP8PPMImagePf
.p2align 4, 0x90
.type _Z9HistogramP8PPMImagePf,@function
_Z9HistogramP8PPMImagePf: # @_Z9HistogramP8PPMImagePf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl (%rdi), %eax
movl %eax, 4(%rsp)
movl 4(%rdi), %ecx
movl %ecx, (%rsp)
imull %eax, %ecx
cvtsi2ss %ecx, %xmm1
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph
movq 8(%r14), %rax
addq $2, %rax
movl $1, %ecx
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
shrb $6, -2(%rax)
shrb $6, (%rax)
shrb $6, -1(%rax)
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
addq $3, %rax
incl %ecx
ucomiss %xmm0, %xmm1
ja .LBB2_2
.LBB2_3: # %._crit_edge
movss %xmm1, 44(%rsp) # 4-byte Spill
cvttss2si %xmm1, %eax
cltq
leaq (%rax,%rax,2), %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 32(%rsp), %rdi
movq 8(%r14), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r14
xorps %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r14d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19computeHistogramGPUP8PPMPixelPiS1_Pf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
movss 44(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_6
# %bb.7:
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9HistogramP8PPMImagePf, .Lfunc_end2-_Z9HistogramP8PPMImagePf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movq 8(%rbx), %rbx
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB3_3
# %bb.5:
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB3_27
# %bb.6:
cmpb $80, 16(%rsp)
jne .LBB3_8
# %bb.7:
cmpb $54, 17(%rsp)
jne .LBB3_8
# %bb.10:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB3_11
# %bb.12:
movq %rax, %r15
.p2align 4, 0x90
.LBB3_13: # =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
movq %r14, %rdi
callq getc
cmpl $35, %eax
jne .LBB3_15
.LBB3_14: # %.preheader44.i
# Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
callq getc
cmpl $10, %eax
jne .LBB3_14
jmp .LBB3_13
.LBB3_15: # %._crit_edge.i
movl %eax, %edi
movq %r14, %rsi
callq ungetc
movq %r15, %rcx
addq $4, %rcx
movl $.L.str.8, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB3_16
# %bb.17:
leaq 12(%rsp), %rdx
movl $.L.str.10, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB3_18
# %bb.19:
cmpl $255, 12(%rsp)
jne .LBB3_20
.p2align 4, 0x90
.LBB3_21: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB3_21
# %bb.22:
movslq (%r15), %rax
movslq 4(%r15), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r15)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movslq 4(%r15), %rcx
cmpq %rcx, %rax
jne .LBB3_23
# %bb.24: # %_ZL7readPPMPKc.exit
movq %r14, %rdi
callq fclose
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movups %xmm0, 192(%rax)
movups %xmm0, 208(%rax)
movups %xmm0, 224(%rax)
movups %xmm0, 240(%rax)
movq %r15, %rdi
movq %rax, %rsi
callq _Z9HistogramP8PPMImagePf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_25: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq $64, %r14
jne .LBB3_25
# %bb.26:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
jmp .LBB3_4
.LBB3_27:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB3_8:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $36, %esi
jmp .LBB3_9
.LBB3_11:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $26, %esi
.LBB3_9:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB3_16:
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
jmp .LBB3_4
.LBB3_18:
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
jmp .LBB3_4
.LBB3_20:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
jmp .LBB3_4
.LBB3_23:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
.LBB3_4:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19computeHistogramGPUP8PPMPixelPiS1_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type _Z19computeHistogramGPUP8PPMPixelPiS1_Pf,@object # @_Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.section .rodata,"a",@progbits
.globl _Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.p2align 3, 0x0
_Z19computeHistogramGPUP8PPMPixelPiS1_Pf:
.quad _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.size _Z19computeHistogramGPUP8PPMPixelPiS1_Pf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%0.3f "
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "rb"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Unable to open file '%s'\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Unable to allocate memory\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d"
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.9, 41
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d"
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.11, 44
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.12, 38
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Error loading image '%s'\n"
.size .L.str.13, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19computeHistogramGPUP8PPMPixelPiS1_Pf"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003fff3_00000000-6_hist.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
.type _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf, @function
_Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19computeHistogramGPUP8PPMPixelPiS1_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf, .-_Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
.globl _Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.type _Z19computeHistogramGPUP8PPMPixelPiS1_Pf, @function
_Z19computeHistogramGPUP8PPMPixelPiS1_Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19computeHistogramGPUP8PPMPixelPiS1_Pf, .-_Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.globl _Z9HistogramP8PPMImagePf
.type _Z9HistogramP8PPMImagePf, @function
_Z9HistogramP8PPMImagePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl (%rdi), %eax
movl %eax, 24(%rsp)
movl 4(%rdi), %edx
movl %edx, 28(%rsp)
imull %edx, %eax
pxor %xmm5, %xmm5
cvtsi2ssl %eax, %xmm5
movss %xmm5, 12(%rsp)
movl $0, %eax
movl $0, %edx
pxor %xmm0, %xmm0
comiss %xmm0, %xmm5
jbe .L18
.L20:
movq %rax, %rcx
addq 8(%rbp), %rcx
shrb $6, (%rcx)
movq %rax, %rcx
addq 8(%rbp), %rcx
shrb $6, 2(%rcx)
movq %rax, %rcx
addq 8(%rbp), %rcx
shrb $6, 1(%rcx)
addl $1, %edx
addq $3, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss 12(%rsp), %xmm7
comiss %xmm0, %xmm7
ja .L20
.L18:
cvttss2sil 12(%rsp), %eax
cltq
leaq (%rax,%rax,2), %r12
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movq 8(%rbp), %rsi
movl $1, %ecx
movq %r12, %rdx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 28(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 28(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC7(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L21
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC6(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L21:
pxor %xmm0, %xmm0
cvtsi2ssl 24(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC7(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC4(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L22
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC6(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L22:
cvttss2siq %xmm4, %rax
movl %eax, 64(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 68(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
movl $2, %ecx
movl $256, %edx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 256(%rbx), %rdx
.L24:
movss (%rax), %xmm0
divss 12(%rsp), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z54__device_stub__Z19computeHistogramGPUP8PPMPixelPiS1_PfP8PPMPixelPiS1_Pf
jmp .L23
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9HistogramP8PPMImagePf, .-_Z9HistogramP8PPMImagePf
.section .rodata.str1.8
.align 8
.LC8:
.string "Too many or no one arguments supplied.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "rb"
.LC10:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC12:
.string "Unable to allocate memory\n"
.LC13:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC14:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC15:
.string "%d"
.section .rodata.str1.8
.align 8
.LC16:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC17:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC18:
.string "Error loading image '%s'\n"
.LC19:
.string "%0.3f "
.LC20:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L57
.L34:
movq 8(%rbx), %rbp
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L58
leaq 16(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L59
cmpb $80, 16(%rsp)
jne .L37
cmpb $54, 17(%rsp)
jne .L37
movl $16, %edi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L60
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L40
.L41:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L41
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L41
.L40:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%r12), %rcx
movq %r12, %rdx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L61
leaq 12(%rsp), %rdx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L62
cmpl $255, 12(%rsp)
jne .L63
.L45:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L45
movl (%r12), %r14d
movl 4(%r12), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%r12)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movq %rax, %rdx
movslq 4(%r12), %rax
cmpq %rax, %rdx
jne .L64
movq %rbx, %rdi
call fclose@PLT
movl $256, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 256(%rax), %rbp
.L47:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L47
movq %r13, %rsi
movq %r12, %rdi
call _Z9HistogramP8PPMImagePf
leaq .LC19(%rip), %r12
.L48:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L34
.L58:
movq %rbp, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movq %rbp, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L37:
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movq %rbp, %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movq %rbp, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movq %rbp, %rcx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movq %rbp, %rcx
leaq .LC18(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC21:
.string "_Z19computeHistogramGPUP8PPMPixelPiS1_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z19computeHistogramGPUP8PPMPixelPiS1_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1031798784
.align 4
.LC4:
.long 1258291200
.align 4
.LC6:
.long 1065353216
.align 4
.LC7:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hist.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf # -- Begin function _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.p2align 4, 0x90
.type _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf,@function
_Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf: # @_Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19computeHistogramGPUP8PPMPixelPiS1_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf, .Lfunc_end1-_Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9HistogramP8PPMImagePf
.LCPI2_0:
.long 0x3d800000 # float 0.0625
.text
.globl _Z9HistogramP8PPMImagePf
.p2align 4, 0x90
.type _Z9HistogramP8PPMImagePf,@function
_Z9HistogramP8PPMImagePf: # @_Z9HistogramP8PPMImagePf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $160, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl (%rdi), %eax
movl %eax, 4(%rsp)
movl 4(%rdi), %ecx
movl %ecx, (%rsp)
imull %eax, %ecx
cvtsi2ss %ecx, %xmm1
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph
movq 8(%r14), %rax
addq $2, %rax
movl $1, %ecx
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
shrb $6, -2(%rax)
shrb $6, (%rax)
shrb $6, -1(%rax)
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
addq $3, %rax
incl %ecx
ucomiss %xmm0, %xmm1
ja .LBB2_2
.LBB2_3: # %._crit_edge
movss %xmm1, 44(%rsp) # 4-byte Spill
cvttss2si %xmm1, %eax
cltq
leaq (%rax,%rax,2), %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq 32(%rsp), %rdi
movq 8(%r14), %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r14
xorps %xmm0, %xmm0
cvtsi2ssl (%rsp), %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r14d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rsi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19computeHistogramGPUP8PPMPixelPiS1_Pf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
movss 44(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_6
# %bb.7:
addq $160, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9HistogramP8PPMImagePf, .Lfunc_end2-_Z9HistogramP8PPMImagePf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movq 8(%rbx), %rbx
movl $.L.str.4, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB3_3
# %bb.5:
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB3_27
# %bb.6:
cmpb $80, 16(%rsp)
jne .LBB3_8
# %bb.7:
cmpb $54, 17(%rsp)
jne .LBB3_8
# %bb.10:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB3_11
# %bb.12:
movq %rax, %r15
.p2align 4, 0x90
.LBB3_13: # =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
movq %r14, %rdi
callq getc
cmpl $35, %eax
jne .LBB3_15
.LBB3_14: # %.preheader44.i
# Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movq %r14, %rdi
callq getc
cmpl $10, %eax
jne .LBB3_14
jmp .LBB3_13
.LBB3_15: # %._crit_edge.i
movl %eax, %edi
movq %r14, %rsi
callq ungetc
movq %r15, %rcx
addq $4, %rcx
movl $.L.str.8, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB3_16
# %bb.17:
leaq 12(%rsp), %rdx
movl $.L.str.10, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB3_18
# %bb.19:
cmpl $255, 12(%rsp)
jne .LBB3_20
.p2align 4, 0x90
.LBB3_21: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB3_21
# %bb.22:
movslq (%r15), %rax
movslq 4(%r15), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r15)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r14, %rcx
callq fread
movslq 4(%r15), %rcx
cmpq %rcx, %rax
jne .LBB3_23
# %bb.24: # %_ZL7readPPMPKc.exit
movq %r14, %rdi
callq fclose
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movups %xmm0, 192(%rax)
movups %xmm0, 208(%rax)
movups %xmm0, 224(%rax)
movups %xmm0, 240(%rax)
movq %r15, %rdi
movq %rax, %rsi
callq _Z9HistogramP8PPMImagePf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_25: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r14
cmpq $64, %r14
jne .LBB3_25
# %bb.26:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rdi
movl $.L.str.5, %esi
jmp .LBB3_4
.LBB3_27:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB3_8:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $36, %esi
jmp .LBB3_9
.LBB3_11:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $26, %esi
.LBB3_9:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB3_16:
movq stderr(%rip), %rdi
movl $.L.str.9, %esi
jmp .LBB3_4
.LBB3_18:
movq stderr(%rip), %rdi
movl $.L.str.11, %esi
jmp .LBB3_4
.LBB3_20:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
jmp .LBB3_4
.LBB3_23:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
.LBB3_4:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19computeHistogramGPUP8PPMPixelPiS1_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type _Z19computeHistogramGPUP8PPMPixelPiS1_Pf,@object # @_Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.section .rodata,"a",@progbits
.globl _Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.p2align 3, 0x0
_Z19computeHistogramGPUP8PPMPixelPiS1_Pf:
.quad _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.size _Z19computeHistogramGPUP8PPMPixelPiS1_Pf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%0.3f "
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "rb"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Unable to open file '%s'\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.6, 37
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Unable to allocate memory\n"
.size .L.str.7, 27
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d"
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.9, 41
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d"
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.11, 44
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.12, 38
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Error loading image '%s'\n"
.size .L.str.13, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19computeHistogramGPUP8PPMPixelPiS1_Pf"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__computeHistogramGPUP8PPMPixelPiS1_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19computeHistogramGPUP8PPMPixelPiS1_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
#ifndef REAL
#define REAL float
#endif
}
__global__ void vector_axpby (const int n, const REAL alpha, const REAL* x, const int offset_x, const int stride_x, const REAL beta, REAL* y, int offset_y, int stride_y) {
const int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < n) {
const int ix = offset_x + gid * stride_x;
const int iy = offset_y + gid * stride_y;
y[iy] = alpha * x[ix] + beta * y [iy];
}
} | code for sm_80
Function : _Z12vector_axpbyifPKfiifPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x18c] ; /* 0x0000630000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R4, R0.reuse, R5, c[0x0][0x188] ; /* 0x0000620000047624 */
/* 0x040fe400078e0205 */
/*00b0*/ IMAD R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027624 */
/* 0x000fe400078e0203 */
/*00c0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x180] ; /* 0x0000600004047625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0207 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000eaa000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FMUL R7, R0, c[0x0][0x178] ; /* 0x00005e0000077a20 */
/* 0x004fc80000400000 */
/*0110*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x008fca0000000007 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
#ifndef REAL
#define REAL float
#endif
}
__global__ void vector_axpby (const int n, const REAL alpha, const REAL* x, const int offset_x, const int stride_x, const REAL beta, REAL* y, int offset_y, int stride_y) {
const int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < n) {
const int ix = offset_x + gid * stride_x;
const int iy = offset_y + gid * stride_y;
y[iy] = alpha * x[ix] + beta * y [iy];
}
} | .file "tmpxft_00111691_00000000-6_vector_axpby.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii
.type _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii, @function
_Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm1, 20(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12vector_axpbyifPKfiifPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii, .-_Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii
.globl _Z12vector_axpbyifPKfiifPfii
.type _Z12vector_axpbyifPKfiifPfii, @function
_Z12vector_axpbyifPKfiifPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12vector_axpbyifPKfiifPfii, .-_Z12vector_axpbyifPKfiifPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12vector_axpbyifPKfiifPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vector_axpbyifPKfiifPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
#ifndef REAL
#define REAL float
#endif
}
__global__ void vector_axpby (const int n, const REAL alpha, const REAL* x, const int offset_x, const int stride_x, const REAL beta, REAL* y, int offset_y, int stride_y) {
const int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < n) {
const int ix = offset_x + gid * stride_x;
const int iy = offset_y + gid * stride_y;
y[iy] = alpha * x[ix] + beta * y [iy];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
#ifndef REAL
#define REAL float
#endif
}
__global__ void vector_axpby (const int n, const REAL alpha, const REAL* x, const int offset_x, const int stride_x, const REAL beta, REAL* y, int offset_y, int stride_y) {
const int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < n) {
const int ix = offset_x + gid * stride_x;
const int iy = offset_y + gid * stride_y;
y[iy] = alpha * x[ix] + beta * y [iy];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
#ifndef REAL
#define REAL float
#endif
}
__global__ void vector_axpby (const int n, const REAL alpha, const REAL* x, const int offset_x, const int stride_x, const REAL beta, REAL* y, int offset_y, int stride_y) {
const int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < n) {
const int ix = offset_x + gid * stride_x;
const int iy = offset_y + gid * stride_y;
y[iy] = alpha * x[ix] + beta * y [iy];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vector_axpbyifPKfiifPfii
.globl _Z12vector_axpbyifPKfiifPfii
.p2align 8
.type _Z12vector_axpbyifPKfiifPfii,@function
_Z12vector_axpbyifPKfiifPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s7, s[6:7]
v_mad_u64_u32 v[4:5], null, v1, s11, s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, s2, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vector_axpbyifPKfiifPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vector_axpbyifPKfiifPfii, .Lfunc_end0-_Z12vector_axpbyifPKfiifPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vector_axpbyifPKfiifPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vector_axpbyifPKfiifPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
#ifndef REAL
#define REAL float
#endif
}
__global__ void vector_axpby (const int n, const REAL alpha, const REAL* x, const int offset_x, const int stride_x, const REAL beta, REAL* y, int offset_y, int stride_y) {
const int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < n) {
const int ix = offset_x + gid * stride_x;
const int iy = offset_y + gid * stride_y;
y[iy] = alpha * x[ix] + beta * y [iy];
}
} | .text
.file "vector_axpby.hip"
.globl _Z27__device_stub__vector_axpbyifPKfiifPfii # -- Begin function _Z27__device_stub__vector_axpbyifPKfiifPfii
.p2align 4, 0x90
.type _Z27__device_stub__vector_axpbyifPKfiifPfii,@function
_Z27__device_stub__vector_axpbyifPKfiifPfii: # @_Z27__device_stub__vector_axpbyifPKfiifPfii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 88(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %r8, 80(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12vector_axpbyifPKfiifPfii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__vector_axpbyifPKfiifPfii, .Lfunc_end0-_Z27__device_stub__vector_axpbyifPKfiifPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vector_axpbyifPKfiifPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vector_axpbyifPKfiifPfii,@object # @_Z12vector_axpbyifPKfiifPfii
.section .rodata,"a",@progbits
.globl _Z12vector_axpbyifPKfiifPfii
.p2align 3, 0x0
_Z12vector_axpbyifPKfiifPfii:
.quad _Z27__device_stub__vector_axpbyifPKfiifPfii
.size _Z12vector_axpbyifPKfiifPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vector_axpbyifPKfiifPfii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vector_axpbyifPKfiifPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vector_axpbyifPKfiifPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vector_axpbyifPKfiifPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R5, c[0x0][0x18c] ; /* 0x0000630000057a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fc60000000f00 */
/*00a0*/ IMAD R4, R0.reuse, R5, c[0x0][0x188] ; /* 0x0000620000047624 */
/* 0x040fe400078e0205 */
/*00b0*/ IMAD R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027624 */
/* 0x000fe400078e0203 */
/*00c0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x180] ; /* 0x0000600004047625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0207 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000eaa000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FMUL R7, R0, c[0x0][0x178] ; /* 0x00005e0000077a20 */
/* 0x004fc80000400000 */
/*0110*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x008fca0000000007 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vector_axpbyifPKfiifPfii
.globl _Z12vector_axpbyifPKfiifPfii
.p2align 8
.type _Z12vector_axpbyifPKfiifPfii,@function
_Z12vector_axpbyifPKfiifPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x3
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b128 s[8:11], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s7, s[6:7]
v_mad_u64_u32 v[4:5], null, v1, s11, s[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, s2, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vector_axpbyifPKfiifPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vector_axpbyifPKfiifPfii, .Lfunc_end0-_Z12vector_axpbyifPKfiifPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vector_axpbyifPKfiifPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vector_axpbyifPKfiifPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00111691_00000000-6_vector_axpby.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii
.type _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii, @function
_Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movss %xmm1, 20(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12vector_axpbyifPKfiifPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii, .-_Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii
.globl _Z12vector_axpbyifPKfiifPfii
.type _Z12vector_axpbyifPKfiifPfii, @function
_Z12vector_axpbyifPKfiifPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z12vector_axpbyifPKfiifPfiiifPKfiifPfii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12vector_axpbyifPKfiifPfii, .-_Z12vector_axpbyifPKfiifPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12vector_axpbyifPKfiifPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vector_axpbyifPKfiifPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_axpby.hip"
.globl _Z27__device_stub__vector_axpbyifPKfiifPfii # -- Begin function _Z27__device_stub__vector_axpbyifPKfiifPfii
.p2align 4, 0x90
.type _Z27__device_stub__vector_axpbyifPKfiifPfii,@function
_Z27__device_stub__vector_axpbyifPKfiifPfii: # @_Z27__device_stub__vector_axpbyifPKfiifPfii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 88(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %r8, 80(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12vector_axpbyifPKfiifPfii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__vector_axpbyifPKfiifPfii, .Lfunc_end0-_Z27__device_stub__vector_axpbyifPKfiifPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vector_axpbyifPKfiifPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vector_axpbyifPKfiifPfii,@object # @_Z12vector_axpbyifPKfiifPfii
.section .rodata,"a",@progbits
.globl _Z12vector_axpbyifPKfiifPfii
.p2align 3, 0x0
_Z12vector_axpbyifPKfiifPfii:
.quad _Z27__device_stub__vector_axpbyifPKfiifPfii
.size _Z12vector_axpbyifPKfiifPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vector_axpbyifPKfiifPfii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vector_axpbyifPKfiifPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vector_axpbyifPKfiifPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void countQueens(int* frontQueensPos, int* data, int* numFQP)
{
int localResult = 0;
//printf("%d\n", numFQP[0]);
int thisThread = ((blockIdx.x * gridDim.x + blockIdx.y) * gridDim.y + threadIdx.x)* blockDim.x + threadIdx.y;
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
if (blockIdx.x >= QUEENS || blockIdx.y >= QUEENS || threadIdx.x >= QUEENS || threadIdx.y >= QUEENS)
return;
int* queenPos = new int[QUEENS];
queenPos[3] = blockIdx.x;
queenPos[4] = blockIdx.y;
queenPos[5] = threadIdx.x;
queenPos[6] = threadIdx.y;
for (int i = 4; i <= 6; i++) {
for (int j = 3; j < i; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
return;
}
}
}
int totalFQP = numFQP[0] / 3;
for (int FQP_number = 0; FQP_number < totalFQP; FQP_number++) {
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
for (int i = 0; i < 3; i++)
queenPos[i] = frontQueensPos[(FQP_number * 3) + i];
bool legal = true;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], totalFQP);
for (int i = 3; i <= 6; i++) {
for (int j = 0; j < 3; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
break;
}
if (!legal)
continue;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], localResult);
//printf("1_%d %d %d %d %d %d %d\n", thisThread, queenPos[2], blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
//backtrace
int posNow = 7;
queenPos[posNow] = -1;
while (posNow > 6) {
queenPos[posNow] ++;
while (queenPos[posNow] < QUEENS) {
legal = true;
for (int j = posNow - 1; j >= 0; j--) {
if ((queenPos[posNow] - posNow) == (queenPos[j] - j) || (queenPos[posNow] + posNow) == (queenPos[j] + j) || queenPos[posNow] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
queenPos[posNow] ++;
else
break;
}
if (queenPos[posNow] < QUEENS) {
if (posNow == (QUEENS - 1)) {
localResult++;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2_%d %d %d %d %d %d %d_%d\n", queenPos[7], queenPos[8], queenPos[9], queenPos[10], queenPos[11], queenPos[12], queenPos[13], localResult);
posNow--;
}
else {
posNow++;
queenPos[posNow] = -1;
}
}
else
posNow--;
}
}
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2.5_%d\n", localResult);
data[thisThread] = localResult;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("3_%d %d %d %d %d %d\n", thisThread, blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
} | code for sm_80
Function : _Z11countQueensPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002600 */
/*0020*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e680000002500 */
/*0030*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000ea80000002100 */
/*0040*/ S2R R18, SR_TID.Y ; /* 0x0000000000127919 */
/* 0x000ee20000002200 */
/*0050*/ ISETP.GT.U32.AND P0, PT, R17, 0xd, PT ; /* 0x0000000d1100780c */
/* 0x001fc80003f04070 */
/*0060*/ ISETP.GT.U32.OR P0, PT, R16, 0xd, P0 ; /* 0x0000000d1000780c */
/* 0x002fc80000704470 */
/*0070*/ ISETP.GT.U32.OR P0, PT, R19, 0xd, P0 ; /* 0x0000000d1300780c */
/* 0x004fc80000704470 */
/*0080*/ ISETP.GT.U32.OR P0, PT, R18, 0xd, P0 ; /* 0x0000000d1200780c */
/* 0x008fda0000704470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x38 ; /* 0x00000038ff047424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00e0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*00f0*/ LEPC R6 ; /* 0x000000000006734e */
/* 0x000fe20000000000 */
/*0100*/ MOV R9, 0x170 ; /* 0x0000017000097802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R20, 0xf0 ; /* 0x000000f000147802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*0140*/ IADD3 R20, P0, P1, -R20, R9, R6 ; /* 0x0000000914147210 */
/* 0x000fc8000791e106 */
/*0150*/ IADD3.X R21, ~R0, R21, R7, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2507 */
/*0160*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0170*/ IADD3 R7, R17.reuse, 0x1, RZ ; /* 0x0000000111077810 */
/* 0x040fe20007ffe0ff */
/*0180*/ ST.E [R4.64+0xc], R16 ; /* 0x00000c1004007985 */
/* 0x0001e2000c101924 */
/*0190*/ IADD3 R3, R17, -0x1, RZ ; /* 0xffffffff11037810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.NE.AND P0, PT, R7, R16.reuse, PT ; /* 0x000000100700720c */
/* 0x080fe20003f05270 */
/*01b0*/ ST.E [R4.64+0x10], R17 ; /* 0x0000101104007985 */
/* 0x0001e2000c101924 */
/*01c0*/ IADD3 R7, R19, 0x2, RZ ; /* 0x0000000213077810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.EQ.OR P0, PT, R3, R16, !P0 ; /* 0x000000100300720c */
/* 0x000fe20004702670 */
/*01e0*/ ST.E [R4.64+0x14], R19 ; /* 0x0000141304007985 */
/* 0x0001e2000c101924 */
/*01f0*/ IADD3 R3, R19, -0x2, RZ ; /* 0xfffffffe13037810 */
/* 0x000fc40007ffe0ff */
/*0200*/ ISETP.EQ.OR P0, PT, R17, R16.reuse, P0 ; /* 0x000000101100720c */
/* 0x080fe20000702670 */
/*0210*/ ST.E [R4.64+0x18], R18 ; /* 0x0000181204007985 */
/* 0x0001e2000c101924 */
/*0220*/ IADD3 R0, R19, -0x1, RZ ; /* 0xffffffff13007810 */
/* 0x000fe40007ffe0ff */
/*0230*/ ISETP.EQ.OR P0, PT, R3, R16.reuse, P0 ; /* 0x000000100300720c */
/* 0x080fe40000702670 */
/*0240*/ IADD3 R2, R19, 0x1, RZ ; /* 0x0000000113027810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.EQ.OR P0, PT, R7, R16, P0 ; /* 0x000000100700720c */
/* 0x000fc80000702670 */
/*0260*/ ISETP.EQ.OR P0, PT, R19, R16, P0 ; /* 0x000000101300720c */
/* 0x000fc80000702670 */
/*0270*/ ISETP.EQ.OR P0, PT, R0, R17, P0 ; /* 0x000000110000720c */
/* 0x000fc80000702670 */
/*0280*/ ISETP.EQ.OR P0, PT, R2, R17, P0 ; /* 0x000000110200720c */
/* 0x000fc80000702670 */
/*0290*/ ISETP.EQ.OR P0, PT, R19, R17, P0 ; /* 0x000000111300720c */
/* 0x000fda0000702670 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R7, R18.reuse, 0x3, RZ ; /* 0x0000000312077810 */
/* 0x041fe40007ffe0ff */
/*02c0*/ IADD3 R3, R18.reuse, -0x3, RZ ; /* 0xfffffffd12037810 */
/* 0x040fe40007ffe0ff */
/*02d0*/ ISETP.NE.AND P0, PT, R7, R16.reuse, PT ; /* 0x000000100700720c */
/* 0x080fe40003f05270 */
/*02e0*/ IADD3 R0, R18.reuse, -0x2, RZ ; /* 0xfffffffe12007810 */
/* 0x040fe40007ffe0ff */
/*02f0*/ ISETP.EQ.OR P0, PT, R3, R16, !P0 ; /* 0x000000100300720c */
/* 0x000fe40004702670 */
/*0300*/ IADD3 R2, R18, 0x2, RZ ; /* 0x0000000212027810 */
/* 0x000fc40007ffe0ff */
/*0310*/ ISETP.EQ.OR P0, PT, R18, R16, P0 ; /* 0x000000101200720c */
/* 0x000fc80000702670 */
/*0320*/ ISETP.EQ.OR P0, PT, R0, R17.reuse, P0 ; /* 0x000000110000720c */
/* 0x080fe40000702670 */
/*0330*/ IADD3 R0, R18, -0x1, RZ ; /* 0xffffffff12007810 */
/* 0x000fe40007ffe0ff */
/*0340*/ ISETP.EQ.OR P0, PT, R2, R17.reuse, P0 ; /* 0x000000110200720c */
/* 0x080fe40000702670 */
/*0350*/ IADD3 R2, R18.reuse, 0x1, RZ ; /* 0x0000000112027810 */
/* 0x040fe40007ffe0ff */
/*0360*/ ISETP.EQ.OR P0, PT, R18, R17, P0 ; /* 0x000000111200720c */
/* 0x000fc80000702670 */
/*0370*/ ISETP.EQ.OR P0, PT, R0, R19, P0 ; /* 0x000000130000720c */
/* 0x000fc80000702670 */
/*0380*/ ISETP.EQ.OR P0, PT, R2, R19, P0 ; /* 0x000000130200720c */
/* 0x000fc80000702670 */
/*0390*/ ISETP.EQ.OR P0, PT, R18, R19, P0 ; /* 0x000000131200720c */
/* 0x000fda0000702670 */
/*03a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*03d0*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD R16, R16, c[0x0][0xc], R17 ; /* 0x0000030010107a24 */
/* 0x000fe400078e0211 */
/*03f0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0400*/ IMAD R19, R16, c[0x0][0x10], R19 ; /* 0x0000040010137a24 */
/* 0x000fc800078e0213 */
/*0410*/ IMAD R18, R19, c[0x0][0x0], R18 ; /* 0x0000000013127a24 */
/* 0x000fe200078e0212 */
/*0420*/ ISETP.GE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x004fda0003f06270 */
/*0430*/ @!P0 BRA 0xda0 ; /* 0x0000096000008947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.HI R3, R2, 0x55555556, RZ ; /* 0x5555555602037827 */
/* 0x000fe200078e02ff */
/*0450*/ BSSY B0, 0xda0 ; /* 0x0000094000007945 */
/* 0x000fe60003800000 */
/*0460*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0470*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fe200078f08ff */
/*0480*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0490*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*04a0*/ LD.E R14, [R4.64+0xc] ; /* 0x00000c24040e7980 */
/* 0x000ea2000c101900 */
/*04b0*/ IMAD R12, R2, 0x3, RZ ; /* 0x00000003020c7824 */
/* 0x000fc800078e02ff */
/*04c0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e020d */
/*04d0*/ LDG.E R7, [R12.64] ; /* 0x000000240c077981 */
/* 0x003ee8000c1e1900 */
/*04e0*/ ST.E [R4.64], R7 ; /* 0x0000000704007985 */
/* 0x0081e8000c101924 */
/*04f0*/ LDG.E R9, [R12.64+0x4] ; /* 0x000004240c097981 */
/* 0x000ee2000c1e1900 */
/*0500*/ IADD3 R8, R14, 0x3, RZ ; /* 0x000000030e087810 */
/* 0x004fc60007ffe0ff */
/*0510*/ ST.E [R4.64+0x4], R9 ; /* 0x0000040904007985 */
/* 0x0081e8000c101924 */
/*0520*/ LDG.E R11, [R12.64+0x8] ; /* 0x000008240c0b7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IADD3 R6, R14, -0x3, RZ ; /* 0xfffffffd0e067810 */
/* 0x000fe40007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fc80003f05270 */
/*0550*/ ISETP.EQ.OR P0, PT, R6, R7, !P0 ; /* 0x000000070600720c */
/* 0x000fe20004702670 */
/*0560*/ BSSY B1, 0x680 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*0570*/ PRMT R6, RZ, 0x7610, R6 ; /* 0x00007610ff067816 */
/* 0x000fe20000000006 */
/*0580*/ ST.E [R4.64+0x8], R11 ; /* 0x0000080b04007985 */
/* 0x0041f4000c101924 */
/*0590*/ @P0 BRA 0x670 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ IADD3 R8, R14.reuse, -0x2, RZ ; /* 0xfffffffe0e087810 */
/* 0x040fe40007ffe0ff */
/*05b0*/ IADD3 R10, R14, 0x1, RZ ; /* 0x000000010e0a7810 */
/* 0x000fc40007ffe0ff */
/*05c0*/ ISETP.NE.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f05270 */
/*05d0*/ IADD3 R8, R14.reuse, 0x2, RZ ; /* 0x000000020e087810 */
/* 0x040fe40007ffe0ff */
/*05e0*/ ISETP.EQ.OR P0, PT, R14, R7, !P0 ; /* 0x000000070e00720c */
/* 0x000fc80004702670 */
/*05f0*/ ISETP.EQ.OR P0, PT, R8, R9.reuse, P0 ; /* 0x000000090800720c */
/* 0x080fe40000702670 */
/*0600*/ IADD3 R8, R14.reuse, -0x1, RZ ; /* 0xffffffff0e087810 */
/* 0x040fe40007ffe0ff */
/*0610*/ ISETP.EQ.OR P0, PT, R14, R9, P0 ; /* 0x000000090e00720c */
/* 0x000fc80000702670 */
/*0620*/ ISETP.EQ.OR P0, PT, R8, R11, P0 ; /* 0x0000000b0800720c */
/* 0x000fc80000702670 */
/*0630*/ ISETP.EQ.OR P0, PT, R10, R11, P0 ; /* 0x0000000b0a00720c */
/* 0x000fda0000702670 */
/*0640*/ @!P0 ISETP.NE.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00820c */
/* 0x000fc80003f25270 */
/*0650*/ @!P0 SEL R8, RZ, 0x1, !P1 ; /* 0x00000001ff088807 */
/* 0x000fc80004800000 */
/*0660*/ @!P0 PRMT R6, R8, 0x7610, R6 ; /* 0x0000761008068816 */
/* 0x000fe40000000006 */
/*0670*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0680*/ PRMT R8, R6, 0x9910, RZ ; /* 0x0000991006087816 */
/* 0x000fe200000000ff */
/*0690*/ BSSY B1, 0xa40 ; /* 0x000003a000017945 */
/* 0x000fe20003800000 */
/*06a0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*06c0*/ ISETP.GE.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe40003f26270 */
/*06d0*/ PRMT R8, RZ, 0x7610, R8 ; /* 0x00007610ff087816 */
/* 0x000fd20000000008 */
/*06e0*/ @!P0 BRA 0xa30 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*06f0*/ LD.E R10, [R4.64+0x10] ; /* 0x00001024040a7980 */
/* 0x000ea4000c101900 */
/*0700*/ IADD3 R14, R10.reuse, 0x4, RZ ; /* 0x000000040a0e7810 */
/* 0x044fe40007ffe0ff */
/*0710*/ IADD3 R12, R10, -0x4, RZ ; /* 0xfffffffc0a0c7810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P0, PT, R14, R7.reuse, PT ; /* 0x000000070e00720c */
/* 0x080fe40003f05270 */
/*0730*/ IADD3 R14, R10, 0x3, RZ ; /* 0x000000030a0e7810 */
/* 0x000fe40007ffe0ff */
/*0740*/ ISETP.EQ.OR P0, PT, R12, R7, !P0 ; /* 0x000000070c00720c */
/* 0x000fc40004702670 */
/*0750*/ IADD3 R12, R10.reuse, -0x3, RZ ; /* 0xfffffffd0a0c7810 */
/* 0x040fe40007ffe0ff */
/*0760*/ ISETP.EQ.OR P0, PT, R10, R7, P0 ; /* 0x000000070a00720c */
/* 0x000fc80000702670 */
/*0770*/ ISETP.EQ.OR P0, PT, R12, R9.reuse, P0 ; /* 0x000000090c00720c */
/* 0x080fe40000702670 */
/*0780*/ IADD3 R12, R10, -0x2, RZ ; /* 0xfffffffe0a0c7810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.EQ.OR P0, PT, R14, R9.reuse, P0 ; /* 0x000000090e00720c */
/* 0x080fe40000702670 */
/*07a0*/ IADD3 R14, R10.reuse, 0x2, RZ ; /* 0x000000020a0e7810 */
/* 0x040fe40007ffe0ff */
/*07b0*/ ISETP.EQ.OR P0, PT, R10, R9, P0 ; /* 0x000000090a00720c */
/* 0x000fc80000702670 */
/*07c0*/ ISETP.EQ.OR P0, PT, R12, R11, P0 ; /* 0x0000000b0c00720c */
/* 0x000fc80000702670 */
/*07d0*/ ISETP.EQ.OR P0, PT, R14, R11, P0 ; /* 0x0000000b0e00720c */
/* 0x000fc80000702670 */
/*07e0*/ ISETP.EQ.OR P0, PT, R10, R11, P0 ; /* 0x0000000b0a00720c */
/* 0x000fda0000702670 */
/*07f0*/ @P0 BRA 0xa30 ; /* 0x0000023000000947 */
/* 0x000fea0003800000 */
/*0800*/ LD.E R10, [R4.64+0x14] ; /* 0x00001424040a7980 */
/* 0x000ea4000c101900 */
/*0810*/ IADD3 R14, R10.reuse, 0x5, RZ ; /* 0x000000050a0e7810 */
/* 0x044fe40007ffe0ff */
/*0820*/ IADD3 R12, R10, -0x5, RZ ; /* 0xfffffffb0a0c7810 */
/* 0x000fe40007ffe0ff */
/*0830*/ ISETP.NE.AND P0, PT, R14, R7.reuse, PT ; /* 0x000000070e00720c */
/* 0x080fe40003f05270 */
/*0840*/ IADD3 R14, R10, 0x4, RZ ; /* 0x000000040a0e7810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.EQ.OR P0, PT, R12, R7, !P0 ; /* 0x000000070c00720c */
/* 0x000fc40004702670 */
/*0860*/ IADD3 R12, R10.reuse, -0x4, RZ ; /* 0xfffffffc0a0c7810 */
/* 0x040fe40007ffe0ff */
/*0870*/ ISETP.EQ.OR P0, PT, R10, R7, P0 ; /* 0x000000070a00720c */
/* 0x000fc80000702670 */
/*0880*/ ISETP.EQ.OR P0, PT, R12, R9.reuse, P0 ; /* 0x000000090c00720c */
/* 0x080fe40000702670 */
/*0890*/ IADD3 R12, R10, -0x3, RZ ; /* 0xfffffffd0a0c7810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ ISETP.EQ.OR P0, PT, R14, R9.reuse, P0 ; /* 0x000000090e00720c */
/* 0x080fe40000702670 */
/*08b0*/ IADD3 R14, R10.reuse, 0x3, RZ ; /* 0x000000030a0e7810 */
/* 0x040fe40007ffe0ff */
/*08c0*/ ISETP.EQ.OR P0, PT, R10, R9, P0 ; /* 0x000000090a00720c */
/* 0x000fc80000702670 */
/*08d0*/ ISETP.EQ.OR P0, PT, R12, R11, P0 ; /* 0x0000000b0c00720c */
/* 0x000fc80000702670 */
/*08e0*/ ISETP.EQ.OR P0, PT, R14, R11, P0 ; /* 0x0000000b0e00720c */
/* 0x000fc80000702670 */
/*08f0*/ ISETP.EQ.OR P0, PT, R10, R11, P0 ; /* 0x0000000b0a00720c */
/* 0x000fda0000702670 */
/*0900*/ @P0 BRA 0xa30 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0910*/ LD.E R8, [R4.64+0x18] ; /* 0x0000182404087980 */
/* 0x000ea4000c101900 */
/*0920*/ IADD3 R12, R8.reuse, 0x6, RZ ; /* 0x00000006080c7810 */
/* 0x044fe40007ffe0ff */
/*0930*/ IADD3 R10, R8, -0x6, RZ ; /* 0xfffffffa080a7810 */
/* 0x000fe40007ffe0ff */
/*0940*/ ISETP.NE.AND P0, PT, R12, R7.reuse, PT ; /* 0x000000070c00720c */
/* 0x080fe40003f05270 */
/*0950*/ IADD3 R12, R8, 0x5, RZ ; /* 0x00000005080c7810 */
/* 0x000fe40007ffe0ff */
/*0960*/ ISETP.EQ.OR P0, PT, R10, R7, !P0 ; /* 0x000000070a00720c */
/* 0x000fc40004702670 */
/*0970*/ IADD3 R10, R8.reuse, -0x5, RZ ; /* 0xfffffffb080a7810 */
/* 0x040fe40007ffe0ff */
/*0980*/ ISETP.EQ.OR P0, PT, R8, R7, P0 ; /* 0x000000070800720c */
/* 0x000fc80000702670 */
/*0990*/ ISETP.EQ.OR P0, PT, R10, R9.reuse, P0 ; /* 0x000000090a00720c */
/* 0x080fe40000702670 */
/*09a0*/ IADD3 R10, R8, -0x4, RZ ; /* 0xfffffffc080a7810 */
/* 0x000fe40007ffe0ff */
/*09b0*/ ISETP.EQ.OR P0, PT, R12, R9.reuse, P0 ; /* 0x000000090c00720c */
/* 0x080fe40000702670 */
/*09c0*/ IADD3 R12, R8.reuse, 0x4, RZ ; /* 0x00000004080c7810 */
/* 0x040fe40007ffe0ff */
/*09d0*/ ISETP.EQ.OR P0, PT, R8, R9, P0 ; /* 0x000000090800720c */
/* 0x000fc80000702670 */
/*09e0*/ ISETP.EQ.OR P0, PT, R10, R11, P0 ; /* 0x0000000b0a00720c */
/* 0x000fc80000702670 */
/*09f0*/ ISETP.EQ.OR P0, PT, R12, R11, P0 ; /* 0x0000000b0c00720c */
/* 0x000fc80000702670 */
/*0a00*/ ISETP.EQ.OR P0, PT, R8, R11, P0 ; /* 0x0000000b0800720c */
/* 0x000fc80000702670 */
/*0a10*/ SEL R6, R6, RZ, !P0 ; /* 0x000000ff06067207 */
/* 0x000fc80004000000 */
/*0a20*/ PRMT R8, R6, 0x7610, R8 ; /* 0x0000761006087816 */
/* 0x000fe40000000008 */
/*0a30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a40*/ PRMT R6, R8, 0x9910, RZ ; /* 0x0000991008067816 */
/* 0x000fe200000000ff */
/*0a50*/ BSSY B1, 0xd80 ; /* 0x0000032000017945 */
/* 0x000fe60003800000 */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0a70*/ @!P0 BRA 0xd70 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*0a80*/ IMAD.MOV.U32 R7, RZ, RZ, -0x1 ; /* 0xffffffffff077424 */
/* 0x001fe400078e00ff */
/*0a90*/ IMAD.MOV.U32 R11, RZ, RZ, 0x7 ; /* 0x00000007ff0b7424 */
/* 0x000fc600078e00ff */
/*0aa0*/ ST.E [R4.64+0x1c], R7 ; /* 0x00001c0704007985 */
/* 0x0001e8000c101924 */
/*0ab0*/ IMAD.WIDE R6, R11, 0x4, R4 ; /* 0x000000040b067825 */
/* 0x003fca00078e0204 */
/*0ac0*/ LD.E R8, [R6.64] ; /* 0x0000002406087980 */
/* 0x000ea2000c101900 */
/*0ad0*/ BSSY B2, 0xca0 ; /* 0x000001c000027945 */
/* 0x000fe20003800000 */
/*0ae0*/ IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000b */
/*0af0*/ IADD3 R10, R8.reuse, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x044fe40007ffe0ff */
/*0b00*/ ISETP.GT.AND P0, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f04270 */
/*0b10*/ ST.E [R6.64], R10 ; /* 0x0000000a06007985 */
/* 0x0001f4000c101924 */
/*0b20*/ @P0 BRA 0xc90 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0b30*/ BSSY B3, 0xc40 ; /* 0x0000010000037945 */
/* 0x000fe20003800000 */
/*0b40*/ IMAD.IADD R17, R10, 0x1, -R11 ; /* 0x000000010a117824 */
/* 0x000fc400078e0a0b */
/*0b50*/ IMAD.IADD R19, R10, 0x1, R11.reuse ; /* 0x000000010a137824 */
/* 0x100fe400078e020b */
/*0b60*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x002fca00078e000b */
/*0b70*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*0b80*/ @!P0 BREAK B3 ; /* 0x0000000000038942 */
/* 0x000fe20003800000 */
/*0b90*/ @!P0 BRA 0xc90 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ IADD3 R13, R13, -0x1, RZ ; /* 0xffffffff0d0d7810 */
/* 0x000fca0007ffe0ff */
/*0bb0*/ IMAD.WIDE R8, R13, 0x4, R4 ; /* 0x000000040d087825 */
/* 0x000fcc00078e0204 */
/*0bc0*/ LD.E R8, [R8.64] ; /* 0x0000002408087980 */
/* 0x000ea4000c101900 */
/*0bd0*/ IMAD.IADD R14, R13, 0x1, R8 ; /* 0x000000010d0e7824 */
/* 0x004fe200078e0208 */
/*0be0*/ ISETP.NE.AND P2, PT, R10, R8, PT ; /* 0x000000080a00720c */
/* 0x000fe20003f45270 */
/*0bf0*/ IMAD.IADD R12, R8, 0x1, -R13 ; /* 0x00000001080c7824 */
/* 0x000fc600078e0a0d */
/*0c00*/ ISETP.NE.AND P0, PT, R14, R19, PT ; /* 0x000000130e00720c */
/* 0x000fc80003f05270 */
/*0c10*/ ISETP.NE.AND P0, PT, R12, R17, P0 ; /* 0x000000110c00720c */
/* 0x000fda0000705270 */
/*0c20*/ @P0 BRA P2, 0xb70 ; /* 0xffffff4000000947 */
/* 0x000fea000103ffff */
/*0c30*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c40*/ IADD3 R9, R10.reuse, 0x1, RZ ; /* 0x000000010a097810 */
/* 0x040fe40007ffe0ff */
/*0c50*/ ISETP.GE.AND P0, PT, R10, 0xd, PT ; /* 0x0000000d0a00780c */
/* 0x000fc60003f06270 */
/*0c60*/ ST.E [R6.64], R9 ; /* 0x0000000906007985 */
/* 0x0003e2000c101924 */
/*0c70*/ IMAD.MOV.U32 R10, RZ, RZ, R9 ; /* 0x000000ffff0a7224 */
/* 0x001fd200078e0009 */
/*0c80*/ @!P0 BRA 0xb30 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*0c90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ca0*/ ISETP.GE.AND P0, PT, R10, 0xe, PT ; /* 0x0000000e0a00780c */
/* 0x000fe20003f06270 */
/*0cb0*/ BSSY B2, 0xd50 ; /* 0x0000009000027945 */
/* 0x000fd80003800000 */
/*0cc0*/ @P0 IADD3 R11, R11, -0x1, RZ ; /* 0xffffffff0b0b0810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ @P0 BRA 0xd40 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0ce0*/ ISETP.NE.AND P0, PT, R15, 0xd, PT ; /* 0x0000000d0f00780c */
/* 0x000fda0003f05270 */
/*0cf0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, -0x1 ; /* 0xffffffffff090424 */
/* 0x002fe200078e00ff */
/*0d00*/ @P0 IADD3 R11, R15, 0x1, RZ ; /* 0x000000010f0b0810 */
/* 0x000fe20007ffe0ff */
/*0d10*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0xc ; /* 0x0000000cff0b8424 */
/* 0x000fe200078e00ff */
/*0d20*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ @P0 ST.E [R6.64+0x4], R9 ; /* 0x0000040906000985 */
/* 0x0003e8000c101924 */
/*0d40*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d50*/ ISETP.GT.AND P0, PT, R11, 0x6, PT ; /* 0x000000060b00780c */
/* 0x000fda0003f04270 */
/*0d60*/ @P0 BRA 0xab0 ; /* 0xfffffd4000000947 */
/* 0x000fea000383ffff */
/*0d70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d80*/ @!P1 BRA 0x490 ; /* 0xfffff70000009947 */
/* 0x000fea000383ffff */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0db0*/ IMAD.WIDE R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fca00078e0213 */
/*0dc0*/ STG.E [R18.64], R0 ; /* 0x0000000012007986 */
/* 0x000fe2000c101924 */
/*0dd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0de0*/ BRA 0xde0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void countQueens(int* frontQueensPos, int* data, int* numFQP)
{
int localResult = 0;
//printf("%d\n", numFQP[0]);
int thisThread = ((blockIdx.x * gridDim.x + blockIdx.y) * gridDim.y + threadIdx.x)* blockDim.x + threadIdx.y;
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
if (blockIdx.x >= QUEENS || blockIdx.y >= QUEENS || threadIdx.x >= QUEENS || threadIdx.y >= QUEENS)
return;
int* queenPos = new int[QUEENS];
queenPos[3] = blockIdx.x;
queenPos[4] = blockIdx.y;
queenPos[5] = threadIdx.x;
queenPos[6] = threadIdx.y;
for (int i = 4; i <= 6; i++) {
for (int j = 3; j < i; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
return;
}
}
}
int totalFQP = numFQP[0] / 3;
for (int FQP_number = 0; FQP_number < totalFQP; FQP_number++) {
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
for (int i = 0; i < 3; i++)
queenPos[i] = frontQueensPos[(FQP_number * 3) + i];
bool legal = true;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], totalFQP);
for (int i = 3; i <= 6; i++) {
for (int j = 0; j < 3; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
break;
}
if (!legal)
continue;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], localResult);
//printf("1_%d %d %d %d %d %d %d\n", thisThread, queenPos[2], blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
//backtrace
int posNow = 7;
queenPos[posNow] = -1;
while (posNow > 6) {
queenPos[posNow] ++;
while (queenPos[posNow] < QUEENS) {
legal = true;
for (int j = posNow - 1; j >= 0; j--) {
if ((queenPos[posNow] - posNow) == (queenPos[j] - j) || (queenPos[posNow] + posNow) == (queenPos[j] + j) || queenPos[posNow] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
queenPos[posNow] ++;
else
break;
}
if (queenPos[posNow] < QUEENS) {
if (posNow == (QUEENS - 1)) {
localResult++;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2_%d %d %d %d %d %d %d_%d\n", queenPos[7], queenPos[8], queenPos[9], queenPos[10], queenPos[11], queenPos[12], queenPos[13], localResult);
posNow--;
}
else {
posNow++;
queenPos[posNow] = -1;
}
}
else
posNow--;
}
}
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2.5_%d\n", localResult);
data[thisThread] = localResult;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("3_%d %d %d %d %d %d\n", thisThread, blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
} | .file "tmpxft_0003c579_00000000-6_countQueens.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11countQueensPiS_S_PiS_S_
.type _Z35__device_stub__Z11countQueensPiS_S_PiS_S_, @function
_Z35__device_stub__Z11countQueensPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11countQueensPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11countQueensPiS_S_PiS_S_, .-_Z35__device_stub__Z11countQueensPiS_S_PiS_S_
.globl _Z11countQueensPiS_S_
.type _Z11countQueensPiS_S_, @function
_Z11countQueensPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11countQueensPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11countQueensPiS_S_, .-_Z11countQueensPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11countQueensPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11countQueensPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void countQueens(int* frontQueensPos, int* data, int* numFQP)
{
int localResult = 0;
//printf("%d\n", numFQP[0]);
int thisThread = ((blockIdx.x * gridDim.x + blockIdx.y) * gridDim.y + threadIdx.x)* blockDim.x + threadIdx.y;
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
if (blockIdx.x >= QUEENS || blockIdx.y >= QUEENS || threadIdx.x >= QUEENS || threadIdx.y >= QUEENS)
return;
int* queenPos = new int[QUEENS];
queenPos[3] = blockIdx.x;
queenPos[4] = blockIdx.y;
queenPos[5] = threadIdx.x;
queenPos[6] = threadIdx.y;
for (int i = 4; i <= 6; i++) {
for (int j = 3; j < i; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
return;
}
}
}
int totalFQP = numFQP[0] / 3;
for (int FQP_number = 0; FQP_number < totalFQP; FQP_number++) {
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
for (int i = 0; i < 3; i++)
queenPos[i] = frontQueensPos[(FQP_number * 3) + i];
bool legal = true;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], totalFQP);
for (int i = 3; i <= 6; i++) {
for (int j = 0; j < 3; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
break;
}
if (!legal)
continue;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], localResult);
//printf("1_%d %d %d %d %d %d %d\n", thisThread, queenPos[2], blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
//backtrace
int posNow = 7;
queenPos[posNow] = -1;
while (posNow > 6) {
queenPos[posNow] ++;
while (queenPos[posNow] < QUEENS) {
legal = true;
for (int j = posNow - 1; j >= 0; j--) {
if ((queenPos[posNow] - posNow) == (queenPos[j] - j) || (queenPos[posNow] + posNow) == (queenPos[j] + j) || queenPos[posNow] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
queenPos[posNow] ++;
else
break;
}
if (queenPos[posNow] < QUEENS) {
if (posNow == (QUEENS - 1)) {
localResult++;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2_%d %d %d %d %d %d %d_%d\n", queenPos[7], queenPos[8], queenPos[9], queenPos[10], queenPos[11], queenPos[12], queenPos[13], localResult);
posNow--;
}
else {
posNow++;
queenPos[posNow] = -1;
}
}
else
posNow--;
}
}
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2.5_%d\n", localResult);
data[thisThread] = localResult;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("3_%d %d %d %d %d %d\n", thisThread, blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void countQueens(int* frontQueensPos, int* data, int* numFQP)
{
int localResult = 0;
//printf("%d\n", numFQP[0]);
int thisThread = ((blockIdx.x * gridDim.x + blockIdx.y) * gridDim.y + threadIdx.x)* blockDim.x + threadIdx.y;
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
if (blockIdx.x >= QUEENS || blockIdx.y >= QUEENS || threadIdx.x >= QUEENS || threadIdx.y >= QUEENS)
return;
int* queenPos = new int[QUEENS];
queenPos[3] = blockIdx.x;
queenPos[4] = blockIdx.y;
queenPos[5] = threadIdx.x;
queenPos[6] = threadIdx.y;
for (int i = 4; i <= 6; i++) {
for (int j = 3; j < i; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
return;
}
}
}
int totalFQP = numFQP[0] / 3;
for (int FQP_number = 0; FQP_number < totalFQP; FQP_number++) {
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
for (int i = 0; i < 3; i++)
queenPos[i] = frontQueensPos[(FQP_number * 3) + i];
bool legal = true;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], totalFQP);
for (int i = 3; i <= 6; i++) {
for (int j = 0; j < 3; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
break;
}
if (!legal)
continue;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], localResult);
//printf("1_%d %d %d %d %d %d %d\n", thisThread, queenPos[2], blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
//backtrace
int posNow = 7;
queenPos[posNow] = -1;
while (posNow > 6) {
queenPos[posNow] ++;
while (queenPos[posNow] < QUEENS) {
legal = true;
for (int j = posNow - 1; j >= 0; j--) {
if ((queenPos[posNow] - posNow) == (queenPos[j] - j) || (queenPos[posNow] + posNow) == (queenPos[j] + j) || queenPos[posNow] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
queenPos[posNow] ++;
else
break;
}
if (queenPos[posNow] < QUEENS) {
if (posNow == (QUEENS - 1)) {
localResult++;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2_%d %d %d %d %d %d %d_%d\n", queenPos[7], queenPos[8], queenPos[9], queenPos[10], queenPos[11], queenPos[12], queenPos[13], localResult);
posNow--;
}
else {
posNow++;
queenPos[posNow] = -1;
}
}
else
posNow--;
}
}
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2.5_%d\n", localResult);
data[thisThread] = localResult;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("3_%d %d %d %d %d %d\n", thisThread, blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void countQueens(int* frontQueensPos, int* data, int* numFQP)
{
int localResult = 0;
//printf("%d\n", numFQP[0]);
int thisThread = ((blockIdx.x * gridDim.x + blockIdx.y) * gridDim.y + threadIdx.x)* blockDim.x + threadIdx.y;
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
if (blockIdx.x >= QUEENS || blockIdx.y >= QUEENS || threadIdx.x >= QUEENS || threadIdx.y >= QUEENS)
return;
int* queenPos = new int[QUEENS];
queenPos[3] = blockIdx.x;
queenPos[4] = blockIdx.y;
queenPos[5] = threadIdx.x;
queenPos[6] = threadIdx.y;
for (int i = 4; i <= 6; i++) {
for (int j = 3; j < i; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
return;
}
}
}
int totalFQP = numFQP[0] / 3;
for (int FQP_number = 0; FQP_number < totalFQP; FQP_number++) {
// printf("1_%d %d %d %d %d %d %d %d\n", thisThread, blockIdx.x, gridDim.x, blockIdx.y, gridDim.y, threadIdx.x, blockDim.x, threadIdx.y);
// if (thisThread >= QUEENS * QUEENS * QUEENS * QUEENS)
// return;
for (int i = 0; i < 3; i++)
queenPos[i] = frontQueensPos[(FQP_number * 3) + i];
bool legal = true;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], totalFQP);
for (int i = 3; i <= 6; i++) {
for (int j = 0; j < 3; j++) {
if ((queenPos[i] - i) == (queenPos[j] - j) || (queenPos[i] + i) == (queenPos[j] + j) || queenPos[i] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
break;
}
if (!legal)
continue;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("1_%d %d %d %d %d %d %d_%d\n", queenPos[0], queenPos[1], queenPos[2], queenPos[3], queenPos[4], queenPos[5], queenPos[6], localResult);
//printf("1_%d %d %d %d %d %d %d\n", thisThread, queenPos[2], blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
//backtrace
int posNow = 7;
queenPos[posNow] = -1;
while (posNow > 6) {
queenPos[posNow] ++;
while (queenPos[posNow] < QUEENS) {
legal = true;
for (int j = posNow - 1; j >= 0; j--) {
if ((queenPos[posNow] - posNow) == (queenPos[j] - j) || (queenPos[posNow] + posNow) == (queenPos[j] + j) || queenPos[posNow] == queenPos[j]) {
legal = false;
break;
}
}
if (!legal)
queenPos[posNow] ++;
else
break;
}
if (queenPos[posNow] < QUEENS) {
if (posNow == (QUEENS - 1)) {
localResult++;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2_%d %d %d %d %d %d %d_%d\n", queenPos[7], queenPos[8], queenPos[9], queenPos[10], queenPos[11], queenPos[12], queenPos[13], localResult);
posNow--;
}
else {
posNow++;
queenPos[posNow] = -1;
}
}
else
posNow--;
}
}
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("2.5_%d\n", localResult);
data[thisThread] = localResult;
//if (blockIdx.x == 6 && blockIdx.y == 11 && threadIdx.x == 9 && threadIdx.y == 12)
// printf("3_%d %d %d %d %d %d\n", thisThread, blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, data[thisThread]);
} | .text
.file "countQueens.hip"
.globl _Z26__device_stub__countQueensPiS_S_ # -- Begin function _Z26__device_stub__countQueensPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__countQueensPiS_S_,@function
_Z26__device_stub__countQueensPiS_S_: # @_Z26__device_stub__countQueensPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11countQueensPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__countQueensPiS_S_, .Lfunc_end0-_Z26__device_stub__countQueensPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11countQueensPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11countQueensPiS_S_,@object # @_Z11countQueensPiS_S_
.section .rodata,"a",@progbits
.globl _Z11countQueensPiS_S_
.p2align 3, 0x0
_Z11countQueensPiS_S_:
.quad _Z26__device_stub__countQueensPiS_S_
.size _Z11countQueensPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11countQueensPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__countQueensPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11countQueensPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003c579_00000000-6_countQueens.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11countQueensPiS_S_PiS_S_
.type _Z35__device_stub__Z11countQueensPiS_S_PiS_S_, @function
_Z35__device_stub__Z11countQueensPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11countQueensPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11countQueensPiS_S_PiS_S_, .-_Z35__device_stub__Z11countQueensPiS_S_PiS_S_
.globl _Z11countQueensPiS_S_
.type _Z11countQueensPiS_S_, @function
_Z11countQueensPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11countQueensPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11countQueensPiS_S_, .-_Z11countQueensPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11countQueensPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11countQueensPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "countQueens.hip"
.globl _Z26__device_stub__countQueensPiS_S_ # -- Begin function _Z26__device_stub__countQueensPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__countQueensPiS_S_,@function
_Z26__device_stub__countQueensPiS_S_: # @_Z26__device_stub__countQueensPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11countQueensPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__countQueensPiS_S_, .Lfunc_end0-_Z26__device_stub__countQueensPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11countQueensPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11countQueensPiS_S_,@object # @_Z11countQueensPiS_S_
.section .rodata,"a",@progbits
.globl _Z11countQueensPiS_S_
.p2align 3, 0x0
_Z11countQueensPiS_S_:
.quad _Z26__device_stub__countQueensPiS_S_
.size _Z11countQueensPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11countQueensPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__countQueensPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11countQueensPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <thrust/version.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/reduce.h>
#include <thrust/fill.h>
// examples
// [1] https://github.com/thrust/thrust/wiki/Quick-Start-Guide
void thrust_reduce_by_key(thrust::device_vector<int> &d_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len);
void reduce_by_key_v1(thrust::device_vector<int> &d_keys,
thrust::device_vector<int> &d_norep_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len);
__global__ void reduce_by_key_kernel_v1 (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output);
__global__ void reduce_by_key_kernel_more (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output);
int main(void)
{
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
cudaSetDevice(0);
int major = THRUST_MAJOR_VERSION;
int minor = THRUST_MINOR_VERSION;
std::cout << "Thrust v" << major << "." << minor << std::endl;
//-----------------------------------------------------------------------//
std::cout << "initialize keys on the host\n";
const int Len = 2047;
const int Ksize = 124;
int REAP = Len / Ksize;
thrust::host_vector<int> h_keys(Len);
thrust::host_vector<float> h_array(Len);
for(int i=0; i<Len; i++) {
//int ii = i / 7;
int ii = i / REAP;
int k = Ksize - (ii + 1); // repeat the value
if(k <0) k =0;
h_keys[i] = k;
h_array[i] = (float) k;
//std::cout << h_keys[i] << " ";
}
//std::cout << std::endl;
//-----------------------------------------------------------------------//
std::cout << "no-repeat keys in order\n";
thrust::host_vector<int> h_norep_keys;
int prev, curr;
for(int i=0; i<Len; i++) {
if(i==0) {
prev = h_keys[i];
h_norep_keys.push_back(prev);
continue;
}
curr = h_keys[i];
if(curr != prev) {
h_norep_keys.push_back(curr);
prev = curr;
}
}
std::cout << "no repeat keys size = " << h_norep_keys.size() << std::endl;
if(h_norep_keys.size() != Ksize) {
std::cerr << "Ksize is not equal to norep_keys.size()\n";
return -1;
}
for(int i=0; i<h_norep_keys.size(); i++) {
std::cout << h_norep_keys[i] << " ";
}
std::cout << std::endl;
//-----------------------------------------------------------------------//
std::cout << "\ncopy host to device\n";
thrust::device_vector<int> d_keys=h_keys;
thrust::device_vector<int> d_norep_keys=h_norep_keys;
thrust::device_vector<float> d_array=h_array;
//-----------------------------------------------------------------------//
std::cout << "\ntesting thrust::reduce_by_key\n";
thrust_reduce_by_key(d_keys, d_array, Ksize, Len);
//-----------------------------------------------------------------------//
std::cout << "\ntesting customized reduce_by_key (v1)\n";
reduce_by_key_v1(d_keys, d_norep_keys, d_array, Ksize, Len);
return 0;
}
void thrust_reduce_by_key(thrust::device_vector<int> &d_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float local_ms;
float gputime_ms = 0.f;
// initialize output
thrust::device_vector<int> d_out_keys(Ksize, 0);
thrust::device_vector<float> d_out_vals(Ksize, 0.f);
for(int reps=0; reps<100; reps++)
{
local_ms = 0.f;
cudaEventRecord(start, 0);
thrust::reduce_by_key(d_keys.begin(),
d_keys.end(),
d_array.begin(),
d_out_keys.begin(),
d_out_vals.begin()
);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&local_ms, start, stop);
gputime_ms += local_ms;
}
printf("(thrust::reduce_by_key) runtime = %lf (ms)\n", gputime_ms * 0.01);
thrust::host_vector<int> h_out_keys;
thrust::host_vector<float> h_out_vals;
h_out_keys = d_out_keys;
h_out_vals = d_out_vals;
//---------------------//
// check output
//---------------------//
std::cout << "\noutput keys\n";
for(int i=0; i<h_out_keys.size(); i++) {
std::cout << h_out_keys[i] << " ";
}
std::cout << std::endl;
std::cout << "\noutput vals\n";
for(int i=0; i<h_out_vals.size(); i++) {
std::cout << h_out_vals[i] << " ";
}
std::cout << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
__global__ void reduce_by_key_kernel_v1 (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output)
{
__shared__ int sm_keys[256];
__shared__ float sm_vals[256];
int lid = threadIdx.x;
if(lid < Ksize) { // 124
sm_keys[lid] = g_norep_keys[lid];
sm_vals[lid] = 0.f;
}
__syncthreads();
if(lid < Len) {
int my_key = g_keys[lid];
float my_val = g_input[lid];
for(int i=0; i<Ksize; i++) {
if(my_key == sm_keys[i]) {
atomicAdd(&sm_vals[i], my_val);
break;
}
}
}
__syncthreads();
if(lid < Ksize) {
g_output[lid] = sm_vals[lid];
}
}
__global__ void reduce_by_key_kernel_more (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output)
{
__shared__ int sm_keys[1024];
__shared__ float sm_vals[1024];
int lid = threadIdx.x;
int gid = threadIdx.x + blockIdx.x * blockDim.x;
// norep_keys should be smaller than 1024, and the size of shared memory
if(lid < Ksize) {
sm_keys[lid] = g_norep_keys[lid];
sm_vals[lid] = 0.f;
}
__syncthreads();
if(gid < Len) {
int my_key = g_keys[gid];
float my_val = g_input[gid];
for(int i=0; i<Ksize; i++) {
if(my_key == sm_keys[i]) {
atomicAdd(&sm_vals[i], my_val);
break;
}
}
}
__syncthreads();
if(lid < Ksize) {
atomicAdd(&g_output[lid], sm_vals[lid]);
}
}
void reduce_by_key_v1(thrust::device_vector<int> &d_keys,
thrust::device_vector<int> &d_norep_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float local_ms;
float gputime_ms = 0.f;
// initialize output
thrust::device_vector<float> d_out_vals(Ksize, 0.f);
int *g_keys = thrust::raw_pointer_cast(d_keys.data());
int *g_norep_keys = thrust::raw_pointer_cast(d_norep_keys.data());
float *g_input = thrust::raw_pointer_cast(d_array.data());
float *g_output = thrust::raw_pointer_cast(d_out_vals.data());
if(Len > 1024) {
dim3 Grds(1,1,1);
dim3 Blks(1024,1,1);
Grds.x = (int) (Len + 1023) / 1024;
// Measure the runtime
for(int reps=0; reps<100; reps++)
{
thrust::fill(d_out_vals.begin(), d_out_vals.end(), 0.f);
local_ms = 0.f;
cudaEventRecord(start, 0);
reduce_by_key_kernel_more <<< Grds, Blks >>> (g_keys,
g_norep_keys,
g_input,
Ksize,
Len,
g_output // this needs to be initialize to zeros
);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&local_ms, start, stop);
gputime_ms += local_ms;
}
printf("(reduce_by_key_more) runtime = %lf (ms)\n", gputime_ms * 0.01);
}else{
dim3 Grds(1,1,1);
dim3 Blks(Len,1,1);
// Measure the runtime
for(int reps=0; reps<100; reps++)
{
local_ms = 0.f;
cudaEventRecord(start, 0);
// NOTE: need to write a template for customization
reduce_by_key_kernel_v1 <<< Grds, Blks >>> (g_keys,
g_norep_keys,
g_input,
Ksize,
Len,
g_output
);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&local_ms, start, stop);
gputime_ms += local_ms;
}
printf("(reduce_by_key_v1) runtime = %lf (ms)\n", gputime_ms * 0.01);
}
thrust::host_vector<float> h_out_vals;
h_out_vals = d_out_vals;
//---------------------//
// check output
//---------------------//
std::cout << "\noutput vals\n";
for(int i=0; i<h_out_vals.size(); i++) {
std::cout << h_out_vals[i] << " ";
}
std::cout << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/version.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/reduce.h>
#include <thrust/fill.h>
// examples
// [1] https://github.com/thrust/thrust/wiki/Quick-Start-Guide
void thrust_reduce_by_key(thrust::device_vector<int> &d_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len);
void reduce_by_key_v1(thrust::device_vector<int> &d_keys,
thrust::device_vector<int> &d_norep_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len);
__global__ void reduce_by_key_kernel_v1 (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output);
__global__ void reduce_by_key_kernel_more (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output);
int main(void)
{
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, 0);
printf("Device name: %s\n", prop.name);
hipSetDevice(0);
int major = THRUST_MAJOR_VERSION;
int minor = THRUST_MINOR_VERSION;
std::cout << "Thrust v" << major << "." << minor << std::endl;
//-----------------------------------------------------------------------//
std::cout << "initialize keys on the host\n";
const int Len = 2047;
const int Ksize = 124;
int REAP = Len / Ksize;
thrust::host_vector<int> h_keys(Len);
thrust::host_vector<float> h_array(Len);
for(int i=0; i<Len; i++) {
//int ii = i / 7;
int ii = i / REAP;
int k = Ksize - (ii + 1); // repeat the value
if(k <0) k =0;
h_keys[i] = k;
h_array[i] = (float) k;
//std::cout << h_keys[i] << " ";
}
//std::cout << std::endl;
//-----------------------------------------------------------------------//
std::cout << "no-repeat keys in order\n";
thrust::host_vector<int> h_norep_keys;
int prev, curr;
for(int i=0; i<Len; i++) {
if(i==0) {
prev = h_keys[i];
h_norep_keys.push_back(prev);
continue;
}
curr = h_keys[i];
if(curr != prev) {
h_norep_keys.push_back(curr);
prev = curr;
}
}
std::cout << "no repeat keys size = " << h_norep_keys.size() << std::endl;
if(h_norep_keys.size() != Ksize) {
std::cerr << "Ksize is not equal to norep_keys.size()\n";
return -1;
}
for(int i=0; i<h_norep_keys.size(); i++) {
std::cout << h_norep_keys[i] << " ";
}
std::cout << std::endl;
//-----------------------------------------------------------------------//
std::cout << "\ncopy host to device\n";
thrust::device_vector<int> d_keys=h_keys;
thrust::device_vector<int> d_norep_keys=h_norep_keys;
thrust::device_vector<float> d_array=h_array;
//-----------------------------------------------------------------------//
std::cout << "\ntesting thrust::reduce_by_key\n";
thrust_reduce_by_key(d_keys, d_array, Ksize, Len);
//-----------------------------------------------------------------------//
std::cout << "\ntesting customized reduce_by_key (v1)\n";
reduce_by_key_v1(d_keys, d_norep_keys, d_array, Ksize, Len);
return 0;
}
void thrust_reduce_by_key(thrust::device_vector<int> &d_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float local_ms;
float gputime_ms = 0.f;
// initialize output
thrust::device_vector<int> d_out_keys(Ksize, 0);
thrust::device_vector<float> d_out_vals(Ksize, 0.f);
for(int reps=0; reps<100; reps++)
{
local_ms = 0.f;
hipEventRecord(start, 0);
thrust::reduce_by_key(d_keys.begin(),
d_keys.end(),
d_array.begin(),
d_out_keys.begin(),
d_out_vals.begin()
);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&local_ms, start, stop);
gputime_ms += local_ms;
}
printf("(thrust::reduce_by_key) runtime = %lf (ms)\n", gputime_ms * 0.01);
thrust::host_vector<int> h_out_keys;
thrust::host_vector<float> h_out_vals;
h_out_keys = d_out_keys;
h_out_vals = d_out_vals;
//---------------------//
// check output
//---------------------//
std::cout << "\noutput keys\n";
for(int i=0; i<h_out_keys.size(); i++) {
std::cout << h_out_keys[i] << " ";
}
std::cout << std::endl;
std::cout << "\noutput vals\n";
for(int i=0; i<h_out_vals.size(); i++) {
std::cout << h_out_vals[i] << " ";
}
std::cout << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
}
__global__ void reduce_by_key_kernel_v1 (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output)
{
__shared__ int sm_keys[256];
__shared__ float sm_vals[256];
int lid = threadIdx.x;
if(lid < Ksize) { // 124
sm_keys[lid] = g_norep_keys[lid];
sm_vals[lid] = 0.f;
}
__syncthreads();
if(lid < Len) {
int my_key = g_keys[lid];
float my_val = g_input[lid];
for(int i=0; i<Ksize; i++) {
if(my_key == sm_keys[i]) {
atomicAdd(&sm_vals[i], my_val);
break;
}
}
}
__syncthreads();
if(lid < Ksize) {
g_output[lid] = sm_vals[lid];
}
}
__global__ void reduce_by_key_kernel_more (int* g_keys,
int* g_norep_keys,
float* g_input,
const int Ksize,
const int Len,
float* g_output)
{
__shared__ int sm_keys[1024];
__shared__ float sm_vals[1024];
int lid = threadIdx.x;
int gid = threadIdx.x + blockIdx.x * blockDim.x;
// norep_keys should be smaller than 1024, and the size of shared memory
if(lid < Ksize) {
sm_keys[lid] = g_norep_keys[lid];
sm_vals[lid] = 0.f;
}
__syncthreads();
if(gid < Len) {
int my_key = g_keys[gid];
float my_val = g_input[gid];
for(int i=0; i<Ksize; i++) {
if(my_key == sm_keys[i]) {
atomicAdd(&sm_vals[i], my_val);
break;
}
}
}
__syncthreads();
if(lid < Ksize) {
atomicAdd(&g_output[lid], sm_vals[lid]);
}
}
void reduce_by_key_v1(thrust::device_vector<int> &d_keys,
thrust::device_vector<int> &d_norep_keys,
thrust::device_vector<float> &d_array,
const int Ksize, const int Len)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float local_ms;
float gputime_ms = 0.f;
// initialize output
thrust::device_vector<float> d_out_vals(Ksize, 0.f);
int *g_keys = thrust::raw_pointer_cast(d_keys.data());
int *g_norep_keys = thrust::raw_pointer_cast(d_norep_keys.data());
float *g_input = thrust::raw_pointer_cast(d_array.data());
float *g_output = thrust::raw_pointer_cast(d_out_vals.data());
if(Len > 1024) {
dim3 Grds(1,1,1);
dim3 Blks(1024,1,1);
Grds.x = (int) (Len + 1023) / 1024;
// Measure the runtime
for(int reps=0; reps<100; reps++)
{
thrust::fill(d_out_vals.begin(), d_out_vals.end(), 0.f);
local_ms = 0.f;
hipEventRecord(start, 0);
reduce_by_key_kernel_more <<< Grds, Blks >>> (g_keys,
g_norep_keys,
g_input,
Ksize,
Len,
g_output // this needs to be initialize to zeros
);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&local_ms, start, stop);
gputime_ms += local_ms;
}
printf("(reduce_by_key_more) runtime = %lf (ms)\n", gputime_ms * 0.01);
}else{
dim3 Grds(1,1,1);
dim3 Blks(Len,1,1);
// Measure the runtime
for(int reps=0; reps<100; reps++)
{
local_ms = 0.f;
hipEventRecord(start, 0);
// NOTE: need to write a template for customization
reduce_by_key_kernel_v1 <<< Grds, Blks >>> (g_keys,
g_norep_keys,
g_input,
Ksize,
Len,
g_output
);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&local_ms, start, stop);
gputime_ms += local_ms;
}
printf("(reduce_by_key_v1) runtime = %lf (ms)\n", gputime_ms * 0.01);
}
thrust::host_vector<float> h_out_vals;
h_out_vals = d_out_vals;
//---------------------//
// check output
//---------------------//
std::cout << "\noutput vals\n";
for(int i=0; i<h_out_vals.size(); i++) {
std::cout << h_out_vals[i] << " ";
}
std::cout << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//kernel
__global__ void Matmul(float *A,float *B,float *C,int wA,int wC,int hC){
int i = blockDim.x*blockIdx.x+threadIdx.x;
int j = blockDim.y*blockIdx.y+threadIdx.y;
int k;
float tmp = 0.0f;
for(k=0;k<wA;k++){
tmp += A[k+j*wC] * B[i+k*hC];
}
C[i+j*wC] = tmp;
}
//C function
void init(float *A, int wA, int hA) {
for (int h=0; h<hA; h++)
for (int w=0; w<wA; w++)
A[w+h*wA] = (float)rand() / (float)RAND_MAX;
}
void compute(float *A, float *B, float *C,int wA, int hA, int wB) {
for (int h=0; h<hA; h++) {
for (int w=0; w<wB; w++) {
float temp = 0.0f;
for (int i=0; i<wA; i++)
temp += A[i+h*wA] * B[w+i*wB];
C[w+h*wB] = temp;
}
}
}
int main() {
float cpu_time;
int iter, max_iter = 10;
int wA = 320, hA = 320, wB = 640, hB = 320;
int wC = wB, hC = hA;
size_t sizeA = wA*hA*sizeof(float);
size_t sizeB = wB*hB*sizeof(float);
size_t sizeC = hA*wB*sizeof(float);
float *A, *B, *C;
A = (float*) malloc(sizeA);
B = (float*) malloc(sizeB);
C = (float*) malloc(sizeC);
// seed random number generator
srand(time(NULL));
// initialize A
init(A, wA, hA);
init(B, wB, hB);
//prepare memory in cuda
float *dA =NULL;
float *dB =NULL;
float *dC =NULL;
cudaMalloc((void**)&dA,sizeA);
cudaMalloc((void**)&dB,sizeB);
cudaMalloc((void**)&dC,sizeC);
//coppy input value from host to cuda
cudaMemcpy(dA,A,sizeA,cudaMemcpyHostToDevice);
cudaMemcpy(dB,B,sizeB,cudaMemcpyHostToDevice);
//execution configurtion
dim3 dimG(wC/32,hC/32);
dim3 dimB(32,32);
// compute matric C
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
for (iter=0; iter<max_iter; iter++){
Matmul<<<dimG,dimB>>>(dA,dB,dC,wA,wC,hC);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_time,start,stop);
printf("CPU time = %lf s\n", cpu_time*0.001/max_iter);
//coppy output value from cuda to host
cudaMemcpy(C,dC,sizeC,cudaMemcpyDeviceToHost);
//result check
///*
float *Check;
Check = (float*) malloc(sizeC);
compute(A, B, Check, wA, hA, wB);
float sum = 0.0f;
for (int h=0; h<hC; h++) {
for (int w=0; w<wC; w++) {
sum += C[w+h*wC]-Check[w+h*wC];
}
}
printf("Check result %f (should be zero)\n", sum/(hC*wC));
free(Check);
//*/
//free memory
free(A);
free(B);
free(C);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
return 0;
} | code for sm_80
Function : _Z6MatmulPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R2, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002027a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xc10 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R4.reuse, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xb00 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R29, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1d7435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R28, R0, R29, c[0x0][0x168] ; /* 0x00005a00001c7625 */
/* 0x000fcc00078e021d */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R6, R8.reuse, 0x4, R28 ; /* 0x0000000408067825 */
/* 0x040fe400078e021c */
/*0270*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c040c0a7981 */
/* 0x000f28000c1e1900 */
/*0280*/ IMAD.WIDE R18, R8.reuse, 0x4, R6 ; /* 0x0000000408127825 */
/* 0x040fe200078e0206 */
/*0290*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IMAD.WIDE R24, R8, 0x4, R18 ; /* 0x0000000408187825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000326000c1e1900 */
/*02d0*/ IMAD.WIDE R28, R8.reuse, 0x4, R24 ; /* 0x00000004081c7825 */
/* 0x041fe200078e0218 */
/*02e0*/ LDG.E R21, [R24.64] ; /* 0x0000000418157981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x002368000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x000f22000c1e1900 */
/*0310*/ IMAD.WIDE R22, R8, 0x4, R28 ; /* 0x0000000408167825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x000f68000c1e1900 */
/*0330*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD.WIDE R22, R8, 0x4, R22 ; /* 0x0000000408167825 */
/* 0x001fca00078e0216 */
/*0360*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000162000c1e1900 */
/*0370*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x000fca00078e0216 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x002362000c1e1900 */
/*0390*/ FFMA R29, R14, R15, R27 ; /* 0x0000000f0e1d7223 */
/* 0x004fc6000000001b */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R14, R8, 0x4, R24 ; /* 0x00000004080e7825 */
/* 0x000fc800078e0218 */
/*03c0*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe4000000001d */
/*03d0*/ IMAD.WIDE R16, R8, 0x4, R14 ; /* 0x0000000408107825 */
/* 0x000fe400078e020e */
/*03e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a8000c1e1900 */
/*03f0*/ LDG.E R15, [R12.64+0x28] ; /* 0x000028040c0f7981 */
/* 0x008ee2000c1e1900 */
/*0400*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0410*/ IMAD.WIDE R18, R8, 0x4, R16 ; /* 0x0000000408127825 */
/* 0x000fc400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0430*/ FFMA R10, R21, R10, R29 ; /* 0x0000000a150a7223 */
/* 0x000fe4000000001d */
/*0440*/ IMAD.WIDE R22, R8.reuse, 0x4, R18 ; /* 0x0000000408167825 */
/* 0x041fe200078e0212 */
/*0450*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ee2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x002fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0490*/ FFMA R7, R7, R26, R10 ; /* 0x0000001a07077223 */
/* 0x020fc6000000000a */
/*04a0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000362000c1e1900 */
/*04b0*/ FFMA R11, R6, R11, R7 ; /* 0x0000000b060b7223 */
/* 0x000fe40000000007 */
/*04c0*/ IMAD.WIDE R6, R8, 0x4, R24 ; /* 0x0000000408067825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R17, [R24.64] ; /* 0x0000000418117981 */
/* 0x010968000c1e1900 */
/*04e0*/ LDG.E R19, [R12.64+0x2c] ; /* 0x00002c040c137981 */
/* 0x001f62000c1e1900 */
/*04f0*/ FFMA R22, R9, R20, R11 ; /* 0x0000001409167223 */
/* 0x002fc6000000000b */
/*0500*/ LDG.E R20, [R12.64+0x30] ; /* 0x000030040c147981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD.WIDE R10, R8, 0x4, R6 ; /* 0x00000004080a7825 */
/* 0x000fc600078e0206 */
/*0520*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000168000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x3c] ; /* 0x00003c040c197981 */
/* 0x010f28000c1e1900 */
/*0540*/ LDG.E R6, [R12.64+0x34] ; /* 0x000034040c067981 */
/* 0x001f22000c1e1900 */
/*0550*/ FFMA R7, R28, R27, R22 ; /* 0x0000001b1c077223 */
/* 0x004fe40000000016 */
/*0560*/ IMAD.WIDE R22, R8, 0x4, R10 ; /* 0x0000000408167825 */
/* 0x000fe200078e020a */
/*0570*/ LDG.E R28, [R12.64+0x38] ; /* 0x000038040c1c7981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*05c0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05d0*/ FFMA R14, R14, R21, R7 ; /* 0x000000150e0e7223 */
/* 0x008fc80000000007 */
/*05e0*/ FFMA R14, R16, R29, R14 ; /* 0x0000001d100e7223 */
/* 0x000fc8000000000e */
/*05f0*/ FFMA R14, R18, R15, R14 ; /* 0x0000000f120e7223 */
/* 0x000fc8000000000e */
/*0600*/ FFMA R14, R26, R19, R14 ; /* 0x000000131a0e7223 */
/* 0x020fc8000000000e */
/*0610*/ FFMA R14, R17, R20, R14 ; /* 0x00000014110e7223 */
/* 0x000fe2000000000e */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0640*/ FFMA R6, R9, R6, R14 ; /* 0x0000000609067223 */
/* 0x010fc8000000000e */
/*0650*/ FFMA R27, R27, R28, R6 ; /* 0x0000001c1b1b7223 */
/* 0x004fe40000000006 */
/*0660*/ IMAD.WIDE R28, R8, 0x4, R22 ; /* 0x00000004081c7825 */
/* 0x000fc800078e0216 */
/*0670*/ FFMA R27, R24, R25, R27 ; /* 0x00000019181b7223 */
/* 0x000fe2000000001b */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R19, c[0x0][0x180] ; /* 0x0000600000137a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R14, R19, 0x4, R28 ; /* 0x00000004130e7825 */
/* 0x000fc800078e021c */
/*0700*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fe200078e0206 */
/*0710*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R10, R19.reuse, 0x4, R14 ; /* 0x00000004130a7825 */
/* 0x040fe200078e020e */
/*0730*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R6.64+0x4] ; /* 0x0000040406167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R12, R19, 0x4, R10 ; /* 0x00000004130c7825 */
/* 0x000fc600078e020a */
/*0760*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000966000c1e1900 */
/*0770*/ IMAD.WIDE R8, R19.reuse, 0x4, R12 ; /* 0x0000000413087825 */
/* 0x040fe200078e020c */
/*0780*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000162000c1e1900 */
/*07a0*/ IMAD.WIDE R14, R19, 0x4, R8 ; /* 0x00000004130e7825 */
/* 0x002fc600078e0208 */
/*07b0*/ LDG.E R25, [R6.64+0xc] ; /* 0x00000c0406197981 */
/* 0x000f66000c1e1900 */
/*07c0*/ IMAD.WIDE R16, R19.reuse, 0x4, R14 ; /* 0x0000000413107825 */
/* 0x040fe200078e020e */
/*07d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R6.64+0x10] ; /* 0x00001004061d7981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R10, R19, 0x4, R16 ; /* 0x00000004130a7825 */
/* 0x010fc600078e0210 */
/*0800*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R28, [R6.64+0x14] ; /* 0x00001404061c7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R9, [R6.64+0x18] ; /* 0x0000180406097981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R18, R18, R20, R27 ; /* 0x0000001412127223 */
/* 0x004fc8000000001b */
/*08c0*/ FFMA R18, R21, R22, R18 ; /* 0x0000001615127223 */
/* 0x008fc80000000012 */
/*08d0*/ FFMA R18, R23, R24, R18 ; /* 0x0000001817127223 */
/* 0x020fc80000000012 */
/*08e0*/ FFMA R12, R12, R25, R18 ; /* 0x000000190c0c7223 */
/* 0x000fc80000000012 */
/*08f0*/ FFMA R29, R8, R29, R12 ; /* 0x0000001d081d7223 */
/* 0x000fc8000000000c */
/*0900*/ FFMA R14, R14, R28, R29 ; /* 0x0000001c0e0e7223 */
/* 0x010fe4000000001d */
/*0910*/ IMAD.WIDE R28, R19, 0x4, R10 ; /* 0x00000004131c7825 */
/* 0x000fc800078e020a */
/*0920*/ FFMA R9, R26, R9, R14 ; /* 0x000000091a097223 */
/* 0x000fc8000000000e */
/*0930*/ FFMA R27, R13, R16, R9 ; /* 0x000000100d1b7223 */
/* 0x000fe40000000009 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R13, c[0x0][0x180] ; /* 0x00006000000d7a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fc800078e0206 */
/*09a0*/ IMAD.WIDE R14, R13.reuse, 0x4, R28 ; /* 0x000000040d0e7825 */
/* 0x040fe200078e021c */
/*09b0*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R10, R13, 0x4, R14 ; /* 0x000000040d0a7825 */
/* 0x000fc600078e020e */
/*09e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040406107981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R8, R13, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x000fc600078e020a */
/*0a10*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080406127981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R12, R28, R12, R27 ; /* 0x0000000c1c0c7223 */
/* 0x004fc8000000001b */
/*0ab0*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x008fe4000000000c */
/*0ac0*/ IMAD.WIDE R28, R13, 0x4, R8 ; /* 0x000000040d1c7825 */
/* 0x000fc800078e0208 */
/*0ad0*/ FFMA R12, R17, R18, R12 ; /* 0x00000012110c7223 */
/* 0x010fc8000000000c */
/*0ae0*/ FFMA R27, R19, R20, R12 ; /* 0x00000014131b7223 */
/* 0x020fe2000000000c */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R2, R3, RZ ; /* 0x0000000302067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b60*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0208 */
/*0b70*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R5, c[0x0][0x180] ; /* 0x0000600000057a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R5, 0x4, R8 ; /* 0x0000000405087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R27, R10, R3, R27 ; /* 0x000000030a1b7223 */
/* 0x004fc8000000001b */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ IADD3 R2, R0, R2, RZ ; /* 0x0000000200027210 */
/* 0x000fe40007ffe0ff */
/*0c20*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c30*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c40*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//kernel
__global__ void Matmul(float *A,float *B,float *C,int wA,int wC,int hC){
int i = blockDim.x*blockIdx.x+threadIdx.x;
int j = blockDim.y*blockIdx.y+threadIdx.y;
int k;
float tmp = 0.0f;
for(k=0;k<wA;k++){
tmp += A[k+j*wC] * B[i+k*hC];
}
C[i+j*wC] = tmp;
}
//C function
void init(float *A, int wA, int hA) {
for (int h=0; h<hA; h++)
for (int w=0; w<wA; w++)
A[w+h*wA] = (float)rand() / (float)RAND_MAX;
}
void compute(float *A, float *B, float *C,int wA, int hA, int wB) {
for (int h=0; h<hA; h++) {
for (int w=0; w<wB; w++) {
float temp = 0.0f;
for (int i=0; i<wA; i++)
temp += A[i+h*wA] * B[w+i*wB];
C[w+h*wB] = temp;
}
}
}
int main() {
float cpu_time;
int iter, max_iter = 10;
int wA = 320, hA = 320, wB = 640, hB = 320;
int wC = wB, hC = hA;
size_t sizeA = wA*hA*sizeof(float);
size_t sizeB = wB*hB*sizeof(float);
size_t sizeC = hA*wB*sizeof(float);
float *A, *B, *C;
A = (float*) malloc(sizeA);
B = (float*) malloc(sizeB);
C = (float*) malloc(sizeC);
// seed random number generator
srand(time(NULL));
// initialize A
init(A, wA, hA);
init(B, wB, hB);
//prepare memory in cuda
float *dA =NULL;
float *dB =NULL;
float *dC =NULL;
cudaMalloc((void**)&dA,sizeA);
cudaMalloc((void**)&dB,sizeB);
cudaMalloc((void**)&dC,sizeC);
//coppy input value from host to cuda
cudaMemcpy(dA,A,sizeA,cudaMemcpyHostToDevice);
cudaMemcpy(dB,B,sizeB,cudaMemcpyHostToDevice);
//execution configurtion
dim3 dimG(wC/32,hC/32);
dim3 dimB(32,32);
// compute matric C
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
for (iter=0; iter<max_iter; iter++){
Matmul<<<dimG,dimB>>>(dA,dB,dC,wA,wC,hC);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_time,start,stop);
printf("CPU time = %lf s\n", cpu_time*0.001/max_iter);
//coppy output value from cuda to host
cudaMemcpy(C,dC,sizeC,cudaMemcpyDeviceToHost);
//result check
///*
float *Check;
Check = (float*) malloc(sizeC);
compute(A, B, Check, wA, hA, wB);
float sum = 0.0f;
for (int h=0; h<hC; h++) {
for (int w=0; w<wC; w++) {
sum += C[w+h*wC]-Check[w+h*wC];
}
}
printf("Check result %f (should be zero)\n", sum/(hC*wC));
free(Check);
//*/
//free memory
free(A);
free(B);
free(C);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
return 0;
} | .file "tmpxft_000832ec_00000000-6_MatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPfii
.type _Z4initPfii, @function
_Z4initPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edx, 12(%rsp)
testl %edx, %edx
jle .L3
movq %rdi, %r15
movl %esi, %r12d
movl $0, %r14d
movl $0, %r13d
jmp .L5
.L7:
movslq %r14d, %rdx
leaq (%r15,%rdx,4), %rbx
movslq %r12d, %rax
addq %rdx, %rax
leaq (%r15,%rax,4), %rbp
.L6:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $1, %r13d
addl %r12d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r12d, %r12d
jg .L7
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4initPfii, .-_Z4initPfii
.globl _Z7computePfS_S_iii
.type _Z7computePfS_S_iii, @function
_Z7computePfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %r8d, -20(%rsp)
testl %r8d, %r8d
jle .L11
movq %rdi, %rbx
movl %ecx, %r10d
movl %r9d, %r14d
movslq %r9d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %ecx, %r15
movq %r15, %rcx
jmp .L13
.L14:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L14
.L16:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L21
.L17:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L14
jmp .L16
.L21:
movl -24(%rsp), %edx
.L15:
addl $1, %edx
addl %r14d, %r12d
addl %r10d, %r13d
cmpl %edx, -20(%rsp)
je .L11
.L13:
testl %r14d, %r14d
jle .L15
movq -16(%rsp), %r9
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rcx, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -8(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L17
.L11:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7computePfS_S_iii, .-_Z7computePfS_S_iii
.globl _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
.type _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii, @function
_Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6MatmulPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii, .-_Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
.globl _Z6MatmulPfS_S_iii
.type _Z6MatmulPfS_S_iii, @function
_Z6MatmulPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6MatmulPfS_S_iii, .-_Z6MatmulPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU time = %lf s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Check result %f (should be zero)\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $409600, %edi
call malloc@PLT
movq %rax, %r13
movl $819200, %edi
call malloc@PLT
movq %rax, %r12
movl $819200, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $320, %edx
movl $320, %esi
movq %r13, %rdi
call _Z4initPfii
movl $320, %edx
movl $640, %esi
movq %r12, %rdi
call _Z4initPfii
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $819200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $819200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $409600, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $819200, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 48(%rsp)
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, %ebp
jmp .L34
.L33:
subl $1, %ebp
je .L42
.L34:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl $320, %r9d
movl $640, %r8d
movl $320, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
jmp .L33
.L42:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $819200, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $819200, %edi
call malloc@PLT
movq %rax, %rbp
movl $640, %r9d
movl $320, %r8d
movl $320, %ecx
movq %rax, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z7computePfS_S_iii
movl $2560, %edx
pxor %xmm1, %xmm1
.L35:
leaq -2560(%rdx), %rax
.L36:
movss (%rbx,%rax), %xmm0
subss 0(%rbp,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rdx, %rax
jne .L36
addq $2560, %rdx
cmpq $821760, %rdx
jne .L35
divss .LC5(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6MatmulPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatmulPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -755914244
.long 1062232653
.align 8
.LC3:
.long 0
.long 1076101120
.section .rodata.cst4
.align 4
.LC5:
.long 1212678144
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
//kernel
__global__ void Matmul(float *A,float *B,float *C,int wA,int wC,int hC){
int i = blockDim.x*blockIdx.x+threadIdx.x;
int j = blockDim.y*blockIdx.y+threadIdx.y;
int k;
float tmp = 0.0f;
for(k=0;k<wA;k++){
tmp += A[k+j*wC] * B[i+k*hC];
}
C[i+j*wC] = tmp;
}
//C function
void init(float *A, int wA, int hA) {
for (int h=0; h<hA; h++)
for (int w=0; w<wA; w++)
A[w+h*wA] = (float)rand() / (float)RAND_MAX;
}
void compute(float *A, float *B, float *C,int wA, int hA, int wB) {
for (int h=0; h<hA; h++) {
for (int w=0; w<wB; w++) {
float temp = 0.0f;
for (int i=0; i<wA; i++)
temp += A[i+h*wA] * B[w+i*wB];
C[w+h*wB] = temp;
}
}
}
int main() {
float cpu_time;
int iter, max_iter = 10;
int wA = 320, hA = 320, wB = 640, hB = 320;
int wC = wB, hC = hA;
size_t sizeA = wA*hA*sizeof(float);
size_t sizeB = wB*hB*sizeof(float);
size_t sizeC = hA*wB*sizeof(float);
float *A, *B, *C;
A = (float*) malloc(sizeA);
B = (float*) malloc(sizeB);
C = (float*) malloc(sizeC);
// seed random number generator
srand(time(NULL));
// initialize A
init(A, wA, hA);
init(B, wB, hB);
//prepare memory in cuda
float *dA =NULL;
float *dB =NULL;
float *dC =NULL;
cudaMalloc((void**)&dA,sizeA);
cudaMalloc((void**)&dB,sizeB);
cudaMalloc((void**)&dC,sizeC);
//coppy input value from host to cuda
cudaMemcpy(dA,A,sizeA,cudaMemcpyHostToDevice);
cudaMemcpy(dB,B,sizeB,cudaMemcpyHostToDevice);
//execution configurtion
dim3 dimG(wC/32,hC/32);
dim3 dimB(32,32);
// compute matric C
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
for (iter=0; iter<max_iter; iter++){
Matmul<<<dimG,dimB>>>(dA,dB,dC,wA,wC,hC);
}
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cpu_time,start,stop);
printf("CPU time = %lf s\n", cpu_time*0.001/max_iter);
//coppy output value from cuda to host
cudaMemcpy(C,dC,sizeC,cudaMemcpyDeviceToHost);
//result check
///*
float *Check;
Check = (float*) malloc(sizeC);
compute(A, B, Check, wA, hA, wB);
float sum = 0.0f;
for (int h=0; h<hC; h++) {
for (int w=0; w<wC; w++) {
sum += C[w+h*wC]-Check[w+h*wC];
}
}
printf("Check result %f (should be zero)\n", sum/(hC*wC));
free(Check);
//*/
//free memory
free(A);
free(B);
free(C);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//kernel
__global__ void Matmul(float *A,float *B,float *C,int wA,int wC,int hC){
int i = blockDim.x*blockIdx.x+threadIdx.x;
int j = blockDim.y*blockIdx.y+threadIdx.y;
int k;
float tmp = 0.0f;
for(k=0;k<wA;k++){
tmp += A[k+j*wC] * B[i+k*hC];
}
C[i+j*wC] = tmp;
}
//C function
void init(float *A, int wA, int hA) {
for (int h=0; h<hA; h++)
for (int w=0; w<wA; w++)
A[w+h*wA] = (float)rand() / (float)RAND_MAX;
}
void compute(float *A, float *B, float *C,int wA, int hA, int wB) {
for (int h=0; h<hA; h++) {
for (int w=0; w<wB; w++) {
float temp = 0.0f;
for (int i=0; i<wA; i++)
temp += A[i+h*wA] * B[w+i*wB];
C[w+h*wB] = temp;
}
}
}
int main() {
float cpu_time;
int iter, max_iter = 10;
int wA = 320, hA = 320, wB = 640, hB = 320;
int wC = wB, hC = hA;
size_t sizeA = wA*hA*sizeof(float);
size_t sizeB = wB*hB*sizeof(float);
size_t sizeC = hA*wB*sizeof(float);
float *A, *B, *C;
A = (float*) malloc(sizeA);
B = (float*) malloc(sizeB);
C = (float*) malloc(sizeC);
// seed random number generator
srand(time(NULL));
// initialize A
init(A, wA, hA);
init(B, wB, hB);
//prepare memory in cuda
float *dA =NULL;
float *dB =NULL;
float *dC =NULL;
hipMalloc((void**)&dA,sizeA);
hipMalloc((void**)&dB,sizeB);
hipMalloc((void**)&dC,sizeC);
//coppy input value from host to cuda
hipMemcpy(dA,A,sizeA,hipMemcpyHostToDevice);
hipMemcpy(dB,B,sizeB,hipMemcpyHostToDevice);
//execution configurtion
dim3 dimG(wC/32,hC/32);
dim3 dimB(32,32);
// compute matric C
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
for (iter=0; iter<max_iter; iter++){
Matmul<<<dimG,dimB>>>(dA,dB,dC,wA,wC,hC);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_time,start,stop);
printf("CPU time = %lf s\n", cpu_time*0.001/max_iter);
//coppy output value from cuda to host
hipMemcpy(C,dC,sizeC,hipMemcpyDeviceToHost);
//result check
///*
float *Check;
Check = (float*) malloc(sizeC);
compute(A, B, Check, wA, hA, wB);
float sum = 0.0f;
for (int h=0; h<hC; h++) {
for (int w=0; w<wC; w++) {
sum += C[w+h*wC]-Check[w+h*wC];
}
}
printf("Check result %f (should be zero)\n", sum/(hC*wC));
free(Check);
//*/
//free memory
free(A);
free(B);
free(C);
hipFree(dA);
hipFree(dB);
hipFree(dC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//kernel
__global__ void Matmul(float *A,float *B,float *C,int wA,int wC,int hC){
int i = blockDim.x*blockIdx.x+threadIdx.x;
int j = blockDim.y*blockIdx.y+threadIdx.y;
int k;
float tmp = 0.0f;
for(k=0;k<wA;k++){
tmp += A[k+j*wC] * B[i+k*hC];
}
C[i+j*wC] = tmp;
}
//C function
void init(float *A, int wA, int hA) {
for (int h=0; h<hA; h++)
for (int w=0; w<wA; w++)
A[w+h*wA] = (float)rand() / (float)RAND_MAX;
}
void compute(float *A, float *B, float *C,int wA, int hA, int wB) {
for (int h=0; h<hA; h++) {
for (int w=0; w<wB; w++) {
float temp = 0.0f;
for (int i=0; i<wA; i++)
temp += A[i+h*wA] * B[w+i*wB];
C[w+h*wB] = temp;
}
}
}
int main() {
float cpu_time;
int iter, max_iter = 10;
int wA = 320, hA = 320, wB = 640, hB = 320;
int wC = wB, hC = hA;
size_t sizeA = wA*hA*sizeof(float);
size_t sizeB = wB*hB*sizeof(float);
size_t sizeC = hA*wB*sizeof(float);
float *A, *B, *C;
A = (float*) malloc(sizeA);
B = (float*) malloc(sizeB);
C = (float*) malloc(sizeC);
// seed random number generator
srand(time(NULL));
// initialize A
init(A, wA, hA);
init(B, wB, hB);
//prepare memory in cuda
float *dA =NULL;
float *dB =NULL;
float *dC =NULL;
hipMalloc((void**)&dA,sizeA);
hipMalloc((void**)&dB,sizeB);
hipMalloc((void**)&dC,sizeC);
//coppy input value from host to cuda
hipMemcpy(dA,A,sizeA,hipMemcpyHostToDevice);
hipMemcpy(dB,B,sizeB,hipMemcpyHostToDevice);
//execution configurtion
dim3 dimG(wC/32,hC/32);
dim3 dimB(32,32);
// compute matric C
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
for (iter=0; iter<max_iter; iter++){
Matmul<<<dimG,dimB>>>(dA,dB,dC,wA,wC,hC);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_time,start,stop);
printf("CPU time = %lf s\n", cpu_time*0.001/max_iter);
//coppy output value from cuda to host
hipMemcpy(C,dC,sizeC,hipMemcpyDeviceToHost);
//result check
///*
float *Check;
Check = (float*) malloc(sizeC);
compute(A, B, Check, wA, hA, wB);
float sum = 0.0f;
for (int h=0; h<hC; h++) {
for (int w=0; w<wC; w++) {
sum += C[w+h*wC]-Check[w+h*wC];
}
}
printf("Check result %f (should be zero)\n", sum/(hC*wC));
free(Check);
//*/
//free memory
free(A);
free(B);
free(C);
hipFree(dA);
hipFree(dB);
hipFree(dC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatmulPfS_S_iii
.globl _Z6MatmulPfS_S_iii
.p2align 8
.type _Z6MatmulPfS_S_iii,@function
_Z6MatmulPfS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s3
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatmulPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatmulPfS_S_iii, .Lfunc_end0-_Z6MatmulPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatmulPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MatmulPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//kernel
__global__ void Matmul(float *A,float *B,float *C,int wA,int wC,int hC){
int i = blockDim.x*blockIdx.x+threadIdx.x;
int j = blockDim.y*blockIdx.y+threadIdx.y;
int k;
float tmp = 0.0f;
for(k=0;k<wA;k++){
tmp += A[k+j*wC] * B[i+k*hC];
}
C[i+j*wC] = tmp;
}
//C function
void init(float *A, int wA, int hA) {
for (int h=0; h<hA; h++)
for (int w=0; w<wA; w++)
A[w+h*wA] = (float)rand() / (float)RAND_MAX;
}
void compute(float *A, float *B, float *C,int wA, int hA, int wB) {
for (int h=0; h<hA; h++) {
for (int w=0; w<wB; w++) {
float temp = 0.0f;
for (int i=0; i<wA; i++)
temp += A[i+h*wA] * B[w+i*wB];
C[w+h*wB] = temp;
}
}
}
int main() {
float cpu_time;
int iter, max_iter = 10;
int wA = 320, hA = 320, wB = 640, hB = 320;
int wC = wB, hC = hA;
size_t sizeA = wA*hA*sizeof(float);
size_t sizeB = wB*hB*sizeof(float);
size_t sizeC = hA*wB*sizeof(float);
float *A, *B, *C;
A = (float*) malloc(sizeA);
B = (float*) malloc(sizeB);
C = (float*) malloc(sizeC);
// seed random number generator
srand(time(NULL));
// initialize A
init(A, wA, hA);
init(B, wB, hB);
//prepare memory in cuda
float *dA =NULL;
float *dB =NULL;
float *dC =NULL;
hipMalloc((void**)&dA,sizeA);
hipMalloc((void**)&dB,sizeB);
hipMalloc((void**)&dC,sizeC);
//coppy input value from host to cuda
hipMemcpy(dA,A,sizeA,hipMemcpyHostToDevice);
hipMemcpy(dB,B,sizeB,hipMemcpyHostToDevice);
//execution configurtion
dim3 dimG(wC/32,hC/32);
dim3 dimB(32,32);
// compute matric C
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
for (iter=0; iter<max_iter; iter++){
Matmul<<<dimG,dimB>>>(dA,dB,dC,wA,wC,hC);
}
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&cpu_time,start,stop);
printf("CPU time = %lf s\n", cpu_time*0.001/max_iter);
//coppy output value from cuda to host
hipMemcpy(C,dC,sizeC,hipMemcpyDeviceToHost);
//result check
///*
float *Check;
Check = (float*) malloc(sizeC);
compute(A, B, Check, wA, hA, wB);
float sum = 0.0f;
for (int h=0; h<hC; h++) {
for (int w=0; w<wC; w++) {
sum += C[w+h*wC]-Check[w+h*wC];
}
}
printf("Check result %f (should be zero)\n", sum/(hC*wC));
free(Check);
//*/
//free memory
free(A);
free(B);
free(C);
hipFree(dA);
hipFree(dB);
hipFree(dC);
return 0;
} | .text
.file "MatMul.hip"
.globl _Z21__device_stub__MatmulPfS_S_iii # -- Begin function _Z21__device_stub__MatmulPfS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__MatmulPfS_S_iii,@function
_Z21__device_stub__MatmulPfS_S_iii: # @_Z21__device_stub__MatmulPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatmulPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__MatmulPfS_S_iii, .Lfunc_end0-_Z21__device_stub__MatmulPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4initPfii
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z4initPfii
.p2align 4, 0x90
.type _Z4initPfii,@function
_Z4initPfii: # @_Z4initPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %esi, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4initPfii, .Lfunc_end1-_Z4initPfii
.cfi_endproc
# -- End function
.globl _Z7computePfS_S_iii # -- Begin function _Z7computePfS_S_iii
.p2align 4, 0x90
.type _Z7computePfS_S_iii,@function
_Z7computePfS_S_iii: # @_Z7computePfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB2_9
# %bb.1: # %.preheader27.lr.ph
movslq %r9d, %rdi
movl %r8d, %r8d
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge31
# in Loop: Header=BB2_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %r8, %r15
je .LBB2_9
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r9d, %r9d
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %ecx, %ecx
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rsi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rdx
addq %rbx, %rbp
cmpq %rdx, %r11
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7computePfS_S_iii, .Lfunc_end2-_Z7computePfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_3:
.long 0x48480000 # float 204800
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI3_2:
.quad 0x4024000000000000 # double 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $409600, %edi # imm = 0x64000
callq malloc
movq %rax, %r13
movl $819200, %edi # imm = 0xC8000
callq malloc
movq %rax, %r14
movl $819200, %edi # imm = 0xC8000
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r13, %r15
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $320, %r12 # imm = 0x140
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %rbx
addq $1280, %r15 # imm = 0x500
cmpq $320, %rbx # imm = 0x140
jne .LBB3_1
# %bb.4: # %.preheader.i73.preheader
xorl %ebx, %ebx
movq %r14, %r15
.p2align 4, 0x90
.LBB3_5: # %.preheader.i73
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $640, %r12 # imm = 0x280
jne .LBB3_6
# %bb.7: # %._crit_edge.i78
# in Loop: Header=BB3_5 Depth=1
incq %rbx
addq $2560, %r15 # imm = 0xA00
cmpq $320, %rbx # imm = 0x140
jne .LBB3_5
# %bb.8: # %_Z4initPfii.exit81
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 16(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $819200, %esi # imm = 0xC8000
callq hipMalloc
movq %rsp, %rdi
movl $819200, %esi # imm = 0xC8000
callq hipMalloc
movq 16(%rsp), %rdi
movl $409600, %edx # imm = 0x64000
movq %r13, 64(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $819200, %edx # imm = 0xC8000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10, %ebx
movabsq $42949672980, %r12 # imm = 0xA00000014
movabsq $137438953504, %r13 # imm = 0x2000000020
leaq 72(%rsp), %rbp
leaq 144(%rsp), %r15
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_9 Depth=1
decl %ebx
je .LBB3_12
.LBB3_9: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $320, 44(%rsp) # imm = 0x140
movl $640, 40(%rsp) # imm = 0x280
movl $320, 36(%rsp) # imm = 0x140
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z6MatmulPfS_S_iii, %edi
movq %r15, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 24(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movl $819200, %edx # imm = 0xC8000
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl $819200, %edi # imm = 0xC8000
callq malloc
movq %rax, %r12
movq 64(%rsp), %r15 # 8-byte Reload
movq %r15, %rax
.p2align 4, 0x90
.LBB3_13: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
# Child Loop BB3_15 Depth 3
leaq (%rbx,%rbx,4), %rcx
shlq $9, %rcx
addq %r12, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_14: # %.preheader.i82
# Parent Loop BB3_13 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_15 Depth 3
xorpd %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_15: # %.lr.ph.i
# Parent Loop BB3_13 Depth=1
# Parent Loop BB3_14 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $2560, %rdi # imm = 0xA00
cmpq $320, %r8 # imm = 0x140
jne .LBB3_15
# %bb.16: # %._crit_edge.i86
# in Loop: Header=BB3_14 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $640, %rsi # imm = 0x280
jne .LBB3_14
# %bb.17: # %._crit_edge31.i
# in Loop: Header=BB3_13 Depth=1
incq %rbx
addq $1280, %rax # imm = 0x500
cmpq $320, %rbx # imm = 0x140
jne .LBB3_13
# %bb.18: # %.preheader.preheader
xorpd %xmm0, %xmm0
xorl %eax, %eax
movq %r13, %rcx
movq %r12, %rdx
.p2align 4, 0x90
.LBB3_19: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_20: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rdx,%rsi,4), %xmm1
addss %xmm1, %xmm0
incq %rsi
cmpq $640, %rsi # imm = 0x280
jne .LBB3_20
# %bb.21: # %_Z7computePfS_S_iii.exit
# in Loop: Header=BB3_19 Depth=1
incq %rax
addq $2560, %rdx # imm = 0xA00
addq $2560, %rcx # imm = 0xA00
cmpq $320, %rax # imm = 0x140
jne .LBB3_19
# %bb.22:
divss .LCPI3_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatmulPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatmulPfS_S_iii,@object # @_Z6MatmulPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z6MatmulPfS_S_iii
.p2align 3, 0x0
_Z6MatmulPfS_S_iii:
.quad _Z21__device_stub__MatmulPfS_S_iii
.size _Z6MatmulPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU time = %lf s\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Check result %f (should be zero)\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatmulPfS_S_iii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatmulPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatmulPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6MatmulPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R2, R2, c[0x0][0x17c], RZ ; /* 0x00005f0002027a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xc10 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R4.reuse, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xb00 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R29, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1d7435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R28, R0, R29, c[0x0][0x168] ; /* 0x00005a00001c7625 */
/* 0x000fcc00078e021d */
/*01a0*/ @!P0 BRA 0x960 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x690 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000a2000c1e1900 */
/*0210*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fc60000000f00 */
/*0250*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD.WIDE R6, R8.reuse, 0x4, R28 ; /* 0x0000000408067825 */
/* 0x040fe400078e021c */
/*0270*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c040c0a7981 */
/* 0x000f28000c1e1900 */
/*0280*/ IMAD.WIDE R18, R8.reuse, 0x4, R6 ; /* 0x0000000408127825 */
/* 0x040fe200078e0206 */
/*0290*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x000f62000c1e1900 */
/*02b0*/ IMAD.WIDE R24, R8, 0x4, R18 ; /* 0x0000000408187825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000326000c1e1900 */
/*02d0*/ IMAD.WIDE R28, R8.reuse, 0x4, R24 ; /* 0x00000004081c7825 */
/* 0x041fe200078e0218 */
/*02e0*/ LDG.E R21, [R24.64] ; /* 0x0000000418157981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x002368000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x000f22000c1e1900 */
/*0310*/ IMAD.WIDE R22, R8, 0x4, R28 ; /* 0x0000000408167825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x000f68000c1e1900 */
/*0330*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000f62000c1e1900 */
/*0350*/ IMAD.WIDE R22, R8, 0x4, R22 ; /* 0x0000000408167825 */
/* 0x001fca00078e0216 */
/*0360*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000162000c1e1900 */
/*0370*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x000fca00078e0216 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x002362000c1e1900 */
/*0390*/ FFMA R29, R14, R15, R27 ; /* 0x0000000f0e1d7223 */
/* 0x004fc6000000001b */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R14, R8, 0x4, R24 ; /* 0x00000004080e7825 */
/* 0x000fc800078e0218 */
/*03c0*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe4000000001d */
/*03d0*/ IMAD.WIDE R16, R8, 0x4, R14 ; /* 0x0000000408107825 */
/* 0x000fe400078e020e */
/*03e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a8000c1e1900 */
/*03f0*/ LDG.E R15, [R12.64+0x28] ; /* 0x000028040c0f7981 */
/* 0x008ee2000c1e1900 */
/*0400*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0410*/ IMAD.WIDE R18, R8, 0x4, R16 ; /* 0x0000000408127825 */
/* 0x000fc400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*0430*/ FFMA R10, R21, R10, R29 ; /* 0x0000000a150a7223 */
/* 0x000fe4000000001d */
/*0440*/ IMAD.WIDE R22, R8.reuse, 0x4, R18 ; /* 0x0000000408167825 */
/* 0x041fe200078e0212 */
/*0450*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x000ee8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ee2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x002fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0490*/ FFMA R7, R7, R26, R10 ; /* 0x0000001a07077223 */
/* 0x020fc6000000000a */
/*04a0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000362000c1e1900 */
/*04b0*/ FFMA R11, R6, R11, R7 ; /* 0x0000000b060b7223 */
/* 0x000fe40000000007 */
/*04c0*/ IMAD.WIDE R6, R8, 0x4, R24 ; /* 0x0000000408067825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R17, [R24.64] ; /* 0x0000000418117981 */
/* 0x010968000c1e1900 */
/*04e0*/ LDG.E R19, [R12.64+0x2c] ; /* 0x00002c040c137981 */
/* 0x001f62000c1e1900 */
/*04f0*/ FFMA R22, R9, R20, R11 ; /* 0x0000001409167223 */
/* 0x002fc6000000000b */
/*0500*/ LDG.E R20, [R12.64+0x30] ; /* 0x000030040c147981 */
/* 0x000f62000c1e1900 */
/*0510*/ IMAD.WIDE R10, R8, 0x4, R6 ; /* 0x00000004080a7825 */
/* 0x000fc600078e0206 */
/*0520*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000168000c1e1900 */
/*0530*/ LDG.E R25, [R12.64+0x3c] ; /* 0x00003c040c197981 */
/* 0x010f28000c1e1900 */
/*0540*/ LDG.E R6, [R12.64+0x34] ; /* 0x000034040c067981 */
/* 0x001f22000c1e1900 */
/*0550*/ FFMA R7, R28, R27, R22 ; /* 0x0000001b1c077223 */
/* 0x004fe40000000016 */
/*0560*/ IMAD.WIDE R22, R8, 0x4, R10 ; /* 0x0000000408167825 */
/* 0x000fe200078e020a */
/*0570*/ LDG.E R28, [R12.64+0x38] ; /* 0x000038040c1c7981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*05c0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05d0*/ FFMA R14, R14, R21, R7 ; /* 0x000000150e0e7223 */
/* 0x008fc80000000007 */
/*05e0*/ FFMA R14, R16, R29, R14 ; /* 0x0000001d100e7223 */
/* 0x000fc8000000000e */
/*05f0*/ FFMA R14, R18, R15, R14 ; /* 0x0000000f120e7223 */
/* 0x000fc8000000000e */
/*0600*/ FFMA R14, R26, R19, R14 ; /* 0x000000131a0e7223 */
/* 0x020fc8000000000e */
/*0610*/ FFMA R14, R17, R20, R14 ; /* 0x00000014110e7223 */
/* 0x000fe2000000000e */
/*0620*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0630*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0640*/ FFMA R6, R9, R6, R14 ; /* 0x0000000609067223 */
/* 0x010fc8000000000e */
/*0650*/ FFMA R27, R27, R28, R6 ; /* 0x0000001c1b1b7223 */
/* 0x004fe40000000006 */
/*0660*/ IMAD.WIDE R28, R8, 0x4, R22 ; /* 0x00000004081c7825 */
/* 0x000fc800078e0216 */
/*0670*/ FFMA R27, R24, R25, R27 ; /* 0x00000019181b7223 */
/* 0x000fe2000000001b */
/*0680*/ @P1 BRA 0x1f0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x940 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06b0*/ MOV R19, c[0x0][0x180] ; /* 0x0000600000137a02 */
/* 0x000fe20000000f00 */
/*06c0*/ LDG.E R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0000a2000c1e1900 */
/*06d0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*06e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*06f0*/ IMAD.WIDE R14, R19, 0x4, R28 ; /* 0x00000004130e7825 */
/* 0x000fc800078e021c */
/*0700*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fe200078e0206 */
/*0710*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R10, R19.reuse, 0x4, R14 ; /* 0x00000004130a7825 */
/* 0x040fe200078e020e */
/*0730*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R22, [R6.64+0x4] ; /* 0x0000040406167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IMAD.WIDE R12, R19, 0x4, R10 ; /* 0x00000004130c7825 */
/* 0x000fc600078e020a */
/*0760*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000966000c1e1900 */
/*0770*/ IMAD.WIDE R8, R19.reuse, 0x4, R12 ; /* 0x0000000413087825 */
/* 0x040fe200078e020c */
/*0780*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000162000c1e1900 */
/*07a0*/ IMAD.WIDE R14, R19, 0x4, R8 ; /* 0x00000004130e7825 */
/* 0x002fc600078e0208 */
/*07b0*/ LDG.E R25, [R6.64+0xc] ; /* 0x00000c0406197981 */
/* 0x000f66000c1e1900 */
/*07c0*/ IMAD.WIDE R16, R19.reuse, 0x4, R14 ; /* 0x0000000413107825 */
/* 0x040fe200078e020e */
/*07d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R6.64+0x10] ; /* 0x00001004061d7981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R10, R19, 0x4, R16 ; /* 0x00000004130a7825 */
/* 0x010fc600078e0210 */
/*0800*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R28, [R6.64+0x14] ; /* 0x00001404061c7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R9, [R6.64+0x18] ; /* 0x0000180406097981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ FFMA R18, R18, R20, R27 ; /* 0x0000001412127223 */
/* 0x004fc8000000001b */
/*08c0*/ FFMA R18, R21, R22, R18 ; /* 0x0000001615127223 */
/* 0x008fc80000000012 */
/*08d0*/ FFMA R18, R23, R24, R18 ; /* 0x0000001817127223 */
/* 0x020fc80000000012 */
/*08e0*/ FFMA R12, R12, R25, R18 ; /* 0x000000190c0c7223 */
/* 0x000fc80000000012 */
/*08f0*/ FFMA R29, R8, R29, R12 ; /* 0x0000001d081d7223 */
/* 0x000fc8000000000c */
/*0900*/ FFMA R14, R14, R28, R29 ; /* 0x0000001c0e0e7223 */
/* 0x010fe4000000001d */
/*0910*/ IMAD.WIDE R28, R19, 0x4, R10 ; /* 0x00000004131c7825 */
/* 0x000fc800078e020a */
/*0920*/ FFMA R9, R26, R9, R14 ; /* 0x000000091a097223 */
/* 0x000fc8000000000e */
/*0930*/ FFMA R27, R13, R16, R9 ; /* 0x000000100d1b7223 */
/* 0x000fe40000000009 */
/*0940*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xb00 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*0970*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0980*/ MOV R13, c[0x0][0x180] ; /* 0x00006000000d7a02 */
/* 0x000fc60000000f00 */
/*0990*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fc800078e0206 */
/*09a0*/ IMAD.WIDE R14, R13.reuse, 0x4, R28 ; /* 0x000000040d0e7825 */
/* 0x040fe200078e021c */
/*09b0*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*09d0*/ IMAD.WIDE R10, R13, 0x4, R14 ; /* 0x000000040d0a7825 */
/* 0x000fc600078e020e */
/*09e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*09f0*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040406107981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IMAD.WIDE R8, R13, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x000fc600078e020a */
/*0a10*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080406127981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R12, R28, R12, R27 ; /* 0x0000000c1c0c7223 */
/* 0x004fc8000000001b */
/*0ab0*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x008fe4000000000c */
/*0ac0*/ IMAD.WIDE R28, R13, 0x4, R8 ; /* 0x000000040d1c7825 */
/* 0x000fc800078e0208 */
/*0ad0*/ FFMA R12, R17, R18, R12 ; /* 0x00000012110c7223 */
/* 0x010fc8000000000c */
/*0ae0*/ FFMA R27, R19, R20, R12 ; /* 0x00000014131b7223 */
/* 0x020fe2000000000c */
/*0af0*/ @P0 BRA 0x960 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc10 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R2, R3, RZ ; /* 0x0000000302067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b60*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0208 */
/*0b70*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ MOV R5, c[0x0][0x180] ; /* 0x0000600000057a02 */
/* 0x000fe40000000f00 */
/*0bb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bc0*/ IMAD.WIDE R8, R5, 0x4, R8 ; /* 0x0000000405087825 */
/* 0x001fe200078e0208 */
/*0bd0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0be0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bf0*/ FFMA R27, R10, R3, R27 ; /* 0x000000030a1b7223 */
/* 0x004fc8000000001b */
/*0c00*/ @P0 BRA 0xb70 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c10*/ IADD3 R2, R0, R2, RZ ; /* 0x0000000200027210 */
/* 0x000fe40007ffe0ff */
/*0c20*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c30*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0c40*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatmulPfS_S_iii
.globl _Z6MatmulPfS_S_iii
.p2align 8
.type _Z6MatmulPfS_S_iii,@function
_Z6MatmulPfS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s3
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatmulPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatmulPfS_S_iii, .Lfunc_end0-_Z6MatmulPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatmulPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6MatmulPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000832ec_00000000-6_MatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPfii
.type _Z4initPfii, @function
_Z4initPfii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edx, 12(%rsp)
testl %edx, %edx
jle .L3
movq %rdi, %r15
movl %esi, %r12d
movl $0, %r14d
movl $0, %r13d
jmp .L5
.L7:
movslq %r14d, %rdx
leaq (%r15,%rdx,4), %rbx
movslq %r12d, %rax
addq %rdx, %rax
leaq (%r15,%rax,4), %rbp
.L6:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $1, %r13d
addl %r12d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r12d, %r12d
jg .L7
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z4initPfii, .-_Z4initPfii
.globl _Z7computePfS_S_iii
.type _Z7computePfS_S_iii, @function
_Z7computePfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %r8d, -20(%rsp)
testl %r8d, %r8d
jle .L11
movq %rdi, %rbx
movl %ecx, %r10d
movl %r9d, %r14d
movslq %r9d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %ecx, %r15
movq %r15, %rcx
jmp .L13
.L14:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L14
.L16:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L21
.L17:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L14
jmp .L16
.L21:
movl -24(%rsp), %edx
.L15:
addl $1, %edx
addl %r14d, %r12d
addl %r10d, %r13d
cmpl %edx, -20(%rsp)
je .L11
.L13:
testl %r14d, %r14d
jle .L15
movq -16(%rsp), %r9
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rcx, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -8(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L17
.L11:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7computePfS_S_iii, .-_Z7computePfS_S_iii
.globl _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
.type _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii, @function
_Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6MatmulPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii, .-_Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
.globl _Z6MatmulPfS_S_iii
.type _Z6MatmulPfS_S_iii, @function
_Z6MatmulPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6MatmulPfS_S_iii, .-_Z6MatmulPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU time = %lf s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Check result %f (should be zero)\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $409600, %edi
call malloc@PLT
movq %rax, %r13
movl $819200, %edi
call malloc@PLT
movq %rax, %r12
movl $819200, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $320, %edx
movl $320, %esi
movq %r13, %rdi
call _Z4initPfii
movl $320, %edx
movl $640, %esi
movq %r12, %rdi
call _Z4initPfii
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $819200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $819200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $409600, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $819200, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $20, 48(%rsp)
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, %ebp
jmp .L34
.L33:
subl $1, %ebp
je .L42
.L34:
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl $320, %r9d
movl $640, %r8d
movl $320, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z6MatmulPfS_S_iiiPfS_S_iii
jmp .L33
.L42:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $819200, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $819200, %edi
call malloc@PLT
movq %rax, %rbp
movl $640, %r9d
movl $320, %r8d
movl $320, %ecx
movq %rax, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z7computePfS_S_iii
movl $2560, %edx
pxor %xmm1, %xmm1
.L35:
leaq -2560(%rdx), %rax
.L36:
movss (%rbx,%rax), %xmm0
subss 0(%rbp,%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
cmpq %rdx, %rax
jne .L36
addq $2560, %rdx
cmpq $821760, %rdx
jne .L35
divss .LC5(%rip), %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6MatmulPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatmulPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -755914244
.long 1062232653
.align 8
.LC3:
.long 0
.long 1076101120
.section .rodata.cst4
.align 4
.LC5:
.long 1212678144
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatMul.hip"
.globl _Z21__device_stub__MatmulPfS_S_iii # -- Begin function _Z21__device_stub__MatmulPfS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__MatmulPfS_S_iii,@function
_Z21__device_stub__MatmulPfS_S_iii: # @_Z21__device_stub__MatmulPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatmulPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__MatmulPfS_S_iii, .Lfunc_end0-_Z21__device_stub__MatmulPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4initPfii
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z4initPfii
.p2align 4, 0x90
.type _Z4initPfii,@function
_Z4initPfii: # @_Z4initPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %esi, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4initPfii, .Lfunc_end1-_Z4initPfii
.cfi_endproc
# -- End function
.globl _Z7computePfS_S_iii # -- Begin function _Z7computePfS_S_iii
.p2align 4, 0x90
.type _Z7computePfS_S_iii,@function
_Z7computePfS_S_iii: # @_Z7computePfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB2_9
# %bb.1: # %.preheader27.lr.ph
movslq %r9d, %rdi
movl %r8d, %r8d
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge31
# in Loop: Header=BB2_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %r8, %r15
je .LBB2_9
.LBB2_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r9d, %r9d
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %ecx, %ecx
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rsi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rdx
addq %rbx, %rbp
cmpq %rdx, %r11
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7computePfS_S_iii, .Lfunc_end2-_Z7computePfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_3:
.long 0x48480000 # float 204800
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI3_2:
.quad 0x4024000000000000 # double 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $409600, %edi # imm = 0x64000
callq malloc
movq %rax, %r13
movl $819200, %edi # imm = 0xC8000
callq malloc
movq %rax, %r14
movl $819200, %edi # imm = 0xC8000
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %r13, %r15
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $320, %r12 # imm = 0x140
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %rbx
addq $1280, %r15 # imm = 0x500
cmpq $320, %rbx # imm = 0x140
jne .LBB3_1
# %bb.4: # %.preheader.i73.preheader
xorl %ebx, %ebx
movq %r14, %r15
.p2align 4, 0x90
.LBB3_5: # %.preheader.i73
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $640, %r12 # imm = 0x280
jne .LBB3_6
# %bb.7: # %._crit_edge.i78
# in Loop: Header=BB3_5 Depth=1
incq %rbx
addq $2560, %r15 # imm = 0xA00
cmpq $320, %rbx # imm = 0x140
jne .LBB3_5
# %bb.8: # %_Z4initPfii.exit81
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
leaq 16(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $819200, %esi # imm = 0xC8000
callq hipMalloc
movq %rsp, %rdi
movl $819200, %esi # imm = 0xC8000
callq hipMalloc
movq 16(%rsp), %rdi
movl $409600, %edx # imm = 0x64000
movq %r13, 64(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $819200, %edx # imm = 0xC8000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $10, %ebx
movabsq $42949672980, %r12 # imm = 0xA00000014
movabsq $137438953504, %r13 # imm = 0x2000000020
leaq 72(%rsp), %rbp
leaq 144(%rsp), %r15
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_9 Depth=1
decl %ebx
je .LBB3_12
.LBB3_9: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl $320, 44(%rsp) # imm = 0x140
movl $640, 40(%rsp) # imm = 0x280
movl $320, 36(%rsp) # imm = 0x140
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z6MatmulPfS_S_iii, %edi
movq %r15, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 24(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movl $819200, %edx # imm = 0xC8000
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movl $819200, %edi # imm = 0xC8000
callq malloc
movq %rax, %r12
movq 64(%rsp), %r15 # 8-byte Reload
movq %r15, %rax
.p2align 4, 0x90
.LBB3_13: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
# Child Loop BB3_15 Depth 3
leaq (%rbx,%rbx,4), %rcx
shlq $9, %rcx
addq %r12, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_14: # %.preheader.i82
# Parent Loop BB3_13 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_15 Depth 3
xorpd %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_15: # %.lr.ph.i
# Parent Loop BB3_13 Depth=1
# Parent Loop BB3_14 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $2560, %rdi # imm = 0xA00
cmpq $320, %r8 # imm = 0x140
jne .LBB3_15
# %bb.16: # %._crit_edge.i86
# in Loop: Header=BB3_14 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $640, %rsi # imm = 0x280
jne .LBB3_14
# %bb.17: # %._crit_edge31.i
# in Loop: Header=BB3_13 Depth=1
incq %rbx
addq $1280, %rax # imm = 0x500
cmpq $320, %rbx # imm = 0x140
jne .LBB3_13
# %bb.18: # %.preheader.preheader
xorpd %xmm0, %xmm0
xorl %eax, %eax
movq %r13, %rcx
movq %r12, %rdx
.p2align 4, 0x90
.LBB3_19: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_20: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rdx,%rsi,4), %xmm1
addss %xmm1, %xmm0
incq %rsi
cmpq $640, %rsi # imm = 0x280
jne .LBB3_20
# %bb.21: # %_Z7computePfS_S_iii.exit
# in Loop: Header=BB3_19 Depth=1
incq %rax
addq $2560, %rdx # imm = 0xA00
addq $2560, %rcx # imm = 0xA00
cmpq $320, %rax # imm = 0x140
jne .LBB3_19
# %bb.22:
divss .LCPI3_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatmulPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatmulPfS_S_iii,@object # @_Z6MatmulPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z6MatmulPfS_S_iii
.p2align 3, 0x0
_Z6MatmulPfS_S_iii:
.quad _Z21__device_stub__MatmulPfS_S_iii
.size _Z6MatmulPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU time = %lf s\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Check result %f (should be zero)\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatmulPfS_S_iii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatmulPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatmulPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
__global__
void saxpy(float x[],float y[],float a,int N){
//printf("Hello World! My threadId is %d\n",threadIdx.x);
//printf("I am a part of block : %d\n",blockIdx.x);
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < N)
y[i] = a * x[i] + y[i];
}
int main(){
int ARRAY_SIZE = 100000000;
int threadsPerBlock = 256;
int numBlocks = (int)ARRAY_SIZE / 256 + 1;
size_t size = ARRAY_SIZE*sizeof(float);
// allocate memory in host
float* X = (float*) malloc(size);
float* Y = (float*) malloc(size);
float A = 6.0;
// initialize the array
for(int i=0;i<ARRAY_SIZE;i++){
X[i] = ((float)rand()/(float)(RAND_MAX) * A);
Y[i] = ((float)rand()/(float)(RAND_MAX) * A);
}
// allocate memory in device
float* dX;
float* dY;
cudaMalloc(&dX, size);
cudaMalloc(&dY, size);
// copy from host to device
cudaMemcpy(dX, X, size, cudaMemcpyHostToDevice);
cudaMemcpy(dY, Y, size, cudaMemcpyHostToDevice);
// compute on CPU
printf("Computing SAXPY on the CPU... ");
auto t_start = chrono::high_resolution_clock::now();
for(int i=0;i<ARRAY_SIZE;i++){
Y[i] = A*X[i] + Y[i];
}
auto t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
// compute on GPU
printf("Computing SAXPY on the GPU... ");
t_start = chrono::high_resolution_clock::now();
saxpy<<<numBlocks,threadsPerBlock>>>(dX,dY,A,ARRAY_SIZE);
t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
//cudaDeviceSynchronize();
// copy result to host
cudaMemcpy(X, dY, size, cudaMemcpyDeviceToHost);
printf("Comparing the output for each implementation... ");
for(int i=0;i<ARRAY_SIZE;i++){
if( abs(Y[i] - X[i]) > 1e-05 ){
cout<<"outputs do not match: "<<abs(Y[i] - X[i])<<"\n";
//exit(0);
}
}
cout<<"Correct!\n";
exit(0);
} | code for sm_80
Function : _Z5saxpyPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
__global__
void saxpy(float x[],float y[],float a,int N){
//printf("Hello World! My threadId is %d\n",threadIdx.x);
//printf("I am a part of block : %d\n",blockIdx.x);
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < N)
y[i] = a * x[i] + y[i];
}
int main(){
int ARRAY_SIZE = 100000000;
int threadsPerBlock = 256;
int numBlocks = (int)ARRAY_SIZE / 256 + 1;
size_t size = ARRAY_SIZE*sizeof(float);
// allocate memory in host
float* X = (float*) malloc(size);
float* Y = (float*) malloc(size);
float A = 6.0;
// initialize the array
for(int i=0;i<ARRAY_SIZE;i++){
X[i] = ((float)rand()/(float)(RAND_MAX) * A);
Y[i] = ((float)rand()/(float)(RAND_MAX) * A);
}
// allocate memory in device
float* dX;
float* dY;
cudaMalloc(&dX, size);
cudaMalloc(&dY, size);
// copy from host to device
cudaMemcpy(dX, X, size, cudaMemcpyHostToDevice);
cudaMemcpy(dY, Y, size, cudaMemcpyHostToDevice);
// compute on CPU
printf("Computing SAXPY on the CPU... ");
auto t_start = chrono::high_resolution_clock::now();
for(int i=0;i<ARRAY_SIZE;i++){
Y[i] = A*X[i] + Y[i];
}
auto t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
// compute on GPU
printf("Computing SAXPY on the GPU... ");
t_start = chrono::high_resolution_clock::now();
saxpy<<<numBlocks,threadsPerBlock>>>(dX,dY,A,ARRAY_SIZE);
t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
//cudaDeviceSynchronize();
// copy result to host
cudaMemcpy(X, dY, size, cudaMemcpyDeviceToHost);
printf("Comparing the output for each implementation... ");
for(int i=0;i<ARRAY_SIZE;i++){
if( abs(Y[i] - X[i]) > 1e-05 ){
cout<<"outputs do not match: "<<abs(Y[i] - X[i])<<"\n";
//exit(0);
}
}
cout<<"Correct!\n";
exit(0);
} | .file "tmpxft_001b4785_00000000-6_exercise2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.type _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, @function
_Z28__device_stub__Z5saxpyPfS_fiPfS_fi:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, .-_Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.globl _Z5saxpyPfS_fi
.type _Z5saxpyPfS_fi, @function
_Z5saxpyPfS_fi:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z5saxpyPfS_fi, .-_Z5saxpyPfS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Computing SAXPY on the CPU... "
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Done! in "
.LC5:
.string " ms\n\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Computing SAXPY on the GPU... "
.align 8
.LC7:
.string "Comparing the output for each implementation... "
.section .rodata.str1.1
.LC10:
.string "outputs do not match: "
.LC11:
.string "\n"
.LC12:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %r12d
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp,%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx,%r12)
addq $4, %r12
cmpq $400000000, %r12
jne .L12
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
.L13:
movaps %xmm1, %xmm0
mulss 0(%rbp,%rax), %xmm0
addss (%rbx,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $400000000, %rax
jne .L13
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r12, %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
divsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $390626, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L14:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r12, %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
divsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $400000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC10(%rip), %r13
jmp .L17
.L24:
movl $100000000, %edx
movss .LC1(%rip), %xmm0
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
jmp .L14
.L15:
addq $4, %r12
cmpq $400000000, %r12
je .L25
.L17:
movss (%rbx,%r12), %xmm0
subss 0(%rbp,%r12), %xmm0
andps .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC9(%rip), %xmm0
jbe .L15
movl $22, %edx
movq %r13, %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss (%rbx,%r12), %xmm0
subss 0(%rbp,%r12), %xmm0
andps .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC11(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L15
.L25:
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z5saxpyPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1086324736
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
__global__
void saxpy(float x[],float y[],float a,int N){
//printf("Hello World! My threadId is %d\n",threadIdx.x);
//printf("I am a part of block : %d\n",blockIdx.x);
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < N)
y[i] = a * x[i] + y[i];
}
int main(){
int ARRAY_SIZE = 100000000;
int threadsPerBlock = 256;
int numBlocks = (int)ARRAY_SIZE / 256 + 1;
size_t size = ARRAY_SIZE*sizeof(float);
// allocate memory in host
float* X = (float*) malloc(size);
float* Y = (float*) malloc(size);
float A = 6.0;
// initialize the array
for(int i=0;i<ARRAY_SIZE;i++){
X[i] = ((float)rand()/(float)(RAND_MAX) * A);
Y[i] = ((float)rand()/(float)(RAND_MAX) * A);
}
// allocate memory in device
float* dX;
float* dY;
cudaMalloc(&dX, size);
cudaMalloc(&dY, size);
// copy from host to device
cudaMemcpy(dX, X, size, cudaMemcpyHostToDevice);
cudaMemcpy(dY, Y, size, cudaMemcpyHostToDevice);
// compute on CPU
printf("Computing SAXPY on the CPU... ");
auto t_start = chrono::high_resolution_clock::now();
for(int i=0;i<ARRAY_SIZE;i++){
Y[i] = A*X[i] + Y[i];
}
auto t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
// compute on GPU
printf("Computing SAXPY on the GPU... ");
t_start = chrono::high_resolution_clock::now();
saxpy<<<numBlocks,threadsPerBlock>>>(dX,dY,A,ARRAY_SIZE);
t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
//cudaDeviceSynchronize();
// copy result to host
cudaMemcpy(X, dY, size, cudaMemcpyDeviceToHost);
printf("Comparing the output for each implementation... ");
for(int i=0;i<ARRAY_SIZE;i++){
if( abs(Y[i] - X[i]) > 1e-05 ){
cout<<"outputs do not match: "<<abs(Y[i] - X[i])<<"\n";
//exit(0);
}
}
cout<<"Correct!\n";
exit(0);
} | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
__global__
void saxpy(float x[],float y[],float a,int N){
//printf("Hello World! My threadId is %d\n",threadIdx.x);
//printf("I am a part of block : %d\n",blockIdx.x);
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < N)
y[i] = a * x[i] + y[i];
}
int main(){
int ARRAY_SIZE = 100000000;
int threadsPerBlock = 256;
int numBlocks = (int)ARRAY_SIZE / 256 + 1;
size_t size = ARRAY_SIZE*sizeof(float);
// allocate memory in host
float* X = (float*) malloc(size);
float* Y = (float*) malloc(size);
float A = 6.0;
// initialize the array
for(int i=0;i<ARRAY_SIZE;i++){
X[i] = ((float)rand()/(float)(RAND_MAX) * A);
Y[i] = ((float)rand()/(float)(RAND_MAX) * A);
}
// allocate memory in device
float* dX;
float* dY;
hipMalloc(&dX, size);
hipMalloc(&dY, size);
// copy from host to device
hipMemcpy(dX, X, size, hipMemcpyHostToDevice);
hipMemcpy(dY, Y, size, hipMemcpyHostToDevice);
// compute on CPU
printf("Computing SAXPY on the CPU... ");
auto t_start = chrono::high_resolution_clock::now();
for(int i=0;i<ARRAY_SIZE;i++){
Y[i] = A*X[i] + Y[i];
}
auto t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
// compute on GPU
printf("Computing SAXPY on the GPU... ");
t_start = chrono::high_resolution_clock::now();
saxpy<<<numBlocks,threadsPerBlock>>>(dX,dY,A,ARRAY_SIZE);
t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
//cudaDeviceSynchronize();
// copy result to host
hipMemcpy(X, dY, size, hipMemcpyDeviceToHost);
printf("Comparing the output for each implementation... ");
for(int i=0;i<ARRAY_SIZE;i++){
if( abs(Y[i] - X[i]) > 1e-05 ){
cout<<"outputs do not match: "<<abs(Y[i] - X[i])<<"\n";
//exit(0);
}
}
cout<<"Correct!\n";
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
__global__
void saxpy(float x[],float y[],float a,int N){
//printf("Hello World! My threadId is %d\n",threadIdx.x);
//printf("I am a part of block : %d\n",blockIdx.x);
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < N)
y[i] = a * x[i] + y[i];
}
int main(){
int ARRAY_SIZE = 100000000;
int threadsPerBlock = 256;
int numBlocks = (int)ARRAY_SIZE / 256 + 1;
size_t size = ARRAY_SIZE*sizeof(float);
// allocate memory in host
float* X = (float*) malloc(size);
float* Y = (float*) malloc(size);
float A = 6.0;
// initialize the array
for(int i=0;i<ARRAY_SIZE;i++){
X[i] = ((float)rand()/(float)(RAND_MAX) * A);
Y[i] = ((float)rand()/(float)(RAND_MAX) * A);
}
// allocate memory in device
float* dX;
float* dY;
hipMalloc(&dX, size);
hipMalloc(&dY, size);
// copy from host to device
hipMemcpy(dX, X, size, hipMemcpyHostToDevice);
hipMemcpy(dY, Y, size, hipMemcpyHostToDevice);
// compute on CPU
printf("Computing SAXPY on the CPU... ");
auto t_start = chrono::high_resolution_clock::now();
for(int i=0;i<ARRAY_SIZE;i++){
Y[i] = A*X[i] + Y[i];
}
auto t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
// compute on GPU
printf("Computing SAXPY on the GPU... ");
t_start = chrono::high_resolution_clock::now();
saxpy<<<numBlocks,threadsPerBlock>>>(dX,dY,A,ARRAY_SIZE);
t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
//cudaDeviceSynchronize();
// copy result to host
hipMemcpy(X, dY, size, hipMemcpyDeviceToHost);
printf("Comparing the output for each implementation... ");
for(int i=0;i<ARRAY_SIZE;i++){
if( abs(Y[i] - X[i]) > 1e-05 ){
cout<<"outputs do not match: "<<abs(Y[i] - X[i])<<"\n";
//exit(0);
}
}
cout<<"Correct!\n";
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPfS_fi
.globl _Z5saxpyPfS_fi
.p2align 8
.type _Z5saxpyPfS_fi,@function
_Z5saxpyPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPfS_fi, .Lfunc_end0-_Z5saxpyPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
__global__
void saxpy(float x[],float y[],float a,int N){
//printf("Hello World! My threadId is %d\n",threadIdx.x);
//printf("I am a part of block : %d\n",blockIdx.x);
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i < N)
y[i] = a * x[i] + y[i];
}
int main(){
int ARRAY_SIZE = 100000000;
int threadsPerBlock = 256;
int numBlocks = (int)ARRAY_SIZE / 256 + 1;
size_t size = ARRAY_SIZE*sizeof(float);
// allocate memory in host
float* X = (float*) malloc(size);
float* Y = (float*) malloc(size);
float A = 6.0;
// initialize the array
for(int i=0;i<ARRAY_SIZE;i++){
X[i] = ((float)rand()/(float)(RAND_MAX) * A);
Y[i] = ((float)rand()/(float)(RAND_MAX) * A);
}
// allocate memory in device
float* dX;
float* dY;
hipMalloc(&dX, size);
hipMalloc(&dY, size);
// copy from host to device
hipMemcpy(dX, X, size, hipMemcpyHostToDevice);
hipMemcpy(dY, Y, size, hipMemcpyHostToDevice);
// compute on CPU
printf("Computing SAXPY on the CPU... ");
auto t_start = chrono::high_resolution_clock::now();
for(int i=0;i<ARRAY_SIZE;i++){
Y[i] = A*X[i] + Y[i];
}
auto t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
// compute on GPU
printf("Computing SAXPY on the GPU... ");
t_start = chrono::high_resolution_clock::now();
saxpy<<<numBlocks,threadsPerBlock>>>(dX,dY,A,ARRAY_SIZE);
t_end = chrono::high_resolution_clock::now();
cout<<"Done! in "<<chrono::duration<double, milli>(t_end-t_start).count()<<" ms\n\n";
//cudaDeviceSynchronize();
// copy result to host
hipMemcpy(X, dY, size, hipMemcpyDeviceToHost);
printf("Comparing the output for each implementation... ");
for(int i=0;i<ARRAY_SIZE;i++){
if( abs(Y[i] - X[i]) > 1e-05 ){
cout<<"outputs do not match: "<<abs(Y[i] - X[i])<<"\n";
//exit(0);
}
}
cout<<"Correct!\n";
exit(0);
} | .text
.file "exercise2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__saxpyPfS_fi # -- Begin function _Z20__device_stub__saxpyPfS_fi
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_fi,@function
_Z20__device_stub__saxpyPfS_fi: # @_Z20__device_stub__saxpyPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPfS_fi, .Lfunc_end0-_Z20__device_stub__saxpyPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x40c00000 # float 6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_4:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $100000000, %r15 # imm = 0x5F5E100
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $100000000, %r12 # imm = 0x5F5E100
jne .LBB1_3
# %bb.4:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 390370(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1086324736, 20(%rsp) # imm = 0x40C00000
movl $100000000, 16(%rsp) # imm = 0x5F5E100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd .LCPI1_4(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
incq %r15
cmpq $100000000, %r15 # imm = 0x5F5E100
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm0
andps .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm0
andps .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI1_4(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB1_9
.LBB1_10:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPfS_fi,@object # @_Z5saxpyPfS_fi
.section .rodata,"a",@progbits
.globl _Z5saxpyPfS_fi
.p2align 3, 0x0
_Z5saxpyPfS_fi:
.quad _Z20__device_stub__saxpyPfS_fi
.size _Z5saxpyPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Computing SAXPY on the CPU... "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Done! in "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ms\n\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Computing SAXPY on the GPU... "
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Comparing the output for each implementation... "
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "outputs do not match: "
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Correct!\n"
.size .L.str.7, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPfS_fi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPfS_fi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPfS_fi
.globl _Z5saxpyPfS_fi
.p2align 8
.type _Z5saxpyPfS_fi,@function
_Z5saxpyPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPfS_fi, .Lfunc_end0-_Z5saxpyPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b4785_00000000-6_exercise2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.type _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, @function
_Z28__device_stub__Z5saxpyPfS_fiPfS_fi:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, .-_Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.globl _Z5saxpyPfS_fi
.type _Z5saxpyPfS_fi, @function
_Z5saxpyPfS_fi:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z5saxpyPfS_fi, .-_Z5saxpyPfS_fi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Computing SAXPY on the CPU... "
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Done! in "
.LC5:
.string " ms\n\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Computing SAXPY on the GPU... "
.align 8
.LC7:
.string "Comparing the output for each implementation... "
.section .rodata.str1.1
.LC10:
.string "outputs do not match: "
.LC11:
.string "\n"
.LC12:
.string "Correct!\n"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %r12d
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, 0(%rbp,%r12)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx,%r12)
addq $4, %r12
cmpq $400000000, %r12
jne .L12
movq %rsp, %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
.L13:
movaps %xmm1, %xmm0
mulss 0(%rbp,%rax), %xmm0
addss (%rbx,%rax), %xmm0
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $400000000, %rax
jne .L13
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r12, %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
divsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $390626, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L14:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r12, %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
divsd .LC4(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $400000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC10(%rip), %r13
jmp .L17
.L24:
movl $100000000, %edx
movss .LC1(%rip), %xmm0
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
jmp .L14
.L15:
addq $4, %r12
cmpq $400000000, %r12
je .L25
.L17:
movss (%rbx,%r12), %xmm0
subss 0(%rbp,%r12), %xmm0
andps .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC9(%rip), %xmm0
jbe .L15
movl $22, %edx
movq %r13, %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss (%rbx,%r12), %xmm0
subss 0(%rbp,%r12), %xmm0
andps .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC11(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L15
.L25:
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z5saxpyPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1086324736
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20__device_stub__saxpyPfS_fi # -- Begin function _Z20__device_stub__saxpyPfS_fi
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_fi,@function
_Z20__device_stub__saxpyPfS_fi: # @_Z20__device_stub__saxpyPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPfS_fi, .Lfunc_end0-_Z20__device_stub__saxpyPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x40c00000 # float 6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_4:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq $100000000, %r15 # imm = 0x5F5E100
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $100000000, %r12 # imm = 0x5F5E100
jne .LBB1_3
# %bb.4:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 390370(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1086324736, 20(%rsp) # imm = 0x40C00000
movl $100000000, 16(%rsp) # imm = 0x5F5E100
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r15, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
divsd .LCPI1_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movsd .LCPI1_4(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
incq %r15
cmpq $100000000, %r15 # imm = 0x5F5E100
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm0
andps .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm1, %xmm0
jbe .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rbx,%r15,4), %xmm0
andps .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI1_4(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB1_9
.LBB1_10:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPfS_fi,@object # @_Z5saxpyPfS_fi
.section .rodata,"a",@progbits
.globl _Z5saxpyPfS_fi
.p2align 3, 0x0
_Z5saxpyPfS_fi:
.quad _Z20__device_stub__saxpyPfS_fi
.size _Z5saxpyPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Computing SAXPY on the CPU... "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Done! in "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ms\n\n"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Computing SAXPY on the GPU... "
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Comparing the output for each implementation... "
.size .L.str.4, 50
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "outputs do not match: "
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Correct!\n"
.size .L.str.7, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPfS_fi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPfS_fi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ double dnorm(float x, float mu, float sigma)
{
float std = (x - mu)/sigma;
float e = exp( - 0.5 * std * std);
return(e / ( sigma * sqrt(2 * 3.141592653589793)));
}
__global__ void log_truncNorm(float *out, float *unifVals, int N)
{
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
/* how big is each block within a grid */
int blocksize = blockDim.x * blockDim.y * blockDim.z;
/* get thread within a block */
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < N) {
// 0.3413447460685 is pnorm(1) - pnorm(0), i.e. Pr( 0 <= Z <= 1) for Z ~ N(0, 1)
out[idx] = log(unifVals[idx]) * dnorm(unifVals[idx], 0, 1)/0.3413447460685;
}
} | code for sm_80
Function : _Z13log_truncNormPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002300 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea80000002200 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ee20000002100 */
/*0060*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0x8], R5 ; /* 0x0000020000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x008fca00078e0209 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fcc00078e0207 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000a2000c1e1900 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, 0x652b82fe ; /* 0x652b82feff087424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x3e0 ; /* 0x000002c000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fe200078e00ff */
/*0150*/ MUFU.RCP64H R7, 2.5066280364990234375 ; /* 0x40040d9300077908 */
/* 0x001e300000001800 */
/*0160*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e620000201800 */
/*0170*/ FSETP.GEU.AND P0, PT, R6, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fe20003f0e000 */
/*0180*/ DMUL R4, R2, -0.5 ; /* 0xbfe0000002047828 */
/* 0x002e4c0000000000 */
/*0190*/ DMUL R2, R2, R4 ; /* 0x0000000402027228 */
/* 0x002e4c0000000000 */
/*01a0*/ DFMA R4, R2, R8, 6.75539944105574400000e+15 ; /* 0x433800000204742b */
/* 0x002e480000000008 */
/*01b0*/ FSETP.GEU.AND P1, PT, |R3|, 4.1917929649353027344, PT ; /* 0x4086232b0300780b */
/* 0x000fe40003f2e200 */
/*01c0*/ DADD R8, R4, -6.75539944105574400000e+15 ; /* 0xc338000004087429 */
/* 0x002e4c0000000000 */
/*01d0*/ DFMA R10, R8, c[0x2][0x0], R2 ; /* 0x00800000080a7a2b */
/* 0x002e4c0000000002 */
/*01e0*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x002e4c000000000a */
/*01f0*/ DFMA R10, R8, R12, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x002e4c000000000c */
/*0200*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x002e4c000000000a */
/*0210*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x002e4c000000000a */
/*0220*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x002e4c000000000a */
/*0230*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x002e4c000000000a */
/*0240*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x002e4c000000000a */
/*0250*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x002e4c000000000a */
/*0260*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x002e4c000000000a */
/*0270*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x002e4c000000000a */
/*0280*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x002e4c000000000a */
/*0290*/ DFMA R12, R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x0022a4000000000a */
/*02a0*/ FMUL R9, R6, 8388608 ; /* 0x4b00000006097820 */
/* 0x002fe40000400000 */
/*02b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1ff62705 ; /* 0x1ff62705ff087424 */
/* 0x000fc600078e00ff */
/*02c0*/ FSEL R10, R9, R6, !P0 ; /* 0x00000006090a7208 */
/* 0x000fe20004000000 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40040d93 ; /* 0x40040d93ff097424 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD R15, R4, 0x100000, R13 ; /* 0x00100000040f7824 */
/* 0x004fe400078e020d */
/*02f0*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0300*/ @!P1 BRA 0x3d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GEU.AND P2, PT, |R3|, 4.2275390625, PT ; /* 0x408748000300780b */
/* 0x001fe20003f4e200 */
/*0320*/ DADD R14, R2, +INF ; /* 0x7ff00000020e7429 */
/* 0x000fc80000000000 */
/*0330*/ DSETP.GEU.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e0c0003f2e000 */
/*0340*/ FSEL R14, R14, RZ, P1 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000800000 */
/*0350*/ @!P2 LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x000000040405a211 */
/* 0x000fe400078f08ff */
/*0360*/ FSEL R15, R15, RZ, P1 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000800000 */
/*0370*/ @!P2 SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff05a819 */
/* 0x000fc80000011405 */
/*0380*/ @!P2 IADD3 R2, R4, -R5, RZ ; /* 0x800000050402a210 */
/* 0x000fe20007ffe0ff */
/*0390*/ @!P2 IMAD R13, R5, 0x100000, R13 ; /* 0x00100000050da824 */
/* 0x000fc600078e020d */
/*03a0*/ @!P2 LEA R3, R2, 0x3ff00000, 0x14 ; /* 0x3ff000000203a811 */
/* 0x000fe200078ea0ff */
/*03b0*/ @!P2 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff02a224 */
/* 0x000fcc00078e00ff */
/*03c0*/ @!P2 DMUL R14, R12, R2 ; /* 0x000000020c0ea228 */
/* 0x00004c0000000000 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*03f0*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x002e220000301000 */
/*0400*/ IADD3 R13, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a0d7810 */
/* 0x040fe20007ffe0ff */
/*0410*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff047424 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.GE.U32.AND P1, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe20003f26070 */
/*0430*/ BSSY B0, 0x700 ; /* 0x000002c000007945 */
/* 0x000fe20003800000 */
/*0440*/ DFMA R2, R6, -R8, 1 ; /* 0x3ff000000602742b */
/* 0x000e620000000808 */
/*0450*/ LOP3.LUT R13, R13, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000d0d7812 */
/* 0x000fca00078ec0ff */
/*0460*/ DFMA R2, R2, R2, R2 ; /* 0x000000020202722b */
/* 0x002e620000000002 */
/*0470*/ IMAD.IADD R11, R10, 0x1, -R13 ; /* 0x000000010a0b7824 */
/* 0x000fe400078e0a0d */
/*0480*/ I2F R13, R13 ; /* 0x0000000d000d7306 */
/* 0x000ea40000201400 */
/*0490*/ FADD R11, R11, -1 ; /* 0xbf8000000b0b7421 */
/* 0x000fe20000000000 */
/*04a0*/ DFMA R6, R6, R2, R6 ; /* 0x000000020606722b */
/* 0x0020460000000006 */
/*04b0*/ FFMA R4, R11.reuse, -R4, 0.14084610342979431152 ; /* 0x3e1039f60b047423 */
/* 0x040fe40000000804 */
/*04c0*/ F2F.F64.F32 R2, R14 ; /* 0x0000000e00027310 */
/* 0x001e220000201800 */
/*04d0*/ DFMA R8, R6, -R8, 1 ; /* 0x3ff000000608742b */
/* 0x002e620000000808 */
/*04e0*/ FFMA R4, R11, R4, -0.12148627638816833496 ; /* 0xbdf8cdcc0b047423 */
/* 0x000fc80000000004 */
/*04f0*/ FFMA R4, R11, R4, 0.13980610668659210205 ; /* 0x3e0f29550b047423 */
/* 0x000fe20000000004 */
/*0500*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x0022060000000006 */
/*0510*/ FFMA R6, R11, R4, -0.16684235632419586182 ; /* 0xbe2ad8b90b067423 */
/* 0x002fc80000000004 */
/*0520*/ FFMA R6, R11, R6, 0.20012299716472625732 ; /* 0x3e4ced0b0b067423 */
/* 0x000fe20000000006 */
/*0530*/ DMUL R4, R2, R8 ; /* 0x0000000802047228 */
/* 0x001e220000000000 */
/*0540*/ FSETP.GEU.AND P3, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fe40003f6e200 */
/*0550*/ FFMA R12, R11, R6, -0.24999669194221496582 ; /* 0xbe7fff220b0c7423 */
/* 0x000fc60000000006 */
/*0560*/ DFMA R6, R4, c[0x2][0x58], R2 ; /* 0x0080160004067a2b */
/* 0x001e220000000002 */
/*0570*/ FFMA R12, R11, R12, 0.33333182334899902344 ; /* 0x3eaaaa780b0c7423 */
/* 0x000fc8000000000c */
/*0580*/ FFMA R12, R11.reuse, R12, -0.5 ; /* 0xbf0000000b0c7423 */
/* 0x040fe2000000000c */
/*0590*/ DFMA R4, R8, R6, R4 ; /* 0x000000060804722b */
/* 0x0010640000000004 */
/*05a0*/ FSEL R6, RZ, -23, P0 ; /* 0xc1b80000ff067808 */
/* 0x001fe20000000000 */
/*05b0*/ FMUL R12, R11, R12 ; /* 0x0000000c0b0c7220 */
/* 0x000fe20000400000 */
/*05c0*/ FSETP.NEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe20003f0d000 */
/*05d0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, 0x7f800000 ; /* 0x7f800000ff071424 */
/* 0x000fe400078e00ff */
/*05e0*/ FFMA R6, R13, 1.1920928955078125e-07, R6 ; /* 0x340000000d067823 */
/* 0x004fe40000000006 */
/*05f0*/ FFMA R11, R11, R12, R11 ; /* 0x0000000c0b0b7223 */
/* 0x000fc4000000000b */
/*0600*/ FFMA R8, RZ, 2.0633285045623779297, R5 ; /* 0x40040d93ff087823 */
/* 0x002fe40000000005 */
/*0610*/ FFMA R6, R6, 0.69314718246459960938, R11 ; /* 0x3f31721806067823 */
/* 0x000fe2000000000b */
/*0620*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*0630*/ @P1 FFMA R6, R10, R7, +INF ; /* 0x7f8000000a061423 */
/* 0x000fe20000000007 */
/*0640*/ FSETP.GT.AND P2, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fc80003f44200 */
/*0650*/ FSEL R10, R6, -INF , P0 ; /* 0xff800000060a7808 */
/* 0x000fd20000000000 */
/*0660*/ @P2 BRA P3, 0x6f0 ; /* 0x0000008000002947 */
/* 0x000fea0001800000 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0680*/ MOV R6, 0x1ff62705 ; /* 0x1ff6270500067802 */
/* 0x000fe20000000f00 */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*06a0*/ MOV R12, 0x6d0 ; /* 0x000006d0000c7802 */
/* 0x000fe20000000f00 */
/*06b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40040d93 ; /* 0x40040d93ff077424 */
/* 0x000fe400078e00ff */
/*06c0*/ CALL.REL.NOINC 0x8f0 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ MUFU.RCP64H R7, 0.34134459495544433594 ; /* 0x3fd5d89700077908 */
/* 0x000e220000001800 */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, -0x5dbe5c0b ; /* 0xa241a3f5ff0c7424 */
/* 0x000fe200078e00ff */
/*0720*/ BSSY B0, 0x8a0 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*0730*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd5d897 ; /* 0x3fd5d897ff0d7424 */
/* 0x000fe400078e00ff */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fcc00078e00ff */
/*0750*/ DFMA R2, R6, -R12, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c000000080c */
/*0760*/ DFMA R8, R2, R2, R2 ; /* 0x000000020208722b */
/* 0x0010880000000002 */
/*0770*/ F2F.F64.F32 R2, R10 ; /* 0x0000000a00027310 */
/* 0x001e240000201800 */
/*0780*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x004e8c0000000006 */
/*0790*/ DFMA R6, R8, -R12, 1 ; /* 0x3ff000000806742b */
/* 0x004e8c000000080c */
/*07a0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x004fc80000000008 */
/*07b0*/ DMUL R12, R2, R4 ; /* 0x00000004020c7228 */
/* 0x001e0c0000000000 */
/*07c0*/ DMUL R2, R12, R6 ; /* 0x000000060c027228 */
/* 0x001e080000000000 */
/*07d0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*07e0*/ DFMA R4, R2, c[0x2][0x60], R12 ; /* 0x0080180002047a2b */
/* 0x001e0c000000000c */
/*07f0*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x001e140000000002 */
/*0800*/ FFMA R4, RZ, 1.670672297477722168, R3 ; /* 0x3fd5d897ff047823 */
/* 0x001fca0000000003 */
/*0810*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*0820*/ @P0 BRA P1, 0x890 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000c */
/*0840*/ MOV R6, 0xa241a3f5 ; /* 0xa241a3f500067802 */
/* 0x000fe20000000f00 */
/*0850*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0860*/ MOV R12, 0x890 ; /* 0x00000890000c7802 */
/* 0x000fe20000000f00 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3fd5d897 ; /* 0x3fd5d897ff077424 */
/* 0x000fe400078e00ff */
/*0880*/ CALL.REL.NOINC 0x8f0 ; /* 0x0000006000007944 */
/* 0x002fea0003c00000 */
/*0890*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08a0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x000e220000301000 */
/*08b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*08c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R11, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f140b */
/*08d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0900*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0910*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*0920*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0930*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0940*/ BSSY B1, 0xe90 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0950*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0970*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fe400078ec0ff */
/*0980*/ LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007147812 */
/* 0x000fc600078ec0ff */
/*0990*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*09a0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*09b0*/ @!P2 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000702a812 */
/* 0x000fe200078ec0ff */
/*09c0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*09d0*/ MUFU.RCP64H R19, R5 ; /* 0x0000000500137308 */
/* 0x001e220000001800 */
/*09e0*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*09f0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0a00*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0a10*/ LOP3.LUT R3, R3, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef809 */
/*0a20*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0a30*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef809 */
/*0a40*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0a50*/ DFMA R22, R18, -R4, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000804 */
/*0a60*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0a70*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0a80*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0a90*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*0aa0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*0ab0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*0ac0*/ @!P0 LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005168812 */
/* 0x000fe400078ec0ff */
/*0ad0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*0ae0*/ DFMA R16, R18, -R4, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000804 */
/*0af0*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0b10*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0b20*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0b30*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0b40*/ DFMA R20, R18, -R4, R2 ; /* 0x800000041214722b */
/* 0x001e0c0000000002 */
/*0b50*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0b60*/ @P0 BRA 0xd30 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R18, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007127812 */
/* 0x001fc800078ec0ff */
/*0b80*/ IADD3 R8, R13.reuse, -R18.reuse, RZ ; /* 0x800000120d087210 */
/* 0x0c0fe40007ffe0ff */
/*0b90*/ ISETP.GE.U32.AND P0, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fe40003f06070 */
/*0ba0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fe40007800200 */
/*0bb0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0bc0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0bd0*/ IMAD.IADD R13, R8, 0x1, -R13 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0d */
/*0be0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0bf0*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0c00*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x002e140000000000 */
/*0c10*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0c20*/ @P0 BRA 0xe80 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0c30*/ DFMA R2, R16, -R4, R2 ; /* 0x800000041002722b */
/* 0x000e220000000002 */
/*0c40*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0c50*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0c60*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0c70*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0c80*/ @!P0 BRA 0xe80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0c90*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0ca0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*0cb0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0cc0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0cd0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*0ce0*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0cf0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0d00*/ FSEL R18, R8, R18, !P0 ; /* 0x0000001208127208 */
/* 0x000fe40004000000 */
/*0d10*/ FSEL R19, R7, R19, !P0 ; /* 0x0000001307137208 */
/* 0x000fe20004000000 */
/*0d20*/ BRA 0xe80 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0d30*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0d40*/ @P0 BRA 0xe60 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0d50*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0d60*/ @P0 BRA 0xe30 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0d70*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0d80*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0d90*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0da0*/ @!P0 BRA 0xe80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0dc0*/ LOP3.LUT R19, R9, 0x80000000, R7, 0x48, !PT ; /* 0x8000000009137812 */
/* 0x000fe400078e4807 */
/*0dd0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0de0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0df0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe200078e00ff */
/*0e00*/ @P0 MOV R18, RZ ; /* 0x000000ff00120202 */
/* 0x000fc60000000f00 */
/*0e10*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0e20*/ BRA 0xe80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0e40*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0e50*/ BRA 0xe80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0e60*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0e70*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*0e80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0e90*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0ea0*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0012 */
/*0eb0*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0ec0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff1300c007950 */
/* 0x000fec0003c3ffff */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ double dnorm(float x, float mu, float sigma)
{
float std = (x - mu)/sigma;
float e = exp( - 0.5 * std * std);
return(e / ( sigma * sqrt(2 * 3.141592653589793)));
}
__global__ void log_truncNorm(float *out, float *unifVals, int N)
{
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
/* how big is each block within a grid */
int blocksize = blockDim.x * blockDim.y * blockDim.z;
/* get thread within a block */
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < N) {
// 0.3413447460685 is pnorm(1) - pnorm(0), i.e. Pr( 0 <= Z <= 1) for Z ~ N(0, 1)
out[idx] = log(unifVals[idx]) * dnorm(unifVals[idx], 0, 1)/0.3413447460685;
}
} | .file "tmpxft_000892f3_00000000-6_log_truncNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5dnormfff
.type _Z5dnormfff, @function
_Z5dnormfff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5dnormfff, .-_Z5dnormfff
.globl _Z36__device_stub__Z13log_truncNormPfS_iPfS_i
.type _Z36__device_stub__Z13log_truncNormPfS_iPfS_i, @function
_Z36__device_stub__Z13log_truncNormPfS_iPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13log_truncNormPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z13log_truncNormPfS_iPfS_i, .-_Z36__device_stub__Z13log_truncNormPfS_iPfS_i
.globl _Z13log_truncNormPfS_i
.type _Z13log_truncNormPfS_i, @function
_Z13log_truncNormPfS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13log_truncNormPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13log_truncNormPfS_i, .-_Z13log_truncNormPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13log_truncNormPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13log_truncNormPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ double dnorm(float x, float mu, float sigma)
{
float std = (x - mu)/sigma;
float e = exp( - 0.5 * std * std);
return(e / ( sigma * sqrt(2 * 3.141592653589793)));
}
__global__ void log_truncNorm(float *out, float *unifVals, int N)
{
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
/* how big is each block within a grid */
int blocksize = blockDim.x * blockDim.y * blockDim.z;
/* get thread within a block */
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < N) {
// 0.3413447460685 is pnorm(1) - pnorm(0), i.e. Pr( 0 <= Z <= 1) for Z ~ N(0, 1)
out[idx] = log(unifVals[idx]) * dnorm(unifVals[idx], 0, 1)/0.3413447460685;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double dnorm(float x, float mu, float sigma)
{
float std = (x - mu)/sigma;
float e = exp( - 0.5 * std * std);
return(e / ( sigma * sqrt(2 * 3.141592653589793)));
}
__global__ void log_truncNorm(float *out, float *unifVals, int N)
{
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
/* how big is each block within a grid */
int blocksize = blockDim.x * blockDim.y * blockDim.z;
/* get thread within a block */
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < N) {
// 0.3413447460685 is pnorm(1) - pnorm(0), i.e. Pr( 0 <= Z <= 1) for Z ~ N(0, 1)
out[idx] = log(unifVals[idx]) * dnorm(unifVals[idx], 0, 1)/0.3413447460685;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double dnorm(float x, float mu, float sigma)
{
float std = (x - mu)/sigma;
float e = exp( - 0.5 * std * std);
return(e / ( sigma * sqrt(2 * 3.141592653589793)));
}
__global__ void log_truncNorm(float *out, float *unifVals, int N)
{
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
/* how big is each block within a grid */
int blocksize = blockDim.x * blockDim.y * blockDim.z;
/* get thread within a block */
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < N) {
// 0.3413447460685 is pnorm(1) - pnorm(0), i.e. Pr( 0 <= Z <= 1) for Z ~ N(0, 1)
out[idx] = log(unifVals[idx]) * dnorm(unifVals[idx], 0, 1)/0.3413447460685;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13log_truncNormPfS_i
.globl _Z13log_truncNormPfS_i
.p2align 8
.type _Z13log_truncNormPfS_i,@function
_Z13log_truncNormPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s4, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s3, s[0:1], 0x10
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v12, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[2:3], -0.5
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
v_rndne_f64_e32 v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_mov_b32 s3, 0x40040d93
s_mov_b32 s2, 0x1ff62705
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
s_mov_b32 s1, 0x3fd5d897
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_cndmask_b32_e64 v3, 0, v5, s0
v_cmp_gt_f32_e64 s0, 0x800000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_mul_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
v_cndmask_b32_e64 v10, 1.0, 0x4f800000, s0
v_mul_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_log_f32_e32 v10, v10
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x3f317217, v10
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v10|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v10, 0x3f317217, -v6
v_fmamk_f32 v7, v10, 0x3377d1cf, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v7
v_cndmask_b32_e64 v7, 0, 0x41b17218, s0
s_mov_b32 s0, 0xa241a3f5
v_cndmask_b32_e32 v6, v10, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_cvt_f64_f32_e32 v[6:7], v6
v_div_fixup_f64 v[2:3], v[4:5], s[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[6:7]
v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13log_truncNormPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13log_truncNormPfS_i, .Lfunc_end0-_Z13log_truncNormPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13log_truncNormPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13log_truncNormPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double dnorm(float x, float mu, float sigma)
{
float std = (x - mu)/sigma;
float e = exp( - 0.5 * std * std);
return(e / ( sigma * sqrt(2 * 3.141592653589793)));
}
__global__ void log_truncNorm(float *out, float *unifVals, int N)
{
int myblock = blockIdx.x + blockIdx.y * gridDim.x;
/* how big is each block within a grid */
int blocksize = blockDim.x * blockDim.y * blockDim.z;
/* get thread within a block */
int subthread = threadIdx.z*(blockDim.x * blockDim.y) + threadIdx.y*blockDim.x + threadIdx.x;
int idx = myblock * blocksize + subthread;
if(idx < N) {
// 0.3413447460685 is pnorm(1) - pnorm(0), i.e. Pr( 0 <= Z <= 1) for Z ~ N(0, 1)
out[idx] = log(unifVals[idx]) * dnorm(unifVals[idx], 0, 1)/0.3413447460685;
}
} | .text
.file "log_truncNorm.hip"
.globl _Z28__device_stub__log_truncNormPfS_i # -- Begin function _Z28__device_stub__log_truncNormPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__log_truncNormPfS_i,@function
_Z28__device_stub__log_truncNormPfS_i: # @_Z28__device_stub__log_truncNormPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13log_truncNormPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__log_truncNormPfS_i, .Lfunc_end0-_Z28__device_stub__log_truncNormPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13log_truncNormPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13log_truncNormPfS_i,@object # @_Z13log_truncNormPfS_i
.section .rodata,"a",@progbits
.globl _Z13log_truncNormPfS_i
.p2align 3, 0x0
_Z13log_truncNormPfS_i:
.quad _Z28__device_stub__log_truncNormPfS_i
.size _Z13log_truncNormPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13log_truncNormPfS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__log_truncNormPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13log_truncNormPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13log_truncNormPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.Z ; /* 0x0000000000057919 */
/* 0x000e680000002300 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea80000002200 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000ee20000002100 */
/*0060*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0x8], R5 ; /* 0x0000020000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x004fc800078e0207 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x008fca00078e0209 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fcc00078e0207 */
/*00f0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000a2000c1e1900 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, 0x652b82fe ; /* 0x652b82feff087424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x3e0 ; /* 0x000002c000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fe200078e00ff */
/*0150*/ MUFU.RCP64H R7, 2.5066280364990234375 ; /* 0x40040d9300077908 */
/* 0x001e300000001800 */
/*0160*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e620000201800 */
/*0170*/ FSETP.GEU.AND P0, PT, R6, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fe20003f0e000 */
/*0180*/ DMUL R4, R2, -0.5 ; /* 0xbfe0000002047828 */
/* 0x002e4c0000000000 */
/*0190*/ DMUL R2, R2, R4 ; /* 0x0000000402027228 */
/* 0x002e4c0000000000 */
/*01a0*/ DFMA R4, R2, R8, 6.75539944105574400000e+15 ; /* 0x433800000204742b */
/* 0x002e480000000008 */
/*01b0*/ FSETP.GEU.AND P1, PT, |R3|, 4.1917929649353027344, PT ; /* 0x4086232b0300780b */
/* 0x000fe40003f2e200 */
/*01c0*/ DADD R8, R4, -6.75539944105574400000e+15 ; /* 0xc338000004087429 */
/* 0x002e4c0000000000 */
/*01d0*/ DFMA R10, R8, c[0x2][0x0], R2 ; /* 0x00800000080a7a2b */
/* 0x002e4c0000000002 */
/*01e0*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x002e4c000000000a */
/*01f0*/ DFMA R10, R8, R12, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x002e4c000000000c */
/*0200*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x002e4c000000000a */
/*0210*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x002e4c000000000a */
/*0220*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x002e4c000000000a */
/*0230*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x002e4c000000000a */
/*0240*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x002e4c000000000a */
/*0250*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x002e4c000000000a */
/*0260*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x002e4c000000000a */
/*0270*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x002e4c000000000a */
/*0280*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x002e4c000000000a */
/*0290*/ DFMA R12, R8, R10, 1 ; /* 0x3ff00000080c742b */
/* 0x0022a4000000000a */
/*02a0*/ FMUL R9, R6, 8388608 ; /* 0x4b00000006097820 */
/* 0x002fe40000400000 */
/*02b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1ff62705 ; /* 0x1ff62705ff087424 */
/* 0x000fc600078e00ff */
/*02c0*/ FSEL R10, R9, R6, !P0 ; /* 0x00000006090a7208 */
/* 0x000fe20004000000 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40040d93 ; /* 0x40040d93ff097424 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD R15, R4, 0x100000, R13 ; /* 0x00100000040f7824 */
/* 0x004fe400078e020d */
/*02f0*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0300*/ @!P1 BRA 0x3d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GEU.AND P2, PT, |R3|, 4.2275390625, PT ; /* 0x408748000300780b */
/* 0x001fe20003f4e200 */
/*0320*/ DADD R14, R2, +INF ; /* 0x7ff00000020e7429 */
/* 0x000fc80000000000 */
/*0330*/ DSETP.GEU.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e0c0003f2e000 */
/*0340*/ FSEL R14, R14, RZ, P1 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000800000 */
/*0350*/ @!P2 LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x000000040405a211 */
/* 0x000fe400078f08ff */
/*0360*/ FSEL R15, R15, RZ, P1 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000800000 */
/*0370*/ @!P2 SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff05a819 */
/* 0x000fc80000011405 */
/*0380*/ @!P2 IADD3 R2, R4, -R5, RZ ; /* 0x800000050402a210 */
/* 0x000fe20007ffe0ff */
/*0390*/ @!P2 IMAD R13, R5, 0x100000, R13 ; /* 0x00100000050da824 */
/* 0x000fc600078e020d */
/*03a0*/ @!P2 LEA R3, R2, 0x3ff00000, 0x14 ; /* 0x3ff000000203a811 */
/* 0x000fe200078ea0ff */
/*03b0*/ @!P2 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff02a224 */
/* 0x000fcc00078e00ff */
/*03c0*/ @!P2 DMUL R14, R12, R2 ; /* 0x000000020c0ea228 */
/* 0x00004c0000000000 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*03f0*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x002e220000301000 */
/*0400*/ IADD3 R13, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a0d7810 */
/* 0x040fe20007ffe0ff */
/*0410*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff047424 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.GE.U32.AND P1, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe20003f26070 */
/*0430*/ BSSY B0, 0x700 ; /* 0x000002c000007945 */
/* 0x000fe20003800000 */
/*0440*/ DFMA R2, R6, -R8, 1 ; /* 0x3ff000000602742b */
/* 0x000e620000000808 */
/*0450*/ LOP3.LUT R13, R13, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000d0d7812 */
/* 0x000fca00078ec0ff */
/*0460*/ DFMA R2, R2, R2, R2 ; /* 0x000000020202722b */
/* 0x002e620000000002 */
/*0470*/ IMAD.IADD R11, R10, 0x1, -R13 ; /* 0x000000010a0b7824 */
/* 0x000fe400078e0a0d */
/*0480*/ I2F R13, R13 ; /* 0x0000000d000d7306 */
/* 0x000ea40000201400 */
/*0490*/ FADD R11, R11, -1 ; /* 0xbf8000000b0b7421 */
/* 0x000fe20000000000 */
/*04a0*/ DFMA R6, R6, R2, R6 ; /* 0x000000020606722b */
/* 0x0020460000000006 */
/*04b0*/ FFMA R4, R11.reuse, -R4, 0.14084610342979431152 ; /* 0x3e1039f60b047423 */
/* 0x040fe40000000804 */
/*04c0*/ F2F.F64.F32 R2, R14 ; /* 0x0000000e00027310 */
/* 0x001e220000201800 */
/*04d0*/ DFMA R8, R6, -R8, 1 ; /* 0x3ff000000608742b */
/* 0x002e620000000808 */
/*04e0*/ FFMA R4, R11, R4, -0.12148627638816833496 ; /* 0xbdf8cdcc0b047423 */
/* 0x000fc80000000004 */
/*04f0*/ FFMA R4, R11, R4, 0.13980610668659210205 ; /* 0x3e0f29550b047423 */
/* 0x000fe20000000004 */
/*0500*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x0022060000000006 */
/*0510*/ FFMA R6, R11, R4, -0.16684235632419586182 ; /* 0xbe2ad8b90b067423 */
/* 0x002fc80000000004 */
/*0520*/ FFMA R6, R11, R6, 0.20012299716472625732 ; /* 0x3e4ced0b0b067423 */
/* 0x000fe20000000006 */
/*0530*/ DMUL R4, R2, R8 ; /* 0x0000000802047228 */
/* 0x001e220000000000 */
/*0540*/ FSETP.GEU.AND P3, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fe40003f6e200 */
/*0550*/ FFMA R12, R11, R6, -0.24999669194221496582 ; /* 0xbe7fff220b0c7423 */
/* 0x000fc60000000006 */
/*0560*/ DFMA R6, R4, c[0x2][0x58], R2 ; /* 0x0080160004067a2b */
/* 0x001e220000000002 */
/*0570*/ FFMA R12, R11, R12, 0.33333182334899902344 ; /* 0x3eaaaa780b0c7423 */
/* 0x000fc8000000000c */
/*0580*/ FFMA R12, R11.reuse, R12, -0.5 ; /* 0xbf0000000b0c7423 */
/* 0x040fe2000000000c */
/*0590*/ DFMA R4, R8, R6, R4 ; /* 0x000000060804722b */
/* 0x0010640000000004 */
/*05a0*/ FSEL R6, RZ, -23, P0 ; /* 0xc1b80000ff067808 */
/* 0x001fe20000000000 */
/*05b0*/ FMUL R12, R11, R12 ; /* 0x0000000c0b0c7220 */
/* 0x000fe20000400000 */
/*05c0*/ FSETP.NEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fe20003f0d000 */
/*05d0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, 0x7f800000 ; /* 0x7f800000ff071424 */
/* 0x000fe400078e00ff */
/*05e0*/ FFMA R6, R13, 1.1920928955078125e-07, R6 ; /* 0x340000000d067823 */
/* 0x004fe40000000006 */
/*05f0*/ FFMA R11, R11, R12, R11 ; /* 0x0000000c0b0b7223 */
/* 0x000fc4000000000b */
/*0600*/ FFMA R8, RZ, 2.0633285045623779297, R5 ; /* 0x40040d93ff087823 */
/* 0x002fe40000000005 */
/*0610*/ FFMA R6, R6, 0.69314718246459960938, R11 ; /* 0x3f31721806067823 */
/* 0x000fe2000000000b */
/*0620*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe20000011400 */
/*0630*/ @P1 FFMA R6, R10, R7, +INF ; /* 0x7f8000000a061423 */
/* 0x000fe20000000007 */
/*0640*/ FSETP.GT.AND P2, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fc80003f44200 */
/*0650*/ FSEL R10, R6, -INF , P0 ; /* 0xff800000060a7808 */
/* 0x000fd20000000000 */
/*0660*/ @P2 BRA P3, 0x6f0 ; /* 0x0000008000002947 */
/* 0x000fea0001800000 */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0680*/ MOV R6, 0x1ff62705 ; /* 0x1ff6270500067802 */
/* 0x000fe20000000f00 */
/*0690*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0003 */
/*06a0*/ MOV R12, 0x6d0 ; /* 0x000006d0000c7802 */
/* 0x000fe20000000f00 */
/*06b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40040d93 ; /* 0x40040d93ff077424 */
/* 0x000fe400078e00ff */
/*06c0*/ CALL.REL.NOINC 0x8f0 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*06e0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ MUFU.RCP64H R7, 0.34134459495544433594 ; /* 0x3fd5d89700077908 */
/* 0x000e220000001800 */
/*0710*/ IMAD.MOV.U32 R12, RZ, RZ, -0x5dbe5c0b ; /* 0xa241a3f5ff0c7424 */
/* 0x000fe200078e00ff */
/*0720*/ BSSY B0, 0x8a0 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*0730*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3fd5d897 ; /* 0x3fd5d897ff0d7424 */
/* 0x000fe400078e00ff */
/*0740*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fcc00078e00ff */
/*0750*/ DFMA R2, R6, -R12, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c000000080c */
/*0760*/ DFMA R8, R2, R2, R2 ; /* 0x000000020208722b */
/* 0x0010880000000002 */
/*0770*/ F2F.F64.F32 R2, R10 ; /* 0x0000000a00027310 */
/* 0x001e240000201800 */
/*0780*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x004e8c0000000006 */
/*0790*/ DFMA R6, R8, -R12, 1 ; /* 0x3ff000000806742b */
/* 0x004e8c000000080c */
/*07a0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x004fc80000000008 */
/*07b0*/ DMUL R12, R2, R4 ; /* 0x00000004020c7228 */
/* 0x001e0c0000000000 */
/*07c0*/ DMUL R2, R12, R6 ; /* 0x000000060c027228 */
/* 0x001e080000000000 */
/*07d0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*07e0*/ DFMA R4, R2, c[0x2][0x60], R12 ; /* 0x0080180002047a2b */
/* 0x001e0c000000000c */
/*07f0*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x001e140000000002 */
/*0800*/ FFMA R4, RZ, 1.670672297477722168, R3 ; /* 0x3fd5d897ff047823 */
/* 0x001fca0000000003 */
/*0810*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fda0003f04200 */
/*0820*/ @P0 BRA P1, 0x890 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0830*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000c */
/*0840*/ MOV R6, 0xa241a3f5 ; /* 0xa241a3f500067802 */
/* 0x000fe20000000f00 */
/*0850*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0860*/ MOV R12, 0x890 ; /* 0x00000890000c7802 */
/* 0x000fe20000000f00 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3fd5d897 ; /* 0x3fd5d897ff077424 */
/* 0x000fe400078e00ff */
/*0880*/ CALL.REL.NOINC 0x8f0 ; /* 0x0000006000007944 */
/* 0x002fea0003c00000 */
/*0890*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08a0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x000e220000301000 */
/*08b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*08c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R11, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f140b */
/*08d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0900*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0910*/ LOP3.LUT R4, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07047812 */
/* 0x000fe200078ec0ff */
/*0920*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0930*/ FSETP.GEU.AND P2, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f4e200 */
/*0940*/ BSSY B1, 0xe90 ; /* 0x0000054000017945 */
/* 0x000fe20003800000 */
/*0950*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0970*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fe400078ec0ff */
/*0980*/ LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007147812 */
/* 0x000fc600078ec0ff */
/*0990*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x000e220000000000 */
/*09a0*/ ISETP.GE.U32.AND P1, PT, R13, R20, PT ; /* 0x000000140d00720c */
/* 0x000fc60003f26070 */
/*09b0*/ @!P2 LOP3.LUT R2, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000702a812 */
/* 0x000fe200078ec0ff */
/*09c0*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*09d0*/ MUFU.RCP64H R19, R5 ; /* 0x0000000500137308 */
/* 0x001e220000001800 */
/*09e0*/ SEL R3, R14.reuse, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x040fe40004800000 */
/*09f0*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0a00*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0008 */
/*0a10*/ LOP3.LUT R3, R3, 0x800fffff, R9, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef809 */
/*0a20*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0a30*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R9, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fc800078ef809 */
/*0a40*/ @!P2 LOP3.LUT R17, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f11a812 */
/* 0x000fe200078efcff */
/*0a50*/ DFMA R22, R18, -R4, 1 ; /* 0x3ff000001216742b */
/* 0x001e220000000804 */
/*0a60*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0a70*/ @!P2 DFMA R2, R2, 2, -R16 ; /* 0x400000000202a82b */
/* 0x000fc80000000810 */
/*0a80*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*0a90*/ DFMA R18, R18, R22, R18 ; /* 0x000000161212722b */
/* 0x0010620000000012 */
/*0aa0*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fe200078ec0ff */
/*0ab0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x001fe200078e0014 */
/*0ac0*/ @!P0 LOP3.LUT R22, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005168812 */
/* 0x000fe400078ec0ff */
/*0ad0*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x000fe20007ffe0ff */
/*0ae0*/ DFMA R16, R18, -R4, 1 ; /* 0x3ff000001210742b */
/* 0x002e220000000804 */
/*0af0*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe40007ffe0ff */
/*0b00*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0b10*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e220000000012 */
/*0b20*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fca0000704470 */
/*0b30*/ DMUL R18, R16, R2 ; /* 0x0000000210127228 */
/* 0x001e0c0000000000 */
/*0b40*/ DFMA R20, R18, -R4, R2 ; /* 0x800000041214722b */
/* 0x001e0c0000000002 */
/*0b50*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010620000000012 */
/*0b60*/ @P0 BRA 0xd30 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R18, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007127812 */
/* 0x001fc800078ec0ff */
/*0b80*/ IADD3 R8, R13.reuse, -R18.reuse, RZ ; /* 0x800000120d087210 */
/* 0x0c0fe40007ffe0ff */
/*0b90*/ ISETP.GE.U32.AND P0, PT, R13, R18, PT ; /* 0x000000120d00720c */
/* 0x000fe40003f06070 */
/*0ba0*/ IMNMX R8, R8, -0x46a00000, !PT ; /* 0xb960000008087817 */
/* 0x000fe40007800200 */
/*0bb0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0bc0*/ IMNMX R8, R8, 0x46a00000, PT ; /* 0x46a0000008087817 */
/* 0x000fca0003800200 */
/*0bd0*/ IMAD.IADD R13, R8, 0x1, -R13 ; /* 0x00000001080d7824 */
/* 0x000fe400078e0a0d */
/*0be0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*0bf0*/ IADD3 R9, R13, 0x7fe00000, RZ ; /* 0x7fe000000d097810 */
/* 0x000fcc0007ffe0ff */
/*0c00*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x002e140000000000 */
/*0c10*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0c20*/ @P0 BRA 0xe80 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0c30*/ DFMA R2, R16, -R4, R2 ; /* 0x800000041002722b */
/* 0x000e220000000002 */
/*0c40*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd200078e00ff */
/*0c50*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0c60*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0c70*/ LOP3.LUT R9, R7, R9, RZ, 0xfc, !PT ; /* 0x0000000907097212 */
/* 0x000fce00078efcff */
/*0c80*/ @!P0 BRA 0xe80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0c90*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0ca0*/ DMUL.RP R8, R16, R8 ; /* 0x0000000810087228 */
/* 0x000e220000008000 */
/*0cb0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0cc0*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0cd0*/ LOP3.LUT R7, R9, R7, RZ, 0x3c, !PT ; /* 0x0000000709077212 */
/* 0x001fc600078e3cff */
/*0ce0*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0cf0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0d00*/ FSEL R18, R8, R18, !P0 ; /* 0x0000001208127208 */
/* 0x000fe40004000000 */
/*0d10*/ FSEL R19, R7, R19, !P0 ; /* 0x0000001307137208 */
/* 0x000fe20004000000 */
/*0d20*/ BRA 0xe80 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0d30*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0d40*/ @P0 BRA 0xe60 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0d50*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0d60*/ @P0 BRA 0xe30 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0d70*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0d80*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x001fe400078e00ff */
/*0d90*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0da0*/ @!P0 BRA 0xe80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0dc0*/ LOP3.LUT R19, R9, 0x80000000, R7, 0x48, !PT ; /* 0x8000000009137812 */
/* 0x000fe400078e4807 */
/*0dd0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0de0*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0df0*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe200078e00ff */
/*0e00*/ @P0 MOV R18, RZ ; /* 0x000000ff00120202 */
/* 0x000fc60000000f00 */
/*0e10*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0e20*/ BRA 0xe80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT R19, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007137812 */
/* 0x001fe200078efcff */
/*0e40*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0e50*/ BRA 0xe80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0e60*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x001fe200078efcff */
/*0e70*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*0e80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0e90*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0ea0*/ IMAD.MOV.U32 R2, RZ, RZ, R18 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0012 */
/*0eb0*/ IMAD.MOV.U32 R3, RZ, RZ, R19 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0013 */
/*0ec0*/ RET.REL.NODEC R12 0x0 ; /* 0xfffff1300c007950 */
/* 0x000fec0003c3ffff */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13log_truncNormPfS_i
.globl _Z13log_truncNormPfS_i
.p2align 8
.type _Z13log_truncNormPfS_i,@function
_Z13log_truncNormPfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s4, s4, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s4, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s3, s[0:1], 0x10
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[3:4], null, v2, s4, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v12, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[2:3], -0.5
v_mul_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
v_rndne_f64_e32 v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_mov_b32 s3, 0x40040d93
s_mov_b32 s2, 0x1ff62705
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
s_mov_b32 s1, 0x3fd5d897
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v10
v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_cndmask_b32_e64 v3, 0, v5, s0
v_cmp_gt_f32_e64 s0, 0x800000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, s[2:3], s[2:3], v[2:3]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[2:3], v[2:3]
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_mul_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
v_cndmask_b32_e64 v10, 1.0, 0x4f800000, s0
v_mul_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_log_f32_e32 v10, v10
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x3f317217, v10
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v10|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v10, 0x3f317217, -v6
v_fmamk_f32 v7, v10, 0x3377d1cf, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v7
v_cndmask_b32_e64 v7, 0, 0x41b17218, s0
s_mov_b32 s0, 0xa241a3f5
v_cndmask_b32_e32 v6, v10, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_cvt_f64_f32_e32 v[6:7], v6
v_div_fixup_f64 v[2:3], v[4:5], s[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[6:7]
v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13log_truncNormPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13log_truncNormPfS_i, .Lfunc_end0-_Z13log_truncNormPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13log_truncNormPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13log_truncNormPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000892f3_00000000-6_log_truncNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5dnormfff
.type _Z5dnormfff, @function
_Z5dnormfff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z5dnormfff, .-_Z5dnormfff
.globl _Z36__device_stub__Z13log_truncNormPfS_iPfS_i
.type _Z36__device_stub__Z13log_truncNormPfS_iPfS_i, @function
_Z36__device_stub__Z13log_truncNormPfS_iPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13log_truncNormPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z13log_truncNormPfS_iPfS_i, .-_Z36__device_stub__Z13log_truncNormPfS_iPfS_i
.globl _Z13log_truncNormPfS_i
.type _Z13log_truncNormPfS_i, @function
_Z13log_truncNormPfS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13log_truncNormPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13log_truncNormPfS_i, .-_Z13log_truncNormPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13log_truncNormPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13log_truncNormPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "log_truncNorm.hip"
.globl _Z28__device_stub__log_truncNormPfS_i # -- Begin function _Z28__device_stub__log_truncNormPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__log_truncNormPfS_i,@function
_Z28__device_stub__log_truncNormPfS_i: # @_Z28__device_stub__log_truncNormPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13log_truncNormPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__log_truncNormPfS_i, .Lfunc_end0-_Z28__device_stub__log_truncNormPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13log_truncNormPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13log_truncNormPfS_i,@object # @_Z13log_truncNormPfS_i
.section .rodata,"a",@progbits
.globl _Z13log_truncNormPfS_i
.p2align 3, 0x0
_Z13log_truncNormPfS_i:
.quad _Z28__device_stub__log_truncNormPfS_i
.size _Z13log_truncNormPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13log_truncNormPfS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__log_truncNormPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13log_truncNormPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* hello.cu:
*
*
*/
#include <stdio.h>
__global__ void mykernel()
{
}
int main()
{
mykernel<<<1,1>>>();
printf("Hello, CUDA World!\n");
return 0;
} | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* hello.cu:
*
*
*/
#include <stdio.h>
__global__ void mykernel()
{
}
int main()
{
mykernel<<<1,1>>>();
printf("Hello, CUDA World!\n");
return 0;
} | .file "tmpxft_00090e95_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, CUDA World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* hello.cu:
*
*
*/
#include <stdio.h>
__global__ void mykernel()
{
}
int main()
{
mykernel<<<1,1>>>();
printf("Hello, CUDA World!\n");
return 0;
} | /*
* hello.cu:
*
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel()
{
}
int main()
{
mykernel<<<1,1>>>();
printf("Hello, CUDA World!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* hello.cu:
*
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel()
{
}
int main()
{
mykernel<<<1,1>>>();
printf("Hello, CUDA World!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* hello.cu:
*
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel()
{
}
int main()
{
mykernel<<<1,1>>>();
printf("Hello, CUDA World!\n");
return 0;
} | .text
.file "hello.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello, CUDA World!"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090e95_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello, CUDA World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello, CUDA World!"
.size .Lstr, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Sum two square matrix (A = B + C)
* Exercise 3.1 of programming massively parallel processors book
* Solution provided with matrix view as array
* @author Niccolò Bellaccini
*/
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h> //rand
#include <time.h> //rand
#include <math.h> //ceil
#include <iostream> //std::cerr
#define BLOCK_WIDTH 64
void initData(float* M, int nRows){ //Remeber: matrix square
for (int i=0; i<nRows; i++){
for(int j=0; j<nRows; j++){
M[nRows * i + j] = (float) (rand() & 0xFF) / 10.0f;
}
}
}
void displayData(float *M, int nRows){
for (int i=0; i<nRows; i++){
printf("\n");
for(int j=0; j<nRows; j++){
printf("%.1f\t", M[nRows * i + j]);
}
}
}
/**
* function-like macro
* __LINE__ = contains the line number of the currently compiled line of code
* __FILE__ = string that contains the name of the source file being compiled
* # operator = turns the argument it precedes into a quoted string
* Reference: [C the complete reference]
* check with > nvcc -E
*/
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__, __LINE__, #value, value)
static void CheckCudaErrorAux (const char *file, unsigned line,
const char *statement, cudaError_t err){
if(err == cudaSuccess)
return;
std::cerr << statement << " returned " << cudaGetErrorString(err) <<
"(" << err << ") at " << file << ":" << line << std::endl;
exit(1);
}
//Kernel function (point b of exercise)
__global__ void matrixAddKernel(float *A, float *B, float *C, int nRows){
int size = nRows * nRows; //Remember: square matrices
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<size)
A[i] = B[i] + C[i];
}
//Kernel function (point c of exercise)
__global__ void matrixPerRowsAddKernel(float *A, float *B, float *C, int nRows){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nRows){
for (int j=0; j<nRows; j++){
A[i * nRows + j] = B[i * nRows + j] + C[i * nRows + j];
}
}
}
//Kernel function (point d of exercise)
__global__ void matrixPerColumnsAddKernel(float *A, float *B, float *C, int nColumns){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nColumns){
for (int j=0; j<nColumns; j++){
A[i + j * nColumns] = B[i + j * nColumns] + C[i + j * nColumns];
}
}
}
/**
* Stub function used to compute matrices sum.
* (function used to launch the kernel and to allocate device mem, ...)
*/
void matrixAdd(float* A, float *B, float *C, int nRows){
size_t size = nRows * nRows * sizeof(float);
float * d_A;
float * d_B;
float * d_C;
//Allocate device memory for matrices
CUDA_CHECK_RETURN(cudaMalloc((void **) &d_B, size));
CUDA_CHECK_RETURN(cudaMalloc((void **) &d_C, size));
CUDA_CHECK_RETURN(cudaMalloc((void **) &d_A, size));
//Copy B and C to device memory
CUDA_CHECK_RETURN(cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(d_C, C, size, cudaMemcpyHostToDevice));
//Kernel launch code
//assume block of 64 threads
matrixAddKernel <<< ceil((double)(nRows*nRows)/BLOCK_WIDTH), BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Two other possible kernel functions
//matrixPerRowsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//matrixPerColumnsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Copy A from the device memory
CUDA_CHECK_RETURN(cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost));
//Free device matrices
cudaFree(d_C);
cudaFree(d_B);
cudaFree(d_A);
}
int main(int argc, char** argv){
//Initialize random seed
//@see http://www.cplusplus.com/reference/cstdlib/srand/
//@see https://stackoverflow.com/questions/20158841/my-random-number-generator-function-generates-the-same-number
srand(time(NULL));
int numRows;
printf("\nInsert the number of rows (equivalently columns): ");
scanf("%d", &numRows);
int numColumns = numRows; //Square matrix
int nElem = numRows * numColumns;
float * B = (float *) malloc(nElem * sizeof(float));
float * C = (float *) malloc(nElem * sizeof(float));
float * A = (float *) malloc(nElem * sizeof(float));
//Initialize B and C matrices
initData(B, numRows);
initData(C, numRows);
//Display B and C matrices
printf("\n\tMatrice B\n");
displayData(B, numRows);
printf("\n\n\tMatrice C\n");
displayData(C, numRows);
//matrices sum
matrixAdd(A, B, C, numRows);
//Display A matrix
printf("\n\n\tMatrice A\n");
displayData(A, numRows);
} | .file "tmpxft_00142723_00000000-6_MatrixSumTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB3671:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initDataPfi
.type _Z8initDataPfi, @function
_Z8initDataPfi:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L12:
leaq 0(%rbp,%r13), %rbx
.L13:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L12
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3669:
.size _Z8initDataPfi, .-_Z8initDataPfi
.section .rodata.str1.1
.LC5:
.string "\n"
.LC6:
.string "%.1f\t"
.text
.globl _Z11displayDataPfi
.type _Z11displayDataPfi, @function
_Z11displayDataPfi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L19
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC6(%rip), %r12
.L22:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(%rbp,%r14), %rbx
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L22
.L19:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11displayDataPfi, .-_Z11displayDataPfi
.globl _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.globl _Z15matrixAddKernelPfS_S_i
.type _Z15matrixAddKernelPfS_S_i, @function
_Z15matrixAddKernelPfS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z15matrixAddKernelPfS_S_i, .-_Z15matrixAddKernelPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cudaMalloc((void **) &d_B, size)"
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kinik93/Matrix-sum-CUDA/master/MatrixSumTest.cu"
.align 8
.LC9:
.string "cudaMalloc((void **) &d_C, size)"
.align 8
.LC10:
.string "cudaMalloc((void **) &d_A, size)"
.align 8
.LC11:
.string "cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice)"
.align 8
.LC12:
.string "cudaMemcpy(d_C, C, size, cudaMemcpyHostToDevice)"
.align 8
.LC17:
.string "cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost)"
.text
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %ecx, %r15d
imull %ecx, %r15d
movslq %r15d, %rbx
salq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC7(%rip), %rdx
movl $97, %esi
leaq .LC8(%rip), %rbp
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $98, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC10(%rip), %rdx
movl $99, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $102, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC12(%rip), %rdx
movl $103, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC13(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC18(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC14(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L35
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC16(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L35:
cvttsd2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $115, %esi
leaq .LC8(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.section .rodata.str1.8
.align 8
.LC19:
.string "\nInsert the number of rows (equivalently columns): "
.section .rodata.str1.1
.LC20:
.string "%d"
.LC21:
.string "\n\tMatrice B\n"
.LC22:
.string "\n\n\tMatrice C\n"
.LC23:
.string "\n\n\tMatrice A\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC20(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %r13d
movl %r13d, %ebx
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %esi
movq %rbp, %rdi
call _Z8initDataPfi
movl 4(%rsp), %esi
movq %r12, %rdi
call _Z8initDataPfi
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
movq %rbp, %rdi
call _Z11displayDataPfi
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
movq %r12, %rdi
call _Z11displayDataPfi
movl 4(%rsp), %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z9matrixAddPfS_S_i
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _Z11displayDataPfi
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.globl _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i
.type _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matrixPerRowsAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i
.globl _Z22matrixPerRowsAddKernelPfS_S_i
.type _Z22matrixPerRowsAddKernelPfS_S_i, @function
_Z22matrixPerRowsAddKernelPfS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z22matrixPerRowsAddKernelPfS_S_i, .-_Z22matrixPerRowsAddKernelPfS_S_i
.globl _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i
.type _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25matrixPerColumnsAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i, .-_Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i
.globl _Z25matrixPerColumnsAddKernelPfS_S_i
.type _Z25matrixPerColumnsAddKernelPfS_S_i, @function
_Z25matrixPerColumnsAddKernelPfS_S_i:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z25matrixPerColumnsAddKernelPfS_S_i, .-_Z25matrixPerColumnsAddKernelPfS_S_i
.section .rodata.str1.8
.align 8
.LC24:
.string "_Z25matrixPerColumnsAddKernelPfS_S_i"
.align 8
.LC25:
.string "_Z22matrixPerRowsAddKernelPfS_S_i"
.section .rodata.str1.1
.LC26:
.string "_Z15matrixAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z25matrixPerColumnsAddKernelPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrixPerRowsAddKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1092616192
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC13:
.long 0
.long 1066401792
.align 8
.LC14:
.long 0
.long 1127219200
.align 8
.LC16:
.long 0
.long 1072693248
.align 8
.LC18:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Sum two square matrix (A = B + C)
* Exercise 3.1 of programming massively parallel processors book
* Solution provided with matrix view as array
* @author Niccolò Bellaccini
*/
#include <cuda.h>
#include <stdio.h>
#include <stdlib.h> //rand
#include <time.h> //rand
#include <math.h> //ceil
#include <iostream> //std::cerr
#define BLOCK_WIDTH 64
void initData(float* M, int nRows){ //Remeber: matrix square
for (int i=0; i<nRows; i++){
for(int j=0; j<nRows; j++){
M[nRows * i + j] = (float) (rand() & 0xFF) / 10.0f;
}
}
}
void displayData(float *M, int nRows){
for (int i=0; i<nRows; i++){
printf("\n");
for(int j=0; j<nRows; j++){
printf("%.1f\t", M[nRows * i + j]);
}
}
}
/**
* function-like macro
* __LINE__ = contains the line number of the currently compiled line of code
* __FILE__ = string that contains the name of the source file being compiled
* # operator = turns the argument it precedes into a quoted string
* Reference: [C the complete reference]
* check with > nvcc -E
*/
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__, __LINE__, #value, value)
static void CheckCudaErrorAux (const char *file, unsigned line,
const char *statement, cudaError_t err){
if(err == cudaSuccess)
return;
std::cerr << statement << " returned " << cudaGetErrorString(err) <<
"(" << err << ") at " << file << ":" << line << std::endl;
exit(1);
}
//Kernel function (point b of exercise)
__global__ void matrixAddKernel(float *A, float *B, float *C, int nRows){
int size = nRows * nRows; //Remember: square matrices
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<size)
A[i] = B[i] + C[i];
}
//Kernel function (point c of exercise)
__global__ void matrixPerRowsAddKernel(float *A, float *B, float *C, int nRows){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nRows){
for (int j=0; j<nRows; j++){
A[i * nRows + j] = B[i * nRows + j] + C[i * nRows + j];
}
}
}
//Kernel function (point d of exercise)
__global__ void matrixPerColumnsAddKernel(float *A, float *B, float *C, int nColumns){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nColumns){
for (int j=0; j<nColumns; j++){
A[i + j * nColumns] = B[i + j * nColumns] + C[i + j * nColumns];
}
}
}
/**
* Stub function used to compute matrices sum.
* (function used to launch the kernel and to allocate device mem, ...)
*/
void matrixAdd(float* A, float *B, float *C, int nRows){
size_t size = nRows * nRows * sizeof(float);
float * d_A;
float * d_B;
float * d_C;
//Allocate device memory for matrices
CUDA_CHECK_RETURN(cudaMalloc((void **) &d_B, size));
CUDA_CHECK_RETURN(cudaMalloc((void **) &d_C, size));
CUDA_CHECK_RETURN(cudaMalloc((void **) &d_A, size));
//Copy B and C to device memory
CUDA_CHECK_RETURN(cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(d_C, C, size, cudaMemcpyHostToDevice));
//Kernel launch code
//assume block of 64 threads
matrixAddKernel <<< ceil((double)(nRows*nRows)/BLOCK_WIDTH), BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Two other possible kernel functions
//matrixPerRowsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//matrixPerColumnsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Copy A from the device memory
CUDA_CHECK_RETURN(cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost));
//Free device matrices
cudaFree(d_C);
cudaFree(d_B);
cudaFree(d_A);
}
int main(int argc, char** argv){
//Initialize random seed
//@see http://www.cplusplus.com/reference/cstdlib/srand/
//@see https://stackoverflow.com/questions/20158841/my-random-number-generator-function-generates-the-same-number
srand(time(NULL));
int numRows;
printf("\nInsert the number of rows (equivalently columns): ");
scanf("%d", &numRows);
int numColumns = numRows; //Square matrix
int nElem = numRows * numColumns;
float * B = (float *) malloc(nElem * sizeof(float));
float * C = (float *) malloc(nElem * sizeof(float));
float * A = (float *) malloc(nElem * sizeof(float));
//Initialize B and C matrices
initData(B, numRows);
initData(C, numRows);
//Display B and C matrices
printf("\n\tMatrice B\n");
displayData(B, numRows);
printf("\n\n\tMatrice C\n");
displayData(C, numRows);
//matrices sum
matrixAdd(A, B, C, numRows);
//Display A matrix
printf("\n\n\tMatrice A\n");
displayData(A, numRows);
} | /**
* Sum two square matrix (A = B + C)
* Exercise 3.1 of programming massively parallel processors book
* Solution provided with matrix view as array
* @author Niccolò Bellaccini
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h> //rand
#include <time.h> //rand
#include <math.h> //ceil
#include <iostream> //std::cerr
#define BLOCK_WIDTH 64
void initData(float* M, int nRows){ //Remeber: matrix square
for (int i=0; i<nRows; i++){
for(int j=0; j<nRows; j++){
M[nRows * i + j] = (float) (rand() & 0xFF) / 10.0f;
}
}
}
void displayData(float *M, int nRows){
for (int i=0; i<nRows; i++){
printf("\n");
for(int j=0; j<nRows; j++){
printf("%.1f\t", M[nRows * i + j]);
}
}
}
/**
* function-like macro
* __LINE__ = contains the line number of the currently compiled line of code
* __FILE__ = string that contains the name of the source file being compiled
* # operator = turns the argument it precedes into a quoted string
* Reference: [C the complete reference]
* check with > nvcc -E
*/
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__, __LINE__, #value, value)
static void CheckCudaErrorAux (const char *file, unsigned line,
const char *statement, hipError_t err){
if(err == hipSuccess)
return;
std::cerr << statement << " returned " << hipGetErrorString(err) <<
"(" << err << ") at " << file << ":" << line << std::endl;
exit(1);
}
//Kernel function (point b of exercise)
__global__ void matrixAddKernel(float *A, float *B, float *C, int nRows){
int size = nRows * nRows; //Remember: square matrices
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<size)
A[i] = B[i] + C[i];
}
//Kernel function (point c of exercise)
__global__ void matrixPerRowsAddKernel(float *A, float *B, float *C, int nRows){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nRows){
for (int j=0; j<nRows; j++){
A[i * nRows + j] = B[i * nRows + j] + C[i * nRows + j];
}
}
}
//Kernel function (point d of exercise)
__global__ void matrixPerColumnsAddKernel(float *A, float *B, float *C, int nColumns){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nColumns){
for (int j=0; j<nColumns; j++){
A[i + j * nColumns] = B[i + j * nColumns] + C[i + j * nColumns];
}
}
}
/**
* Stub function used to compute matrices sum.
* (function used to launch the kernel and to allocate device mem, ...)
*/
void matrixAdd(float* A, float *B, float *C, int nRows){
size_t size = nRows * nRows * sizeof(float);
float * d_A;
float * d_B;
float * d_C;
//Allocate device memory for matrices
CUDA_CHECK_RETURN(hipMalloc((void **) &d_B, size));
CUDA_CHECK_RETURN(hipMalloc((void **) &d_C, size));
CUDA_CHECK_RETURN(hipMalloc((void **) &d_A, size));
//Copy B and C to device memory
CUDA_CHECK_RETURN(hipMemcpy(d_B, B, size, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(d_C, C, size, hipMemcpyHostToDevice));
//Kernel launch code
//assume block of 64 threads
matrixAddKernel <<< ceil((double)(nRows*nRows)/BLOCK_WIDTH), BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Two other possible kernel functions
//matrixPerRowsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//matrixPerColumnsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Copy A from the device memory
CUDA_CHECK_RETURN(hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost));
//Free device matrices
hipFree(d_C);
hipFree(d_B);
hipFree(d_A);
}
int main(int argc, char** argv){
//Initialize random seed
//@see http://www.cplusplus.com/reference/cstdlib/srand/
//@see https://stackoverflow.com/questions/20158841/my-random-number-generator-function-generates-the-same-number
srand(time(NULL));
int numRows;
printf("\nInsert the number of rows (equivalently columns): ");
scanf("%d", &numRows);
int numColumns = numRows; //Square matrix
int nElem = numRows * numColumns;
float * B = (float *) malloc(nElem * sizeof(float));
float * C = (float *) malloc(nElem * sizeof(float));
float * A = (float *) malloc(nElem * sizeof(float));
//Initialize B and C matrices
initData(B, numRows);
initData(C, numRows);
//Display B and C matrices
printf("\n\tMatrice B\n");
displayData(B, numRows);
printf("\n\n\tMatrice C\n");
displayData(C, numRows);
//matrices sum
matrixAdd(A, B, C, numRows);
//Display A matrix
printf("\n\n\tMatrice A\n");
displayData(A, numRows);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Sum two square matrix (A = B + C)
* Exercise 3.1 of programming massively parallel processors book
* Solution provided with matrix view as array
* @author Niccolò Bellaccini
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h> //rand
#include <time.h> //rand
#include <math.h> //ceil
#include <iostream> //std::cerr
#define BLOCK_WIDTH 64
void initData(float* M, int nRows){ //Remeber: matrix square
for (int i=0; i<nRows; i++){
for(int j=0; j<nRows; j++){
M[nRows * i + j] = (float) (rand() & 0xFF) / 10.0f;
}
}
}
void displayData(float *M, int nRows){
for (int i=0; i<nRows; i++){
printf("\n");
for(int j=0; j<nRows; j++){
printf("%.1f\t", M[nRows * i + j]);
}
}
}
/**
* function-like macro
* __LINE__ = contains the line number of the currently compiled line of code
* __FILE__ = string that contains the name of the source file being compiled
* # operator = turns the argument it precedes into a quoted string
* Reference: [C the complete reference]
* check with > nvcc -E
*/
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__, __LINE__, #value, value)
static void CheckCudaErrorAux (const char *file, unsigned line,
const char *statement, hipError_t err){
if(err == hipSuccess)
return;
std::cerr << statement << " returned " << hipGetErrorString(err) <<
"(" << err << ") at " << file << ":" << line << std::endl;
exit(1);
}
//Kernel function (point b of exercise)
__global__ void matrixAddKernel(float *A, float *B, float *C, int nRows){
int size = nRows * nRows; //Remember: square matrices
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<size)
A[i] = B[i] + C[i];
}
//Kernel function (point c of exercise)
__global__ void matrixPerRowsAddKernel(float *A, float *B, float *C, int nRows){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nRows){
for (int j=0; j<nRows; j++){
A[i * nRows + j] = B[i * nRows + j] + C[i * nRows + j];
}
}
}
//Kernel function (point d of exercise)
__global__ void matrixPerColumnsAddKernel(float *A, float *B, float *C, int nColumns){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nColumns){
for (int j=0; j<nColumns; j++){
A[i + j * nColumns] = B[i + j * nColumns] + C[i + j * nColumns];
}
}
}
/**
* Stub function used to compute matrices sum.
* (function used to launch the kernel and to allocate device mem, ...)
*/
void matrixAdd(float* A, float *B, float *C, int nRows){
size_t size = nRows * nRows * sizeof(float);
float * d_A;
float * d_B;
float * d_C;
//Allocate device memory for matrices
CUDA_CHECK_RETURN(hipMalloc((void **) &d_B, size));
CUDA_CHECK_RETURN(hipMalloc((void **) &d_C, size));
CUDA_CHECK_RETURN(hipMalloc((void **) &d_A, size));
//Copy B and C to device memory
CUDA_CHECK_RETURN(hipMemcpy(d_B, B, size, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(d_C, C, size, hipMemcpyHostToDevice));
//Kernel launch code
//assume block of 64 threads
matrixAddKernel <<< ceil((double)(nRows*nRows)/BLOCK_WIDTH), BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Two other possible kernel functions
//matrixPerRowsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//matrixPerColumnsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Copy A from the device memory
CUDA_CHECK_RETURN(hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost));
//Free device matrices
hipFree(d_C);
hipFree(d_B);
hipFree(d_A);
}
int main(int argc, char** argv){
//Initialize random seed
//@see http://www.cplusplus.com/reference/cstdlib/srand/
//@see https://stackoverflow.com/questions/20158841/my-random-number-generator-function-generates-the-same-number
srand(time(NULL));
int numRows;
printf("\nInsert the number of rows (equivalently columns): ");
scanf("%d", &numRows);
int numColumns = numRows; //Square matrix
int nElem = numRows * numColumns;
float * B = (float *) malloc(nElem * sizeof(float));
float * C = (float *) malloc(nElem * sizeof(float));
float * A = (float *) malloc(nElem * sizeof(float));
//Initialize B and C matrices
initData(B, numRows);
initData(C, numRows);
//Display B and C matrices
printf("\n\tMatrice B\n");
displayData(B, numRows);
printf("\n\n\tMatrice C\n");
displayData(C, numRows);
//matrices sum
matrixAdd(A, B, C, numRows);
//Display A matrix
printf("\n\n\tMatrice A\n");
displayData(A, numRows);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixAddKernelPfS_S_i
.globl _Z15matrixAddKernelPfS_S_i
.p2align 8
.type _Z15matrixAddKernelPfS_S_i,@function
_Z15matrixAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s3, s3, s3
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixAddKernelPfS_S_i, .Lfunc_end0-_Z15matrixAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22matrixPerRowsAddKernelPfS_S_i
.globl _Z22matrixPerRowsAddKernelPfS_S_i
.p2align 8
.type _Z22matrixPerRowsAddKernelPfS_S_i,@function
_Z22matrixPerRowsAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB1_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22matrixPerRowsAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22matrixPerRowsAddKernelPfS_S_i, .Lfunc_end1-_Z22matrixPerRowsAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25matrixPerColumnsAddKernelPfS_S_i
.globl _Z25matrixPerColumnsAddKernelPfS_S_i
.p2align 8
.type _Z25matrixPerColumnsAddKernelPfS_S_i,@function
_Z25matrixPerColumnsAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB2_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, s2
.p2align 6
.LBB2_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25matrixPerColumnsAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z25matrixPerColumnsAddKernelPfS_S_i, .Lfunc_end2-_Z25matrixPerColumnsAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22matrixPerRowsAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22matrixPerRowsAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25matrixPerColumnsAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25matrixPerColumnsAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Sum two square matrix (A = B + C)
* Exercise 3.1 of programming massively parallel processors book
* Solution provided with matrix view as array
* @author Niccolò Bellaccini
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h> //rand
#include <time.h> //rand
#include <math.h> //ceil
#include <iostream> //std::cerr
#define BLOCK_WIDTH 64
void initData(float* M, int nRows){ //Remeber: matrix square
for (int i=0; i<nRows; i++){
for(int j=0; j<nRows; j++){
M[nRows * i + j] = (float) (rand() & 0xFF) / 10.0f;
}
}
}
void displayData(float *M, int nRows){
for (int i=0; i<nRows; i++){
printf("\n");
for(int j=0; j<nRows; j++){
printf("%.1f\t", M[nRows * i + j]);
}
}
}
/**
* function-like macro
* __LINE__ = contains the line number of the currently compiled line of code
* __FILE__ = string that contains the name of the source file being compiled
* # operator = turns the argument it precedes into a quoted string
* Reference: [C the complete reference]
* check with > nvcc -E
*/
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__, __LINE__, #value, value)
static void CheckCudaErrorAux (const char *file, unsigned line,
const char *statement, hipError_t err){
if(err == hipSuccess)
return;
std::cerr << statement << " returned " << hipGetErrorString(err) <<
"(" << err << ") at " << file << ":" << line << std::endl;
exit(1);
}
//Kernel function (point b of exercise)
__global__ void matrixAddKernel(float *A, float *B, float *C, int nRows){
int size = nRows * nRows; //Remember: square matrices
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<size)
A[i] = B[i] + C[i];
}
//Kernel function (point c of exercise)
__global__ void matrixPerRowsAddKernel(float *A, float *B, float *C, int nRows){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nRows){
for (int j=0; j<nRows; j++){
A[i * nRows + j] = B[i * nRows + j] + C[i * nRows + j];
}
}
}
//Kernel function (point d of exercise)
__global__ void matrixPerColumnsAddKernel(float *A, float *B, float *C, int nColumns){
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i<nColumns){
for (int j=0; j<nColumns; j++){
A[i + j * nColumns] = B[i + j * nColumns] + C[i + j * nColumns];
}
}
}
/**
* Stub function used to compute matrices sum.
* (function used to launch the kernel and to allocate device mem, ...)
*/
void matrixAdd(float* A, float *B, float *C, int nRows){
size_t size = nRows * nRows * sizeof(float);
float * d_A;
float * d_B;
float * d_C;
//Allocate device memory for matrices
CUDA_CHECK_RETURN(hipMalloc((void **) &d_B, size));
CUDA_CHECK_RETURN(hipMalloc((void **) &d_C, size));
CUDA_CHECK_RETURN(hipMalloc((void **) &d_A, size));
//Copy B and C to device memory
CUDA_CHECK_RETURN(hipMemcpy(d_B, B, size, hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(hipMemcpy(d_C, C, size, hipMemcpyHostToDevice));
//Kernel launch code
//assume block of 64 threads
matrixAddKernel <<< ceil((double)(nRows*nRows)/BLOCK_WIDTH), BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Two other possible kernel functions
//matrixPerRowsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//matrixPerColumnsAddKernel<<< ceil((double)nRows/BLOCK_WIDTH) ,BLOCK_WIDTH>>>(d_A, d_B, d_C, nRows);
//Copy A from the device memory
CUDA_CHECK_RETURN(hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost));
//Free device matrices
hipFree(d_C);
hipFree(d_B);
hipFree(d_A);
}
int main(int argc, char** argv){
//Initialize random seed
//@see http://www.cplusplus.com/reference/cstdlib/srand/
//@see https://stackoverflow.com/questions/20158841/my-random-number-generator-function-generates-the-same-number
srand(time(NULL));
int numRows;
printf("\nInsert the number of rows (equivalently columns): ");
scanf("%d", &numRows);
int numColumns = numRows; //Square matrix
int nElem = numRows * numColumns;
float * B = (float *) malloc(nElem * sizeof(float));
float * C = (float *) malloc(nElem * sizeof(float));
float * A = (float *) malloc(nElem * sizeof(float));
//Initialize B and C matrices
initData(B, numRows);
initData(C, numRows);
//Display B and C matrices
printf("\n\tMatrice B\n");
displayData(B, numRows);
printf("\n\n\tMatrice C\n");
displayData(C, numRows);
//matrices sum
matrixAdd(A, B, C, numRows);
//Display A matrix
printf("\n\n\tMatrice A\n");
displayData(A, numRows);
} | .text
.file "MatrixSumTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8initDataPfi
.LCPI0_0:
.long 0x41200000 # float 10
.text
.globl _Z8initDataPfi
.p2align 4, 0x90
.type _Z8initDataPfi,@function
_Z8initDataPfi: # @_Z8initDataPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB0_2
.LBB0_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8initDataPfi, .Lfunc_end0-_Z8initDataPfi
.cfi_endproc
# -- End function
.globl _Z11displayDataPfi # -- Begin function _Z11displayDataPfi
.p2align 4, 0x90
.type _Z11displayDataPfi,@function
_Z11displayDataPfi: # @_Z11displayDataPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.lr.ph14
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge15
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11displayDataPfi, .Lfunc_end1-_Z11displayDataPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixAddKernelPfS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPfS_S_i,@function
_Z30__device_stub__matrixAddKernelPfS_S_i: # @_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__matrixAddKernelPfS_S_i, .Lfunc_end2-_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i # -- Begin function _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i,@function
_Z37__device_stub__matrixPerRowsAddKernelPfS_S_i: # @_Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22matrixPerRowsAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i, .Lfunc_end3-_Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i # -- Begin function _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i,@function
_Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i: # @_Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25matrixPerColumnsAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i, .Lfunc_end4-_Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9matrixAddPfS_S_i
.LCPI5_0:
.quad 0x3f90000000000000 # double 0.015625
.text
.globl _Z9matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i: # @_Z9matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
movl %ecx, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl $97, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str.4, %esi
movl $98, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str.5, %esi
movl $99, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl $102, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.7, %esi
movl $103, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
cvtsi2sd %r13d, %xmm0
mulsd .LCPI5_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.8, %esi
movl $115, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9matrixAddPfS_S_i, .Lfunc_end5-_Z9matrixAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB6_2
# %bb.1:
retq
.LBB6_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.14, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.16, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.17, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end6:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end6-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %r13d
movl %r13d, %ebx
imull %ebx, %ebx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB7_5
# %bb.1: # %.preheader.lr.ph.i
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
movl %r12d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r13
jne .LBB7_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB7_2 Depth=1
incq %rbp
addl %r13d, %r12d
cmpq %r13, %rbp
jne .LBB7_2
.LBB7_5: # %_Z8initDataPfi.exit
movl 4(%rsp), %r12d
testl %r12d, %r12d
jle .LBB7_10
# %bb.6: # %.preheader.lr.ph.i13
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_7: # %.preheader.i15
# =>This Loop Header: Depth=1
# Child Loop BB7_8 Depth 2
movl %r13d, %eax
leaq (%r15,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_8: # Parent Loop BB7_7 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r12
jne .LBB7_8
# %bb.9: # %._crit_edge.i21
# in Loop: Header=BB7_7 Depth=1
incq %rbp
addl %r12d, %r13d
cmpq %r12, %rbp
jne .LBB7_7
.LBB7_10: # %_Z8initDataPfi.exit24
movl $.Lstr, %edi
callq puts@PLT
movl 4(%rsp), %r12d
testl %r12d, %r12d
jle .LBB7_15
# %bb.11: # %.lr.ph14.i
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_12: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB7_13 Depth 2
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_13: # Parent Loop BB7_12 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB7_13
# %bb.14: # %._crit_edge.i29
# in Loop: Header=BB7_12 Depth=1
incq %rbp
addl %r12d, %r13d
cmpq %r12, %rbp
jne .LBB7_12
.LBB7_15: # %_Z11displayDataPfi.exit
movl $.Lstr.1, %edi
callq puts@PLT
movl 4(%rsp), %r12d
testl %r12d, %r12d
jle .LBB7_20
# %bb.16: # %.lr.ph14.i30
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_17: # %.lr.ph.i32
# =>This Loop Header: Depth=1
# Child Loop BB7_18 Depth 2
movl %r13d, %eax
leaq (%r15,%rax,4), %rbx
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_18: # Parent Loop BB7_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB7_18
# %bb.19: # %._crit_edge.i39
# in Loop: Header=BB7_17 Depth=1
incq %rbp
addl %r12d, %r13d
cmpq %r12, %rbp
jne .LBB7_17
.LBB7_20: # %_Z11displayDataPfi.exit42
movl 4(%rsp), %ecx
movq 16(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
callq _Z9matrixAddPfS_S_i
movl $.Lstr.2, %edi
callq puts@PLT
movl 4(%rsp), %r14d
testl %r14d, %r14d
jle .LBB7_25
# %bb.21: # %.lr.ph14.i43
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_22: # %.lr.ph.i45
# =>This Loop Header: Depth=1
# Child Loop BB7_23 Depth 2
movl %r15d, %eax
leaq (,%rax,4), %rbx
addq %rbp, %rbx
movl $10, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_23: # Parent Loop BB7_22 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB7_23
# %bb.24: # %._crit_edge.i52
# in Loop: Header=BB7_22 Depth=1
incq %r12
addl %r14d, %r15d
cmpq %r14, %r12
jne .LBB7_22
.LBB7_25: # %_Z11displayDataPfi.exit55
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matrixPerRowsAddKernelPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25matrixPerColumnsAddKernelPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.1f\t"
.size .L.str.1, 6
.type _Z15matrixAddKernelPfS_S_i,@object # @_Z15matrixAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPfS_S_i
.p2align 3, 0x0
_Z15matrixAddKernelPfS_S_i:
.quad _Z30__device_stub__matrixAddKernelPfS_S_i
.size _Z15matrixAddKernelPfS_S_i, 8
.type _Z22matrixPerRowsAddKernelPfS_S_i,@object # @_Z22matrixPerRowsAddKernelPfS_S_i
.globl _Z22matrixPerRowsAddKernelPfS_S_i
.p2align 3, 0x0
_Z22matrixPerRowsAddKernelPfS_S_i:
.quad _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.size _Z22matrixPerRowsAddKernelPfS_S_i, 8
.type _Z25matrixPerColumnsAddKernelPfS_S_i,@object # @_Z25matrixPerColumnsAddKernelPfS_S_i
.globl _Z25matrixPerColumnsAddKernelPfS_S_i
.p2align 3, 0x0
_Z25matrixPerColumnsAddKernelPfS_S_i:
.quad _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.size _Z25matrixPerColumnsAddKernelPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kinik93/Matrix-sum-CUDA/master/MatrixSumTest.hip"
.size .L.str.2, 106
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void **) &d_B, size)"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc((void **) &d_C, size)"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc((void **) &d_A, size)"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(d_B, B, size, hipMemcpyHostToDevice)"
.size .L.str.6, 47
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy(d_C, C, size, hipMemcpyHostToDevice)"
.size .L.str.7, 47
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost)"
.size .L.str.8, 47
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nInsert the number of rows (equivalently columns): "
.size .L.str.9, 52
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d"
.size .L.str.10, 3
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " returned "
.size .L.str.14, 11
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "("
.size .L.str.15, 2
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz ") at "
.size .L.str.16, 6
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz ":"
.size .L.str.17, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22matrixPerRowsAddKernelPfS_S_i"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z25matrixPerColumnsAddKernelPfS_S_i"
.size .L__unnamed_3, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\tMatrice B"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\n\tMatrice C"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\n\tMatrice A"
.size .Lstr.2, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPfS_S_i
.addrsig_sym _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.addrsig_sym _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPfS_S_i
.addrsig_sym _Z22matrixPerRowsAddKernelPfS_S_i
.addrsig_sym _Z25matrixPerColumnsAddKernelPfS_S_i
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142723_00000000-6_MatrixSumTest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB3671:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initDataPfi
.type _Z8initDataPfi, @function
_Z8initDataPfi:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L12:
leaq 0(%rbp,%r13), %rbx
.L13:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC4(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L12
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3669:
.size _Z8initDataPfi, .-_Z8initDataPfi
.section .rodata.str1.1
.LC5:
.string "\n"
.LC6:
.string "%.1f\t"
.text
.globl _Z11displayDataPfi
.type _Z11displayDataPfi, @function
_Z11displayDataPfi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L19
movslq %esi, %r14
leaq 0(,%r14,4), %r15
leaq (%rdi,%r15), %rbp
negq %r14
salq $2, %r14
movl $0, %r13d
leaq .LC6(%rip), %r12
.L22:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(%rbp,%r14), %rbx
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
addl $1, %r13d
addq %r15, %rbp
cmpl %r13d, 12(%rsp)
jne .L22
.L19:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z11displayDataPfi, .-_Z11displayDataPfi
.globl _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
.globl _Z15matrixAddKernelPfS_S_i
.type _Z15matrixAddKernelPfS_S_i, @function
_Z15matrixAddKernelPfS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z15matrixAddKernelPfS_S_i, .-_Z15matrixAddKernelPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cudaMalloc((void **) &d_B, size)"
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kinik93/Matrix-sum-CUDA/master/MatrixSumTest.cu"
.align 8
.LC9:
.string "cudaMalloc((void **) &d_C, size)"
.align 8
.LC10:
.string "cudaMalloc((void **) &d_A, size)"
.align 8
.LC11:
.string "cudaMemcpy(d_B, B, size, cudaMemcpyHostToDevice)"
.align 8
.LC12:
.string "cudaMemcpy(d_C, C, size, cudaMemcpyHostToDevice)"
.align 8
.LC17:
.string "cudaMemcpy(A, d_A, size, cudaMemcpyDeviceToHost)"
.text
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movq %rsi, %r14
movq %rdx, %r13
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %ecx, %r15d
imull %ecx, %r15d
movslq %r15d, %rbx
salq $2, %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC7(%rip), %rdx
movl $97, %esi
leaq .LC8(%rip), %rbp
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $98, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC10(%rip), %rdx
movl $99, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $102, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC12(%rip), %rdx
movl $103, %esi
movq %rbp, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $64, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
mulsd .LC13(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC18(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC14(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L35
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC16(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L35:
cvttsd2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L36:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $115, %esi
leaq .LC8(%rip), %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z15matrixAddKernelPfS_S_iPfS_S_i
jmp .L36
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.section .rodata.str1.8
.align 8
.LC19:
.string "\nInsert the number of rows (equivalently columns): "
.section .rodata.str1.1
.LC20:
.string "%d"
.LC21:
.string "\n\tMatrice B\n"
.LC22:
.string "\n\n\tMatrice C\n"
.LC23:
.string "\n\n\tMatrice A\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC20(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %r13d
movl %r13d, %ebx
imull %r13d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %esi
movq %rbp, %rdi
call _Z8initDataPfi
movl 4(%rsp), %esi
movq %r12, %rdi
call _Z8initDataPfi
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
movq %rbp, %rdi
call _Z11displayDataPfi
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
movq %r12, %rdi
call _Z11displayDataPfi
movl 4(%rsp), %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z9matrixAddPfS_S_i
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
movq %rbx, %rdi
call _Z11displayDataPfi
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.globl _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i
.type _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matrixPerRowsAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i
.globl _Z22matrixPerRowsAddKernelPfS_S_i
.type _Z22matrixPerRowsAddKernelPfS_S_i, @function
_Z22matrixPerRowsAddKernelPfS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22matrixPerRowsAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z22matrixPerRowsAddKernelPfS_S_i, .-_Z22matrixPerRowsAddKernelPfS_S_i
.globl _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i
.type _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i, @function
_Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L57
.L53:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25matrixPerColumnsAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L53
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i, .-_Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i
.globl _Z25matrixPerColumnsAddKernelPfS_S_i
.type _Z25matrixPerColumnsAddKernelPfS_S_i, @function
_Z25matrixPerColumnsAddKernelPfS_S_i:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25matrixPerColumnsAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z25matrixPerColumnsAddKernelPfS_S_i, .-_Z25matrixPerColumnsAddKernelPfS_S_i
.section .rodata.str1.8
.align 8
.LC24:
.string "_Z25matrixPerColumnsAddKernelPfS_S_i"
.align 8
.LC25:
.string "_Z22matrixPerRowsAddKernelPfS_S_i"
.section .rodata.str1.1
.LC26:
.string "_Z15matrixAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z25matrixPerColumnsAddKernelPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrixPerRowsAddKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1092616192
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC13:
.long 0
.long 1066401792
.align 8
.LC14:
.long 0
.long 1127219200
.align 8
.LC16:
.long 0
.long 1072693248
.align 8
.LC18:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixSumTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z8initDataPfi
.LCPI0_0:
.long 0x41200000 # float 10
.text
.globl _Z8initDataPfi
.p2align 4, 0x90
.type _Z8initDataPfi,@function
_Z8initDataPfi: # @_Z8initDataPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB0_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB0_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB0_2
.LBB0_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8initDataPfi, .Lfunc_end0-_Z8initDataPfi
.cfi_endproc
# -- End function
.globl _Z11displayDataPfi # -- Begin function _Z11displayDataPfi
.p2align 4, 0x90
.type _Z11displayDataPfi,@function
_Z11displayDataPfi: # @_Z11displayDataPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.lr.ph14
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge15
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11displayDataPfi, .Lfunc_end1-_Z11displayDataPfi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixAddKernelPfS_S_i # -- Begin function _Z30__device_stub__matrixAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPfS_S_i,@function
_Z30__device_stub__matrixAddKernelPfS_S_i: # @_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z30__device_stub__matrixAddKernelPfS_S_i, .Lfunc_end2-_Z30__device_stub__matrixAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i # -- Begin function _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i,@function
_Z37__device_stub__matrixPerRowsAddKernelPfS_S_i: # @_Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22matrixPerRowsAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i, .Lfunc_end3-_Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i # -- Begin function _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i,@function
_Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i: # @_Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25matrixPerColumnsAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i, .Lfunc_end4-_Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9matrixAddPfS_S_i
.LCPI5_0:
.quad 0x3f90000000000000 # double 0.015625
.text
.globl _Z9matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i: # @_Z9matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
movl %ecx, %r13d
imull %r13d, %r13d
leaq (,%r13,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl $97, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str.4, %esi
movl $98, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str.5, %esi
movl $99, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl $102, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.7, %esi
movl $103, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
cvtsi2sd %r13d, %xmm0
mulsd .LCPI5_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $64, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.8, %esi
movl $115, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9matrixAddPfS_S_i, .Lfunc_end5-_Z9matrixAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB6_2
# %bb.1:
retq
.LBB6_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.14, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.16, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.17, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end6:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end6-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.10, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %r13d
movl %r13d, %ebx
imull %ebx, %ebx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB7_5
# %bb.1: # %.preheader.lr.ph.i
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
movl %r12d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r13
jne .LBB7_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB7_2 Depth=1
incq %rbp
addl %r13d, %r12d
cmpq %r13, %rbp
jne .LBB7_2
.LBB7_5: # %_Z8initDataPfi.exit
movl 4(%rsp), %r12d
testl %r12d, %r12d
jle .LBB7_10
# %bb.6: # %.preheader.lr.ph.i13
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_7: # %.preheader.i15
# =>This Loop Header: Depth=1
# Child Loop BB7_8 Depth 2
movl %r13d, %eax
leaq (%r15,%rax,4), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_8: # Parent Loop BB7_7 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI7_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq %r14, %r12
jne .LBB7_8
# %bb.9: # %._crit_edge.i21
# in Loop: Header=BB7_7 Depth=1
incq %rbp
addl %r12d, %r13d
cmpq %r12, %rbp
jne .LBB7_7
.LBB7_10: # %_Z8initDataPfi.exit24
movl $.Lstr, %edi
callq puts@PLT
movl 4(%rsp), %r12d
testl %r12d, %r12d
jle .LBB7_15
# %bb.11: # %.lr.ph14.i
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_12: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB7_13 Depth 2
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_13: # Parent Loop BB7_12 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB7_13
# %bb.14: # %._crit_edge.i29
# in Loop: Header=BB7_12 Depth=1
incq %rbp
addl %r12d, %r13d
cmpq %r12, %rbp
jne .LBB7_12
.LBB7_15: # %_Z11displayDataPfi.exit
movl $.Lstr.1, %edi
callq puts@PLT
movl 4(%rsp), %r12d
testl %r12d, %r12d
jle .LBB7_20
# %bb.16: # %.lr.ph14.i30
xorl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB7_17: # %.lr.ph.i32
# =>This Loop Header: Depth=1
# Child Loop BB7_18 Depth 2
movl %r13d, %eax
leaq (%r15,%rax,4), %rbx
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_18: # Parent Loop BB7_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB7_18
# %bb.19: # %._crit_edge.i39
# in Loop: Header=BB7_17 Depth=1
incq %rbp
addl %r12d, %r13d
cmpq %r12, %rbp
jne .LBB7_17
.LBB7_20: # %_Z11displayDataPfi.exit42
movl 4(%rsp), %ecx
movq 16(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
callq _Z9matrixAddPfS_S_i
movl $.Lstr.2, %edi
callq puts@PLT
movl 4(%rsp), %r14d
testl %r14d, %r14d
jle .LBB7_25
# %bb.21: # %.lr.ph14.i43
xorl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_22: # %.lr.ph.i45
# =>This Loop Header: Depth=1
# Child Loop BB7_23 Depth 2
movl %r15d, %eax
leaq (,%rax,4), %rbx
addq %rbp, %rbx
movl $10, %edi
callq putchar@PLT
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_23: # Parent Loop BB7_22 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r13
cmpq %r13, %r14
jne .LBB7_23
# %bb.24: # %._crit_edge.i52
# in Loop: Header=BB7_22 Depth=1
incq %r12
addl %r14d, %r15d
cmpq %r14, %r12
jne .LBB7_22
.LBB7_25: # %_Z11displayDataPfi.exit55
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matrixPerRowsAddKernelPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25matrixPerColumnsAddKernelPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.1f\t"
.size .L.str.1, 6
.type _Z15matrixAddKernelPfS_S_i,@object # @_Z15matrixAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPfS_S_i
.p2align 3, 0x0
_Z15matrixAddKernelPfS_S_i:
.quad _Z30__device_stub__matrixAddKernelPfS_S_i
.size _Z15matrixAddKernelPfS_S_i, 8
.type _Z22matrixPerRowsAddKernelPfS_S_i,@object # @_Z22matrixPerRowsAddKernelPfS_S_i
.globl _Z22matrixPerRowsAddKernelPfS_S_i
.p2align 3, 0x0
_Z22matrixPerRowsAddKernelPfS_S_i:
.quad _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.size _Z22matrixPerRowsAddKernelPfS_S_i, 8
.type _Z25matrixPerColumnsAddKernelPfS_S_i,@object # @_Z25matrixPerColumnsAddKernelPfS_S_i
.globl _Z25matrixPerColumnsAddKernelPfS_S_i
.p2align 3, 0x0
_Z25matrixPerColumnsAddKernelPfS_S_i:
.quad _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.size _Z25matrixPerColumnsAddKernelPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kinik93/Matrix-sum-CUDA/master/MatrixSumTest.hip"
.size .L.str.2, 106
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void **) &d_B, size)"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc((void **) &d_C, size)"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMalloc((void **) &d_A, size)"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(d_B, B, size, hipMemcpyHostToDevice)"
.size .L.str.6, 47
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy(d_C, C, size, hipMemcpyHostToDevice)"
.size .L.str.7, 47
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy(A, d_A, size, hipMemcpyDeviceToHost)"
.size .L.str.8, 47
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nInsert the number of rows (equivalently columns): "
.size .L.str.9, 52
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d"
.size .L.str.10, 3
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " returned "
.size .L.str.14, 11
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "("
.size .L.str.15, 2
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz ") at "
.size .L.str.16, 6
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz ":"
.size .L.str.17, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22matrixPerRowsAddKernelPfS_S_i"
.size .L__unnamed_2, 34
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z25matrixPerColumnsAddKernelPfS_S_i"
.size .L__unnamed_3, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\tMatrice B"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\n\tMatrice C"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\n\tMatrice A"
.size .Lstr.2, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPfS_S_i
.addrsig_sym _Z37__device_stub__matrixPerRowsAddKernelPfS_S_i
.addrsig_sym _Z40__device_stub__matrixPerColumnsAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPfS_S_i
.addrsig_sym _Z22matrixPerRowsAddKernelPfS_S_i
.addrsig_sym _Z25matrixPerColumnsAddKernelPfS_S_i
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// From: https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
// by Mark Harris
//
#include <algorithm>
#include <cmath>
#include <stdio.h>
template<typename T, typename U>
constexpr T ceildiv(T t, U u) {
return (t + u - 1) / u;
}
__global__
void saxpy(int n, float a, float* x, float* y) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
y[i] = a * x[i] + y[i];
}
}
int main() {
constexpr int N = 1 << 20;
float *x, *y, *d_x, *d_y;
x = (float*)malloc(N * sizeof(float));
y = (float*)malloc(N * sizeof(float));
cudaMalloc(&d_x, N * sizeof(float));
cudaMalloc(&d_y, N * sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(d_x, x, N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N * sizeof(float), cudaMemcpyHostToDevice);
constexpr int blockSize = 256;
constexpr int nBlocks = ceildiv(N, blockSize);
cudaEventRecord(start);
saxpy<<<nBlocks, blockSize>>>(N, 2.0f, d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float millis = 0.0f;
cudaEventElapsedTime(&millis, start, stop);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = std::max(maxError, std::abs(y[i] - 4.0f));
}
printf("max error: %f\n", maxError);
printf("duration (ms): %f\n", millis);
printf("effective bandwidth (gb/s): %f\n", (float)N * sizeof(float) * 3 / millis / 1e6);
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
return 0;
} | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// From: https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
// by Mark Harris
//
#include <algorithm>
#include <cmath>
#include <stdio.h>
template<typename T, typename U>
constexpr T ceildiv(T t, U u) {
return (t + u - 1) / u;
}
__global__
void saxpy(int n, float a, float* x, float* y) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
y[i] = a * x[i] + y[i];
}
}
int main() {
constexpr int N = 1 << 20;
float *x, *y, *d_x, *d_y;
x = (float*)malloc(N * sizeof(float));
y = (float*)malloc(N * sizeof(float));
cudaMalloc(&d_x, N * sizeof(float));
cudaMalloc(&d_y, N * sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(d_x, x, N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N * sizeof(float), cudaMemcpyHostToDevice);
constexpr int blockSize = 256;
constexpr int nBlocks = ceildiv(N, blockSize);
cudaEventRecord(start);
saxpy<<<nBlocks, blockSize>>>(N, 2.0f, d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float millis = 0.0f;
cudaEventElapsedTime(&millis, start, stop);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = std::max(maxError, std::abs(y[i] - 4.0f));
}
printf("max error: %f\n", maxError);
printf("duration (ms): %f\n", millis);
printf("effective bandwidth (gb/s): %f\n", (float)N * sizeof(float) * 3 / millis / 1e6);
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
return 0;
} | .file "tmpxft_0017ac0c_00000000-6_02_timers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2342:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2342:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2364:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2364:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2365:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2365:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max error: %f\n"
.LC6:
.string "duration (ms): %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "effective bandwidth (gb/s): %f\n"
.text
.globl main
.type main, @function
main:
.LFB2338:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rax
leaq 4194304(%rbx), %rdx
pxor %xmm1, %xmm1
movss .LC3(%rip), %xmm3
movss .LC4(%rip), %xmm2
.L16:
movss (%rax), %xmm0
subss %xmm3, %xmm0
andps %xmm2, %xmm0
maxss %xmm1, %xmm0
movaps %xmm0, %xmm1
addq $4, %rax
cmpq %rax, %rdx
jne .L16
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC7(%rip), %xmm0
divss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC2(%rip), %xmm0
movl $1048576, %edi
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
jmp .L13
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2367:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2367:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC7:
.long 1262485504
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// From: https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
// by Mark Harris
//
#include <algorithm>
#include <cmath>
#include <stdio.h>
template<typename T, typename U>
constexpr T ceildiv(T t, U u) {
return (t + u - 1) / u;
}
__global__
void saxpy(int n, float a, float* x, float* y) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
y[i] = a * x[i] + y[i];
}
}
int main() {
constexpr int N = 1 << 20;
float *x, *y, *d_x, *d_y;
x = (float*)malloc(N * sizeof(float));
y = (float*)malloc(N * sizeof(float));
cudaMalloc(&d_x, N * sizeof(float));
cudaMalloc(&d_y, N * sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(d_x, x, N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, N * sizeof(float), cudaMemcpyHostToDevice);
constexpr int blockSize = 256;
constexpr int nBlocks = ceildiv(N, blockSize);
cudaEventRecord(start);
saxpy<<<nBlocks, blockSize>>>(N, 2.0f, d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float millis = 0.0f;
cudaEventElapsedTime(&millis, start, stop);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = std::max(maxError, std::abs(y[i] - 4.0f));
}
printf("max error: %f\n", maxError);
printf("duration (ms): %f\n", millis);
printf("effective bandwidth (gb/s): %f\n", (float)N * sizeof(float) * 3 / millis / 1e6);
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
return 0;
} | //
// From: https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
// by Mark Harris
//
#include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <stdio.h>
template<typename T, typename U>
constexpr T ceildiv(T t, U u) {
return (t + u - 1) / u;
}
__global__
void saxpy(int n, float a, float* x, float* y) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
y[i] = a * x[i] + y[i];
}
}
int main() {
constexpr int N = 1 << 20;
float *x, *y, *d_x, *d_y;
x = (float*)malloc(N * sizeof(float));
y = (float*)malloc(N * sizeof(float));
hipMalloc(&d_x, N * sizeof(float));
hipMalloc(&d_y, N * sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(d_x, x, N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N * sizeof(float), hipMemcpyHostToDevice);
constexpr int blockSize = 256;
constexpr int nBlocks = ceildiv(N, blockSize);
hipEventRecord(start);
saxpy<<<nBlocks, blockSize>>>(N, 2.0f, d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, N * sizeof(float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float millis = 0.0f;
hipEventElapsedTime(&millis, start, stop);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = std::max(maxError, std::abs(y[i] - 4.0f));
}
printf("max error: %f\n", maxError);
printf("duration (ms): %f\n", millis);
printf("effective bandwidth (gb/s): %f\n", (float)N * sizeof(float) * 3 / millis / 1e6);
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// From: https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
// by Mark Harris
//
#include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <stdio.h>
template<typename T, typename U>
constexpr T ceildiv(T t, U u) {
return (t + u - 1) / u;
}
__global__
void saxpy(int n, float a, float* x, float* y) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
y[i] = a * x[i] + y[i];
}
}
int main() {
constexpr int N = 1 << 20;
float *x, *y, *d_x, *d_y;
x = (float*)malloc(N * sizeof(float));
y = (float*)malloc(N * sizeof(float));
hipMalloc(&d_x, N * sizeof(float));
hipMalloc(&d_y, N * sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(d_x, x, N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N * sizeof(float), hipMemcpyHostToDevice);
constexpr int blockSize = 256;
constexpr int nBlocks = ceildiv(N, blockSize);
hipEventRecord(start);
saxpy<<<nBlocks, blockSize>>>(N, 2.0f, d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, N * sizeof(float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float millis = 0.0f;
hipEventElapsedTime(&millis, start, stop);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = std::max(maxError, std::abs(y[i] - 4.0f));
}
printf("max error: %f\n", maxError);
printf("duration (ms): %f\n", millis);
printf("effective bandwidth (gb/s): %f\n", (float)N * sizeof(float) * 3 / millis / 1e6);
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// From: https://developer.nvidia.com/blog/how-implement-performance-metrics-cuda-cc/
// by Mark Harris
//
#include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <stdio.h>
template<typename T, typename U>
constexpr T ceildiv(T t, U u) {
return (t + u - 1) / u;
}
__global__
void saxpy(int n, float a, float* x, float* y) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
y[i] = a * x[i] + y[i];
}
}
int main() {
constexpr int N = 1 << 20;
float *x, *y, *d_x, *d_y;
x = (float*)malloc(N * sizeof(float));
y = (float*)malloc(N * sizeof(float));
hipMalloc(&d_x, N * sizeof(float));
hipMalloc(&d_y, N * sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(d_x, x, N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, N * sizeof(float), hipMemcpyHostToDevice);
constexpr int blockSize = 256;
constexpr int nBlocks = ceildiv(N, blockSize);
hipEventRecord(start);
saxpy<<<nBlocks, blockSize>>>(N, 2.0f, d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, N * sizeof(float), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float millis = 0.0f;
hipEventElapsedTime(&millis, start, stop);
float maxError = 0.0f;
for (int i = 0; i < N; i++) {
maxError = std::max(maxError, std::abs(y[i] - 4.0f));
}
printf("max error: %f\n", maxError);
printf("duration (ms): %f\n", millis);
printf("effective bandwidth (gb/s): %f\n", (float)N * sizeof(float) * 3 / millis / 1e6);
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
return 0;
} | .text
.file "02_timers.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0800000 # float -4
.LCPI1_2:
.long 0x4b400000 # float 12582912
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 36(%rsp) # imm = 0x100000
movl $1073741824, 32(%rsp) # imm = 0x40000000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 48(%rsp)
leaq 32(%rsp), %rax
movq %rax, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm3
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
andps %xmm2, %xmm0
maxss %xmm3, %xmm0
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 48(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max error: %f\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "duration (ms): %f\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "effective bandwidth (gb/s): %f\n"
.size .L.str.2, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyifPfS_
.globl _Z5saxpyifPfS_
.p2align 8
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017ac0c_00000000-6_02_timers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2342:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2342:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyifPfS_ifPfS_
.type _Z28__device_stub__Z5saxpyifPfS_ifPfS_, @function
_Z28__device_stub__Z5saxpyifPfS_ifPfS_:
.LFB2364:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2364:
.size _Z28__device_stub__Z5saxpyifPfS_ifPfS_, .-_Z28__device_stub__Z5saxpyifPfS_ifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2365:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2365:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max error: %f\n"
.LC6:
.string "duration (ms): %f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "effective bandwidth (gb/s): %f\n"
.text
.globl main
.type main, @function
main:
.LFB2338:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rax
leaq 4194304(%rbx), %rdx
pxor %xmm1, %xmm1
movss .LC3(%rip), %xmm3
movss .LC4(%rip), %xmm2
.L16:
movss (%rax), %xmm0
subss %xmm3, %xmm0
andps %xmm2, %xmm0
maxss %xmm1, %xmm0
movaps %xmm0, %xmm1
addq $4, %rax
cmpq %rax, %rdx
jne .L16
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss .LC7(%rip), %xmm0
divss 44(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC2(%rip), %xmm0
movl $1048576, %edi
call _Z28__device_stub__Z5saxpyifPfS_ifPfS_
jmp .L13
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z5saxpyifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2367:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2367:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC7:
.long 1262485504
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "02_timers.hip"
.globl _Z20__device_stub__saxpyifPfS_ # -- Begin function _Z20__device_stub__saxpyifPfS_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyifPfS_,@function
_Z20__device_stub__saxpyifPfS_: # @_Z20__device_stub__saxpyifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyifPfS_, .Lfunc_end0-_Z20__device_stub__saxpyifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0800000 # float -4
.LCPI1_2:
.long 0x4b400000 # float 12582912
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 36(%rsp) # imm = 0x100000
movl $1073741824, 32(%rsp) # imm = 0x40000000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 48(%rsp)
leaq 32(%rsp), %rax
movq %rax, 56(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5saxpyifPfS_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
xorps %xmm0, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movaps %xmm0, %xmm3
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm1, %xmm0
andps %xmm2, %xmm0
maxss %xmm3, %xmm0
incq %r15
cmpq $1048576, %r15 # imm = 0x100000
jne .LBB1_5
# %bb.6:
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 48(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_3(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyifPfS_,@object # @_Z5saxpyifPfS_
.section .rodata,"a",@progbits
.globl _Z5saxpyifPfS_
.p2align 3, 0x0
_Z5saxpyifPfS_:
.quad _Z20__device_stub__saxpyifPfS_
.size _Z5saxpyifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max error: %f\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "duration (ms): %f\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "effective bandwidth (gb/s): %f\n"
.size .L.str.2, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyifPfS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_profiler_api.h>
#include <iostream>
#include <vector>
#include <future>
void getDeviceInformation() {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, 0);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("No CUDA GPU has been detected\n");
}
else {
printf("Device name: %s\n", deviceProp.name);
printf("Total Global Memory: %d\n", deviceProp.regsPerMultiprocessor);
printf("Total shared mem per block: %d\n", deviceProp.sharedMemPerMultiprocessor);
printf("Total const mem size: %d\n", deviceProp.maxThreadsPerMultiProcessor);
}
}
//cudaStream_t streams[NUM_STREAMS];
void exec(const char* s){
system(s);
}
class Scheduler {
std::vector<std::string> programs;
std::vector<int> map;
int i=0;
public:
Scheduler(){
}
void programCall(std::string str) {
//std::cout << str << "\n";
programs.push_back(str);
map.push_back(-1);
}
void schedule(){
}
void execute(){
//cudaProfilerStart();
for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
std::thread t1(exec, f.data());
t1.join();
}
/*for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
t1(exec, f.data());
}*/
//cudaProfilerStop();
}
};
int main(int argc, char **argv) {
getDeviceInformation();
Scheduler s;
std::string line = "";
while(line != " ") {
std::getline (std::cin, line);
//std::cout << line << "\n";
//std::string str = argv[i];//"./hotspot 1024 2 2 ../../data/hotspot/temp_1024 ../../data/hotspot/power_1024 output.out";
s.programCall(line);
// s.schedule();
}
s.execute();
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_profiler_api.h>
#include <iostream>
#include <vector>
#include <future>
void getDeviceInformation() {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, 0);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("No CUDA GPU has been detected\n");
}
else {
printf("Device name: %s\n", deviceProp.name);
printf("Total Global Memory: %d\n", deviceProp.regsPerMultiprocessor);
printf("Total shared mem per block: %d\n", deviceProp.sharedMemPerMultiprocessor);
printf("Total const mem size: %d\n", deviceProp.maxThreadsPerMultiProcessor);
}
}
//cudaStream_t streams[NUM_STREAMS];
void exec(const char* s){
system(s);
}
class Scheduler {
std::vector<std::string> programs;
std::vector<int> map;
int i=0;
public:
Scheduler(){
}
void programCall(std::string str) {
//std::cout << str << "\n";
programs.push_back(str);
map.push_back(-1);
}
void schedule(){
}
void execute(){
//cudaProfilerStart();
for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
std::thread t1(exec, f.data());
t1.join();
}
/*for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
t1(exec, f.data());
}*/
//cudaProfilerStop();
}
};
int main(int argc, char **argv) {
getDeviceInformation();
Scheduler s;
std::string line = "";
while(line != " ") {
std::getline (std::cin, line);
//std::cout << line << "\n";
//std::string str = argv[i];//"./hotspot 1024 2 2 ../../data/hotspot/temp_1024 ../../data/hotspot/power_1024 output.out";
s.programCall(line);
// s.schedule();
}
s.execute();
return 0;
} | .file "tmpxft_0019009a_00000000-6_main2_bkp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZNSt6thread24_M_thread_deps_never_runEv,"axG",@progbits,_ZNSt6thread24_M_thread_deps_never_runEv,comdat
.weak _ZNSt6thread24_M_thread_deps_never_runEv
.type _ZNSt6thread24_M_thread_deps_never_runEv, @function
_ZNSt6thread24_M_thread_deps_never_runEv:
.LFB4995:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE4995:
.size _ZNSt6thread24_M_thread_deps_never_runEv, .-_ZNSt6thread24_M_thread_deps_never_runEv
.section .text._ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv,"axG",@progbits,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv,comdat
.align 2
.weak _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv, @function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv:
.LFB6900:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq 8(%rdi), %rdi
call *16(%rax)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6900:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv, .-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.text
.globl _Z4execPKc
.type _Z4execPKc, @function
_Z4execPKc:
.LFB5295:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call system@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5295:
.size _Z4execPKc, .-_Z4execPKc
.section .text._ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev,"axG",@progbits,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED5Ev,comdat
.align 2
.weak _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev, @function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev:
.LFB6879:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16+_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE(%rip), %rax
movq %rax, (%rdi)
call _ZNSt6thread6_StateD2Ev@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6879:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev, .-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev
.weak _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED1Ev
.set _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED1Ev,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED2Ev
.section .text._ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev,"axG",@progbits,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED5Ev,comdat
.align 2
.weak _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev, @function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev:
.LFB6881:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 16+_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE(%rip), %rax
movq %rax, (%rdi)
call _ZNSt6thread6_StateD2Ev@PLT
movl $24, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6881:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev, .-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5328:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5328:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "No CUDA GPU has been detected\n"
.align 8
.LC1:
.string "Device name: %s\n"
.align 8
.LC2:
.string "Total Global Memory: %d\n"
.align 8
.LC3:
.string "Total shared mem per block: %d\n"
.align 8
.LC4:
.string "Total const mem size: %d\n"
.text
.globl _Z20getDeviceInformationv
.type _Z20getDeviceInformationv, @function
_Z20getDeviceInformationv:
.LFB5294:
.cfi_startproc
endbr64
subq $1048, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movabsq $42945378002703, %rax
cmpq %rax, 360(%rsp)
je .L17
movq %rsp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 648(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 640(%rsp), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 624(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L12:
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5294:
.size _Z20getDeviceInformationv, .-_Z20getDeviceInformationv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5351:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5351:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev:
.LFB5908:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq 8(%rdi), %rbp
movq (%rdi), %rbx
cmpq %rbx, %rbp
jne .L24
.L22:
movq (%r12), %rdi
testq %rdi, %rdi
je .L21
movq 16(%r12), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L21:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
addq $32, %rbx
cmpq %rbx, %rbp
je .L22
.L24:
movq (%rbx), %rdi
leaq 16(%rbx), %rax
cmpq %rax, %rdi
je .L23
movq 16(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
jmp .L23
.cfi_endproc
.LFE5908:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
.set _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag:
.LFB6269:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L35
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L31
movzbl (%rsi), %eax
movb %al, (%rdi)
.L32:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L30:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L32
.L31:
testq %rdx, %rdx
je .L32
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6269:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.section .rodata._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_.str1.1,"aMS",@progbits,1
.LC5:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_:
.LFB6256:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA6256
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, 8(%rsp)
movq 8(%rdi), %r13
movq (%rdi), %rbp
movq %r13, %rax
subq %rbp, %rax
sarq $5, %rax
movabsq $288230376151711743, %rdx
cmpq %rdx, %rax
je .L79
movq %rdi, %r12
movq %rsi, %rbx
cmpq %rbp, %r13
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L40
movabsq $288230376151711743, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, (%rsp)
movq %rsi, %r14
subq %rbp, %r14
movl $0, %r15d
testq %rax, %rax
je .L41
jmp .L67
.L79:
leaq .LC5(%rip), %rdi
.LEHB0:
call _ZSt20__throw_length_errorPKc@PLT
.LEHE0:
.L86:
cmpq %rbp, %rbx
je .L70
leaq 16(%rbp), %rax
leaq 16(%rbx), %r8
movq %r15, %rdx
jmp .L51
.L82:
movq -8(%rcx), %r11
leaq 1(%r11), %r9
cmpl $8, %r9d
jnb .L44
testb $4, %r9b
jne .L80
testl %r9d, %r9d
je .L50
movzbl (%rcx), %r10d
movb %r10b, (%rsi)
testb $2, %r9b
je .L50
movl %r9d, %r9d
movzwl -2(%rcx,%r9), %ecx
movw %cx, -2(%rsi,%r9)
jmp .L50
.L80:
movl (%rcx), %r10d
movl %r10d, (%rsi)
movl %r9d, %r9d
movl -4(%rcx,%r9), %ecx
movl %ecx, -4(%rsi,%r9)
jmp .L50
.L44:
movq (%rcx), %r10
movq %r10, (%rsi)
movl %r9d, %r10d
movq -8(%rcx,%r10), %r11
movq %r11, -8(%rsi,%r10)
leaq 8(%rsi), %r10
andq $-8, %r10
subq %r10, %rsi
subq %rsi, %rcx
addl %esi, %r9d
andl $-8, %r9d
cmpl $8, %r9d
jb .L50
andl $-8, %r9d
movl $0, %esi
.L48:
movl %esi, %r11d
movq (%rcx,%r11), %r14
movq %r14, (%r10,%r11)
addl $8, %esi
cmpl %r9d, %esi
jb .L48
.L50:
movq -8(%rdi), %rcx
movq %rcx, 8(%rdx)
addq $32, %rdx
addq $32, %rax
cmpq %rax, %r8
je .L81
.L51:
leaq 16(%rdx), %rsi
movq %rsi, (%rdx)
movq %rax, %rdi
movq -16(%rax), %rcx
cmpq %rcx, %rax
je .L82
movq %rcx, (%rdx)
movq (%rax), %rcx
movq %rcx, 16(%rdx)
jmp .L50
.L81:
movq %rbx, %r14
subq %rbp, %r14
addq %r15, %r14
.L42:
addq $32, %r14
cmpq %r13, %rbx
je .L52
leaq 16(%rbx), %rax
leaq 16(%r13), %rdi
movq %r14, %rdx
jmp .L61
.L70:
movq %r15, %r14
jmp .L42
.L85:
movq -8(%rax), %rsi
addq $1, %rsi
movq %rax, %r11
cmpl $8, %esi
jnb .L54
testb $4, %sil
jne .L83
testl %esi, %esi
je .L60
movzbl (%rax), %r9d
movb %r9b, (%r8)
testb $2, %sil
je .L60
movl %esi, %esi
movzwl -2(%rax,%rsi), %r9d
movw %r9w, -2(%r8,%rsi)
jmp .L60
.L83:
movl (%rax), %r9d
movl %r9d, (%r8)
movl %esi, %esi
movl -4(%rax,%rsi), %r9d
movl %r9d, -4(%r8,%rsi)
jmp .L60
.L54:
movq (%rax), %r9
movq %r9, (%r8)
movl %esi, %r9d
movq -8(%rax,%r9), %r10
movq %r10, -8(%r8,%r9)
leaq 8(%r8), %r10
andq $-8, %r10
subq %r10, %r8
subq %r8, %r11
addl %r8d, %esi
andl $-8, %esi
cmpl $8, %esi
jb .L60
andl $-8, %esi
movl $0, %r8d
movq %rax, 8(%rsp)
.L58:
movl %r8d, %r9d
movq (%r11,%r9), %rax
movq %rax, (%r10,%r9)
addl $8, %r8d
cmpl %esi, %r8d
jb .L58
movq 8(%rsp), %rax
.L60:
movq -8(%rcx), %rcx
movq %rcx, 8(%rdx)
addq $32, %rdx
addq $32, %rax
cmpq %rdi, %rax
je .L84
.L61:
leaq 16(%rdx), %r8
movq %r8, (%rdx)
movq %rax, %rcx
movq -16(%rax), %rsi
cmpq %rax, %rsi
je .L85
movq %rsi, (%rdx)
movq (%rax), %rsi
movq %rsi, 16(%rdx)
jmp .L60
.L84:
subq %rbx, %r13
addq %r13, %r14
.L52:
testq %rbp, %rbp
je .L62
movq 16(%r12), %rsi
subq %rbp, %rsi
movq %rbp, %rdi
call _ZdlPvm@PLT
.L62:
movq %r15, (%r12)
movq %r14, 8(%r12)
movq (%rsp), %rax
salq $5, %rax
addq %r15, %rax
movq %rax, 16(%r12)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
testq %r15, %r15
jne .L64
movq %r14, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L65:
.LEHB1:
call __cxa_rethrow@PLT
.LEHE1:
.L72:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.L64:
movq (%rsp), %rsi
salq $5, %rsi
movq %r15, %rdi
call _ZdlPvm@PLT
jmp .L65
.L40:
movq %rsi, %r14
subq %rbp, %r14
movabsq $288230376151711743, %rax
movq %rax, (%rsp)
.L67:
movq (%rsp), %rdi
salq $5, %rdi
call _Znwm@PLT
.LEHE2:
movq %rax, %r15
.L41:
addq %r15, %r14
leaq 16(%r14), %rax
movq %rax, (%r14)
movq 8(%rsp), %rax
movq (%rax), %rsi
movq %rsi, %rdx
addq 8(%rax), %rdx
movq %r14, %rdi
.LEHB3:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE3:
jmp .L86
.cfi_endproc
.LFE6256:
.globl __gxx_personality_v0
.section .gcc_except_table._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"aG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 4
.LLSDA6256:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT6256-.LLSDATTD6256
.LLSDATTD6256:
.byte 0x1
.uleb128 .LLSDACSE6256-.LLSDACSB6256
.LLSDACSB6256:
.uleb128 .LEHB0-.LFB6256
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB6256
.uleb128 .LEHE1-.LEHB1
.uleb128 .L72-.LFB6256
.uleb128 0
.uleb128 .LEHB2-.LFB6256
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB6256
.uleb128 .LEHE3-.LEHB3
.uleb128 .L71-.LFB6256
.uleb128 0x1
.LLSDACSE6256:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT6256:
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.section .text._ZN9Scheduler7executeEv,"axG",@progbits,_ZN9Scheduler7executeEv,comdat
.align 2
.weak _ZN9Scheduler7executeEv
.type _ZN9Scheduler7executeEv, @function
_ZN9Scheduler7executeEv:
.LFB5321:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5321
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq (%rdi), %rbx
movq 8(%rdi), %r12
cmpq %rbx, %r12
je .L87
leaq 16(%rsp), %r15
leaq 16+_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE(%rip), %r14
leaq _Z4execPKc(%rip), %r13
jmp .L96
.L109:
movq %r14, (%rax)
movq %rbp, 8(%rax)
movq %r13, 16(%rax)
movq %rax, 8(%rsp)
leaq 8(%rsp), %rsi
movq %rsp, %rdi
leaq _ZNSt6thread24_M_thread_deps_never_runEv(%rip), %rdx
.LEHB4:
call _ZNSt6thread15_M_start_threadESt10unique_ptrINS_6_StateESt14default_deleteIS1_EEPFvvE@PLT
.LEHE4:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L89
movq (%rdi), %rax
call *8(%rax)
.L89:
movq %rsp, %rdi
.LEHB5:
call _ZNSt6thread4joinEv@PLT
.LEHE5:
jmp .L107
.L103:
endbr64
movq %rax, %rbx
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L93
movq (%rdi), %rax
call *8(%rax)
.L93:
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L99
call __stack_chk_fail@PLT
.L107:
cmpq $0, (%rsp)
jne .L108
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .L95
movq 32(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L95:
addq $32, %rbx
cmpq %rbx, %r12
je .L87
.L96:
leaq 32(%rsp), %rax
movq %rax, 16(%rsp)
movq (%rbx), %rsi
movq %rsi, %rdx
addq 8(%rbx), %rdx
movq %r15, %rdi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE6:
movq 16(%rsp), %rbp
movq $0, (%rsp)
movl $24, %edi
.LEHB7:
call _Znwm@PLT
.LEHE7:
jmp .L109
.L108:
call _ZSt9terminatev@PLT
.L102:
endbr64
movq %rax, %rbx
cmpq $0, (%rsp)
je .L93
call _ZSt9terminatev@PLT
.L101:
endbr64
movq %rax, %rbx
jmp .L93
.L99:
movq %rbx, %rdi
.LEHB8:
call _Unwind_Resume@PLT
.LEHE8:
.L87:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L110
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5321:
.section .gcc_except_table._ZN9Scheduler7executeEv,"aG",@progbits,_ZN9Scheduler7executeEv,comdat
.LLSDA5321:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5321-.LLSDACSB5321
.LLSDACSB5321:
.uleb128 .LEHB4-.LFB5321
.uleb128 .LEHE4-.LEHB4
.uleb128 .L103-.LFB5321
.uleb128 0
.uleb128 .LEHB5-.LFB5321
.uleb128 .LEHE5-.LEHB5
.uleb128 .L102-.LFB5321
.uleb128 0
.uleb128 .LEHB6-.LFB5321
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB5321
.uleb128 .LEHE7-.LEHB7
.uleb128 .L101-.LFB5321
.uleb128 0
.uleb128 .LEHB8-.LFB5321
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE5321:
.section .text._ZN9Scheduler7executeEv,"axG",@progbits,_ZN9Scheduler7executeEv,comdat
.size _ZN9Scheduler7executeEv, .-_ZN9Scheduler7executeEv
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB6469:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L128
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L114
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L115
jmp .L122
.L128:
leaq .LC5(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L129:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L117
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L121
.L114:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L122:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L115:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L129
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L119
.L117:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L119:
addq %rbp, %r15
testq %r13, %r13
je .L120
movq 16(%rbx), %rsi
subq %r13, %rsi
.L121:
movq %r13, %rdi
call _ZdlPvm@PLT
.L120:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6469:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.text
.globl main
.type main, @function
main:
.LFB5322:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA5322
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
.LEHB9:
call _Z20getDeviceInformationv
.LEHE9:
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movl $0, 64(%rsp)
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $0, 88(%rsp)
movb $0, 96(%rsp)
leaq _ZSt3cin(%rip), %rbp
jmp .L131
.L154:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L152
.LEHB10:
call _ZSt16__throw_bad_castv@PLT
.L148:
endbr64
movq %rax, %rbx
jmp .L144
.L152:
call __stack_chk_fail@PLT
.L134:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L135
.L155:
leaq 112(%rsp), %rdi
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq 80(%rsp), %rsi
movq %rsi, %rdx
addq 88(%rsp), %rdx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE10:
movq 24(%rsp), %rbx
cmpq 32(%rsp), %rbx
je .L136
leaq 16(%rbx), %rax
movq %rax, (%rbx)
movq 112(%rsp), %rsi
movq %rsi, %rdx
addq 120(%rsp), %rdx
movq %rbx, %rdi
.LEHB11:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE11:
addq $32, %rbx
movq %rbx, 24(%rsp)
.L137:
movl $-1, 12(%rsp)
movq 48(%rsp), %rsi
cmpq 56(%rsp), %rsi
je .L138
movl $-1, (%rsi)
addq $4, %rsi
movq %rsi, 48(%rsp)
.L139:
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .L131
movq 128(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L131:
cmpq $1, 88(%rsp)
je .L153
.L141:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L154
cmpb $0, 56(%rbx)
je .L134
movzbl 67(%rbx), %edx
.L135:
movsbl %dl, %edx
leaq 80(%rsp), %rsi
movq %rbp, %rdi
.LEHB12:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
.LEHE12:
jmp .L155
.L136:
leaq 112(%rsp), %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
.LEHB13:
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
jmp .L137
.L138:
leaq 12(%rsp), %rdx
leaq 40(%rsp), %rdi
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.LEHE13:
jmp .L139
.L153:
movq 80(%rsp), %rax
cmpb $32, (%rax)
jne .L141
leaq 16(%rsp), %rdi
.LEHB14:
call _ZN9Scheduler7executeEv
.LEHE14:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L142
movq 56(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L142:
leaq 16(%rsp), %rdi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L156
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L149:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L144:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rdi
movq 56(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L145
call _ZdlPvm@PLT
.L145:
leaq 16(%rsp), %rdi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L146
call __stack_chk_fail@PLT
.L146:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L156:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5322:
.section .gcc_except_table,"a",@progbits
.LLSDA5322:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE5322-.LLSDACSB5322
.LLSDACSB5322:
.uleb128 .LEHB9-.LFB5322
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.uleb128 .LEHB10-.LFB5322
.uleb128 .LEHE10-.LEHB10
.uleb128 .L148-.LFB5322
.uleb128 0
.uleb128 .LEHB11-.LFB5322
.uleb128 .LEHE11-.LEHB11
.uleb128 .L149-.LFB5322
.uleb128 0
.uleb128 .LEHB12-.LFB5322
.uleb128 .LEHE12-.LEHB12
.uleb128 .L148-.LFB5322
.uleb128 0
.uleb128 .LEHB13-.LFB5322
.uleb128 .LEHE13-.LEHB13
.uleb128 .L149-.LFB5322
.uleb128 0
.uleb128 .LEHB14-.LFB5322
.uleb128 .LEHE14-.LEHB14
.uleb128 .L148-.LFB5322
.uleb128 0
.uleb128 .LEHB15-.LFB5322
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.LLSDACSE5322:
.text
.size main, .-main
.weak _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.section .rodata._ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,"aG",@progbits,_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,comdat
.align 32
.type _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, @object
.size _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, 63
_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE:
.string "NSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE"
.weak _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.section .data.rel.ro._ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,"awG",@progbits,_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,comdat
.align 8
.type _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, @object
.size _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, 24
_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.quad _ZTINSt6thread6_StateE
.weak _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.section .data.rel.ro.local._ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,"awG",@progbits,_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,comdat
.align 8
.type _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, @object
.size _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, 40
_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE:
.quad 0
.quad _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED1Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_profiler_api.h>
#include <iostream>
#include <vector>
#include <future>
void getDeviceInformation() {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, 0);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("No CUDA GPU has been detected\n");
}
else {
printf("Device name: %s\n", deviceProp.name);
printf("Total Global Memory: %d\n", deviceProp.regsPerMultiprocessor);
printf("Total shared mem per block: %d\n", deviceProp.sharedMemPerMultiprocessor);
printf("Total const mem size: %d\n", deviceProp.maxThreadsPerMultiProcessor);
}
}
//cudaStream_t streams[NUM_STREAMS];
void exec(const char* s){
system(s);
}
class Scheduler {
std::vector<std::string> programs;
std::vector<int> map;
int i=0;
public:
Scheduler(){
}
void programCall(std::string str) {
//std::cout << str << "\n";
programs.push_back(str);
map.push_back(-1);
}
void schedule(){
}
void execute(){
//cudaProfilerStart();
for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
std::thread t1(exec, f.data());
t1.join();
}
/*for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
t1(exec, f.data());
}*/
//cudaProfilerStop();
}
};
int main(int argc, char **argv) {
getDeviceInformation();
Scheduler s;
std::string line = "";
while(line != " ") {
std::getline (std::cin, line);
//std::cout << line << "\n";
//std::string str = argv[i];//"./hotspot 1024 2 2 ../../data/hotspot/temp_1024 ../../data/hotspot/power_1024 output.out";
s.programCall(line);
// s.schedule();
}
s.execute();
return 0;
} | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <vector>
#include <future>
void getDeviceInformation() {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, 0);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("No CUDA GPU has been detected\n");
}
else {
printf("Device name: %s\n", deviceProp.name);
printf("Total Global Memory: %d\n", deviceProp.regsPerMultiprocessor);
printf("Total shared mem per block: %d\n", deviceProp.sharedMemPerMultiprocessor);
printf("Total const mem size: %d\n", deviceProp.maxThreadsPerMultiProcessor);
}
}
//cudaStream_t streams[NUM_STREAMS];
void exec(const char* s){
system(s);
}
class Scheduler {
std::vector<std::string> programs;
std::vector<int> map;
int i=0;
public:
Scheduler(){
}
void programCall(std::string str) {
//std::cout << str << "\n";
programs.push_back(str);
map.push_back(-1);
}
void schedule(){
}
void execute(){
//cudaProfilerStart();
for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
std::thread t1(exec, f.data());
t1.join();
}
/*for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
t1(exec, f.data());
}*/
//cudaProfilerStop();
}
};
int main(int argc, char **argv) {
getDeviceInformation();
Scheduler s;
std::string line = "";
while(line != " ") {
std::getline (std::cin, line);
//std::cout << line << "\n";
//std::string str = argv[i];//"./hotspot 1024 2 2 ../../data/hotspot/temp_1024 ../../data/hotspot/power_1024 output.out";
s.programCall(line);
// s.schedule();
}
s.execute();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <vector>
#include <future>
void getDeviceInformation() {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, 0);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("No CUDA GPU has been detected\n");
}
else {
printf("Device name: %s\n", deviceProp.name);
printf("Total Global Memory: %d\n", deviceProp.regsPerMultiprocessor);
printf("Total shared mem per block: %d\n", deviceProp.sharedMemPerMultiprocessor);
printf("Total const mem size: %d\n", deviceProp.maxThreadsPerMultiProcessor);
}
}
//cudaStream_t streams[NUM_STREAMS];
void exec(const char* s){
system(s);
}
class Scheduler {
std::vector<std::string> programs;
std::vector<int> map;
int i=0;
public:
Scheduler(){
}
void programCall(std::string str) {
//std::cout << str << "\n";
programs.push_back(str);
map.push_back(-1);
}
void schedule(){
}
void execute(){
//cudaProfilerStart();
for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
std::thread t1(exec, f.data());
t1.join();
}
/*for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
t1(exec, f.data());
}*/
//cudaProfilerStop();
}
};
int main(int argc, char **argv) {
getDeviceInformation();
Scheduler s;
std::string line = "";
while(line != " ") {
std::getline (std::cin, line);
//std::cout << line << "\n";
//std::string str = argv[i];//"./hotspot 1024 2 2 ../../data/hotspot/temp_1024 ../../data/hotspot/power_1024 output.out";
s.programCall(line);
// s.schedule();
}
s.execute();
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <vector>
#include <future>
void getDeviceInformation() {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, 0);
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
printf("No CUDA GPU has been detected\n");
}
else {
printf("Device name: %s\n", deviceProp.name);
printf("Total Global Memory: %d\n", deviceProp.regsPerMultiprocessor);
printf("Total shared mem per block: %d\n", deviceProp.sharedMemPerMultiprocessor);
printf("Total const mem size: %d\n", deviceProp.maxThreadsPerMultiProcessor);
}
}
//cudaStream_t streams[NUM_STREAMS];
void exec(const char* s){
system(s);
}
class Scheduler {
std::vector<std::string> programs;
std::vector<int> map;
int i=0;
public:
Scheduler(){
}
void programCall(std::string str) {
//std::cout << str << "\n";
programs.push_back(str);
map.push_back(-1);
}
void schedule(){
}
void execute(){
//cudaProfilerStart();
for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
std::thread t1(exec, f.data());
t1.join();
}
/*for(auto f : programs){
//std::async(std::launch::async, exec, f.data());
t1(exec, f.data());
}*/
//cudaProfilerStop();
}
};
int main(int argc, char **argv) {
getDeviceInformation();
Scheduler s;
std::string line = "";
while(line != " ") {
std::getline (std::cin, line);
//std::cout << line << "\n";
//std::string str = argv[i];//"./hotspot 1024 2 2 ../../data/hotspot/temp_1024 ../../data/hotspot/power_1024 output.out";
s.programCall(line);
// s.schedule();
}
s.execute();
return 0;
} | .text
.file "main2_bkp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20getDeviceInformationv # -- Begin function _Z20getDeviceInformationv
.p2align 4, 0x90
.type _Z20getDeviceInformationv,@function
_Z20getDeviceInformationv: # @_Z20getDeviceInformationv
.cfi_startproc
# %bb.0:
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
cmpl $9999, 368(%rsp) # imm = 0x270F
jne .LBB0_3
# %bb.1:
cmpl $9999, 372(%rsp) # imm = 0x270F
jne .LBB0_3
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.LBB0_3:
.cfi_def_cfa_offset 1488
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl 656(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 648(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 632(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20getDeviceInformationv, .Lfunc_end0-_Z20getDeviceInformationv
.cfi_endproc
# -- End function
.globl _Z4execPKc # -- Begin function _Z4execPKc
.p2align 4, 0x90
.type _Z4execPKc,@function
_Z4execPKc: # @_Z4execPKc
.cfi_startproc
# %bb.0:
jmp system # TAILCALL
.Lfunc_end1:
.size _Z4execPKc, .Lfunc_end1-_Z4execPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _Z20getDeviceInformationv
xorps %xmm0, %xmm0
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movl $0, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, (%rsp)
movq $0, 8(%rsp)
movb $0, 16(%rsp)
leaq 48(%rsp), %rbp
movq %rsp, %rbx
leaq 64(%rsp), %r14
leaq 32(%rsp), %r15
.p2align 4, 0x90
.LBB2_1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdx
cmpq $1, %rdx
jne .LBB2_3
# %bb.2: # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit
# in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rdi
movl $.L.str.6, %esi
callq bcmp@PLT
testl %eax, %eax
je .LBB2_30
.LBB2_3: # %.critedge
# in Loop: Header=BB2_1 Depth=1
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
movq _ZSt3cin+240(%rax), %r12
testq %r12, %r12
je .LBB2_4
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_1 Depth=1
cmpb $0, 56(%r12)
je .LBB2_8
# %bb.7: # in Loop: Header=BB2_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB2_10
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_1 Depth=1
.Ltmp0:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp1:
# %bb.9: # %.noexc9
# in Loop: Header=BB2_1 Depth=1
movq (%r12), %rax
.Ltmp2:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp3:
.LBB2_10: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB2_1 Depth=1
.Ltmp4:
movsbl %al, %edx
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp5:
# %bb.11: # %_ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
# in Loop: Header=BB2_1 Depth=1
movq %rbp, 32(%rsp)
movq (%rsp), %r13
movq 8(%rsp), %r12
cmpq $16, %r12
jb .LBB2_20
# %bb.12: # in Loop: Header=BB2_1 Depth=1
testq %r12, %r12
js .LBB2_13
# %bb.15: # in Loop: Header=BB2_1 Depth=1
movq %r12, %rdi
incq %rdi
js .LBB2_16
# %bb.18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i12
# in Loop: Header=BB2_1 Depth=1
.Ltmp6:
callq _Znwm
.Ltmp7:
# %bb.19: # %.noexc16
# in Loop: Header=BB2_1 Depth=1
movq %rax, 32(%rsp)
movq %r12, 48(%rsp)
.LBB2_20: # in Loop: Header=BB2_1 Depth=1
testq %r12, %r12
je .LBB2_24
# %bb.21: # in Loop: Header=BB2_1 Depth=1
movq 32(%rsp), %rdi
cmpq $1, %r12
jne .LBB2_23
# %bb.22: # in Loop: Header=BB2_1 Depth=1
movzbl (%r13), %eax
movb %al, (%rdi)
jmp .LBB2_24
.p2align 4, 0x90
.LBB2_23: # in Loop: Header=BB2_1 Depth=1
movq %r13, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB2_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_.exit
# in Loop: Header=BB2_1 Depth=1
movq %r12, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax,%r12)
.Ltmp9:
movq %r14, %rdi
movq %r15, %rsi
callq _ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp10:
# %bb.25: # in Loop: Header=BB2_1 Depth=1
movq 32(%rsp), %rdi
cmpq %rbp, %rdi
je .LBB2_1
# %bb.26: # %.critedge.i.i
# in Loop: Header=BB2_1 Depth=1
callq _ZdlPv
jmp .LBB2_1
.LBB2_30: # %.critedge26
.Ltmp18:
leaq 64(%rsp), %rdi
callq _ZN9Scheduler7executeEv
.Ltmp19:
# %bb.31:
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_33
# %bb.32: # %.critedge.i.i20
callq _ZdlPv
.LBB2_33: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit22
movq 88(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_35
# %bb.34:
callq _ZdlPv
.LBB2_35: # %_ZNSt6vectorIiSaIiEED2Ev.exit.i
movq 64(%rsp), %rbx
movq 72(%rsp), %r14
jmp .LBB2_36
.p2align 4, 0x90
.LBB2_39: # %_ZSt8_DestroyINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEvPT_.exit.i.i.i.i.i
# in Loop: Header=BB2_36 Depth=1
addq $16, %rbx
.LBB2_36: # %_ZNSt6vectorIiSaIiEED2Ev.exit.i
# =>This Inner Loop Header: Depth=1
cmpq %r14, %rbx
je .LBB2_40
# %bb.37: # %.lr.ph.i.i.i.i.i
# in Loop: Header=BB2_36 Depth=1
movq (%rbx), %rdi
addq $16, %rbx
cmpq %rbx, %rdi
je .LBB2_39
# %bb.38: # %.critedge.i.i.i.i.i.i.i.i.i
# in Loop: Header=BB2_36 Depth=1
callq _ZdlPv
jmp .LBB2_39
.LBB2_40: # %_ZSt8_DestroyIPNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_EvT_S7_RSaIT0_E.exit.i.i
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_42
# %bb.41:
callq _ZdlPv
.LBB2_42: # %_ZN9SchedulerD2Ev.exit
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_16: # %.noexc6.i
.cfi_def_cfa_offset 176
.Ltmp12:
callq _ZSt17__throw_bad_allocv
.Ltmp13:
# %bb.17: # %.noexc15
.LBB2_4:
.Ltmp16:
callq _ZSt16__throw_bad_castv
.Ltmp17:
# %bb.5: # %.noexc8
.LBB2_13: # %.noexc.i13
.Ltmp14:
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp15:
# %bb.14: # %.noexc14
.LBB2_28:
.Ltmp11:
movq %rax, %rbx
movq 32(%rsp), %rdi
cmpq %rbp, %rdi
je .LBB2_45
# %bb.29: # %.critedge.i.i17
callq _ZdlPv
jmp .LBB2_45
.LBB2_43: # %.loopexit
.Ltmp8:
jmp .LBB2_44
.LBB2_27: # %.loopexit.split-lp
.Ltmp20:
.LBB2_44: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit19
movq %rax, %rbx
.LBB2_45: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit19
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB2_47
# %bb.46: # %.critedge.i.i23
callq _ZdlPv
.LBB2_47: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit25
leaq 64(%rsp), %rdi
callq _ZN9SchedulerD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp0 # Call between .Ltmp0 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp18 # Call between .Ltmp18 and .Ltmp15
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end2-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,"axG",@progbits,_ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,comdat
.weak _ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
callq _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_
movq 32(%rbx), %r14
cmpq 40(%rbx), %r14
je .LBB3_2
# %bb.1:
movl $-1, (%r14)
addq $4, %r14
movq %r14, 32(%rbx)
jmp .LBB3_11
.LBB3_2:
movq 24(%rbx), %r15
subq %r15, %r14
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r14
je .LBB3_12
# %bb.3: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
movq %r14, %rbp
sarq $2, %rbp
cmpq $1, %rbp
movq %rbp, %rax
adcq $0, %rax
leaq (%rax,%rbp), %r13
movabsq $2305843009213693951, %rcx # imm = 0x1FFFFFFFFFFFFFFF
cmpq %rcx, %r13
cmovaeq %rcx, %r13
addq %rbp, %rax
cmovbq %rcx, %r13
testq %r13, %r13
je .LBB3_4
# %bb.5:
leaq (,%r13,4), %rdi
callq _Znwm
movq %rax, %r12
jmp .LBB3_6
.LBB3_4:
xorl %r12d, %r12d
.LBB3_6: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i.i
movl $-1, (%r12,%rbp,4)
testq %r14, %r14
jle .LBB3_8
# %bb.7:
movq %r12, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB3_8: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i.i
addq %r12, %r14
addq $4, %r14
testq %r15, %r15
je .LBB3_10
# %bb.9:
movq %r15, %rdi
callq _ZdlPv
.LBB3_10: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i.i
movq %r12, 24(%rbx)
movq %r14, 32(%rbx)
leaq (%r12,%r13,4), %rax
movq %rax, 40(%rbx)
.LBB3_11: # %_ZNSt6vectorIiSaIiEE9push_backEOi.exit
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 64
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end3:
.size _ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end3-_ZN9Scheduler11programCallENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
# -- End function
.section .text._ZN9Scheduler7executeEv,"axG",@progbits,_ZN9Scheduler7executeEv,comdat
.weak _ZN9Scheduler7executeEv # -- Begin function _ZN9Scheduler7executeEv
.p2align 4, 0x90
.type _ZN9Scheduler7executeEv,@function
_ZN9Scheduler7executeEv: # @_ZN9Scheduler7executeEv
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rdi), %rbp
movq 8(%rdi), %r14
cmpq %r14, %rbp
je .LBB4_23
# %bb.1: # %.lr.ph
leaq 40(%rsp), %r13
leaq 16(%rsp), %rbx
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_22: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB4_2 Depth=1
addq $32, %rbp
cmpq %r14, %rbp
je .LBB4_23
.LBB4_2: # =>This Inner Loop Header: Depth=1
movq %r13, 24(%rsp)
movq (%rbp), %r12
movq 8(%rbp), %r15
cmpq $16, %r15
jb .LBB4_6
# %bb.3: # in Loop: Header=BB4_2 Depth=1
testq %r15, %r15
js .LBB4_30
# %bb.4: # in Loop: Header=BB4_2 Depth=1
movq %r15, %rdi
incq %rdi
js .LBB4_31
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
# in Loop: Header=BB4_2 Depth=1
callq _Znwm
movq %rax, 24(%rsp)
movq %r15, 40(%rsp)
.LBB4_6: # in Loop: Header=BB4_2 Depth=1
testq %r15, %r15
je .LBB4_10
# %bb.7: # in Loop: Header=BB4_2 Depth=1
movq 24(%rsp), %rdi
cmpq $1, %r15
jne .LBB4_9
# %bb.8: # in Loop: Header=BB4_2 Depth=1
movzbl (%r12), %eax
movb %al, (%rdi)
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_2 Depth=1
movq %r12, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB4_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_.exit
# in Loop: Header=BB4_2 Depth=1
movq %r15, 32(%rsp)
movq 24(%rsp), %rax
movb $0, (%rax,%r15)
movq 24(%rsp), %r15
movq $0, 16(%rsp)
.Ltmp21:
movl $24, %edi
callq _Znwm
.Ltmp22:
# %bb.11: # %.noexc
# in Loop: Header=BB4_2 Depth=1
movq $_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE+16, (%rax)
movq %r15, 8(%rax)
movq $_Z4execPKc, 16(%rax)
movq %rax, 8(%rsp)
.Ltmp24:
movl $_ZNSt6thread24_M_thread_deps_never_runEv, %edx
movq %rbx, %rdi
leaq 8(%rsp), %rsi
callq _ZNSt6thread15_M_start_threadESt10unique_ptrINS_6_StateESt14default_deleteIS1_EEPFvvE
.Ltmp25:
# %bb.12: # in Loop: Header=BB4_2 Depth=1
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_14
# %bb.13: # %_ZNKSt14default_deleteINSt6thread6_StateEEclEPS1_.exit.i.i
# in Loop: Header=BB4_2 Depth=1
movq (%rdi), %rax
callq *8(%rax)
.LBB4_14: # %_ZNSt6threadC2IRFvPKcEJPcEvEEOT_DpOT0_.exit
# in Loop: Header=BB4_2 Depth=1
.Ltmp27:
movq %rbx, %rdi
callq _ZNSt6thread4joinEv
.Ltmp28:
# %bb.15: # in Loop: Header=BB4_2 Depth=1
cmpq $0, 16(%rsp)
jne .LBB4_16
# %bb.20: # %_ZNSt6threadD2Ev.exit
# in Loop: Header=BB4_2 Depth=1
movq 24(%rsp), %rdi
cmpq %r13, %rdi
je .LBB4_22
# %bb.21: # %.critedge.i.i
# in Loop: Header=BB4_2 Depth=1
callq _ZdlPv
jmp .LBB4_22
.LBB4_23: # %._crit_edge
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_31: # %.noexc6.i
.cfi_def_cfa_offset 112
callq _ZSt17__throw_bad_allocv
.LBB4_30: # %.noexc.i
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.LBB4_25:
.Ltmp23:
jmp .LBB4_26
.LBB4_17:
.Ltmp26:
movq %rax, %rbx
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_19
# %bb.18: # %_ZNKSt14default_deleteINSt6thread6_StateEEclEPS1_.exit.i7.i
movq (%rdi), %rax
callq *8(%rax)
.LBB4_19: # %_ZNSt10unique_ptrINSt6thread6_StateESt14default_deleteIS1_EED2Ev.exit8.i
movq $0, 8(%rsp)
jmp .LBB4_27
.LBB4_24:
.Ltmp29:
cmpq $0, 16(%rsp)
jne .LBB4_16
.LBB4_26: # %.body
movq %rax, %rbx
.LBB4_27: # %.body
movq 24(%rsp), %rdi
cmpq %r13, %rdi
je .LBB4_29
# %bb.28: # %.critedge.i.i9
callq _ZdlPv
.LBB4_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit11
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB4_16:
callq _ZSt9terminatev
.Lfunc_end4:
.size _ZN9Scheduler7executeEv, .Lfunc_end4-_ZN9Scheduler7executeEv
.cfi_endproc
.section .gcc_except_table._ZN9Scheduler7executeEv,"aG",@progbits,_ZN9Scheduler7executeEv,comdat
.p2align 2, 0x0
GCC_except_table4:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp21-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin1 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp27-.Ltmp25 # Call between .Ltmp25 and .Ltmp27
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin1 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Lfunc_end4-.Ltmp28 # Call between .Ltmp28 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZN9SchedulerD2Ev,"axG",@progbits,_ZN9SchedulerD2Ev,comdat
.weak _ZN9SchedulerD2Ev # -- Begin function _ZN9SchedulerD2Ev
.p2align 4, 0x90
.type _ZN9SchedulerD2Ev,@function
_ZN9SchedulerD2Ev: # @_ZN9SchedulerD2Ev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq 24(%rdi), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
callq _ZdlPv
.LBB5_2: # %_ZNSt6vectorIiSaIiEED2Ev.exit
movq (%rbx), %r14
movq 8(%rbx), %r15
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_6: # %_ZSt8_DestroyINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEvPT_.exit.i.i.i.i
# in Loop: Header=BB5_3 Depth=1
addq $16, %r14
.LBB5_3: # %_ZNSt6vectorIiSaIiEED2Ev.exit
# =>This Inner Loop Header: Depth=1
cmpq %r15, %r14
je .LBB5_7
# %bb.4: # %.lr.ph.i.i.i.i
# in Loop: Header=BB5_3 Depth=1
movq (%r14), %rdi
addq $16, %r14
cmpq %r14, %rdi
je .LBB5_6
# %bb.5: # %.critedge.i.i.i.i.i.i.i.i
# in Loop: Header=BB5_3 Depth=1
callq _ZdlPv
jmp .LBB5_6
.LBB5_7: # %_ZSt8_DestroyIPNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_EvT_S7_RSaIT0_E.exit.i
movq (%rbx), %rdi
testq %rdi, %rdi
je .LBB5_8
# %bb.9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB5_8: # %_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev.exit
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _ZN9SchedulerD2Ev, .Lfunc_end5-_ZN9SchedulerD2Ev
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end6:
.size __clang_call_terminate, .Lfunc_end6-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_,comdat
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_ # -- Begin function _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_
.p2align 4, 0x90
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_,@function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_: # @_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rdx
movq %rdi, %rbx
movq 8(%rdi), %r14
cmpq 16(%rdi), %r14
je .LBB7_10
# %bb.1:
leaq 16(%r14), %rax
movq %rax, (%r14)
movq (%rdx), %r12
movq 8(%rdx), %r15
cmpq $16, %r15
jb .LBB7_5
# %bb.2:
testq %r15, %r15
js .LBB7_11
# %bb.3:
movq %r15, %rdi
incq %rdi
js .LBB7_12
# %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i.i.i
callq _Znwm
movq %rax, (%r14)
movq %r15, 16(%r14)
.LBB7_5:
testq %r15, %r15
je .LBB7_9
# %bb.6:
movq (%r14), %rdi
cmpq $1, %r15
jne .LBB7_8
# %bb.7:
movzbl (%r12), %eax
movb %al, (%rdi)
jmp .LBB7_9
.LBB7_10:
movq %rbx, %rdi
movq %r14, %rsi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_ # TAILCALL
.LBB7_8:
.cfi_def_cfa_offset 48
movq %r12, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB7_9: # %_ZNSt16allocator_traitsISaINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEE9constructIS5_JRKS5_EEEvRS6_PT_DpOT0_.exit
movq %r15, 8(%r14)
movq (%r14), %rax
movb $0, (%rax,%r15)
addq $32, 8(%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB7_12: # %.noexc6.i.i.i
.cfi_def_cfa_offset 48
callq _ZSt17__throw_bad_allocv
.LBB7_11: # %.noexc.i.i.i
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end7:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_, .Lfunc_end7-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE9push_backERKS5_
.cfi_endproc
# -- End function
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_ # -- Begin function _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.p2align 4, 0x90
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,@function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_: # @_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
movq (%rdi), %rsi
movq 8(%rdi), %r15
movq %r15, %rax
subq %rsi, %rax
movabsq $9223372036854775776, %rcx # imm = 0x7FFFFFFFFFFFFFE0
cmpq %rcx, %rax
je .LBB8_45
# %bb.1: # %_ZNKSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE12_M_check_lenEmPKc.exit
movq %rdx, %r13
movq %rdi, 32(%rsp) # 8-byte Spill
sarq $5, %rax
cmpq $1, %rax
movq %rax, %rcx
adcq $0, %rcx
leaq (%rcx,%rax), %r14
movabsq $288230376151711743, %rdx # imm = 0x3FFFFFFFFFFFFFF
cmpq %rdx, %r14
cmovaeq %rdx, %r14
addq %rax, %rcx
cmovbq %rdx, %r14
movq %r12, %rbp
movq %rsi, 24(%rsp) # 8-byte Spill
subq %rsi, %rbp
sarq $5, %rbp
testq %r14, %r14
je .LBB8_2
# %bb.3:
movq %r14, %rdi
shlq $5, %rdi
callq _Znwm
movq %rax, %rbx
jmp .LBB8_4
.LBB8_2:
xorl %ebx, %ebx
.LBB8_4: # %_ZNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE11_M_allocateEm.exit
shlq $5, %rbp
leaq (%rbx,%rbp), %rax
movq %rax, (%rsp) # 8-byte Spill
leaq (%rbx,%rbp), %rax
addq $16, %rax
movq %rax, 8(%rsp) # 8-byte Spill
movq %rax, (%rbx,%rbp)
movq (%r13), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movq 8(%r13), %r13
cmpq $16, %r13
jb .LBB8_13
# %bb.5:
testq %r13, %r13
js .LBB8_6
# %bb.8:
movq %r13, %rdi
incq %rdi
js .LBB8_9
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i.i.i
.Ltmp30:
callq _Znwm
.Ltmp31:
# %bb.12: # %.noexc27
movq (%rsp), %rcx # 8-byte Reload
movq %rax, (%rcx)
movq 8(%rsp), %rax # 8-byte Reload
movq %r13, (%rax)
.LBB8_13:
testq %r13, %r13
je .LBB8_17
# %bb.14:
movq (%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
cmpq $1, %r13
jne .LBB8_16
# %bb.15:
movq 16(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB8_17
.LBB8_16:
movq 16(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
callq memcpy@PLT
.LBB8_17: # %_ZNSt16allocator_traitsISaINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEE9constructIS5_JRKS5_EEEvRS6_PT_DpOT0_.exit
movq %r13, 8(%rbx,%rbp)
movq (%rsp), %rax # 8-byte Reload
movq (%rax), %rax
movb $0, (%rax,%r13)
movq %rbx, %r13
movq 24(%rsp), %rbp # 8-byte Reload
cmpq %r12, %rbp
je .LBB8_24
# %bb.18: # %.lr.ph.i.i.i.preheader
leaq 16(%rbx), %r13
addq $16, %rbp
jmp .LBB8_19
.p2align 4, 0x90
.LBB8_21: # %.critedge.i.i.i.i.i.i.i
# in Loop: Header=BB8_19 Depth=1
movq %rax, -16(%r13)
movq (%rbp), %rax
movq %rax, (%r13)
.LBB8_22: # %_ZSt19__relocate_object_aINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_SaIS5_EEvPT_PT0_RT1_.exit.i.i.i
# in Loop: Header=BB8_19 Depth=1
movq -8(%rbp), %rax
movq %rax, -8(%r13)
movq %rbp, -16(%rbp)
movq $0, -8(%rbp)
movb $0, (%rbp)
addq $32, %r13
leaq 32(%rbp), %rax
addq $16, %rbp
cmpq %r12, %rbp
movq %rax, %rbp
je .LBB8_23
.LBB8_19: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
movq %r13, -16(%r13)
movq -16(%rbp), %rax
cmpq %rax, %rbp
jne .LBB8_21
# %bb.20: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i.i.i.i.i.i
# in Loop: Header=BB8_19 Depth=1
movq -8(%rbp), %rdx
incq %rdx
movq %r13, %rdi
movq %rbp, %rsi
callq memcpy@PLT
jmp .LBB8_22
.LBB8_23: # %_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE11_S_relocateEPS5_S8_S8_RS6_.exit.loopexit
addq $-16, %r13
movq 24(%rsp), %rbp # 8-byte Reload
.LBB8_24: # %_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE11_S_relocateEPS5_S8_S8_RS6_.exit
cmpq %r12, %r15
je .LBB8_25
# %bb.26: # %.lr.ph.i.i.i29.preheader
addq $48, %r13
addq $16, %r12
jmp .LBB8_27
.p2align 4, 0x90
.LBB8_29: # %.critedge.i.i.i.i.i.i.i32
# in Loop: Header=BB8_27 Depth=1
movq %rax, -16(%r13)
movq (%r12), %rax
movq %rax, (%r13)
.LBB8_30: # %_ZSt19__relocate_object_aINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEES5_SaIS5_EEvPT_PT0_RT1_.exit.i.i.i33
# in Loop: Header=BB8_27 Depth=1
movq -8(%r12), %rax
movq %rax, -8(%r13)
movq %r12, -16(%r12)
movq $0, -8(%r12)
movb $0, (%r12)
addq $32, %r13
leaq 32(%r12), %rax
addq $16, %r12
cmpq %r15, %r12
movq %rax, %r12
je .LBB8_31
.LBB8_27: # %.lr.ph.i.i.i29
# =>This Inner Loop Header: Depth=1
movq %r13, -16(%r13)
movq -16(%r12), %rax
cmpq %rax, %r12
jne .LBB8_29
# %bb.28: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i.i.i.i.i.i36
# in Loop: Header=BB8_27 Depth=1
movq -8(%r12), %rdx
incq %rdx
movq %r13, %rdi
movq %r12, %rsi
callq memcpy@PLT
jmp .LBB8_30
.LBB8_31: # %_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE11_S_relocateEPS5_S8_S8_RS6_.exit37.loopexit
addq $-16, %r13
testq %rbp, %rbp
je .LBB8_34
.LBB8_33:
movq %rbp, %rdi
callq _ZdlPv
.LBB8_34: # %_ZNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE13_M_deallocateEPS5_m.exit
movq 32(%rsp), %rax # 8-byte Reload
movq %rbx, (%rax)
movq %r13, 8(%rax)
shlq $5, %r14
addq %rbx, %r14
movq %r14, 16(%rax)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_25:
.cfi_def_cfa_offset 96
addq $32, %r13
testq %rbp, %rbp
jne .LBB8_33
jmp .LBB8_34
.LBB8_9: # %.noexc6.i.i.i
.Ltmp32:
callq _ZSt17__throw_bad_allocv
.Ltmp33:
# %bb.10: # %.noexc26
.LBB8_45:
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.LBB8_6: # %.noexc.i.i.i
.Ltmp34:
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp35:
# %bb.7: # %.noexc
.LBB8_35:
.Ltmp36:
movq %rax, %rdi
callq __cxa_begin_catch
testq %rbx, %rbx
jne .LBB8_39
# %bb.36:
movq (%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
cmpq 8(%rsp), %rdi # 8-byte Folded Reload
je .LBB8_38
# %bb.37: # %.critedge.i.i.i.i
callq _ZdlPv
.LBB8_38: # %_ZNSt16allocator_traitsISaINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEE7destroyIS5_EEvRS6_PT_.exit
testq %rbx, %rbx
je .LBB8_40
.LBB8_39: # %.critedge
movq %rbx, %rdi
callq _ZdlPv
.LBB8_40: # %_ZNSt12_Vector_baseINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE13_M_deallocateEPS5_m.exit40
.Ltmp37:
callq __cxa_rethrow
.Ltmp38:
# %bb.44:
.LBB8_41:
.Ltmp39:
movq %rax, %rbx
.Ltmp40:
callq __cxa_end_catch
.Ltmp41:
# %bb.42:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB8_43:
.Ltmp42:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end8:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, .Lfunc_end8-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.cfi_endproc
.section .gcc_except_table._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"aG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.p2align 2, 0x0
GCC_except_table8:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Lfunc_begin2-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp30-.Lfunc_begin2 # Call between .Lfunc_begin2 and .Ltmp30
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp31-.Ltmp30 # Call between .Ltmp30 and .Ltmp31
.uleb128 .Ltmp36-.Lfunc_begin2 # jumps to .Ltmp36
.byte 1 # On action: 1
.uleb128 .Ltmp31-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp32-.Ltmp31 # Call between .Ltmp31 and .Ltmp32
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp36-.Lfunc_begin2 # jumps to .Ltmp36
.byte 1 # On action: 1
.uleb128 .Ltmp33-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Ltmp35-.Ltmp34 # Call between .Ltmp34 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin2 # jumps to .Ltmp36
.byte 1 # On action: 1
.uleb128 .Ltmp35-.Lfunc_begin2 # >> Call Site 7 <<
.uleb128 .Ltmp37-.Ltmp35 # Call between .Ltmp35 and .Ltmp37
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin2 # >> Call Site 8 <<
.uleb128 .Ltmp38-.Ltmp37 # Call between .Ltmp37 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin2 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin2 # >> Call Site 9 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin2 # jumps to .Ltmp42
.byte 1 # On action: 1
.uleb128 .Ltmp41-.Lfunc_begin2 # >> Call Site 10 <<
.uleb128 .Lfunc_end8-.Ltmp41 # Call between .Ltmp41 and .Lfunc_end8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6thread24_M_thread_deps_never_runEv,"axG",@progbits,_ZNSt6thread24_M_thread_deps_never_runEv,comdat
.weak _ZNSt6thread24_M_thread_deps_never_runEv # -- Begin function _ZNSt6thread24_M_thread_deps_never_runEv
.p2align 4, 0x90
.type _ZNSt6thread24_M_thread_deps_never_runEv,@function
_ZNSt6thread24_M_thread_deps_never_runEv: # @_ZNSt6thread24_M_thread_deps_never_runEv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end9:
.size _ZNSt6thread24_M_thread_deps_never_runEv, .Lfunc_end9-_ZNSt6thread24_M_thread_deps_never_runEv
.cfi_endproc
# -- End function
.section .text._ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev,"axG",@progbits,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev,comdat
.weak _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev # -- Begin function _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.p2align 4, 0x90
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev,@function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev: # @_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq _ZNSt6thread6_StateD2Ev
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.Lfunc_end10:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev, .Lfunc_end10-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.cfi_endproc
# -- End function
.section .text._ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv,"axG",@progbits,_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv,comdat
.weak _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv # -- Begin function _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.p2align 4, 0x90
.type _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv,@function
_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv: # @_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq 8(%rdi), %rdi
jmpq *16(%rax) # TAILCALL
.Lfunc_end11:
.size _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv, .Lfunc_end11-_ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Device name: %s\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total Global Memory: %d\n"
.size .L.str.2, 32
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total shared mem per block: %d\n"
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total const mem size: %d\n"
.size .L.str.4, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "basic_string::_M_create"
.size .L.str.8, 24
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "vector::_M_realloc_insert"
.size .L.str.9, 26
.type _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,@object # @_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.section .rodata._ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,"aG",@progbits,_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,comdat
.weak _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.p2align 3, 0x0
_ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE:
.quad 0
.quad _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.quad _ZNSt6thread6_StateD2Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEED0Ev
.quad _ZNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEE6_M_runEv
.size _ZTVNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, 40
.type _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,@object # @_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.section .rodata._ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,"aG",@progbits,_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,comdat
.weak _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
_ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE:
.asciz "NSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE"
.size _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, 63
.type _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,@object # @_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.section .rodata._ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,"aG",@progbits,_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE,comdat
.weak _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.p2align 3, 0x0
_ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.quad _ZTINSt6thread6_StateE
.size _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No CUDA GPU has been detected"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z4execPKc
.addrsig_sym __gxx_personality_v0
.addrsig_sym _ZNSt6thread24_M_thread_deps_never_runEv
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt3cin
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTSNSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.addrsig_sym _ZTINSt6thread6_StateE
.addrsig_sym _ZTINSt6thread11_State_implINS_8_InvokerISt5tupleIJPFvPKcEPcEEEEEE
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernelGetPhi3(const int N, double *T, double *q)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N)
{
T[i] = q[i] * q[i] * q[i];
}
} | code for sm_80
Function : _Z13kernelGetPhi3iPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ DMUL R4, R2, R2 ; /* 0x0000000202047228 */
/* 0x004e0c0000000000 */
/*00c0*/ DMUL R4, R2, R4 ; /* 0x0000000402047228 */
/* 0x001e0e0000000000 */
/*00d0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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