system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define Dx 256
extern "C" {
__global__ void advance_src(int nx, int ny, int tn, double *f) {
int tid0 = nx/3 + (ny/2)*nx;
f[tid0] += sin(0.1*tn);
}
__global__ void advance(int nx, int ny, double *c, double *f, double *g) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int i = tid%nx;
int j = tid/nx;
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(g[tid+1] + g[tid-1] + g[tid+nx] + g[tid-nx] - 4*g[tid])
+ 2*g[tid] - f[tid];
}
__global__ void advance_smem(int nx, int ny, double *c, double *f, double *g) {
int tx = threadIdx.x;
int tid = blockIdx.x*blockDim.x + tx;
int i = tid%nx;
int j = tid/nx;
__shared__ double sm[Dx+2];
double *s = &sm[1];
s[tx] = g[tid];
if( tx==0 && i>0 ) s[-1] = g[tid-1];
if( tx==Dx-1 && i<nx-1 ) s[Dx] = g[tid+1];
__syncthreads();
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(s[tx+1] + s[tx-1] + g[tid+nx] + g[tid-nx] - 4*s[tx])
+ 2*s[tx] - f[tid];
}
} | .file "tmpxft_00002d39_00000000-6_core.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11advance_srciiiPdiiiPd
.type _Z34__device_stub__Z11advance_srciiiPdiiiPd, @function
_Z34__device_stub__Z11advance_srciiiPdiiiPd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq advance_src(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11advance_srciiiPdiiiPd, .-_Z34__device_stub__Z11advance_srciiiPdiiiPd
.globl advance_src
.type advance_src, @function
advance_src:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11advance_srciiiPdiiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size advance_src, .-advance_src
.globl _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_
.type _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_, @function
_Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq advance(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_, .-_Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_
.globl advance
.type advance, @function
advance:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size advance, .-advance
.globl _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_
.type _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_, @function
_Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq advance_smem(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_, .-_Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_
.globl advance_smem
.type advance_smem, @function
advance_smem:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size advance_smem, .-advance_smem
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "advance_smem"
.LC1:
.string "advance"
.LC2:
.string "advance_src"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq advance_smem(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq advance(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq advance_src(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define Dx 256
extern "C" {
__global__ void advance_src(int nx, int ny, int tn, double *f) {
int tid0 = nx/3 + (ny/2)*nx;
f[tid0] += sin(0.1*tn);
}
__global__ void advance(int nx, int ny, double *c, double *f, double *g) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int i = tid%nx;
int j = tid/nx;
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(g[tid+1] + g[tid-1] + g[tid+nx] + g[tid-nx] - 4*g[tid])
+ 2*g[tid] - f[tid];
}
__global__ void advance_smem(int nx, int ny, double *c, double *f, double *g) {
int tx = threadIdx.x;
int tid = blockIdx.x*blockDim.x + tx;
int i = tid%nx;
int j = tid/nx;
__shared__ double sm[Dx+2];
double *s = &sm[1];
s[tx] = g[tid];
if( tx==0 && i>0 ) s[-1] = g[tid-1];
if( tx==Dx-1 && i<nx-1 ) s[Dx] = g[tid+1];
__syncthreads();
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(s[tx+1] + s[tx-1] + g[tid+nx] + g[tid-nx] - 4*s[tx])
+ 2*s[tx] - f[tid];
}
} | #include <hip/hip_runtime.h>
#define Dx 256
extern "C" {
__global__ void advance_src(int nx, int ny, int tn, double *f) {
int tid0 = nx/3 + (ny/2)*nx;
f[tid0] += sin(0.1*tn);
}
__global__ void advance(int nx, int ny, double *c, double *f, double *g) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int i = tid%nx;
int j = tid/nx;
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(g[tid+1] + g[tid-1] + g[tid+nx] + g[tid-nx] - 4*g[tid])
+ 2*g[tid] - f[tid];
}
__global__ void advance_smem(int nx, int ny, double *c, double *f, double *g) {
int tx = threadIdx.x;
int tid = blockIdx.x*blockDim.x + tx;
int i = tid%nx;
int j = tid/nx;
__shared__ double sm[Dx+2];
double *s = &sm[1];
s[tx] = g[tid];
if( tx==0 && i>0 ) s[-1] = g[tid-1];
if( tx==Dx-1 && i<nx-1 ) s[Dx] = g[tid+1];
__syncthreads();
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(s[tx+1] + s[tx-1] + g[tid+nx] + g[tid-nx] - 4*s[tx])
+ 2*s[tx] - f[tid];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define Dx 256
extern "C" {
__global__ void advance_src(int nx, int ny, int tn, double *f) {
int tid0 = nx/3 + (ny/2)*nx;
f[tid0] += sin(0.1*tn);
}
__global__ void advance(int nx, int ny, double *c, double *f, double *g) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int i = tid%nx;
int j = tid/nx;
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(g[tid+1] + g[tid-1] + g[tid+nx] + g[tid-nx] - 4*g[tid])
+ 2*g[tid] - f[tid];
}
__global__ void advance_smem(int nx, int ny, double *c, double *f, double *g) {
int tx = threadIdx.x;
int tid = blockIdx.x*blockDim.x + tx;
int i = tid%nx;
int j = tid/nx;
__shared__ double sm[Dx+2];
double *s = &sm[1];
s[tx] = g[tid];
if( tx==0 && i>0 ) s[-1] = g[tid-1];
if( tx==Dx-1 && i<nx-1 ) s[Dx] = g[tid+1];
__syncthreads();
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(s[tx+1] + s[tx-1] + g[tid+nx] + g[tid-nx] - 4*s[tx])
+ 2*s[tx] - f[tid];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected advance_src
.globl advance_src
.p2align 8
.type advance_src,@function
advance_src:
s_load_b32 s2, s[0:1], 0x8
s_mov_b32 s3, 0x3fb99999
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[0:1], s2
s_mov_b32 s2, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[0:1], v[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ngt_f64_e64 s2, 0x41d00000, |v[0:1]|
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_2
v_ldexp_f64 v[2:3], |v[0:1]|, 0xffffff80
v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[0:1]|
v_trig_preop_f64 v[4:5], |v[0:1]|, 0
v_and_b32_e32 v6, 0x7fffffff, v1
v_trig_preop_f64 v[16:17], |v[0:1]|, 2
s_mov_b32 s4, 0
s_mov_b32 s3, 0x3ff921fb
s_mov_b32 s7, 0x3c91a626
s_mov_b32 s6, 0x33145c07
v_dual_cndmask_b32 v3, v6, v3 :: v_dual_cndmask_b32 v2, v0, v2
v_trig_preop_f64 v[6:7], |v[0:1]|, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[8:9], v[4:5], v[2:3]
v_mul_f64 v[22:23], v[16:17], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[10:11], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[4:5], v[2:3], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[6:7], v[6:7], v[2:3], -v[10:11]
v_fma_f64 v[2:3], v[16:17], v[2:3], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[12:13], v[10:11], v[4:5]
v_add_f64 v[14:15], v[12:13], -v[10:11]
v_add_f64 v[20:21], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[12:13], -v[14:15]
v_add_f64 v[4:5], v[4:5], -v[14:15]
v_ldexp_f64 v[14:15], v[20:21], -2
v_add_f64 v[8:9], v[20:21], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_f64 v[10:11], v[10:11], -v[18:19]
v_add_f64 v[18:19], v[22:23], v[6:7]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[8:9], v[12:13], -v[8:9]
v_add_f64 v[4:5], v[4:5], v[10:11]
v_fract_f64_e32 v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], v[4:5]
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f64 v[10:11], v[10:11], 2
v_add_f64 v[14:15], v[8:9], v[12:13]
v_add_f64 v[24:25], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[14:15], v[10:11]
v_add_f64 v[30:31], v[12:13], -v[24:25]
v_add_f64 v[4:5], v[4:5], -v[24:25]
v_add_f64 v[8:9], v[14:15], -v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0, v[20:21]
v_add_f64 v[20:21], v[18:19], -v[22:23]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s5, 0x40100000, 0
v_add_f64 v[28:29], v[18:19], -v[20:21]
v_add_f64 v[10:11], v[10:11], s[4:5]
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[18:19], v[18:19], -v[30:31]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f64 v[20:21], v[22:23], -v[28:29]
v_add_f64 v[26:27], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[18:19]
v_add_f64 v[6:7], v[6:7], v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f64_e32 v26, v[26:27]
v_add_f64 v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[24:25], v26
v_add_f64 v[6:7], v[12:13], -v[8:9]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], -v[24:25]
v_add_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[16:17], v[14:15], v[10:11]
v_add_f64 v[4:5], v[16:17], -v[10:11]
v_cmp_le_f64_e32 vcc_lo, 0.5, v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[14:15], -v[4:5]
s_and_b32 s2, vcc_lo, exec_lo
s_cselect_b32 s5, 0x3ff00000, 0
v_add_co_ci_u32_e64 v6, s2, 0, v26, vcc_lo
s_mov_b32 s2, 0x54442d18
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[4:5], v[16:17], -s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[4:5], v[2:3]
v_mul_f64 v[9:10], v[7:8], s[2:3]
v_add_f64 v[4:5], v[7:8], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[11:12], v[7:8], s[2:3], -v[9:10]
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[7:8], s[6:7], v[11:12]
v_fma_f64 v[4:5], v[2:3], s[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[9:10], v[4:5]
v_add_f64 v[7:8], v[2:3], -v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[7:8]
s_cbranch_execz .LBB0_3
s_branch .LBB0_4
.LBB0_2:
.LBB0_3:
s_mov_b32 s3, 0x3fe45f30
s_mov_b32 s2, 0x6dc9c883
s_mov_b32 s5, 0xbc91a626
v_mul_f64 v[2:3], |v[0:1]|, s[2:3]
s_mov_b32 s3, 0xbff921fb
s_mov_b32 s2, 0x54442d18
s_mov_b32 s4, 0x33145c00
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[6:7], v[2:3]
v_fma_f64 v[2:3], v[6:7], s[2:3], |v[0:1]|
v_mul_f64 v[4:5], v[6:7], s[4:5]
s_mov_b32 s3, 0xb97b839a
s_mov_b32 s2, 0x252049c0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[6:7], s[4:5], v[2:3]
v_add_f64 v[8:9], v[2:3], v[4:5]
s_mov_b32 s5, 0x3c91a626
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_add_f64 v[8:9], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_fma_f64 v[4:5], v[6:7], s[4:5], v[4:5]
v_add_f64 v[2:3], v[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_fma_f64 v[4:5], v[6:7], s[2:3], v[2:3]
v_cvt_i32_f64_e32 v6, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[10:11], v[4:5]
v_add_f64 v[8:9], v[2:3], -v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[8:9]
.LBB0_4:
v_mul_f64 v[7:8], v[2:3], v[2:3]
s_mov_b32 s3, 0xbe5ae600
s_mov_b32 s2, 0xb42fdfa7
s_mov_b32 s5, 0x3de5e0b2
s_mov_b32 s4, 0xf9a43bb8
s_mov_b32 s7, 0x3ec71de3
s_mov_b32 s6, 0x796cde01
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[17:18], v[4:5], 0.5
v_fma_f64 v[9:10], v[7:8], s[4:5], s[2:3]
s_mov_b32 s3, 0x3e21eeb6
s_mov_b32 s2, 0x9037ab78
s_mov_b32 s5, 0xbda907db
s_mov_b32 s4, 0x46cc5e42
v_mul_f64 v[13:14], v[7:8], 0.5
v_fma_f64 v[11:12], v[7:8], s[4:5], s[2:3]
s_mov_b32 s3, 0xbe927e4f
s_mov_b32 s2, 0xa17f65f6
s_mov_b32 s5, 0xbf2a01a0
s_mov_b32 s4, 0x19e83e5c
v_mul_f64 v[19:20], v[2:3], -v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[6:7]
v_add_f64 v[15:16], -v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0x3efa01a0
s_mov_b32 s2, 0x19f4ec90
v_fma_f64 v[9:10], v[7:8], v[9:10], s[4:5]
s_mov_b32 s5, 0x3f811111
s_mov_b32 s4, 0x11110bb3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], -v[15:16], 1.0
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0xbf56c16c
s_mov_b32 s2, 0x16c16967
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[7:8], v[9:10], s[4:5]
s_load_b64 s[4:5], s[0:1], 0x10
v_add_f64 v[13:14], v[21:22], -v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0x3fa55555
s_mov_b32 s2, 0x55555555
v_fma_f64 v[9:10], v[19:20], v[9:10], v[17:18]
v_mul_f64 v[17:18], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f64 v[13:14], v[2:3], -v[4:5], v[13:14]
v_fma_f64 v[11:12], v[7:8], v[11:12], s[2:3]
s_mov_b32 s3, 0xbfc55555
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[7:8], v[9:10], -v[4:5]
v_fma_f64 v[7:8], v[17:18], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f64 v[4:5], v[19:20], s[2:3], v[4:5]
s_load_b64 s[2:3], s[0:1], 0x0
v_cmp_class_f64_e64 s0, v[0:1], 0x1f8
v_lshlrev_b32_e32 v0, 30, v6
v_add_f64 v[7:8], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v1
v_and_b32_e32 v0, 0x80000000, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s1, s3, 31
s_mul_hi_i32 s6, s2, 0x55555556
s_add_i32 s1, s3, s1
s_lshr_b32 s3, s6, 31
s_ashr_i32 s1, s1, 1
s_add_i32 s6, s6, s3
s_mul_i32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s1, s6
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 3
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b64 s[4:5], s[2:3], 0x0
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_and_b32_e32 v4, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_dual_cndmask_b32 v1, v8, v3 :: v_dual_cndmask_b32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v1, v0
v_cndmask_b32_e64 v0, 0, v2, s0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v1, 0x7ff80000, v1, s0
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], v[0:1]
global_store_b64 v2, v[0:1], s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel advance_src
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size advance_src, .Lfunc_end0-advance_src
.section .AMDGPU.csdata,"",@progbits
.text
.protected advance
.globl advance
.p2align 8
.type advance,@function
advance:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s6, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_add_i32 s2, s6, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
s_add_i32 s3, s7, -1
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v0
v_cmp_lt_i32_e64 s3, 0, v0
v_cmp_lt_i32_e64 s4, 0, v2
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v10, s6, v1
v_subrev_nc_u32_e32 v0, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[1:2]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
s_clause 0x1
global_load_b128 v[2:5], v[8:9], off
global_load_b64 v[8:9], v[8:9], off offset:-8
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b64 v[10:11], v[10:11], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x8
global_load_b64 v[0:1], v[0:1], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[6:7], off
s_waitcnt vmcnt(4)
v_add_f64 v[4:5], v[4:5], v[8:9]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[10:11]
s_waitcnt vmcnt(2)
v_add_f64 v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[2:3], -4.0, v[0:1]
s_waitcnt vmcnt(1)
v_mul_f64 v[0:1], v[12:13], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[2:3], 2.0, v[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], -v[14:15]
global_store_b64 v[6:7], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel advance
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size advance, .Lfunc_end1-advance
.section .AMDGPU.csdata,"",@progbits
.text
.protected advance_smem
.globl advance_smem
.p2align 8
.type advance_smem,@function
advance_smem:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_ashr_i32 s2, s6, 31
s_add_i32 s3, s6, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s2
v_cvt_f32_u32_e32 v5, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v7, 31, v1
s_sub_i32 s7, 0, s3
v_rcp_iflag_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v10, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_xor_b32_e32 v10, v10, v7
v_xor_b32_e32 v7, s2, v7
global_load_b64 v[8:9], v[3:4], off
v_cmp_eq_u32_e64 s2, 0, v0
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s7, v5
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v5, s3
v_sub_nc_u32_e32 v6, v10, v6
v_add_nc_u32_e32 v10, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s3, v6
v_cmp_le_u32_e32 vcc_lo, s3, v6
v_dual_cndmask_b32 v6, v6, v11 :: v_dual_cndmask_b32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v6
v_add_nc_u32_e32 v10, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v10, vcc_lo
v_xor_b32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v5, v7
v_mul_lo_u32 v5, v6, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v1, v5
v_lshlrev_b32_e32 v5, 3, v0
v_cmp_lt_i32_e32 vcc_lo, 0, v7
s_and_b32 s3, s2, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[8:9] offset:8
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB2_2
global_load_b64 v[8:9], v[3:4], off offset:-8
v_mov_b32_e32 v10, 0
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[8:9]
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s6, -1
v_cmp_eq_u32_e64 s3, 0xff, v0
v_cmp_gt_i32_e64 s2, s2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, s3, s2
s_and_saveexec_b32 s3, s7
s_cbranch_execz .LBB2_4
global_load_b64 v[3:4], v[3:4], off offset:8
v_mov_b32_e32 v0, 0
s_waitcnt vmcnt(0)
ds_store_b64 v0, v[3:4] offset:2056
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB2_7
s_load_b32 s3, s[0:1], 0x4
v_cmp_lt_i32_e32 vcc_lo, 0, v6
s_and_b32 s2, s2, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s3, v6
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB2_7
v_add_nc_u32_e32 v3, s6, v1
s_load_b128 s[0:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[6:7], v[3:4], off
v_subrev_nc_u32_e32 v3, s6, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
global_load_b64 v[8:9], v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[10:11], v[2:3], off
v_add_nc_u32_e32 v0, 8, v5
global_load_b64 v[14:15], v[12:13], off
v_add_nc_u32_e32 v4, -8, v0
ds_load_2addr_b64 v[0:3], v0 offset1:1
ds_load_b64 v[4:5], v4
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(2)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
s_waitcnt vmcnt(1)
v_mul_f64 v[2:3], v[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], 2.0, v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], -v[14:15]
global_store_b64 v[12:13], v[0:1], off
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel advance_smem
.amdhsa_group_segment_fixed_size 2064
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size advance_smem, .Lfunc_end2-advance_smem
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: advance_src
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: advance_src.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: advance
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: advance.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2064
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: advance_smem
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: advance_smem.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define Dx 256
extern "C" {
__global__ void advance_src(int nx, int ny, int tn, double *f) {
int tid0 = nx/3 + (ny/2)*nx;
f[tid0] += sin(0.1*tn);
}
__global__ void advance(int nx, int ny, double *c, double *f, double *g) {
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int i = tid%nx;
int j = tid/nx;
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(g[tid+1] + g[tid-1] + g[tid+nx] + g[tid-nx] - 4*g[tid])
+ 2*g[tid] - f[tid];
}
__global__ void advance_smem(int nx, int ny, double *c, double *f, double *g) {
int tx = threadIdx.x;
int tid = blockIdx.x*blockDim.x + tx;
int i = tid%nx;
int j = tid/nx;
__shared__ double sm[Dx+2];
double *s = &sm[1];
s[tx] = g[tid];
if( tx==0 && i>0 ) s[-1] = g[tid-1];
if( tx==Dx-1 && i<nx-1 ) s[Dx] = g[tid+1];
__syncthreads();
if( i>0 && i<nx-1 && j>0 && j<ny-1 )
f[tid] = c[tid]*(s[tx+1] + s[tx-1] + g[tid+nx] + g[tid-nx] - 4*s[tx])
+ 2*s[tx] - f[tid];
}
} | .text
.file "core.hip"
.globl __device_stub__advance_src # -- Begin function __device_stub__advance_src
.p2align 4, 0x90
.type __device_stub__advance_src,@function
__device_stub__advance_src: # @__device_stub__advance_src
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $advance_src, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__advance_src, .Lfunc_end0-__device_stub__advance_src
.cfi_endproc
# -- End function
.globl __device_stub__advance # -- Begin function __device_stub__advance
.p2align 4, 0x90
.type __device_stub__advance,@function
__device_stub__advance: # @__device_stub__advance
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $advance, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__advance, .Lfunc_end1-__device_stub__advance
.cfi_endproc
# -- End function
.globl __device_stub__advance_smem # -- Begin function __device_stub__advance_smem
.p2align 4, 0x90
.type __device_stub__advance_smem,@function
__device_stub__advance_smem: # @__device_stub__advance_smem
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $advance_smem, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__advance_smem, .Lfunc_end2-__device_stub__advance_smem
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $advance_src, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $advance, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $advance_smem, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type advance_src,@object # @advance_src
.section .rodata,"a",@progbits
.globl advance_src
.p2align 3, 0x0
advance_src:
.quad __device_stub__advance_src
.size advance_src, 8
.type advance,@object # @advance
.globl advance
.p2align 3, 0x0
advance:
.quad __device_stub__advance
.size advance, 8
.type advance_smem,@object # @advance_smem
.globl advance_smem
.p2align 3, 0x0
advance_smem:
.quad __device_stub__advance_smem
.size advance_smem, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "advance_src"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "advance"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "advance_smem"
.size .L__unnamed_3, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__advance_src
.addrsig_sym __device_stub__advance
.addrsig_sym __device_stub__advance_smem
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym advance_src
.addrsig_sym advance
.addrsig_sym advance_smem
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00002d39_00000000-6_core.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11advance_srciiiPdiiiPd
.type _Z34__device_stub__Z11advance_srciiiPdiiiPd, @function
_Z34__device_stub__Z11advance_srciiiPdiiiPd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq advance_src(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z11advance_srciiiPdiiiPd, .-_Z34__device_stub__Z11advance_srciiiPdiiiPd
.globl advance_src
.type advance_src, @function
advance_src:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11advance_srciiiPdiiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size advance_src, .-advance_src
.globl _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_
.type _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_, @function
_Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq advance(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_, .-_Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_
.globl advance
.type advance, @function
advance:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7advanceiiPdS_S_iiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size advance, .-advance
.globl _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_
.type _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_, @function
_Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq advance_smem(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_, .-_Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_
.globl advance_smem
.type advance_smem, @function
advance_smem:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12advance_smemiiPdS_S_iiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size advance_smem, .-advance_smem
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "advance_smem"
.LC1:
.string "advance"
.LC2:
.string "advance_src"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq advance_smem(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq advance(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq advance_src(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "core.hip"
.globl __device_stub__advance_src # -- Begin function __device_stub__advance_src
.p2align 4, 0x90
.type __device_stub__advance_src,@function
__device_stub__advance_src: # @__device_stub__advance_src
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $advance_src, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__advance_src, .Lfunc_end0-__device_stub__advance_src
.cfi_endproc
# -- End function
.globl __device_stub__advance # -- Begin function __device_stub__advance
.p2align 4, 0x90
.type __device_stub__advance,@function
__device_stub__advance: # @__device_stub__advance
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $advance, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__advance, .Lfunc_end1-__device_stub__advance
.cfi_endproc
# -- End function
.globl __device_stub__advance_smem # -- Begin function __device_stub__advance_smem
.p2align 4, 0x90
.type __device_stub__advance_smem,@function
__device_stub__advance_smem: # @__device_stub__advance_smem
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $advance_smem, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size __device_stub__advance_smem, .Lfunc_end2-__device_stub__advance_smem
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $advance_src, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $advance, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $advance_smem, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type advance_src,@object # @advance_src
.section .rodata,"a",@progbits
.globl advance_src
.p2align 3, 0x0
advance_src:
.quad __device_stub__advance_src
.size advance_src, 8
.type advance,@object # @advance
.globl advance
.p2align 3, 0x0
advance:
.quad __device_stub__advance
.size advance, 8
.type advance_smem,@object # @advance_smem
.globl advance_smem
.p2align 3, 0x0
advance_smem:
.quad __device_stub__advance_smem
.size advance_smem, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "advance_src"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "advance"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "advance_smem"
.size .L__unnamed_3, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__advance_src
.addrsig_sym __device_stub__advance
.addrsig_sym __device_stub__advance_smem
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym advance_src
.addrsig_sym advance
.addrsig_sym advance_smem
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // P2P Test by Greg Gutmann
// https://codingbyexample.com/2020/09/14/p2p-memcpy-with-nvlink/
#include "stdio.h"
#include "stdint.h"
int main()
{
// GPUs
int gpuid_0 = 0;
int gpuid_1 = 1;
// Memory Copy Size
uint32_t size = pow(2, 26); // 2^26 = 67MB
// Allocate Memory
uint32_t* dev_0;
cudaSetDevice(gpuid_0);
cudaMalloc((void**)&dev_0, size);
uint32_t* dev_1;
cudaSetDevice(gpuid_1);
cudaMalloc((void**)&dev_1, size);
//Check for peer access between participating GPUs:
int can_access_peer_0_1;
int can_access_peer_1_0;
cudaDeviceCanAccessPeer(&can_access_peer_0_1, gpuid_0, gpuid_1);
cudaDeviceCanAccessPeer(&can_access_peer_1_0, gpuid_1, gpuid_0);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_0, gpuid_1, can_access_peer_0_1);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_1, gpuid_0, can_access_peer_1_0);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Enable P2P Access
cudaSetDevice(gpuid_0);
cudaDeviceEnablePeerAccess(gpuid_1, 0);
cudaSetDevice(gpuid_1);
cudaDeviceEnablePeerAccess(gpuid_0, 0);
}
// Init Timing Data
uint32_t repeat = 10;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Init Stream
cudaStream_t stream;
cudaStreamCreateWithFlags(&stream, cudaStreamNonBlocking);
// ~~ Start Test ~~
cudaEventRecord(start, stream);
//Do a P2P memcpy
for (int i = 0; i < repeat; ++i) {
cudaMemcpyAsync(dev_0, dev_1, size, cudaMemcpyDeviceToDevice, stream);
}
cudaEventRecord(stop, stream);
cudaStreamSynchronize(stream);
// ~~ End of Test ~~
// Check Timing & Performance
float time_ms;
cudaEventElapsedTime(&time_ms, start, stop);
double time_s = time_ms / 1e3;
double gb = size * repeat / (double)1e9;
double bandwidth = gb / time_s;
printf("Seconds: %f\n", time_s);
printf("Unidirectional Bandwidth: %f (GB/s)\n", bandwidth);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Shutdown P2P Settings
cudaSetDevice(gpuid_0);
cudaDeviceDisablePeerAccess(gpuid_1);
cudaSetDevice(gpuid_1);
cudaDeviceDisablePeerAccess(gpuid_0);
}
// Clean Up
cudaFree(dev_0);
cudaFree(dev_1);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaStreamDestroy(stream);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // P2P Test by Greg Gutmann
// https://codingbyexample.com/2020/09/14/p2p-memcpy-with-nvlink/
#include "stdio.h"
#include "stdint.h"
int main()
{
// GPUs
int gpuid_0 = 0;
int gpuid_1 = 1;
// Memory Copy Size
uint32_t size = pow(2, 26); // 2^26 = 67MB
// Allocate Memory
uint32_t* dev_0;
cudaSetDevice(gpuid_0);
cudaMalloc((void**)&dev_0, size);
uint32_t* dev_1;
cudaSetDevice(gpuid_1);
cudaMalloc((void**)&dev_1, size);
//Check for peer access between participating GPUs:
int can_access_peer_0_1;
int can_access_peer_1_0;
cudaDeviceCanAccessPeer(&can_access_peer_0_1, gpuid_0, gpuid_1);
cudaDeviceCanAccessPeer(&can_access_peer_1_0, gpuid_1, gpuid_0);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_0, gpuid_1, can_access_peer_0_1);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_1, gpuid_0, can_access_peer_1_0);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Enable P2P Access
cudaSetDevice(gpuid_0);
cudaDeviceEnablePeerAccess(gpuid_1, 0);
cudaSetDevice(gpuid_1);
cudaDeviceEnablePeerAccess(gpuid_0, 0);
}
// Init Timing Data
uint32_t repeat = 10;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Init Stream
cudaStream_t stream;
cudaStreamCreateWithFlags(&stream, cudaStreamNonBlocking);
// ~~ Start Test ~~
cudaEventRecord(start, stream);
//Do a P2P memcpy
for (int i = 0; i < repeat; ++i) {
cudaMemcpyAsync(dev_0, dev_1, size, cudaMemcpyDeviceToDevice, stream);
}
cudaEventRecord(stop, stream);
cudaStreamSynchronize(stream);
// ~~ End of Test ~~
// Check Timing & Performance
float time_ms;
cudaEventElapsedTime(&time_ms, start, stop);
double time_s = time_ms / 1e3;
double gb = size * repeat / (double)1e9;
double bandwidth = gb / time_s;
printf("Seconds: %f\n", time_s);
printf("Unidirectional Bandwidth: %f (GB/s)\n", bandwidth);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Shutdown P2P Settings
cudaSetDevice(gpuid_0);
cudaDeviceDisablePeerAccess(gpuid_1);
cudaSetDevice(gpuid_1);
cudaDeviceDisablePeerAccess(gpuid_0);
}
// Clean Up
cudaFree(dev_0);
cudaFree(dev_1);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaStreamDestroy(stream);
} | .file "tmpxft_00025b3c_00000000-6_memcpy_with_nvlink.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaDeviceCanAccessPeer(%d->%d): %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Seconds: %f\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Unidirectional Bandwidth: %f (GB/s)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rdi
movl $1, %edx
movl $0, %esi
call cudaDeviceCanAccessPeer@PLT
leaq 8(%rsp), %rdi
movl $0, %edx
movl $1, %esi
call cudaDeviceCanAccessPeer@PLT
movl 4(%rsp), %r8d
movl $1, %ecx
movl $0, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %r8d
movl $0, %ecx
movl $1, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
je .L4
cmpl $0, 8(%rsp)
jne .L10
.L4:
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaStreamCreateWithFlags@PLT
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, %ebx
.L5:
movq 48(%rsp), %r8
movl $3, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpyAsync@PLT
subl $1, %ebx
jne .L5
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaStreamSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
divsd .LC1(%rip), %xmm0
movsd .LC2(%rip), %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
je .L6
cmpl $0, 8(%rsp)
jne .L11
.L6:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl $0, %edi
call cudaSetDevice@PLT
movl $0, %esi
movl $1, %edi
call cudaDeviceEnablePeerAccess@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %esi
movl $0, %edi
call cudaDeviceEnablePeerAccess@PLT
jmp .L4
.L11:
movl $0, %edi
call cudaSetDevice@PLT
movl $1, %edi
call cudaDeviceDisablePeerAccess@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %edi
call cudaDeviceDisablePeerAccess@PLT
jmp .L6
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long -500134854
.long 1072003470
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // P2P Test by Greg Gutmann
// https://codingbyexample.com/2020/09/14/p2p-memcpy-with-nvlink/
#include "stdio.h"
#include "stdint.h"
int main()
{
// GPUs
int gpuid_0 = 0;
int gpuid_1 = 1;
// Memory Copy Size
uint32_t size = pow(2, 26); // 2^26 = 67MB
// Allocate Memory
uint32_t* dev_0;
cudaSetDevice(gpuid_0);
cudaMalloc((void**)&dev_0, size);
uint32_t* dev_1;
cudaSetDevice(gpuid_1);
cudaMalloc((void**)&dev_1, size);
//Check for peer access between participating GPUs:
int can_access_peer_0_1;
int can_access_peer_1_0;
cudaDeviceCanAccessPeer(&can_access_peer_0_1, gpuid_0, gpuid_1);
cudaDeviceCanAccessPeer(&can_access_peer_1_0, gpuid_1, gpuid_0);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_0, gpuid_1, can_access_peer_0_1);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_1, gpuid_0, can_access_peer_1_0);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Enable P2P Access
cudaSetDevice(gpuid_0);
cudaDeviceEnablePeerAccess(gpuid_1, 0);
cudaSetDevice(gpuid_1);
cudaDeviceEnablePeerAccess(gpuid_0, 0);
}
// Init Timing Data
uint32_t repeat = 10;
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Init Stream
cudaStream_t stream;
cudaStreamCreateWithFlags(&stream, cudaStreamNonBlocking);
// ~~ Start Test ~~
cudaEventRecord(start, stream);
//Do a P2P memcpy
for (int i = 0; i < repeat; ++i) {
cudaMemcpyAsync(dev_0, dev_1, size, cudaMemcpyDeviceToDevice, stream);
}
cudaEventRecord(stop, stream);
cudaStreamSynchronize(stream);
// ~~ End of Test ~~
// Check Timing & Performance
float time_ms;
cudaEventElapsedTime(&time_ms, start, stop);
double time_s = time_ms / 1e3;
double gb = size * repeat / (double)1e9;
double bandwidth = gb / time_s;
printf("Seconds: %f\n", time_s);
printf("Unidirectional Bandwidth: %f (GB/s)\n", bandwidth);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Shutdown P2P Settings
cudaSetDevice(gpuid_0);
cudaDeviceDisablePeerAccess(gpuid_1);
cudaSetDevice(gpuid_1);
cudaDeviceDisablePeerAccess(gpuid_0);
}
// Clean Up
cudaFree(dev_0);
cudaFree(dev_1);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaStreamDestroy(stream);
} | // P2P Test by Greg Gutmann
// https://codingbyexample.com/2020/09/14/p2p-memcpy-with-nvlink/
#include <hip/hip_runtime.h>
#include "stdio.h"
#include "stdint.h"
int main()
{
// GPUs
int gpuid_0 = 0;
int gpuid_1 = 1;
// Memory Copy Size
uint32_t size = pow(2, 26); // 2^26 = 67MB
// Allocate Memory
uint32_t* dev_0;
hipSetDevice(gpuid_0);
hipMalloc((void**)&dev_0, size);
uint32_t* dev_1;
hipSetDevice(gpuid_1);
hipMalloc((void**)&dev_1, size);
//Check for peer access between participating GPUs:
int can_access_peer_0_1;
int can_access_peer_1_0;
hipDeviceCanAccessPeer(&can_access_peer_0_1, gpuid_0, gpuid_1);
hipDeviceCanAccessPeer(&can_access_peer_1_0, gpuid_1, gpuid_0);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_0, gpuid_1, can_access_peer_0_1);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_1, gpuid_0, can_access_peer_1_0);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Enable P2P Access
hipSetDevice(gpuid_0);
hipDeviceEnablePeerAccess(gpuid_1, 0);
hipSetDevice(gpuid_1);
hipDeviceEnablePeerAccess(gpuid_0, 0);
}
// Init Timing Data
uint32_t repeat = 10;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Init Stream
hipStream_t stream;
hipStreamCreateWithFlags(&stream, hipStreamNonBlocking);
// ~~ Start Test ~~
hipEventRecord(start, stream);
//Do a P2P memcpy
for (int i = 0; i < repeat; ++i) {
hipMemcpyAsync(dev_0, dev_1, size, hipMemcpyDeviceToDevice, stream);
}
hipEventRecord(stop, stream);
hipStreamSynchronize(stream);
// ~~ End of Test ~~
// Check Timing & Performance
float time_ms;
hipEventElapsedTime(&time_ms, start, stop);
double time_s = time_ms / 1e3;
double gb = size * repeat / (double)1e9;
double bandwidth = gb / time_s;
printf("Seconds: %f\n", time_s);
printf("Unidirectional Bandwidth: %f (GB/s)\n", bandwidth);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Shutdown P2P Settings
hipSetDevice(gpuid_0);
hipDeviceDisablePeerAccess(gpuid_1);
hipSetDevice(gpuid_1);
hipDeviceDisablePeerAccess(gpuid_0);
}
// Clean Up
hipFree(dev_0);
hipFree(dev_1);
hipEventDestroy(start);
hipEventDestroy(stop);
hipStreamDestroy(stream);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // P2P Test by Greg Gutmann
// https://codingbyexample.com/2020/09/14/p2p-memcpy-with-nvlink/
#include <hip/hip_runtime.h>
#include "stdio.h"
#include "stdint.h"
int main()
{
// GPUs
int gpuid_0 = 0;
int gpuid_1 = 1;
// Memory Copy Size
uint32_t size = pow(2, 26); // 2^26 = 67MB
// Allocate Memory
uint32_t* dev_0;
hipSetDevice(gpuid_0);
hipMalloc((void**)&dev_0, size);
uint32_t* dev_1;
hipSetDevice(gpuid_1);
hipMalloc((void**)&dev_1, size);
//Check for peer access between participating GPUs:
int can_access_peer_0_1;
int can_access_peer_1_0;
hipDeviceCanAccessPeer(&can_access_peer_0_1, gpuid_0, gpuid_1);
hipDeviceCanAccessPeer(&can_access_peer_1_0, gpuid_1, gpuid_0);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_0, gpuid_1, can_access_peer_0_1);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_1, gpuid_0, can_access_peer_1_0);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Enable P2P Access
hipSetDevice(gpuid_0);
hipDeviceEnablePeerAccess(gpuid_1, 0);
hipSetDevice(gpuid_1);
hipDeviceEnablePeerAccess(gpuid_0, 0);
}
// Init Timing Data
uint32_t repeat = 10;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Init Stream
hipStream_t stream;
hipStreamCreateWithFlags(&stream, hipStreamNonBlocking);
// ~~ Start Test ~~
hipEventRecord(start, stream);
//Do a P2P memcpy
for (int i = 0; i < repeat; ++i) {
hipMemcpyAsync(dev_0, dev_1, size, hipMemcpyDeviceToDevice, stream);
}
hipEventRecord(stop, stream);
hipStreamSynchronize(stream);
// ~~ End of Test ~~
// Check Timing & Performance
float time_ms;
hipEventElapsedTime(&time_ms, start, stop);
double time_s = time_ms / 1e3;
double gb = size * repeat / (double)1e9;
double bandwidth = gb / time_s;
printf("Seconds: %f\n", time_s);
printf("Unidirectional Bandwidth: %f (GB/s)\n", bandwidth);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Shutdown P2P Settings
hipSetDevice(gpuid_0);
hipDeviceDisablePeerAccess(gpuid_1);
hipSetDevice(gpuid_1);
hipDeviceDisablePeerAccess(gpuid_0);
}
// Clean Up
hipFree(dev_0);
hipFree(dev_1);
hipEventDestroy(start);
hipEventDestroy(stop);
hipStreamDestroy(stream);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // P2P Test by Greg Gutmann
// https://codingbyexample.com/2020/09/14/p2p-memcpy-with-nvlink/
#include <hip/hip_runtime.h>
#include "stdio.h"
#include "stdint.h"
int main()
{
// GPUs
int gpuid_0 = 0;
int gpuid_1 = 1;
// Memory Copy Size
uint32_t size = pow(2, 26); // 2^26 = 67MB
// Allocate Memory
uint32_t* dev_0;
hipSetDevice(gpuid_0);
hipMalloc((void**)&dev_0, size);
uint32_t* dev_1;
hipSetDevice(gpuid_1);
hipMalloc((void**)&dev_1, size);
//Check for peer access between participating GPUs:
int can_access_peer_0_1;
int can_access_peer_1_0;
hipDeviceCanAccessPeer(&can_access_peer_0_1, gpuid_0, gpuid_1);
hipDeviceCanAccessPeer(&can_access_peer_1_0, gpuid_1, gpuid_0);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_0, gpuid_1, can_access_peer_0_1);
printf("cudaDeviceCanAccessPeer(%d->%d): %d\n", gpuid_1, gpuid_0, can_access_peer_1_0);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Enable P2P Access
hipSetDevice(gpuid_0);
hipDeviceEnablePeerAccess(gpuid_1, 0);
hipSetDevice(gpuid_1);
hipDeviceEnablePeerAccess(gpuid_0, 0);
}
// Init Timing Data
uint32_t repeat = 10;
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Init Stream
hipStream_t stream;
hipStreamCreateWithFlags(&stream, hipStreamNonBlocking);
// ~~ Start Test ~~
hipEventRecord(start, stream);
//Do a P2P memcpy
for (int i = 0; i < repeat; ++i) {
hipMemcpyAsync(dev_0, dev_1, size, hipMemcpyDeviceToDevice, stream);
}
hipEventRecord(stop, stream);
hipStreamSynchronize(stream);
// ~~ End of Test ~~
// Check Timing & Performance
float time_ms;
hipEventElapsedTime(&time_ms, start, stop);
double time_s = time_ms / 1e3;
double gb = size * repeat / (double)1e9;
double bandwidth = gb / time_s;
printf("Seconds: %f\n", time_s);
printf("Unidirectional Bandwidth: %f (GB/s)\n", bandwidth);
if (can_access_peer_0_1 && can_access_peer_1_0) {
// Shutdown P2P Settings
hipSetDevice(gpuid_0);
hipDeviceDisablePeerAccess(gpuid_1);
hipSetDevice(gpuid_1);
hipDeviceDisablePeerAccess(gpuid_0);
}
// Clean Up
hipFree(dev_0);
hipFree(dev_1);
hipEventDestroy(start);
hipEventDestroy(stop);
hipStreamDestroy(stream);
} | .text
.file "memcpy_with_nvlink.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x408f400000000000 # double 1000
.LCPI0_1:
.quad 0x3fe5798ee2308c3a # double 0.67108864000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
leaq 48(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movl $1, %edi
callq hipSetDevice
leaq 40(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 4(%rsp), %rdi
xorl %esi, %esi
movl $1, %edx
callq hipDeviceCanAccessPeer
movq %rsp, %rdi
movl $1, %esi
xorl %edx, %edx
callq hipDeviceCanAccessPeer
movl 4(%rsp), %ecx
movl $.L.str, %edi
xorl %esi, %esi
movl $1, %edx
xorl %eax, %eax
callq printf
movl (%rsp), %ecx
movl $.L.str, %edi
movl $1, %esi
xorl %edx, %edx
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
je .LBB0_3
# %bb.1:
cmpl $0, (%rsp)
je .LBB0_3
# %bb.2:
xorl %edi, %edi
callq hipSetDevice
movl $1, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
movl $1, %edi
callq hipSetDevice
xorl %edi, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
.LBB0_3:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
movl $1, %esi
callq hipStreamCreateWithFlags
movq 24(%rsp), %rdi
movq 8(%rsp), %rsi
callq hipEventRecord
movl $10, %ebx
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 8(%rsp), %r8
movl $67108864, %edx # imm = 0x4000000
movl $3, %ecx
callq hipMemcpyAsync
decl %ebx
jne .LBB0_4
# %bb.5:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
cmpl $0, 4(%rsp)
je .LBB0_8
# %bb.6:
cmpl $0, (%rsp)
je .LBB0_8
# %bb.7:
xorl %edi, %edi
callq hipSetDevice
movl $1, %edi
callq hipDeviceDisablePeerAccess
movl $1, %edi
callq hipSetDevice
xorl %edi, %edi
callq hipDeviceDisablePeerAccess
.LBB0_8:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipStreamDestroy
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaDeviceCanAccessPeer(%d->%d): %d\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Seconds: %f\n"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Unidirectional Bandwidth: %f (GB/s)\n"
.size .L.str.2, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00025b3c_00000000-6_memcpy_with_nvlink.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaDeviceCanAccessPeer(%d->%d): %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Seconds: %f\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Unidirectional Bandwidth: %f (GB/s)\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rdi
movl $1, %edx
movl $0, %esi
call cudaDeviceCanAccessPeer@PLT
leaq 8(%rsp), %rdi
movl $0, %edx
movl $1, %esi
call cudaDeviceCanAccessPeer@PLT
movl 4(%rsp), %r8d
movl $1, %ecx
movl $0, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %r8d
movl $0, %ecx
movl $1, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
je .L4
cmpl $0, 8(%rsp)
jne .L10
.L4:
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
movl $1, %esi
call cudaStreamCreateWithFlags@PLT
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $10, %ebx
.L5:
movq 48(%rsp), %r8
movl $3, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpyAsync@PLT
subl $1, %ebx
jne .L5
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaStreamSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
divsd .LC1(%rip), %xmm0
movsd .LC2(%rip), %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
je .L6
cmpl $0, 8(%rsp)
jne .L11
.L6:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl $0, %edi
call cudaSetDevice@PLT
movl $0, %esi
movl $1, %edi
call cudaDeviceEnablePeerAccess@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %esi
movl $0, %edi
call cudaDeviceEnablePeerAccess@PLT
jmp .L4
.L11:
movl $0, %edi
call cudaSetDevice@PLT
movl $1, %edi
call cudaDeviceDisablePeerAccess@PLT
movl $1, %edi
call cudaSetDevice@PLT
movl $0, %edi
call cudaDeviceDisablePeerAccess@PLT
jmp .L6
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long -500134854
.long 1072003470
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memcpy_with_nvlink.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x408f400000000000 # double 1000
.LCPI0_1:
.quad 0x3fe5798ee2308c3a # double 0.67108864000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
leaq 48(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movl $1, %edi
callq hipSetDevice
leaq 40(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 4(%rsp), %rdi
xorl %esi, %esi
movl $1, %edx
callq hipDeviceCanAccessPeer
movq %rsp, %rdi
movl $1, %esi
xorl %edx, %edx
callq hipDeviceCanAccessPeer
movl 4(%rsp), %ecx
movl $.L.str, %edi
xorl %esi, %esi
movl $1, %edx
xorl %eax, %eax
callq printf
movl (%rsp), %ecx
movl $.L.str, %edi
movl $1, %esi
xorl %edx, %edx
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
je .LBB0_3
# %bb.1:
cmpl $0, (%rsp)
je .LBB0_3
# %bb.2:
xorl %edi, %edi
callq hipSetDevice
movl $1, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
movl $1, %edi
callq hipSetDevice
xorl %edi, %edi
xorl %esi, %esi
callq hipDeviceEnablePeerAccess
.LBB0_3:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
movl $1, %esi
callq hipStreamCreateWithFlags
movq 24(%rsp), %rdi
movq 8(%rsp), %rsi
callq hipEventRecord
movl $10, %ebx
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq 48(%rsp), %rdi
movq 40(%rsp), %rsi
movq 8(%rsp), %r8
movl $67108864, %edx # imm = 0x4000000
movl $3, %ecx
callq hipMemcpyAsync
decl %ebx
jne .LBB0_4
# %bb.5:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 36(%rsp), %rdi
callq hipEventElapsedTime
movss 36(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 56(%rsp) # 8-byte Spill
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
cmpl $0, 4(%rsp)
je .LBB0_8
# %bb.6:
cmpl $0, (%rsp)
je .LBB0_8
# %bb.7:
xorl %edi, %edi
callq hipSetDevice
movl $1, %edi
callq hipDeviceDisablePeerAccess
movl $1, %edi
callq hipSetDevice
xorl %edi, %edi
callq hipDeviceDisablePeerAccess
.LBB0_8:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipStreamDestroy
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaDeviceCanAccessPeer(%d->%d): %d\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Seconds: %f\n"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Unidirectional Bandwidth: %f (GB/s)\n"
.size .L.str.2, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Test Programm nach:
https://www.thomas-krenn.com/de/wiki/CUDA_Programmierung
*/
#include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
// Vars
// Host-Vars
int* h_A;
int* h_B;
int* h_C;
// Device-Vars
int* d_A;
int* d_B;
int* d_C;
// Prototypes
void RandomInit(int* data, int n);
int CheckResults(int* A, int* B, int* C, int n);
// Kernel
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(void) {
printf("Vector addtion\n");
//int i;
int N = 100000 * 1000;
size_t size = N * sizeof(int);
// Speicher auf Host allozieren
h_A = (int*)malloc(size);
h_B = (int*)malloc(size);
h_C = (int*)malloc(size);
// Random Init
RandomInit(h_A, N);
RandomInit(h_B, N);
// Speicher auf Device allozieren
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
// Vektoren zum Device kopieren
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Kernelaufruf
// Nvidia GTX 1080 TI hat 1024 Threads pro Block
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n", blocksPerGrid, threadsPerBlock);
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
// Auf das Gerät warten
cudaDeviceSynchronize();
// Ergebnis auf Host kopieren
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Ergebnisse prüfen
if (CheckResults(h_A, h_B, h_C, N) == 0)
printf("Alles ok!\n");
else
printf("Fehler\n");
// Speicherfreigabe
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
}
// Vector mit Zufallszahlen füllen
void RandomInit(int* data, int n) {
for (int i = 0; i < n; i++)
data[i] = rand() % (int) 100;
}
// Ergebnis Prüfen
int CheckResults(int* A, int* B, int* C, int n) {
int i;
for (i = 0; i < n; i++) {
if ((A[i]+B[i]) != C[i])
return -1;
}
return 0;
} | code for sm_80
Function : _Z6VecAddPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Test Programm nach:
https://www.thomas-krenn.com/de/wiki/CUDA_Programmierung
*/
#include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
// Vars
// Host-Vars
int* h_A;
int* h_B;
int* h_C;
// Device-Vars
int* d_A;
int* d_B;
int* d_C;
// Prototypes
void RandomInit(int* data, int n);
int CheckResults(int* A, int* B, int* C, int n);
// Kernel
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(void) {
printf("Vector addtion\n");
//int i;
int N = 100000 * 1000;
size_t size = N * sizeof(int);
// Speicher auf Host allozieren
h_A = (int*)malloc(size);
h_B = (int*)malloc(size);
h_C = (int*)malloc(size);
// Random Init
RandomInit(h_A, N);
RandomInit(h_B, N);
// Speicher auf Device allozieren
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
// Vektoren zum Device kopieren
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Kernelaufruf
// Nvidia GTX 1080 TI hat 1024 Threads pro Block
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n", blocksPerGrid, threadsPerBlock);
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
// Auf das Gerät warten
cudaDeviceSynchronize();
// Ergebnis auf Host kopieren
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Ergebnisse prüfen
if (CheckResults(h_A, h_B, h_C, N) == 0)
printf("Alles ok!\n");
else
printf("Fehler\n");
// Speicherfreigabe
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
}
// Vector mit Zufallszahlen füllen
void RandomInit(int* data, int n) {
for (int i = 0; i < n; i++)
data[i] = rand() % (int) 100;
}
// Ergebnis Prüfen
int CheckResults(int* A, int* B, int* C, int n) {
int i;
for (i = 0; i < n; i++) {
if ((A[i]+B[i]) != C[i])
return -1;
}
return 0;
} | .file "tmpxft_0018b16d_00000000-6_memtest_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10RandomInitPii
.type _Z10RandomInitPii, @function
_Z10RandomInitPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10RandomInitPii, .-_Z10RandomInitPii
.globl _Z12CheckResultsPiS_S_i
.type _Z12CheckResultsPiS_S_i, @function
_Z12CheckResultsPiS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L14
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L13:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
cmpl (%rdx,%rax), %ecx
jne .L15
addq $4, %rax
cmpq %r8, %rax
jne .L13
movl $0, %eax
ret
.L14:
movl $0, %eax
ret
.L15:
movl $-1, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z12CheckResultsPiS_S_i, .-_Z12CheckResultsPiS_S_i
.globl _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.type _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, @function
_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, .-_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.type _Z6VecAddPKiS0_Pii, @function
_Z6VecAddPKiS0_Pii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6VecAddPKiS0_Pii, .-_Z6VecAddPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Vector addtion\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n"
.section .rodata.str1.1
.LC2:
.string "Alles ok!\n"
.LC3:
.string "Fehler\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, h_A(%rip)
movl $400000000, %edi
call malloc@PLT
movq %rax, h_B(%rip)
movl $400000000, %edi
call malloc@PLT
movq %rax, h_C(%rip)
movl $100000000, %esi
movq %rbx, %rdi
call _Z10RandomInitPii
movl $100000000, %esi
movq h_B(%rip), %rdi
call _Z10RandomInitPii
movl $400000000, %esi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
movl $400000000, %esi
leaq d_B(%rip), %rdi
call cudaMalloc@PLT
movl $400000000, %esi
leaq d_C(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq h_A(%rip), %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq h_B(%rip), %rsi
movq d_B(%rip), %rdi
call cudaMemcpy@PLT
movl $1024, %ecx
movl $97657, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $97657, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $400000000, %edx
movq d_C(%rip), %rsi
movq h_C(%rip), %rdi
call cudaMemcpy@PLT
movl $100000000, %ecx
movq h_C(%rip), %rdx
movq h_B(%rip), %rsi
movq h_A(%rip), %rdi
call _Z12CheckResultsPiS_S_i
testl %eax, %eax
jne .L27
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L28:
movq d_A(%rip), %rdi
call cudaFree@PLT
movq d_B(%rip), %rdi
call cudaFree@PLT
movq d_C(%rip), %rdi
call cudaFree@PLT
movq h_A(%rip), %rdi
call free@PLT
movq h_B(%rip), %rdi
call free@PLT
movq h_C(%rip), %rdi
call free@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $100000000, %ecx
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
jmp .L26
.L27:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6VecAddPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_C
.bss
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Test Programm nach:
https://www.thomas-krenn.com/de/wiki/CUDA_Programmierung
*/
#include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
// Vars
// Host-Vars
int* h_A;
int* h_B;
int* h_C;
// Device-Vars
int* d_A;
int* d_B;
int* d_C;
// Prototypes
void RandomInit(int* data, int n);
int CheckResults(int* A, int* B, int* C, int n);
// Kernel
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(void) {
printf("Vector addtion\n");
//int i;
int N = 100000 * 1000;
size_t size = N * sizeof(int);
// Speicher auf Host allozieren
h_A = (int*)malloc(size);
h_B = (int*)malloc(size);
h_C = (int*)malloc(size);
// Random Init
RandomInit(h_A, N);
RandomInit(h_B, N);
// Speicher auf Device allozieren
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
// Vektoren zum Device kopieren
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Kernelaufruf
// Nvidia GTX 1080 TI hat 1024 Threads pro Block
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n", blocksPerGrid, threadsPerBlock);
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
// Auf das Gerät warten
cudaDeviceSynchronize();
// Ergebnis auf Host kopieren
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
// Ergebnisse prüfen
if (CheckResults(h_A, h_B, h_C, N) == 0)
printf("Alles ok!\n");
else
printf("Fehler\n");
// Speicherfreigabe
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
}
// Vector mit Zufallszahlen füllen
void RandomInit(int* data, int n) {
for (int i = 0; i < n; i++)
data[i] = rand() % (int) 100;
}
// Ergebnis Prüfen
int CheckResults(int* A, int* B, int* C, int n) {
int i;
for (i = 0; i < n; i++) {
if ((A[i]+B[i]) != C[i])
return -1;
}
return 0;
} | /*
Test Programm nach:
https://www.thomas-krenn.com/de/wiki/CUDA_Programmierung
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
// Vars
// Host-Vars
int* h_A;
int* h_B;
int* h_C;
// Device-Vars
int* d_A;
int* d_B;
int* d_C;
// Prototypes
void RandomInit(int* data, int n);
int CheckResults(int* A, int* B, int* C, int n);
// Kernel
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(void) {
printf("Vector addtion\n");
//int i;
int N = 100000 * 1000;
size_t size = N * sizeof(int);
// Speicher auf Host allozieren
h_A = (int*)malloc(size);
h_B = (int*)malloc(size);
h_C = (int*)malloc(size);
// Random Init
RandomInit(h_A, N);
RandomInit(h_B, N);
// Speicher auf Device allozieren
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
// Vektoren zum Device kopieren
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Kernelaufruf
// Nvidia GTX 1080 TI hat 1024 Threads pro Block
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n", blocksPerGrid, threadsPerBlock);
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
// Auf das Gerät warten
hipDeviceSynchronize();
// Ergebnis auf Host kopieren
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Ergebnisse prüfen
if (CheckResults(h_A, h_B, h_C, N) == 0)
printf("Alles ok!\n");
else
printf("Fehler\n");
// Speicherfreigabe
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
}
// Vector mit Zufallszahlen füllen
void RandomInit(int* data, int n) {
for (int i = 0; i < n; i++)
data[i] = rand() % (int) 100;
}
// Ergebnis Prüfen
int CheckResults(int* A, int* B, int* C, int n) {
int i;
for (i = 0; i < n; i++) {
if ((A[i]+B[i]) != C[i])
return -1;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Test Programm nach:
https://www.thomas-krenn.com/de/wiki/CUDA_Programmierung
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
// Vars
// Host-Vars
int* h_A;
int* h_B;
int* h_C;
// Device-Vars
int* d_A;
int* d_B;
int* d_C;
// Prototypes
void RandomInit(int* data, int n);
int CheckResults(int* A, int* B, int* C, int n);
// Kernel
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(void) {
printf("Vector addtion\n");
//int i;
int N = 100000 * 1000;
size_t size = N * sizeof(int);
// Speicher auf Host allozieren
h_A = (int*)malloc(size);
h_B = (int*)malloc(size);
h_C = (int*)malloc(size);
// Random Init
RandomInit(h_A, N);
RandomInit(h_B, N);
// Speicher auf Device allozieren
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
// Vektoren zum Device kopieren
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Kernelaufruf
// Nvidia GTX 1080 TI hat 1024 Threads pro Block
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n", blocksPerGrid, threadsPerBlock);
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
// Auf das Gerät warten
hipDeviceSynchronize();
// Ergebnis auf Host kopieren
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Ergebnisse prüfen
if (CheckResults(h_A, h_B, h_C, N) == 0)
printf("Alles ok!\n");
else
printf("Fehler\n");
// Speicherfreigabe
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
}
// Vector mit Zufallszahlen füllen
void RandomInit(int* data, int n) {
for (int i = 0; i < n; i++)
data[i] = rand() % (int) 100;
}
// Ergebnis Prüfen
int CheckResults(int* A, int* B, int* C, int n) {
int i;
for (i = 0; i < n; i++) {
if ((A[i]+B[i]) != C[i])
return -1;
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.p2align 8
.type _Z6VecAddPKiS0_Pii,@function
_Z6VecAddPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPKiS0_Pii, .Lfunc_end0-_Z6VecAddPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Test Programm nach:
https://www.thomas-krenn.com/de/wiki/CUDA_Programmierung
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
// Vars
// Host-Vars
int* h_A;
int* h_B;
int* h_C;
// Device-Vars
int* d_A;
int* d_B;
int* d_C;
// Prototypes
void RandomInit(int* data, int n);
int CheckResults(int* A, int* B, int* C, int n);
// Kernel
__global__ void VecAdd(const int* A, const int* B, int* C, int N) {
// Index holen
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}
int main(void) {
printf("Vector addtion\n");
//int i;
int N = 100000 * 1000;
size_t size = N * sizeof(int);
// Speicher auf Host allozieren
h_A = (int*)malloc(size);
h_B = (int*)malloc(size);
h_C = (int*)malloc(size);
// Random Init
RandomInit(h_A, N);
RandomInit(h_B, N);
// Speicher auf Device allozieren
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
// Vektoren zum Device kopieren
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Kernelaufruf
// Nvidia GTX 1080 TI hat 1024 Threads pro Block
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n", blocksPerGrid, threadsPerBlock);
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
// Auf das Gerät warten
hipDeviceSynchronize();
// Ergebnis auf Host kopieren
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
// Ergebnisse prüfen
if (CheckResults(h_A, h_B, h_C, N) == 0)
printf("Alles ok!\n");
else
printf("Fehler\n");
// Speicherfreigabe
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
}
// Vector mit Zufallszahlen füllen
void RandomInit(int* data, int n) {
for (int i = 0; i < n; i++)
data[i] = rand() % (int) 100;
}
// Ergebnis Prüfen
int CheckResults(int* A, int* B, int* C, int n) {
int i;
for (i = 0; i < n; i++) {
if ((A[i]+B[i]) != C[i])
return -1;
}
return 0;
} | .text
.file "memtest_gpu.hip"
.globl _Z21__device_stub__VecAddPKiS0_Pii # -- Begin function _Z21__device_stub__VecAddPKiS0_Pii
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPKiS0_Pii,@function
_Z21__device_stub__VecAddPKiS0_Pii: # @_Z21__device_stub__VecAddPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPKiS0_Pii, .Lfunc_end0-_Z21__device_stub__VecAddPKiS0_Pii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.Lstr, %edi
callq puts@PLT
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movq %rax, h_A(%rip)
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, h_B(%rip)
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, h_C(%rip)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB1_1
# %bb.2: # %_Z10RandomInitPii.exit
movq h_B(%rip), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i25
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB1_3
# %bb.4: # %_Z10RandomInitPii.exit29
movl $d_A, %edi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $d_B, %edi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $d_C, %edi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq d_A(%rip), %rdi
movq h_A(%rip), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movq d_B(%rip), %rdi
movq h_B(%rip), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
movl $97657, %esi # imm = 0x17D79
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 96633(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq d_A(%rip), %rax
movq d_B(%rip), %rcx
movq d_C(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $100000000, 4(%rsp) # imm = 0x5F5E100
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
movq h_C(%rip), %rdi
movq d_C(%rip), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $2, %ecx
callq hipMemcpy
movq h_A(%rip), %rax
movq h_B(%rip), %rcx
xorl %edx, %edx
movq h_C(%rip), %rsi
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i30
# =>This Inner Loop Header: Depth=1
movl (%rcx,%rdx,4), %edi
addl (%rax,%rdx,4), %edi
movl (%rsi,%rdx,4), %r8d
cmpl %r8d, %edi
jne .LBB1_9
# %bb.8: # %.lr.ph.i30
# in Loop: Header=BB1_7 Depth=1
leaq 1(%rdx), %r9
cmpq $99999999, %rdx # imm = 0x5F5E0FF
movq %r9, %rdx
jne .LBB1_7
.LBB1_9: # %_Z12CheckResultsPiS_S_i.exit
cmpl %r8d, %edi
movl $.Lstr.1, %eax
movl $.Lstr.2, %edi
cmovneq %rax, %rdi
callq puts@PLT
movq d_A(%rip), %rdi
callq hipFree
movq d_B(%rip), %rdi
callq hipFree
movq d_C(%rip), %rdi
callq hipFree
movq h_A(%rip), %rdi
callq free
movq h_B(%rip), %rdi
callq free
movq h_C(%rip), %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10RandomInitPii # -- Begin function _Z10RandomInitPii
.p2align 4, 0x90
.type _Z10RandomInitPii,@function
_Z10RandomInitPii: # @_Z10RandomInitPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10RandomInitPii, .Lfunc_end2-_Z10RandomInitPii
.cfi_endproc
# -- End function
.globl _Z12CheckResultsPiS_S_i # -- Begin function _Z12CheckResultsPiS_S_i
.p2align 4, 0x90
.type _Z12CheckResultsPiS_S_i,@function
_Z12CheckResultsPiS_S_i: # @_Z12CheckResultsPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
cmpl (%rdx,%rcx,4), %r8d
jne .LBB3_6
# %bb.3: # in Loop: Header=BB3_2 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_5:
xorl %eax, %eax
retq
.LBB3_6:
movl $-1, %eax
retq
.Lfunc_end3:
.size _Z12CheckResultsPiS_S_i, .Lfunc_end3-_Z12CheckResultsPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type _Z6VecAddPKiS0_Pii,@object # @_Z6VecAddPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z6VecAddPKiS0_Pii
.p2align 3, 0x0
_Z6VecAddPKiS0_Pii:
.quad _Z21__device_stub__VecAddPKiS0_Pii
.size _Z6VecAddPKiS0_Pii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n"
.size .L.str.1, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPKiS0_Pii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Vector addtion"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Fehler"
.size .Lstr.1, 7
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Alles ok!"
.size .Lstr.2, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_A
.addrsig_sym d_B
.addrsig_sym d_C
.addrsig_sym _Z6VecAddPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.p2align 8
.type _Z6VecAddPKiS0_Pii,@function
_Z6VecAddPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPKiS0_Pii, .Lfunc_end0-_Z6VecAddPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018b16d_00000000-6_memtest_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10RandomInitPii
.type _Z10RandomInitPii, @function
_Z10RandomInitPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z10RandomInitPii, .-_Z10RandomInitPii
.globl _Z12CheckResultsPiS_S_i
.type _Z12CheckResultsPiS_S_i, @function
_Z12CheckResultsPiS_S_i:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L14
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L13:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
cmpl (%rdx,%rax), %ecx
jne .L15
addq $4, %rax
cmpq %r8, %rax
jne .L13
movl $0, %eax
ret
.L14:
movl $0, %eax
ret
.L15:
movl $-1, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z12CheckResultsPiS_S_i, .-_Z12CheckResultsPiS_S_i
.globl _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.type _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, @function
_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii, .-_Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
.globl _Z6VecAddPKiS0_Pii
.type _Z6VecAddPKiS0_Pii, @function
_Z6VecAddPKiS0_Pii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6VecAddPKiS0_Pii, .-_Z6VecAddPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Vector addtion\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n"
.section .rodata.str1.1
.LC2:
.string "Alles ok!\n"
.LC3:
.string "Fehler\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, h_A(%rip)
movl $400000000, %edi
call malloc@PLT
movq %rax, h_B(%rip)
movl $400000000, %edi
call malloc@PLT
movq %rax, h_C(%rip)
movl $100000000, %esi
movq %rbx, %rdi
call _Z10RandomInitPii
movl $100000000, %esi
movq h_B(%rip), %rdi
call _Z10RandomInitPii
movl $400000000, %esi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
movl $400000000, %esi
leaq d_B(%rip), %rdi
call cudaMalloc@PLT
movl $400000000, %esi
leaq d_C(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000000, %edx
movq h_A(%rip), %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq h_B(%rip), %rsi
movq d_B(%rip), %rdi
call cudaMemcpy@PLT
movl $1024, %ecx
movl $97657, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $97657, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $400000000, %edx
movq d_C(%rip), %rsi
movq h_C(%rip), %rdi
call cudaMemcpy@PLT
movl $100000000, %ecx
movq h_C(%rip), %rdx
movq h_B(%rip), %rsi
movq h_A(%rip), %rdi
call _Z12CheckResultsPiS_S_i
testl %eax, %eax
jne .L27
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L28:
movq d_A(%rip), %rdi
call cudaFree@PLT
movq d_B(%rip), %rdi
call cudaFree@PLT
movq d_C(%rip), %rdi
call cudaFree@PLT
movq h_A(%rip), %rdi
call free@PLT
movq h_B(%rip), %rdi
call free@PLT
movq h_C(%rip), %rdi
call free@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $100000000, %ecx
movq d_C(%rip), %rdx
movq d_B(%rip), %rsi
movq d_A(%rip), %rdi
call _Z32__device_stub__Z6VecAddPKiS0_PiiPKiS0_Pii
jmp .L26
.L27:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6VecAddPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_C
.bss
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memtest_gpu.hip"
.globl _Z21__device_stub__VecAddPKiS0_Pii # -- Begin function _Z21__device_stub__VecAddPKiS0_Pii
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPKiS0_Pii,@function
_Z21__device_stub__VecAddPKiS0_Pii: # @_Z21__device_stub__VecAddPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPKiS0_Pii, .Lfunc_end0-_Z21__device_stub__VecAddPKiS0_Pii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.Lstr, %edi
callq puts@PLT
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
movq %rax, h_A(%rip)
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, h_B(%rip)
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, h_C(%rip)
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB1_1
# %bb.2: # %_Z10RandomInitPii.exit
movq h_B(%rip), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i25
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $100000000, %r14 # imm = 0x5F5E100
jne .LBB1_3
# %bb.4: # %_Z10RandomInitPii.exit29
movl $d_A, %edi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $d_B, %edi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $d_C, %edi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movq d_A(%rip), %rdi
movq h_A(%rip), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movq d_B(%rip), %rdi
movq h_B(%rip), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $1, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
movl $97657, %esi # imm = 0x17D79
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 96633(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq d_A(%rip), %rax
movq d_B(%rip), %rcx
movq d_C(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $100000000, 4(%rsp) # imm = 0x5F5E100
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
movq h_C(%rip), %rdi
movq d_C(%rip), %rsi
movl $400000000, %edx # imm = 0x17D78400
movl $2, %ecx
callq hipMemcpy
movq h_A(%rip), %rax
movq h_B(%rip), %rcx
xorl %edx, %edx
movq h_C(%rip), %rsi
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i30
# =>This Inner Loop Header: Depth=1
movl (%rcx,%rdx,4), %edi
addl (%rax,%rdx,4), %edi
movl (%rsi,%rdx,4), %r8d
cmpl %r8d, %edi
jne .LBB1_9
# %bb.8: # %.lr.ph.i30
# in Loop: Header=BB1_7 Depth=1
leaq 1(%rdx), %r9
cmpq $99999999, %rdx # imm = 0x5F5E0FF
movq %r9, %rdx
jne .LBB1_7
.LBB1_9: # %_Z12CheckResultsPiS_S_i.exit
cmpl %r8d, %edi
movl $.Lstr.1, %eax
movl $.Lstr.2, %edi
cmovneq %rax, %rdi
callq puts@PLT
movq d_A(%rip), %rdi
callq hipFree
movq d_B(%rip), %rdi
callq hipFree
movq d_C(%rip), %rdi
callq hipFree
movq h_A(%rip), %rdi
callq free
movq h_B(%rip), %rdi
callq free
movq h_C(%rip), %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10RandomInitPii # -- Begin function _Z10RandomInitPii
.p2align 4, 0x90
.type _Z10RandomInitPii,@function
_Z10RandomInitPii: # @_Z10RandomInitPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10RandomInitPii, .Lfunc_end2-_Z10RandomInitPii
.cfi_endproc
# -- End function
.globl _Z12CheckResultsPiS_S_i # -- Begin function _Z12CheckResultsPiS_S_i
.p2align 4, 0x90
.type _Z12CheckResultsPiS_S_i,@function
_Z12CheckResultsPiS_S_i: # @_Z12CheckResultsPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
cmpl (%rdx,%rcx,4), %r8d
jne .LBB3_6
# %bb.3: # in Loop: Header=BB3_2 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_5:
xorl %eax, %eax
retq
.LBB3_6:
movl $-1, %eax
retq
.Lfunc_end3:
.size _Z12CheckResultsPiS_S_i, .Lfunc_end3-_Z12CheckResultsPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type _Z6VecAddPKiS0_Pii,@object # @_Z6VecAddPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z6VecAddPKiS0_Pii
.p2align 3, 0x0
_Z6VecAddPKiS0_Pii:
.quad _Z21__device_stub__VecAddPKiS0_Pii
.size _Z6VecAddPKiS0_Pii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "BlocksPerGrid = %i, ThreadsPerBlock = %i\n\n"
.size .L.str.1, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPKiS0_Pii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Vector addtion"
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Fehler"
.size .Lstr.1, 7
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Alles ok!"
.size .Lstr.2, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_A
.addrsig_sym d_B
.addrsig_sym d_C
.addrsig_sym _Z6VecAddPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768
//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{
int tid = threadIdx.x;
for(int j = 0; j < unsize; j++){
if (j == 0){
out_array[tid * unsize] = in_array[tid * unsize];
} else {
for(int k = 0; k <= j; k++) {
out_array[tid * unsize + j] += in_array[tid * unsize + k];
}
}
}
}
//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
int tid = threadIdx.x;
if (tid <= maxid) {
int maxstep = unsize * (int)(powf(2, idx - 1));
for(int j = 0; j < maxstep; j++) {
int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
}
}
}
void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
int *array_d;
int *tmp_one;
int unsize = size/(blocks * threads);
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
// allocate tmp_d
cudaMalloc((void **)&tmp_one, size * sizeof(int));
//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
cudaMalloc((void **)&array_d, size * sizeof(int));
//copy data from host to device
cudaMemcpy(array_d, array_h, size * sizeof(int),
cudaMemcpyHostToDevice);
cudaMemset(tmp_one, 0, size * sizeof(int));
//do stage 1
prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
if (steps !=0) {
int maxtid = 0;
//do stage 2
for (int i = 1; i <= steps; i++) {
maxtid = (int)pow(2, steps-i) - 1;
prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
}
}
cudaMemcpy(array_h, tmp_one, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(array_d);
cudaFree(tmp_one);
}
void prepare_numbers(int **array, int count)
{
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (int i = 0; i < count; i++) {
numbers[i] = 1;
}
*array = numbers;
}
void print_array(int *array, int count)
{
for (int i = 0; i < count; i++) {
printf("%d\t", array[i]);
}
printf("\n");
}
int main()
{
int blocks, threads, max, stepTwo;
int *array;
float calTime;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
stepTwo = 8;
max = NUM_MEM;
// pre-init numbers
array = NULL;
prepare_numbers(&array, max);
cudaEventRecord(start, 0);
prefixsum(blocks, threads, stepTwo, array, max);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&calTime, start, end);
// print array
// print_array(array, max);
printf("the elapsed time with %d threads is %.10f\n", threads, calTime);
free(array);
return 0;
} | .file "tmpxft_00028e98_00000000-6_prefix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15prepare_numbersPPii
.type _Z15prepare_numbersPPii, @function
_Z15prepare_numbersPPii:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
movslq %esi, %rcx
leaq 0(,%rcx,4), %rbx
movq %rbx, %rdi
call malloc@PLT
testl %r12d, %r12d
jle .L4
movq %rax, %rdx
leaq (%rbx,%rax), %rcx
.L5:
movl $1, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L5
.L4:
movq %rax, 0(%rbp)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z15prepare_numbersPPii, .-_Z15prepare_numbersPPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2072:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L9
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L10:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
.L9:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
.type _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii, @function
_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9prefixOnePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii, .-_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
.globl _Z9prefixOnePiS_ii
.type _Z9prefixOnePiS_ii, @function
_Z9prefixOnePiS_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z9prefixOnePiS_ii, .-_Z9prefixOnePiS_ii
.globl _Z31__device_stub__Z9prefixTwoPiiiiPiiii
.type _Z31__device_stub__Z9prefixTwoPiiiiPiiii, @function
_Z31__device_stub__Z9prefixTwoPiiiiPiiii:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9prefixTwoPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z31__device_stub__Z9prefixTwoPiiiiPiiii, .-_Z31__device_stub__Z9prefixTwoPiiiiPiiii
.globl _Z9prefixTwoPiiii
.type _Z9prefixTwoPiiii, @function
_Z9prefixTwoPiiii:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9prefixTwoPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z9prefixTwoPiiii, .-_Z9prefixTwoPiiii
.globl _Z9prefixsumiiiPii
.type _Z9prefixsumiiiPii, @function
_Z9prefixsumiiiPii:
.LFB2070:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edx, %ebp
movq %rcx, %r13
movl %r8d, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, %ecx
imull %esi, %ecx
movl %r8d, %eax
cltd
idivl %ecx
movl %eax, %r14d
movl %edi, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %esi, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movslq %r8d, %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %r12, %rdx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L30:
testl %ebp, %ebp
jle .L31
movl $1, %ebx
jmp .L33
.L37:
movl %ebx, %ecx
movl %r14d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
jmp .L30
.L32:
addl $1, %ebx
cmpl %ebx, %ebp
jl .L31
.L33:
movl %ebp, %eax
subl %ebx, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
movsd %xmm0, 8(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
cvttsd2sil 8(%rsp), %edx
subl $1, %edx
movl %ebx, %ecx
movl %r14d, %esi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z9prefixTwoPiiiiPiiii
jmp .L32
.L31:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z9prefixsumiiiPii, .-_Z9prefixsumiiiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "the elapsed time with %d threads is %.10f\n"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
movl $32768, %esi
call _Z15prepare_numbersPPii
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rbx
movl $32768, %r8d
movq %rbx, %rcx
movl $8, %edx
movl $256, %esi
movl $1, %edi
call _Z9prefixsumiiiPii
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl $256, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9prefixTwoPiiii"
.LC5:
.string "_Z9prefixOnePiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9prefixTwoPiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9prefixOnePiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768
//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{
int tid = threadIdx.x;
for(int j = 0; j < unsize; j++){
if (j == 0){
out_array[tid * unsize] = in_array[tid * unsize];
} else {
for(int k = 0; k <= j; k++) {
out_array[tid * unsize + j] += in_array[tid * unsize + k];
}
}
}
}
//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
int tid = threadIdx.x;
if (tid <= maxid) {
int maxstep = unsize * (int)(powf(2, idx - 1));
for(int j = 0; j < maxstep; j++) {
int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
}
}
}
void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
int *array_d;
int *tmp_one;
int unsize = size/(blocks * threads);
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
// allocate tmp_d
cudaMalloc((void **)&tmp_one, size * sizeof(int));
//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
cudaMalloc((void **)&array_d, size * sizeof(int));
//copy data from host to device
cudaMemcpy(array_d, array_h, size * sizeof(int),
cudaMemcpyHostToDevice);
cudaMemset(tmp_one, 0, size * sizeof(int));
//do stage 1
prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
if (steps !=0) {
int maxtid = 0;
//do stage 2
for (int i = 1; i <= steps; i++) {
maxtid = (int)pow(2, steps-i) - 1;
prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
}
}
cudaMemcpy(array_h, tmp_one, size * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(array_d);
cudaFree(tmp_one);
}
void prepare_numbers(int **array, int count)
{
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (int i = 0; i < count; i++) {
numbers[i] = 1;
}
*array = numbers;
}
void print_array(int *array, int count)
{
for (int i = 0; i < count; i++) {
printf("%d\t", array[i]);
}
printf("\n");
}
int main()
{
int blocks, threads, max, stepTwo;
int *array;
float calTime;
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
stepTwo = 8;
max = NUM_MEM;
// pre-init numbers
array = NULL;
prepare_numbers(&array, max);
cudaEventRecord(start, 0);
prefixsum(blocks, threads, stepTwo, array, max);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&calTime, start, end);
// print array
// print_array(array, max);
printf("the elapsed time with %d threads is %.10f\n", threads, calTime);
free(array);
return 0;
} | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "hip/hip_runtime.h"
#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768
//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{
int tid = threadIdx.x;
for(int j = 0; j < unsize; j++){
if (j == 0){
out_array[tid * unsize] = in_array[tid * unsize];
} else {
for(int k = 0; k <= j; k++) {
out_array[tid * unsize + j] += in_array[tid * unsize + k];
}
}
}
}
//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
int tid = threadIdx.x;
if (tid <= maxid) {
int maxstep = unsize * (int)(powf(2, idx - 1));
for(int j = 0; j < maxstep; j++) {
int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
}
}
}
void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
int *array_d;
int *tmp_one;
int unsize = size/(blocks * threads);
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
// allocate tmp_d
hipMalloc((void **)&tmp_one, size * sizeof(int));
//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
hipMalloc((void **)&array_d, size * sizeof(int));
//copy data from host to device
hipMemcpy(array_d, array_h, size * sizeof(int),
hipMemcpyHostToDevice);
hipMemset(tmp_one, 0, size * sizeof(int));
//do stage 1
prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
if (steps !=0) {
int maxtid = 0;
//do stage 2
for (int i = 1; i <= steps; i++) {
maxtid = (int)pow(2, steps-i) - 1;
prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
}
}
hipMemcpy(array_h, tmp_one, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(array_d);
hipFree(tmp_one);
}
void prepare_numbers(int **array, int count)
{
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (int i = 0; i < count; i++) {
numbers[i] = 1;
}
*array = numbers;
}
void print_array(int *array, int count)
{
for (int i = 0; i < count; i++) {
printf("%d\t", array[i]);
}
printf("\n");
}
int main()
{
int blocks, threads, max, stepTwo;
int *array;
float calTime;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
stepTwo = 8;
max = NUM_MEM;
// pre-init numbers
array = NULL;
prepare_numbers(&array, max);
hipEventRecord(start, 0);
prefixsum(blocks, threads, stepTwo, array, max);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&calTime, start, end);
// print array
// print_array(array, max);
printf("the elapsed time with %d threads is %.10f\n", threads, calTime);
free(array);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "hip/hip_runtime.h"
#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768
//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{
int tid = threadIdx.x;
for(int j = 0; j < unsize; j++){
if (j == 0){
out_array[tid * unsize] = in_array[tid * unsize];
} else {
for(int k = 0; k <= j; k++) {
out_array[tid * unsize + j] += in_array[tid * unsize + k];
}
}
}
}
//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
int tid = threadIdx.x;
if (tid <= maxid) {
int maxstep = unsize * (int)(powf(2, idx - 1));
for(int j = 0; j < maxstep; j++) {
int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
}
}
}
void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
int *array_d;
int *tmp_one;
int unsize = size/(blocks * threads);
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
// allocate tmp_d
hipMalloc((void **)&tmp_one, size * sizeof(int));
//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
hipMalloc((void **)&array_d, size * sizeof(int));
//copy data from host to device
hipMemcpy(array_d, array_h, size * sizeof(int),
hipMemcpyHostToDevice);
hipMemset(tmp_one, 0, size * sizeof(int));
//do stage 1
prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
if (steps !=0) {
int maxtid = 0;
//do stage 2
for (int i = 1; i <= steps; i++) {
maxtid = (int)pow(2, steps-i) - 1;
prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
}
}
hipMemcpy(array_h, tmp_one, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(array_d);
hipFree(tmp_one);
}
void prepare_numbers(int **array, int count)
{
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (int i = 0; i < count; i++) {
numbers[i] = 1;
}
*array = numbers;
}
void print_array(int *array, int count)
{
for (int i = 0; i < count; i++) {
printf("%d\t", array[i]);
}
printf("\n");
}
int main()
{
int blocks, threads, max, stepTwo;
int *array;
float calTime;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
stepTwo = 8;
max = NUM_MEM;
// pre-init numbers
array = NULL;
prepare_numbers(&array, max);
hipEventRecord(start, 0);
prefixsum(blocks, threads, stepTwo, array, max);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&calTime, start, end);
// print array
// print_array(array, max);
printf("the elapsed time with %d threads is %.10f\n", threads, calTime);
free(array);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9prefixOnePiS_ii
.globl _Z9prefixOnePiS_ii
.p2align 8
.type _Z9prefixOnePiS_ii,@function
_Z9prefixOnePiS_ii:
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s5, 1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_9
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v3, v1
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_mov_b32 s0, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s0, s0, 1
s_add_i32 s5, s5, 1
s_cmp_eq_u32 s0, s4
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_cmp_eq_u32 s0, 0
s_mov_b32 s1, -1
s_cbranch_scc1 .LBB0_7
v_add_nc_u32_e32 v0, s0, v2
v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v9, v3
s_mov_b32 s1, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v0, v[7:8], off
.LBB0_5:
global_load_b32 v11, v[9:10], off
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s1, s1, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v11
global_store_b32 v[7:8], v0, off
s_cbranch_scc1 .LBB0_5
s_mov_b32 s1, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccz .LBB0_2
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off
s_branch .LBB0_2
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9prefixOnePiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9prefixOnePiS_ii, .Lfunc_end0-_Z9prefixOnePiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9prefixTwoPiiii
.globl _Z9prefixTwoPiiii
.p2align 8
.type _Z9prefixTwoPiiii,@function
_Z9prefixTwoPiiii:
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_4
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cselect_b32 s3, -1, 0
v_cndmask_b32_e64 v1, 2.0, 1.0, s3
s_mov_b32 s3, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v2, v1
v_frexp_exp_i32_f32_e32 v1, v1
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_ldexp_f32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v1
v_add_f32_e32 v5, -1.0, v2
v_add_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v6, v5, v4 :: v_dual_add_f32 v7, -1.0, v3
v_mul_f32_e32 v8, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v2, v2, v7
v_fma_f32 v3, v6, v3, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v6, v2
v_add_f32_e32 v2, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v5, v2 :: v_dual_sub_f32 v8, v2, v8
v_sub_f32_e32 v3, v8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v7
v_sub_f32_e32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v3, v2
v_add_f32_e32 v2, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v4, v2
v_add_f32_e32 v3, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v3, v3
v_sub_f32_e32 v4, v3, v6
v_sub_f32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, v3, v3, -v5
v_add_f32_e32 v6, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v3, v6
v_add_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v7, s3, v6, 0x3e91f4c4
v_sub_f32_e32 v5, v6, v5
v_dual_fmaak_f32 v7, v6, v7, 0x3ecccdef :: v_dual_sub_f32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v6, v7
v_fma_f32 v5, v6, v7, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v5, v4, v7 :: v_dual_mul_f32 v10, v3, v6
v_add_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, v6, v3, -v10
v_dual_sub_f32 v8, v7, v8 :: v_dual_fmac_f32 v11, v6, v2
v_add_f32_e32 v9, 0x3f2aaaaa, v7
v_ldexp_f32 v2, v2, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v5, v5, v8
v_fmac_f32_e32 v11, v4, v3
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, 0x31739010, v5
v_add_f32_e32 v8, 0xbf2aaaaa, v9
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v4, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v10, v11 :: v_dual_sub_f32 v7, v9, v4
v_mul_f32_e32 v8, v6, v4
v_sub_f32_e32 v9, v6, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v5, v7
v_fma_f32 v7, v6, v4, -v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v11, v9
v_fmac_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v4
v_add_f32_e32 v4, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v4, v8
v_mul_f32_e32 v8, 0x3f317218, v1
v_sub_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v1, 0x3f317218, -v8
v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v5, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v5, v3
v_sub_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
v_add_f32_e32 v4, v5, v2
v_fmamk_f32 v1, v1, 0xb102e308, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v4, v5
v_sub_f32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v8, v1
v_add_f32_e32 v6, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v3, v8 :: v_dual_sub_f32 v7, v6, v3
v_dual_sub_f32 v1, v1, v8 :: v_dual_sub_f32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v1, v2
v_sub_f32_e32 v9, v6, v7
v_sub_f32_e32 v3, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v4, v3 :: v_dual_sub_f32 v4, v5, v1
v_add_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v5, v4
v_sub_f32_e32 v2, v2, v4
v_add_f32_e32 v7, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v1, v1, v5 :: v_dual_sub_f32 v4, v7, v6
v_dual_add_f32 v1, v2, v1 :: v_dual_sub_f32 v2, v3, v4
v_cvt_f32_i32_e32 v3, s2
s_load_b32 s2, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
v_add_f32_e32 v2, v7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v2, v7
v_mul_f32_e32 v5, v2, v3
v_sub_f32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v2, v3, v2, -v5
v_cmp_class_f32_e64 vcc_lo, v5, 0x204
v_fmac_f32_e32 v2, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v5, v2
v_cndmask_b32_e32 v3, v1, v5, vcc_lo
v_sub_f32_e32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v3
v_sub_f32_e32 v1, v2, v1
v_cndmask_b32_e64 v4, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v3|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v3, v4 :: v_dual_cndmask_b32 v1, 0, v1
v_mul_f32_e32 v7, 0x3fb8aa3b, v6
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v1, v4, v1
v_fma_f32 v8, v6, 0x3fb8aa3b, -v7
v_rndne_f32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmamk_f32 v8, v6, 0x32a5705f, v8 :: v_dual_sub_f32 v7, v7, v9
v_cvt_i32_f32_e32 v5, v9
v_add_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_ldexp_f32 v2, v7, v5
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v2, vcc_lo
v_fma_f32 v1, v2, v1, v2
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_cvt_i32_f32_e64 v1, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s3, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_or_b32 v0, v0, 1, 1
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s2, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s0, -4
s_addc_u32 s4, s1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s3, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s4, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB1_3:
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB1_3
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9prefixTwoPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9prefixTwoPiiii, .Lfunc_end1-_Z9prefixTwoPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9prefixOnePiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9prefixOnePiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9prefixTwoPiiii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z9prefixTwoPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <math.h>
#include "hip/hip_runtime.h"
#define NUM_BLOCKS 1
#define BLOCK_SIZE 256
#define NUM_MEM 32768
//stage one
__global__ void prefixOne(int *in_array, int *out_array, int unsize, int size)
{
int tid = threadIdx.x;
for(int j = 0; j < unsize; j++){
if (j == 0){
out_array[tid * unsize] = in_array[tid * unsize];
} else {
for(int k = 0; k <= j; k++) {
out_array[tid * unsize + j] += in_array[tid * unsize + k];
}
}
}
}
//stage two
__global__ void prefixTwo(int *in_array, int unsize, int maxid, int idx)
{
int tid = threadIdx.x;
if (tid <= maxid) {
int maxstep = unsize * (int)(powf(2, idx - 1));
for(int j = 0; j < maxstep; j++) {
int startIdx = unsize * (int)(powf(2, idx - 1)) * (1 + 2 * tid);
in_array[startIdx + j] = in_array[startIdx - 1] + in_array[startIdx + j];
}
}
}
void prefixsum(int blocks, int threads, int steps, int *array_h, int size)
{
int *array_d;
int *tmp_one;
int unsize = size/(blocks * threads);
dim3 dim_grid(blocks, 1, 1);
dim3 dim_block(threads, 1, 1);
// allocate tmp_d
hipMalloc((void **)&tmp_one, size * sizeof(int));
//cudaMalloc((void **)&out_array_d, blocks * sizeof(int));
hipMalloc((void **)&array_d, size * sizeof(int));
//copy data from host to device
hipMemcpy(array_d, array_h, size * sizeof(int),
hipMemcpyHostToDevice);
hipMemset(tmp_one, 0, size * sizeof(int));
//do stage 1
prefixOne<<<dim_grid, dim_block>>> (array_d, tmp_one, unsize, size);
if (steps !=0) {
int maxtid = 0;
//do stage 2
for (int i = 1; i <= steps; i++) {
maxtid = (int)pow(2, steps-i) - 1;
prefixTwo<<<dim_grid, dim_block>>>(tmp_one, unsize, maxtid, i);
}
}
hipMemcpy(array_h, tmp_one, size * sizeof(int), hipMemcpyDeviceToHost);
hipFree(array_d);
hipFree(tmp_one);
}
void prepare_numbers(int **array, int count)
{
int *numbers = (int *)malloc(count * sizeof(int));
// load array
for (int i = 0; i < count; i++) {
numbers[i] = 1;
}
*array = numbers;
}
void print_array(int *array, int count)
{
for (int i = 0; i < count; i++) {
printf("%d\t", array[i]);
}
printf("\n");
}
int main()
{
int blocks, threads, max, stepTwo;
int *array;
float calTime;
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
blocks = NUM_BLOCKS;
threads = BLOCK_SIZE;
stepTwo = 8;
max = NUM_MEM;
// pre-init numbers
array = NULL;
prepare_numbers(&array, max);
hipEventRecord(start, 0);
prefixsum(blocks, threads, stepTwo, array, max);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&calTime, start, end);
// print array
// print_array(array, max);
printf("the elapsed time with %d threads is %.10f\n", threads, calTime);
free(array);
return 0;
} | .text
.file "prefix.hip"
.globl _Z24__device_stub__prefixOnePiS_ii # -- Begin function _Z24__device_stub__prefixOnePiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__prefixOnePiS_ii,@function
_Z24__device_stub__prefixOnePiS_ii: # @_Z24__device_stub__prefixOnePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9prefixOnePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__prefixOnePiS_ii, .Lfunc_end0-_Z24__device_stub__prefixOnePiS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__prefixTwoPiiii # -- Begin function _Z24__device_stub__prefixTwoPiiii
.p2align 4, 0x90
.type _Z24__device_stub__prefixTwoPiiii,@function
_Z24__device_stub__prefixTwoPiiii: # @_Z24__device_stub__prefixTwoPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9prefixTwoPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__prefixTwoPiiii, .Lfunc_end1-_Z24__device_stub__prefixTwoPiiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9prefixsumiiiPii
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z9prefixsumiiiPii
.p2align 4, 0x90
.type _Z9prefixsumiiiPii,@function
_Z9prefixsumiiiPii: # @_Z9prefixsumiiiPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebx
movq %rcx, %r15
movl %edx, %ebp
movl %esi, %r14d
imull %edi, %esi
movl %r8d, %eax
cltd
idivl %esi
movl %eax, 20(%rsp) # 4-byte Spill
movl %edi, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r14
movslq %r8d, %r13
shlq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, 136(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r13, 128(%rsp) # 8-byte Spill
movq %r13, %rdx
callq hipMemset
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 48(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
movl %ebx, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9prefixOnePiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
testl %ebp, %ebp
jle .LBB2_7
# %bb.3: # %.lr.ph
decl %ebp
movl $1, %r15d
leaq 40(%rsp), %r13
leaq 96(%rsp), %rbx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
incl %r15d
addl $-1, %ebp
jae .LBB2_7
.LBB2_4: # =>This Inner Loop Header: Depth=1
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
cvttsd2si 144(%rsp), %eax # 8-byte Folded Reload
decl %eax
movq 8(%rsp), %rcx
movq %rcx, 88(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 32(%rsp)
movl %eax, 4(%rsp)
movl %r15d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z9prefixTwoPiiii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_6
.LBB2_7: # %.loopexit
movq 8(%rsp), %rsi
movq 136(%rsp), %rdi # 8-byte Reload
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9prefixsumiiiPii, .Lfunc_end2-_Z9prefixsumiiiPii
.cfi_endproc
# -- End function
.globl _Z15prepare_numbersPPii # -- Begin function _Z15prepare_numbersPPii
.p2align 4, 0x90
.type _Z15prepare_numbersPPii,@function
_Z15prepare_numbersPPii: # @_Z15prepare_numbersPPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %r14
leaq (,%r14,4), %rdi
callq malloc
testl %r14d, %r14d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq %rax, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15prepare_numbersPPii, .Lfunc_end3-_Z15prepare_numbersPPii
.cfi_endproc
# -- End function
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB4_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z11print_arrayPii, .Lfunc_end4-_Z11print_arrayPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB5_1
# %bb.2: # %_Z15prepare_numbersPPii.exit
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1, %edi
movl $256, %esi # imm = 0x100
movl $8, %edx
movq %rbx, %rcx
movl $32768, %r8d # imm = 0x8000
callq _Z9prefixsumiiiPii
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9prefixOnePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9prefixTwoPiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9prefixOnePiS_ii,@object # @_Z9prefixOnePiS_ii
.section .rodata,"a",@progbits
.globl _Z9prefixOnePiS_ii
.p2align 3, 0x0
_Z9prefixOnePiS_ii:
.quad _Z24__device_stub__prefixOnePiS_ii
.size _Z9prefixOnePiS_ii, 8
.type _Z9prefixTwoPiiii,@object # @_Z9prefixTwoPiiii
.globl _Z9prefixTwoPiiii
.p2align 3, 0x0
_Z9prefixTwoPiiii:
.quad _Z24__device_stub__prefixTwoPiiii
.size _Z9prefixTwoPiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "the elapsed time with %d threads is %.10f\n"
.size .L.str.2, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9prefixOnePiS_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9prefixTwoPiiii"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__prefixOnePiS_ii
.addrsig_sym _Z24__device_stub__prefixTwoPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9prefixOnePiS_ii
.addrsig_sym _Z9prefixTwoPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00028e98_00000000-6_prefix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15prepare_numbersPPii
.type _Z15prepare_numbersPPii, @function
_Z15prepare_numbersPPii:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
movslq %esi, %rcx
leaq 0(,%rcx,4), %rbx
movq %rbx, %rdi
call malloc@PLT
testl %r12d, %r12d
jle .L4
movq %rax, %rdx
leaq (%rbx,%rax), %rcx
.L5:
movl $1, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L5
.L4:
movq %rax, 0(%rbp)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z15prepare_numbersPPii, .-_Z15prepare_numbersPPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2072:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L9
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L10:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
.L9:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
.type _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii, @function
_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9prefixOnePiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii, .-_Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
.globl _Z9prefixOnePiS_ii
.type _Z9prefixOnePiS_ii, @function
_Z9prefixOnePiS_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z9prefixOnePiS_ii, .-_Z9prefixOnePiS_ii
.globl _Z31__device_stub__Z9prefixTwoPiiiiPiiii
.type _Z31__device_stub__Z9prefixTwoPiiiiPiiii, @function
_Z31__device_stub__Z9prefixTwoPiiiiPiiii:
.LFB2100:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9prefixTwoPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z31__device_stub__Z9prefixTwoPiiiiPiiii, .-_Z31__device_stub__Z9prefixTwoPiiiiPiiii
.globl _Z9prefixTwoPiiii
.type _Z9prefixTwoPiiii, @function
_Z9prefixTwoPiiii:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9prefixTwoPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z9prefixTwoPiiii, .-_Z9prefixTwoPiiii
.globl _Z9prefixsumiiiPii
.type _Z9prefixsumiiiPii, @function
_Z9prefixsumiiiPii:
.LFB2070:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edx, %ebp
movq %rcx, %r13
movl %r8d, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, %ecx
imull %esi, %ecx
movl %r8d, %eax
cltd
idivl %ecx
movl %eax, %r14d
movl %edi, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %esi, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movslq %r8d, %r12
salq $2, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq %r12, %rdx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L30:
testl %ebp, %ebp
jle .L31
movl $1, %ebx
jmp .L33
.L37:
movl %ebx, %ecx
movl %r14d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z9prefixOnePiS_iiPiS_ii
jmp .L30
.L32:
addl $1, %ebx
cmpl %ebx, %ebp
jl .L31
.L33:
movl %ebp, %eax
subl %ebx, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC2(%rip), %xmm0
call pow@PLT
movsd %xmm0, 8(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
cvttsd2sil 8(%rsp), %edx
subl $1, %edx
movl %ebx, %ecx
movl %r14d, %esi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z9prefixTwoPiiiiPiiii
jmp .L32
.L31:
movl $2, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z9prefixsumiiiPii, .-_Z9prefixsumiiiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "the elapsed time with %d threads is %.10f\n"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
movl $32768, %esi
call _Z15prepare_numbersPPii
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rbx
movl $32768, %r8d
movq %rbx, %rcx
movl $8, %edx
movl $256, %esi
movl $1, %edi
call _Z9prefixsumiiiPii
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl $256, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9prefixTwoPiiii"
.LC5:
.string "_Z9prefixOnePiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9prefixTwoPiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9prefixOnePiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "prefix.hip"
.globl _Z24__device_stub__prefixOnePiS_ii # -- Begin function _Z24__device_stub__prefixOnePiS_ii
.p2align 4, 0x90
.type _Z24__device_stub__prefixOnePiS_ii,@function
_Z24__device_stub__prefixOnePiS_ii: # @_Z24__device_stub__prefixOnePiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9prefixOnePiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__prefixOnePiS_ii, .Lfunc_end0-_Z24__device_stub__prefixOnePiS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__prefixTwoPiiii # -- Begin function _Z24__device_stub__prefixTwoPiiii
.p2align 4, 0x90
.type _Z24__device_stub__prefixTwoPiiii,@function
_Z24__device_stub__prefixTwoPiiii: # @_Z24__device_stub__prefixTwoPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9prefixTwoPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__prefixTwoPiiii, .Lfunc_end1-_Z24__device_stub__prefixTwoPiiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9prefixsumiiiPii
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z9prefixsumiiiPii
.p2align 4, 0x90
.type _Z9prefixsumiiiPii,@function
_Z9prefixsumiiiPii: # @_Z9prefixsumiiiPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebx
movq %rcx, %r15
movl %edx, %ebp
movl %esi, %r14d
imull %edi, %esi
movl %r8d, %eax
cltd
idivl %esi
movl %eax, 20(%rsp) # 4-byte Spill
movl %edi, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r14
movslq %r8d, %r13
shlq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, 136(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r13, 128(%rsp) # 8-byte Spill
movq %r13, %rdx
callq hipMemset
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 48(%rsp)
movl 20(%rsp), %eax # 4-byte Reload
movl %eax, 4(%rsp)
movl %ebx, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9prefixOnePiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
testl %ebp, %ebp
jle .LBB2_7
# %bb.3: # %.lr.ph
decl %ebp
movl $1, %r15d
leaq 40(%rsp), %r13
leaq 96(%rsp), %rbx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=1
incl %r15d
addl $-1, %ebp
jae .LBB2_7
.LBB2_4: # =>This Inner Loop Header: Depth=1
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %ebp, %edi
callq ldexp@PLT
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=1
cvttsd2si 144(%rsp), %eax # 8-byte Folded Reload
decl %eax
movq 8(%rsp), %rcx
movq %rcx, 88(%rsp)
movl 20(%rsp), %ecx # 4-byte Reload
movl %ecx, 32(%rsp)
movl %eax, 4(%rsp)
movl %r15d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z9prefixTwoPiiii, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_6
.LBB2_7: # %.loopexit
movq 8(%rsp), %rsi
movq 136(%rsp), %rdi # 8-byte Reload
movq 128(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9prefixsumiiiPii, .Lfunc_end2-_Z9prefixsumiiiPii
.cfi_endproc
# -- End function
.globl _Z15prepare_numbersPPii # -- Begin function _Z15prepare_numbersPPii
.p2align 4, 0x90
.type _Z15prepare_numbersPPii,@function
_Z15prepare_numbersPPii: # @_Z15prepare_numbersPPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %r14
leaq (,%r14,4), %rdi
callq malloc
testl %r14d, %r14d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq %rax, (%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15prepare_numbersPPii, .Lfunc_end3-_Z15prepare_numbersPPii
.cfi_endproc
# -- End function
.globl _Z11print_arrayPii # -- Begin function _Z11print_arrayPii
.p2align 4, 0x90
.type _Z11print_arrayPii,@function
_Z11print_arrayPii: # @_Z11print_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB4_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z11print_arrayPii, .Lfunc_end4-_Z11print_arrayPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB5_1
# %bb.2: # %_Z15prepare_numbersPPii.exit
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1, %edi
movl $256, %esi # imm = 0x100
movl $8, %edx
movq %rbx, %rcx
movl $32768, %r8d # imm = 0x8000
callq _Z9prefixsumiiiPii
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9prefixOnePiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9prefixTwoPiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9prefixOnePiS_ii,@object # @_Z9prefixOnePiS_ii
.section .rodata,"a",@progbits
.globl _Z9prefixOnePiS_ii
.p2align 3, 0x0
_Z9prefixOnePiS_ii:
.quad _Z24__device_stub__prefixOnePiS_ii
.size _Z9prefixOnePiS_ii, 8
.type _Z9prefixTwoPiiii,@object # @_Z9prefixTwoPiiii
.globl _Z9prefixTwoPiiii
.p2align 3, 0x0
_Z9prefixTwoPiiii:
.quad _Z24__device_stub__prefixTwoPiiii
.size _Z9prefixTwoPiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "the elapsed time with %d threads is %.10f\n"
.size .L.str.2, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9prefixOnePiS_ii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9prefixTwoPiiii"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__prefixOnePiS_ii
.addrsig_sym _Z24__device_stub__prefixTwoPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9prefixOnePiS_ii
.addrsig_sym _Z9prefixTwoPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#define ARRAY_SIZE 16
__global__ void unique_idx_calc_threadIdx(int * input) {
int tid = threadIdx.x+blockIdx.x*blockDim.x;
printf("threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d, value: %d\n", tid, blockIdx.x, blockDim.x, input[tid]);
}
__global__ void unique_gid_calc(int * input) {
int tid = threadIdx.x;
int offset = blockDim.x * blockIdx.x;
int gid = tid + offset;
printf("threadIdx.x: %d, blockIdx.x: %d, gid.x: %d, value: %d\n", tid, blockIdx.x, gid, input[gid]);
}
int main() {
int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
int h_data[] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
for(int i=0; i<ARRAY_SIZE; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int * d_data;
cudaMalloc((void**)&d_data, ARRAY_BYTES);
cudaMemcpy(d_data, h_data, ARRAY_BYTES, cudaMemcpyHostToDevice);
dim3 grid(4);
dim3 block(4);
// unique_idx_calc_threadIdx<<<grid,block>>>(d_data);
unique_gid_calc<<<grid,block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z15unique_gid_calcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R14, R13, c[0x0][0x0], R12 ; /* 0x000000000d0e7a24 */
/* 0x001fc800078e020c */
/*0070*/ IMAD.WIDE R2, R14, R3, c[0x0][0x160] ; /* 0x000058000e027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*00e0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00f0*/ STL.128 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0041e80000100c00 */
/*0100*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*0110*/ MOV R11, 0x180 ; /* 0x00000180000b7802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0160*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0170*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z25unique_idx_calc_threadIdxPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R8, R9, c[0x0][0x0], R8 ; /* 0x0000000009087a24 */
/* 0x001fc800078e0208 */
/*0070*/ IMAD.WIDE R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ LDC.64 R12, c[0x4][R0] ; /* 0x01000000000c7b82 */
/* 0x0000660000000a00 */
/*00f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0100*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0041e80000100c00 */
/*0110*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fc60000000000 */
/*0120*/ MOV R9, 0x190 ; /* 0x0000019000097802 */
/* 0x001fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0170*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0180*/ CALL.ABS.NOINC R12 ; /* 0x000000000c007343 */
/* 0x000fea0003c00000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define ARRAY_SIZE 16
__global__ void unique_idx_calc_threadIdx(int * input) {
int tid = threadIdx.x+blockIdx.x*blockDim.x;
printf("threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d, value: %d\n", tid, blockIdx.x, blockDim.x, input[tid]);
}
__global__ void unique_gid_calc(int * input) {
int tid = threadIdx.x;
int offset = blockDim.x * blockIdx.x;
int gid = tid + offset;
printf("threadIdx.x: %d, blockIdx.x: %d, gid.x: %d, value: %d\n", tid, blockIdx.x, gid, input[gid]);
}
int main() {
int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
int h_data[] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
for(int i=0; i<ARRAY_SIZE; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int * d_data;
cudaMalloc((void**)&d_data, ARRAY_BYTES);
cudaMemcpy(d_data, h_data, ARRAY_BYTES, cudaMemcpyHostToDevice);
dim3 grid(4);
dim3 block(4);
// unique_idx_calc_threadIdx<<<grid,block>>>(d_data);
unique_gid_calc<<<grid,block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | .file "tmpxft_00058dcf_00000000-6_unique_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.type _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, @function
_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, .-_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.globl _Z25unique_idx_calc_threadIdxPi
.type _Z25unique_idx_calc_threadIdxPi, @function
_Z25unique_idx_calc_threadIdxPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25unique_idx_calc_threadIdxPi, .-_Z25unique_idx_calc_threadIdxPi
.globl _Z35__device_stub__Z15unique_gid_calcPiPi
.type _Z35__device_stub__Z15unique_gid_calcPiPi, @function
_Z35__device_stub__Z15unique_gid_calcPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15unique_gid_calcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z15unique_gid_calcPiPi, .-_Z35__device_stub__Z15unique_gid_calcPiPi
.globl _Z15unique_gid_calcPi
.type _Z15unique_gid_calcPi, @function
_Z15unique_gid_calcPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15unique_gid_calcPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15unique_gid_calcPi, .-_Z15unique_gid_calcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $7, 40(%rsp)
movl $14, 44(%rsp)
movl $27, 48(%rsp)
movl $4, 52(%rsp)
movl $3, 56(%rsp)
movl $11, 60(%rsp)
movl $10, 64(%rsp)
movl $13, 68(%rsp)
movl $61, 72(%rsp)
movl $42, 76(%rsp)
movl $50, 80(%rsp)
movl $67, 84(%rsp)
movl $83, 88(%rsp)
movl $22, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r12
leaq .LC0(%rip), %rbp
.L20:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq (%rsp), %rdi
call _Z35__device_stub__Z15unique_gid_calcPiPi
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z15unique_gid_calcPi"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z25unique_idx_calc_threadIdxPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15unique_gid_calcPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define ARRAY_SIZE 16
__global__ void unique_idx_calc_threadIdx(int * input) {
int tid = threadIdx.x+blockIdx.x*blockDim.x;
printf("threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d, value: %d\n", tid, blockIdx.x, blockDim.x, input[tid]);
}
__global__ void unique_gid_calc(int * input) {
int tid = threadIdx.x;
int offset = blockDim.x * blockIdx.x;
int gid = tid + offset;
printf("threadIdx.x: %d, blockIdx.x: %d, gid.x: %d, value: %d\n", tid, blockIdx.x, gid, input[gid]);
}
int main() {
int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
int h_data[] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
for(int i=0; i<ARRAY_SIZE; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int * d_data;
cudaMalloc((void**)&d_data, ARRAY_BYTES);
cudaMemcpy(d_data, h_data, ARRAY_BYTES, cudaMemcpyHostToDevice);
dim3 grid(4);
dim3 block(4);
// unique_idx_calc_threadIdx<<<grid,block>>>(d_data);
unique_gid_calc<<<grid,block>>>(d_data);
cudaDeviceSynchronize();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define ARRAY_SIZE 16
__global__ void unique_idx_calc_threadIdx(int * input) {
int tid = threadIdx.x+blockIdx.x*blockDim.x;
printf("threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d, value: %d\n", tid, blockIdx.x, blockDim.x, input[tid]);
}
__global__ void unique_gid_calc(int * input) {
int tid = threadIdx.x;
int offset = blockDim.x * blockIdx.x;
int gid = tid + offset;
printf("threadIdx.x: %d, blockIdx.x: %d, gid.x: %d, value: %d\n", tid, blockIdx.x, gid, input[gid]);
}
int main() {
int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
int h_data[] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
for(int i=0; i<ARRAY_SIZE; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int * d_data;
hipMalloc((void**)&d_data, ARRAY_BYTES);
hipMemcpy(d_data, h_data, ARRAY_BYTES, hipMemcpyHostToDevice);
dim3 grid(4);
dim3 block(4);
// unique_idx_calc_threadIdx<<<grid,block>>>(d_data);
unique_gid_calc<<<grid,block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define ARRAY_SIZE 16
__global__ void unique_idx_calc_threadIdx(int * input) {
int tid = threadIdx.x+blockIdx.x*blockDim.x;
printf("threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d, value: %d\n", tid, blockIdx.x, blockDim.x, input[tid]);
}
__global__ void unique_gid_calc(int * input) {
int tid = threadIdx.x;
int offset = blockDim.x * blockIdx.x;
int gid = tid + offset;
printf("threadIdx.x: %d, blockIdx.x: %d, gid.x: %d, value: %d\n", tid, blockIdx.x, gid, input[gid]);
}
int main() {
int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
int h_data[] = {23, 9, 7, 14, 27, 4, 3, 11, 10, 13, 61, 42, 50, 67, 83, 22};
for(int i=0; i<ARRAY_SIZE; i++) {
printf("%d ", h_data[i]);
}
printf("\n \n");
int * d_data;
hipMalloc((void**)&d_data, ARRAY_BYTES);
hipMemcpy(d_data, h_data, ARRAY_BYTES, hipMemcpyHostToDevice);
dim3 grid(4);
dim3 block(4);
// unique_idx_calc_threadIdx<<<grid,block>>>(d_data);
unique_gid_calc<<<grid,block>>>(d_data);
hipDeviceSynchronize();
hipDeviceReset();
return 0;
} | .text
.file "unique_index.hip"
.globl _Z40__device_stub__unique_idx_calc_threadIdxPi # -- Begin function _Z40__device_stub__unique_idx_calc_threadIdxPi
.p2align 4, 0x90
.type _Z40__device_stub__unique_idx_calc_threadIdxPi,@function
_Z40__device_stub__unique_idx_calc_threadIdxPi: # @_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z25unique_idx_calc_threadIdxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z40__device_stub__unique_idx_calc_threadIdxPi, .Lfunc_end0-_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__unique_gid_calcPi # -- Begin function _Z30__device_stub__unique_gid_calcPi
.p2align 4, 0x90
.type _Z30__device_stub__unique_gid_calcPi,@function
_Z30__device_stub__unique_gid_calcPi: # @_Z30__device_stub__unique_gid_calcPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15unique_gid_calcPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__unique_gid_calcPi, .Lfunc_end1-_Z30__device_stub__unique_gid_calcPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 23 # 0x17
.long 9 # 0x9
.long 7 # 0x7
.long 14 # 0xe
.LCPI2_1:
.long 27 # 0x1b
.long 4 # 0x4
.long 3 # 0x3
.long 11 # 0xb
.LCPI2_2:
.long 10 # 0xa
.long 13 # 0xd
.long 61 # 0x3d
.long 42 # 0x2a
.LCPI2_3:
.long 50 # 0x32
.long 67 # 0x43
.long 83 # 0x53
.long 22 # 0x16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [23,9,7,14]
movaps %xmm0, 80(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [27,4,3,11]
movaps %xmm0, 96(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [10,13,61,42]
movaps %xmm0, 112(%rsp)
movaps .LCPI2_3(%rip), %xmm0 # xmm0 = [50,67,83,22]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15unique_gid_calcPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25unique_idx_calc_threadIdxPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15unique_gid_calcPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25unique_idx_calc_threadIdxPi,@object # @_Z25unique_idx_calc_threadIdxPi
.section .rodata,"a",@progbits
.globl _Z25unique_idx_calc_threadIdxPi
.p2align 3, 0x0
_Z25unique_idx_calc_threadIdxPi:
.quad _Z40__device_stub__unique_idx_calc_threadIdxPi
.size _Z25unique_idx_calc_threadIdxPi, 8
.type _Z15unique_gid_calcPi,@object # @_Z15unique_gid_calcPi
.globl _Z15unique_gid_calcPi
.p2align 3, 0x0
_Z15unique_gid_calcPi:
.quad _Z30__device_stub__unique_gid_calcPi
.size _Z15unique_gid_calcPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25unique_idx_calc_threadIdxPi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15unique_gid_calcPi"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n "
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__unique_idx_calc_threadIdxPi
.addrsig_sym _Z30__device_stub__unique_gid_calcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25unique_idx_calc_threadIdxPi
.addrsig_sym _Z15unique_gid_calcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00058dcf_00000000-6_unique_index.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.type _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, @function
_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi, .-_Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
.globl _Z25unique_idx_calc_threadIdxPi
.type _Z25unique_idx_calc_threadIdxPi, @function
_Z25unique_idx_calc_threadIdxPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z25unique_idx_calc_threadIdxPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25unique_idx_calc_threadIdxPi, .-_Z25unique_idx_calc_threadIdxPi
.globl _Z35__device_stub__Z15unique_gid_calcPiPi
.type _Z35__device_stub__Z15unique_gid_calcPiPi, @function
_Z35__device_stub__Z15unique_gid_calcPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15unique_gid_calcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z15unique_gid_calcPiPi, .-_Z35__device_stub__Z15unique_gid_calcPiPi
.globl _Z15unique_gid_calcPi
.type _Z15unique_gid_calcPi, @function
_Z15unique_gid_calcPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z15unique_gid_calcPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15unique_gid_calcPi, .-_Z15unique_gid_calcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $23, 32(%rsp)
movl $9, 36(%rsp)
movl $7, 40(%rsp)
movl $14, 44(%rsp)
movl $27, 48(%rsp)
movl $4, 52(%rsp)
movl $3, 56(%rsp)
movl $11, 60(%rsp)
movl $10, 64(%rsp)
movl $13, 68(%rsp)
movl $61, 72(%rsp)
movl $42, 76(%rsp)
movl $50, 80(%rsp)
movl $67, 84(%rsp)
movl $83, 88(%rsp)
movl $22, 92(%rsp)
leaq 32(%rsp), %rbx
leaq 96(%rsp), %r12
leaq .LC0(%rip), %rbp
.L20:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 8(%rsp)
movl $1, 12(%rsp)
movl $4, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceSynchronize@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq (%rsp), %rdi
call _Z35__device_stub__Z15unique_gid_calcPiPi
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z15unique_gid_calcPi"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z25unique_idx_calc_threadIdxPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15unique_gid_calcPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z25unique_idx_calc_threadIdxPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unique_index.hip"
.globl _Z40__device_stub__unique_idx_calc_threadIdxPi # -- Begin function _Z40__device_stub__unique_idx_calc_threadIdxPi
.p2align 4, 0x90
.type _Z40__device_stub__unique_idx_calc_threadIdxPi,@function
_Z40__device_stub__unique_idx_calc_threadIdxPi: # @_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z25unique_idx_calc_threadIdxPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z40__device_stub__unique_idx_calc_threadIdxPi, .Lfunc_end0-_Z40__device_stub__unique_idx_calc_threadIdxPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__unique_gid_calcPi # -- Begin function _Z30__device_stub__unique_gid_calcPi
.p2align 4, 0x90
.type _Z30__device_stub__unique_gid_calcPi,@function
_Z30__device_stub__unique_gid_calcPi: # @_Z30__device_stub__unique_gid_calcPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z15unique_gid_calcPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z30__device_stub__unique_gid_calcPi, .Lfunc_end1-_Z30__device_stub__unique_gid_calcPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 23 # 0x17
.long 9 # 0x9
.long 7 # 0x7
.long 14 # 0xe
.LCPI2_1:
.long 27 # 0x1b
.long 4 # 0x4
.long 3 # 0x3
.long 11 # 0xb
.LCPI2_2:
.long 10 # 0xa
.long 13 # 0xd
.long 61 # 0x3d
.long 42 # 0x2a
.LCPI2_3:
.long 50 # 0x32
.long 67 # 0x43
.long 83 # 0x53
.long 22 # 0x16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [23,9,7,14]
movaps %xmm0, 80(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [27,4,3,11]
movaps %xmm0, 96(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [10,13,61,42]
movaps %xmm0, 112(%rsp)
movaps .LCPI2_3(%rip), %xmm0 # xmm0 = [50,67,83,22]
movaps %xmm0, 128(%rsp)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB2_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z15unique_gid_calcPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
callq hipDeviceReset
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25unique_idx_calc_threadIdxPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15unique_gid_calcPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25unique_idx_calc_threadIdxPi,@object # @_Z25unique_idx_calc_threadIdxPi
.section .rodata,"a",@progbits
.globl _Z25unique_idx_calc_threadIdxPi
.p2align 3, 0x0
_Z25unique_idx_calc_threadIdxPi:
.quad _Z40__device_stub__unique_idx_calc_threadIdxPi
.size _Z25unique_idx_calc_threadIdxPi, 8
.type _Z15unique_gid_calcPi,@object # @_Z15unique_gid_calcPi
.globl _Z15unique_gid_calcPi
.p2align 3, 0x0
_Z15unique_gid_calcPi:
.quad _Z30__device_stub__unique_gid_calcPi
.size _Z15unique_gid_calcPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25unique_idx_calc_threadIdxPi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15unique_gid_calcPi"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n "
.size .Lstr, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__unique_idx_calc_threadIdxPi
.addrsig_sym _Z30__device_stub__unique_gid_calcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25unique_idx_calc_threadIdxPi
.addrsig_sym _Z15unique_gid_calcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void addition(float* d_A, float* d_B, float* d_C, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row < numElements && col < numElements) {
tmp_1 = d_A[col];
__syncthreads();
tmp_2 = d_B[col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
__global__
void additionByRows(float* d_A, float* d_B, float* d_C, int numRows) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numRows && col<numRows){
for(int i=0; i<numRows; i++){
tmp_1 = d_A[row+i*col];
__syncthreads();
tmp_2 = d_B[row+i*col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
__global__
void additionByColumns(float* d_A, float* d_B, float* d_C, int numColumns) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numColumns && col<numColumns){
for(int i=0; i<numColumns; i++){
tmp_1 = d_A[row*i+col];
__syncthreads();
tmp_2 = d_B[row*i+col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
int main() {
// size of matrixes
int numArows = 512;
int numAcolumns = 512;
int numBcolumns = 512;
float *h_A;
float *h_B;
float *h_C;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_A = (float*) malloc( numArows*numAcolumns*sizeof(float));
h_B = (float*) malloc( numAcolumns*numBcolumns*sizeof(float));
h_C = (float*) malloc( numArows*numBcolumns*sizeof(float));
// matrix initialization
for(int i=0; i<numArows*numAcolumns; i++)
h_A[i] = i;
for(int i=0; i<numAcolumns*numBcolumns; i++)
h_B[i] = i;
// allocate data in device
cudaMalloc((void**)&d_A, numArows*numAcolumns*sizeof(float));
cudaMalloc((void**)&d_B, numAcolumns*numBcolumns*sizeof(float));
cudaMalloc((void**)&d_C, numArows*numBcolumns*sizeof(float));
// copy inputs to device
cudaMemcpy(d_A, h_A, numArows*numAcolumns*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, numAcolumns*numBcolumns*sizeof(float),cudaMemcpyHostToDevice);
// launch kernel
int threadsPerBlock = 32;
int n_blocks = ceil(numAcolumns*numAcolumns/32.0);
addition<<<n_blocks, threadsPerBlock>>>(d_A,d_B,d_C, numAcolumns*numAcolumns);
// copy output to host
cudaMemcpy(h_C, d_C, numArows*numBcolumns*sizeof(float),cudaMemcpyDeviceToHost);
// freeing space
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | code for sm_80
Function : _Z17additionByColumnsPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0130*/ IMAD.WIDE R2, R5, R7, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fe200078e0207 */
/*0140*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fd20000011405 */
/*0150*/ @!P1 BRA 0x510 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.WIDE R8, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x0c0fe200078e0207 */
/*0170*/ SHF.L.U32 R15, R5, 0x2, RZ ; /* 0x00000002050f7819 */
/* 0x000fe200000006ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0190*/ IMAD.WIDE R10, R0, R7, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x000fe200078e0207 */
/*01a0*/ MOV R18, R8 ; /* 0x0000000800127202 */
/* 0x000fc60000000f00 */
/*01b0*/ IMAD.MOV.U32 R19, RZ, RZ, R9 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0009 */
/*01c0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*01d0*/ IADD3 R10, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040a7a10 */
/* 0x000fe20007ffe1ff */
/*01e0*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000b */
/*01f0*/ SHF.L.U64.HI R11, R5, 0x2, R6 ; /* 0x00000002050b7819 */
/* 0x000fe40000010206 */
/*0200*/ LDG.E R14, [R18.64] ; /* 0x00000006120e7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R17, RZ, RZ, R9 ; /* 0x000000ffff117224 */
/* 0x002fc600078e0009 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ LDG.E R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea8000c1e1900 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ IADD3 R12, P1, R18, R15, RZ ; /* 0x0000000f120c7210 */
/* 0x000fca0007f3e0ff */
/*0260*/ IMAD.X R13, R19, 0x1, R11, P1 ; /* 0x00000001130d7824 */
/* 0x000fe200008e060b */
/*0270*/ IADD3 R8, P2, R16, R15, RZ ; /* 0x0000000f10087210 */
/* 0x000fca0007f5e0ff */
/*0280*/ IMAD.X R9, R9, 0x1, R11, P2 ; /* 0x0000000109097824 */
/* 0x000fe400010e060b */
/*0290*/ FADD R21, R14, R17 ; /* 0x000000110e157221 */
/* 0x004fca0000000000 */
/*02a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101906 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ LDG.E R23, [R8.64] ; /* 0x0000000608177981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ IADD3 R16, P1, R12, R15, RZ ; /* 0x0000000f0c107210 */
/* 0x000fc80007f3e0ff */
/*0310*/ IADD3.X R17, R13, R11, RZ, P1, !PT ; /* 0x0000000b0d117210 */
/* 0x000fe40000ffe4ff */
/*0320*/ IADD3 R18, P2, R8, R15, RZ ; /* 0x0000000f08127210 */
/* 0x000fca0007f5e0ff */
/*0330*/ IMAD.X R19, R9, 0x1, R11, P2 ; /* 0x0000000109137824 */
/* 0x000fe400010e060b */
/*0340*/ FADD R23, R14, R23 ; /* 0x000000170e177221 */
/* 0x004fca0000000000 */
/*0350*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101906 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ LDG.E R14, [R16.64] ; /* 0x00000006100e7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDG.E R21, [R18.64] ; /* 0x0000000612157981 */
/* 0x001ea8000c1e1900 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03b0*/ IADD3 R8, P1, R16, R15, RZ ; /* 0x0000000f10087210 */
/* 0x000fca0007f3e0ff */
/*03c0*/ IMAD.X R9, R17, 0x1, R11, P1 ; /* 0x0000000111097824 */
/* 0x000fe200008e060b */
/*03d0*/ IADD3 R12, P2, R18, R15, RZ ; /* 0x0000000f120c7210 */
/* 0x000fc80007f5e0ff */
/*03e0*/ IADD3.X R13, R19, R11, RZ, P2, !PT ; /* 0x0000000b130d7210 */
/* 0x000fe200017fe4ff */
/*03f0*/ FADD R21, R14, R21 ; /* 0x000000150e157221 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101906 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ LDG.E R14, [R8.64] ; /* 0x00000006080e7981 */
/* 0x0000a8000c1e1900 */
/*0430*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0440*/ LDG.E R17, [R12.64] ; /* 0x000000060c117981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fc60007ffe0ff */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0470*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*0480*/ IADD3 R18, P2, R8, R15.reuse, RZ ; /* 0x0000000f08127210 */
/* 0x080fe40007f5e0ff */
/*0490*/ IADD3 R16, P3, R12, R15, RZ ; /* 0x0000000f0c107210 */
/* 0x000fe20007f7e0ff */
/*04a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*04b0*/ IMAD.X R19, R9, 0x1, R11.reuse, P2 ; /* 0x0000000109137824 */
/* 0x100fe400010e060b */
/*04c0*/ IMAD.X R9, R13, 0x1, R11, P3 ; /* 0x000000010d097824 */
/* 0x001fc400018e060b */
/*04d0*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101906 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @P1 BRA 0x200 ; /* 0xfffffcf000001947 */
/* 0x000fea000383ffff */
/*0510*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0520*/ IMAD R0, R5.reuse, UR4, R0 ; /* 0x0000000405007c24 */
/* 0x040fe2000f8e0200 */
/*0530*/ SHF.L.U64.HI R12, R5, 0x2, R6 ; /* 0x00000002050c7819 */
/* 0x000fc40000010206 */
/*0540*/ SHF.L.U32 R13, R5, 0x2, RZ ; /* 0x00000002050d7819 */
/* 0x000fe200000006ff */
/*0550*/ IMAD.WIDE R8, R0, R7, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fc800078e0207 */
/*0560*/ IMAD.WIDE R10, R0, R7, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fc800078e0207 */
/*0570*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0580*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000b */
/*0590*/ LDG.E R0, [R6.64] ; /* 0x0000000606007981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05b0*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x0010a2000c1e1900 */
/*05c0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*05f0*/ IADD3 R10, P2, R10, R13.reuse, RZ ; /* 0x0000000d0a0a7210 */
/* 0x080fe40007f5e0ff */
/*0600*/ IADD3 R8, P1, R8, R13, RZ ; /* 0x0000000d08087210 */
/* 0x001fc60007f3e0ff */
/*0610*/ IMAD.X R11, R11, 0x1, R12, P2 ; /* 0x000000010b0b7824 */
/* 0x000fe200010e060c */
/*0620*/ IADD3.X R9, R9, R12, RZ, P1, !PT ; /* 0x0000000c09097210 */
/* 0x000fe20000ffe4ff */
/*0630*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e8000c101906 */
/*0650*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0660*/ @P0 BRA 0x570 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0670*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0680*/ BRA 0x680; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14additionByRowsPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0040*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R4, 0x1, P0 ; /* 0x000000010400780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fca0003f05270 */
/*0130*/ IMAD.WIDE R2, R6, R5, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fcc00078e0205 */
/*0140*/ @!P1 BRA 0x4a0 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.SHL.U32 R14, R6, 0x4, RZ ; /* 0x00000004060e7824 */
/* 0x000fe200078e00ff */
/*0160*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe20000011406 */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0180*/ IADD3 R10, P1, R14, c[0x0][0x160], RZ ; /* 0x000058000e0a7a10 */
/* 0x000fe40007f3e0ff */
/*0190*/ SHF.L.U64.HI R15, R6, 0x2, R7 ; /* 0x00000002060f7819 */
/* 0x000fe40000010207 */
/*01a0*/ IADD3 R14, P2, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0e7a10 */
/* 0x000fe40007f5e0ff */
/*01b0*/ IADD3.X R11, R15.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x000059000f0b7a10 */
/* 0x040fe40000ffe4ff */
/*01c0*/ IADD3 R7, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004077a10 */
/* 0x000fe40007ffe1ff */
/*01d0*/ IADD3.X R15, R15, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b000f0f7a10 */
/* 0x000fc400017fe4ff */
/*01e0*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e000b */
/*0200*/ LDG.E R8, [R12.64] ; /* 0x000000060c087981 */
/* 0x004ea8000c1e1900 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0220*/ LDG.E R9, [R14.64] ; /* 0x000000060e097981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ FADD R17, R8, R9 ; /* 0x0000000908117221 */
/* 0x004fe40000000000 */
/*0260*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc600078e020c */
/*0270*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101906 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDG.E R16, [R8.64] ; /* 0x0000000608107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDG.E R13, [R10.64] ; /* 0x000000060a0d7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020a */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ FADD R19, R16, R13 ; /* 0x0000000d10137221 */
/* 0x004fe40000000000 */
/*02f0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0300*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101906 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0320*/ LDG.E R16, [R12.64] ; /* 0x000000060c107981 */
/* 0x000ea8000c1e1900 */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0340*/ LDG.E R9, [R14.64] ; /* 0x000000060e097981 */
/* 0x000ea8000c1e1900 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ FADD R21, R16, R9 ; /* 0x0000000910157221 */
/* 0x004fc40000000000 */
/*0370*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc600078e020c */
/*0380*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e2000c101906 */
/*0390*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x001fc600078e020e */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03b0*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000e68000c1e1900 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ LDG.E R11, [R16.64] ; /* 0x00000006100b7981 */
/* 0x000e62000c1e1900 */
/*03e0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0210 */
/*0400*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc40003f25270 */
/*0430*/ MOV R14, R12 ; /* 0x0000000c000e7202 */
/* 0x000fe40000000f00 */
/*0440*/ MOV R15, R13 ; /* 0x0000000d000f7202 */
/* 0x000fe20000000f00 */
/*0450*/ FADD R19, R10, R11 ; /* 0x0000000b0a137221 */
/* 0x002fe40000000000 */
/*0460*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0470*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0005e8000c101906 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ @P1 BRA 0x1e0 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*04a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04b0*/ IMAD R8, R0, UR4, R6 ; /* 0x0000000400087c24 */
/* 0x000fc8000f8e0206 */
/*04c0*/ IMAD.WIDE R6, R8, R5, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fc800078e0205 */
/*04d0*/ IMAD.WIDE R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e0205 */
/*04e0*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x0010e8000c1e1900 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x0002e2000c1e1900 */
/*0510*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc400078e0208 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0550*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fc800078e0206 */
/*0560*/ FADD R5, R5, R10 ; /* 0x0000000a05057221 */
/* 0x008fca0000000000 */
/*0570*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e8000c101906 */
/*0580*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0590*/ @P0 BRA 0x4e0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8additionPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R4, R4, R7.reuse, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x080fe400078e0207 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc600078e0207 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0130*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe8000c101904 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void addition(float* d_A, float* d_B, float* d_C, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row < numElements && col < numElements) {
tmp_1 = d_A[col];
__syncthreads();
tmp_2 = d_B[col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
__global__
void additionByRows(float* d_A, float* d_B, float* d_C, int numRows) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numRows && col<numRows){
for(int i=0; i<numRows; i++){
tmp_1 = d_A[row+i*col];
__syncthreads();
tmp_2 = d_B[row+i*col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
__global__
void additionByColumns(float* d_A, float* d_B, float* d_C, int numColumns) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numColumns && col<numColumns){
for(int i=0; i<numColumns; i++){
tmp_1 = d_A[row*i+col];
__syncthreads();
tmp_2 = d_B[row*i+col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
int main() {
// size of matrixes
int numArows = 512;
int numAcolumns = 512;
int numBcolumns = 512;
float *h_A;
float *h_B;
float *h_C;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_A = (float*) malloc( numArows*numAcolumns*sizeof(float));
h_B = (float*) malloc( numAcolumns*numBcolumns*sizeof(float));
h_C = (float*) malloc( numArows*numBcolumns*sizeof(float));
// matrix initialization
for(int i=0; i<numArows*numAcolumns; i++)
h_A[i] = i;
for(int i=0; i<numAcolumns*numBcolumns; i++)
h_B[i] = i;
// allocate data in device
cudaMalloc((void**)&d_A, numArows*numAcolumns*sizeof(float));
cudaMalloc((void**)&d_B, numAcolumns*numBcolumns*sizeof(float));
cudaMalloc((void**)&d_C, numArows*numBcolumns*sizeof(float));
// copy inputs to device
cudaMemcpy(d_A, h_A, numArows*numAcolumns*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, numAcolumns*numBcolumns*sizeof(float),cudaMemcpyHostToDevice);
// launch kernel
int threadsPerBlock = 32;
int n_blocks = ceil(numAcolumns*numAcolumns/32.0);
addition<<<n_blocks, threadsPerBlock>>>(d_A,d_B,d_C, numAcolumns*numAcolumns);
// copy output to host
cudaMemcpy(h_C, d_C, numArows*numBcolumns*sizeof(float),cudaMemcpyDeviceToHost);
// freeing space
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | .file "tmpxft_00142402_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8additionPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8additionPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8additionPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8additionPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8additionPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8additionPfS_S_iPfS_S_i
.globl _Z8additionPfS_S_i
.type _Z8additionPfS_S_i, @function
_Z8additionPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8additionPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8additionPfS_S_i, .-_Z8additionPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L12
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movl $1048576, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $262144, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8additionPfS_S_iPfS_S_i
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14additionByRowsPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i
.globl _Z14additionByRowsPfS_S_i
.type _Z14additionByRowsPfS_S_i, @function
_Z14additionByRowsPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14additionByRowsPfS_S_i, .-_Z14additionByRowsPfS_S_i
.globl _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17additionByColumnsPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i
.globl _Z17additionByColumnsPfS_S_i
.type _Z17additionByColumnsPfS_S_i, @function
_Z17additionByColumnsPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z17additionByColumnsPfS_S_i, .-_Z17additionByColumnsPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17additionByColumnsPfS_S_i"
.LC1:
.string "_Z14additionByRowsPfS_S_i"
.LC2:
.string "_Z8additionPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17additionByColumnsPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14additionByRowsPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8additionPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void addition(float* d_A, float* d_B, float* d_C, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row < numElements && col < numElements) {
tmp_1 = d_A[col];
__syncthreads();
tmp_2 = d_B[col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
__global__
void additionByRows(float* d_A, float* d_B, float* d_C, int numRows) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numRows && col<numRows){
for(int i=0; i<numRows; i++){
tmp_1 = d_A[row+i*col];
__syncthreads();
tmp_2 = d_B[row+i*col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
__global__
void additionByColumns(float* d_A, float* d_B, float* d_C, int numColumns) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numColumns && col<numColumns){
for(int i=0; i<numColumns; i++){
tmp_1 = d_A[row*i+col];
__syncthreads();
tmp_2 = d_B[row*i+col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
int main() {
// size of matrixes
int numArows = 512;
int numAcolumns = 512;
int numBcolumns = 512;
float *h_A;
float *h_B;
float *h_C;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_A = (float*) malloc( numArows*numAcolumns*sizeof(float));
h_B = (float*) malloc( numAcolumns*numBcolumns*sizeof(float));
h_C = (float*) malloc( numArows*numBcolumns*sizeof(float));
// matrix initialization
for(int i=0; i<numArows*numAcolumns; i++)
h_A[i] = i;
for(int i=0; i<numAcolumns*numBcolumns; i++)
h_B[i] = i;
// allocate data in device
cudaMalloc((void**)&d_A, numArows*numAcolumns*sizeof(float));
cudaMalloc((void**)&d_B, numAcolumns*numBcolumns*sizeof(float));
cudaMalloc((void**)&d_C, numArows*numBcolumns*sizeof(float));
// copy inputs to device
cudaMemcpy(d_A, h_A, numArows*numAcolumns*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, numAcolumns*numBcolumns*sizeof(float),cudaMemcpyHostToDevice);
// launch kernel
int threadsPerBlock = 32;
int n_blocks = ceil(numAcolumns*numAcolumns/32.0);
addition<<<n_blocks, threadsPerBlock>>>(d_A,d_B,d_C, numAcolumns*numAcolumns);
// copy output to host
cudaMemcpy(h_C, d_C, numArows*numBcolumns*sizeof(float),cudaMemcpyDeviceToHost);
// freeing space
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void addition(float* d_A, float* d_B, float* d_C, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row < numElements && col < numElements) {
tmp_1 = d_A[col];
__syncthreads();
tmp_2 = d_B[col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
__global__
void additionByRows(float* d_A, float* d_B, float* d_C, int numRows) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numRows && col<numRows){
for(int i=0; i<numRows; i++){
tmp_1 = d_A[row+i*col];
__syncthreads();
tmp_2 = d_B[row+i*col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
__global__
void additionByColumns(float* d_A, float* d_B, float* d_C, int numColumns) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numColumns && col<numColumns){
for(int i=0; i<numColumns; i++){
tmp_1 = d_A[row*i+col];
__syncthreads();
tmp_2 = d_B[row*i+col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
int main() {
// size of matrixes
int numArows = 512;
int numAcolumns = 512;
int numBcolumns = 512;
float *h_A;
float *h_B;
float *h_C;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_A = (float*) malloc( numArows*numAcolumns*sizeof(float));
h_B = (float*) malloc( numAcolumns*numBcolumns*sizeof(float));
h_C = (float*) malloc( numArows*numBcolumns*sizeof(float));
// matrix initialization
for(int i=0; i<numArows*numAcolumns; i++)
h_A[i] = i;
for(int i=0; i<numAcolumns*numBcolumns; i++)
h_B[i] = i;
// allocate data in device
hipMalloc((void**)&d_A, numArows*numAcolumns*sizeof(float));
hipMalloc((void**)&d_B, numAcolumns*numBcolumns*sizeof(float));
hipMalloc((void**)&d_C, numArows*numBcolumns*sizeof(float));
// copy inputs to device
hipMemcpy(d_A, h_A, numArows*numAcolumns*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, numAcolumns*numBcolumns*sizeof(float),hipMemcpyHostToDevice);
// launch kernel
int threadsPerBlock = 32;
int n_blocks = ceil(numAcolumns*numAcolumns/32.0);
addition<<<n_blocks, threadsPerBlock>>>(d_A,d_B,d_C, numAcolumns*numAcolumns);
// copy output to host
hipMemcpy(h_C, d_C, numArows*numBcolumns*sizeof(float),hipMemcpyDeviceToHost);
// freeing space
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void addition(float* d_A, float* d_B, float* d_C, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row < numElements && col < numElements) {
tmp_1 = d_A[col];
__syncthreads();
tmp_2 = d_B[col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
__global__
void additionByRows(float* d_A, float* d_B, float* d_C, int numRows) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numRows && col<numRows){
for(int i=0; i<numRows; i++){
tmp_1 = d_A[row+i*col];
__syncthreads();
tmp_2 = d_B[row+i*col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
__global__
void additionByColumns(float* d_A, float* d_B, float* d_C, int numColumns) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numColumns && col<numColumns){
for(int i=0; i<numColumns; i++){
tmp_1 = d_A[row*i+col];
__syncthreads();
tmp_2 = d_B[row*i+col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
int main() {
// size of matrixes
int numArows = 512;
int numAcolumns = 512;
int numBcolumns = 512;
float *h_A;
float *h_B;
float *h_C;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_A = (float*) malloc( numArows*numAcolumns*sizeof(float));
h_B = (float*) malloc( numAcolumns*numBcolumns*sizeof(float));
h_C = (float*) malloc( numArows*numBcolumns*sizeof(float));
// matrix initialization
for(int i=0; i<numArows*numAcolumns; i++)
h_A[i] = i;
for(int i=0; i<numAcolumns*numBcolumns; i++)
h_B[i] = i;
// allocate data in device
hipMalloc((void**)&d_A, numArows*numAcolumns*sizeof(float));
hipMalloc((void**)&d_B, numAcolumns*numBcolumns*sizeof(float));
hipMalloc((void**)&d_C, numArows*numBcolumns*sizeof(float));
// copy inputs to device
hipMemcpy(d_A, h_A, numArows*numAcolumns*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, numAcolumns*numBcolumns*sizeof(float),hipMemcpyHostToDevice);
// launch kernel
int threadsPerBlock = 32;
int n_blocks = ceil(numAcolumns*numAcolumns/32.0);
addition<<<n_blocks, threadsPerBlock>>>(d_A,d_B,d_C, numAcolumns*numAcolumns);
// copy output to host
hipMemcpy(h_C, d_C, numArows*numBcolumns*sizeof(float),hipMemcpyDeviceToHost);
// freeing space
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8additionPfS_S_i
.globl _Z8additionPfS_S_i
.p2align 8
.type _Z8additionPfS_S_i,@function
_Z8additionPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v2, v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8additionPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8additionPfS_S_i, .Lfunc_end0-_Z8additionPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14additionByRowsPfS_S_i
.globl _Z14additionByRowsPfS_S_i
.p2align 8
.type _Z14additionByRowsPfS_S_i,@function
_Z14additionByRowsPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v1, v0, v2, 0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_3
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[7:8], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f32_e32 v1, v1, v5
global_store_b32 v[3:4], v1, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14additionByRowsPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14additionByRowsPfS_S_i, .Lfunc_end1-_Z14additionByRowsPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17additionByColumnsPfS_S_i
.globl _Z17additionByColumnsPfS_S_i
.p2align 8
.type _Z17additionByColumnsPfS_S_i,@function
_Z17additionByColumnsPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v1, v0, v2, 0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB2_3
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
.p2align 6
.LBB2_2:
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s4, 0
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v1, v[8:9], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add_f32_e32 v1, v1, v3
global_store_b32 v[4:5], v1, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17additionByColumnsPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17additionByColumnsPfS_S_i, .Lfunc_end2-_Z17additionByColumnsPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8additionPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8additionPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14additionByRowsPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14additionByRowsPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17additionByColumnsPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17additionByColumnsPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void addition(float* d_A, float* d_B, float* d_C, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row < numElements && col < numElements) {
tmp_1 = d_A[col];
__syncthreads();
tmp_2 = d_B[col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
__global__
void additionByRows(float* d_A, float* d_B, float* d_C, int numRows) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numRows && col<numRows){
for(int i=0; i<numRows; i++){
tmp_1 = d_A[row+i*col];
__syncthreads();
tmp_2 = d_B[row+i*col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
__global__
void additionByColumns(float* d_A, float* d_B, float* d_C, int numColumns) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float tmp_1, tmp_2;
if(row<numColumns && col<numColumns){
for(int i=0; i<numColumns; i++){
tmp_1 = d_A[row*i+col];
__syncthreads();
tmp_2 = d_B[row*i+col];
__syncthreads();
d_C[row] = tmp_1 + tmp_2;
__syncthreads();
}
}
}
int main() {
// size of matrixes
int numArows = 512;
int numAcolumns = 512;
int numBcolumns = 512;
float *h_A;
float *h_B;
float *h_C;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_A = (float*) malloc( numArows*numAcolumns*sizeof(float));
h_B = (float*) malloc( numAcolumns*numBcolumns*sizeof(float));
h_C = (float*) malloc( numArows*numBcolumns*sizeof(float));
// matrix initialization
for(int i=0; i<numArows*numAcolumns; i++)
h_A[i] = i;
for(int i=0; i<numAcolumns*numBcolumns; i++)
h_B[i] = i;
// allocate data in device
hipMalloc((void**)&d_A, numArows*numAcolumns*sizeof(float));
hipMalloc((void**)&d_B, numAcolumns*numBcolumns*sizeof(float));
hipMalloc((void**)&d_C, numArows*numBcolumns*sizeof(float));
// copy inputs to device
hipMemcpy(d_A, h_A, numArows*numAcolumns*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, numAcolumns*numBcolumns*sizeof(float),hipMemcpyHostToDevice);
// launch kernel
int threadsPerBlock = 32;
int n_blocks = ceil(numAcolumns*numAcolumns/32.0);
addition<<<n_blocks, threadsPerBlock>>>(d_A,d_B,d_C, numAcolumns*numAcolumns);
// copy output to host
hipMemcpy(h_C, d_C, numArows*numBcolumns*sizeof(float),hipMemcpyDeviceToHost);
// freeing space
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} | .text
.file "matrix_addition.hip"
.globl _Z23__device_stub__additionPfS_S_i # -- Begin function _Z23__device_stub__additionPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__additionPfS_S_i,@function
_Z23__device_stub__additionPfS_S_i: # @_Z23__device_stub__additionPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8additionPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__additionPfS_S_i, .Lfunc_end0-_Z23__device_stub__additionPfS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__additionByRowsPfS_S_i # -- Begin function _Z29__device_stub__additionByRowsPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__additionByRowsPfS_S_i,@function
_Z29__device_stub__additionByRowsPfS_S_i: # @_Z29__device_stub__additionByRowsPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14additionByRowsPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__additionByRowsPfS_S_i, .Lfunc_end1-_Z29__device_stub__additionByRowsPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__additionByColumnsPfS_S_i # -- Begin function _Z32__device_stub__additionByColumnsPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__additionByColumnsPfS_S_i,@function
_Z32__device_stub__additionByColumnsPfS_S_i: # @_Z32__device_stub__additionByColumnsPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17additionByColumnsPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z32__device_stub__additionByColumnsPfS_S_i, .Lfunc_end2-_Z32__device_stub__additionByColumnsPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB3_3
# %bb.4:
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
movq 24(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 8160(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $262144, 36(%rsp) # imm = 0x40000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8additionPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 8(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8additionPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14additionByRowsPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17additionByColumnsPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8additionPfS_S_i,@object # @_Z8additionPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8additionPfS_S_i
.p2align 3, 0x0
_Z8additionPfS_S_i:
.quad _Z23__device_stub__additionPfS_S_i
.size _Z8additionPfS_S_i, 8
.type _Z14additionByRowsPfS_S_i,@object # @_Z14additionByRowsPfS_S_i
.globl _Z14additionByRowsPfS_S_i
.p2align 3, 0x0
_Z14additionByRowsPfS_S_i:
.quad _Z29__device_stub__additionByRowsPfS_S_i
.size _Z14additionByRowsPfS_S_i, 8
.type _Z17additionByColumnsPfS_S_i,@object # @_Z17additionByColumnsPfS_S_i
.globl _Z17additionByColumnsPfS_S_i
.p2align 3, 0x0
_Z17additionByColumnsPfS_S_i:
.quad _Z32__device_stub__additionByColumnsPfS_S_i
.size _Z17additionByColumnsPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8additionPfS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14additionByRowsPfS_S_i"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17additionByColumnsPfS_S_i"
.size .L__unnamed_3, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__additionPfS_S_i
.addrsig_sym _Z29__device_stub__additionByRowsPfS_S_i
.addrsig_sym _Z32__device_stub__additionByColumnsPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8additionPfS_S_i
.addrsig_sym _Z14additionByRowsPfS_S_i
.addrsig_sym _Z17additionByColumnsPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142402_00000000-6_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8additionPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8additionPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8additionPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8additionPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8additionPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8additionPfS_S_iPfS_S_i
.globl _Z8additionPfS_S_i
.type _Z8additionPfS_S_i, @function
_Z8additionPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8additionPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8additionPfS_S_i, .-_Z8additionPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbx
movl $1048576, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L12
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movl $1048576, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $262144, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8additionPfS_S_iPfS_S_i
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14additionByRowsPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i
.globl _Z14additionByRowsPfS_S_i
.type _Z14additionByRowsPfS_S_i, @function
_Z14additionByRowsPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14additionByRowsPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14additionByRowsPfS_S_i, .-_Z14additionByRowsPfS_S_i
.globl _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i
.type _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i, @function
_Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17additionByColumnsPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i, .-_Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i
.globl _Z17additionByColumnsPfS_S_i
.type _Z17additionByColumnsPfS_S_i, @function
_Z17additionByColumnsPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17additionByColumnsPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z17additionByColumnsPfS_S_i, .-_Z17additionByColumnsPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17additionByColumnsPfS_S_i"
.LC1:
.string "_Z14additionByRowsPfS_S_i"
.LC2:
.string "_Z8additionPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17additionByColumnsPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14additionByRowsPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8additionPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_addition.hip"
.globl _Z23__device_stub__additionPfS_S_i # -- Begin function _Z23__device_stub__additionPfS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__additionPfS_S_i,@function
_Z23__device_stub__additionPfS_S_i: # @_Z23__device_stub__additionPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8additionPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__additionPfS_S_i, .Lfunc_end0-_Z23__device_stub__additionPfS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__additionByRowsPfS_S_i # -- Begin function _Z29__device_stub__additionByRowsPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__additionByRowsPfS_S_i,@function
_Z29__device_stub__additionByRowsPfS_S_i: # @_Z29__device_stub__additionByRowsPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14additionByRowsPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__additionByRowsPfS_S_i, .Lfunc_end1-_Z29__device_stub__additionByRowsPfS_S_i
.cfi_endproc
# -- End function
.globl _Z32__device_stub__additionByColumnsPfS_S_i # -- Begin function _Z32__device_stub__additionByColumnsPfS_S_i
.p2align 4, 0x90
.type _Z32__device_stub__additionByColumnsPfS_S_i,@function
_Z32__device_stub__additionByColumnsPfS_S_i: # @_Z32__device_stub__additionByColumnsPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17additionByColumnsPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z32__device_stub__additionByColumnsPfS_S_i, .Lfunc_end2-_Z32__device_stub__additionByColumnsPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB3_3
# %bb.4:
leaq 24(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
movq 24(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 8160(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $262144, 36(%rsp) # imm = 0x40000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8additionPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 8(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8additionPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14additionByRowsPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17additionByColumnsPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8additionPfS_S_i,@object # @_Z8additionPfS_S_i
.section .rodata,"a",@progbits
.globl _Z8additionPfS_S_i
.p2align 3, 0x0
_Z8additionPfS_S_i:
.quad _Z23__device_stub__additionPfS_S_i
.size _Z8additionPfS_S_i, 8
.type _Z14additionByRowsPfS_S_i,@object # @_Z14additionByRowsPfS_S_i
.globl _Z14additionByRowsPfS_S_i
.p2align 3, 0x0
_Z14additionByRowsPfS_S_i:
.quad _Z29__device_stub__additionByRowsPfS_S_i
.size _Z14additionByRowsPfS_S_i, 8
.type _Z17additionByColumnsPfS_S_i,@object # @_Z17additionByColumnsPfS_S_i
.globl _Z17additionByColumnsPfS_S_i
.p2align 3, 0x0
_Z17additionByColumnsPfS_S_i:
.quad _Z32__device_stub__additionByColumnsPfS_S_i
.size _Z17additionByColumnsPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8additionPfS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14additionByRowsPfS_S_i"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17additionByColumnsPfS_S_i"
.size .L__unnamed_3, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__additionPfS_S_i
.addrsig_sym _Z29__device_stub__additionByRowsPfS_S_i
.addrsig_sym _Z32__device_stub__additionByColumnsPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8additionPfS_S_i
.addrsig_sym _Z14additionByRowsPfS_S_i
.addrsig_sym _Z17additionByColumnsPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
long layer_sizes[] = {56l * 56 * 96, 28l * 28 * 96, 27l * 27 * 256,
13l * 13 * 256, 13l * 12 * 384, 13l * 12 * 384,
13l * 13 * 256, 6l * 6 * 256};
int num_layers = 8;
int main() {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// long size_to_alloc = layer_sizes[0];
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
int num_pieces = 8;
void *p[num_pieces];
for (int i = 0; i < num_pieces; i++) {
cudaMallocHost(&p[i], size_to_alloc / num_pieces);
}
for (int i = 0; i < num_pieces; i++) {
cudaFreeHost(p[i]);
}
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milli;
cudaEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing pieces(ms): " << milli << endl;
void *p_bulk;
cudaEventRecord(start);
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
cudaMallocHost(&p_bulk, size_to_alloc);
cudaFreeHost(p_bulk);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing bulk(ms): " << milli << endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
long layer_sizes[] = {56l * 56 * 96, 28l * 28 * 96, 27l * 27 * 256,
13l * 13 * 256, 13l * 12 * 384, 13l * 12 * 384,
13l * 13 * 256, 6l * 6 * 256};
int num_layers = 8;
int main() {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// long size_to_alloc = layer_sizes[0];
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
int num_pieces = 8;
void *p[num_pieces];
for (int i = 0; i < num_pieces; i++) {
cudaMallocHost(&p[i], size_to_alloc / num_pieces);
}
for (int i = 0; i < num_pieces; i++) {
cudaFreeHost(p[i]);
}
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milli;
cudaEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing pieces(ms): " << milli << endl;
void *p_bulk;
cudaEventRecord(start);
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
cudaMallocHost(&p_bulk, size_to_alloc);
cudaFreeHost(p_bulk);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing bulk(ms): " << milli << endl;
} | .file "tmpxft_0012e9e3_00000000-6_host_copy_time.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "allocating and freeing pieces(ms): "
.align 8
.LC1:
.string "allocating and freeing bulk(ms): "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -80(%rbp), %rdi
call cudaEventCreate@PLT
leaq -72(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
cmpl $0, num_layers(%rip)
jle .L4
movl $0, %r15d
jmp .L10
.L6:
subq $64, %rsp
orq $0, 56(%rsp)
movq %rsp, %rbx
leaq 7(%rdx), %r14
testq %rdx, %rdx
cmovns %rdx, %r14
sarq $3, %r14
movq %rbx, %r12
leaq 64(%rbx), %r13
.L8:
movq %r14, %rsi
movq %rbx, %rdi
call cudaMallocHost@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L8
.L9:
movq (%r12), %rdi
call cudaFreeHost@PLT
addq $8, %r12
cmpq %r13, %r12
jne .L9
movq -104(%rbp), %rsp
addq $1, %r15
cmpl %r15d, num_layers(%rip)
jle .L4
.L10:
movq %rsp, -104(%rbp)
leaq layer_sizes(%rip), %rax
movq (%rax,%r15,8), %rdx
movq %rsp, %rax
.L5:
cmpq %rax, %rsp
je .L6
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L5
.L4:
movl $0, %esi
movq -72(%rbp), %rdi
call cudaEventRecord@PLT
movq -72(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -84(%rbp), %rdi
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -84(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
cmpl $0, num_layers(%rip)
jle .L11
movl $0, %ebx
leaq layer_sizes(%rip), %r12
.L12:
movq (%r12,%rbx,8), %rsi
leaq -64(%rbp), %rdi
call cudaMallocHost@PLT
movq -64(%rbp), %rdi
call cudaFreeHost@PLT
addq $1, %rbx
cmpl %ebx, num_layers(%rip)
jg .L12
.L11:
movl $0, %esi
movq -72(%rbp), %rdi
call cudaEventRecord@PLT
movq -72(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -84(%rbp), %rdi
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -84(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl num_layers
.data
.align 4
.type num_layers, @object
.size num_layers, 4
num_layers:
.long 8
.globl layer_sizes
.align 32
.type layer_sizes, @object
.size layer_sizes, 64
layer_sizes:
.quad 301056
.quad 75264
.quad 186624
.quad 43264
.quad 59904
.quad 59904
.quad 43264
.quad 9216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
long layer_sizes[] = {56l * 56 * 96, 28l * 28 * 96, 27l * 27 * 256,
13l * 13 * 256, 13l * 12 * 384, 13l * 12 * 384,
13l * 13 * 256, 6l * 6 * 256};
int num_layers = 8;
int main() {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
// long size_to_alloc = layer_sizes[0];
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
int num_pieces = 8;
void *p[num_pieces];
for (int i = 0; i < num_pieces; i++) {
cudaMallocHost(&p[i], size_to_alloc / num_pieces);
}
for (int i = 0; i < num_pieces; i++) {
cudaFreeHost(p[i]);
}
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milli;
cudaEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing pieces(ms): " << milli << endl;
void *p_bulk;
cudaEventRecord(start);
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
cudaMallocHost(&p_bulk, size_to_alloc);
cudaFreeHost(p_bulk);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing bulk(ms): " << milli << endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
long layer_sizes[] = {56l * 56 * 96, 28l * 28 * 96, 27l * 27 * 256,
13l * 13 * 256, 13l * 12 * 384, 13l * 12 * 384,
13l * 13 * 256, 6l * 6 * 256};
int num_layers = 8;
int main() {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// long size_to_alloc = layer_sizes[0];
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
int num_pieces = 8;
void *p[num_pieces];
for (int i = 0; i < num_pieces; i++) {
hipHostMalloc(&p[i], size_to_alloc / num_pieces, hipHostMallocDefault);
}
for (int i = 0; i < num_pieces; i++) {
hipHostFree(p[i]);
}
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milli;
hipEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing pieces(ms): " << milli << endl;
void *p_bulk;
hipEventRecord(start);
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
hipHostMalloc(&p_bulk, size_to_alloc, hipHostMallocDefault);
hipHostFree(p_bulk);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing bulk(ms): " << milli << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
long layer_sizes[] = {56l * 56 * 96, 28l * 28 * 96, 27l * 27 * 256,
13l * 13 * 256, 13l * 12 * 384, 13l * 12 * 384,
13l * 13 * 256, 6l * 6 * 256};
int num_layers = 8;
int main() {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// long size_to_alloc = layer_sizes[0];
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
int num_pieces = 8;
void *p[num_pieces];
for (int i = 0; i < num_pieces; i++) {
hipHostMalloc(&p[i], size_to_alloc / num_pieces, hipHostMallocDefault);
}
for (int i = 0; i < num_pieces; i++) {
hipHostFree(p[i]);
}
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milli;
hipEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing pieces(ms): " << milli << endl;
void *p_bulk;
hipEventRecord(start);
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
hipHostMalloc(&p_bulk, size_to_alloc, hipHostMallocDefault);
hipHostFree(p_bulk);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing bulk(ms): " << milli << endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
long layer_sizes[] = {56l * 56 * 96, 28l * 28 * 96, 27l * 27 * 256,
13l * 13 * 256, 13l * 12 * 384, 13l * 12 * 384,
13l * 13 * 256, 6l * 6 * 256};
int num_layers = 8;
int main() {
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
// long size_to_alloc = layer_sizes[0];
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
int num_pieces = 8;
void *p[num_pieces];
for (int i = 0; i < num_pieces; i++) {
hipHostMalloc(&p[i], size_to_alloc / num_pieces, hipHostMallocDefault);
}
for (int i = 0; i < num_pieces; i++) {
hipHostFree(p[i]);
}
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milli;
hipEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing pieces(ms): " << milli << endl;
void *p_bulk;
hipEventRecord(start);
for (int j = 0; j < num_layers; j++) {
long size_to_alloc = layer_sizes[j];
hipHostMalloc(&p_bulk, size_to_alloc, hipHostMallocDefault);
hipHostFree(p_bulk);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
cout << "allocating and freeing bulk(ms): " << milli << endl;
} | .text
.file "host_copy_time.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $40, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
leaq -64(%rbp), %rdi
callq hipEventCreate
leaq -56(%rbp), %rdi
callq hipEventCreate
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $0, num_layers(%rip)
jle .LBB0_7
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_5 Depth 2
movq %rsp, %r15
movq layer_sizes(,%r14,8), %rax
movq %rsp, %r12
addq $-64, %r12
movq %r12, %rsp
leaq 7(%rax), %rbx
testq %rax, %rax
cmovnsq %rax, %rbx
sarq $3, %rbx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r12,%r13), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
addq $8, %r13
cmpq $64, %r13
jne .LBB0_3
# %bb.4: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%rbx,8), %rdi
callq hipHostFree
incq %rbx
cmpq $8, %rbx
jne .LBB0_5
# %bb.6: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rsp
incq %r14
movslq num_layers(%rip), %rax
cmpq %rax, %r14
jl .LBB0_2
.LBB0_7: # %._crit_edge
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rdi
callq hipEventSynchronize
movq -64(%rbp), %rsi
movq -56(%rbp), %rdx
leaq -44(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -44(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_19
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_10
# %bb.9:
movzbl 67(%rbx), %ecx
jmp .LBB0_11
.LBB0_10:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $0, num_layers(%rip)
jle .LBB0_14
# %bb.12: # %.lr.ph31.preheader
xorl %r14d, %r14d
leaq -72(%rbp), %rbx
.p2align 4, 0x90
.LBB0_13: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
movq layer_sizes(,%r14,8), %rsi
movq %rbx, %rdi
xorl %edx, %edx
callq hipHostMalloc
movq -72(%rbp), %rdi
callq hipHostFree
incq %r14
movslq num_layers(%rip), %rax
cmpq %rax, %r14
jl .LBB0_13
.LBB0_14: # %._crit_edge32
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rdi
callq hipEventSynchronize
movq -64(%rbp), %rsi
movq -56(%rbp), %rdx
leaq -44(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -44(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB0_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB0_18
.LBB0_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB0_19:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type layer_sizes,@object # @layer_sizes
.data
.globl layer_sizes
.p2align 4, 0x0
layer_sizes:
.quad 301056 # 0x49800
.quad 75264 # 0x12600
.quad 186624 # 0x2d900
.quad 43264 # 0xa900
.quad 59904 # 0xea00
.quad 59904 # 0xea00
.quad 43264 # 0xa900
.quad 9216 # 0x2400
.size layer_sizes, 64
.type num_layers,@object # @num_layers
.globl num_layers
.p2align 2, 0x0
num_layers:
.long 8 # 0x8
.size num_layers, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "allocating and freeing pieces(ms): "
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "allocating and freeing bulk(ms): "
.size .L.str.1, 34
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012e9e3_00000000-6_host_copy_time.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "allocating and freeing pieces(ms): "
.align 8
.LC1:
.string "allocating and freeing bulk(ms): "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $72, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -80(%rbp), %rdi
call cudaEventCreate@PLT
leaq -72(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
cmpl $0, num_layers(%rip)
jle .L4
movl $0, %r15d
jmp .L10
.L6:
subq $64, %rsp
orq $0, 56(%rsp)
movq %rsp, %rbx
leaq 7(%rdx), %r14
testq %rdx, %rdx
cmovns %rdx, %r14
sarq $3, %r14
movq %rbx, %r12
leaq 64(%rbx), %r13
.L8:
movq %r14, %rsi
movq %rbx, %rdi
call cudaMallocHost@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L8
.L9:
movq (%r12), %rdi
call cudaFreeHost@PLT
addq $8, %r12
cmpq %r13, %r12
jne .L9
movq -104(%rbp), %rsp
addq $1, %r15
cmpl %r15d, num_layers(%rip)
jle .L4
.L10:
movq %rsp, -104(%rbp)
leaq layer_sizes(%rip), %rax
movq (%rax,%r15,8), %rdx
movq %rsp, %rax
.L5:
cmpq %rax, %rsp
je .L6
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L5
.L4:
movl $0, %esi
movq -72(%rbp), %rdi
call cudaEventRecord@PLT
movq -72(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -84(%rbp), %rdi
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -84(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
cmpl $0, num_layers(%rip)
jle .L11
movl $0, %ebx
leaq layer_sizes(%rip), %r12
.L12:
movq (%r12,%rbx,8), %rsi
leaq -64(%rbp), %rdi
call cudaMallocHost@PLT
movq -64(%rbp), %rdi
call cudaFreeHost@PLT
addq $1, %rbx
cmpl %ebx, num_layers(%rip)
jg .L12
.L11:
movl $0, %esi
movq -72(%rbp), %rdi
call cudaEventRecord@PLT
movq -72(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -84(%rbp), %rdi
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -84(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl num_layers
.data
.align 4
.type num_layers, @object
.size num_layers, 4
num_layers:
.long 8
.globl layer_sizes
.align 32
.type layer_sizes, @object
.size layer_sizes, 64
layer_sizes:
.quad 301056
.quad 75264
.quad 186624
.quad 43264
.quad 59904
.quad 59904
.quad 43264
.quad 9216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "host_copy_time.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $40, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
leaq -64(%rbp), %rdi
callq hipEventCreate
leaq -56(%rbp), %rdi
callq hipEventCreate
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $0, num_layers(%rip)
jle .LBB0_7
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_5 Depth 2
movq %rsp, %r15
movq layer_sizes(,%r14,8), %rax
movq %rsp, %r12
addq $-64, %r12
movq %r12, %rsp
leaq 7(%rax), %rbx
testq %rax, %rax
cmovnsq %rax, %rbx
sarq $3, %rbx
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_3: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r12,%r13), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostMalloc
addq $8, %r13
cmpq $64, %r13
jne .LBB0_3
# %bb.4: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%rbx,8), %rdi
callq hipHostFree
incq %rbx
cmpq $8, %rbx
jne .LBB0_5
# %bb.6: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rsp
incq %r14
movslq num_layers(%rip), %rax
cmpq %rax, %r14
jl .LBB0_2
.LBB0_7: # %._crit_edge
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rdi
callq hipEventSynchronize
movq -64(%rbp), %rsi
movq -56(%rbp), %rdx
leaq -44(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -44(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_19
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_10
# %bb.9:
movzbl 67(%rbx), %ecx
jmp .LBB0_11
.LBB0_10:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq -64(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
cmpl $0, num_layers(%rip)
jle .LBB0_14
# %bb.12: # %.lr.ph31.preheader
xorl %r14d, %r14d
leaq -72(%rbp), %rbx
.p2align 4, 0x90
.LBB0_13: # %.lr.ph31
# =>This Inner Loop Header: Depth=1
movq layer_sizes(,%r14,8), %rsi
movq %rbx, %rdi
xorl %edx, %edx
callq hipHostMalloc
movq -72(%rbp), %rdi
callq hipHostFree
incq %r14
movslq num_layers(%rip), %rax
cmpq %rax, %r14
jl .LBB0_13
.LBB0_14: # %._crit_edge32
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rdi
callq hipEventSynchronize
movq -64(%rbp), %rsi
movq -56(%rbp), %rdx
leaq -44(%rbp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -44(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
je .LBB0_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB0_18
.LBB0_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB0_19:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type layer_sizes,@object # @layer_sizes
.data
.globl layer_sizes
.p2align 4, 0x0
layer_sizes:
.quad 301056 # 0x49800
.quad 75264 # 0x12600
.quad 186624 # 0x2d900
.quad 43264 # 0xa900
.quad 59904 # 0xea00
.quad 59904 # 0xea00
.quad 43264 # 0xa900
.quad 9216 # 0x2400
.size layer_sizes, 64
.type num_layers,@object # @num_layers
.globl num_layers
.p2align 2, 0x0
num_layers:
.long 8 # 0x8
.size num_layers, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "allocating and freeing pieces(ms): "
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "allocating and freeing bulk(ms): "
.size .L.str.1, 34
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | template<typename T>
__device__ void getRow(const T* matrix, const int row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[row * cols + index];
}
template<typename T>
__device__ void matrixAddRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowAddMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixSubRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] - row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowSubMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] - matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixTimesRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowTimesMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixDivRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] / row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowDivMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] / matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | template<typename T>
__device__ void getRow(const T* matrix, const int row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[row * cols + index];
}
template<typename T>
__device__ void matrixAddRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowAddMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixSubRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] - row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowSubMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] - matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixTimesRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowTimesMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixDivRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] / row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowDivMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] / matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
} | .file "tmpxft_0006acc5_00000000-6_Row.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | template<typename T>
__device__ void getRow(const T* matrix, const int row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[row * cols + index];
}
template<typename T>
__device__ void matrixAddRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowAddMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixSubRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] - row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowSubMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] - matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixTimesRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowTimesMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixDivRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] / row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowDivMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] / matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
} | #include <hip/hip_runtime.h>
template<typename T>
__device__ void getRow(const T* matrix, const int row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[row * cols + index];
}
template<typename T>
__device__ void matrixAddRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowAddMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixSubRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] - row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowSubMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] - matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixTimesRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowTimesMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixDivRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] / row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowDivMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] / matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
template<typename T>
__device__ void getRow(const T* matrix, const int row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[row * cols + index];
}
template<typename T>
__device__ void matrixAddRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowAddMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixSubRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] - row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowSubMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] - matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixTimesRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowTimesMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixDivRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] / row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowDivMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] / matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
template<typename T>
__device__ void getRow(const T* matrix, const int row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int tx = threadIdx.x;
int index = bx * blockDim.x + tx;
result[index] = matrix[row * cols + index];
}
template<typename T>
__device__ void matrixAddRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowAddMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] + row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixSubRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] - row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowSubMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] - matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixTimesRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowTimesMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] * row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void matrixDivRow(const T* matrix, const T* row, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = matrix[rowIndex * cols + colIndex] / row[colIndex];
result[rowIndex * cols + colIndex] = value;
}
}
template<typename T>
__device__ void rowDivMatrix(const T* row, const T* matrix, T* result,
const int rows, const int cols) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int rowIndex = by * blockDim.y + ty;
int colIndex = bx * blockDim.x + tx;
if (rowIndex < rows && colIndex < cols) {
T value = row[colIndex] / matrix[rowIndex * cols + colIndex];
result[rowIndex * cols + colIndex] = value;
}
} | .text
.file "Row.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006acc5_00000000-6_Row.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Row.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cstdio>
#include<cstdlib>
#include<iostream>
#define DFL_LEN 32
#define MAX_THREADS_PER_BLOCK 1024 //supported by hardware, run ./deviceQuery to determine
//cuda error checking
#define check_error(ans) {cudaCheckError((ans),__FILE__,__LINE__);}
inline void cudaCheckError(cudaError_t e,const char *file,int line,bool abort = true){
if(e != cudaSuccess){
fprintf(stderr,"GPUassert: %s\nFile: %s\nLine: %d\n",cudaGetErrorString(e),file,line);
if(abort) exit(e);
}
}
//end of error checking
typedef long int g_type;
//struct declarations and global variables begin here
struct vertex{
g_type number;
g_type start;
int n;
};
struct map{
g_type node;
g_type index;
};
struct entry{
g_type edge;
double val;
};
g_type *edges;
g_type edges_length;
g_type edges_size;
g_type edges_itr;
struct vertex *vertex_list;
g_type vertex_length;
g_type vertex_size;
g_type vertex_itr;
struct entry *transitions;
struct map *node_map;
double *ranks;
double *result;
//end of struct and global definitions
//start of interface
int init_edges(){
if(edges != NULL)
return 0;
edges = (g_type *)malloc(DFL_LEN * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
edges_size = DFL_LEN;
edges_length = 0;
edges_itr = 0;
return 1;
}
void delete_edges(){
edges_length = 0;
edges_size = DFL_LEN;
edges_itr = 0;
if(edges != NULL)
free(edges);
}
int add_edge(int edge){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(edges_length == edges_size){
edges_size *= 2;
edges = (g_type *)realloc(edges,edges_size * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
edges[edges_length] = edge;
edges_length++;
return 1;
}
int get_edge(g_type *e){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(e == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
g_type val = edges[edges_itr];
edges_itr++;
if(edges_itr >= edges_size){
edges_itr = edges_itr % edges_size;
}
*e = val;
return 1;
}
void reset_edge(){
edges_itr = 0;
}
void move_edge(g_type index){
edges_itr = index;
}
int init_vertices(){
if(vertex_list != NULL)
return 0;
vertex_list = (struct vertex *)malloc(DFL_LEN * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
vertex_length = 0;
vertex_size = DFL_LEN;
vertex_itr = 0;
return 1;
}
void delete_vertices(){
vertex_itr = 0;
vertex_length = 0;
vertex_size = 0;
if(vertex_list != NULL)
free(vertex_list);
}
int add_vertex(struct vertex v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(vertex_length == vertex_size){
vertex_size *= 2;
vertex_list = (struct vertex *)realloc(vertex_list,vertex_size * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
vertex_list[vertex_length].number = v.number;
vertex_list[vertex_length].n = v.n;
vertex_list[vertex_length].start = v.start;
g_type temp = vertex_length;
vertex_length++;
return temp;
}
int get_vertex(struct vertex *v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
v->number = vertex_list[vertex_itr].number;
v->start = vertex_list[vertex_itr].start;
v->n = vertex_list[vertex_itr].n;
vertex_itr++;
if(vertex_itr >= vertex_size){
vertex_itr = vertex_itr % vertex_size;
}
return 1;
}
void reset_vertex(){
vertex_itr = 0;
}
void move_vertex(g_type index){
vertex_itr = index;
}
void build_graph(FILE *fp){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(fp == NULL){
fprintf(stderr,"File pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
g_type from,to;
int seen = 0;
g_type cur = -1;
while(fscanf(fp,"%ld %ld",&from,&to) != -1){
if(from == vertex_list[cur].number && vertex_length != 0){
seen = 1;
}
else{
seen = 0;
}
if(!seen){
struct vertex temp;
temp.number = from;
temp.start = edges_length;
temp.n = 0;
cur = add_vertex(temp);
}
add_edge(to);
vertex_list[cur].n++;
}
}
void create_map(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(node_map == NULL){
node_map = (struct map *)malloc(vertex_length * sizeof(struct map));
if(node_map == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
node_map[i].node = vertex_list[i].number;
node_map[i].index = i;
}
}
g_type search_map(g_type node){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(node_map == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
for(int i=0;i<vertex_length;i++){
if(node_map[i].node == node)
return node_map[i].index;
}
return -1;
}
__device__ g_type search_dmap(struct map *d_map,g_type *d_vlength,g_type node){
if(d_map == NULL){
return -1;
}
g_type len = *d_vlength;
for(g_type i=0;i<len;i++){
if(d_map[i].node == node)
return d_map[i].index;
}
return -1;
}
void delete_map(){
if(node_map != NULL)
free(node_map);
}
void init_ranks(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(ranks == NULL){
ranks = (double *)malloc(vertex_length * sizeof(double));
if(ranks == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
ranks[i] = 0.25;
}
}
void delete_ranks(){
if(ranks != NULL)
free(ranks);
}
void init_transitions(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(transitions == NULL){
transitions = (struct entry *)malloc(edges_length * sizeof(struct entry));
if(transitions == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(g_type i=0;i<vertex_length;i++){
g_type start = vertex_list[i].start;
g_type j = start;
int n = vertex_list[i].n;
while(j < start + n){
transitions[j].edge = edges[j];
transitions[j].val = 1.0 / vertex_list[i].n;
j++;
}
}
}
void delete_transitions(){
if(transitions != NULL)
free(transitions);
}
void init_result(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(result == NULL){
result = (double *)malloc(vertex_length * sizeof(double));
if(result == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
result[i] = 0.0;
}
}
void delete_result(){
if(result != NULL)
free(result);
}
int pagerank(){
for(int i=0;i<vertex_length;i++){
for(int j = vertex_list[i].start; j < vertex_list[i].start + vertex_list[i].n; j++){
double temp = transitions[j].val * ranks[i];
g_type index = search_map(transitions[j].edge);
result[index] += temp;
}
}
return 1;
}
void update_ranks(){
for(int i=0;i<vertex_length;i++){
ranks[i] = result[i];
result[i] = 0.0;
}
}
//end of interface
//CUDA kernels
__global__ void multiply_kernel(struct vertex *d_vertices,struct entry *d_transitions,struct map *d_map,double *d_ranks,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
double b = d_ranks[threadId];
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
double a = d_transitions[i].val;
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double res = a * b;
double temp = d_tempranks[index];
__syncthreads();
temp += res;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
//deprecated
__global__ void add_kernel(struct vertex *d_vertices,struct entry *d_transitions,double *d_res,struct map *d_map,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double val = d_res[i];
double temp = d_tempranks[index];
__syncthreads();
temp += val;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
__global__ void update_kernel(double *d_tempranks,double *d_ranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
d_ranks[threadId] = d_tempranks[threadId];
}
}
//end of CUDA kernels
//main program begins here
int main(int argc,char **argv){
if(argc != 4){
fprintf(stderr,"Correct usage: %s <pathToGraph> <numIterations> <serial = 0/parallel = 1>\n",argv[0]);
exit(1);
}
FILE *fp = fopen(argv[1],"r");
const int iterations = atoi(argv[2]);
const int mode = atoi(argv[3]);
init_vertices();
init_edges();
build_graph(fp);
create_map();
init_ranks();
init_transitions();
if(mode == 1){
//initializing device memory
g_type *d_elength;
check_error(cudaMalloc((void **)&d_elength,sizeof(g_type)));
check_error(cudaMemcpy(d_elength,&edges_length,sizeof(g_type),cudaMemcpyHostToDevice));
g_type *d_vlength;
check_error(cudaMalloc((void **)&d_vlength,sizeof(g_type)));
check_error(cudaMemcpy(d_vlength,&vertex_length,sizeof(g_type),cudaMemcpyHostToDevice));
struct vertex *d_vertices;
check_error(cudaMalloc((void **)&d_vertices,vertex_length * sizeof(struct vertex)));
check_error(cudaMemcpy(d_vertices,vertex_list,vertex_length * sizeof(struct vertex),cudaMemcpyHostToDevice));
struct entry *d_transitions;
check_error(cudaMalloc((void **)&d_transitions,edges_length * sizeof(struct entry)));
check_error(cudaMemcpy(d_transitions,transitions,edges_length * sizeof(struct entry),cudaMemcpyHostToDevice));
struct map *d_map;
check_error(cudaMalloc((void **)&d_map,vertex_length * sizeof(struct map)));
check_error(cudaMemcpy(d_map,node_map,vertex_length * sizeof(struct map),cudaMemcpyHostToDevice));
double *d_ranks;
check_error(cudaMalloc((void **)&d_ranks,vertex_length * sizeof(double)));
check_error(cudaMemcpy(d_ranks,ranks,vertex_length * sizeof(double),cudaMemcpyHostToDevice));
double *d_res;
check_error(cudaMalloc((void **)&d_res,edges_length * sizeof(double)));
double *d_tempranks;
check_error(cudaMalloc((void **)&d_tempranks,vertex_length * sizeof(double)));
//pagerank iterations begin here: Power method
int blocks = 1;
int threads = vertex_length;
if(vertex_length > MAX_THREADS_PER_BLOCK){
blocks = (int)ceil(vertex_length / (double)MAX_THREADS_PER_BLOCK);
threads = MAX_THREADS_PER_BLOCK;
}
int counter = 0;
clock_t begin = clock();
while(counter < iterations){
check_error(cudaMemset(d_res,0.0,edges_length * sizeof(double)));
check_error(cudaMemset(d_tempranks,0.0,vertex_length * sizeof(double)));
multiply_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_map,d_ranks,d_tempranks,d_vlength);
cudaDeviceSynchronize();
//add_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_res,d_map,d_tempranks,d_vlength);
//cudaDeviceSynchronize();
update_kernel<<<blocks,threads>>>(d_tempranks,d_ranks,d_vlength);
cudaDeviceSynchronize();
counter++;
}
clock_t end = clock();
//end of pagerank iterations
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
double *res;
res = (double *)malloc(vertex_length * sizeof(double));
check_error(cudaMemcpy(res,d_ranks,vertex_length * sizeof(double),cudaMemcpyDeviceToHost));
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",res[i]);
}
free(res);
printf("%lf s\n",time_spent);
check_error(cudaFree(d_elength));
check_error(cudaFree(d_vlength));
check_error(cudaFree(d_vertices));
check_error(cudaFree(d_transitions));
check_error(cudaFree(d_map));
check_error(cudaFree(d_ranks));
check_error(cudaFree(d_res));
check_error(cudaFree(d_tempranks));
}
else{
clock_t begin = clock();
init_result();
int counter = 0;
while(counter < iterations){
if(!pagerank()){
fprintf(stderr,"Pagerank failed in iteration: %d\n",counter);
break;
}
update_ranks();
counter++;
}
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",ranks[i]);
}
printf("%lf s\n",time_spent);
}
//end of device memory initialization
delete_edges();
delete_vertices();
delete_ranks();
delete_transitions();
delete_map();
delete_result();
return 0;
} | code for sm_80
Function : _Z13update_kernelPdS_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fcc00078e00ff */
/*0040*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R0, RZ, 0x1f, R5 ; /* 0x0000001fff007819 */
/* 0x000fe40000011405 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.AND.EX P0, PT, R3, R0, PT, P0 ; /* 0x000000000300720c */
/* 0x000fda0003f04300 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.SHL.U32 R4, R5.reuse, 0x8, RZ ; /* 0x0000000805047824 */
/* 0x040fe200078e00ff */
/*00d0*/ SHF.L.U64.HI R0, R5, 0x3, R0 ; /* 0x0000000305007819 */
/* 0x000fc80000010200 */
/*00e0*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fcc00007fe4ff */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fca00007fe4ff */
/*0130*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R9, RZ, 0x1f, R7 ; /* 0x0000001fff097819 */
/* 0x000fe40000011407 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.AND.EX P0, PT, R5, R9, PT, P0 ; /* 0x000000090500720c */
/* 0x000fda0003f04300 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x18 ; /* 0x00000018ff067424 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD R9, R9, 0x18, RZ ; /* 0x0000001809097824 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0006 */
/*00f0*/ IMAD.IADD R7, R7, 0x1, R9 ; /* 0x0000000107077824 */
/* 0x000fca00078e0209 */
/*0100*/ LDG.E R0, [R6.64+0x10] ; /* 0x0000100406007981 */
/* 0x000ea4000c1e1900 */
/*0110*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fda0003f06270 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ LDG.E.64 R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000164000c1e1b00 */
/*0140*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05070 */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fc600078e00ff */
/*0160*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f05300 */
/*0170*/ @!P0 BRA 0x2f0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0180*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ BSSY B0, 0x2f0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x004fc80003f06070 */
/*01b0*/ ISETP.GE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f06300 */
/*01c0*/ @!P0 BRA 0x2e0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*01d0*/ LEA R10, P0, R4, c[0x0][0x168], 0x4 ; /* 0x00005a00040a7a11 */
/* 0x020fc800078020ff */
/*01e0*/ LEA.HI.X R11, R4, c[0x0][0x16c], R5, 0x4, P0 ; /* 0x00005b00040b7a11 */
/* 0x000fca00000f2405 */
/*01f0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000362000c1e1b00 */
/*0200*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fcc000001ff00 */
/*0210*/ LEA R14, P0, R17, c[0x0][0x178], 0x4 ; /* 0x00005e00110e7a11 */
/* 0x000fc800078020ff */
/*0220*/ LEA.HI.X R15, R17, c[0x0][0x17c], R16, 0x4, P0 ; /* 0x00005f00110f7a11 */
/* 0x000fca00000f2410 */
/*0230*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x002ea4000c1e1b00 */
/*0240*/ ISETP.NE.U32.AND P0, PT, R10, R12, PT ; /* 0x0000000c0a00720c */
/* 0x024fc80003f05070 */
/*0250*/ ISETP.NE.AND.EX P0, PT, R11, R13, PT, P0 ; /* 0x0000000d0b00720c */
/* 0x000fda0003f05300 */
/*0260*/ @!P0 BRA 0x2d0 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R17, P0, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fca0007f1e0ff */
/*0280*/ IMAD.X R16, RZ, RZ, R16, P0 ; /* 0x000000ffff107224 */
/* 0x000fe200000e0610 */
/*0290*/ ISETP.GE.U32.AND P0, PT, R17, R8, PT ; /* 0x000000081100720c */
/* 0x000fc80003f06070 */
/*02a0*/ ISETP.GE.AND.EX P0, PT, R16, R9, PT, P0 ; /* 0x000000091000720c */
/* 0x000fda0003f06300 */
/*02b0*/ @!P0 BRA 0x210 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*02c0*/ BRA 0x2e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E R0, [R14.64+0x8] ; /* 0x000008040e007981 */
/* 0x000364000c1e1900 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.S64 R10, RZ, 0x1d, R0 ; /* 0x0000001dff0a7819 */
/* 0x020fe40000001000 */
/*0300*/ LEA R14, P0, R4, c[0x0][0x170], 0x3 ; /* 0x00005c00040e7a11 */
/* 0x002fe400078018ff */
/*0310*/ IADD3 R10, P1, R10, c[0x0][0x180], RZ ; /* 0x000060000a0a7a10 */
/* 0x000fe40007f3e0ff */
/*0320*/ LEA.HI.X R15, R4, c[0x0][0x174], R5, 0x3, P0 ; /* 0x00005d00040f7a11 */
/* 0x000fe400000f1c05 */
/*0330*/ LEA.HI.X.SX32 R11, R0, c[0x0][0x184], 0x3, P1 ; /* 0x00006100000b7a11 */
/* 0x000fc600008f1eff */
/*0340*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x004e4e000000000c */
/*0390*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0023e8000c101b04 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03b0*/ LDG.E R17, [R6.64+0x10] ; /* 0x0000100406117981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea2000c1e1b00 */
/*03d0*/ IADD3 R4, P1, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fca0007f3e0ff */
/*03e0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*03f0*/ IADD3 R19, P0, R17, R12, RZ ; /* 0x0000000c11137210 */
/* 0x004fc80007f1e0ff */
/*0400*/ LEA.HI.X.SX32 R12, R17, R13, 0x1, P0 ; /* 0x0000000d110c7211 */
/* 0x000fe400000f0eff */
/*0410*/ ISETP.GE.U32.AND P0, PT, R4, R19, PT ; /* 0x000000130400720c */
/* 0x000fc80003f06070 */
/*0420*/ ISETP.GE.AND.EX P0, PT, R5, R12, PT, P0 ; /* 0x0000000c0500720c */
/* 0x000fda0003f06300 */
/*0430*/ @!P0 BRA 0x140 ; /* 0xfffffd0000008947 */
/* 0x002fea000383ffff */
/*0440*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0450*/ BRA 0x450; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0080*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe40000011409 */
/*0090*/ ISETP.GT.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x004fc80003f04070 */
/*00a0*/ ISETP.GT.AND.EX P0, PT, R5, R0, PT, P0 ; /* 0x000000000500720c */
/* 0x000fda0003f04300 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x18 ; /* 0x00000018ff067424 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD R5, R0, 0x18, RZ ; /* 0x0000001800057824 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R6, R9, R6, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fc800078e0006 */
/*00f0*/ IMAD.IADD R7, R7, 0x1, R5 ; /* 0x0000000107077824 */
/* 0x000fca00078e0205 */
/*0100*/ LDG.E R4, [R6.64+0x10] ; /* 0x0000100406047981 */
/* 0x000ea4000c1e1900 */
/*0110*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f06270 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ LEA R8, P0, R9.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e0009087a11 */
/* 0x040fe200078018ff */
/*0140*/ LDG.E.64 R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000166000c1e1b00 */
/*0150*/ LEA.HI.X R9, R9, c[0x0][0x17c], R0, 0x3, P0 ; /* 0x00005f0009097a11 */
/* 0x000fcc00000f1c00 */
/*0160*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f66000c1e1b00 */
/*0170*/ LEA R14, P0, R4, c[0x0][0x168], 0x4 ; /* 0x00005a00040e7a11 */
/* 0x020fc800078020ff */
/*0180*/ LEA.HI.X R15, R4, c[0x0][0x16c], R5, 0x4, P0 ; /* 0x00005b00040f7a11 */
/* 0x000fca00000f2405 */
/*0190*/ LDG.E.64 R10, [R14.64+0x8] ; /* 0x000008040e0a7981 */
/* 0x000362000c1e1b00 */
/*01a0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05070 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, -0x1 ; /* 0xffffffffff007424 */
/* 0x000fc600078e00ff */
/*01c0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f05300 */
/*01d0*/ @!P0 BRA 0x330 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x002ea2000c1e1b00 */
/*01f0*/ BSSY B0, 0x330 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x004fc80003f06070 */
/*0210*/ ISETP.GE.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0003f06300 */
/*0220*/ @!P0 BRA 0x320 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000362000c1e1b00 */
/*0240*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fcc000001ff00 */
/*0250*/ LEA R18, P0, R21, c[0x0][0x170], 0x4 ; /* 0x00005c0015127a11 */
/* 0x000fc800078020ff */
/*0260*/ LEA.HI.X R19, R21, c[0x0][0x174], R20, 0x4, P0 ; /* 0x00005d0015137a11 */
/* 0x000fca00000f2414 */
/*0270*/ LDG.E.64 R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x002ea4000c1e1b00 */
/*0280*/ ISETP.NE.U32.AND P0, PT, R14, R16, PT ; /* 0x000000100e00720c */
/* 0x024fc80003f05070 */
/*0290*/ ISETP.NE.AND.EX P0, PT, R15, R17, PT, P0 ; /* 0x000000110f00720c */
/* 0x000fda0003f05300 */
/*02a0*/ @!P0 BRA 0x310 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R21, P0, R21, 0x1, RZ ; /* 0x0000000115157810 */
/* 0x000fca0007f1e0ff */
/*02c0*/ IMAD.X R20, RZ, RZ, R20, P0 ; /* 0x000000ffff147224 */
/* 0x000fe200000e0614 */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R21, R12, PT ; /* 0x0000000c1500720c */
/* 0x000fc80003f06070 */
/*02e0*/ ISETP.GE.AND.EX P0, PT, R20, R13, PT, P0 ; /* 0x0000000d1400720c */
/* 0x000fda0003f06300 */
/*02f0*/ @!P0 BRA 0x250 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0300*/ BRA 0x320 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R0, [R18.64+0x8] ; /* 0x0000080412007981 */
/* 0x000364000c1e1900 */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ SHF.R.S64 R12, RZ, 0x1d, R0 ; /* 0x0000001dff0c7819 */
/* 0x022fc80000001000 */
/*0340*/ IADD3 R12, P0, R12, c[0x0][0x180], RZ ; /* 0x000060000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0350*/ LEA.HI.X.SX32 R13, R0, c[0x0][0x184], 0x3, P0 ; /* 0x00006100000d7a11 */
/* 0x000fca00000f1eff */
/*0360*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0370*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ DFMA R10, R8, R10, R14 ; /* 0x0000000a080a722b */
/* 0x004e4e000000000e */
/*03a0*/ STG.E.64 [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x0023e8000c101b04 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03c0*/ LDG.E R17, [R6.64+0x10] ; /* 0x0000100406117981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IADD3 R4, P1, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fca0007f3e0ff */
/*03f0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0400*/ IADD3 R19, P0, R17, R14, RZ ; /* 0x0000000e11137210 */
/* 0x004fc80007f1e0ff */
/*0410*/ LEA.HI.X.SX32 R14, R17, R15, 0x1, P0 ; /* 0x0000000f110e7211 */
/* 0x000fe400000f0eff */
/*0420*/ ISETP.GE.U32.AND P0, PT, R4, R19, PT ; /* 0x000000130400720c */
/* 0x000fc80003f06070 */
/*0430*/ ISETP.GE.AND.EX P0, PT, R5, R14, PT, P0 ; /* 0x0000000e0500720c */
/* 0x000fda0003f06300 */
/*0440*/ @!P0 BRA 0x170 ; /* 0xfffffd2000008947 */
/* 0x002fea000383ffff */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
#include<cstdlib>
#include<iostream>
#define DFL_LEN 32
#define MAX_THREADS_PER_BLOCK 1024 //supported by hardware, run ./deviceQuery to determine
//cuda error checking
#define check_error(ans) {cudaCheckError((ans),__FILE__,__LINE__);}
inline void cudaCheckError(cudaError_t e,const char *file,int line,bool abort = true){
if(e != cudaSuccess){
fprintf(stderr,"GPUassert: %s\nFile: %s\nLine: %d\n",cudaGetErrorString(e),file,line);
if(abort) exit(e);
}
}
//end of error checking
typedef long int g_type;
//struct declarations and global variables begin here
struct vertex{
g_type number;
g_type start;
int n;
};
struct map{
g_type node;
g_type index;
};
struct entry{
g_type edge;
double val;
};
g_type *edges;
g_type edges_length;
g_type edges_size;
g_type edges_itr;
struct vertex *vertex_list;
g_type vertex_length;
g_type vertex_size;
g_type vertex_itr;
struct entry *transitions;
struct map *node_map;
double *ranks;
double *result;
//end of struct and global definitions
//start of interface
int init_edges(){
if(edges != NULL)
return 0;
edges = (g_type *)malloc(DFL_LEN * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
edges_size = DFL_LEN;
edges_length = 0;
edges_itr = 0;
return 1;
}
void delete_edges(){
edges_length = 0;
edges_size = DFL_LEN;
edges_itr = 0;
if(edges != NULL)
free(edges);
}
int add_edge(int edge){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(edges_length == edges_size){
edges_size *= 2;
edges = (g_type *)realloc(edges,edges_size * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
edges[edges_length] = edge;
edges_length++;
return 1;
}
int get_edge(g_type *e){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(e == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
g_type val = edges[edges_itr];
edges_itr++;
if(edges_itr >= edges_size){
edges_itr = edges_itr % edges_size;
}
*e = val;
return 1;
}
void reset_edge(){
edges_itr = 0;
}
void move_edge(g_type index){
edges_itr = index;
}
int init_vertices(){
if(vertex_list != NULL)
return 0;
vertex_list = (struct vertex *)malloc(DFL_LEN * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
vertex_length = 0;
vertex_size = DFL_LEN;
vertex_itr = 0;
return 1;
}
void delete_vertices(){
vertex_itr = 0;
vertex_length = 0;
vertex_size = 0;
if(vertex_list != NULL)
free(vertex_list);
}
int add_vertex(struct vertex v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(vertex_length == vertex_size){
vertex_size *= 2;
vertex_list = (struct vertex *)realloc(vertex_list,vertex_size * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
vertex_list[vertex_length].number = v.number;
vertex_list[vertex_length].n = v.n;
vertex_list[vertex_length].start = v.start;
g_type temp = vertex_length;
vertex_length++;
return temp;
}
int get_vertex(struct vertex *v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
v->number = vertex_list[vertex_itr].number;
v->start = vertex_list[vertex_itr].start;
v->n = vertex_list[vertex_itr].n;
vertex_itr++;
if(vertex_itr >= vertex_size){
vertex_itr = vertex_itr % vertex_size;
}
return 1;
}
void reset_vertex(){
vertex_itr = 0;
}
void move_vertex(g_type index){
vertex_itr = index;
}
void build_graph(FILE *fp){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(fp == NULL){
fprintf(stderr,"File pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
g_type from,to;
int seen = 0;
g_type cur = -1;
while(fscanf(fp,"%ld %ld",&from,&to) != -1){
if(from == vertex_list[cur].number && vertex_length != 0){
seen = 1;
}
else{
seen = 0;
}
if(!seen){
struct vertex temp;
temp.number = from;
temp.start = edges_length;
temp.n = 0;
cur = add_vertex(temp);
}
add_edge(to);
vertex_list[cur].n++;
}
}
void create_map(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(node_map == NULL){
node_map = (struct map *)malloc(vertex_length * sizeof(struct map));
if(node_map == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
node_map[i].node = vertex_list[i].number;
node_map[i].index = i;
}
}
g_type search_map(g_type node){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(node_map == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
for(int i=0;i<vertex_length;i++){
if(node_map[i].node == node)
return node_map[i].index;
}
return -1;
}
__device__ g_type search_dmap(struct map *d_map,g_type *d_vlength,g_type node){
if(d_map == NULL){
return -1;
}
g_type len = *d_vlength;
for(g_type i=0;i<len;i++){
if(d_map[i].node == node)
return d_map[i].index;
}
return -1;
}
void delete_map(){
if(node_map != NULL)
free(node_map);
}
void init_ranks(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(ranks == NULL){
ranks = (double *)malloc(vertex_length * sizeof(double));
if(ranks == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
ranks[i] = 0.25;
}
}
void delete_ranks(){
if(ranks != NULL)
free(ranks);
}
void init_transitions(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(transitions == NULL){
transitions = (struct entry *)malloc(edges_length * sizeof(struct entry));
if(transitions == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(g_type i=0;i<vertex_length;i++){
g_type start = vertex_list[i].start;
g_type j = start;
int n = vertex_list[i].n;
while(j < start + n){
transitions[j].edge = edges[j];
transitions[j].val = 1.0 / vertex_list[i].n;
j++;
}
}
}
void delete_transitions(){
if(transitions != NULL)
free(transitions);
}
void init_result(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(result == NULL){
result = (double *)malloc(vertex_length * sizeof(double));
if(result == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
result[i] = 0.0;
}
}
void delete_result(){
if(result != NULL)
free(result);
}
int pagerank(){
for(int i=0;i<vertex_length;i++){
for(int j = vertex_list[i].start; j < vertex_list[i].start + vertex_list[i].n; j++){
double temp = transitions[j].val * ranks[i];
g_type index = search_map(transitions[j].edge);
result[index] += temp;
}
}
return 1;
}
void update_ranks(){
for(int i=0;i<vertex_length;i++){
ranks[i] = result[i];
result[i] = 0.0;
}
}
//end of interface
//CUDA kernels
__global__ void multiply_kernel(struct vertex *d_vertices,struct entry *d_transitions,struct map *d_map,double *d_ranks,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
double b = d_ranks[threadId];
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
double a = d_transitions[i].val;
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double res = a * b;
double temp = d_tempranks[index];
__syncthreads();
temp += res;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
//deprecated
__global__ void add_kernel(struct vertex *d_vertices,struct entry *d_transitions,double *d_res,struct map *d_map,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double val = d_res[i];
double temp = d_tempranks[index];
__syncthreads();
temp += val;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
__global__ void update_kernel(double *d_tempranks,double *d_ranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
d_ranks[threadId] = d_tempranks[threadId];
}
}
//end of CUDA kernels
//main program begins here
int main(int argc,char **argv){
if(argc != 4){
fprintf(stderr,"Correct usage: %s <pathToGraph> <numIterations> <serial = 0/parallel = 1>\n",argv[0]);
exit(1);
}
FILE *fp = fopen(argv[1],"r");
const int iterations = atoi(argv[2]);
const int mode = atoi(argv[3]);
init_vertices();
init_edges();
build_graph(fp);
create_map();
init_ranks();
init_transitions();
if(mode == 1){
//initializing device memory
g_type *d_elength;
check_error(cudaMalloc((void **)&d_elength,sizeof(g_type)));
check_error(cudaMemcpy(d_elength,&edges_length,sizeof(g_type),cudaMemcpyHostToDevice));
g_type *d_vlength;
check_error(cudaMalloc((void **)&d_vlength,sizeof(g_type)));
check_error(cudaMemcpy(d_vlength,&vertex_length,sizeof(g_type),cudaMemcpyHostToDevice));
struct vertex *d_vertices;
check_error(cudaMalloc((void **)&d_vertices,vertex_length * sizeof(struct vertex)));
check_error(cudaMemcpy(d_vertices,vertex_list,vertex_length * sizeof(struct vertex),cudaMemcpyHostToDevice));
struct entry *d_transitions;
check_error(cudaMalloc((void **)&d_transitions,edges_length * sizeof(struct entry)));
check_error(cudaMemcpy(d_transitions,transitions,edges_length * sizeof(struct entry),cudaMemcpyHostToDevice));
struct map *d_map;
check_error(cudaMalloc((void **)&d_map,vertex_length * sizeof(struct map)));
check_error(cudaMemcpy(d_map,node_map,vertex_length * sizeof(struct map),cudaMemcpyHostToDevice));
double *d_ranks;
check_error(cudaMalloc((void **)&d_ranks,vertex_length * sizeof(double)));
check_error(cudaMemcpy(d_ranks,ranks,vertex_length * sizeof(double),cudaMemcpyHostToDevice));
double *d_res;
check_error(cudaMalloc((void **)&d_res,edges_length * sizeof(double)));
double *d_tempranks;
check_error(cudaMalloc((void **)&d_tempranks,vertex_length * sizeof(double)));
//pagerank iterations begin here: Power method
int blocks = 1;
int threads = vertex_length;
if(vertex_length > MAX_THREADS_PER_BLOCK){
blocks = (int)ceil(vertex_length / (double)MAX_THREADS_PER_BLOCK);
threads = MAX_THREADS_PER_BLOCK;
}
int counter = 0;
clock_t begin = clock();
while(counter < iterations){
check_error(cudaMemset(d_res,0.0,edges_length * sizeof(double)));
check_error(cudaMemset(d_tempranks,0.0,vertex_length * sizeof(double)));
multiply_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_map,d_ranks,d_tempranks,d_vlength);
cudaDeviceSynchronize();
//add_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_res,d_map,d_tempranks,d_vlength);
//cudaDeviceSynchronize();
update_kernel<<<blocks,threads>>>(d_tempranks,d_ranks,d_vlength);
cudaDeviceSynchronize();
counter++;
}
clock_t end = clock();
//end of pagerank iterations
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
double *res;
res = (double *)malloc(vertex_length * sizeof(double));
check_error(cudaMemcpy(res,d_ranks,vertex_length * sizeof(double),cudaMemcpyDeviceToHost));
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",res[i]);
}
free(res);
printf("%lf s\n",time_spent);
check_error(cudaFree(d_elength));
check_error(cudaFree(d_vlength));
check_error(cudaFree(d_vertices));
check_error(cudaFree(d_transitions));
check_error(cudaFree(d_map));
check_error(cudaFree(d_ranks));
check_error(cudaFree(d_res));
check_error(cudaFree(d_tempranks));
}
else{
clock_t begin = clock();
init_result();
int counter = 0;
while(counter < iterations){
if(!pagerank()){
fprintf(stderr,"Pagerank failed in iteration: %d\n",counter);
break;
}
update_ranks();
counter++;
}
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",ranks[i]);
}
printf("%lf s\n",time_spent);
}
//end of device memory initialization
delete_edges();
delete_vertices();
delete_ranks();
delete_transitions();
delete_map();
delete_result();
return 0;
} | #include <hip/hip_runtime.h>
#include<cstdio>
#include<cstdlib>
#include<iostream>
#define DFL_LEN 32
#define MAX_THREADS_PER_BLOCK 1024 //supported by hardware, run ./deviceQuery to determine
//cuda error checking
#define check_error(ans) {cudaCheckError((ans),__FILE__,__LINE__);}
inline void cudaCheckError(hipError_t e,const char *file,int line,bool abort = true){
if(e != hipSuccess){
fprintf(stderr,"GPUassert: %s\nFile: %s\nLine: %d\n",hipGetErrorString(e),file,line);
if(abort) exit(e);
}
}
//end of error checking
typedef long int g_type;
//struct declarations and global variables begin here
struct vertex{
g_type number;
g_type start;
int n;
};
struct map{
g_type node;
g_type index;
};
struct entry{
g_type edge;
double val;
};
g_type *edges;
g_type edges_length;
g_type edges_size;
g_type edges_itr;
struct vertex *vertex_list;
g_type vertex_length;
g_type vertex_size;
g_type vertex_itr;
struct entry *transitions;
struct map *node_map;
double *ranks;
double *result;
//end of struct and global definitions
//start of interface
int init_edges(){
if(edges != NULL)
return 0;
edges = (g_type *)malloc(DFL_LEN * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
edges_size = DFL_LEN;
edges_length = 0;
edges_itr = 0;
return 1;
}
void delete_edges(){
edges_length = 0;
edges_size = DFL_LEN;
edges_itr = 0;
if(edges != NULL)
free(edges);
}
int add_edge(int edge){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(edges_length == edges_size){
edges_size *= 2;
edges = (g_type *)realloc(edges,edges_size * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
edges[edges_length] = edge;
edges_length++;
return 1;
}
int get_edge(g_type *e){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(e == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
g_type val = edges[edges_itr];
edges_itr++;
if(edges_itr >= edges_size){
edges_itr = edges_itr % edges_size;
}
*e = val;
return 1;
}
void reset_edge(){
edges_itr = 0;
}
void move_edge(g_type index){
edges_itr = index;
}
int init_vertices(){
if(vertex_list != NULL)
return 0;
vertex_list = (struct vertex *)malloc(DFL_LEN * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
vertex_length = 0;
vertex_size = DFL_LEN;
vertex_itr = 0;
return 1;
}
void delete_vertices(){
vertex_itr = 0;
vertex_length = 0;
vertex_size = 0;
if(vertex_list != NULL)
free(vertex_list);
}
int add_vertex(struct vertex v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(vertex_length == vertex_size){
vertex_size *= 2;
vertex_list = (struct vertex *)realloc(vertex_list,vertex_size * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
vertex_list[vertex_length].number = v.number;
vertex_list[vertex_length].n = v.n;
vertex_list[vertex_length].start = v.start;
g_type temp = vertex_length;
vertex_length++;
return temp;
}
int get_vertex(struct vertex *v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
v->number = vertex_list[vertex_itr].number;
v->start = vertex_list[vertex_itr].start;
v->n = vertex_list[vertex_itr].n;
vertex_itr++;
if(vertex_itr >= vertex_size){
vertex_itr = vertex_itr % vertex_size;
}
return 1;
}
void reset_vertex(){
vertex_itr = 0;
}
void move_vertex(g_type index){
vertex_itr = index;
}
void build_graph(FILE *fp){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(fp == NULL){
fprintf(stderr,"File pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
g_type from,to;
int seen = 0;
g_type cur = -1;
while(fscanf(fp,"%ld %ld",&from,&to) != -1){
if(from == vertex_list[cur].number && vertex_length != 0){
seen = 1;
}
else{
seen = 0;
}
if(!seen){
struct vertex temp;
temp.number = from;
temp.start = edges_length;
temp.n = 0;
cur = add_vertex(temp);
}
add_edge(to);
vertex_list[cur].n++;
}
}
void create_map(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(node_map == NULL){
node_map = (struct map *)malloc(vertex_length * sizeof(struct map));
if(node_map == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
node_map[i].node = vertex_list[i].number;
node_map[i].index = i;
}
}
g_type search_map(g_type node){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(node_map == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
for(int i=0;i<vertex_length;i++){
if(node_map[i].node == node)
return node_map[i].index;
}
return -1;
}
__device__ g_type search_dmap(struct map *d_map,g_type *d_vlength,g_type node){
if(d_map == NULL){
return -1;
}
g_type len = *d_vlength;
for(g_type i=0;i<len;i++){
if(d_map[i].node == node)
return d_map[i].index;
}
return -1;
}
void delete_map(){
if(node_map != NULL)
free(node_map);
}
void init_ranks(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(ranks == NULL){
ranks = (double *)malloc(vertex_length * sizeof(double));
if(ranks == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
ranks[i] = 0.25;
}
}
void delete_ranks(){
if(ranks != NULL)
free(ranks);
}
void init_transitions(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(transitions == NULL){
transitions = (struct entry *)malloc(edges_length * sizeof(struct entry));
if(transitions == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(g_type i=0;i<vertex_length;i++){
g_type start = vertex_list[i].start;
g_type j = start;
int n = vertex_list[i].n;
while(j < start + n){
transitions[j].edge = edges[j];
transitions[j].val = 1.0 / vertex_list[i].n;
j++;
}
}
}
void delete_transitions(){
if(transitions != NULL)
free(transitions);
}
void init_result(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(result == NULL){
result = (double *)malloc(vertex_length * sizeof(double));
if(result == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
result[i] = 0.0;
}
}
void delete_result(){
if(result != NULL)
free(result);
}
int pagerank(){
for(int i=0;i<vertex_length;i++){
for(int j = vertex_list[i].start; j < vertex_list[i].start + vertex_list[i].n; j++){
double temp = transitions[j].val * ranks[i];
g_type index = search_map(transitions[j].edge);
result[index] += temp;
}
}
return 1;
}
void update_ranks(){
for(int i=0;i<vertex_length;i++){
ranks[i] = result[i];
result[i] = 0.0;
}
}
//end of interface
//CUDA kernels
__global__ void multiply_kernel(struct vertex *d_vertices,struct entry *d_transitions,struct map *d_map,double *d_ranks,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
double b = d_ranks[threadId];
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
double a = d_transitions[i].val;
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double res = a * b;
double temp = d_tempranks[index];
__syncthreads();
temp += res;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
//deprecated
__global__ void add_kernel(struct vertex *d_vertices,struct entry *d_transitions,double *d_res,struct map *d_map,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double val = d_res[i];
double temp = d_tempranks[index];
__syncthreads();
temp += val;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
__global__ void update_kernel(double *d_tempranks,double *d_ranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
d_ranks[threadId] = d_tempranks[threadId];
}
}
//end of CUDA kernels
//main program begins here
int main(int argc,char **argv){
if(argc != 4){
fprintf(stderr,"Correct usage: %s <pathToGraph> <numIterations> <serial = 0/parallel = 1>\n",argv[0]);
exit(1);
}
FILE *fp = fopen(argv[1],"r");
const int iterations = atoi(argv[2]);
const int mode = atoi(argv[3]);
init_vertices();
init_edges();
build_graph(fp);
create_map();
init_ranks();
init_transitions();
if(mode == 1){
//initializing device memory
g_type *d_elength;
check_error(hipMalloc((void **)&d_elength,sizeof(g_type)));
check_error(hipMemcpy(d_elength,&edges_length,sizeof(g_type),hipMemcpyHostToDevice));
g_type *d_vlength;
check_error(hipMalloc((void **)&d_vlength,sizeof(g_type)));
check_error(hipMemcpy(d_vlength,&vertex_length,sizeof(g_type),hipMemcpyHostToDevice));
struct vertex *d_vertices;
check_error(hipMalloc((void **)&d_vertices,vertex_length * sizeof(struct vertex)));
check_error(hipMemcpy(d_vertices,vertex_list,vertex_length * sizeof(struct vertex),hipMemcpyHostToDevice));
struct entry *d_transitions;
check_error(hipMalloc((void **)&d_transitions,edges_length * sizeof(struct entry)));
check_error(hipMemcpy(d_transitions,transitions,edges_length * sizeof(struct entry),hipMemcpyHostToDevice));
struct map *d_map;
check_error(hipMalloc((void **)&d_map,vertex_length * sizeof(struct map)));
check_error(hipMemcpy(d_map,node_map,vertex_length * sizeof(struct map),hipMemcpyHostToDevice));
double *d_ranks;
check_error(hipMalloc((void **)&d_ranks,vertex_length * sizeof(double)));
check_error(hipMemcpy(d_ranks,ranks,vertex_length * sizeof(double),hipMemcpyHostToDevice));
double *d_res;
check_error(hipMalloc((void **)&d_res,edges_length * sizeof(double)));
double *d_tempranks;
check_error(hipMalloc((void **)&d_tempranks,vertex_length * sizeof(double)));
//pagerank iterations begin here: Power method
int blocks = 1;
int threads = vertex_length;
if(vertex_length > MAX_THREADS_PER_BLOCK){
blocks = (int)ceil(vertex_length / (double)MAX_THREADS_PER_BLOCK);
threads = MAX_THREADS_PER_BLOCK;
}
int counter = 0;
clock_t begin = clock();
while(counter < iterations){
check_error(hipMemset(d_res,0.0,edges_length * sizeof(double)));
check_error(hipMemset(d_tempranks,0.0,vertex_length * sizeof(double)));
multiply_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_map,d_ranks,d_tempranks,d_vlength);
hipDeviceSynchronize();
//add_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_res,d_map,d_tempranks,d_vlength);
//cudaDeviceSynchronize();
update_kernel<<<blocks,threads>>>(d_tempranks,d_ranks,d_vlength);
hipDeviceSynchronize();
counter++;
}
clock_t end = clock();
//end of pagerank iterations
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
double *res;
res = (double *)malloc(vertex_length * sizeof(double));
check_error(hipMemcpy(res,d_ranks,vertex_length * sizeof(double),hipMemcpyDeviceToHost));
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",res[i]);
}
free(res);
printf("%lf s\n",time_spent);
check_error(hipFree(d_elength));
check_error(hipFree(d_vlength));
check_error(hipFree(d_vertices));
check_error(hipFree(d_transitions));
check_error(hipFree(d_map));
check_error(hipFree(d_ranks));
check_error(hipFree(d_res));
check_error(hipFree(d_tempranks));
}
else{
clock_t begin = clock();
init_result();
int counter = 0;
while(counter < iterations){
if(!pagerank()){
fprintf(stderr,"Pagerank failed in iteration: %d\n",counter);
break;
}
update_ranks();
counter++;
}
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",ranks[i]);
}
printf("%lf s\n",time_spent);
}
//end of device memory initialization
delete_edges();
delete_vertices();
delete_ranks();
delete_transitions();
delete_map();
delete_result();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<cstdio>
#include<cstdlib>
#include<iostream>
#define DFL_LEN 32
#define MAX_THREADS_PER_BLOCK 1024 //supported by hardware, run ./deviceQuery to determine
//cuda error checking
#define check_error(ans) {cudaCheckError((ans),__FILE__,__LINE__);}
inline void cudaCheckError(hipError_t e,const char *file,int line,bool abort = true){
if(e != hipSuccess){
fprintf(stderr,"GPUassert: %s\nFile: %s\nLine: %d\n",hipGetErrorString(e),file,line);
if(abort) exit(e);
}
}
//end of error checking
typedef long int g_type;
//struct declarations and global variables begin here
struct vertex{
g_type number;
g_type start;
int n;
};
struct map{
g_type node;
g_type index;
};
struct entry{
g_type edge;
double val;
};
g_type *edges;
g_type edges_length;
g_type edges_size;
g_type edges_itr;
struct vertex *vertex_list;
g_type vertex_length;
g_type vertex_size;
g_type vertex_itr;
struct entry *transitions;
struct map *node_map;
double *ranks;
double *result;
//end of struct and global definitions
//start of interface
int init_edges(){
if(edges != NULL)
return 0;
edges = (g_type *)malloc(DFL_LEN * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
edges_size = DFL_LEN;
edges_length = 0;
edges_itr = 0;
return 1;
}
void delete_edges(){
edges_length = 0;
edges_size = DFL_LEN;
edges_itr = 0;
if(edges != NULL)
free(edges);
}
int add_edge(int edge){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(edges_length == edges_size){
edges_size *= 2;
edges = (g_type *)realloc(edges,edges_size * sizeof(g_type));
if(edges == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
edges[edges_length] = edge;
edges_length++;
return 1;
}
int get_edge(g_type *e){
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(e == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
g_type val = edges[edges_itr];
edges_itr++;
if(edges_itr >= edges_size){
edges_itr = edges_itr % edges_size;
}
*e = val;
return 1;
}
void reset_edge(){
edges_itr = 0;
}
void move_edge(g_type index){
edges_itr = index;
}
int init_vertices(){
if(vertex_list != NULL)
return 0;
vertex_list = (struct vertex *)malloc(DFL_LEN * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
vertex_length = 0;
vertex_size = DFL_LEN;
vertex_itr = 0;
return 1;
}
void delete_vertices(){
vertex_itr = 0;
vertex_length = 0;
vertex_size = 0;
if(vertex_list != NULL)
free(vertex_list);
}
int add_vertex(struct vertex v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
if(vertex_length == vertex_size){
vertex_size *= 2;
vertex_list = (struct vertex *)realloc(vertex_list,vertex_size * sizeof(struct vertex));
if(vertex_list == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
}
vertex_list[vertex_length].number = v.number;
vertex_list[vertex_length].n = v.n;
vertex_list[vertex_length].start = v.start;
g_type temp = vertex_length;
vertex_length++;
return temp;
}
int get_vertex(struct vertex *v){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return 0;
}
v->number = vertex_list[vertex_itr].number;
v->start = vertex_list[vertex_itr].start;
v->n = vertex_list[vertex_itr].n;
vertex_itr++;
if(vertex_itr >= vertex_size){
vertex_itr = vertex_itr % vertex_size;
}
return 1;
}
void reset_vertex(){
vertex_itr = 0;
}
void move_vertex(g_type index){
vertex_itr = index;
}
void build_graph(FILE *fp){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(fp == NULL){
fprintf(stderr,"File pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
g_type from,to;
int seen = 0;
g_type cur = -1;
while(fscanf(fp,"%ld %ld",&from,&to) != -1){
if(from == vertex_list[cur].number && vertex_length != 0){
seen = 1;
}
else{
seen = 0;
}
if(!seen){
struct vertex temp;
temp.number = from;
temp.start = edges_length;
temp.n = 0;
cur = add_vertex(temp);
}
add_edge(to);
vertex_list[cur].n++;
}
}
void create_map(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(node_map == NULL){
node_map = (struct map *)malloc(vertex_length * sizeof(struct map));
if(node_map == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
node_map[i].node = vertex_list[i].number;
node_map[i].index = i;
}
}
g_type search_map(g_type node){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
if(node_map == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return -1;
}
for(int i=0;i<vertex_length;i++){
if(node_map[i].node == node)
return node_map[i].index;
}
return -1;
}
__device__ g_type search_dmap(struct map *d_map,g_type *d_vlength,g_type node){
if(d_map == NULL){
return -1;
}
g_type len = *d_vlength;
for(g_type i=0;i<len;i++){
if(d_map[i].node == node)
return d_map[i].index;
}
return -1;
}
void delete_map(){
if(node_map != NULL)
free(node_map);
}
void init_ranks(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(ranks == NULL){
ranks = (double *)malloc(vertex_length * sizeof(double));
if(ranks == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
ranks[i] = 0.25;
}
}
void delete_ranks(){
if(ranks != NULL)
free(ranks);
}
void init_transitions(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(transitions == NULL){
transitions = (struct entry *)malloc(edges_length * sizeof(struct entry));
if(transitions == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(g_type i=0;i<vertex_length;i++){
g_type start = vertex_list[i].start;
g_type j = start;
int n = vertex_list[i].n;
while(j < start + n){
transitions[j].edge = edges[j];
transitions[j].val = 1.0 / vertex_list[i].n;
j++;
}
}
}
void delete_transitions(){
if(transitions != NULL)
free(transitions);
}
void init_result(){
if(vertex_list == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(edges == NULL){
fprintf(stderr,"Null pointer error in %s at line %d\n",__FILE__,__LINE__);
return ;
}
if(result == NULL){
result = (double *)malloc(vertex_length * sizeof(double));
if(result == NULL){
fprintf(stderr,"Malloc failed in %s at line %d\n",__FILE__,__LINE__);
return ;
}
}
for(int i=0;i<vertex_length;i++){
result[i] = 0.0;
}
}
void delete_result(){
if(result != NULL)
free(result);
}
int pagerank(){
for(int i=0;i<vertex_length;i++){
for(int j = vertex_list[i].start; j < vertex_list[i].start + vertex_list[i].n; j++){
double temp = transitions[j].val * ranks[i];
g_type index = search_map(transitions[j].edge);
result[index] += temp;
}
}
return 1;
}
void update_ranks(){
for(int i=0;i<vertex_length;i++){
ranks[i] = result[i];
result[i] = 0.0;
}
}
//end of interface
//CUDA kernels
__global__ void multiply_kernel(struct vertex *d_vertices,struct entry *d_transitions,struct map *d_map,double *d_ranks,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
double b = d_ranks[threadId];
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
double a = d_transitions[i].val;
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double res = a * b;
double temp = d_tempranks[index];
__syncthreads();
temp += res;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
//deprecated
__global__ void add_kernel(struct vertex *d_vertices,struct entry *d_transitions,double *d_res,struct map *d_map,double *d_tempranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
for(g_type i = d_vertices[threadId].start;i < d_vertices[threadId].start + d_vertices[threadId].n;i++){
int index = search_dmap(d_map,d_vlength,d_transitions[i].edge);
double val = d_res[i];
double temp = d_tempranks[index];
__syncthreads();
temp += val;
d_tempranks[index] = temp;
__syncthreads();
}
}
}
__global__ void update_kernel(double *d_tempranks,double *d_ranks,g_type *d_vlength){
int threadId = blockDim.x * blockIdx.x + threadIdx.x;
g_type len = *d_vlength;
if(threadId < len){
d_ranks[threadId] = d_tempranks[threadId];
}
}
//end of CUDA kernels
//main program begins here
int main(int argc,char **argv){
if(argc != 4){
fprintf(stderr,"Correct usage: %s <pathToGraph> <numIterations> <serial = 0/parallel = 1>\n",argv[0]);
exit(1);
}
FILE *fp = fopen(argv[1],"r");
const int iterations = atoi(argv[2]);
const int mode = atoi(argv[3]);
init_vertices();
init_edges();
build_graph(fp);
create_map();
init_ranks();
init_transitions();
if(mode == 1){
//initializing device memory
g_type *d_elength;
check_error(hipMalloc((void **)&d_elength,sizeof(g_type)));
check_error(hipMemcpy(d_elength,&edges_length,sizeof(g_type),hipMemcpyHostToDevice));
g_type *d_vlength;
check_error(hipMalloc((void **)&d_vlength,sizeof(g_type)));
check_error(hipMemcpy(d_vlength,&vertex_length,sizeof(g_type),hipMemcpyHostToDevice));
struct vertex *d_vertices;
check_error(hipMalloc((void **)&d_vertices,vertex_length * sizeof(struct vertex)));
check_error(hipMemcpy(d_vertices,vertex_list,vertex_length * sizeof(struct vertex),hipMemcpyHostToDevice));
struct entry *d_transitions;
check_error(hipMalloc((void **)&d_transitions,edges_length * sizeof(struct entry)));
check_error(hipMemcpy(d_transitions,transitions,edges_length * sizeof(struct entry),hipMemcpyHostToDevice));
struct map *d_map;
check_error(hipMalloc((void **)&d_map,vertex_length * sizeof(struct map)));
check_error(hipMemcpy(d_map,node_map,vertex_length * sizeof(struct map),hipMemcpyHostToDevice));
double *d_ranks;
check_error(hipMalloc((void **)&d_ranks,vertex_length * sizeof(double)));
check_error(hipMemcpy(d_ranks,ranks,vertex_length * sizeof(double),hipMemcpyHostToDevice));
double *d_res;
check_error(hipMalloc((void **)&d_res,edges_length * sizeof(double)));
double *d_tempranks;
check_error(hipMalloc((void **)&d_tempranks,vertex_length * sizeof(double)));
//pagerank iterations begin here: Power method
int blocks = 1;
int threads = vertex_length;
if(vertex_length > MAX_THREADS_PER_BLOCK){
blocks = (int)ceil(vertex_length / (double)MAX_THREADS_PER_BLOCK);
threads = MAX_THREADS_PER_BLOCK;
}
int counter = 0;
clock_t begin = clock();
while(counter < iterations){
check_error(hipMemset(d_res,0.0,edges_length * sizeof(double)));
check_error(hipMemset(d_tempranks,0.0,vertex_length * sizeof(double)));
multiply_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_map,d_ranks,d_tempranks,d_vlength);
hipDeviceSynchronize();
//add_kernel<<<blocks,threads>>>(d_vertices,d_transitions,d_res,d_map,d_tempranks,d_vlength);
//cudaDeviceSynchronize();
update_kernel<<<blocks,threads>>>(d_tempranks,d_ranks,d_vlength);
hipDeviceSynchronize();
counter++;
}
clock_t end = clock();
//end of pagerank iterations
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
double *res;
res = (double *)malloc(vertex_length * sizeof(double));
check_error(hipMemcpy(res,d_ranks,vertex_length * sizeof(double),hipMemcpyDeviceToHost));
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",res[i]);
}
free(res);
printf("%lf s\n",time_spent);
check_error(hipFree(d_elength));
check_error(hipFree(d_vlength));
check_error(hipFree(d_vertices));
check_error(hipFree(d_transitions));
check_error(hipFree(d_map));
check_error(hipFree(d_ranks));
check_error(hipFree(d_res));
check_error(hipFree(d_tempranks));
}
else{
clock_t begin = clock();
init_result();
int counter = 0;
while(counter < iterations){
if(!pagerank()){
fprintf(stderr,"Pagerank failed in iteration: %d\n",counter);
break;
}
update_ranks();
counter++;
}
clock_t end = clock();
double time_spent = (double)(end - begin) / CLOCKS_PER_SEC;
for(int i = 0;i<vertex_length;i++){
printf("%lf\n",ranks[i]);
}
printf("%lf s\n",time_spent);
}
//end of device memory initialization
delete_edges();
delete_vertices();
delete_ranks();
delete_transitions();
delete_map();
delete_result();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl
.globl _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl
.p2align 8
.type _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl,@function
_Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[8:9], 0x0
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b64 s[10:11], s[0:1], 0x0
s_mov_b32 s16, 0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 24, s[10:11]
global_load_b32 v0, v[4:5], off offset:16
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_mad_i64_i32 v[6:7], null, v1, 24, s[10:11]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 16
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
global_load_b64 v[0:1], v[0:1], off
global_load_b64 v[2:3], v[6:7], off offset:8
v_add_co_u32 v6, vcc_lo, v6, 8
s_cmp_lg_u64 s[2:3], 0
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_cselect_b32 s17, -1, 0
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_branch .LBB0_5
.LBB0_3:
v_mov_b32_e32 v12, -1
v_mov_b32_e32 v13, -1
.LBB0_4:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[10:11], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_load_b64 v[12:13], v[10:11], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_fma_f64 v[8:9], v[0:1], v[8:9], v[12:13]
global_store_b64 v[10:11], v[8:9], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v10, v[4:5], off
global_load_b64 v[8:9], v[6:7], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v11, vcc_lo
v_cmp_ge_i64_e32 vcc_lo, v[2:3], v[8:9]
s_or_b32 s16, vcc_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_14
.LBB0_5:
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[10:11], 4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v11, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s17
global_load_b64 v[8:9], v[8:9], off offset:8
s_cbranch_vccnz .LBB0_3
s_load_b64 s[4:5], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s10, s[4:5], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_3
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
s_mov_b32 s18, 0
s_mov_b64 s[10:11], s[2:3]
global_load_b64 v[10:11], v[10:11], off
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s22, exec_lo, s21
v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15
s_or_b32 s18, s22, s18
v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
s_and_not1_b32 s10, s19, exec_lo
s_and_b32 s11, s20, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s19, s10, s11
s_mov_b64 s[10:11], s[12:13]
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_11
.LBB0_9:
s_add_u32 s12, s10, -8
s_addc_u32 s13, s11, -1
s_or_b32 s20, s20, exec_lo
s_load_b64 s[12:13], s[12:13], 0x0
s_or_b32 s21, s21, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, s[12:13], v[10:11]
s_and_saveexec_b32 s22, vcc_lo
s_cbranch_execz .LBB0_8
s_add_u32 s12, s10, 16
s_addc_u32 s13, s11, 0
s_add_u32 s4, s4, -1
s_addc_u32 s5, s5, -1
s_mov_b64 s[14:15], -1
s_cmp_eq_u64 s[4:5], 0
s_cselect_b32 s23, -1, 0
s_and_not1_b32 s21, s21, exec_lo
s_and_b32 s23, s23, exec_lo
s_and_not1_b32 s20, s20, exec_lo
s_or_b32 s21, s21, s23
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s4, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_13
global_load_b64 v[12:13], v[13:14], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
s_branch .LBB0_4
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl, .Lfunc_end0-_Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl
.globl _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl
.p2align 8
.type _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl,@function
_Z10add_kernelP6vertexP5entryPdP3mapS3_Pl:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[8:9], 0x0
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_14
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 24, s[2:3]
global_load_b32 v0, v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_14
v_mad_i64_i32 v[4:5], null, v1, 24, s[2:3]
s_load_b256 s[0:7], s[0:1], 0x8
v_add_co_u32 v2, vcc_lo, v2, 16
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_load_b64 v[0:1], v[4:5], off offset:8
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt lgkmcnt(0)
s_cmp_lg_u64 s[4:5], 0
s_cselect_b32 s19, -1, 0
s_add_u32 s4, s4, 8
s_addc_u32 s5, s5, 0
s_branch .LBB1_5
.LBB1_3:
v_mov_b32_e32 v8, -1
v_mov_b32_e32 v9, -1
.LBB1_4:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, 1
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[10:11], v[8:9], off
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_f64 v[6:7], v[6:7], v[10:11]
global_store_b64 v[8:9], v[6:7], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x1
global_load_b32 v8, v[2:3], off
global_load_b64 v[6:7], v[4:5], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt vmcnt(0)
v_add_co_u32 v6, vcc_lo, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
v_cmp_ge_i64_e32 vcc_lo, v[0:1], v[6:7]
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB1_14
.LBB1_5:
s_and_not1_b32 vcc_lo, exec_lo, s19
s_cbranch_vccnz .LBB1_3
s_load_b64 s[10:11], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s12, s[10:11], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB1_3
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[6:7], 4, v[0:1]
s_mov_b32 s20, 0
s_mov_b64 s[12:13], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_9
.p2align 6
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, exec_lo, s23
v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17
s_or_b32 s20, s24, s20
v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
s_and_not1_b32 s12, s21, exec_lo
s_and_b32 s13, s22, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s21, s12, s13
s_mov_b64 s[12:13], s[14:15]
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB1_11
.LBB1_9:
s_add_u32 s14, s12, -8
s_addc_u32 s15, s13, -1
s_or_b32 s22, s22, exec_lo
s_load_b64 s[14:15], s[14:15], 0x0
s_or_b32 s23, s23, exec_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, s[14:15], v[6:7]
s_and_saveexec_b32 s24, vcc_lo
s_cbranch_execz .LBB1_8
s_add_u32 s14, s12, 16
s_addc_u32 s15, s13, 0
s_add_u32 s10, s10, -1
s_addc_u32 s11, s11, -1
s_mov_b64 s[16:17], -1
s_cmp_eq_u64 s[10:11], 0
s_cselect_b32 s25, -1, 0
s_and_not1_b32 s23, s23, exec_lo
s_and_b32 s25, s25, exec_lo
s_and_not1_b32 s22, s22, exec_lo
s_or_b32 s23, s23, s25
s_branch .LBB1_8
.LBB1_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s20
s_and_saveexec_b32 s10, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_13
global_load_b64 v[8:9], v[9:10], off
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s10
s_branch .LBB1_4
.LBB1_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl, .Lfunc_end1-_Z10add_kernelP6vertexP5entryPdP3mapS3_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13update_kernelPdS_Pl
.globl _Z13update_kernelPdS_Pl
.p2align 8
.type _Z13update_kernelPdS_Pl,@function
_Z13update_kernelPdS_Pl:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13update_kernelPdS_Pl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13update_kernelPdS_Pl, .Lfunc_end2-_Z13update_kernelPdS_Pl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z15multiply_kernelP6vertexP5entryP3mapPdS5_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z10add_kernelP6vertexP5entryPdP3mapS3_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13update_kernelPdS_Pl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13update_kernelPdS_Pl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Dummy file to trigger CUDA compile in this project | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Dummy file to trigger CUDA compile in this project | .file "tmpxft_000c5c8e_00000000-6_File.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Dummy file to trigger CUDA compile in this project | #include <hip/hip_runtime.h>
// Dummy file to trigger CUDA compile in this project |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Dummy file to trigger CUDA compile in this project | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Dummy file to trigger CUDA compile in this project | .text
.file "File.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c5c8e_00000000-6_File.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "File.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // fermi
/*
* Copyright 2018 Vrije Universiteit Amsterdam, The Netherlands
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define EPS (1.0f)
extern "C" {
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input);
}
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input) {
const int i = blockIdx.y;
const int bj = blockIdx.x;
const int wtj = threadIdx.y;
const int ttj = threadIdx.x;
const int nrThreadsW = min(1024, w);
const int nrThreadsNrThreadsW = min(32, nrThreadsW);
const int tj = wtj * (1 * nrThreadsNrThreadsW) + ttj;
if (tj < nrThreadsW) {
const int j = bj * (1 * nrThreadsW) + tj;
if (j < w) {
float dx;
if (j == 0) dx = input[j + 1 + i * (1 * w)] - input[j + i * (1 * w)];
else if (j == w - 1) dx = input[j + i * (1 * w)] - input[j - 1 + i * (1 * w)];
else dx = 0.5 * (input[j + 1 + i * (1 * w)] - input[j - 1 + i * (1 * w)]);
float dy;
if (i == 0) dy = input[j + (i + 1) * (1 * w)] - input[j + i * (1 * w)];
else if (i == h - 1) dy = input[j + i * (1 * w)] - input[j + (i - 1) * (1 * w)];
else dy = 0.5 * (input[j + (i + 1) * (1 * w)] - input[j + (i - 1) * (1 * w)]);
const float norm = sqrtf(dx * dx + dy * dy);
const float scale = 1.0 / (EPS + norm);
dxsdys[j + 0 * (1 * h * w) + i * (1 * w)] = dx * scale;
dxsdys[j + 1 * (1 * h * w) + i * (1 * w)] = dy * scale;
}
}
} | code for sm_80
Function : fastnoise1Kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC UR8, c[0x0][0x164] ; /* 0x0000590000087ab9 */
/* 0x000fe40000000800 */
/*0030*/ UISETP.LT.AND UP0, UPT, UR8, 0x400, UPT ; /* 0x000004000800788c */
/* 0x000fe2000bf01270 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ USEL UR4, UR8, 0x400, UP0 ; /* 0x0000040008047887 */
/* 0x000fc80008000000 */
/*0060*/ UISETP.GE.AND UP0, UPT, UR4, 0x20, UPT ; /* 0x000000200400788c */
/* 0x000fc8000bf06270 */
/*0070*/ USEL UR5, UR8, 0x20, !UP0 ; /* 0x0000002008057887 */
/* 0x000fcc000c000000 */
/*0080*/ IMAD R0, R0, UR5, R3 ; /* 0x0000000500007c24 */
/* 0x001fca000f8e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*00c0*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x001fca000f8e0200 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0100*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ BSSY B0, 0x260 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD R9, R3, c[0x0][0x164], RZ ; /* 0x0000590003097a24 */
/* 0x001fca00078e02ff */
/*0150*/ IADD3 R4, R0, R9, RZ ; /* 0x0000000900047210 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R4, R4, R10, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e020a */
/*0170*/ @!P0 BRA 0x210 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0180*/ UIADD3 UR4, UR8, -0x1, URZ ; /* 0xffffffff08047890 */
/* 0x000fe2000fffe03f */
/*0190*/ LDG.E R7, [R4.64+-0x4] ; /* 0xfffffc0604077981 */
/* 0x000eaa000c1e1900 */
/*01a0*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*01b0*/ @P0 LDG.E R2, [R4.64+0x4] ; /* 0x0000040604020981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ @!P0 LDG.E R6, [R4.64] ; /* 0x0000000604068981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ @P0 FADD R2, -R7, R2 ; /* 0x0000000207020221 */
/* 0x004fc80000000100 */
/*01e0*/ @P0 FMUL R2, R2, 0.5 ; /* 0x3f00000002020820 */
/* 0x000fe40000400000 */
/*01f0*/ @!P0 FADD R2, R6, -R7 ; /* 0x8000000706028221 */
/* 0x008fe20000000000 */
/*0200*/ BRA 0x250 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.WIDE R6, R9, R10, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x000fca00078e020a */
/*0220*/ LDG.E R2, [R6.64] ; /* 0x0000000606027981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000406060b7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R2, -R2, R11 ; /* 0x0000000b02027221 */
/* 0x004fe40000000100 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0270*/ @!P0 BRA 0x370 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R9, R0, -c[0x0][0x164], R9 ; /* 0x8000590000097a10 */
/* 0x000fc80007ffe009 */
/*02a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.WIDE R8, R9, R10, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc600078e020a */
/*02c0*/ ISETP.NE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fc60003f05270 */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000eb4000c1e1900 */
/*02e0*/ @P0 IADD3 R7, R3, 0x1, RZ ; /* 0x0000000103070810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x000ee8000c1e1900 */
/*0300*/ @P0 IMAD R7, R7, c[0x0][0x164], R0 ; /* 0x0000590007070a24 */
/* 0x000fc800078e0200 */
/*0310*/ @P0 IMAD.WIDE R10, R7, R10, c[0x0][0x170] ; /* 0x00005c00070a0625 */
/* 0x000fcc00078e020a */
/*0320*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000060a0b0981 */
/* 0x000ea4000c1e1900 */
/*0330*/ @P0 FADD R6, -R8, R11 ; /* 0x0000000b08060221 */
/* 0x004fc80000000100 */
/*0340*/ @P0 FMUL R6, R6, 0.5 ; /* 0x3f00000006060820 */
/* 0x000fe40000400000 */
/*0350*/ @!P0 FADD R6, R5, -R8 ; /* 0x8000000805068221 */
/* 0x008fe20000000000 */
/*0360*/ BRA 0x3d0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R4, R0.reuse, c[0x0][0x164], RZ ; /* 0x0000590000047a10 */
/* 0x040fe20007ffe0ff */
/*0380*/ IMAD.WIDE R8, R0, R10, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fc800078e020a */
/*0390*/ IMAD.WIDE R4, R4, R10, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e020a */
/*03a0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FADD R6, -R8, R5 ; /* 0x0000000508067221 */
/* 0x004fc80000000100 */
/*03d0*/ FMUL R5, R6, R6 ; /* 0x0000000606057220 */
/* 0x000fe20000400000 */
/*03e0*/ BSSY B0, 0x4d0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*03f0*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x000fc80000000005 */
/*0400*/ MUFU.RSQ R8, R5 ; /* 0x0000000500087308 */
/* 0x0000620000001400 */
/*0410*/ IADD3 R4, R5, -0xd000000, RZ ; /* 0xf300000005047810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0430*/ @!P0 BRA 0x480 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0440*/ MOV R11, 0x460 ; /* 0x00000460000b7802 */
/* 0x003fe40000000f00 */
/*0450*/ CALL.REL.NOINC 0x9c0 ; /* 0x0000056000007944 */
/* 0x000fea0003c00000 */
/*0460*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe20000000f00 */
/*0470*/ BRA 0x4c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0480*/ FMUL.FTZ R4, R5, R8 ; /* 0x0000000805047220 */
/* 0x003fe40000410000 */
/*0490*/ FMUL.FTZ R7, R8, 0.5 ; /* 0x3f00000008077820 */
/* 0x000fe40000410000 */
/*04a0*/ FFMA R5, -R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fc80000000105 */
/*04b0*/ FFMA R4, R5, R7, R4 ; /* 0x0000000705047223 */
/* 0x000fe40000000004 */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04d0*/ FADD R8, R4, 1 ; /* 0x3f80000004087421 */
/* 0x000fe20000000000 */
/*04e0*/ BSSY B0, 0x5c0 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*04f0*/ IADD3 R4, R8, 0x1800000, RZ ; /* 0x0180000008047810 */
/* 0x000fc80007ffe0ff */
/*0500*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000004047812 */
/* 0x000fc800078ec0ff */
/*0510*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ffffff, PT ; /* 0x01ffffff0400780c */
/* 0x000fda0003f04070 */
/*0520*/ @P0 BRA 0x570 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0530*/ MOV R4, 0x550 ; /* 0x0000055000047802 */
/* 0x000fe40000000f00 */
/*0540*/ CALL.REL.NOINC 0x670 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x002fe200078e0007 */
/*0560*/ BRA 0x5b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0570*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e240000001000 */
/*0580*/ FFMA R4, R8, R5, -1 ; /* 0xbf80000008047423 */
/* 0x001fc80000000005 */
/*0590*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*05a0*/ FFMA R5, R5, R4, R5 ; /* 0x0000000405057223 */
/* 0x000fe40000000005 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*05d0*/ IMAD R3, R3, c[0x0][0x164], R0 ; /* 0x0000590003037a24 */
/* 0x000fe400078e0200 */
/*05e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe400078e00ff */
/*05f0*/ IMAD R4, R4, c[0x0][0x160], R3 ; /* 0x0000580004047a24 */
/* 0x000fe400078e0203 */
/*0600*/ FMUL R7, R5.reuse, R2 ; /* 0x0000000205077220 */
/* 0x040fe40000400000 */
/*0610*/ FMUL R9, R5, R6 ; /* 0x0000000605097220 */
/* 0x000fe40000400000 */
/*0620*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0200 */
/*0630*/ IMAD.WIDE R4, R4, R0, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0200 */
/*0640*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101906 */
/*0650*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101906 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ SHF.L.U32 R5, R8, 0x1, RZ ; /* 0x0000000108057819 */
/* 0x000fe200000006ff */
/*0680*/ BSSY B1, 0x9a0 ; /* 0x0000031000017945 */
/* 0x000fe60003800000 */
/*0690*/ SHF.R.U32.HI R12, RZ, 0x18, R5 ; /* 0x00000018ff0c7819 */
/* 0x000fc40000011605 */
/*06a0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe40000000f00 */
/*06b0*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05070 */
/*06c0*/ @P0 BRA 0x770 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.SHL.U32 R7, R5, 0x2, RZ ; /* 0x0000000205077824 */
/* 0x000fca00078e00ff */
/*06e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*06f0*/ @P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005080823 */
/* 0x000fe200000000ff */
/*0700*/ @!P0 MUFU.RCP R7, R5 ; /* 0x0000000500078308 */
/* 0x000ff00000001000 */
/*0710*/ @P0 MUFU.RCP R9, R8 ; /* 0x0000000800090308 */
/* 0x000e240000001000 */
/*0720*/ @P0 FFMA R10, R8, R9, -1 ; /* 0xbf800000080a0423 */
/* 0x001fc80000000009 */
/*0730*/ @P0 FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a0221 */
/* 0x000fc80000010100 */
/*0740*/ @P0 FFMA R10, R9, R10, R9 ; /* 0x0000000a090a0223 */
/* 0x000fc80000000009 */
/*0750*/ @P0 FFMA R7, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a070823 */
/* 0x000fe200000000ff */
/*0760*/ BRA 0x990 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0770*/ IADD3 R14, R12, -0xfd, RZ ; /* 0xffffff030c0e7810 */
/* 0x000fc80007ffe0ff */
/*0780*/ ISETP.GT.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f04070 */
/*0790*/ @P0 BRA 0x980 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*07b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff0b7435 */
/* 0x000fc600000001ff */
/*07c0*/ LOP3.LUT R7, R7, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000007077812 */
/* 0x000fc800078efcff */
/*07d0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e260000001000 */
/*07e0*/ SHF.L.U32 R11, R11, R14, RZ ; /* 0x0000000e0b0b7219 */
/* 0x000fe200000006ff */
/*07f0*/ FFMA R9, R7, R8, -1 ; /* 0xbf80000007097423 */
/* 0x001fc80000000008 */
/*0800*/ FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09097221 */
/* 0x000fc80000010100 */
/*0810*/ FFMA.RM R10, R8.reuse, R9.reuse, R8.reuse ; /* 0x00000009080a7223 */
/* 0x1c0fe40000004008 */
/*0820*/ FFMA.RP R9, R8, R9, R8 ; /* 0x0000000908097223 */
/* 0x000fc60000008008 */
/*0830*/ LOP3.LUT R8, R10.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a087812 */
/* 0x040fe400078ec0ff */
/*0840*/ FSETP.NEU.FTZ.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fe40003f1d000 */
/*0850*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0860*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*0870*/ LOP3.LUT R11, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b0b7212 */
/* 0x000fe400078ec0ff */
/*0880*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fc40007ffe1ff */
/*0890*/ SHF.R.U32.HI R11, RZ, R14.reuse, R11 ; /* 0x0000000eff0b7219 */
/* 0x080fe4000001160b */
/*08a0*/ LOP3.LUT P1, RZ, R9, R14, R8, 0xf8, !PT ; /* 0x0000000e09ff7212 */
/* 0x000fe4000782f808 */
/*08b0*/ LOP3.LUT P0, RZ, R11.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010bff7812 */
/* 0x040fe4000780c0ff */
/*08c0*/ LOP3.LUT P2, RZ, R11, 0x2, RZ, 0xc0, !PT ; /* 0x000000020bff7812 */
/* 0x000fc8000784c0ff */
/*08d0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*08e0*/ LOP3.LUT P1, RZ, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05ff7812 */
/* 0x000fe4000782c0ff */
/*08f0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0900*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*0910*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f06270 */
/*0920*/ IADD3 R7, R12, -0xfc, RZ ; /* 0xffffff040c077810 */
/* 0x000fc80007ffe0ff */
/*0930*/ SHF.R.U32.HI R8, RZ, R7, R8 ; /* 0x00000007ff087219 */
/* 0x000fce0000011608 */
/*0940*/ @!P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108088810 */
/* 0x000fc80007ffe0ff */
/*0950*/ @!P1 SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108089819 */
/* 0x000fc800000006ff */
/*0960*/ LOP3.LUT R7, R8, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000008077812 */
/* 0x000fe200078ef805 */
/*0970*/ BRA 0x990 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0980*/ MUFU.RCP R7, R5 ; /* 0x0000000500077308 */
/* 0x0000640000001000 */
/*0990*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09a0*/ MOV R5, 0x0 ; /* 0x0000000000057802 */
/* 0x001fc80000000f00 */
/*09b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff64004007950 */
/* 0x000fea0003c3ffff */
/*09c0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*09d0*/ @!P0 BRA 0xaf0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*09e0*/ FSETP.GEU.FTZ.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fe20003f1e000 */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0005 */
/*0a00*/ @!P0 MOV R5, 0x7fffffff ; /* 0x7fffffff00058802 */
/* 0x000fe20000000f00 */
/*0a10*/ @!P0 BRA 0xaf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0a30*/ @P0 FADD.FTZ R5, R4, 1 ; /* 0x3f80000004050421 */
/* 0x000fe20000010000 */
/*0a40*/ @P0 BRA 0xaf0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0a50*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*0a60*/ @P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004070823 */
/* 0x000fc800000000ff */
/*0a70*/ @P0 MUFU.RSQ R8, R7 ; /* 0x0000000700080308 */
/* 0x000e240000001400 */
/*0a80*/ @P0 FMUL.FTZ R10, R7, R8 ; /* 0x00000008070a0220 */
/* 0x001fe40000410000 */
/*0a90*/ @P0 FMUL.FTZ R8, R8, 0.5 ; /* 0x3f00000008080820 */
/* 0x000fe40000410000 */
/*0aa0*/ @P0 FADD.FTZ R5, -R10, -RZ ; /* 0x800000ff0a050221 */
/* 0x000fc80000010100 */
/*0ab0*/ @P0 FFMA R9, R10, R5, R7 ; /* 0x000000050a090223 */
/* 0x000fe20000000007 */
/*0ac0*/ @!P0 MOV R5, R4 ; /* 0x0000000400058202 */
/* 0x000fc60000000f00 */
/*0ad0*/ @P0 FFMA R8, R9, R8, R10 ; /* 0x0000000809080223 */
/* 0x000fc8000000000a */
/*0ae0*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008050820 */
/* 0x000fc80000410000 */
/*0af0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0b00*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0b10*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fca0000000f00 */
/*0b20*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff4d004007950 */
/* 0x000fea0003c3ffff */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // fermi
/*
* Copyright 2018 Vrije Universiteit Amsterdam, The Netherlands
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define EPS (1.0f)
extern "C" {
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input);
}
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input) {
const int i = blockIdx.y;
const int bj = blockIdx.x;
const int wtj = threadIdx.y;
const int ttj = threadIdx.x;
const int nrThreadsW = min(1024, w);
const int nrThreadsNrThreadsW = min(32, nrThreadsW);
const int tj = wtj * (1 * nrThreadsNrThreadsW) + ttj;
if (tj < nrThreadsW) {
const int j = bj * (1 * nrThreadsW) + tj;
if (j < w) {
float dx;
if (j == 0) dx = input[j + 1 + i * (1 * w)] - input[j + i * (1 * w)];
else if (j == w - 1) dx = input[j + i * (1 * w)] - input[j - 1 + i * (1 * w)];
else dx = 0.5 * (input[j + 1 + i * (1 * w)] - input[j - 1 + i * (1 * w)]);
float dy;
if (i == 0) dy = input[j + (i + 1) * (1 * w)] - input[j + i * (1 * w)];
else if (i == h - 1) dy = input[j + i * (1 * w)] - input[j + (i - 1) * (1 * w)];
else dy = 0.5 * (input[j + (i + 1) * (1 * w)] - input[j + (i - 1) * (1 * w)]);
const float norm = sqrtf(dx * dx + dy * dy);
const float scale = 1.0 / (EPS + norm);
dxsdys[j + 0 * (1 * h * w) + i * (1 * w)] = dx * scale;
dxsdys[j + 1 * (1 * h * w) + i * (1 * w)] = dy * scale;
}
}
} | .file "tmpxft_00103720_00000000-6_fastnoise1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf
.type _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf, @function
_Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq fastnoise1Kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf, .-_Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf
.globl fastnoise1Kernel
.type fastnoise1Kernel, @function
fastnoise1Kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size fastnoise1Kernel, .-fastnoise1Kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fastnoise1Kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq fastnoise1Kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // fermi
/*
* Copyright 2018 Vrije Universiteit Amsterdam, The Netherlands
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define EPS (1.0f)
extern "C" {
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input);
}
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input) {
const int i = blockIdx.y;
const int bj = blockIdx.x;
const int wtj = threadIdx.y;
const int ttj = threadIdx.x;
const int nrThreadsW = min(1024, w);
const int nrThreadsNrThreadsW = min(32, nrThreadsW);
const int tj = wtj * (1 * nrThreadsNrThreadsW) + ttj;
if (tj < nrThreadsW) {
const int j = bj * (1 * nrThreadsW) + tj;
if (j < w) {
float dx;
if (j == 0) dx = input[j + 1 + i * (1 * w)] - input[j + i * (1 * w)];
else if (j == w - 1) dx = input[j + i * (1 * w)] - input[j - 1 + i * (1 * w)];
else dx = 0.5 * (input[j + 1 + i * (1 * w)] - input[j - 1 + i * (1 * w)]);
float dy;
if (i == 0) dy = input[j + (i + 1) * (1 * w)] - input[j + i * (1 * w)];
else if (i == h - 1) dy = input[j + i * (1 * w)] - input[j + (i - 1) * (1 * w)];
else dy = 0.5 * (input[j + (i + 1) * (1 * w)] - input[j + (i - 1) * (1 * w)]);
const float norm = sqrtf(dx * dx + dy * dy);
const float scale = 1.0 / (EPS + norm);
dxsdys[j + 0 * (1 * h * w) + i * (1 * w)] = dx * scale;
dxsdys[j + 1 * (1 * h * w) + i * (1 * w)] = dy * scale;
}
}
} | #include <hip/hip_runtime.h>
// fermi
/*
* Copyright 2018 Vrije Universiteit Amsterdam, The Netherlands
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define EPS (1.0f)
extern "C" {
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input);
}
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input) {
const int i = blockIdx.y;
const int bj = blockIdx.x;
const int wtj = threadIdx.y;
const int ttj = threadIdx.x;
const int nrThreadsW = min(1024, w);
const int nrThreadsNrThreadsW = min(32, nrThreadsW);
const int tj = wtj * (1 * nrThreadsNrThreadsW) + ttj;
if (tj < nrThreadsW) {
const int j = bj * (1 * nrThreadsW) + tj;
if (j < w) {
float dx;
if (j == 0) dx = input[j + 1 + i * (1 * w)] - input[j + i * (1 * w)];
else if (j == w - 1) dx = input[j + i * (1 * w)] - input[j - 1 + i * (1 * w)];
else dx = 0.5 * (input[j + 1 + i * (1 * w)] - input[j - 1 + i * (1 * w)]);
float dy;
if (i == 0) dy = input[j + (i + 1) * (1 * w)] - input[j + i * (1 * w)];
else if (i == h - 1) dy = input[j + i * (1 * w)] - input[j + (i - 1) * (1 * w)];
else dy = 0.5 * (input[j + (i + 1) * (1 * w)] - input[j + (i - 1) * (1 * w)]);
const float norm = sqrtf(dx * dx + dy * dy);
const float scale = 1.0 / (EPS + norm);
dxsdys[j + 0 * (1 * h * w) + i * (1 * w)] = dx * scale;
dxsdys[j + 1 * (1 * h * w) + i * (1 * w)] = dy * scale;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// fermi
/*
* Copyright 2018 Vrije Universiteit Amsterdam, The Netherlands
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define EPS (1.0f)
extern "C" {
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input);
}
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input) {
const int i = blockIdx.y;
const int bj = blockIdx.x;
const int wtj = threadIdx.y;
const int ttj = threadIdx.x;
const int nrThreadsW = min(1024, w);
const int nrThreadsNrThreadsW = min(32, nrThreadsW);
const int tj = wtj * (1 * nrThreadsNrThreadsW) + ttj;
if (tj < nrThreadsW) {
const int j = bj * (1 * nrThreadsW) + tj;
if (j < w) {
float dx;
if (j == 0) dx = input[j + 1 + i * (1 * w)] - input[j + i * (1 * w)];
else if (j == w - 1) dx = input[j + i * (1 * w)] - input[j - 1 + i * (1 * w)];
else dx = 0.5 * (input[j + 1 + i * (1 * w)] - input[j - 1 + i * (1 * w)]);
float dy;
if (i == 0) dy = input[j + (i + 1) * (1 * w)] - input[j + i * (1 * w)];
else if (i == h - 1) dy = input[j + i * (1 * w)] - input[j + (i - 1) * (1 * w)];
else dy = 0.5 * (input[j + (i + 1) * (1 * w)] - input[j + (i - 1) * (1 * w)]);
const float norm = sqrtf(dx * dx + dy * dy);
const float scale = 1.0 / (EPS + norm);
dxsdys[j + 0 * (1 * h * w) + i * (1 * w)] = dx * scale;
dxsdys[j + 1 * (1 * h * w) + i * (1 * w)] = dy * scale;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected fastnoise1Kernel
.globl fastnoise1Kernel
.p2align 8
.type fastnoise1Kernel,@function
fastnoise1Kernel:
s_load_b32 s6, s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_min_i32 s2, s6, 32
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, v0, v[1:2]
s_min_i32 s2, s6, 0x400
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s2, s14, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s6, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s4, s15, s6
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_8
s_add_i32 s7, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_5
v_add3_u32 v1, s4, 1, v0
v_add3_u32 v3, s4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0.5, v1
.LBB0_5:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v1, s4, v0
v_add3_u32 v3, s4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v1, v2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_8:
s_and_not1_saveexec_b32 s7, s5
s_cbranch_execz .LBB0_10
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v2, s5, s4
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_load_b32 s4, s[0:1], 0x0
s_cmp_lg_u32 s15, 0
s_cbranch_scc0 .LBB0_13
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s5
s_mov_b32 s5, -1
s_cbranch_scc0 .LBB0_14
s_add_i32 s5, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s5, s6, v[0:1]
s_add_i32 s5, s15, -1
v_mad_u64_u32 v[5:6], null, s5, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, 0.5, v1
s_cbranch_execz .LBB0_15
s_branch .LBB0_16
.LBB0_13:
s_branch .LBB0_17
.LBB0_14:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_16
.LBB0_15:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_add_i32 s5, s15, -1
v_mad_u64_u32 v[5:6], null, s5, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v3
.LBB0_16:
s_cbranch_execnz .LBB0_18
.LBB0_17:
v_add_nc_u32_e32 v3, s6, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v3
.LBB0_18:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v1, v1
s_load_b64 s[0:1], s[0:1], 0x8
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v7, -v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v4, v3
s_waitcnt lgkmcnt(0)
v_cmp_ge_f32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s2
v_cmp_lt_f32_e64 s2, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v6, s2
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, 1.0, v3
v_div_scale_f32 v8, null, v7, v7, 1.0
v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v8, v9, 1.0
v_fmac_f32_e32 v9, v3, v9
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_add_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v10, v9
v_mad_u64_u32 v[5:6], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, -v8, v11, v10
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v11, v0, v9
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_fma_f32 v0, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f32 v0, v0, v9, v11
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fixup_f32 v0, v0, v7, 1.0
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_mul_f32_e32 v2, v2, v0
v_mul_f32_e32 v0, v1, v0
s_clause 0x1
global_store_b32 v[3:4], v2, off
global_store_b32 v[5:6], v0, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel fastnoise1Kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size fastnoise1Kernel, .Lfunc_end0-fastnoise1Kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: fastnoise1Kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: fastnoise1Kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// fermi
/*
* Copyright 2018 Vrije Universiteit Amsterdam, The Netherlands
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define EPS (1.0f)
extern "C" {
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input);
}
__global__ void fastnoise1Kernel(const int h, const int w, float* dxsdys, const float* input) {
const int i = blockIdx.y;
const int bj = blockIdx.x;
const int wtj = threadIdx.y;
const int ttj = threadIdx.x;
const int nrThreadsW = min(1024, w);
const int nrThreadsNrThreadsW = min(32, nrThreadsW);
const int tj = wtj * (1 * nrThreadsNrThreadsW) + ttj;
if (tj < nrThreadsW) {
const int j = bj * (1 * nrThreadsW) + tj;
if (j < w) {
float dx;
if (j == 0) dx = input[j + 1 + i * (1 * w)] - input[j + i * (1 * w)];
else if (j == w - 1) dx = input[j + i * (1 * w)] - input[j - 1 + i * (1 * w)];
else dx = 0.5 * (input[j + 1 + i * (1 * w)] - input[j - 1 + i * (1 * w)]);
float dy;
if (i == 0) dy = input[j + (i + 1) * (1 * w)] - input[j + i * (1 * w)];
else if (i == h - 1) dy = input[j + i * (1 * w)] - input[j + (i - 1) * (1 * w)];
else dy = 0.5 * (input[j + (i + 1) * (1 * w)] - input[j + (i - 1) * (1 * w)]);
const float norm = sqrtf(dx * dx + dy * dy);
const float scale = 1.0 / (EPS + norm);
dxsdys[j + 0 * (1 * h * w) + i * (1 * w)] = dx * scale;
dxsdys[j + 1 * (1 * h * w) + i * (1 * w)] = dy * scale;
}
}
} | .text
.file "fastnoise1Kernel.hip"
.globl __device_stub__fastnoise1Kernel # -- Begin function __device_stub__fastnoise1Kernel
.p2align 4, 0x90
.type __device_stub__fastnoise1Kernel,@function
__device_stub__fastnoise1Kernel: # @__device_stub__fastnoise1Kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fastnoise1Kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__fastnoise1Kernel, .Lfunc_end0-__device_stub__fastnoise1Kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fastnoise1Kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type fastnoise1Kernel,@object # @fastnoise1Kernel
.section .rodata,"a",@progbits
.globl fastnoise1Kernel
.p2align 3, 0x0
fastnoise1Kernel:
.quad __device_stub__fastnoise1Kernel
.size fastnoise1Kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fastnoise1Kernel"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__fastnoise1Kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fastnoise1Kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : fastnoise1Kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC UR8, c[0x0][0x164] ; /* 0x0000590000087ab9 */
/* 0x000fe40000000800 */
/*0030*/ UISETP.LT.AND UP0, UPT, UR8, 0x400, UPT ; /* 0x000004000800788c */
/* 0x000fe2000bf01270 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ USEL UR4, UR8, 0x400, UP0 ; /* 0x0000040008047887 */
/* 0x000fc80008000000 */
/*0060*/ UISETP.GE.AND UP0, UPT, UR4, 0x20, UPT ; /* 0x000000200400788c */
/* 0x000fc8000bf06270 */
/*0070*/ USEL UR5, UR8, 0x20, !UP0 ; /* 0x0000002008057887 */
/* 0x000fcc000c000000 */
/*0080*/ IMAD R0, R0, UR5, R3 ; /* 0x0000000500007c24 */
/* 0x001fca000f8e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*00c0*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x001fca000f8e0200 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0100*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ BSSY B0, 0x260 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD R9, R3, c[0x0][0x164], RZ ; /* 0x0000590003097a24 */
/* 0x001fca00078e02ff */
/*0150*/ IADD3 R4, R0, R9, RZ ; /* 0x0000000900047210 */
/* 0x000fca0007ffe0ff */
/*0160*/ IMAD.WIDE R4, R4, R10, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e020a */
/*0170*/ @!P0 BRA 0x210 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0180*/ UIADD3 UR4, UR8, -0x1, URZ ; /* 0xffffffff08047890 */
/* 0x000fe2000fffe03f */
/*0190*/ LDG.E R7, [R4.64+-0x4] ; /* 0xfffffc0604077981 */
/* 0x000eaa000c1e1900 */
/*01a0*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*01b0*/ @P0 LDG.E R2, [R4.64+0x4] ; /* 0x0000040604020981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ @!P0 LDG.E R6, [R4.64] ; /* 0x0000000604068981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ @P0 FADD R2, -R7, R2 ; /* 0x0000000207020221 */
/* 0x004fc80000000100 */
/*01e0*/ @P0 FMUL R2, R2, 0.5 ; /* 0x3f00000002020820 */
/* 0x000fe40000400000 */
/*01f0*/ @!P0 FADD R2, R6, -R7 ; /* 0x8000000706028221 */
/* 0x008fe20000000000 */
/*0200*/ BRA 0x250 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.WIDE R6, R9, R10, c[0x0][0x170] ; /* 0x00005c0009067625 */
/* 0x000fca00078e020a */
/*0220*/ LDG.E R2, [R6.64] ; /* 0x0000000606027981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000406060b7981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R2, -R2, R11 ; /* 0x0000000b02027221 */
/* 0x004fe40000000100 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0270*/ @!P0 BRA 0x370 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R9, R0, -c[0x0][0x164], R9 ; /* 0x8000590000097a10 */
/* 0x000fc80007ffe009 */
/*02a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ IMAD.WIDE R8, R9, R10, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc600078e020a */
/*02c0*/ ISETP.NE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fc60003f05270 */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000eb4000c1e1900 */
/*02e0*/ @P0 IADD3 R7, R3, 0x1, RZ ; /* 0x0000000103070810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x000ee8000c1e1900 */
/*0300*/ @P0 IMAD R7, R7, c[0x0][0x164], R0 ; /* 0x0000590007070a24 */
/* 0x000fc800078e0200 */
/*0310*/ @P0 IMAD.WIDE R10, R7, R10, c[0x0][0x170] ; /* 0x00005c00070a0625 */
/* 0x000fcc00078e020a */
/*0320*/ @P0 LDG.E R11, [R10.64] ; /* 0x000000060a0b0981 */
/* 0x000ea4000c1e1900 */
/*0330*/ @P0 FADD R6, -R8, R11 ; /* 0x0000000b08060221 */
/* 0x004fc80000000100 */
/*0340*/ @P0 FMUL R6, R6, 0.5 ; /* 0x3f00000006060820 */
/* 0x000fe40000400000 */
/*0350*/ @!P0 FADD R6, R5, -R8 ; /* 0x8000000805068221 */
/* 0x008fe20000000000 */
/*0360*/ BRA 0x3d0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R4, R0.reuse, c[0x0][0x164], RZ ; /* 0x0000590000047a10 */
/* 0x040fe20007ffe0ff */
/*0380*/ IMAD.WIDE R8, R0, R10, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fc800078e020a */
/*0390*/ IMAD.WIDE R4, R4, R10, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e020a */
/*03a0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FADD R6, -R8, R5 ; /* 0x0000000508067221 */
/* 0x004fc80000000100 */
/*03d0*/ FMUL R5, R6, R6 ; /* 0x0000000606057220 */
/* 0x000fe20000400000 */
/*03e0*/ BSSY B0, 0x4d0 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*03f0*/ FFMA R5, R2, R2, R5 ; /* 0x0000000202057223 */
/* 0x000fc80000000005 */
/*0400*/ MUFU.RSQ R8, R5 ; /* 0x0000000500087308 */
/* 0x0000620000001400 */
/*0410*/ IADD3 R4, R5, -0xd000000, RZ ; /* 0xf300000005047810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0430*/ @!P0 BRA 0x480 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0440*/ MOV R11, 0x460 ; /* 0x00000460000b7802 */
/* 0x003fe40000000f00 */
/*0450*/ CALL.REL.NOINC 0x9c0 ; /* 0x0000056000007944 */
/* 0x000fea0003c00000 */
/*0460*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe20000000f00 */
/*0470*/ BRA 0x4c0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0480*/ FMUL.FTZ R4, R5, R8 ; /* 0x0000000805047220 */
/* 0x003fe40000410000 */
/*0490*/ FMUL.FTZ R7, R8, 0.5 ; /* 0x3f00000008077820 */
/* 0x000fe40000410000 */
/*04a0*/ FFMA R5, -R4, R4, R5 ; /* 0x0000000404057223 */
/* 0x000fc80000000105 */
/*04b0*/ FFMA R4, R5, R7, R4 ; /* 0x0000000705047223 */
/* 0x000fe40000000004 */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04d0*/ FADD R8, R4, 1 ; /* 0x3f80000004087421 */
/* 0x000fe20000000000 */
/*04e0*/ BSSY B0, 0x5c0 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*04f0*/ IADD3 R4, R8, 0x1800000, RZ ; /* 0x0180000008047810 */
/* 0x000fc80007ffe0ff */
/*0500*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000004047812 */
/* 0x000fc800078ec0ff */
/*0510*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ffffff, PT ; /* 0x01ffffff0400780c */
/* 0x000fda0003f04070 */
/*0520*/ @P0 BRA 0x570 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0530*/ MOV R4, 0x550 ; /* 0x0000055000047802 */
/* 0x000fe40000000f00 */
/*0540*/ CALL.REL.NOINC 0x670 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x002fe200078e0007 */
/*0560*/ BRA 0x5b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0570*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e240000001000 */
/*0580*/ FFMA R4, R8, R5, -1 ; /* 0xbf80000008047423 */
/* 0x001fc80000000005 */
/*0590*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*05a0*/ FFMA R5, R5, R4, R5 ; /* 0x0000000405057223 */
/* 0x000fe40000000005 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*05d0*/ IMAD R3, R3, c[0x0][0x164], R0 ; /* 0x0000590003037a24 */
/* 0x000fe400078e0200 */
/*05e0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe400078e00ff */
/*05f0*/ IMAD R4, R4, c[0x0][0x160], R3 ; /* 0x0000580004047a24 */
/* 0x000fe400078e0203 */
/*0600*/ FMUL R7, R5.reuse, R2 ; /* 0x0000000205077220 */
/* 0x040fe40000400000 */
/*0610*/ FMUL R9, R5, R6 ; /* 0x0000000605097220 */
/* 0x000fe40000400000 */
/*0620*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0200 */
/*0630*/ IMAD.WIDE R4, R4, R0, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0200 */
/*0640*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101906 */
/*0650*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101906 */
/*0660*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0670*/ SHF.L.U32 R5, R8, 0x1, RZ ; /* 0x0000000108057819 */
/* 0x000fe200000006ff */
/*0680*/ BSSY B1, 0x9a0 ; /* 0x0000031000017945 */
/* 0x000fe60003800000 */
/*0690*/ SHF.R.U32.HI R12, RZ, 0x18, R5 ; /* 0x00000018ff0c7819 */
/* 0x000fc40000011605 */
/*06a0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe40000000f00 */
/*06b0*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fda0003f05070 */
/*06c0*/ @P0 BRA 0x770 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.SHL.U32 R7, R5, 0x2, RZ ; /* 0x0000000205077824 */
/* 0x000fca00078e00ff */
/*06e0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*06f0*/ @P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005080823 */
/* 0x000fe200000000ff */
/*0700*/ @!P0 MUFU.RCP R7, R5 ; /* 0x0000000500078308 */
/* 0x000ff00000001000 */
/*0710*/ @P0 MUFU.RCP R9, R8 ; /* 0x0000000800090308 */
/* 0x000e240000001000 */
/*0720*/ @P0 FFMA R10, R8, R9, -1 ; /* 0xbf800000080a0423 */
/* 0x001fc80000000009 */
/*0730*/ @P0 FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a0221 */
/* 0x000fc80000010100 */
/*0740*/ @P0 FFMA R10, R9, R10, R9 ; /* 0x0000000a090a0223 */
/* 0x000fc80000000009 */
/*0750*/ @P0 FFMA R7, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a070823 */
/* 0x000fe200000000ff */
/*0760*/ BRA 0x990 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0770*/ IADD3 R14, R12, -0xfd, RZ ; /* 0xffffff030c0e7810 */
/* 0x000fc80007ffe0ff */
/*0780*/ ISETP.GT.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fda0003f04070 */
/*0790*/ @P0 BRA 0x980 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*07b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff0b7435 */
/* 0x000fc600000001ff */
/*07c0*/ LOP3.LUT R7, R7, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000007077812 */
/* 0x000fc800078efcff */
/*07d0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x000e260000001000 */
/*07e0*/ SHF.L.U32 R11, R11, R14, RZ ; /* 0x0000000e0b0b7219 */
/* 0x000fe200000006ff */
/*07f0*/ FFMA R9, R7, R8, -1 ; /* 0xbf80000007097423 */
/* 0x001fc80000000008 */
/*0800*/ FADD.FTZ R9, -R9, -RZ ; /* 0x800000ff09097221 */
/* 0x000fc80000010100 */
/*0810*/ FFMA.RM R10, R8.reuse, R9.reuse, R8.reuse ; /* 0x00000009080a7223 */
/* 0x1c0fe40000004008 */
/*0820*/ FFMA.RP R9, R8, R9, R8 ; /* 0x0000000908097223 */
/* 0x000fc60000008008 */
/*0830*/ LOP3.LUT R8, R10.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a087812 */
/* 0x040fe400078ec0ff */
/*0840*/ FSETP.NEU.FTZ.AND P0, PT, R10, R9, PT ; /* 0x000000090a00720b */
/* 0x000fe40003f1d000 */
/*0850*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0860*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*0870*/ LOP3.LUT R11, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b0b7212 */
/* 0x000fe400078ec0ff */
/*0880*/ IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff09097210 */
/* 0x000fc40007ffe1ff */
/*0890*/ SHF.R.U32.HI R11, RZ, R14.reuse, R11 ; /* 0x0000000eff0b7219 */
/* 0x080fe4000001160b */
/*08a0*/ LOP3.LUT P1, RZ, R9, R14, R8, 0xf8, !PT ; /* 0x0000000e09ff7212 */
/* 0x000fe4000782f808 */
/*08b0*/ LOP3.LUT P0, RZ, R11.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x000000010bff7812 */
/* 0x040fe4000780c0ff */
/*08c0*/ LOP3.LUT P2, RZ, R11, 0x2, RZ, 0xc0, !PT ; /* 0x000000020bff7812 */
/* 0x000fc8000784c0ff */
/*08d0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*08e0*/ LOP3.LUT P1, RZ, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05ff7812 */
/* 0x000fe4000782c0ff */
/*08f0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*0900*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*0910*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f06270 */
/*0920*/ IADD3 R7, R12, -0xfc, RZ ; /* 0xffffff040c077810 */
/* 0x000fc80007ffe0ff */
/*0930*/ SHF.R.U32.HI R8, RZ, R7, R8 ; /* 0x00000007ff087219 */
/* 0x000fce0000011608 */
/*0940*/ @!P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108088810 */
/* 0x000fc80007ffe0ff */
/*0950*/ @!P1 SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108089819 */
/* 0x000fc800000006ff */
/*0960*/ LOP3.LUT R7, R8, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000008077812 */
/* 0x000fe200078ef805 */
/*0970*/ BRA 0x990 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0980*/ MUFU.RCP R7, R5 ; /* 0x0000000500077308 */
/* 0x0000640000001000 */
/*0990*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09a0*/ MOV R5, 0x0 ; /* 0x0000000000057802 */
/* 0x001fc80000000f00 */
/*09b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff64004007950 */
/* 0x000fea0003c3ffff */
/*09c0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*09d0*/ @!P0 BRA 0xaf0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*09e0*/ FSETP.GEU.FTZ.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x000fe20003f1e000 */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0005 */
/*0a00*/ @!P0 MOV R5, 0x7fffffff ; /* 0x7fffffff00058802 */
/* 0x000fe20000000f00 */
/*0a10*/ @!P0 BRA 0xaf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0a30*/ @P0 FADD.FTZ R5, R4, 1 ; /* 0x3f80000004050421 */
/* 0x000fe20000010000 */
/*0a40*/ @P0 BRA 0xaf0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0a50*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*0a60*/ @P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004070823 */
/* 0x000fc800000000ff */
/*0a70*/ @P0 MUFU.RSQ R8, R7 ; /* 0x0000000700080308 */
/* 0x000e240000001400 */
/*0a80*/ @P0 FMUL.FTZ R10, R7, R8 ; /* 0x00000008070a0220 */
/* 0x001fe40000410000 */
/*0a90*/ @P0 FMUL.FTZ R8, R8, 0.5 ; /* 0x3f00000008080820 */
/* 0x000fe40000410000 */
/*0aa0*/ @P0 FADD.FTZ R5, -R10, -RZ ; /* 0x800000ff0a050221 */
/* 0x000fc80000010100 */
/*0ab0*/ @P0 FFMA R9, R10, R5, R7 ; /* 0x000000050a090223 */
/* 0x000fe20000000007 */
/*0ac0*/ @!P0 MOV R5, R4 ; /* 0x0000000400058202 */
/* 0x000fc60000000f00 */
/*0ad0*/ @P0 FFMA R8, R9, R8, R10 ; /* 0x0000000809080223 */
/* 0x000fc8000000000a */
/*0ae0*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008050820 */
/* 0x000fc80000410000 */
/*0af0*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0b00*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0b10*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fca0000000f00 */
/*0b20*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff4d004007950 */
/* 0x000fea0003c3ffff */
/*0b30*/ BRA 0xb30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected fastnoise1Kernel
.globl fastnoise1Kernel
.p2align 8
.type fastnoise1Kernel,@function
fastnoise1Kernel:
s_load_b32 s6, s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_min_i32 s2, s6, 32
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, v0, v[1:2]
s_min_i32 s2, s6, 0x400
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s2, s14, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s6, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_19
s_load_b64 s[2:3], s[0:1], 0x10
s_mul_i32 s4, s15, s6
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_8
s_add_i32 s7, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_5
v_add3_u32 v1, s4, 1, v0
v_add3_u32 v3, s4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, 0.5, v1
.LBB0_5:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v1, s4, v0
v_add3_u32 v3, s4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v1, v2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_8:
s_and_not1_saveexec_b32 s7, s5
s_cbranch_execz .LBB0_10
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v2, s5, s4
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
s_load_b32 s4, s[0:1], 0x0
s_cmp_lg_u32 s15, 0
s_cbranch_scc0 .LBB0_13
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s5
s_mov_b32 s5, -1
s_cbranch_scc0 .LBB0_14
s_add_i32 s5, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s5, s6, v[0:1]
s_add_i32 s5, s15, -1
v_mad_u64_u32 v[5:6], null, s5, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, 0.5, v1
s_cbranch_execz .LBB0_15
s_branch .LBB0_16
.LBB0_13:
s_branch .LBB0_17
.LBB0_14:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_16
.LBB0_15:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_add_i32 s5, s15, -1
v_mad_u64_u32 v[5:6], null, s5, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v3
.LBB0_16:
s_cbranch_execnz .LBB0_18
.LBB0_17:
v_add_nc_u32_e32 v3, s6, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_clause 0x1
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v1, v1, v3
.LBB0_18:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v1, v1
s_load_b64 s[0:1], s[0:1], 0x8
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v7, -v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v4, v3
s_waitcnt lgkmcnt(0)
v_cmp_ge_f32_e64 s2, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s2
v_cmp_lt_f32_e64 s2, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v6, s2
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, 1.0, v3
v_div_scale_f32 v8, null, v7, v7, 1.0
v_div_scale_f32 v10, vcc_lo, 1.0, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v8, v9, 1.0
v_fmac_f32_e32 v9, v3, v9
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_add_i32 s15, s15, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v10, v9
v_mad_u64_u32 v[5:6], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, -v8, v11, v10
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v11, v0, v9
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_fma_f32 v0, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fmas_f32 v0, v0, v9, v11
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fixup_f32 v0, v0, v7, 1.0
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_mul_f32_e32 v2, v2, v0
v_mul_f32_e32 v0, v1, v0
s_clause 0x1
global_store_b32 v[3:4], v2, off
global_store_b32 v[5:6], v0, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel fastnoise1Kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size fastnoise1Kernel, .Lfunc_end0-fastnoise1Kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: fastnoise1Kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: fastnoise1Kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103720_00000000-6_fastnoise1Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf
.type _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf, @function
_Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq fastnoise1Kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf, .-_Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf
.globl fastnoise1Kernel
.type fastnoise1Kernel, @function
fastnoise1Kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16fastnoise1KerneliiPfPKfiiPfPKf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size fastnoise1Kernel, .-fastnoise1Kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "fastnoise1Kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq fastnoise1Kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fastnoise1Kernel.hip"
.globl __device_stub__fastnoise1Kernel # -- Begin function __device_stub__fastnoise1Kernel
.p2align 4, 0x90
.type __device_stub__fastnoise1Kernel,@function
__device_stub__fastnoise1Kernel: # @__device_stub__fastnoise1Kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $fastnoise1Kernel, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__fastnoise1Kernel, .Lfunc_end0-__device_stub__fastnoise1Kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $fastnoise1Kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type fastnoise1Kernel,@object # @fastnoise1Kernel
.section .rodata,"a",@progbits
.globl fastnoise1Kernel
.p2align 3, 0x0
fastnoise1Kernel:
.quad __device_stub__fastnoise1Kernel
.size fastnoise1Kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "fastnoise1Kernel"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__fastnoise1Kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fastnoise1Kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void update_linear_and_quadratic_terms_kernel( int32_t n, float old_num_frames, float prior_offset, float* cur_tot_weight, int32_t max_count, float* quadratic, float* linear) {
float cur_weight = *cur_tot_weight;
float new_num_frames = old_num_frames + cur_weight;
float prior_scale_change = 1.0f;
if(max_count!=0.0f) {
float old_prior_scale = max(old_num_frames, (float)max_count) / max_count;
float new_prior_scale = max(new_num_frames, (float)max_count) / max_count;
prior_scale_change += new_prior_scale - old_prior_scale;
}
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
i += blockDim.x * gridDim.x) {
int32_t diag_idx = ((i + 1) * (i + 2) / 2) - 1;
quadratic[diag_idx] += prior_scale_change;
}
if (threadIdx.x == 0 && blockIdx.x==0) {
linear[0] += prior_offset * prior_scale_change;
}
} | code for sm_80
Function : _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff007424 */
/* 0x000fd600078e00ff */
/*0040*/ @!P0 BRA 0x260 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000162000c1e1900 */
/*0080*/ I2F R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e700000201400 */
/*0090*/ MUFU.RCP R3, R0 ; /* 0x0000000000037308 */
/* 0x002e620000001000 */
/*00a0*/ FMNMX R7, R0, c[0x0][0x164], !PT ; /* 0x0000590000077a09 */
/* 0x000fce0007800000 */
/*00b0*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000ea20000000000 */
/*00c0*/ FFMA R6, -R0, R3, 1 ; /* 0x3f80000000067423 */
/* 0x002fc80000000103 */
/*00d0*/ FFMA R6, R3, R6, R3 ; /* 0x0000000603067223 */
/* 0x000fc80000000003 */
/*00e0*/ FFMA R3, R7, R6, RZ ; /* 0x0000000607037223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R8, -R0, R3, R7 ; /* 0x0000000300087223 */
/* 0x000fc80000000107 */
/*0100*/ FFMA R3, R6, R8, R3 ; /* 0x0000000806037223 */
/* 0x000fe20000000003 */
/*0110*/ @!P0 BRA 0x160 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0007 */
/*0130*/ MOV R4, 0x150 ; /* 0x0000015000047802 */
/* 0x000fe40000000f00 */
/*0140*/ CALL.REL.NOINC 0x440 ; /* 0x000002f000007944 */
/* 0x020fea0003c00000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0160*/ MUFU.RCP R7, R0 ; /* 0x0000000000077308 */
/* 0x001e220000001000 */
/*0170*/ FADD R5, R2, c[0x0][0x164] ; /* 0x0000590002057621 */
/* 0x020fca0000000000 */
/*0180*/ FMNMX R5, R0, R5, !PT ; /* 0x0000000500057209 */
/* 0x000fc80007800000 */
/*0190*/ FCHK P0, R5, R0 ; /* 0x0000000005007302 */
/* 0x000e620000000000 */
/*01a0*/ FFMA R2, -R0, R7, 1 ; /* 0x3f80000000027423 */
/* 0x001fc80000000107 */
/*01b0*/ FFMA R4, R7, R2, R7 ; /* 0x0000000207047223 */
/* 0x000fc80000000007 */
/*01c0*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R7, -R0, R2, R5 ; /* 0x0000000200077223 */
/* 0x000fc80000000105 */
/*01e0*/ FFMA R2, R4, R7, R2 ; /* 0x0000000704027223 */
/* 0x000fe20000000002 */
/*01f0*/ @!P0 BRA 0x240 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0210*/ MOV R4, 0x230 ; /* 0x0000023000047802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x440 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0006 */
/*0240*/ FADD R2, R2, -R3 ; /* 0x8000000302027221 */
/* 0x000fc80000000000 */
/*0250*/ FADD R0, R2, 1 ; /* 0x3f80000002007421 */
/* 0x000fe40000000000 */
/*0260*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0270*/ BSSY B0, 0x3d0 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*0280*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0290*/ IMAD R2, R3, c[0x0][0x0], R4 ; /* 0x0000000003027a24 */
/* 0x001fe200078e0204 */
/*02a0*/ LOP3.LUT P0, RZ, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304ff7212 */
/* 0x000fc8000780fcff */
/*02b0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f26270 */
/*02c0*/ @P1 BRA 0x3c0 ; /* 0x000000f000001947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0002 */
/*02e0*/ IADD3 R2, R4.reuse, 0x2, RZ ; /* 0x0000000204027810 */
/* 0x041fe40007ffe0ff */
/*02f0*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fca0007ffe0ff */
/*0300*/ IMAD R2, R2, R3, RZ ; /* 0x0000000302027224 */
/* 0x000fe400078e02ff */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0320*/ LEA.HI R2, R2, R2, RZ, 0x1 ; /* 0x0000000202027211 */
/* 0x000fc800078f08ff */
/*0330*/ LEA.HI.SX32 R2, R2, 0xffffffff, 0x1f ; /* 0xffffffff02027811 */
/* 0x000fca00078ffaff */
/*0340*/ IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0203 */
/*0350*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD R4, R7, c[0x0][0xc], R4 ; /* 0x0000030007047a24 */
/* 0x000fca00078e0204 */
/*0380*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fe20003f26270 */
/*0390*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x004fca0000000000 */
/*03a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*03b0*/ @!P1 BRA 0x2e0 ; /* 0xffffff2000009947 */
/* 0x000fea000383ffff */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x001fe400078e00ff */
/*03f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0400*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FFMA R5, R0, c[0x0][0x168], R5 ; /* 0x00005a0000057a23 */
/* 0x004fca0000000005 */
/*0420*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ SHF.R.U32.HI R6, RZ, 0x17, R0 ; /* 0x00000017ff067819 */
/* 0x000fe40000011600 */
/*0450*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fe40000011608 */
/*0460*/ LOP3.LUT R13, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060d7812 */
/* 0x000fe200078ec0ff */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0480*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe200078ec0ff */
/*0490*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*04a0*/ IADD3 R10, R13, -0x1, RZ ; /* 0xffffffff0d0a7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R9, R11, -0x1, RZ ; /* 0xffffffff0b097810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*04d0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*04e0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*04f0*/ @!P0 BRA 0x670 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0510*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0530*/ @P0 BRA 0xa50 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0550*/ @!P0 BRA 0xa30 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0560*/ FSETP.NEU.FTZ.AND P2, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f5d200 */
/*0570*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*0580*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0590*/ @!P1 BRA !P2, 0xa30 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*05a0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05b0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*05c0*/ @P1 BRA 0xa10 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*05d0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*05e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*05f0*/ @P0 BRA 0x9e0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0610*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0620*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0630*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0640*/ @!P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008058823 */
/* 0x000fe400000000ff */
/*0650*/ @!P1 FFMA R6, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000069823 */
/* 0x000fe200000000ff */
/*0660*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0670*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fca00078eb8ff */
/*0680*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a09 */
/*0690*/ IADD3 R6, R11, -0x7f, RZ ; /* 0xffffff810b067810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*06b0*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fe40000010100 */
/*06c0*/ IMAD R5, R6, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x000fe400078e0205 */
/*06d0*/ FFMA R11, R8, R10, 1 ; /* 0x3f800000080b7423 */
/* 0x001fc8000000000a */
/*06e0*/ FFMA R12, R8, R11, R8 ; /* 0x0000000b080c7223 */
/* 0x000fc80000000008 */
/*06f0*/ FFMA R8, R5, R12, RZ ; /* 0x0000000c05087223 */
/* 0x000fc800000000ff */
/*0700*/ FFMA R11, R10, R8, R5 ; /* 0x000000080a0b7223 */
/* 0x000fc80000000005 */
/*0710*/ FFMA R11, R12, R11, R8 ; /* 0x0000000b0c0b7223 */
/* 0x000fe20000000008 */
/*0720*/ IADD3 R8, R6, 0x7f, -R13 ; /* 0x0000007f06087810 */
/* 0x000fc60007ffe80d */
/*0730*/ FFMA R10, R10, R11, R5 ; /* 0x0000000b0a0a7223 */
/* 0x000fe40000000005 */
/*0740*/ IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108087824 */
/* 0x000fe400078e0207 */
/*0750*/ FFMA R5, R12, R10, R11 ; /* 0x0000000a0c057223 */
/* 0x000fca000000000b */
/*0760*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*0770*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R13, R6, 0x1, R8 ; /* 0x00000001060d7824 */
/* 0x000fca00078e0208 */
/*0790*/ IADD3 R6, R13, -0x1, RZ ; /* 0xffffffff0d067810 */
/* 0x000fc80007ffe0ff */
/*07a0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*07b0*/ @!P0 BRA 0x9c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*07d0*/ @P0 BRA 0x990 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*07f0*/ @P0 BRA 0xa60 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0810*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0820*/ @!P0 BRA 0xa60 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0830*/ FFMA.RZ R6, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe2000000c00b */
/*0840*/ IADD3 R9, R13.reuse, 0x20, RZ ; /* 0x000000200d097810 */
/* 0x040fe20007ffe0ff */
/*0850*/ FFMA.RM R7, R12, R10.reuse, R11.reuse ; /* 0x0000000a0c077223 */
/* 0x180fe2000000400b */
/*0860*/ ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x040fe40003f45270 */
/*0870*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0880*/ FFMA.RP R6, R12, R10, R11 ; /* 0x0000000a0c067223 */
/* 0x000fe2000000800b */
/*0890*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*08a0*/ IMAD.MOV R10, RZ, RZ, -R13 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0d */
/*08b0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*08c0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*08d0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*08e0*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*08f0*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0900*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0910*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0920*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0930*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0940*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0950*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0960*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0970*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0980*/ BRA 0xa60 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09a0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*09b0*/ BRA 0xa60 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe200078e0205 */
/*09d0*/ BRA 0xa60 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fc800078e4805 */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a10*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078e4805 */
/*0a20*/ BRA 0xa60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a30*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0a40*/ BRA 0xa60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a50*/ FADD.FTZ R5, R8, R0 ; /* 0x0000000008057221 */
/* 0x000fc80000010000 */
/*0a60*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*0a70*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a80*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff57004007950 */
/* 0x000fea0003c3ffff */
/*0a90*/ BRA 0xa90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update_linear_and_quadratic_terms_kernel( int32_t n, float old_num_frames, float prior_offset, float* cur_tot_weight, int32_t max_count, float* quadratic, float* linear) {
float cur_weight = *cur_tot_weight;
float new_num_frames = old_num_frames + cur_weight;
float prior_scale_change = 1.0f;
if(max_count!=0.0f) {
float old_prior_scale = max(old_num_frames, (float)max_count) / max_count;
float new_prior_scale = max(new_num_frames, (float)max_count) / max_count;
prior_scale_change += new_prior_scale - old_prior_scale;
}
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
i += blockDim.x * gridDim.x) {
int32_t diag_idx = ((i + 1) * (i + 2) / 2) - 1;
quadratic[diag_idx] += prior_scale_change;
}
if (threadIdx.x == 0 && blockIdx.x==0) {
linear[0] += prior_offset * prior_scale_change;
}
} | .file "tmpxft_000dffc9_00000000-6_update_linear_and_quadratic_terms_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_
.type _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_, @function
_Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movss %xmm0, 40(%rsp)
movss %xmm1, 36(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_, .-_Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_
.globl _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.type _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, @function
_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, .-_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update_linear_and_quadratic_terms_kernel( int32_t n, float old_num_frames, float prior_offset, float* cur_tot_weight, int32_t max_count, float* quadratic, float* linear) {
float cur_weight = *cur_tot_weight;
float new_num_frames = old_num_frames + cur_weight;
float prior_scale_change = 1.0f;
if(max_count!=0.0f) {
float old_prior_scale = max(old_num_frames, (float)max_count) / max_count;
float new_prior_scale = max(new_num_frames, (float)max_count) / max_count;
prior_scale_change += new_prior_scale - old_prior_scale;
}
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
i += blockDim.x * gridDim.x) {
int32_t diag_idx = ((i + 1) * (i + 2) / 2) - 1;
quadratic[diag_idx] += prior_scale_change;
}
if (threadIdx.x == 0 && blockIdx.x==0) {
linear[0] += prior_offset * prior_scale_change;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_linear_and_quadratic_terms_kernel( int32_t n, float old_num_frames, float prior_offset, float* cur_tot_weight, int32_t max_count, float* quadratic, float* linear) {
float cur_weight = *cur_tot_weight;
float new_num_frames = old_num_frames + cur_weight;
float prior_scale_change = 1.0f;
if(max_count!=0.0f) {
float old_prior_scale = max(old_num_frames, (float)max_count) / max_count;
float new_prior_scale = max(new_num_frames, (float)max_count) / max_count;
prior_scale_change += new_prior_scale - old_prior_scale;
}
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
i += blockDim.x * gridDim.x) {
int32_t diag_idx = ((i + 1) * (i + 2) / 2) - 1;
quadratic[diag_idx] += prior_scale_change;
}
if (threadIdx.x == 0 && blockIdx.x==0) {
linear[0] += prior_offset * prior_scale_change;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_linear_and_quadratic_terms_kernel( int32_t n, float old_num_frames, float prior_offset, float* cur_tot_weight, int32_t max_count, float* quadratic, float* linear) {
float cur_weight = *cur_tot_weight;
float new_num_frames = old_num_frames + cur_weight;
float prior_scale_change = 1.0f;
if(max_count!=0.0f) {
float old_prior_scale = max(old_num_frames, (float)max_count) / max_count;
float new_prior_scale = max(new_num_frames, (float)max_count) / max_count;
prior_scale_change += new_prior_scale - old_prior_scale;
}
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
i += blockDim.x * gridDim.x) {
int32_t diag_idx = ((i + 1) * (i + 2) / 2) - 1;
quadratic[diag_idx] += prior_scale_change;
}
if (threadIdx.x == 0 && blockIdx.x==0) {
linear[0] += prior_offset * prior_scale_change;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.globl _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.p2align 8
.type _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_,@function
_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x4
v_cvt_f32_i32_e32 v1, s2
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[4:5], 0x0
v_max_f32_e64 v2, s3, s3
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v3, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f32_e32 v3, v3, v1
v_div_scale_f32 v5, null, v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v5, v7, 1.0
v_dual_max_f32 v2, v2, v1 :: v_dual_fmac_f32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v1, v1, v2
v_div_scale_f32 v10, vcc_lo, v2, v1, v2
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s2, v3, v1, v3
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v4, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v7, v11
v_div_fixup_f32 v2, v4, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v5, v1, v3
v_sub_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v1
s_branch .LBB0_3
.LBB0_2:
v_mov_b32_e32 v3, 1.0
.LBB0_3:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b32 s3, s[2:3], 0x0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, -4
s_mul_i32 s3, s3, s6
s_addc_u32 s6, s9, -1
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v2, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v2, v1, v[2:3]
v_lshrrev_b32_e32 v2, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v4, v2
v_ashrrev_i32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s6, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v3, v2 :: v_dual_add_nc_u32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
global_store_b32 v[4:5], v2, off
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
v_or_b32_e32 v0, s15, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b32 s0, s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, s0, v3
global_store_b32 v0, v1, s[2:3]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, .Lfunc_end0-_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_linear_and_quadratic_terms_kernel( int32_t n, float old_num_frames, float prior_offset, float* cur_tot_weight, int32_t max_count, float* quadratic, float* linear) {
float cur_weight = *cur_tot_weight;
float new_num_frames = old_num_frames + cur_weight;
float prior_scale_change = 1.0f;
if(max_count!=0.0f) {
float old_prior_scale = max(old_num_frames, (float)max_count) / max_count;
float new_prior_scale = max(new_num_frames, (float)max_count) / max_count;
prior_scale_change += new_prior_scale - old_prior_scale;
}
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < n;
i += blockDim.x * gridDim.x) {
int32_t diag_idx = ((i + 1) * (i + 2) / 2) - 1;
quadratic[diag_idx] += prior_scale_change;
}
if (threadIdx.x == 0 && blockIdx.x==0) {
linear[0] += prior_offset * prior_scale_change;
}
} | .text
.file "update_linear_and_quadratic_terms_kernel.hip"
.globl _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_ # -- Begin function _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.p2align 4, 0x90
.type _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_,@function
_Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_: # @_Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %rsi, 88(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_, .Lfunc_end0-_Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_,@object # @_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.section .rodata,"a",@progbits
.globl _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.p2align 3, 0x0
_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_:
.quad _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.size _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff007424 */
/* 0x000fd600078e00ff */
/*0040*/ @!P0 BRA 0x260 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000162000c1e1900 */
/*0080*/ I2F R0, c[0x0][0x178] ; /* 0x00005e0000007b06 */
/* 0x000e700000201400 */
/*0090*/ MUFU.RCP R3, R0 ; /* 0x0000000000037308 */
/* 0x002e620000001000 */
/*00a0*/ FMNMX R7, R0, c[0x0][0x164], !PT ; /* 0x0000590000077a09 */
/* 0x000fce0007800000 */
/*00b0*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x000ea20000000000 */
/*00c0*/ FFMA R6, -R0, R3, 1 ; /* 0x3f80000000067423 */
/* 0x002fc80000000103 */
/*00d0*/ FFMA R6, R3, R6, R3 ; /* 0x0000000603067223 */
/* 0x000fc80000000003 */
/*00e0*/ FFMA R3, R7, R6, RZ ; /* 0x0000000607037223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R8, -R0, R3, R7 ; /* 0x0000000300087223 */
/* 0x000fc80000000107 */
/*0100*/ FFMA R3, R6, R8, R3 ; /* 0x0000000806037223 */
/* 0x000fe20000000003 */
/*0110*/ @!P0 BRA 0x160 ; /* 0x0000004000008947 */
/* 0x004fea0003800000 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe200078e0007 */
/*0130*/ MOV R4, 0x150 ; /* 0x0000015000047802 */
/* 0x000fe40000000f00 */
/*0140*/ CALL.REL.NOINC 0x440 ; /* 0x000002f000007944 */
/* 0x020fea0003c00000 */
/*0150*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*0160*/ MUFU.RCP R7, R0 ; /* 0x0000000000077308 */
/* 0x001e220000001000 */
/*0170*/ FADD R5, R2, c[0x0][0x164] ; /* 0x0000590002057621 */
/* 0x020fca0000000000 */
/*0180*/ FMNMX R5, R0, R5, !PT ; /* 0x0000000500057209 */
/* 0x000fc80007800000 */
/*0190*/ FCHK P0, R5, R0 ; /* 0x0000000005007302 */
/* 0x000e620000000000 */
/*01a0*/ FFMA R2, -R0, R7, 1 ; /* 0x3f80000000027423 */
/* 0x001fc80000000107 */
/*01b0*/ FFMA R4, R7, R2, R7 ; /* 0x0000000207047223 */
/* 0x000fc80000000007 */
/*01c0*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*01d0*/ FFMA R7, -R0, R2, R5 ; /* 0x0000000200077223 */
/* 0x000fc80000000105 */
/*01e0*/ FFMA R2, R4, R7, R2 ; /* 0x0000000704027223 */
/* 0x000fe20000000002 */
/*01f0*/ @!P0 BRA 0x240 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0210*/ MOV R4, 0x230 ; /* 0x0000023000047802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x440 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0006 */
/*0240*/ FADD R2, R2, -R3 ; /* 0x8000000302027221 */
/* 0x000fc80000000000 */
/*0250*/ FADD R0, R2, 1 ; /* 0x3f80000002007421 */
/* 0x000fe40000000000 */
/*0260*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0270*/ BSSY B0, 0x3d0 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*0280*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0290*/ IMAD R2, R3, c[0x0][0x0], R4 ; /* 0x0000000003027a24 */
/* 0x001fe200078e0204 */
/*02a0*/ LOP3.LUT P0, RZ, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304ff7212 */
/* 0x000fc8000780fcff */
/*02b0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f26270 */
/*02c0*/ @P1 BRA 0x3c0 ; /* 0x000000f000001947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0002 */
/*02e0*/ IADD3 R2, R4.reuse, 0x2, RZ ; /* 0x0000000204027810 */
/* 0x041fe40007ffe0ff */
/*02f0*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fca0007ffe0ff */
/*0300*/ IMAD R2, R2, R3, RZ ; /* 0x0000000302027224 */
/* 0x000fe400078e02ff */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0320*/ LEA.HI R2, R2, R2, RZ, 0x1 ; /* 0x0000000202027211 */
/* 0x000fc800078f08ff */
/*0330*/ LEA.HI.SX32 R2, R2, 0xffffffff, 0x1f ; /* 0xffffffff02027811 */
/* 0x000fca00078ffaff */
/*0340*/ IMAD.WIDE R2, R2, R3, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0203 */
/*0350*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD R4, R7, c[0x0][0xc], R4 ; /* 0x0000030007047a24 */
/* 0x000fca00078e0204 */
/*0380*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fe20003f26270 */
/*0390*/ FADD R5, R5, R0 ; /* 0x0000000005057221 */
/* 0x004fca0000000000 */
/*03a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*03b0*/ @!P1 BRA 0x2e0 ; /* 0xffffff2000009947 */
/* 0x000fea000383ffff */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x001fe400078e00ff */
/*03f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fca00078e00ff */
/*0400*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FFMA R5, R0, c[0x0][0x168], R5 ; /* 0x00005a0000057a23 */
/* 0x004fca0000000005 */
/*0420*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0430*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0440*/ SHF.R.U32.HI R6, RZ, 0x17, R0 ; /* 0x00000017ff067819 */
/* 0x000fe40000011600 */
/*0450*/ SHF.R.U32.HI R5, RZ, 0x17, R8 ; /* 0x00000017ff057819 */
/* 0x000fe40000011608 */
/*0460*/ LOP3.LUT R13, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060d7812 */
/* 0x000fe200078ec0ff */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0000 */
/*0480*/ LOP3.LUT R11, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050b7812 */
/* 0x000fe200078ec0ff */
/*0490*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0008 */
/*04a0*/ IADD3 R10, R13, -0x1, RZ ; /* 0xffffffff0d0a7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ IADD3 R9, R11, -0x1, RZ ; /* 0xffffffff0b097810 */
/* 0x000fc40007ffe0ff */
/*04c0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*04d0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*04e0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*04f0*/ @!P0 BRA 0x670 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0500*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0510*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0530*/ @P0 BRA 0xa50 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0550*/ @!P0 BRA 0xa30 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0560*/ FSETP.NEU.FTZ.AND P2, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f5d200 */
/*0570*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*0580*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*0590*/ @!P1 BRA !P2, 0xa30 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*05a0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05b0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*05c0*/ @P1 BRA 0xa10 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*05d0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*05e0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*05f0*/ @P0 BRA 0x9e0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0610*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0620*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0630*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0640*/ @!P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008058823 */
/* 0x000fe400000000ff */
/*0650*/ @!P1 FFMA R6, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000069823 */
/* 0x000fe200000000ff */
/*0660*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0670*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fca00078eb8ff */
/*0680*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a09 */
/*0690*/ IADD3 R6, R11, -0x7f, RZ ; /* 0xffffff810b067810 */
/* 0x000fc60007ffe0ff */
/*06a0*/ MUFU.RCP R8, R9 ; /* 0x0000000900087308 */
/* 0x000e220000001000 */
/*06b0*/ FADD.FTZ R10, -R9, -RZ ; /* 0x800000ff090a7221 */
/* 0x000fe40000010100 */
/*06c0*/ IMAD R5, R6, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x000fe400078e0205 */
/*06d0*/ FFMA R11, R8, R10, 1 ; /* 0x3f800000080b7423 */
/* 0x001fc8000000000a */
/*06e0*/ FFMA R12, R8, R11, R8 ; /* 0x0000000b080c7223 */
/* 0x000fc80000000008 */
/*06f0*/ FFMA R8, R5, R12, RZ ; /* 0x0000000c05087223 */
/* 0x000fc800000000ff */
/*0700*/ FFMA R11, R10, R8, R5 ; /* 0x000000080a0b7223 */
/* 0x000fc80000000005 */
/*0710*/ FFMA R11, R12, R11, R8 ; /* 0x0000000b0c0b7223 */
/* 0x000fe20000000008 */
/*0720*/ IADD3 R8, R6, 0x7f, -R13 ; /* 0x0000007f06087810 */
/* 0x000fc60007ffe80d */
/*0730*/ FFMA R10, R10, R11, R5 ; /* 0x0000000b0a0a7223 */
/* 0x000fe40000000005 */
/*0740*/ IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108087824 */
/* 0x000fe400078e0207 */
/*0750*/ FFMA R5, R12, R10, R11 ; /* 0x0000000a0c057223 */
/* 0x000fca000000000b */
/*0760*/ SHF.R.U32.HI R6, RZ, 0x17, R5 ; /* 0x00000017ff067819 */
/* 0x000fc80000011605 */
/*0770*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R13, R6, 0x1, R8 ; /* 0x00000001060d7824 */
/* 0x000fca00078e0208 */
/*0790*/ IADD3 R6, R13, -0x1, RZ ; /* 0xffffffff0d067810 */
/* 0x000fc80007ffe0ff */
/*07a0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*07b0*/ @!P0 BRA 0x9c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*07d0*/ @P0 BRA 0x990 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*07f0*/ @P0 BRA 0xa60 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0810*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0820*/ @!P0 BRA 0xa60 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0830*/ FFMA.RZ R6, R12.reuse, R10.reuse, R11.reuse ; /* 0x0000000a0c067223 */
/* 0x1c0fe2000000c00b */
/*0840*/ IADD3 R9, R13.reuse, 0x20, RZ ; /* 0x000000200d097810 */
/* 0x040fe20007ffe0ff */
/*0850*/ FFMA.RM R7, R12, R10.reuse, R11.reuse ; /* 0x0000000a0c077223 */
/* 0x180fe2000000400b */
/*0860*/ ISETP.NE.AND P2, PT, R13.reuse, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x040fe40003f45270 */
/*0870*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0880*/ FFMA.RP R6, R12, R10, R11 ; /* 0x0000000a0c067223 */
/* 0x000fe2000000800b */
/*0890*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*08a0*/ IMAD.MOV R10, RZ, RZ, -R13 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0d */
/*08b0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*08c0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fc40003f1d000 */
/*08d0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*08e0*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*08f0*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0900*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0910*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0920*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fc40000011607 */
/*0930*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0940*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0950*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0960*/ IMAD.IADD R6, R9, 0x1, R6 ; /* 0x0000000109067824 */
/* 0x000fca00078e0206 */
/*0970*/ LOP3.LUT R5, R6, R5, RZ, 0xfc, !PT ; /* 0x0000000506057212 */
/* 0x000fe200078efcff */
/*0980*/ BRA 0xa60 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09a0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*09b0*/ BRA 0xa60 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe200078e0205 */
/*09d0*/ BRA 0xa60 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fc800078e4805 */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a10*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078e4805 */
/*0a20*/ BRA 0xa60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a30*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0a40*/ BRA 0xa60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a50*/ FADD.FTZ R5, R8, R0 ; /* 0x0000000008057221 */
/* 0x000fc80000010000 */
/*0a60*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*0a70*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0a80*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff57004007950 */
/* 0x000fea0003c3ffff */
/*0a90*/ BRA 0xa90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.globl _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.p2align 8
.type _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_,@function
_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x4
v_cvt_f32_i32_e32 v1, s2
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[4:5], 0x0
v_max_f32_e64 v2, s3, s3
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v3, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_f32_e32 v3, v3, v1
v_div_scale_f32 v5, null, v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v5, v7, 1.0
v_dual_max_f32 v2, v2, v1 :: v_dual_fmac_f32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v1, v1, v2
v_div_scale_f32 v10, vcc_lo, v2, v1, v2
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s2, v3, v1, v3
v_mul_f32_e32 v9, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v8, v7
v_fma_f32 v12, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v5, v11, v8
v_fmac_f32_e32 v9, v12, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v7
v_fma_f32 v4, -v4, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v11, v8
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v7, v11
v_div_fixup_f32 v2, v4, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v5, v1, v3
v_sub_f32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, 1.0, v1
s_branch .LBB0_3
.LBB0_2:
v_mov_b32_e32 v3, 1.0
.LBB0_3:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b32 s3, s[2:3], 0x0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s8, -4
s_mul_i32 s3, s3, s6
s_addc_u32 s6, s9, -1
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v2, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v2, v1, v[2:3]
v_lshrrev_b32_e32 v2, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v4, v2
v_ashrrev_i32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s6, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v3, v2 :: v_dual_add_nc_u32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
global_store_b32 v[4:5], v2, off
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
v_or_b32_e32 v0, s15, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x28
s_load_b32 s0, s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, s0, v3
global_store_b32 v0, v1, s[2:3]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, .Lfunc_end0-_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dffc9_00000000-6_update_linear_and_quadratic_terms_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_
.type _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_, @function
_Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movss %xmm0, 40(%rsp)
movss %xmm1, 36(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_, .-_Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_
.globl _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.type _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, @function
_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z68__device_stub__Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_iffPfiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, .-_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_linear_and_quadratic_terms_kernel.hip"
.globl _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_ # -- Begin function _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.p2align 4, 0x90
.type _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_,@function
_Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_: # @_Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movq %rsi, 88(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_, .Lfunc_end0-_Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_,@object # @_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.section .rodata,"a",@progbits
.globl _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.p2align 3, 0x0
_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_:
.quad _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.size _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z55__device_stub__update_linear_and_quadratic_terms_kerneliffPfiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z40update_linear_and_quadratic_terms_kerneliffPfiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<string>
__global__
void vecAddKernel(float * a, float * b, float * c, int n){//funcion ejecutada en la gpu, osea la funcion device
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n)
*(c+i) = *(a+i) + *(b+i);//c[i] = a[i] + b[i]
}
void vecAdd(float * a, float * b, float * c, int n){
int size = n * sizeof(float);//calcular el tamaño de memoria de los vectores
float * d_a, * d_b, * d_c;
cudaMalloc((void **) & d_a, size);//creacion de los vectores en la memoria del gpu. //es necesario el void **?
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);//destino, origen, tamaño,
cudaMalloc((void **) & d_b, size);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) & d_c, size);
//llamada al la funcon kernel con ciertos parametros
//<<<numero de bloques, tamaño de los bloques>>>, el numero de bloques es el techo de (tamaño de elementos / tamaño del bloque), el tamaño del bloque es el numero de threads del bloque
//el numero recibido por la funcion ceil (techo) debe ser un flotante, por eso el .0
vecAddKernel<<<ceil(n/256.0), 256>>> (d_a, d_b, d_c, n);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
//liberando memoria del device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
int main(){
int n = 1 << 20;//probar con 20
float * a, * b, * c;
a = (float *)malloc(n*sizeof(float));//los malloc fevuelven un tipo void * ahy que convertirlo a lfoat *
b = (float *)malloc(n*sizeof(float));
c = (float *)malloc(n*sizeof(float));
for(int i = 0; i < n; i++){
*(a+i) = i;
*(b+i) = i;
}
vecAdd(a, b, c, n);
/*for(int i = 0; i < n; i++){
printf("%f ", *(c+i));
}*/
printf("Finalizado\n");
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<string>
__global__
void vecAddKernel(float * a, float * b, float * c, int n){//funcion ejecutada en la gpu, osea la funcion device
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n)
*(c+i) = *(a+i) + *(b+i);//c[i] = a[i] + b[i]
}
void vecAdd(float * a, float * b, float * c, int n){
int size = n * sizeof(float);//calcular el tamaño de memoria de los vectores
float * d_a, * d_b, * d_c;
cudaMalloc((void **) & d_a, size);//creacion de los vectores en la memoria del gpu. //es necesario el void **?
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);//destino, origen, tamaño,
cudaMalloc((void **) & d_b, size);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) & d_c, size);
//llamada al la funcon kernel con ciertos parametros
//<<<numero de bloques, tamaño de los bloques>>>, el numero de bloques es el techo de (tamaño de elementos / tamaño del bloque), el tamaño del bloque es el numero de threads del bloque
//el numero recibido por la funcion ceil (techo) debe ser un flotante, por eso el .0
vecAddKernel<<<ceil(n/256.0), 256>>> (d_a, d_b, d_c, n);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
//liberando memoria del device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
int main(){
int n = 1 << 20;//probar con 20
float * a, * b, * c;
a = (float *)malloc(n*sizeof(float));//los malloc fevuelven un tipo void * ahy que convertirlo a lfoat *
b = (float *)malloc(n*sizeof(float));
c = (float *)malloc(n*sizeof(float));
for(int i = 0; i < n; i++){
*(a+i) = i;
*(b+i) = i;
}
vecAdd(a, b, c, n);
/*for(int i = 0; i < n; i++){
printf("%f ", *(c+i));
}*/
printf("Finalizado\n");
return 0;
} | .file "tmpxft_00132881_00000000-6_sumavector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i:
.LFB3082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3082:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.type _Z12vecAddKernelPfS_S_i, @function
_Z12vecAddKernelPfS_S_i:
.LFB3083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3083:
.size _Z12vecAddKernelPfS_S_i, .-_Z12vecAddKernelPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB3056:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L12:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3056:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Finalizado\n"
.text
.globl main
.type main, @function
main:
.LFB3057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movl $0, %edx
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rdx,4)
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq $1048576, %rdx
jne .L19
movl $1048576, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z6vecAddPfS_S_i
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12vecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<string>
__global__
void vecAddKernel(float * a, float * b, float * c, int n){//funcion ejecutada en la gpu, osea la funcion device
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n)
*(c+i) = *(a+i) + *(b+i);//c[i] = a[i] + b[i]
}
void vecAdd(float * a, float * b, float * c, int n){
int size = n * sizeof(float);//calcular el tamaño de memoria de los vectores
float * d_a, * d_b, * d_c;
cudaMalloc((void **) & d_a, size);//creacion de los vectores en la memoria del gpu. //es necesario el void **?
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);//destino, origen, tamaño,
cudaMalloc((void **) & d_b, size);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMalloc((void **) & d_c, size);
//llamada al la funcon kernel con ciertos parametros
//<<<numero de bloques, tamaño de los bloques>>>, el numero de bloques es el techo de (tamaño de elementos / tamaño del bloque), el tamaño del bloque es el numero de threads del bloque
//el numero recibido por la funcion ceil (techo) debe ser un flotante, por eso el .0
vecAddKernel<<<ceil(n/256.0), 256>>> (d_a, d_b, d_c, n);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
//liberando memoria del device
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
}
int main(){
int n = 1 << 20;//probar con 20
float * a, * b, * c;
a = (float *)malloc(n*sizeof(float));//los malloc fevuelven un tipo void * ahy que convertirlo a lfoat *
b = (float *)malloc(n*sizeof(float));
c = (float *)malloc(n*sizeof(float));
for(int i = 0; i < n; i++){
*(a+i) = i;
*(b+i) = i;
}
vecAdd(a, b, c, n);
/*for(int i = 0; i < n; i++){
printf("%f ", *(c+i));
}*/
printf("Finalizado\n");
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<string>
__global__
void vecAddKernel(float * a, float * b, float * c, int n){//funcion ejecutada en la gpu, osea la funcion device
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n)
*(c+i) = *(a+i) + *(b+i);//c[i] = a[i] + b[i]
}
void vecAdd(float * a, float * b, float * c, int n){
int size = n * sizeof(float);//calcular el tamaño de memoria de los vectores
float * d_a, * d_b, * d_c;
hipMalloc((void **) & d_a, size);//creacion de los vectores en la memoria del gpu. //es necesario el void **?
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);//destino, origen, tamaño,
hipMalloc((void **) & d_b, size);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMalloc((void **) & d_c, size);
//llamada al la funcon kernel con ciertos parametros
//<<<numero de bloques, tamaño de los bloques>>>, el numero de bloques es el techo de (tamaño de elementos / tamaño del bloque), el tamaño del bloque es el numero de threads del bloque
//el numero recibido por la funcion ceil (techo) debe ser un flotante, por eso el .0
vecAddKernel<<<ceil(n/256.0), 256>>> (d_a, d_b, d_c, n);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
//liberando memoria del device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
int main(){
int n = 1 << 20;//probar con 20
float * a, * b, * c;
a = (float *)malloc(n*sizeof(float));//los malloc fevuelven un tipo void * ahy que convertirlo a lfoat *
b = (float *)malloc(n*sizeof(float));
c = (float *)malloc(n*sizeof(float));
for(int i = 0; i < n; i++){
*(a+i) = i;
*(b+i) = i;
}
vecAdd(a, b, c, n);
/*for(int i = 0; i < n; i++){
printf("%f ", *(c+i));
}*/
printf("Finalizado\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<string>
__global__
void vecAddKernel(float * a, float * b, float * c, int n){//funcion ejecutada en la gpu, osea la funcion device
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n)
*(c+i) = *(a+i) + *(b+i);//c[i] = a[i] + b[i]
}
void vecAdd(float * a, float * b, float * c, int n){
int size = n * sizeof(float);//calcular el tamaño de memoria de los vectores
float * d_a, * d_b, * d_c;
hipMalloc((void **) & d_a, size);//creacion de los vectores en la memoria del gpu. //es necesario el void **?
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);//destino, origen, tamaño,
hipMalloc((void **) & d_b, size);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMalloc((void **) & d_c, size);
//llamada al la funcon kernel con ciertos parametros
//<<<numero de bloques, tamaño de los bloques>>>, el numero de bloques es el techo de (tamaño de elementos / tamaño del bloque), el tamaño del bloque es el numero de threads del bloque
//el numero recibido por la funcion ceil (techo) debe ser un flotante, por eso el .0
vecAddKernel<<<ceil(n/256.0), 256>>> (d_a, d_b, d_c, n);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
//liberando memoria del device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
int main(){
int n = 1 << 20;//probar con 20
float * a, * b, * c;
a = (float *)malloc(n*sizeof(float));//los malloc fevuelven un tipo void * ahy que convertirlo a lfoat *
b = (float *)malloc(n*sizeof(float));
c = (float *)malloc(n*sizeof(float));
for(int i = 0; i < n; i++){
*(a+i) = i;
*(b+i) = i;
}
vecAdd(a, b, c, n);
/*for(int i = 0; i < n; i++){
printf("%f ", *(c+i));
}*/
printf("Finalizado\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.p2align 8
.type _Z12vecAddKernelPfS_S_i,@function
_Z12vecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_i, .Lfunc_end0-_Z12vecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<string>
__global__
void vecAddKernel(float * a, float * b, float * c, int n){//funcion ejecutada en la gpu, osea la funcion device
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < n)
*(c+i) = *(a+i) + *(b+i);//c[i] = a[i] + b[i]
}
void vecAdd(float * a, float * b, float * c, int n){
int size = n * sizeof(float);//calcular el tamaño de memoria de los vectores
float * d_a, * d_b, * d_c;
hipMalloc((void **) & d_a, size);//creacion de los vectores en la memoria del gpu. //es necesario el void **?
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);//destino, origen, tamaño,
hipMalloc((void **) & d_b, size);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMalloc((void **) & d_c, size);
//llamada al la funcon kernel con ciertos parametros
//<<<numero de bloques, tamaño de los bloques>>>, el numero de bloques es el techo de (tamaño de elementos / tamaño del bloque), el tamaño del bloque es el numero de threads del bloque
//el numero recibido por la funcion ceil (techo) debe ser un flotante, por eso el .0
vecAddKernel<<<ceil(n/256.0), 256>>> (d_a, d_b, d_c, n);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
//liberando memoria del device
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
}
int main(){
int n = 1 << 20;//probar con 20
float * a, * b, * c;
a = (float *)malloc(n*sizeof(float));//los malloc fevuelven un tipo void * ahy que convertirlo a lfoat *
b = (float *)malloc(n*sizeof(float));
c = (float *)malloc(n*sizeof(float));
for(int i = 0; i < n; i++){
*(a+i) = i;
*(b+i) = i;
}
vecAdd(a, b, c, n);
/*for(int i = 0; i < n; i++){
printf("%f ", *(c+i));
}*/
printf("Finalizado\n");
return 0;
} | .text
.file "sumavector.hip"
.globl _Z27__device_stub__vecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_i,@function
_Z27__device_stub__vecAddKernelPfS_S_i: # @_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6vecAddPfS_S_i
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6vecAddPfS_S_i, .Lfunc_end1-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movss %xmm0, (%r14,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
movl $1048576, %ecx # imm = 0x100000
callq _Z6vecAddPfS_S_i
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_i,@object # @_Z12vecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_i:
.quad _Z27__device_stub__vecAddKernelPfS_S_i
.size _Z12vecAddKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finalizado"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.p2align 8
.type _Z12vecAddKernelPfS_S_i,@function
_Z12vecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPfS_S_i, .Lfunc_end0-_Z12vecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00132881_00000000-6_sumavector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i:
.LFB3082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3082:
.size _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
.globl _Z12vecAddKernelPfS_S_i
.type _Z12vecAddKernelPfS_S_i, @function
_Z12vecAddKernelPfS_S_i:
.LFB3083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3083:
.size _Z12vecAddKernelPfS_S_i, .-_Z12vecAddKernelPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB3056:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC4(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L12:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPfS_S_iPfS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3056:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Finalizado\n"
.text
.globl main
.type main, @function
main:
.LFB3057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movl $0, %edx
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rdx,4)
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq $1048576, %rdx
jne .L19
movl $1048576, %ecx
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z6vecAddPfS_S_i
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z12vecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1064304640
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumavector.hip"
.globl _Z27__device_stub__vecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPfS_S_i,@function
_Z27__device_stub__vecAddKernelPfS_S_i: # @_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__vecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6vecAddPfS_S_i
.LCPI1_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
cvtsi2sd %r15d, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6vecAddPfS_S_i, .Lfunc_end1-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
movss %xmm0, (%r14,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %rax, %rdx
movl $1048576, %ecx # imm = 0x100000
callq _Z6vecAddPfS_S_i
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPfS_S_i,@object # @_Z12vecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPfS_S_i:
.quad _Z27__device_stub__vecAddKernelPfS_S_i
.size _Z12vecAddKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12vecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Finalizado"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cassert>
#include <iostream>
#include <cuda_runtime.h>
class CudaTimer {
private:
cudaEvent_t _start;
cudaEvent_t _stop;
public:
CudaTimer() noexcept {
cudaEventCreate(&_start);
cudaEventCreate(&_stop);
}
~CudaTimer() noexcept {
cudaEventDestroy(_start);
cudaEventDestroy(_stop);
}
void start() noexcept {
cudaEventRecord(_start, 0);
}
void stop() noexcept {
cudaEventRecord(_stop, 0);
cudaEventSynchronize(_stop);
}
float count() noexcept {
float time = 0.0;
cudaEventElapsedTime(&time, _start, _stop);
return time;
}
};
__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int count = 0;
double *value = A + tid;
for (int i = 0; i < n; ++i) {
count += (*value) ?1 :0;
value += lda;
}
rownnz[tid] = count;
}
}
__global__ void block_scan(int n, int *array, int *buffer) {
extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)
// Initialize shm
int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
if (tid < n) {
shm[threadIdx.x] = array[tid];
} else {
shm[threadIdx.x] = 0;
}
if (tid + blockDim.x < n) {
shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
} else {
shm[threadIdx.x + blockDim.x] = 0;
}
__syncthreads();
int num_elements = blockDim.x << 1;
// Start up-sweep phase
int idx = threadIdx.x << 1, shift = 1;
while (shift < num_elements) {
if (idx + shift < num_elements) {
shm[idx + shift] += shm[idx];
}
idx += idx + 1;
shift <<= 1;
}
__syncthreads();
// Start down-sweep phase
int sum = shm[num_elements - 1];
if (threadIdx.x == 0) {
shm[num_elements - 1] = 0;
}
idx = (idx - 1) >> 1;
shift >>= 1;
while (shift > 0) {
if (idx + shift < num_elements) {
int tmp = shm[idx + shift];
shm[idx + shift] += shm[idx];
shm[idx] = tmp;
}
idx = (idx - 1) >> 1;
shift >>= 1;
__syncthreads();
}
__syncthreads();
if (tid < n) {
array[tid] = shm[threadIdx.x];
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
}
if (threadIdx.x == 0) {
buffer[blockIdx.x] = sum;
}
}
__global__ void block_add(int n, int *array, int *buf) {
int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;
int val = buf[blockIdx.x];
if (tid < n) {
array[tid] += val;
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] += val;
}
}
void exclusive_scan(int n, int *array) {
int bs = 1024;
int gs = (n - 1) / (bs << 1) + 1;
int *buffer;
cudaError_t cudaErr = cudaMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
assert(cudaErr == cudaSuccess);
#ifndef NDEBUG
CudaTimer scanTimer;
scanTimer.start();
#endif
block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
scanTimer.stop();
std::cout << scanTimer.count() << ",";
#endif
if (gs > 1) {
#ifndef NDEBUG
CudaTimer addTimer;
addTimer.start();
#endif
block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
addTimer.stop();
std::cout << addTimer.count() << ",";
#endif
}
cudaFree(buffer);
}
__global__ void fill_csr_values(
int m, int n,
double *A, int lda,
int *rowptr, int *colidx, double *values) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int idx = rowptr[tid];
double *ptr = A + tid;
for (int i = 0; i < n; ++i) {
if (*ptr) {
colidx[idx] = i;
values[idx] = *ptr;
++idx;
}
ptr += lda;
}
}
}
void full_to_csr(
int m, int n,
double *A, int lda,
int **rowptr, int **colidx, double **values) {
cudaError_t cudaErr;
cudaErr = cudaMalloc(rowptr, (m + 1) * sizeof(int));
assert(cudaErr == cudaSuccess);
#ifndef NDEBUG
CudaTimer cntNnzTimer;
cntNnzTimer.start();
#endif
// Launch kernel to get number of nnz
int bs = 1024, gs = (m - 1) / bs + 1;
count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
cntNnzTimer.stop();
std::cout << cntNnzTimer.count() << ",";
#endif
exclusive_scan(m + 1, *rowptr);
int nnz = 0;
cudaErr = cudaMemcpy(&nnz, *rowptr + m, sizeof(int), cudaMemcpyDeviceToHost);
assert(cudaErr == cudaSuccess);
cudaErr = cudaMalloc(colidx, nnz * sizeof(int));
assert(cudaErr == cudaSuccess);
cudaErr = cudaMalloc(values, nnz * sizeof(double));
assert(cudaErr == cudaSuccess);
#ifndef NDEBUG
CudaTimer fillValTimer;
fillValTimer.start();
#endif
fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
fillValTimer.stop();
std::cout << fillValTimer.count() << std::endl;
#endif
} | .file "tmpxft_000b7e31_00000000-6_ex4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3682:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3682:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
.type _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi, @function
_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi:
.LFB3704:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13count_row_nnziiPdiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi, .-_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
.globl _Z13count_row_nnziiPdiPi
.type _Z13count_row_nnziiPdiPi, @function
_Z13count_row_nnziiPdiPi:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z13count_row_nnziiPdiPi, .-_Z13count_row_nnziiPdiPi
.globl _Z33__device_stub__Z10block_scaniPiS_iPiS_
.type _Z33__device_stub__Z10block_scaniPiS_iPiS_, @function
_Z33__device_stub__Z10block_scaniPiS_iPiS_:
.LFB3706:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10block_scaniPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3706:
.size _Z33__device_stub__Z10block_scaniPiS_iPiS_, .-_Z33__device_stub__Z10block_scaniPiS_iPiS_
.globl _Z10block_scaniPiS_
.type _Z10block_scaniPiS_, @function
_Z10block_scaniPiS_:
.LFB3707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10block_scaniPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _Z10block_scaniPiS_, .-_Z10block_scaniPiS_
.globl _Z31__device_stub__Z9block_addiPiS_iPiS_
.type _Z31__device_stub__Z9block_addiPiS_iPiS_, @function
_Z31__device_stub__Z9block_addiPiS_iPiS_:
.LFB3708:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9block_addiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z31__device_stub__Z9block_addiPiS_iPiS_, .-_Z31__device_stub__Z9block_addiPiS_iPiS_
.globl _Z9block_addiPiS_
.type _Z9block_addiPiS_, @function
_Z9block_addiPiS_:
.LFB3709:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9block_addiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _Z9block_addiPiS_, .-_Z9block_addiPiS_
.globl _Z14exclusive_scaniPi
.type _Z14exclusive_scaniPi, @function
_Z14exclusive_scaniPi:
.LFB3678:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 2046(%rdi), %ebp
movl %edi, %eax
subl $1, %eax
cmovns %eax, %ebp
sarl $11, %ebp
leal 1(%rbp), %r13d
movslq %r13d, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r13d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
cmpl $1, %r13d
jg .L34
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 8(%rsp), %rdx
movq %r12, %rsi
movl %ebx, %edi
call _Z33__device_stub__Z10block_scaniPiS_iPiS_
jmp .L28
.L34:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
leaq 8192(%r12), %rsi
leal -2048(%rbx), %edi
movq 8(%rsp), %rdx
call _Z31__device_stub__Z9block_addiPiS_iPiS_
jmp .L29
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3678:
.size _Z14exclusive_scaniPi, .-_Z14exclusive_scaniPi
.globl _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
.type _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_, @function
_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_:
.LFB3710:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15fill_csr_valuesiiPdiPiS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3710:
.size _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_, .-_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
.globl _Z15fill_csr_valuesiiPdiPiS0_S_
.type _Z15fill_csr_valuesiiPdiPiS0_S_, @function
_Z15fill_csr_valuesiiPdiPiS0_S_:
.LFB3711:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _Z15fill_csr_valuesiiPdiPiS0_S_, .-_Z15fill_csr_valuesiiPdiPiS0_S_
.globl _Z11full_to_csriiPdiPPiS1_PS_
.type _Z11full_to_csriiPdiPPiS1_PS_, @function
_Z11full_to_csriiPdiPPiS1_PS_:
.LFB3679:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 28(%rsp)
movq %r8, %r12
movq %r9, 8(%rsp)
movq 144(%rsp), %r15
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 1(%rdi), %r14d
movslq %r14d, %r13
salq $2, %r13
movq %r13, %rsi
movq %r8, %rdi
call cudaMalloc@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leal 1022(%rbp), %ebx
movl %ebp, %eax
subl $1, %eax
cmovns %eax, %ebx
sarl $10, %ebx
addl $1, %ebx
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq (%r12), %rsi
movl %r14d, %edi
call _Z14exclusive_scaniPi
movl $0, 44(%rsp)
movq (%r12), %rax
leaq -4(%rax,%r13), %rsi
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movslq 44(%rsp), %rsi
salq $2, %rsi
movq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
salq $3, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L44:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq (%r12), %r8
movl 28(%rsp), %ecx
movq 16(%rsp), %rdx
movl 24(%rsp), %esi
movl %ebp, %edi
call _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
jmp .L45
.L50:
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq (%r15)
.cfi_def_cfa_offset 160
movq 24(%rsp), %rax
movq (%rax), %r9
movq (%r12), %r8
movl 44(%rsp), %ecx
movq 32(%rsp), %rdx
movl 40(%rsp), %esi
movl %ebp, %edi
call _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L44
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3679:
.size _Z11full_to_csriiPdiPPiS1_PS_, .-_Z11full_to_csriiPdiPPiS1_PS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15fill_csr_valuesiiPdiPiS0_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9block_addiPiS_"
.LC2:
.string "_Z10block_scaniPiS_"
.LC3:
.string "_Z13count_row_nnziiPdiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3713:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15fill_csr_valuesiiPdiPiS0_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9block_addiPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10block_scaniPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13count_row_nnziiPdiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cassert>
#include <iostream>
#include <cuda_runtime.h>
class CudaTimer {
private:
cudaEvent_t _start;
cudaEvent_t _stop;
public:
CudaTimer() noexcept {
cudaEventCreate(&_start);
cudaEventCreate(&_stop);
}
~CudaTimer() noexcept {
cudaEventDestroy(_start);
cudaEventDestroy(_stop);
}
void start() noexcept {
cudaEventRecord(_start, 0);
}
void stop() noexcept {
cudaEventRecord(_stop, 0);
cudaEventSynchronize(_stop);
}
float count() noexcept {
float time = 0.0;
cudaEventElapsedTime(&time, _start, _stop);
return time;
}
};
__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int count = 0;
double *value = A + tid;
for (int i = 0; i < n; ++i) {
count += (*value) ?1 :0;
value += lda;
}
rownnz[tid] = count;
}
}
__global__ void block_scan(int n, int *array, int *buffer) {
extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)
// Initialize shm
int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
if (tid < n) {
shm[threadIdx.x] = array[tid];
} else {
shm[threadIdx.x] = 0;
}
if (tid + blockDim.x < n) {
shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
} else {
shm[threadIdx.x + blockDim.x] = 0;
}
__syncthreads();
int num_elements = blockDim.x << 1;
// Start up-sweep phase
int idx = threadIdx.x << 1, shift = 1;
while (shift < num_elements) {
if (idx + shift < num_elements) {
shm[idx + shift] += shm[idx];
}
idx += idx + 1;
shift <<= 1;
}
__syncthreads();
// Start down-sweep phase
int sum = shm[num_elements - 1];
if (threadIdx.x == 0) {
shm[num_elements - 1] = 0;
}
idx = (idx - 1) >> 1;
shift >>= 1;
while (shift > 0) {
if (idx + shift < num_elements) {
int tmp = shm[idx + shift];
shm[idx + shift] += shm[idx];
shm[idx] = tmp;
}
idx = (idx - 1) >> 1;
shift >>= 1;
__syncthreads();
}
__syncthreads();
if (tid < n) {
array[tid] = shm[threadIdx.x];
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
}
if (threadIdx.x == 0) {
buffer[blockIdx.x] = sum;
}
}
__global__ void block_add(int n, int *array, int *buf) {
int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;
int val = buf[blockIdx.x];
if (tid < n) {
array[tid] += val;
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] += val;
}
}
void exclusive_scan(int n, int *array) {
int bs = 1024;
int gs = (n - 1) / (bs << 1) + 1;
int *buffer;
cudaError_t cudaErr = cudaMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
assert(cudaErr == cudaSuccess);
#ifndef NDEBUG
CudaTimer scanTimer;
scanTimer.start();
#endif
block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
scanTimer.stop();
std::cout << scanTimer.count() << ",";
#endif
if (gs > 1) {
#ifndef NDEBUG
CudaTimer addTimer;
addTimer.start();
#endif
block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
addTimer.stop();
std::cout << addTimer.count() << ",";
#endif
}
cudaFree(buffer);
}
__global__ void fill_csr_values(
int m, int n,
double *A, int lda,
int *rowptr, int *colidx, double *values) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int idx = rowptr[tid];
double *ptr = A + tid;
for (int i = 0; i < n; ++i) {
if (*ptr) {
colidx[idx] = i;
values[idx] = *ptr;
++idx;
}
ptr += lda;
}
}
}
void full_to_csr(
int m, int n,
double *A, int lda,
int **rowptr, int **colidx, double **values) {
cudaError_t cudaErr;
cudaErr = cudaMalloc(rowptr, (m + 1) * sizeof(int));
assert(cudaErr == cudaSuccess);
#ifndef NDEBUG
CudaTimer cntNnzTimer;
cntNnzTimer.start();
#endif
// Launch kernel to get number of nnz
int bs = 1024, gs = (m - 1) / bs + 1;
count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
cntNnzTimer.stop();
std::cout << cntNnzTimer.count() << ",";
#endif
exclusive_scan(m + 1, *rowptr);
int nnz = 0;
cudaErr = cudaMemcpy(&nnz, *rowptr + m, sizeof(int), cudaMemcpyDeviceToHost);
assert(cudaErr == cudaSuccess);
cudaErr = cudaMalloc(colidx, nnz * sizeof(int));
assert(cudaErr == cudaSuccess);
cudaErr = cudaMalloc(values, nnz * sizeof(double));
assert(cudaErr == cudaSuccess);
#ifndef NDEBUG
CudaTimer fillValTimer;
fillValTimer.start();
#endif
fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
assert(cudaGetLastError() == cudaSuccess);
#ifndef NDEBUG
fillValTimer.stop();
std::cout << fillValTimer.count() << std::endl;
#endif
} | #include <cassert>
#include <iostream>
#include <hip/hip_runtime.h>
class CudaTimer {
private:
hipEvent_t _start;
hipEvent_t _stop;
public:
CudaTimer() noexcept {
hipEventCreate(&_start);
hipEventCreate(&_stop);
}
~CudaTimer() noexcept {
hipEventDestroy(_start);
hipEventDestroy(_stop);
}
void start() noexcept {
hipEventRecord(_start, 0);
}
void stop() noexcept {
hipEventRecord(_stop, 0);
hipEventSynchronize(_stop);
}
float count() noexcept {
float time = 0.0;
hipEventElapsedTime(&time, _start, _stop);
return time;
}
};
__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int count = 0;
double *value = A + tid;
for (int i = 0; i < n; ++i) {
count += (*value) ?1 :0;
value += lda;
}
rownnz[tid] = count;
}
}
__global__ void block_scan(int n, int *array, int *buffer) {
extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)
// Initialize shm
int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
if (tid < n) {
shm[threadIdx.x] = array[tid];
} else {
shm[threadIdx.x] = 0;
}
if (tid + blockDim.x < n) {
shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
} else {
shm[threadIdx.x + blockDim.x] = 0;
}
__syncthreads();
int num_elements = blockDim.x << 1;
// Start up-sweep phase
int idx = threadIdx.x << 1, shift = 1;
while (shift < num_elements) {
if (idx + shift < num_elements) {
shm[idx + shift] += shm[idx];
}
idx += idx + 1;
shift <<= 1;
}
__syncthreads();
// Start down-sweep phase
int sum = shm[num_elements - 1];
if (threadIdx.x == 0) {
shm[num_elements - 1] = 0;
}
idx = (idx - 1) >> 1;
shift >>= 1;
while (shift > 0) {
if (idx + shift < num_elements) {
int tmp = shm[idx + shift];
shm[idx + shift] += shm[idx];
shm[idx] = tmp;
}
idx = (idx - 1) >> 1;
shift >>= 1;
__syncthreads();
}
__syncthreads();
if (tid < n) {
array[tid] = shm[threadIdx.x];
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
}
if (threadIdx.x == 0) {
buffer[blockIdx.x] = sum;
}
}
__global__ void block_add(int n, int *array, int *buf) {
int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;
int val = buf[blockIdx.x];
if (tid < n) {
array[tid] += val;
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] += val;
}
}
void exclusive_scan(int n, int *array) {
int bs = 1024;
int gs = (n - 1) / (bs << 1) + 1;
int *buffer;
hipError_t cudaErr = hipMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer scanTimer;
scanTimer.start();
#endif
block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
scanTimer.stop();
std::cout << scanTimer.count() << ",";
#endif
if (gs > 1) {
#ifndef NDEBUG
CudaTimer addTimer;
addTimer.start();
#endif
block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
addTimer.stop();
std::cout << addTimer.count() << ",";
#endif
}
hipFree(buffer);
}
__global__ void fill_csr_values(
int m, int n,
double *A, int lda,
int *rowptr, int *colidx, double *values) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int idx = rowptr[tid];
double *ptr = A + tid;
for (int i = 0; i < n; ++i) {
if (*ptr) {
colidx[idx] = i;
values[idx] = *ptr;
++idx;
}
ptr += lda;
}
}
}
void full_to_csr(
int m, int n,
double *A, int lda,
int **rowptr, int **colidx, double **values) {
hipError_t cudaErr;
cudaErr = hipMalloc(rowptr, (m + 1) * sizeof(int));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer cntNnzTimer;
cntNnzTimer.start();
#endif
// Launch kernel to get number of nnz
int bs = 1024, gs = (m - 1) / bs + 1;
count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
cntNnzTimer.stop();
std::cout << cntNnzTimer.count() << ",";
#endif
exclusive_scan(m + 1, *rowptr);
int nnz = 0;
cudaErr = hipMemcpy(&nnz, *rowptr + m, sizeof(int), hipMemcpyDeviceToHost);
assert(cudaErr == hipSuccess);
cudaErr = hipMalloc(colidx, nnz * sizeof(int));
assert(cudaErr == hipSuccess);
cudaErr = hipMalloc(values, nnz * sizeof(double));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer fillValTimer;
fillValTimer.start();
#endif
fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
fillValTimer.stop();
std::cout << fillValTimer.count() << std::endl;
#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cassert>
#include <iostream>
#include <hip/hip_runtime.h>
class CudaTimer {
private:
hipEvent_t _start;
hipEvent_t _stop;
public:
CudaTimer() noexcept {
hipEventCreate(&_start);
hipEventCreate(&_stop);
}
~CudaTimer() noexcept {
hipEventDestroy(_start);
hipEventDestroy(_stop);
}
void start() noexcept {
hipEventRecord(_start, 0);
}
void stop() noexcept {
hipEventRecord(_stop, 0);
hipEventSynchronize(_stop);
}
float count() noexcept {
float time = 0.0;
hipEventElapsedTime(&time, _start, _stop);
return time;
}
};
__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int count = 0;
double *value = A + tid;
for (int i = 0; i < n; ++i) {
count += (*value) ?1 :0;
value += lda;
}
rownnz[tid] = count;
}
}
__global__ void block_scan(int n, int *array, int *buffer) {
extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)
// Initialize shm
int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
if (tid < n) {
shm[threadIdx.x] = array[tid];
} else {
shm[threadIdx.x] = 0;
}
if (tid + blockDim.x < n) {
shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
} else {
shm[threadIdx.x + blockDim.x] = 0;
}
__syncthreads();
int num_elements = blockDim.x << 1;
// Start up-sweep phase
int idx = threadIdx.x << 1, shift = 1;
while (shift < num_elements) {
if (idx + shift < num_elements) {
shm[idx + shift] += shm[idx];
}
idx += idx + 1;
shift <<= 1;
}
__syncthreads();
// Start down-sweep phase
int sum = shm[num_elements - 1];
if (threadIdx.x == 0) {
shm[num_elements - 1] = 0;
}
idx = (idx - 1) >> 1;
shift >>= 1;
while (shift > 0) {
if (idx + shift < num_elements) {
int tmp = shm[idx + shift];
shm[idx + shift] += shm[idx];
shm[idx] = tmp;
}
idx = (idx - 1) >> 1;
shift >>= 1;
__syncthreads();
}
__syncthreads();
if (tid < n) {
array[tid] = shm[threadIdx.x];
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
}
if (threadIdx.x == 0) {
buffer[blockIdx.x] = sum;
}
}
__global__ void block_add(int n, int *array, int *buf) {
int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;
int val = buf[blockIdx.x];
if (tid < n) {
array[tid] += val;
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] += val;
}
}
void exclusive_scan(int n, int *array) {
int bs = 1024;
int gs = (n - 1) / (bs << 1) + 1;
int *buffer;
hipError_t cudaErr = hipMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer scanTimer;
scanTimer.start();
#endif
block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
scanTimer.stop();
std::cout << scanTimer.count() << ",";
#endif
if (gs > 1) {
#ifndef NDEBUG
CudaTimer addTimer;
addTimer.start();
#endif
block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
addTimer.stop();
std::cout << addTimer.count() << ",";
#endif
}
hipFree(buffer);
}
__global__ void fill_csr_values(
int m, int n,
double *A, int lda,
int *rowptr, int *colidx, double *values) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int idx = rowptr[tid];
double *ptr = A + tid;
for (int i = 0; i < n; ++i) {
if (*ptr) {
colidx[idx] = i;
values[idx] = *ptr;
++idx;
}
ptr += lda;
}
}
}
void full_to_csr(
int m, int n,
double *A, int lda,
int **rowptr, int **colidx, double **values) {
hipError_t cudaErr;
cudaErr = hipMalloc(rowptr, (m + 1) * sizeof(int));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer cntNnzTimer;
cntNnzTimer.start();
#endif
// Launch kernel to get number of nnz
int bs = 1024, gs = (m - 1) / bs + 1;
count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
cntNnzTimer.stop();
std::cout << cntNnzTimer.count() << ",";
#endif
exclusive_scan(m + 1, *rowptr);
int nnz = 0;
cudaErr = hipMemcpy(&nnz, *rowptr + m, sizeof(int), hipMemcpyDeviceToHost);
assert(cudaErr == hipSuccess);
cudaErr = hipMalloc(colidx, nnz * sizeof(int));
assert(cudaErr == hipSuccess);
cudaErr = hipMalloc(values, nnz * sizeof(double));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer fillValTimer;
fillValTimer.start();
#endif
fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
fillValTimer.stop();
std::cout << fillValTimer.count() << std::endl;
#endif
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13count_row_nnziiPdiPi
.globl _Z13count_row_nnziiPdiPi
.p2align 8
.type _Z13count_row_nnziiPdiPi,@function
_Z13count_row_nnziiPdiPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[0:1], 0x4
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[6:7], 3
.LBB0_3:
global_load_b64 v[5:6], v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, s2
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_cmp_neq_f64_e32 vcc_lo, 0, v[5:6]
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13count_row_nnziiPdiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13count_row_nnziiPdiPi, .Lfunc_end0-_Z13count_row_nnziiPdiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10block_scaniPiS_
.globl _Z10block_scaniPiS_
.p2align 8
.type _Z10block_scaniPiS_,@function
_Z10block_scaniPiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x8
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, 0
s_mov_b32 s6, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s4
v_lshl_add_u32 v1, s2, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s2, s8, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
global_load_b32 v2, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v3, s4, v1
v_lshl_add_u32 v4, v0, 2, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v3
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s3, s8, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s3, s9, v5, s3
global_load_b32 v5, v[4:5], off
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v4, s4, v0
v_lshlrev_b32_e32 v2, 1, v0
s_lshl_b32 s5, s4, 1
s_mov_b32 s7, 1
s_cmp_eq_u32 s4, 0
v_lshl_add_u32 v6, v4, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_16
.LBB1_5:
s_lshl_b32 s3, s5, 2
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, 0
s_barrier
s_add_i32 s4, s4, -4
buffer_gl0_inv
v_mov_b32_e32 v5, s4
v_cmp_eq_u32_e64 s3, 0, v0
ds_load_b32 v5, v5
s_and_saveexec_b32 s10, s3
s_cbranch_execz .LBB1_7
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, s4
ds_store_b32 v7, v6
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s10
s_cmp_lt_u32 s7, 2
s_cbranch_scc0 .LBB1_19
.LBB1_8:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_10
v_lshl_add_u32 v0, v0, 2, 0
v_ashrrev_i32_e32 v2, 31, v1
ds_load_b32 v6, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v6, off
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_12
v_lshl_add_u32 v0, v4, 2, 0
v_mov_b32_e32 v4, 0
ds_load_b32 v2, v0
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_14
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s7, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[6:7], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v5, s[0:1]
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_or_b32 v2, v2, 1, 1
s_lshl_b32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s7, s5
s_cbranch_scc0 .LBB1_5
.LBB1_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s7, v2
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s5, v5
s_cbranch_execz .LBB1_15
v_lshl_add_u32 v6, v2, 2, 0
v_lshl_add_u32 v5, v5, 2, 0
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
ds_store_b32 v5, v6
s_branch .LBB1_15
.p2align 6
.LBB1_18:
s_or_b32 exec_lo, exec_lo, s11
s_cmp_gt_u32 s7, 3
s_mov_b32 s7, s10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_8
.LBB1_19:
v_add_nc_u32_e32 v2, -1, v2
s_lshr_b32 s10, s7, 1
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 1, v2
v_add_nc_u32_e32 v6, s10, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v6
s_cbranch_execz .LBB1_18
v_lshl_add_u32 v6, v6, 2, 0
v_lshl_add_u32 v7, v2, 2, 0
ds_load_b32 v8, v6
ds_load_b32 v9, v7
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v9, v9, v8
ds_store_b32 v6, v9
ds_store_b32 v7, v8
s_branch .LBB1_18
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10block_scaniPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10block_scaniPiS_, .Lfunc_end1-_Z10block_scaniPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9block_addiPiS_
.globl _Z9block_addiPiS_
.p2align 8
.type _Z9block_addiPiS_,@function
_Z9block_addiPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_mov_b32 s8, s15
s_mov_b32 s9, 0
s_load_b32 s1, s[0:1], 0x0
s_lshl_b64 s[10:11], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_add_u32 s6, s6, s10
s_addc_u32 s7, s7, s11
s_mul_i32 s3, s15, s2
s_load_b32 s0, s[6:7], 0x0
v_lshl_add_u32 v0, s3, 1, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s1, v0
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, s0, v3
global_store_b32 v[1:2], v3, off
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s1, v0
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB2_4
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_addiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9block_addiPiS_, .Lfunc_end2-_Z9block_addiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15fill_csr_valuesiiPdiPiS0_S_
.globl _Z15fill_csr_valuesiiPdiPiS0_S_
.p2align 8
.type _Z15fill_csr_valuesiiPdiPiS0_S_,@function
_Z15fill_csr_valuesiiPdiPiS0_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_gt_i32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_mov_b32 s2, 0
s_and_b32 s4, vcc_lo, s4
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x10
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s4
v_add_co_u32 v2, vcc_lo, v2, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, s2
s_cbranch_scc0 .LBB3_5
.LBB3_3:
global_load_b64 v[4:5], v[2:3], off
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_neq_f64_e32 0, v[4:5]
s_cbranch_execz .LBB3_2
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v10, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_lshlrev_b64 v[8:9], 3, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[6:7], v10, off
global_store_b64 v[8:9], v[4:5], off
s_branch .LBB3_2
.LBB3_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15fill_csr_valuesiiPdiPiS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z15fill_csr_valuesiiPdiPiS0_S_, .Lfunc_end3-_Z15fill_csr_valuesiiPdiPiS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
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.size: 4
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.value_kind: global_buffer
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.size: 4
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- .offset: 36
.size: 4
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.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
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- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
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.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13count_row_nnziiPdiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13count_row_nnziiPdiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
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.vgpr_spill_count: 0
.wavefront_size: 32
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.language: OpenCL C
.language_version:
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- 0
.max_flat_workgroup_size: 1024
.name: _Z10block_scaniPiS_
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.uniform_work_group_size: 1
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.vgpr_spill_count: 0
.wavefront_size: 32
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- 0
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.name: _Z9block_addiPiS_
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.sgpr_spill_count: 0
.symbol: _Z9block_addiPiS_.kd
.uniform_work_group_size: 1
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.workgroup_processor_mode: 1
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.size: 8
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.size: 2
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.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15fill_csr_valuesiiPdiPiS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15fill_csr_valuesiiPdiPiS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cassert>
#include <iostream>
#include <hip/hip_runtime.h>
class CudaTimer {
private:
hipEvent_t _start;
hipEvent_t _stop;
public:
CudaTimer() noexcept {
hipEventCreate(&_start);
hipEventCreate(&_stop);
}
~CudaTimer() noexcept {
hipEventDestroy(_start);
hipEventDestroy(_stop);
}
void start() noexcept {
hipEventRecord(_start, 0);
}
void stop() noexcept {
hipEventRecord(_stop, 0);
hipEventSynchronize(_stop);
}
float count() noexcept {
float time = 0.0;
hipEventElapsedTime(&time, _start, _stop);
return time;
}
};
__global__ void count_row_nnz(int m, int n, double *A, int lda, int *rownnz) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int count = 0;
double *value = A + tid;
for (int i = 0; i < n; ++i) {
count += (*value) ?1 :0;
value += lda;
}
rownnz[tid] = count;
}
}
__global__ void block_scan(int n, int *array, int *buffer) {
extern __shared__ int shm[]; // size of shm: 2 * blockDim.x * sizeof(int)
// Initialize shm
int tid = threadIdx.x + (blockIdx.x << 1) * blockDim.x;
if (tid < n) {
shm[threadIdx.x] = array[tid];
} else {
shm[threadIdx.x] = 0;
}
if (tid + blockDim.x < n) {
shm[threadIdx.x + blockDim.x] = array[tid + blockDim.x];
} else {
shm[threadIdx.x + blockDim.x] = 0;
}
__syncthreads();
int num_elements = blockDim.x << 1;
// Start up-sweep phase
int idx = threadIdx.x << 1, shift = 1;
while (shift < num_elements) {
if (idx + shift < num_elements) {
shm[idx + shift] += shm[idx];
}
idx += idx + 1;
shift <<= 1;
}
__syncthreads();
// Start down-sweep phase
int sum = shm[num_elements - 1];
if (threadIdx.x == 0) {
shm[num_elements - 1] = 0;
}
idx = (idx - 1) >> 1;
shift >>= 1;
while (shift > 0) {
if (idx + shift < num_elements) {
int tmp = shm[idx + shift];
shm[idx + shift] += shm[idx];
shm[idx] = tmp;
}
idx = (idx - 1) >> 1;
shift >>= 1;
__syncthreads();
}
__syncthreads();
if (tid < n) {
array[tid] = shm[threadIdx.x];
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] = shm[threadIdx.x + blockDim.x];
}
if (threadIdx.x == 0) {
buffer[blockIdx.x] = sum;
}
}
__global__ void block_add(int n, int *array, int *buf) {
int tid = blockIdx.x * (blockDim.x << 1) + threadIdx.x;
int val = buf[blockIdx.x];
if (tid < n) {
array[tid] += val;
}
if (tid + blockDim.x < n) {
array[tid + blockDim.x] += val;
}
}
void exclusive_scan(int n, int *array) {
int bs = 1024;
int gs = (n - 1) / (bs << 1) + 1;
int *buffer;
hipError_t cudaErr = hipMalloc(reinterpret_cast<void **>(&buffer), gs * sizeof(int));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer scanTimer;
scanTimer.start();
#endif
block_scan<<<gs , bs, 2 * bs * sizeof(int)>>>(n, array, buffer);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
scanTimer.stop();
std::cout << scanTimer.count() << ",";
#endif
if (gs > 1) {
#ifndef NDEBUG
CudaTimer addTimer;
addTimer.start();
#endif
block_add<<<gs - 1, bs>>>(n - (bs << 1), array + (bs << 1), buffer);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
addTimer.stop();
std::cout << addTimer.count() << ",";
#endif
}
hipFree(buffer);
}
__global__ void fill_csr_values(
int m, int n,
double *A, int lda,
int *rowptr, int *colidx, double *values) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if (tid < m) {
int idx = rowptr[tid];
double *ptr = A + tid;
for (int i = 0; i < n; ++i) {
if (*ptr) {
colidx[idx] = i;
values[idx] = *ptr;
++idx;
}
ptr += lda;
}
}
}
void full_to_csr(
int m, int n,
double *A, int lda,
int **rowptr, int **colidx, double **values) {
hipError_t cudaErr;
cudaErr = hipMalloc(rowptr, (m + 1) * sizeof(int));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer cntNnzTimer;
cntNnzTimer.start();
#endif
// Launch kernel to get number of nnz
int bs = 1024, gs = (m - 1) / bs + 1;
count_row_nnz<<<gs, bs>>>(m, n, A, lda, *rowptr);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
cntNnzTimer.stop();
std::cout << cntNnzTimer.count() << ",";
#endif
exclusive_scan(m + 1, *rowptr);
int nnz = 0;
cudaErr = hipMemcpy(&nnz, *rowptr + m, sizeof(int), hipMemcpyDeviceToHost);
assert(cudaErr == hipSuccess);
cudaErr = hipMalloc(colidx, nnz * sizeof(int));
assert(cudaErr == hipSuccess);
cudaErr = hipMalloc(values, nnz * sizeof(double));
assert(cudaErr == hipSuccess);
#ifndef NDEBUG
CudaTimer fillValTimer;
fillValTimer.start();
#endif
fill_csr_values<<<gs, bs>>>(m, n, A, lda, *rowptr, *colidx, *values);
assert(hipGetLastError() == hipSuccess);
#ifndef NDEBUG
fillValTimer.stop();
std::cout << fillValTimer.count() << std::endl;
#endif
} | .text
.file "ex4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__count_row_nnziiPdiPi # -- Begin function _Z28__device_stub__count_row_nnziiPdiPi
.p2align 4, 0x90
.type _Z28__device_stub__count_row_nnziiPdiPi,@function
_Z28__device_stub__count_row_nnziiPdiPi: # @_Z28__device_stub__count_row_nnziiPdiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13count_row_nnziiPdiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__count_row_nnziiPdiPi, .Lfunc_end0-_Z28__device_stub__count_row_nnziiPdiPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__block_scaniPiS_ # -- Begin function _Z25__device_stub__block_scaniPiS_
.p2align 4, 0x90
.type _Z25__device_stub__block_scaniPiS_,@function
_Z25__device_stub__block_scaniPiS_: # @_Z25__device_stub__block_scaniPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10block_scaniPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__block_scaniPiS_, .Lfunc_end1-_Z25__device_stub__block_scaniPiS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__block_addiPiS_ # -- Begin function _Z24__device_stub__block_addiPiS_
.p2align 4, 0x90
.type _Z24__device_stub__block_addiPiS_,@function
_Z24__device_stub__block_addiPiS_: # @_Z24__device_stub__block_addiPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_addiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__block_addiPiS_, .Lfunc_end2-_Z24__device_stub__block_addiPiS_
.cfi_endproc
# -- End function
.globl _Z14exclusive_scaniPi # -- Begin function _Z14exclusive_scaniPi
.p2align 4, 0x90
.type _Z14exclusive_scaniPi,@function
_Z14exclusive_scaniPi: # @_Z14exclusive_scaniPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
movabsq $4294967296, %r15 # imm = 0x100000000
leal -1(%r14), %eax
leal 2046(%r14), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $11, %r13d
leal 1(%r13), %r12d
movslq %r13d, %rax
leaq 4(,%rax,4), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
orq %r15, %r12
leaq 1024(%r15), %rdx
movl $8192, %r8d # imm = 0x2000
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_1
# %bb.2:
cmpl $2049, %r14d # imm = 0x801
jge .LBB3_3
jmp .LBB3_5
.LBB3_1:
movq 8(%rsp), %rax
movl %r14d, 4(%rsp)
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10block_scaniPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $2049, %r14d # imm = 0x801
jl .LBB3_5
.LBB3_3:
movl %r13d, %edi
orq %r15, %rdi
addq $1024, %r15 # imm = 0x400
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
addl $-2048, %r14d # imm = 0xF800
addq $8192, %rbx # imm = 0x2000
movq 8(%rsp), %rax
movl %r14d, 4(%rsp)
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_addiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movq 8(%rsp), %rdi
callq hipFree
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14exclusive_scaniPi, .Lfunc_end3-_Z14exclusive_scaniPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_ # -- Begin function _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.p2align 4, 0x90
.type _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_,@function
_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_: # @_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15fill_csr_valuesiiPdiPiS0_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_, .Lfunc_end4-_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.cfi_endproc
# -- End function
.globl _Z11full_to_csriiPdiPPiS1_PS_ # -- Begin function _Z11full_to_csriiPdiPPiS1_PS_
.p2align 4, 0x90
.type _Z11full_to_csriiPdiPPiS1_PS_,@function
_Z11full_to_csriiPdiPPiS1_PS_: # @_Z11full_to_csriiPdiPPiS1_PS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 176(%rsp) # 8-byte Spill
movq %r8, %r12
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rdx, 104(%rsp) # 8-byte Spill
movl %esi, 8(%rsp) # 4-byte Spill
movl %edi, %r13d
movabsq $4294968320, %r15 # imm = 0x100000400
leal 1(%r13), %ebx
movslq %edi, %rbp
leaq 4(,%rbp,4), %rsi
movq %r8, %rdi
callq hipMalloc
leal -1(%rbp), %eax
leal 1022(%rbp), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $10, %ecx
incl %ecx
leaq (%rcx,%r15), %r14
addq $-1024, %r14 # imm = 0xFC00
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq (%r12), %rax
movl %r13d, 24(%rsp)
movl 8(%rsp), %ecx # 4-byte Reload
movl %ecx, 16(%rsp)
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movl 12(%rsp), %ecx # 4-byte Reload
movl %ecx, 4(%rsp)
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13count_row_nnziiPdiPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq (%r12), %rsi
movl %ebx, %edi
callq _Z14exclusive_scaniPi
movl $0, (%rsp)
shlq $2, %rbp
addq (%r12), %rbp
movq %rsp, %rdi
movl $4, %edx
movq %rbp, %rsi
movl $2, %ecx
callq hipMemcpy
movslq (%rsp), %rsi
shlq $2, %rsi
movq 176(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
callq hipMalloc
movslq (%rsp), %rsi
shlq $3, %rsi
movq 240(%rsp), %rbx
movq %rbx, %rdi
callq hipMalloc
movq %r14, %rdi
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq (%r12), %rax
movq (%r15), %rcx
movq (%rbx), %rdx
movl %r13d, 4(%rsp)
movl 8(%rsp), %esi # 4-byte Reload
movl %esi, 100(%rsp)
movq 104(%rsp), %rsi # 8-byte Reload
movq %rsi, 88(%rsp)
movl 12(%rsp), %esi # 4-byte Reload
movl %esi, 96(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 100(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15fill_csr_valuesiiPdiPiS0_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11full_to_csriiPdiPPiS1_PS_, .Lfunc_end5-_Z11full_to_csriiPdiPPiS1_PS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13count_row_nnziiPdiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10block_scaniPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9block_addiPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15fill_csr_valuesiiPdiPiS0_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13count_row_nnziiPdiPi,@object # @_Z13count_row_nnziiPdiPi
.section .rodata,"a",@progbits
.globl _Z13count_row_nnziiPdiPi
.p2align 3, 0x0
_Z13count_row_nnziiPdiPi:
.quad _Z28__device_stub__count_row_nnziiPdiPi
.size _Z13count_row_nnziiPdiPi, 8
.type _Z10block_scaniPiS_,@object # @_Z10block_scaniPiS_
.globl _Z10block_scaniPiS_
.p2align 3, 0x0
_Z10block_scaniPiS_:
.quad _Z25__device_stub__block_scaniPiS_
.size _Z10block_scaniPiS_, 8
.type _Z9block_addiPiS_,@object # @_Z9block_addiPiS_
.globl _Z9block_addiPiS_
.p2align 3, 0x0
_Z9block_addiPiS_:
.quad _Z24__device_stub__block_addiPiS_
.size _Z9block_addiPiS_, 8
.type _Z15fill_csr_valuesiiPdiPiS0_S_,@object # @_Z15fill_csr_valuesiiPdiPiS0_S_
.globl _Z15fill_csr_valuesiiPdiPiS0_S_
.p2align 3, 0x0
_Z15fill_csr_valuesiiPdiPiS0_S_:
.quad _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.size _Z15fill_csr_valuesiiPdiPiS0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13count_row_nnziiPdiPi"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10block_scaniPiS_"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9block_addiPiS_"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15fill_csr_valuesiiPdiPiS0_S_"
.size .L__unnamed_4, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__count_row_nnziiPdiPi
.addrsig_sym _Z25__device_stub__block_scaniPiS_
.addrsig_sym _Z24__device_stub__block_addiPiS_
.addrsig_sym _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13count_row_nnziiPdiPi
.addrsig_sym _Z10block_scaniPiS_
.addrsig_sym _Z9block_addiPiS_
.addrsig_sym _Z15fill_csr_valuesiiPdiPiS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b7e31_00000000-6_ex4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3682:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3682:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
.type _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi, @function
_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi:
.LFB3704:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13count_row_nnziiPdiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3704:
.size _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi, .-_Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
.globl _Z13count_row_nnziiPdiPi
.type _Z13count_row_nnziiPdiPi, @function
_Z13count_row_nnziiPdiPi:
.LFB3705:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _Z13count_row_nnziiPdiPi, .-_Z13count_row_nnziiPdiPi
.globl _Z33__device_stub__Z10block_scaniPiS_iPiS_
.type _Z33__device_stub__Z10block_scaniPiS_iPiS_, @function
_Z33__device_stub__Z10block_scaniPiS_iPiS_:
.LFB3706:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10block_scaniPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3706:
.size _Z33__device_stub__Z10block_scaniPiS_iPiS_, .-_Z33__device_stub__Z10block_scaniPiS_iPiS_
.globl _Z10block_scaniPiS_
.type _Z10block_scaniPiS_, @function
_Z10block_scaniPiS_:
.LFB3707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10block_scaniPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _Z10block_scaniPiS_, .-_Z10block_scaniPiS_
.globl _Z31__device_stub__Z9block_addiPiS_iPiS_
.type _Z31__device_stub__Z9block_addiPiS_iPiS_, @function
_Z31__device_stub__Z9block_addiPiS_iPiS_:
.LFB3708:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9block_addiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z31__device_stub__Z9block_addiPiS_iPiS_, .-_Z31__device_stub__Z9block_addiPiS_iPiS_
.globl _Z9block_addiPiS_
.type _Z9block_addiPiS_, @function
_Z9block_addiPiS_:
.LFB3709:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9block_addiPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _Z9block_addiPiS_, .-_Z9block_addiPiS_
.globl _Z14exclusive_scaniPi
.type _Z14exclusive_scaniPi, @function
_Z14exclusive_scaniPi:
.LFB3678:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 2046(%rdi), %ebp
movl %edi, %eax
subl $1, %eax
cmovns %eax, %ebp
sarl $11, %ebp
leal 1(%rbp), %r13d
movslq %r13d, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r13d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
cmpl $1, %r13d
jg .L34
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 8(%rsp), %rdx
movq %r12, %rsi
movl %ebx, %edi
call _Z33__device_stub__Z10block_scaniPiS_iPiS_
jmp .L28
.L34:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
leaq 8192(%r12), %rsi
leal -2048(%rbx), %edi
movq 8(%rsp), %rdx
call _Z31__device_stub__Z9block_addiPiS_iPiS_
jmp .L29
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3678:
.size _Z14exclusive_scaniPi, .-_Z14exclusive_scaniPi
.globl _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
.type _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_, @function
_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_:
.LFB3710:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15fill_csr_valuesiiPdiPiS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3710:
.size _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_, .-_Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
.globl _Z15fill_csr_valuesiiPdiPiS0_S_
.type _Z15fill_csr_valuesiiPdiPiS0_S_, @function
_Z15fill_csr_valuesiiPdiPiS0_S_:
.LFB3711:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _Z15fill_csr_valuesiiPdiPiS0_S_, .-_Z15fill_csr_valuesiiPdiPiS0_S_
.globl _Z11full_to_csriiPdiPPiS1_PS_
.type _Z11full_to_csriiPdiPPiS1_PS_, @function
_Z11full_to_csriiPdiPPiS1_PS_:
.LFB3679:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %ebp
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 28(%rsp)
movq %r8, %r12
movq %r9, 8(%rsp)
movq 144(%rsp), %r15
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 1(%rdi), %r14d
movslq %r14d, %r13
salq $2, %r13
movq %r13, %rsi
movq %r8, %rdi
call cudaMalloc@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leal 1022(%rbp), %ebx
movl %ebp, %eax
subl $1, %eax
cmovns %eax, %ebx
sarl $10, %ebx
addl $1, %ebx
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq (%r12), %rsi
movl %r14d, %edi
call _Z14exclusive_scaniPi
movl $0, 44(%rsp)
movq (%r12), %rax
leaq -4(%rax,%r13), %rsi
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movslq 44(%rsp), %rsi
salq $2, %rsi
movq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 44(%rsp), %rsi
salq $3, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L44:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq (%r12), %r8
movl 28(%rsp), %ecx
movq 16(%rsp), %rdx
movl 24(%rsp), %esi
movl %ebp, %edi
call _Z38__device_stub__Z13count_row_nnziiPdiPiiiPdiPi
jmp .L45
.L50:
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq (%r15)
.cfi_def_cfa_offset 160
movq 24(%rsp), %rax
movq (%rax), %r9
movq (%r12), %r8
movl 44(%rsp), %ecx
movq 32(%rsp), %rdx
movl 40(%rsp), %esi
movl %ebp, %edi
call _Z45__device_stub__Z15fill_csr_valuesiiPdiPiS0_S_iiPdiPiS0_S_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L44
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3679:
.size _Z11full_to_csriiPdiPPiS1_PS_, .-_Z11full_to_csriiPdiPPiS1_PS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15fill_csr_valuesiiPdiPiS0_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9block_addiPiS_"
.LC2:
.string "_Z10block_scaniPiS_"
.LC3:
.string "_Z13count_row_nnziiPdiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3713:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15fill_csr_valuesiiPdiPiS0_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9block_addiPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10block_scaniPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13count_row_nnziiPdiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3713:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__count_row_nnziiPdiPi # -- Begin function _Z28__device_stub__count_row_nnziiPdiPi
.p2align 4, 0x90
.type _Z28__device_stub__count_row_nnziiPdiPi,@function
_Z28__device_stub__count_row_nnziiPdiPi: # @_Z28__device_stub__count_row_nnziiPdiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13count_row_nnziiPdiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__count_row_nnziiPdiPi, .Lfunc_end0-_Z28__device_stub__count_row_nnziiPdiPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__block_scaniPiS_ # -- Begin function _Z25__device_stub__block_scaniPiS_
.p2align 4, 0x90
.type _Z25__device_stub__block_scaniPiS_,@function
_Z25__device_stub__block_scaniPiS_: # @_Z25__device_stub__block_scaniPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10block_scaniPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__block_scaniPiS_, .Lfunc_end1-_Z25__device_stub__block_scaniPiS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__block_addiPiS_ # -- Begin function _Z24__device_stub__block_addiPiS_
.p2align 4, 0x90
.type _Z24__device_stub__block_addiPiS_,@function
_Z24__device_stub__block_addiPiS_: # @_Z24__device_stub__block_addiPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_addiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z24__device_stub__block_addiPiS_, .Lfunc_end2-_Z24__device_stub__block_addiPiS_
.cfi_endproc
# -- End function
.globl _Z14exclusive_scaniPi # -- Begin function _Z14exclusive_scaniPi
.p2align 4, 0x90
.type _Z14exclusive_scaniPi,@function
_Z14exclusive_scaniPi: # @_Z14exclusive_scaniPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
movabsq $4294967296, %r15 # imm = 0x100000000
leal -1(%r14), %eax
leal 2046(%r14), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $11, %r13d
leal 1(%r13), %r12d
movslq %r13d, %rax
leaq 4(,%rax,4), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
orq %r15, %r12
leaq 1024(%r15), %rdx
movl $8192, %r8d # imm = 0x2000
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_1
# %bb.2:
cmpl $2049, %r14d # imm = 0x801
jge .LBB3_3
jmp .LBB3_5
.LBB3_1:
movq 8(%rsp), %rax
movl %r14d, 4(%rsp)
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10block_scaniPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $2049, %r14d # imm = 0x801
jl .LBB3_5
.LBB3_3:
movl %r13d, %edi
orq %r15, %rdi
addq $1024, %r15 # imm = 0x400
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
addl $-2048, %r14d # imm = 0xF800
addq $8192, %rbx # imm = 0x2000
movq 8(%rsp), %rax
movl %r14d, 4(%rsp)
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_addiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movq 8(%rsp), %rdi
callq hipFree
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14exclusive_scaniPi, .Lfunc_end3-_Z14exclusive_scaniPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_ # -- Begin function _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.p2align 4, 0x90
.type _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_,@function
_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_: # @_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movq %rdx, 88(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15fill_csr_valuesiiPdiPiS0_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_, .Lfunc_end4-_Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.cfi_endproc
# -- End function
.globl _Z11full_to_csriiPdiPPiS1_PS_ # -- Begin function _Z11full_to_csriiPdiPPiS1_PS_
.p2align 4, 0x90
.type _Z11full_to_csriiPdiPPiS1_PS_,@function
_Z11full_to_csriiPdiPPiS1_PS_: # @_Z11full_to_csriiPdiPPiS1_PS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 176(%rsp) # 8-byte Spill
movq %r8, %r12
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rdx, 104(%rsp) # 8-byte Spill
movl %esi, 8(%rsp) # 4-byte Spill
movl %edi, %r13d
movabsq $4294968320, %r15 # imm = 0x100000400
leal 1(%r13), %ebx
movslq %edi, %rbp
leaq 4(,%rbp,4), %rsi
movq %r8, %rdi
callq hipMalloc
leal -1(%rbp), %eax
leal 1022(%rbp), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $10, %ecx
incl %ecx
leaq (%rcx,%r15), %r14
addq $-1024, %r14 # imm = 0xFC00
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq (%r12), %rax
movl %r13d, 24(%rsp)
movl 8(%rsp), %ecx # 4-byte Reload
movl %ecx, 16(%rsp)
movq 104(%rsp), %rcx # 8-byte Reload
movq %rcx, 88(%rsp)
movl 12(%rsp), %ecx # 4-byte Reload
movl %ecx, 4(%rsp)
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13count_row_nnziiPdiPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq (%r12), %rsi
movl %ebx, %edi
callq _Z14exclusive_scaniPi
movl $0, (%rsp)
shlq $2, %rbp
addq (%r12), %rbp
movq %rsp, %rdi
movl $4, %edx
movq %rbp, %rsi
movl $2, %ecx
callq hipMemcpy
movslq (%rsp), %rsi
shlq $2, %rsi
movq 176(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
callq hipMalloc
movslq (%rsp), %rsi
shlq $3, %rsi
movq 240(%rsp), %rbx
movq %rbx, %rdi
callq hipMalloc
movq %r14, %rdi
movl $1, %esi
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq (%r12), %rax
movq (%r15), %rcx
movq (%rbx), %rdx
movl %r13d, 4(%rsp)
movl 8(%rsp), %esi # 4-byte Reload
movl %esi, 100(%rsp)
movq 104(%rsp), %rsi # 8-byte Reload
movq %rsi, 88(%rsp)
movl 12(%rsp), %esi # 4-byte Reload
movl %esi, 96(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 100(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15fill_csr_valuesiiPdiPiS0_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z11full_to_csriiPdiPPiS1_PS_, .Lfunc_end5-_Z11full_to_csriiPdiPPiS1_PS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13count_row_nnziiPdiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10block_scaniPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9block_addiPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15fill_csr_valuesiiPdiPiS0_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13count_row_nnziiPdiPi,@object # @_Z13count_row_nnziiPdiPi
.section .rodata,"a",@progbits
.globl _Z13count_row_nnziiPdiPi
.p2align 3, 0x0
_Z13count_row_nnziiPdiPi:
.quad _Z28__device_stub__count_row_nnziiPdiPi
.size _Z13count_row_nnziiPdiPi, 8
.type _Z10block_scaniPiS_,@object # @_Z10block_scaniPiS_
.globl _Z10block_scaniPiS_
.p2align 3, 0x0
_Z10block_scaniPiS_:
.quad _Z25__device_stub__block_scaniPiS_
.size _Z10block_scaniPiS_, 8
.type _Z9block_addiPiS_,@object # @_Z9block_addiPiS_
.globl _Z9block_addiPiS_
.p2align 3, 0x0
_Z9block_addiPiS_:
.quad _Z24__device_stub__block_addiPiS_
.size _Z9block_addiPiS_, 8
.type _Z15fill_csr_valuesiiPdiPiS0_S_,@object # @_Z15fill_csr_valuesiiPdiPiS0_S_
.globl _Z15fill_csr_valuesiiPdiPiS0_S_
.p2align 3, 0x0
_Z15fill_csr_valuesiiPdiPiS0_S_:
.quad _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.size _Z15fill_csr_valuesiiPdiPiS0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13count_row_nnziiPdiPi"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10block_scaniPiS_"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9block_addiPiS_"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15fill_csr_valuesiiPdiPiS0_S_"
.size .L__unnamed_4, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__count_row_nnziiPdiPi
.addrsig_sym _Z25__device_stub__block_scaniPiS_
.addrsig_sym _Z24__device_stub__block_addiPiS_
.addrsig_sym _Z30__device_stub__fill_csr_valuesiiPdiPiS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13count_row_nnziiPdiPi
.addrsig_sym _Z10block_scaniPiS_
.addrsig_sym _Z9block_addiPiS_
.addrsig_sym _Z15fill_csr_valuesiiPdiPiS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void unique_index_kernel(const char* flag, const int* flag_inc_sum, int* unique_index, int num_elems) {
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_elems; gid += blockDim.x * gridDim.x) {
if (flag[gid] == 1) {
int id = flag_inc_sum[gid] - 1;
unique_index[id] = gid;
}
}
} | code for sm_80
Function : _Z19unique_index_kernelPKcPKiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0080*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ BSSY B0, 0x170 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 BRA 0x160 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*00f0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0100*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1405 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x004fca0007ffe0ff */
/*0140*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0150*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e4000c101904 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x001fca00078e0200 */
/*0180*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0190*/ @!P0 BRA 0x70 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void unique_index_kernel(const char* flag, const int* flag_inc_sum, int* unique_index, int num_elems) {
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_elems; gid += blockDim.x * gridDim.x) {
if (flag[gid] == 1) {
int id = flag_inc_sum[gid] - 1;
unique_index[id] = gid;
}
}
} | .file "tmpxft_0012975a_00000000-6_unique_index_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii
.type _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii, @function
_Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19unique_index_kernelPKcPKiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii, .-_Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii
.globl _Z19unique_index_kernelPKcPKiPii
.type _Z19unique_index_kernelPKcPKiPii, @function
_Z19unique_index_kernelPKcPKiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19unique_index_kernelPKcPKiPii, .-_Z19unique_index_kernelPKcPKiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19unique_index_kernelPKcPKiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19unique_index_kernelPKcPKiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void unique_index_kernel(const char* flag, const int* flag_inc_sum, int* unique_index, int num_elems) {
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_elems; gid += blockDim.x * gridDim.x) {
if (flag[gid] == 1) {
int id = flag_inc_sum[gid] - 1;
unique_index[id] = gid;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void unique_index_kernel(const char* flag, const int* flag_inc_sum, int* unique_index, int num_elems) {
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_elems; gid += blockDim.x * gridDim.x) {
if (flag[gid] == 1) {
int id = flag_inc_sum[gid] - 1;
unique_index[id] = gid;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void unique_index_kernel(const char* flag, const int* flag_inc_sum, int* unique_index, int num_elems) {
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_elems; gid += blockDim.x * gridDim.x) {
if (flag[gid] == 1) {
int id = flag_inc_sum[gid] - 1;
unique_index[id] = gid;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19unique_index_kernelPKcPKiPii
.globl _Z19unique_index_kernelPKcPKiPii
.p2align 8
.type _Z19unique_index_kernelPKcPKiPii,@function
_Z19unique_index_kernelPKcPKiPii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s5, s8, -4
s_mul_i32 s6, s7, s6
s_addc_u32 s7, s9, -1
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s0, v1
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 1, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19unique_index_kernelPKcPKiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19unique_index_kernelPKcPKiPii, .Lfunc_end0-_Z19unique_index_kernelPKcPKiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19unique_index_kernelPKcPKiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19unique_index_kernelPKcPKiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void unique_index_kernel(const char* flag, const int* flag_inc_sum, int* unique_index, int num_elems) {
int gid_base = blockIdx.x * blockDim.x + threadIdx.x;
for (int gid = gid_base; gid < num_elems; gid += blockDim.x * gridDim.x) {
if (flag[gid] == 1) {
int id = flag_inc_sum[gid] - 1;
unique_index[id] = gid;
}
}
} | .text
.file "unique_index_kernel.hip"
.globl _Z34__device_stub__unique_index_kernelPKcPKiPii # -- Begin function _Z34__device_stub__unique_index_kernelPKcPKiPii
.p2align 4, 0x90
.type _Z34__device_stub__unique_index_kernelPKcPKiPii,@function
_Z34__device_stub__unique_index_kernelPKcPKiPii: # @_Z34__device_stub__unique_index_kernelPKcPKiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19unique_index_kernelPKcPKiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__unique_index_kernelPKcPKiPii, .Lfunc_end0-_Z34__device_stub__unique_index_kernelPKcPKiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19unique_index_kernelPKcPKiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19unique_index_kernelPKcPKiPii,@object # @_Z19unique_index_kernelPKcPKiPii
.section .rodata,"a",@progbits
.globl _Z19unique_index_kernelPKcPKiPii
.p2align 3, 0x0
_Z19unique_index_kernelPKcPKiPii:
.quad _Z34__device_stub__unique_index_kernelPKcPKiPii
.size _Z19unique_index_kernelPKcPKiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19unique_index_kernelPKcPKiPii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__unique_index_kernelPKcPKiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19unique_index_kernelPKcPKiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19unique_index_kernelPKcPKiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0080*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ BSSY B0, 0x170 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 BRA 0x160 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*00f0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0100*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1405 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R2, R4, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x004fca0007ffe0ff */
/*0140*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0150*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e4000c101904 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x001fca00078e0200 */
/*0180*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0190*/ @!P0 BRA 0x70 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19unique_index_kernelPKcPKiPii
.globl _Z19unique_index_kernelPKcPKiPii
.p2align 8
.type _Z19unique_index_kernelPKcPKiPii,@function
_Z19unique_index_kernelPKcPKiPii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s7, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s5, s8, -4
s_mul_i32 s6, s7, s6
s_addc_u32 s7, s9, -1
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v3, vcc_lo, s0, v1
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e32 1, v0
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19unique_index_kernelPKcPKiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19unique_index_kernelPKcPKiPii, .Lfunc_end0-_Z19unique_index_kernelPKcPKiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19unique_index_kernelPKcPKiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19unique_index_kernelPKcPKiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012975a_00000000-6_unique_index_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii
.type _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii, @function
_Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19unique_index_kernelPKcPKiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii, .-_Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii
.globl _Z19unique_index_kernelPKcPKiPii
.type _Z19unique_index_kernelPKcPKiPii, @function
_Z19unique_index_kernelPKcPKiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19unique_index_kernelPKcPKiPiiPKcPKiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19unique_index_kernelPKcPKiPii, .-_Z19unique_index_kernelPKcPKiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19unique_index_kernelPKcPKiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19unique_index_kernelPKcPKiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unique_index_kernel.hip"
.globl _Z34__device_stub__unique_index_kernelPKcPKiPii # -- Begin function _Z34__device_stub__unique_index_kernelPKcPKiPii
.p2align 4, 0x90
.type _Z34__device_stub__unique_index_kernelPKcPKiPii,@function
_Z34__device_stub__unique_index_kernelPKcPKiPii: # @_Z34__device_stub__unique_index_kernelPKcPKiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19unique_index_kernelPKcPKiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__unique_index_kernelPKcPKiPii, .Lfunc_end0-_Z34__device_stub__unique_index_kernelPKcPKiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19unique_index_kernelPKcPKiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19unique_index_kernelPKcPKiPii,@object # @_Z19unique_index_kernelPKcPKiPii
.section .rodata,"a",@progbits
.globl _Z19unique_index_kernelPKcPKiPii
.p2align 3, 0x0
_Z19unique_index_kernelPKcPKiPii:
.quad _Z34__device_stub__unique_index_kernelPKcPKiPii
.size _Z19unique_index_kernelPKcPKiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19unique_index_kernelPKcPKiPii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__unique_index_kernelPKcPKiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19unique_index_kernelPKcPKiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_fp16.h>
#include <stdio.h>
#include <stdint.h>
#include <zlib.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <fcntl.h>
#include <limits.h>
typedef struct __ReadSeqList {
char* sequence;
unsigned int length;
struct __ReadSeqList* next;
} ReadSeqList;
typedef struct HashTable {
unsigned int bits;
unsigned int count;
unsigned int read_count;
unsigned long long int *keys;
unsigned int *values;
} HashTable;
__device__ const unsigned char seq_nt4_table[256] = { // translate ACGT to 0123
0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
// funcion para calcular un hash de 64 bits
__device__ unsigned int hash_uint64(unsigned long long int key) {
key = ~key + (key << 21);
key = key ^ key >> 24;
key = (key + (key << 3)) + (key << 8);
key = key ^ key >> 14;
key = (key + (key << 2)) + (key << 4);
key = key ^ key >> 28;
key = key + (key << 31);
return (unsigned int)key;
}
HashTable* HashTable_init(unsigned int bits, unsigned int read_count){
HashTable *ht;
ht = (HashTable*)calloc(1, sizeof(HashTable));
ht->read_count = read_count;
ht->bits = bits;
ht->count = 0;
return ht;
}
void HashTable_destory(HashTable *ht) {
if (!ht) return;
free(ht);
}
__device__ unsigned int h2b(unsigned int hash, unsigned int bits) {
return hash * 2654435769U >> (32 - bits);
}
__device__ void hash_insert(HashTable *ht, unsigned long long int kmer) {
unsigned int iKey, last;
bool end = false;
iKey = last = h2b(hash_uint64(kmer), ht->bits);
while (true)
{
unsigned long long int prev = atomicCAS(&(ht->keys[iKey]), 0ULL, kmer);
if (prev == 0ULL || prev == kmer) {
atomicAdd(&(ht->values[iKey]), 1U);
return;
}
if(end) return;
// Collition: Open addressing
iKey = (iKey + 1U) & ((1U << ht->bits) - 1);
// loop back
end = (iKey == last);
}
}
// insert k-mers in $seq to hash table $ht
__global__ void kernel_count_seq_kmers(HashTable *ht, int k, char **d_reads)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < ht->read_count) {
int i, l;
char *seq = d_reads[tid];
int len = 100;
unsigned long long int x[2], mask = (1ULL<<k*2) - 1, shift = (k - 1) * 2;
for (i = l = 0, x[0] = x[1] = 0; i < len; ++i) {
int c = seq_nt4_table[(unsigned char)seq[i]];
if (c < 4) { // not an "N" base
x[0] = (x[0] << 2 | c) & mask; // forward strand
x[1] = x[1] >> 2 | (unsigned long long int)(3 - c) << shift; // reverse strand
if (++l >= k) { // we find a k-mer
unsigned long long int kmer = x[0] < x[1]? x[0] : x[1];
hash_insert(ht, kmer); // only add one strand!
}
} else l = 0, x[0] = x[1] = 0; // if there is an "N", restart
}
}
}
__global__ void kernel_print_hist(const HashTable *ht, unsigned int *cnt_d)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int pos;
if(tid < (1U << ht->bits)) {
if (ht->values[tid] > 0) {
pos = ht->values[tid] < 256U ? ht->values[tid] : 255;
atomicAdd(&(cnt_d[pos]), 1U);
}
}
}
static int count_file(const char *fn, int k, unsigned int p)
{
HashTable *ht;
unsigned int capacity = 1U << p;
unsigned int cnt[256];
unsigned int read_count = 0;
// variables para cuda
HashTable *ht_d;
char **reads_d;
unsigned int *cnt_d;
FILE * fp;
char * line = NULL;
size_t len = 0;
ssize_t read;
fp = fopen(fn, "r");
if (fp == NULL) exit(EXIT_FAILURE);
ReadSeqList *current, *head;
head = current = NULL;
while ((read = getline(&line, &len, fp)) != -1) {
read_count++;
ReadSeqList *node = (ReadSeqList*)malloc(sizeof(ReadSeqList));
node->sequence = (char*)malloc(strlen(line));
strcpy(node->sequence, line);
node->length = read;
node->next =NULL;
if(head == NULL){
current = head = node;
} else {
current = current->next = node;
}
}
fclose(fp);
if (line) free(line);
printf("%d\n", read_count);
unsigned int i;
char **reads = (char**)malloc(read_count * sizeof(char*));
for(i=0, current = head; current; current=current->next){
reads[i] = (char*)malloc(current->length);
sprintf(reads[i], "%s", current->sequence);
i++;
}
// inicializar hashtable
ht = HashTable_init(p, read_count);
unsigned long long int *keys_d;
unsigned int *values_d;
// allocate memory in device
cudaMalloc((void **)&ht_d, sizeof(HashTable));
cudaMalloc((void **)&keys_d, capacity * sizeof(unsigned long long int));
cudaMalloc((void **)&values_d, capacity * sizeof(unsigned int));
cudaMalloc((void **)&cnt_d, 256 * sizeof(unsigned int));
cudaMemset(keys_d, 0ULL, capacity * sizeof(unsigned long long int));
cudaMemset(values_d, 0, capacity * sizeof(unsigned int));
cudaMemset(cnt_d, 0, 256 * sizeof(unsigned int));
// copy data to device
ht->keys = keys_d;
ht->values = values_d;
cudaMemcpy(ht_d, ht, sizeof(HashTable), cudaMemcpyHostToDevice);
char **tmp = (char**)malloc (read_count * sizeof (char*));
for (int i = 0; i < read_count; i++) {
cudaMalloc ((void **)&tmp[i], head->length * sizeof (char));
}
cudaMalloc((void **)&reads_d, read_count * sizeof(char*));
cudaMemcpy(reads_d, tmp, read_count * sizeof (char*), cudaMemcpyHostToDevice);
for (int i = 0; i < read_count; i++) {
cudaMemcpy(tmp[i], reads[i], head->length * sizeof (char), cudaMemcpyHostToDevice);
}
free(tmp);
printf("total reads: %d\n", read_count);
// invocar kernels
unsigned int thr = 1024;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
kernel_count_seq_kmers<<<ceil(read_count/thr), thr>>>(ht_d, k, reads_d);
cudaDeviceSynchronize();
kernel_print_hist<<<ceil(capacity/thr), thr>>>(ht_d, cnt_d);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
float seconds = milliseconds / 1000.0f;
printf("GPU time: %fs\n", seconds);
cudaMemcpy(ht, ht_d, sizeof(HashTable), cudaMemcpyDeviceToHost);
cudaMemcpy(ht->keys, keys_d, capacity * sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
cudaMemcpy(ht->values, values_d, capacity * sizeof(unsigned int), cudaMemcpyDeviceToHost);
cudaMemcpy(cnt, cnt_d, 256 * sizeof(unsigned int), cudaMemcpyDeviceToHost);
printf("COUNT: %d\n\n", ht->count);
for (i = 1; i < 256; ++i)
printf("%d\t%d\n", i, cnt[i]);
// limpieza
cudaFree(reads_d);
cudaFree(ht_d);
cudaFree(cnt_d);
cudaFree(keys_d);
cudaFree(values_d);
// limpieza
i = 0;
for(current = head; current; current=current->next){
free(current->sequence);
free(current);
free(reads[i]);
i++;
}
free(reads);
HashTable_destory(ht);
return 0;
}
int main(int argc, char *argv[])
{
int k = 31;
unsigned int p = 27;
k = (int)strtol(argv[1], NULL, 10);
p = (unsigned int)strtol(argv[2], NULL, 10);
count_file(argv[3], k, p);
return 0;
} | code for sm_80
Function : _Z17kernel_print_histPK9HashTablePj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0070*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0204 */
/*0090*/ SHF.L.U32 R0, R7, R0, RZ ; /* 0x0000000007007219 */
/* 0x004fc800000006ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E.64 R2, [R2.64+0x18] ; /* 0x0000180402027981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD.WIDE.U32 R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x004fcc00078e0002 */
/*00e0*/ LD.E R4, [R4.64] ; /* 0x0000000404047980 */
/* 0x000ea4000c101900 */
/*00f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ ISETP.LT.U32.AND P0, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x000fc80003f01070 */
/*0120*/ ISETP.LT.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fc80003f01100 */
/*0130*/ SEL R4, R4, 0xff, P0 ; /* 0x000000ff04047807 */
/* 0x000fc80000000000 */
/*0140*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x000fc800078010ff */
/*0150*/ LEA.HI.X R3, R4, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f14ff */
/*0160*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e184 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z22kernel_count_seq_kmersP9HashTableiPPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000080602037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fc6000ff1e03f */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0090*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*00a0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fc8000f8e00ff */
/*00b0*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fe4000f8e00ff */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06070 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0003 */
/*0110*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000f62000c1e1b00 */
/*0120*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0130*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0140*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0150*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*0160*/ UMOV UR5, 0xffffffff ; /* 0xffffffff00057882 */
/* 0x000fe20000000000 */
/*0170*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0180*/ USHF.L.U64.HI UR8, UR5, UR4, 0xffffffff ; /* 0xffffffff05087499 */
/* 0x000fe40008010204 */
/*0190*/ USHF.L.U32 UR5, UR5, UR4, URZ ; /* 0x0000000405057299 */
/* 0x000fe4000800063f */
/*01a0*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fc4000fffe03f */
/*01b0*/ IADD3 R4, P0, R2, R19, RZ ; /* 0x0000001302047210 */
/* 0x021fc80007f1e0ff */
/*01c0*/ LEA.HI.X.SX32 R5, R19, R3, 0x1, P0 ; /* 0x0000000313057211 */
/* 0x000fca00000f0eff */
/*01d0*/ LD.E.U8 R4, [R4.64] ; /* 0x0000000604047980 */
/* 0x000ea4000c101100 */
/*01e0*/ IADD3 R6, P0, R4, c[0x4][0x0], RZ ; /* 0x0100000004067a10 */
/* 0x004fca0007f1e0ff */
/*01f0*/ IMAD.X R7, RZ, RZ, c[0x4][0x4], P0 ; /* 0x01000100ff077624 */
/* 0x000fcc00000e06ff */
/*0200*/ LDG.E.U8.CONSTANT R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e9100 */
/*0210*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0220*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B0, 0x900 ; /* 0x000006c000007945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0012 */
/*0250*/ ISETP.GE.U32.AND P2, PT, R19, 0x64, PT ; /* 0x000000641300780c */
/* 0x000fe20003f46070 */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*0270*/ IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0011 */
/*0280*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000f */
/*0290*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fc400078e000e */
/*02b0*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*02c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x004fda0003f04070 */
/*02e0*/ @P0 BRA 0x8f0 ; /* 0x0000060000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R0, P0, -R7, 0x3, RZ ; /* 0x0000000307007810 */
/* 0x000fe20007f1e1ff */
/*0300*/ IMAD.SHL.U32 R16, R11, 0x4, RZ ; /* 0x000000040b107824 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R18, R10, 0x1, RZ ; /* 0x000000010a127810 */
/* 0x000fe40007ffe0ff */
/*0320*/ SHF.R.U64 R15, R13, 0x2, R4.reuse ; /* 0x000000020d0f7819 */
/* 0x100fe20000001204 */
/*0330*/ IMAD.X R5, RZ, RZ, -0x1, P0 ; /* 0xffffffffff057424 */
/* 0x000fe200000e06ff */
/*0340*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x168], PT ; /* 0x00005a0012007a0c */
/* 0x000fe40003f06270 */
/*0350*/ SHF.R.U32.HI R14, RZ, 0x2, R4 ; /* 0x00000002ff0e7819 */
/* 0x000fe40000011604 */
/*0360*/ SHF.L.U64.HI R5, R0, UR4, R5 ; /* 0x0000000400057c19 */
/* 0x000fc40008010205 */
/*0370*/ SHF.L.U32 R0, R0, UR4, RZ ; /* 0x0000000400007c19 */
/* 0x000fe400080006ff */
/*0380*/ SHF.L.U64.HI R17, R11, 0x2, R12 ; /* 0x000000020b117819 */
/* 0x000fe4000001020c */
/*0390*/ LOP3.LUT R16, R16, UR5, R7, 0x32, !PT ; /* 0x0000000510107c12 */
/* 0x000fe4000f8e3207 */
/*03a0*/ LOP3.LUT R15, R0, R15, RZ, 0xfc, !PT ; /* 0x0000000f000f7212 */
/* 0x000fe400078efcff */
/*03b0*/ LOP3.LUT R14, R5, R14, RZ, 0xfc, !PT ; /* 0x0000000e050e7212 */
/* 0x000fe400078efcff */
/*03c0*/ LOP3.LUT R17, R17, UR8, RZ, 0x30, !PT ; /* 0x0000000811117c12 */
/* 0x000fe2000f8e30ff */
/*03d0*/ @!P0 BRA 0x8f0 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R0, [R8.64+-0x8] ; /* 0xfffff80608007981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000806080a7981 */
/* 0x000ee2000c1e1b00 */
/*0400*/ ISETP.LT.U32.AND P0, PT, R16, R15, PT ; /* 0x0000000f1000720c */
/* 0x000fc80003f01070 */
/*0410*/ ISETP.LT.U32.AND.EX P0, PT, R17, R14, PT, P0 ; /* 0x0000000e1100720c */
/* 0x000fc80003f01100 */
/*0420*/ SEL R6, R16, R15, P0 ; /* 0x0000000f10067207 */
/* 0x000fe40000000000 */
/*0430*/ SEL R7, R17, R14, P0 ; /* 0x0000000e11077207 */
/* 0x000fe40000000000 */
/*0440*/ LOP3.LUT R13, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff0d7212 */
/* 0x000fe400078e33ff */
/*0450*/ LOP3.LUT R12, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0c7212 */
/* 0x000fe400078e33ff */
/*0460*/ LEA R13, P0, R6, R13, 0x15 ; /* 0x0000000d060d7211 */
/* 0x000fc8000780a8ff */
/*0470*/ LEA.HI.X R12, R6, R12, R7, 0x15, P0 ; /* 0x0000000c060c7211 */
/* 0x000fc800000fac07 */
/*0480*/ SHF.R.U32.HI R5, RZ, 0x18, R12.reuse ; /* 0x00000018ff057819 */
/* 0x100fe4000001160c */
/*0490*/ SHF.R.U64 R4, R13, 0x18, R12 ; /* 0x000000180d047819 */
/* 0x000fe4000000120c */
/*04a0*/ LOP3.LUT R5, R5, R12, RZ, 0x3c, !PT ; /* 0x0000000c05057212 */
/* 0x000fe400078e3cff */
/*04b0*/ LOP3.LUT R4, R4, R13, RZ, 0x3c, !PT ; /* 0x0000000d04047212 */
/* 0x000fc600078e3cff */
/*04c0*/ IMAD R13, R5, 0x109, RZ ; /* 0x00000109050d7824 */
/* 0x000fe400078e02ff */
/*04d0*/ IMAD.WIDE.U32 R4, R4, 0x109, RZ ; /* 0x0000010904047825 */
/* 0x000fc800078e00ff */
/*04e0*/ IMAD.IADD R12, R5, 0x1, R13 ; /* 0x00000001050c7824 */
/* 0x000fca00078e020d */
/*04f0*/ SHF.R.U32.HI R5, RZ, 0xe, R12.reuse ; /* 0x0000000eff057819 */
/* 0x100fe4000001160c */
/*0500*/ SHF.R.U64 R13, R4, 0xe, R12 ; /* 0x0000000e040d7819 */
/* 0x000fe4000000120c */
/*0510*/ LOP3.LUT R5, R5, R12, RZ, 0x3c, !PT ; /* 0x0000000c05057212 */
/* 0x000fe400078e3cff */
/*0520*/ LOP3.LUT R4, R13, R4, RZ, 0x3c, !PT ; /* 0x000000040d047212 */
/* 0x000fc600078e3cff */
/*0530*/ IMAD R13, R5, 0x15, RZ ; /* 0x00000015050d7824 */
/* 0x000fe400078e02ff */
/*0540*/ IMAD.WIDE.U32 R4, R4, 0x15, RZ ; /* 0x0000001504047825 */
/* 0x000fc800078e00ff */
/*0550*/ IMAD.IADD R5, R5, 0x1, R13 ; /* 0x0000000105057824 */
/* 0x000fca00078e020d */
/*0560*/ SHF.R.U64 R5, R4, 0x1c, R5 ; /* 0x0000001c04057819 */
/* 0x000fc80000001205 */
/*0570*/ LOP3.LUT R4, R5, R4, RZ, 0x3c, !PT ; /* 0x0000000405047212 */
/* 0x000fca00078e3cff */
/*0580*/ IMAD R4, R4, 0x1e3779b9, RZ ; /* 0x1e3779b904047824 */
/* 0x000fe200078e02ff */
/*0590*/ IADD3 R5, -R0, 0x20, RZ ; /* 0x0000002000057810 */
/* 0x004fc80007ffe1ff */
/*05a0*/ SHF.R.U32.HI R0, RZ, R5, R4 ; /* 0x00000005ff007219 */
/* 0x000fe40000011604 */
/*05b0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc6000001ff00 */
/*05c0*/ IMAD.WIDE.U32 R10, R0, 0x8, R10 ; /* 0x00000008000a7825 */
/* 0x008fca00078e000a */
/*05d0*/ ATOM.E.CAS.64.STRONG.GPU P0, R12, [R10], R4, R6 ; /* 0x000000040a0c738b */
/* 0x000ea2000010e506 */
/*05e0*/ BSSY B1, 0x670 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*05f0*/ @P0 BRA 0x660 ; /* 0x0000006000000947 */
/* 0x004fea0003800000 */
/*0600*/ LD.E.64 R12, [R10] ; /* 0x000000000a0c7980 */
/* 0x000ea40000100b00 */
/*0610*/ ISETP.EQ.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x004fc80003f02070 */
/*0620*/ ISETP.EQ.U32.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fc80003f02100 */
/*0630*/ SEL R4, R6, R12, P0 ; /* 0x0000000c06047207 */
/* 0x000fe40000000000 */
/*0640*/ SEL R5, R7, R13, P0 ; /* 0x0000000d07057207 */
/* 0x000fca0000000000 */
/*0650*/ ST.E.64 [R10], R4 ; /* 0x000000000a007385 */
/* 0x0001e40000100b04 */
/*0660*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.NE.U32.AND P0, PT, R12.reuse, R6, PT ; /* 0x000000060c00720c */
/* 0x040fe20003f05070 */
/*0680*/ IMAD.MOV.U32 R22, RZ, RZ, R0 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0000 */
/*0690*/ ISETP.EQ.U32.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f22070 */
/*06a0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*06b0*/ ISETP.NE.AND.EX P0, PT, R13, R7, PT, P0 ; /* 0x000000070d00720c */
/* 0x000fc80003f05300 */
/*06c0*/ ISETP.EQ.OR.EX P0, PT, R13, RZ, !P0, P1 ; /* 0x000000ff0d00720c */
/* 0x000fda0004702710 */
/*06d0*/ @P0 BRA 0x8a0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*06e0*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x001fe20000000004 */
/*06f0*/ IMAD.MOV.U32 R22, RZ, RZ, R0 ; /* 0x000000ffff167224 */
/* 0x000fc600078e0000 */
/*0700*/ LOP3.LUT P0, RZ, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04ff7812 */
/* 0x000fe2000780c0ff */
/*0710*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fd80003800000 */
/*0720*/ @P0 BRA 0x8f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R4, [R8.64+-0x8] ; /* 0xfffff80608047981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000806080a7981 */
/* 0x000ee2000c1e1b00 */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fe200078e00ff */
/*0760*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fc80007ffe0ff */
/*0770*/ SHF.L.U32 R5, R5, R4, RZ ; /* 0x0000000405057219 */
/* 0x004fc800000006ff */
/*0780*/ LOP3.LUT R22, R22, R5, RZ, 0x30, !PT ; /* 0x0000000516167212 */
/* 0x000fe400078e30ff */
/*0790*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc6000001ff00 */
/*07a0*/ IMAD.WIDE.U32 R10, R22, 0x8, R10 ; /* 0x00000008160a7825 */
/* 0x008fca00078e000a */
/*07b0*/ ATOM.E.CAS.64.STRONG.GPU P1, R12, [R10], R4, R6 ; /* 0x000000040a0c738b */
/* 0x000ea8000012e506 */
/*07c0*/ @!P1 LD.E.64 R12, [R10] ; /* 0x000000000a0c9980 */
/* 0x004ea20000100b00 */
/*07d0*/ ISETP.NE.AND P3, PT, R22, R0, PT ; /* 0x000000001600720c */
/* 0x000fe20003f65270 */
/*07e0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fc600078e00ff */
/*07f0*/ SEL R4, RZ, 0x1, P3 ; /* 0x00000001ff047807 */
/* 0x000fe40001800000 */
/*0800*/ @!P1 ISETP.EQ.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00920c */
/* 0x004fc80003f02070 */
/*0810*/ @!P1 ISETP.EQ.U32.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00920c */
/* 0x000fc80003f02100 */
/*0820*/ @!P1 SEL R20, R6, R12, P0 ; /* 0x0000000c06149207 */
/* 0x000fe40000000000 */
/*0830*/ @!P1 SEL R21, R7, R13, P0 ; /* 0x0000000d07159207 */
/* 0x000fe40000000000 */
/*0840*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc60003f05070 */
/*0850*/ @!P1 ST.E.64 [R10], R20 ; /* 0x000000000a009385 */
/* 0x0001e20000100b14 */
/*0860*/ ISETP.NE.U32.AND P1, PT, R12, R6, PT ; /* 0x000000060c00720c */
/* 0x000fe40003f25070 */
/*0870*/ ISETP.NE.AND.EX P0, PT, R13.reuse, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x040fe40003f05300 */
/*0880*/ ISETP.NE.AND.EX P1, PT, R13, R7, PT, P1 ; /* 0x000000070d00720c */
/* 0x000fda0003f25310 */
/*0890*/ @P1 BRA P0, 0x700 ; /* 0xfffffe6000001947 */
/* 0x001fea000003ffff */
/*08a0*/ LDG.E.64 R4, [R8.64+0x10] ; /* 0x0000100608047981 */
/* 0x001ea2000c1e1b00 */
/*08b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*08c0*/ LEA R4, P0, R22, R4, 0x2 ; /* 0x0000000416047211 */
/* 0x004fc800078010ff */
/*08d0*/ LEA.HI.X R5, R22, R5, R23, 0x2, P0 ; /* 0x0000000516057211 */
/* 0x000fca00000f1417 */
/*08e0*/ ATOM.E.ADD.STRONG.GPU PT, RZ, [R4.64], R7 ; /* 0x0000000704ff798a */
/* 0x0001e800081ee1c6 */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ @!P2 BRA 0x1b0 ; /* 0xfffff8a00000a947 */
/* 0x000fea000383ffff */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_fp16.h>
#include <stdio.h>
#include <stdint.h>
#include <zlib.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <fcntl.h>
#include <limits.h>
typedef struct __ReadSeqList {
char* sequence;
unsigned int length;
struct __ReadSeqList* next;
} ReadSeqList;
typedef struct HashTable {
unsigned int bits;
unsigned int count;
unsigned int read_count;
unsigned long long int *keys;
unsigned int *values;
} HashTable;
__device__ const unsigned char seq_nt4_table[256] = { // translate ACGT to 0123
0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
// funcion para calcular un hash de 64 bits
__device__ unsigned int hash_uint64(unsigned long long int key) {
key = ~key + (key << 21);
key = key ^ key >> 24;
key = (key + (key << 3)) + (key << 8);
key = key ^ key >> 14;
key = (key + (key << 2)) + (key << 4);
key = key ^ key >> 28;
key = key + (key << 31);
return (unsigned int)key;
}
HashTable* HashTable_init(unsigned int bits, unsigned int read_count){
HashTable *ht;
ht = (HashTable*)calloc(1, sizeof(HashTable));
ht->read_count = read_count;
ht->bits = bits;
ht->count = 0;
return ht;
}
void HashTable_destory(HashTable *ht) {
if (!ht) return;
free(ht);
}
__device__ unsigned int h2b(unsigned int hash, unsigned int bits) {
return hash * 2654435769U >> (32 - bits);
}
__device__ void hash_insert(HashTable *ht, unsigned long long int kmer) {
unsigned int iKey, last;
bool end = false;
iKey = last = h2b(hash_uint64(kmer), ht->bits);
while (true)
{
unsigned long long int prev = atomicCAS(&(ht->keys[iKey]), 0ULL, kmer);
if (prev == 0ULL || prev == kmer) {
atomicAdd(&(ht->values[iKey]), 1U);
return;
}
if(end) return;
// Collition: Open addressing
iKey = (iKey + 1U) & ((1U << ht->bits) - 1);
// loop back
end = (iKey == last);
}
}
// insert k-mers in $seq to hash table $ht
__global__ void kernel_count_seq_kmers(HashTable *ht, int k, char **d_reads)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < ht->read_count) {
int i, l;
char *seq = d_reads[tid];
int len = 100;
unsigned long long int x[2], mask = (1ULL<<k*2) - 1, shift = (k - 1) * 2;
for (i = l = 0, x[0] = x[1] = 0; i < len; ++i) {
int c = seq_nt4_table[(unsigned char)seq[i]];
if (c < 4) { // not an "N" base
x[0] = (x[0] << 2 | c) & mask; // forward strand
x[1] = x[1] >> 2 | (unsigned long long int)(3 - c) << shift; // reverse strand
if (++l >= k) { // we find a k-mer
unsigned long long int kmer = x[0] < x[1]? x[0] : x[1];
hash_insert(ht, kmer); // only add one strand!
}
} else l = 0, x[0] = x[1] = 0; // if there is an "N", restart
}
}
}
__global__ void kernel_print_hist(const HashTable *ht, unsigned int *cnt_d)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int pos;
if(tid < (1U << ht->bits)) {
if (ht->values[tid] > 0) {
pos = ht->values[tid] < 256U ? ht->values[tid] : 255;
atomicAdd(&(cnt_d[pos]), 1U);
}
}
}
static int count_file(const char *fn, int k, unsigned int p)
{
HashTable *ht;
unsigned int capacity = 1U << p;
unsigned int cnt[256];
unsigned int read_count = 0;
// variables para cuda
HashTable *ht_d;
char **reads_d;
unsigned int *cnt_d;
FILE * fp;
char * line = NULL;
size_t len = 0;
ssize_t read;
fp = fopen(fn, "r");
if (fp == NULL) exit(EXIT_FAILURE);
ReadSeqList *current, *head;
head = current = NULL;
while ((read = getline(&line, &len, fp)) != -1) {
read_count++;
ReadSeqList *node = (ReadSeqList*)malloc(sizeof(ReadSeqList));
node->sequence = (char*)malloc(strlen(line));
strcpy(node->sequence, line);
node->length = read;
node->next =NULL;
if(head == NULL){
current = head = node;
} else {
current = current->next = node;
}
}
fclose(fp);
if (line) free(line);
printf("%d\n", read_count);
unsigned int i;
char **reads = (char**)malloc(read_count * sizeof(char*));
for(i=0, current = head; current; current=current->next){
reads[i] = (char*)malloc(current->length);
sprintf(reads[i], "%s", current->sequence);
i++;
}
// inicializar hashtable
ht = HashTable_init(p, read_count);
unsigned long long int *keys_d;
unsigned int *values_d;
// allocate memory in device
cudaMalloc((void **)&ht_d, sizeof(HashTable));
cudaMalloc((void **)&keys_d, capacity * sizeof(unsigned long long int));
cudaMalloc((void **)&values_d, capacity * sizeof(unsigned int));
cudaMalloc((void **)&cnt_d, 256 * sizeof(unsigned int));
cudaMemset(keys_d, 0ULL, capacity * sizeof(unsigned long long int));
cudaMemset(values_d, 0, capacity * sizeof(unsigned int));
cudaMemset(cnt_d, 0, 256 * sizeof(unsigned int));
// copy data to device
ht->keys = keys_d;
ht->values = values_d;
cudaMemcpy(ht_d, ht, sizeof(HashTable), cudaMemcpyHostToDevice);
char **tmp = (char**)malloc (read_count * sizeof (char*));
for (int i = 0; i < read_count; i++) {
cudaMalloc ((void **)&tmp[i], head->length * sizeof (char));
}
cudaMalloc((void **)&reads_d, read_count * sizeof(char*));
cudaMemcpy(reads_d, tmp, read_count * sizeof (char*), cudaMemcpyHostToDevice);
for (int i = 0; i < read_count; i++) {
cudaMemcpy(tmp[i], reads[i], head->length * sizeof (char), cudaMemcpyHostToDevice);
}
free(tmp);
printf("total reads: %d\n", read_count);
// invocar kernels
unsigned int thr = 1024;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
kernel_count_seq_kmers<<<ceil(read_count/thr), thr>>>(ht_d, k, reads_d);
cudaDeviceSynchronize();
kernel_print_hist<<<ceil(capacity/thr), thr>>>(ht_d, cnt_d);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
float seconds = milliseconds / 1000.0f;
printf("GPU time: %fs\n", seconds);
cudaMemcpy(ht, ht_d, sizeof(HashTable), cudaMemcpyDeviceToHost);
cudaMemcpy(ht->keys, keys_d, capacity * sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
cudaMemcpy(ht->values, values_d, capacity * sizeof(unsigned int), cudaMemcpyDeviceToHost);
cudaMemcpy(cnt, cnt_d, 256 * sizeof(unsigned int), cudaMemcpyDeviceToHost);
printf("COUNT: %d\n\n", ht->count);
for (i = 1; i < 256; ++i)
printf("%d\t%d\n", i, cnt[i]);
// limpieza
cudaFree(reads_d);
cudaFree(ht_d);
cudaFree(cnt_d);
cudaFree(keys_d);
cudaFree(values_d);
// limpieza
i = 0;
for(current = head; current; current=current->next){
free(current->sequence);
free(current);
free(reads[i]);
i++;
}
free(reads);
HashTable_destory(ht);
return 0;
}
int main(int argc, char *argv[])
{
int k = 31;
unsigned int p = 27;
k = (int)strtol(argv[1], NULL, 10);
p = (unsigned int)strtol(argv[2], NULL, 10);
count_file(argv[3], k, p);
return 0;
} | .file "tmpxft_00169cf9_00000000-6_cuda-slow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2457:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2457:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11hash_uint64y
.type _Z11hash_uint64y, @function
_Z11hash_uint64y:
.LFB2448:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2448:
.size _Z11hash_uint64y, .-_Z11hash_uint64y
.globl _Z14HashTable_initjj
.type _Z14HashTable_initjj, @function
_Z14HashTable_initjj:
.LFB2449:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
movl $32, %esi
movl $1, %edi
call calloc@PLT
movl %ebp, 8(%rax)
movl %ebx, (%rax)
movl $0, 4(%rax)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2449:
.size _Z14HashTable_initjj, .-_Z14HashTable_initjj
.globl _Z17HashTable_destoryP9HashTable
.type _Z17HashTable_destoryP9HashTable, @function
_Z17HashTable_destoryP9HashTable:
.LFB2450:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L10
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L10:
ret
.cfi_endproc
.LFE2450:
.size _Z17HashTable_destoryP9HashTable, .-_Z17HashTable_destoryP9HashTable
.globl _Z3h2bjj
.type _Z3h2bjj, @function
_Z3h2bjj:
.LFB2451:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2451:
.size _Z3h2bjj, .-_Z3h2bjj
.globl _Z11hash_insertP9HashTabley
.type _Z11hash_insertP9HashTabley, @function
_Z11hash_insertP9HashTabley:
.LFB2452:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2452:
.size _Z11hash_insertP9HashTabley, .-_Z11hash_insertP9HashTabley
.globl _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
.type _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc, @function
_Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc:
.LFB2479:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22kernel_count_seq_kmersP9HashTableiPPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2479:
.size _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc, .-_Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
.globl _Z22kernel_count_seq_kmersP9HashTableiPPc
.type _Z22kernel_count_seq_kmersP9HashTableiPPc, @function
_Z22kernel_count_seq_kmersP9HashTableiPPc:
.LFB2480:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2480:
.size _Z22kernel_count_seq_kmersP9HashTableiPPc, .-_Z22kernel_count_seq_kmersP9HashTableiPPc
.globl _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
.type _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj, @function
_Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj:
.LFB2481:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17kernel_print_histPK9HashTablePj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2481:
.size _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj, .-_Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
.globl _Z17kernel_print_histPK9HashTablePj
.type _Z17kernel_print_histPK9HashTablePj, @function
_Z17kernel_print_histPK9HashTablePj:
.LFB2482:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2482:
.size _Z17kernel_print_histPK9HashTablePj, .-_Z17kernel_print_histPK9HashTablePj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d\n"
.LC2:
.string "%s"
.LC3:
.string "total reads: %d\n"
.LC6:
.string "GPU time: %fs\n"
.LC7:
.string "COUNT: %d\n\n"
.LC8:
.string "%d\t%d\n"
.text
.type _ZL10count_filePKcij, @function
_ZL10count_filePKcij:
.LFB2453:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1192, %rsp
.cfi_def_cfa_offset 1248
movl %esi, 44(%rsp)
movl %edx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 1176(%rsp)
xorl %eax, %eax
movl $1, %eax
movl %edx, %ecx
sall %cl, %eax
movl %eax, 40(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L59
movq %rax, %r12
movl $0, %r15d
movq $0, (%rsp)
movl $0, %esi
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
movq %r12, 8(%rsp)
movl %esi, %r12d
jmp .L34
.L59:
movl $1, %edi
call exit@PLT
.L51:
movq %rbx, %r15
.L35:
movq %rbx, (%rsp)
.L34:
leaq 72(%rsp), %rdi
movq 8(%rsp), %rcx
movl $10, %edx
movq 16(%rsp), %rsi
call __getdelim@PLT
movq %rax, %rbp
cmpq $-1, %rax
je .L60
addl $1, %r12d
movl $24, %edi
call malloc@PLT
movq %rax, %rbx
movq 72(%rsp), %r14
movq %r14, %rdi
call strlen@PLT
movq %rax, %r13
movq %rax, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq %r13, %rdx
movq %r14, %rsi
call __strcpy_chk@PLT
movl %ebp, 8(%rbx)
movq $0, 16(%rbx)
testq %r15, %r15
je .L51
movq (%rsp), %rax
movq %rbx, 16(%rax)
jmp .L35
.L60:
movl %r12d, (%rsp)
movq 8(%rsp), %r12
movq %r12, %rdi
call fclose@PLT
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .L37
call free@PLT
.L37:
movl (%rsp), %ebx
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
testq %r15, %r15
je .L38
movq %r15, %rbx
movl $0, %ebp
leaq .LC2(%rip), %r14
.L39:
movl 8(%rbx), %r12d
movq %r12, %rdi
call malloc@PLT
movq %rax, %rdi
movl %ebp, %eax
movq %rdi, 0(%r13,%rax,8)
movq (%rbx), %r8
movq %r14, %rcx
movq %r12, %rdx
movl $2, %esi
movl $0, %eax
call __sprintf_chk@PLT
addl $1, %ebp
movq 16(%rbx), %rbx
testq %rbx, %rbx
jne .L39
.L38:
movl (%rsp), %r12d
movl %r12d, %esi
movl 24(%rsp), %edi
call _Z14HashTable_initjj
movq %rax, %r14
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl 40(%rsp), %ebx
leaq 0(,%rbx,8), %rbp
movq %rbp, 24(%rsp)
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
salq $2, %rbx
movq %rbx, 32(%rsp)
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movq %rbp, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movl $1024, %edx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movq 88(%rsp), %rax
movq %rax, 16(%r14)
movq 96(%rsp), %rax
movq %rax, 24(%r14)
movl $1, %ecx
movl $32, %edx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
testl %r12d, %r12d
je .L40
movq %rax, %rbp
movq 8(%rsp), %rax
leaq (%rax,%rbx), %r12
.L41:
movl 8(%r15), %esi
movq %rbx, %rdi
call cudaMalloc@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L41
leaq 56(%rsp), %rdi
movq 8(%rsp), %r12
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
addq %r13, %r12
.L42:
movl 8(%r15), %edx
movq (%rbx), %rsi
movq 0(%rbp), %rdi
movl $1, %ecx
call cudaMemcpy@PLT
addq $8, %rbx
addq $8, %rbp
cmpq %rbx, %r12
jne .L42
.L48:
movq 16(%rsp), %rdi
call free@PLT
movl (%rsp), %ebx
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl %ebx, %eax
shrl $10, %eax
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L43:
call cudaDeviceSynchronize@PLT
movl $1024, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl 40(%rsp), %eax
shrl $10, %eax
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L44:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
movq 112(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 132(%rsp)
leaq 132(%rsp), %rdi
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 132(%rsp), %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $32, %edx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 16(%r14), %rdi
movl $2, %ecx
movq 24(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%r14), %rdi
movl $2, %ecx
movq 32(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%r14), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC8(%rip), %rbp
.L45:
movl 144(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L45
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
testq %r15, %r15
je .L46
movl $0, %ebx
.L47:
movq (%r15), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movl %ebx, %eax
movq 0(%r13,%rax,8), %rdi
call free@PLT
addl $1, %ebx
movq 16(%r15), %r15
testq %r15, %r15
jne .L47
.L46:
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call _Z17HashTable_destoryP9HashTable
movq 1176(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $1192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq 56(%rsp), %rdx
movl 44(%rsp), %esi
movq 48(%rsp), %rdi
call _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
jmp .L43
.L62:
movq 64(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
jmp .L44
.L40:
leaq 56(%rsp), %rdi
movl $0, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $0, %edx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L48
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2453:
.size _ZL10count_filePKcij, .-_ZL10count_filePKcij
.globl main
.type main, @function
main:
.LFB2454:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rbp), %rdi
movl %eax, %edx
movl %ebx, %esi
call _ZL10count_filePKcij
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2454:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z17kernel_print_histPK9HashTablePj"
.align 8
.LC10:
.string "_Z22kernel_count_seq_kmersP9HashTableiPPc"
.section .rodata.str1.1
.LC11:
.string "seq_nt4_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2484:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_print_histPK9HashTablePj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kernel_count_seq_kmersP9HashTableiPPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13seq_nt4_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2484:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 32
.type _ZL13seq_nt4_table, @object
.size _ZL13seq_nt4_table, 256
_ZL13seq_nt4_table:
.string ""
.string "\001\002\003\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.string "\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004"
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_fp16.h>
#include <stdio.h>
#include <stdint.h>
#include <zlib.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <fcntl.h>
#include <limits.h>
typedef struct __ReadSeqList {
char* sequence;
unsigned int length;
struct __ReadSeqList* next;
} ReadSeqList;
typedef struct HashTable {
unsigned int bits;
unsigned int count;
unsigned int read_count;
unsigned long long int *keys;
unsigned int *values;
} HashTable;
__device__ const unsigned char seq_nt4_table[256] = { // translate ACGT to 0123
0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
// funcion para calcular un hash de 64 bits
__device__ unsigned int hash_uint64(unsigned long long int key) {
key = ~key + (key << 21);
key = key ^ key >> 24;
key = (key + (key << 3)) + (key << 8);
key = key ^ key >> 14;
key = (key + (key << 2)) + (key << 4);
key = key ^ key >> 28;
key = key + (key << 31);
return (unsigned int)key;
}
HashTable* HashTable_init(unsigned int bits, unsigned int read_count){
HashTable *ht;
ht = (HashTable*)calloc(1, sizeof(HashTable));
ht->read_count = read_count;
ht->bits = bits;
ht->count = 0;
return ht;
}
void HashTable_destory(HashTable *ht) {
if (!ht) return;
free(ht);
}
__device__ unsigned int h2b(unsigned int hash, unsigned int bits) {
return hash * 2654435769U >> (32 - bits);
}
__device__ void hash_insert(HashTable *ht, unsigned long long int kmer) {
unsigned int iKey, last;
bool end = false;
iKey = last = h2b(hash_uint64(kmer), ht->bits);
while (true)
{
unsigned long long int prev = atomicCAS(&(ht->keys[iKey]), 0ULL, kmer);
if (prev == 0ULL || prev == kmer) {
atomicAdd(&(ht->values[iKey]), 1U);
return;
}
if(end) return;
// Collition: Open addressing
iKey = (iKey + 1U) & ((1U << ht->bits) - 1);
// loop back
end = (iKey == last);
}
}
// insert k-mers in $seq to hash table $ht
__global__ void kernel_count_seq_kmers(HashTable *ht, int k, char **d_reads)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < ht->read_count) {
int i, l;
char *seq = d_reads[tid];
int len = 100;
unsigned long long int x[2], mask = (1ULL<<k*2) - 1, shift = (k - 1) * 2;
for (i = l = 0, x[0] = x[1] = 0; i < len; ++i) {
int c = seq_nt4_table[(unsigned char)seq[i]];
if (c < 4) { // not an "N" base
x[0] = (x[0] << 2 | c) & mask; // forward strand
x[1] = x[1] >> 2 | (unsigned long long int)(3 - c) << shift; // reverse strand
if (++l >= k) { // we find a k-mer
unsigned long long int kmer = x[0] < x[1]? x[0] : x[1];
hash_insert(ht, kmer); // only add one strand!
}
} else l = 0, x[0] = x[1] = 0; // if there is an "N", restart
}
}
}
__global__ void kernel_print_hist(const HashTable *ht, unsigned int *cnt_d)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int pos;
if(tid < (1U << ht->bits)) {
if (ht->values[tid] > 0) {
pos = ht->values[tid] < 256U ? ht->values[tid] : 255;
atomicAdd(&(cnt_d[pos]), 1U);
}
}
}
static int count_file(const char *fn, int k, unsigned int p)
{
HashTable *ht;
unsigned int capacity = 1U << p;
unsigned int cnt[256];
unsigned int read_count = 0;
// variables para cuda
HashTable *ht_d;
char **reads_d;
unsigned int *cnt_d;
FILE * fp;
char * line = NULL;
size_t len = 0;
ssize_t read;
fp = fopen(fn, "r");
if (fp == NULL) exit(EXIT_FAILURE);
ReadSeqList *current, *head;
head = current = NULL;
while ((read = getline(&line, &len, fp)) != -1) {
read_count++;
ReadSeqList *node = (ReadSeqList*)malloc(sizeof(ReadSeqList));
node->sequence = (char*)malloc(strlen(line));
strcpy(node->sequence, line);
node->length = read;
node->next =NULL;
if(head == NULL){
current = head = node;
} else {
current = current->next = node;
}
}
fclose(fp);
if (line) free(line);
printf("%d\n", read_count);
unsigned int i;
char **reads = (char**)malloc(read_count * sizeof(char*));
for(i=0, current = head; current; current=current->next){
reads[i] = (char*)malloc(current->length);
sprintf(reads[i], "%s", current->sequence);
i++;
}
// inicializar hashtable
ht = HashTable_init(p, read_count);
unsigned long long int *keys_d;
unsigned int *values_d;
// allocate memory in device
cudaMalloc((void **)&ht_d, sizeof(HashTable));
cudaMalloc((void **)&keys_d, capacity * sizeof(unsigned long long int));
cudaMalloc((void **)&values_d, capacity * sizeof(unsigned int));
cudaMalloc((void **)&cnt_d, 256 * sizeof(unsigned int));
cudaMemset(keys_d, 0ULL, capacity * sizeof(unsigned long long int));
cudaMemset(values_d, 0, capacity * sizeof(unsigned int));
cudaMemset(cnt_d, 0, 256 * sizeof(unsigned int));
// copy data to device
ht->keys = keys_d;
ht->values = values_d;
cudaMemcpy(ht_d, ht, sizeof(HashTable), cudaMemcpyHostToDevice);
char **tmp = (char**)malloc (read_count * sizeof (char*));
for (int i = 0; i < read_count; i++) {
cudaMalloc ((void **)&tmp[i], head->length * sizeof (char));
}
cudaMalloc((void **)&reads_d, read_count * sizeof(char*));
cudaMemcpy(reads_d, tmp, read_count * sizeof (char*), cudaMemcpyHostToDevice);
for (int i = 0; i < read_count; i++) {
cudaMemcpy(tmp[i], reads[i], head->length * sizeof (char), cudaMemcpyHostToDevice);
}
free(tmp);
printf("total reads: %d\n", read_count);
// invocar kernels
unsigned int thr = 1024;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
kernel_count_seq_kmers<<<ceil(read_count/thr), thr>>>(ht_d, k, reads_d);
cudaDeviceSynchronize();
kernel_print_hist<<<ceil(capacity/thr), thr>>>(ht_d, cnt_d);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
float seconds = milliseconds / 1000.0f;
printf("GPU time: %fs\n", seconds);
cudaMemcpy(ht, ht_d, sizeof(HashTable), cudaMemcpyDeviceToHost);
cudaMemcpy(ht->keys, keys_d, capacity * sizeof(unsigned long long int), cudaMemcpyDeviceToHost);
cudaMemcpy(ht->values, values_d, capacity * sizeof(unsigned int), cudaMemcpyDeviceToHost);
cudaMemcpy(cnt, cnt_d, 256 * sizeof(unsigned int), cudaMemcpyDeviceToHost);
printf("COUNT: %d\n\n", ht->count);
for (i = 1; i < 256; ++i)
printf("%d\t%d\n", i, cnt[i]);
// limpieza
cudaFree(reads_d);
cudaFree(ht_d);
cudaFree(cnt_d);
cudaFree(keys_d);
cudaFree(values_d);
// limpieza
i = 0;
for(current = head; current; current=current->next){
free(current->sequence);
free(current);
free(reads[i]);
i++;
}
free(reads);
HashTable_destory(ht);
return 0;
}
int main(int argc, char *argv[])
{
int k = 31;
unsigned int p = 27;
k = (int)strtol(argv[1], NULL, 10);
p = (unsigned int)strtol(argv[2], NULL, 10);
count_file(argv[3], k, p);
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <stdio.h>
#include <stdint.h>
#include <zlib.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <fcntl.h>
#include <limits.h>
typedef struct __ReadSeqList {
char* sequence;
unsigned int length;
struct __ReadSeqList* next;
} ReadSeqList;
typedef struct HashTable {
unsigned int bits;
unsigned int count;
unsigned int read_count;
unsigned long long int *keys;
unsigned int *values;
} HashTable;
__device__ const unsigned char seq_nt4_table[256] = { // translate ACGT to 0123
0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
// funcion para calcular un hash de 64 bits
__device__ unsigned int hash_uint64(unsigned long long int key) {
key = ~key + (key << 21);
key = key ^ key >> 24;
key = (key + (key << 3)) + (key << 8);
key = key ^ key >> 14;
key = (key + (key << 2)) + (key << 4);
key = key ^ key >> 28;
key = key + (key << 31);
return (unsigned int)key;
}
HashTable* HashTable_init(unsigned int bits, unsigned int read_count){
HashTable *ht;
ht = (HashTable*)calloc(1, sizeof(HashTable));
ht->read_count = read_count;
ht->bits = bits;
ht->count = 0;
return ht;
}
void HashTable_destory(HashTable *ht) {
if (!ht) return;
free(ht);
}
__device__ unsigned int h2b(unsigned int hash, unsigned int bits) {
return hash * 2654435769U >> (32 - bits);
}
__device__ void hash_insert(HashTable *ht, unsigned long long int kmer) {
unsigned int iKey, last;
bool end = false;
iKey = last = h2b(hash_uint64(kmer), ht->bits);
while (true)
{
unsigned long long int prev = atomicCAS(&(ht->keys[iKey]), 0ULL, kmer);
if (prev == 0ULL || prev == kmer) {
atomicAdd(&(ht->values[iKey]), 1U);
return;
}
if(end) return;
// Collition: Open addressing
iKey = (iKey + 1U) & ((1U << ht->bits) - 1);
// loop back
end = (iKey == last);
}
}
// insert k-mers in $seq to hash table $ht
__global__ void kernel_count_seq_kmers(HashTable *ht, int k, char **d_reads)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < ht->read_count) {
int i, l;
char *seq = d_reads[tid];
int len = 100;
unsigned long long int x[2], mask = (1ULL<<k*2) - 1, shift = (k - 1) * 2;
for (i = l = 0, x[0] = x[1] = 0; i < len; ++i) {
int c = seq_nt4_table[(unsigned char)seq[i]];
if (c < 4) { // not an "N" base
x[0] = (x[0] << 2 | c) & mask; // forward strand
x[1] = x[1] >> 2 | (unsigned long long int)(3 - c) << shift; // reverse strand
if (++l >= k) { // we find a k-mer
unsigned long long int kmer = x[0] < x[1]? x[0] : x[1];
hash_insert(ht, kmer); // only add one strand!
}
} else l = 0, x[0] = x[1] = 0; // if there is an "N", restart
}
}
}
__global__ void kernel_print_hist(const HashTable *ht, unsigned int *cnt_d)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int pos;
if(tid < (1U << ht->bits)) {
if (ht->values[tid] > 0) {
pos = ht->values[tid] < 256U ? ht->values[tid] : 255;
atomicAdd(&(cnt_d[pos]), 1U);
}
}
}
static int count_file(const char *fn, int k, unsigned int p)
{
HashTable *ht;
unsigned int capacity = 1U << p;
unsigned int cnt[256];
unsigned int read_count = 0;
// variables para cuda
HashTable *ht_d;
char **reads_d;
unsigned int *cnt_d;
FILE * fp;
char * line = NULL;
size_t len = 0;
ssize_t read;
fp = fopen(fn, "r");
if (fp == NULL) exit(EXIT_FAILURE);
ReadSeqList *current, *head;
head = current = NULL;
while ((read = getline(&line, &len, fp)) != -1) {
read_count++;
ReadSeqList *node = (ReadSeqList*)malloc(sizeof(ReadSeqList));
node->sequence = (char*)malloc(strlen(line));
strcpy(node->sequence, line);
node->length = read;
node->next =NULL;
if(head == NULL){
current = head = node;
} else {
current = current->next = node;
}
}
fclose(fp);
if (line) free(line);
printf("%d\n", read_count);
unsigned int i;
char **reads = (char**)malloc(read_count * sizeof(char*));
for(i=0, current = head; current; current=current->next){
reads[i] = (char*)malloc(current->length);
sprintf(reads[i], "%s", current->sequence);
i++;
}
// inicializar hashtable
ht = HashTable_init(p, read_count);
unsigned long long int *keys_d;
unsigned int *values_d;
// allocate memory in device
hipMalloc((void **)&ht_d, sizeof(HashTable));
hipMalloc((void **)&keys_d, capacity * sizeof(unsigned long long int));
hipMalloc((void **)&values_d, capacity * sizeof(unsigned int));
hipMalloc((void **)&cnt_d, 256 * sizeof(unsigned int));
hipMemset(keys_d, 0ULL, capacity * sizeof(unsigned long long int));
hipMemset(values_d, 0, capacity * sizeof(unsigned int));
hipMemset(cnt_d, 0, 256 * sizeof(unsigned int));
// copy data to device
ht->keys = keys_d;
ht->values = values_d;
hipMemcpy(ht_d, ht, sizeof(HashTable), hipMemcpyHostToDevice);
char **tmp = (char**)malloc (read_count * sizeof (char*));
for (int i = 0; i < read_count; i++) {
hipMalloc ((void **)&tmp[i], head->length * sizeof (char));
}
hipMalloc((void **)&reads_d, read_count * sizeof(char*));
hipMemcpy(reads_d, tmp, read_count * sizeof (char*), hipMemcpyHostToDevice);
for (int i = 0; i < read_count; i++) {
hipMemcpy(tmp[i], reads[i], head->length * sizeof (char), hipMemcpyHostToDevice);
}
free(tmp);
printf("total reads: %d\n", read_count);
// invocar kernels
unsigned int thr = 1024;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
kernel_count_seq_kmers<<<ceil(read_count/thr), thr>>>(ht_d, k, reads_d);
hipDeviceSynchronize();
kernel_print_hist<<<ceil(capacity/thr), thr>>>(ht_d, cnt_d);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
float seconds = milliseconds / 1000.0f;
printf("GPU time: %fs\n", seconds);
hipMemcpy(ht, ht_d, sizeof(HashTable), hipMemcpyDeviceToHost);
hipMemcpy(ht->keys, keys_d, capacity * sizeof(unsigned long long int), hipMemcpyDeviceToHost);
hipMemcpy(ht->values, values_d, capacity * sizeof(unsigned int), hipMemcpyDeviceToHost);
hipMemcpy(cnt, cnt_d, 256 * sizeof(unsigned int), hipMemcpyDeviceToHost);
printf("COUNT: %d\n\n", ht->count);
for (i = 1; i < 256; ++i)
printf("%d\t%d\n", i, cnt[i]);
// limpieza
hipFree(reads_d);
hipFree(ht_d);
hipFree(cnt_d);
hipFree(keys_d);
hipFree(values_d);
// limpieza
i = 0;
for(current = head; current; current=current->next){
free(current->sequence);
free(current);
free(reads[i]);
i++;
}
free(reads);
HashTable_destory(ht);
return 0;
}
int main(int argc, char *argv[])
{
int k = 31;
unsigned int p = 27;
k = (int)strtol(argv[1], NULL, 10);
p = (unsigned int)strtol(argv[2], NULL, 10);
count_file(argv[3], k, p);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <stdio.h>
#include <stdint.h>
#include <zlib.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <fcntl.h>
#include <limits.h>
typedef struct __ReadSeqList {
char* sequence;
unsigned int length;
struct __ReadSeqList* next;
} ReadSeqList;
typedef struct HashTable {
unsigned int bits;
unsigned int count;
unsigned int read_count;
unsigned long long int *keys;
unsigned int *values;
} HashTable;
__device__ const unsigned char seq_nt4_table[256] = { // translate ACGT to 0123
0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
// funcion para calcular un hash de 64 bits
__device__ unsigned int hash_uint64(unsigned long long int key) {
key = ~key + (key << 21);
key = key ^ key >> 24;
key = (key + (key << 3)) + (key << 8);
key = key ^ key >> 14;
key = (key + (key << 2)) + (key << 4);
key = key ^ key >> 28;
key = key + (key << 31);
return (unsigned int)key;
}
HashTable* HashTable_init(unsigned int bits, unsigned int read_count){
HashTable *ht;
ht = (HashTable*)calloc(1, sizeof(HashTable));
ht->read_count = read_count;
ht->bits = bits;
ht->count = 0;
return ht;
}
void HashTable_destory(HashTable *ht) {
if (!ht) return;
free(ht);
}
__device__ unsigned int h2b(unsigned int hash, unsigned int bits) {
return hash * 2654435769U >> (32 - bits);
}
__device__ void hash_insert(HashTable *ht, unsigned long long int kmer) {
unsigned int iKey, last;
bool end = false;
iKey = last = h2b(hash_uint64(kmer), ht->bits);
while (true)
{
unsigned long long int prev = atomicCAS(&(ht->keys[iKey]), 0ULL, kmer);
if (prev == 0ULL || prev == kmer) {
atomicAdd(&(ht->values[iKey]), 1U);
return;
}
if(end) return;
// Collition: Open addressing
iKey = (iKey + 1U) & ((1U << ht->bits) - 1);
// loop back
end = (iKey == last);
}
}
// insert k-mers in $seq to hash table $ht
__global__ void kernel_count_seq_kmers(HashTable *ht, int k, char **d_reads)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < ht->read_count) {
int i, l;
char *seq = d_reads[tid];
int len = 100;
unsigned long long int x[2], mask = (1ULL<<k*2) - 1, shift = (k - 1) * 2;
for (i = l = 0, x[0] = x[1] = 0; i < len; ++i) {
int c = seq_nt4_table[(unsigned char)seq[i]];
if (c < 4) { // not an "N" base
x[0] = (x[0] << 2 | c) & mask; // forward strand
x[1] = x[1] >> 2 | (unsigned long long int)(3 - c) << shift; // reverse strand
if (++l >= k) { // we find a k-mer
unsigned long long int kmer = x[0] < x[1]? x[0] : x[1];
hash_insert(ht, kmer); // only add one strand!
}
} else l = 0, x[0] = x[1] = 0; // if there is an "N", restart
}
}
}
__global__ void kernel_print_hist(const HashTable *ht, unsigned int *cnt_d)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int pos;
if(tid < (1U << ht->bits)) {
if (ht->values[tid] > 0) {
pos = ht->values[tid] < 256U ? ht->values[tid] : 255;
atomicAdd(&(cnt_d[pos]), 1U);
}
}
}
static int count_file(const char *fn, int k, unsigned int p)
{
HashTable *ht;
unsigned int capacity = 1U << p;
unsigned int cnt[256];
unsigned int read_count = 0;
// variables para cuda
HashTable *ht_d;
char **reads_d;
unsigned int *cnt_d;
FILE * fp;
char * line = NULL;
size_t len = 0;
ssize_t read;
fp = fopen(fn, "r");
if (fp == NULL) exit(EXIT_FAILURE);
ReadSeqList *current, *head;
head = current = NULL;
while ((read = getline(&line, &len, fp)) != -1) {
read_count++;
ReadSeqList *node = (ReadSeqList*)malloc(sizeof(ReadSeqList));
node->sequence = (char*)malloc(strlen(line));
strcpy(node->sequence, line);
node->length = read;
node->next =NULL;
if(head == NULL){
current = head = node;
} else {
current = current->next = node;
}
}
fclose(fp);
if (line) free(line);
printf("%d\n", read_count);
unsigned int i;
char **reads = (char**)malloc(read_count * sizeof(char*));
for(i=0, current = head; current; current=current->next){
reads[i] = (char*)malloc(current->length);
sprintf(reads[i], "%s", current->sequence);
i++;
}
// inicializar hashtable
ht = HashTable_init(p, read_count);
unsigned long long int *keys_d;
unsigned int *values_d;
// allocate memory in device
hipMalloc((void **)&ht_d, sizeof(HashTable));
hipMalloc((void **)&keys_d, capacity * sizeof(unsigned long long int));
hipMalloc((void **)&values_d, capacity * sizeof(unsigned int));
hipMalloc((void **)&cnt_d, 256 * sizeof(unsigned int));
hipMemset(keys_d, 0ULL, capacity * sizeof(unsigned long long int));
hipMemset(values_d, 0, capacity * sizeof(unsigned int));
hipMemset(cnt_d, 0, 256 * sizeof(unsigned int));
// copy data to device
ht->keys = keys_d;
ht->values = values_d;
hipMemcpy(ht_d, ht, sizeof(HashTable), hipMemcpyHostToDevice);
char **tmp = (char**)malloc (read_count * sizeof (char*));
for (int i = 0; i < read_count; i++) {
hipMalloc ((void **)&tmp[i], head->length * sizeof (char));
}
hipMalloc((void **)&reads_d, read_count * sizeof(char*));
hipMemcpy(reads_d, tmp, read_count * sizeof (char*), hipMemcpyHostToDevice);
for (int i = 0; i < read_count; i++) {
hipMemcpy(tmp[i], reads[i], head->length * sizeof (char), hipMemcpyHostToDevice);
}
free(tmp);
printf("total reads: %d\n", read_count);
// invocar kernels
unsigned int thr = 1024;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
kernel_count_seq_kmers<<<ceil(read_count/thr), thr>>>(ht_d, k, reads_d);
hipDeviceSynchronize();
kernel_print_hist<<<ceil(capacity/thr), thr>>>(ht_d, cnt_d);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
float seconds = milliseconds / 1000.0f;
printf("GPU time: %fs\n", seconds);
hipMemcpy(ht, ht_d, sizeof(HashTable), hipMemcpyDeviceToHost);
hipMemcpy(ht->keys, keys_d, capacity * sizeof(unsigned long long int), hipMemcpyDeviceToHost);
hipMemcpy(ht->values, values_d, capacity * sizeof(unsigned int), hipMemcpyDeviceToHost);
hipMemcpy(cnt, cnt_d, 256 * sizeof(unsigned int), hipMemcpyDeviceToHost);
printf("COUNT: %d\n\n", ht->count);
for (i = 1; i < 256; ++i)
printf("%d\t%d\n", i, cnt[i]);
// limpieza
hipFree(reads_d);
hipFree(ht_d);
hipFree(cnt_d);
hipFree(keys_d);
hipFree(values_d);
// limpieza
i = 0;
for(current = head; current; current=current->next){
free(current->sequence);
free(current);
free(reads[i]);
i++;
}
free(reads);
HashTable_destory(ht);
return 0;
}
int main(int argc, char *argv[])
{
int k = 31;
unsigned int p = 27;
k = (int)strtol(argv[1], NULL, 10);
p = (unsigned int)strtol(argv[2], NULL, 10);
count_file(argv[3], k, p);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22kernel_count_seq_kmersP9HashTableiPPc
.globl _Z22kernel_count_seq_kmersP9HashTableiPPc
.p2align 8
.type _Z22kernel_count_seq_kmersP9HashTableiPPc,@function
_Z22kernel_count_seq_kmersP9HashTableiPPc:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x8
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_14
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_load_b32 s1, s[0:1], 0x8
s_mov_b32 s6, 0
s_mov_b32 s8, 0
v_mov_b32_e32 v7, 0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_lshl_b32 s0, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], -1, s0
global_load_b64 v[4:5], v[0:1], off
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v14, 1
s_not_b64 s[4:5], s[4:5]
s_add_i32 s7, s0, -2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v13, v9
v_dual_mov_b32 v0, v10 :: v_dual_mov_b32 v1, v11
v_mov_b32_e32 v12, v8
s_add_i32 s8, s8, 1
s_cmpk_lg_i32 s8, 0x64
s_cbranch_scc0 .LBB0_14
.LBB0_4:
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, _ZL13seq_nt4_table@rel32@lo+4
s_addc_u32 s11, s11, _ZL13seq_nt4_table@rel32@hi+12
v_mov_b32_e32 v15, v7
s_mov_b32 s9, exec_lo
flat_load_u8 v3, v[8:9]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v3, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, v3, s10
v_add_co_ci_u32_e64 v9, null, 0, s11, s0
global_load_u8 v3, v[8:9], off
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
s_waitcnt vmcnt(0)
v_cmpx_gt_u16_e32 4, v3
s_cbranch_execz .LBB0_3
v_xor_b32_e32 v6, 3, v3
v_lshlrev_b64 v[8:9], 2, v[12:13]
v_mov_b32_e32 v11, s6
v_and_b32_e32 v3, 0xffff, v3
v_lshrrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v10, 0xffff, v6
v_add_nc_u32_e32 v15, 1, v2
v_and_b32_e32 v9, s5, v9
v_or_b32_e32 v3, v8, v3
s_mov_b32 s10, exec_lo
v_lshlrev_b64 v[10:11], s7, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v8, s4, v3
v_or_b32_e32 v11, v11, v1
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v10, v10, v0
v_cmpx_le_i32_e64 s1, v15
s_cbranch_execz .LBB0_2
global_load_b32 v6, v7, s[2:3]
v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[10:11]
s_mov_b32 s12, 0
s_mov_b32 s11, 0
v_dual_cndmask_b32 v1, v11, v9 :: v_dual_cndmask_b32 v0, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_not_b32_e32 v13, v1
v_lshlrev_b64 v[2:3], 21, v[0:1]
v_not_b32_e32 v12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b64 v[12:13], 24, v[2:3]
v_xor_b32_e32 v2, v12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v13, v3
v_mad_u64_u32 v[16:17], null, v2, 0x109, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v17
v_mad_u64_u32 v[12:13], null, v3, 0x109, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v17, v12
v_lshrrev_b64 v[2:3], 14, v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v16
v_xor_b32_e32 v3, v3, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v2, 21, 0
v_mov_b32_e32 v2, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[16:17], null, v3, 21, v[2:3]
v_mov_b32_e32 v2, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v2, v2, v12, 28
v_xor_b32_e32 v2, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, 0x1e3779b9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, 32, v6
v_lshrrev_b32_e32 v12, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v12
s_branch .LBB0_8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
s_xor_b32 s0, s0, -1
s_mov_b32 s12, s13
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s0, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_2
.LBB0_8:
global_load_b64 v[16:17], v7, s[2:3] offset:16
v_lshlrev_b64 v[18:19], 3, v[6:7]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v16, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v17, vcc_lo, v17, v19, vcc_lo
flat_atomic_cmpswap_b64 v[2:3], v[16:17], v[0:3] glc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
v_cmp_ne_u64_e64 s0, v[2:3], v[0:1]
s_and_b32 s14, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_12
s_xor_b32 s16, s12, -1
s_mov_b32 s0, 0
s_mov_b32 s15, s12
s_and_saveexec_b32 s13, s16
s_cbranch_execz .LBB0_11
global_load_b32 v2, v7, s[2:3]
v_add_nc_u32_e32 v3, 1, v6
s_and_not1_b32 s15, s12, exec_lo
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_u32 v6, v3, 0, v2
v_cmp_eq_u32_e32 vcc_lo, v6, v12
s_and_b32 s16, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s15, s15, s16
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_and_b32 s13, s15, exec_lo
.LBB0_12:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_7
global_load_b64 v[2:3], v7, s[2:3] offset:24
v_lshlrev_b64 v[16:17], 2, v[6:7]
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s12, s12, exec_lo
s_and_not1_b32 s0, s0, exec_lo
s_or_b32 s13, s13, s12
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, v16
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
flat_atomic_add_u32 v[2:3], v14
s_branch .LBB0_7
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22kernel_count_seq_kmersP9HashTableiPPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22kernel_count_seq_kmersP9HashTableiPPc, .Lfunc_end0-_Z22kernel_count_seq_kmersP9HashTableiPPc
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17kernel_print_histPK9HashTablePj
.globl _Z17kernel_print_histPK9HashTablePj
.p2align 8
.type _Z17kernel_print_histPK9HashTablePj,@function
_Z17kernel_print_histPK9HashTablePj:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v0, s5, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[2:3], s[2:3], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
flat_load_b32 v0, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x8
v_min_u32_e32 v0, 0xff, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_print_histPK9HashTablePj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17kernel_print_histPK9HashTablePj, .Lfunc_end1-_Z17kernel_print_histPK9HashTablePj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL13seq_nt4_table,@object
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL13seq_nt4_table:
.ascii "\000\001\002\003\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\000\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004\004\000\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.size _ZL13seq_nt4_table, 256
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22kernel_count_seq_kmersP9HashTableiPPc
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z22kernel_count_seq_kmersP9HashTableiPPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_print_histPK9HashTablePj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_print_histPK9HashTablePj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <stdio.h>
#include <stdint.h>
#include <zlib.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <fcntl.h>
#include <limits.h>
typedef struct __ReadSeqList {
char* sequence;
unsigned int length;
struct __ReadSeqList* next;
} ReadSeqList;
typedef struct HashTable {
unsigned int bits;
unsigned int count;
unsigned int read_count;
unsigned long long int *keys;
unsigned int *values;
} HashTable;
__device__ const unsigned char seq_nt4_table[256] = { // translate ACGT to 0123
0, 1, 2, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 0, 4, 1, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
// funcion para calcular un hash de 64 bits
__device__ unsigned int hash_uint64(unsigned long long int key) {
key = ~key + (key << 21);
key = key ^ key >> 24;
key = (key + (key << 3)) + (key << 8);
key = key ^ key >> 14;
key = (key + (key << 2)) + (key << 4);
key = key ^ key >> 28;
key = key + (key << 31);
return (unsigned int)key;
}
HashTable* HashTable_init(unsigned int bits, unsigned int read_count){
HashTable *ht;
ht = (HashTable*)calloc(1, sizeof(HashTable));
ht->read_count = read_count;
ht->bits = bits;
ht->count = 0;
return ht;
}
void HashTable_destory(HashTable *ht) {
if (!ht) return;
free(ht);
}
__device__ unsigned int h2b(unsigned int hash, unsigned int bits) {
return hash * 2654435769U >> (32 - bits);
}
__device__ void hash_insert(HashTable *ht, unsigned long long int kmer) {
unsigned int iKey, last;
bool end = false;
iKey = last = h2b(hash_uint64(kmer), ht->bits);
while (true)
{
unsigned long long int prev = atomicCAS(&(ht->keys[iKey]), 0ULL, kmer);
if (prev == 0ULL || prev == kmer) {
atomicAdd(&(ht->values[iKey]), 1U);
return;
}
if(end) return;
// Collition: Open addressing
iKey = (iKey + 1U) & ((1U << ht->bits) - 1);
// loop back
end = (iKey == last);
}
}
// insert k-mers in $seq to hash table $ht
__global__ void kernel_count_seq_kmers(HashTable *ht, int k, char **d_reads)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < ht->read_count) {
int i, l;
char *seq = d_reads[tid];
int len = 100;
unsigned long long int x[2], mask = (1ULL<<k*2) - 1, shift = (k - 1) * 2;
for (i = l = 0, x[0] = x[1] = 0; i < len; ++i) {
int c = seq_nt4_table[(unsigned char)seq[i]];
if (c < 4) { // not an "N" base
x[0] = (x[0] << 2 | c) & mask; // forward strand
x[1] = x[1] >> 2 | (unsigned long long int)(3 - c) << shift; // reverse strand
if (++l >= k) { // we find a k-mer
unsigned long long int kmer = x[0] < x[1]? x[0] : x[1];
hash_insert(ht, kmer); // only add one strand!
}
} else l = 0, x[0] = x[1] = 0; // if there is an "N", restart
}
}
}
__global__ void kernel_print_hist(const HashTable *ht, unsigned int *cnt_d)
{
unsigned int tid = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int pos;
if(tid < (1U << ht->bits)) {
if (ht->values[tid] > 0) {
pos = ht->values[tid] < 256U ? ht->values[tid] : 255;
atomicAdd(&(cnt_d[pos]), 1U);
}
}
}
static int count_file(const char *fn, int k, unsigned int p)
{
HashTable *ht;
unsigned int capacity = 1U << p;
unsigned int cnt[256];
unsigned int read_count = 0;
// variables para cuda
HashTable *ht_d;
char **reads_d;
unsigned int *cnt_d;
FILE * fp;
char * line = NULL;
size_t len = 0;
ssize_t read;
fp = fopen(fn, "r");
if (fp == NULL) exit(EXIT_FAILURE);
ReadSeqList *current, *head;
head = current = NULL;
while ((read = getline(&line, &len, fp)) != -1) {
read_count++;
ReadSeqList *node = (ReadSeqList*)malloc(sizeof(ReadSeqList));
node->sequence = (char*)malloc(strlen(line));
strcpy(node->sequence, line);
node->length = read;
node->next =NULL;
if(head == NULL){
current = head = node;
} else {
current = current->next = node;
}
}
fclose(fp);
if (line) free(line);
printf("%d\n", read_count);
unsigned int i;
char **reads = (char**)malloc(read_count * sizeof(char*));
for(i=0, current = head; current; current=current->next){
reads[i] = (char*)malloc(current->length);
sprintf(reads[i], "%s", current->sequence);
i++;
}
// inicializar hashtable
ht = HashTable_init(p, read_count);
unsigned long long int *keys_d;
unsigned int *values_d;
// allocate memory in device
hipMalloc((void **)&ht_d, sizeof(HashTable));
hipMalloc((void **)&keys_d, capacity * sizeof(unsigned long long int));
hipMalloc((void **)&values_d, capacity * sizeof(unsigned int));
hipMalloc((void **)&cnt_d, 256 * sizeof(unsigned int));
hipMemset(keys_d, 0ULL, capacity * sizeof(unsigned long long int));
hipMemset(values_d, 0, capacity * sizeof(unsigned int));
hipMemset(cnt_d, 0, 256 * sizeof(unsigned int));
// copy data to device
ht->keys = keys_d;
ht->values = values_d;
hipMemcpy(ht_d, ht, sizeof(HashTable), hipMemcpyHostToDevice);
char **tmp = (char**)malloc (read_count * sizeof (char*));
for (int i = 0; i < read_count; i++) {
hipMalloc ((void **)&tmp[i], head->length * sizeof (char));
}
hipMalloc((void **)&reads_d, read_count * sizeof(char*));
hipMemcpy(reads_d, tmp, read_count * sizeof (char*), hipMemcpyHostToDevice);
for (int i = 0; i < read_count; i++) {
hipMemcpy(tmp[i], reads[i], head->length * sizeof (char), hipMemcpyHostToDevice);
}
free(tmp);
printf("total reads: %d\n", read_count);
// invocar kernels
unsigned int thr = 1024;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
kernel_count_seq_kmers<<<ceil(read_count/thr), thr>>>(ht_d, k, reads_d);
hipDeviceSynchronize();
kernel_print_hist<<<ceil(capacity/thr), thr>>>(ht_d, cnt_d);
hipDeviceSynchronize();
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
float seconds = milliseconds / 1000.0f;
printf("GPU time: %fs\n", seconds);
hipMemcpy(ht, ht_d, sizeof(HashTable), hipMemcpyDeviceToHost);
hipMemcpy(ht->keys, keys_d, capacity * sizeof(unsigned long long int), hipMemcpyDeviceToHost);
hipMemcpy(ht->values, values_d, capacity * sizeof(unsigned int), hipMemcpyDeviceToHost);
hipMemcpy(cnt, cnt_d, 256 * sizeof(unsigned int), hipMemcpyDeviceToHost);
printf("COUNT: %d\n\n", ht->count);
for (i = 1; i < 256; ++i)
printf("%d\t%d\n", i, cnt[i]);
// limpieza
hipFree(reads_d);
hipFree(ht_d);
hipFree(cnt_d);
hipFree(keys_d);
hipFree(values_d);
// limpieza
i = 0;
for(current = head; current; current=current->next){
free(current->sequence);
free(current);
free(reads[i]);
i++;
}
free(reads);
HashTable_destory(ht);
return 0;
}
int main(int argc, char *argv[])
{
int k = 31;
unsigned int p = 27;
k = (int)strtol(argv[1], NULL, 10);
p = (unsigned int)strtol(argv[2], NULL, 10);
count_file(argv[3], k, p);
return 0;
} | .text
.file "cuda-slow.hip"
.globl _Z14HashTable_initjj # -- Begin function _Z14HashTable_initjj
.p2align 4, 0x90
.type _Z14HashTable_initjj,@function
_Z14HashTable_initjj: # @_Z14HashTable_initjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movl $1, %edi
movl $32, %esi
callq calloc
movl %ebx, 8(%rax)
movl %ebp, (%rax)
movl $0, 4(%rax)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z14HashTable_initjj, .Lfunc_end0-_Z14HashTable_initjj
.cfi_endproc
# -- End function
.globl _Z17HashTable_destoryP9HashTable # -- Begin function _Z17HashTable_destoryP9HashTable
.p2align 4, 0x90
.type _Z17HashTable_destoryP9HashTable,@function
_Z17HashTable_destoryP9HashTable: # @_Z17HashTable_destoryP9HashTable
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
jne free # TAILCALL
# %bb.1:
retq
.Lfunc_end1:
.size _Z17HashTable_destoryP9HashTable, .Lfunc_end1-_Z17HashTable_destoryP9HashTable
.cfi_endproc
# -- End function
.globl _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc # -- Begin function _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.p2align 4, 0x90
.type _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc,@function
_Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc: # @_Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22kernel_count_seq_kmersP9HashTableiPPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc, .Lfunc_end2-_Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.cfi_endproc
# -- End function
.globl _Z32__device_stub__kernel_print_histPK9HashTablePj # -- Begin function _Z32__device_stub__kernel_print_histPK9HashTablePj
.p2align 4, 0x90
.type _Z32__device_stub__kernel_print_histPK9HashTablePj,@function
_Z32__device_stub__kernel_print_histPK9HashTablePj: # @_Z32__device_stub__kernel_print_histPK9HashTablePj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17kernel_print_histPK9HashTablePj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z32__device_stub__kernel_print_histPK9HashTablePj, .Lfunc_end3-_Z32__device_stub__kernel_print_histPK9HashTablePj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1240, %rsp # imm = 0x4D8
.cfi_def_cfa_offset 1296
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $1, %eax
movl %r15d, %ecx
shll %cl, %eax
movq %rax, 160(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
movq $0, 72(%rsp)
movq $0, 176(%rsp)
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.1: # %.preheader.i
movq %r15, 88(%rsp) # 8-byte Spill
movq %r14, 184(%rsp) # 8-byte Spill
leaq 72(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $10, %edx
movq %rax, 48(%rsp) # 8-byte Spill
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB4_2
# %bb.4: # %.lr.ph.i.preheader
movq %rax, %r13
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %r14d, %r14d
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_5 Depth=1
leaq 72(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $10, %edx
movq 48(%rsp), %rcx # 8-byte Reload
callq __getdelim
movq %rax, %r13
movq 8(%rsp), %rax # 8-byte Reload
incl %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, %r12
movq %rbp, %r14
cmpq $-1, %r13
je .LBB4_8
.LBB4_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $24, %edi
callq malloc
movq %rax, %rbx
movq 72(%rsp), %r15
movq %r15, %rdi
callq strlen
movq %rax, %rdi
callq malloc
movq %rax, (%rbx)
movq %rax, %rdi
movq %r15, %rsi
callq strcpy
movl %r13d, 8(%rbx)
movq $0, 16(%rbx)
movq %rbx, %rbp
testq %r14, %r14
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_5 Depth=1
movq %rbx, 16(%r12)
movq %r14, %rbp
jmp .LBB4_7
.LBB4_2:
xorl %ebp, %ebp
.LBB4_8: # %._crit_edge.i
movq 48(%rsp), %rdi # 8-byte Reload
callq fclose
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_10
# %bb.9:
callq free
.LBB4_10:
xorl %r12d, %r12d
movl $.L.str.1, %edi
movq 8(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, %eax
movq %rax, 192(%rsp) # 8-byte Spill
leaq (,%rax,8), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
testq %rbp, %rbp
je .LBB4_13
# %bb.11: # %.lr.ph129.i.preheader
movq %rbp, %r15
.p2align 4, 0x90
.LBB4_12: # %.lr.ph129.i
# =>This Inner Loop Header: Depth=1
movl 8(%r15), %edi
callq malloc
movl %r12d, %ecx
movq %rax, (%r14,%rcx,8)
movq (%r15), %rsi
movq %rax, %rdi
callq strcpy
incl %r12d
movq 16(%r15), %r15
testq %r15, %r15
jne .LBB4_12
.LBB4_13: # %._crit_edge130.i
movl $1, %edi
movl $32, %esi
callq calloc
movq %rax, %r15
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 8(%r15)
movq 88(%rsp), %rax # 8-byte Reload
movl %eax, (%r15)
movl $0, 4(%r15)
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movl 160(%rsp), %r12d # 4-byte Reload
leaq (,%r12,8), %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
shlq $2, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 64(%rsp), %rdi
xorl %esi, %esi
movq %rbx, 200(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq hipMemset
movq 56(%rsp), %rdi
xorl %esi, %esi
movq %r12, 88(%rsp) # 8-byte Spill
movq %r12, %rdx
callq hipMemset
movq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
movq 64(%rsp), %rax
movq %rax, 16(%r15)
movq 56(%rsp), %rax
movq %rax, 24(%r15)
movq 24(%rsp), %rdi
movl $32, %edx
movq %r15, 48(%rsp) # 8-byte Spill
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
callq malloc
movq %rax, %r12
cmpl $0, 8(%rsp) # 4-byte Folded Reload
je .LBB4_19
# %bb.14: # %.lr.ph133.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_15: # =>This Inner Loop Header: Depth=1
leaq (%r12,%r15), %rdi
movl 8(%rbp), %esi
callq hipMalloc
addq $8, %r15
cmpq %r15, %r13
jne .LBB4_15
# %bb.16: # %._crit_edge134.i
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movq 192(%rsp), %rbx # 8-byte Reload
je .LBB4_20
# %bb.17: # %.lr.ph137.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # =>This Inner Loop Header: Depth=1
movq (%r12,%r15,8), %rdi
movq (%r14,%r15,8), %rsi
movl 8(%rbp), %edx
movl $1, %ecx
callq hipMemcpy
incq %r15
cmpq %r15, %rbx
jne .LBB4_18
jmp .LBB4_20
.LBB4_19: # %._crit_edge138.i.critedge
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
.LBB4_20: # %._crit_edge138.i
movabsq $4294967296, %r13 # imm = 0x100000000
movq %r12, %rdi
callq free
movl $.L.str.3, %edi
movq 8(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
shrl $10, %ebx
orq %r13, %rbx
leaq 1024(%r13), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_22
# %bb.21:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq 184(%rsp), %rax # 8-byte Reload
movl %eax, 156(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 156(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rax
movq %rax, 224(%rsp)
leaq 32(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z22kernel_count_seq_kmersP9HashTableiPPc, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_22:
callq hipDeviceSynchronize
movq 160(%rsp), %rdi # 8-byte Reload
shrl $10, %edi
orq %r13, %rdi
addq $1024, %r13 # imm = 0x400
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 48(%rsp), %r15 # 8-byte Reload
jne .LBB4_24
# %bb.23:
movq 24(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z17kernel_print_histPK9HashTablePj, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_24:
callq hipDeviceSynchronize
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 168(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $32, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%r15), %rdi
movq 64(%rsp), %rsi
movq 200(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%r15), %rdi
movq 56(%rsp), %rsi
movq 88(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 80(%rsp), %rsi
leaq 208(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movl 4(%r15), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $1, %r12d
.p2align 4, 0x90
.LBB4_25: # =>This Inner Loop Header: Depth=1
movl 208(%rsp,%r12,4), %edx
movl $.L.str.6, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB4_25
# %bb.26:
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
testq %rbp, %rbp
je .LBB4_29
# %bb.27: # %.lr.ph144.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_28: # %.lr.ph144.i
# =>This Inner Loop Header: Depth=1
movq (%rbp), %rdi
callq free
movq %rbp, %rdi
callq free
movl %ebx, %eax
movq (%r14,%rax,8), %rdi
callq free
incl %ebx
movq 16(%rbp), %rbp
testq %rbp, %rbp
jne .LBB4_28
.LBB4_29: # %_ZL10count_filePKcij.exit
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1240, %rsp # imm = 0x4D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 1296
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22kernel_count_seq_kmersP9HashTableiPPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_print_histPK9HashTablePj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22kernel_count_seq_kmersP9HashTableiPPc,@object # @_Z22kernel_count_seq_kmersP9HashTableiPPc
.section .rodata,"a",@progbits
.globl _Z22kernel_count_seq_kmersP9HashTableiPPc
.p2align 3, 0x0
_Z22kernel_count_seq_kmersP9HashTableiPPc:
.quad _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.size _Z22kernel_count_seq_kmersP9HashTableiPPc, 8
.type _Z17kernel_print_histPK9HashTablePj,@object # @_Z17kernel_print_histPK9HashTablePj
.globl _Z17kernel_print_histPK9HashTablePj
.p2align 3, 0x0
_Z17kernel_print_histPK9HashTablePj:
.quad _Z32__device_stub__kernel_print_histPK9HashTablePj
.size _Z17kernel_print_histPK9HashTablePj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total reads: %d\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU time: %fs\n"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "COUNT: %d\n\n"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d\t%d\n"
.size .L.str.6, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22kernel_count_seq_kmersP9HashTableiPPc"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17kernel_print_histPK9HashTablePj"
.size .L__unnamed_2, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.addrsig_sym _Z32__device_stub__kernel_print_histPK9HashTablePj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22kernel_count_seq_kmersP9HashTableiPPc
.addrsig_sym _Z17kernel_print_histPK9HashTablePj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17kernel_print_histPK9HashTablePj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0070*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0204 */
/*0090*/ SHF.L.U32 R0, R7, R0, RZ ; /* 0x0000000007007219 */
/* 0x004fc800000006ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E.64 R2, [R2.64+0x18] ; /* 0x0000180402027981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD.WIDE.U32 R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x004fcc00078e0002 */
/*00e0*/ LD.E R4, [R4.64] ; /* 0x0000000404047980 */
/* 0x000ea4000c101900 */
/*00f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ ISETP.LT.U32.AND P0, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x000fc80003f01070 */
/*0120*/ ISETP.LT.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fc80003f01100 */
/*0130*/ SEL R4, R4, 0xff, P0 ; /* 0x000000ff04047807 */
/* 0x000fc80000000000 */
/*0140*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x000fc800078010ff */
/*0150*/ LEA.HI.X R3, R4, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f14ff */
/*0160*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e184 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z22kernel_count_seq_kmersP9HashTableiPPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R3, [R2.64+0x8] ; /* 0x0000080602037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fc6000ff1e03f */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0090*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*00a0*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fc8000f8e00ff */
/*00b0*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x000fe4000f8e00ff */
/*00c0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06070 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0003 */
/*0110*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000f62000c1e1b00 */
/*0120*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0130*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0140*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0150*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*0160*/ UMOV UR5, 0xffffffff ; /* 0xffffffff00057882 */
/* 0x000fe20000000000 */
/*0170*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0180*/ USHF.L.U64.HI UR8, UR5, UR4, 0xffffffff ; /* 0xffffffff05087499 */
/* 0x000fe40008010204 */
/*0190*/ USHF.L.U32 UR5, UR5, UR4, URZ ; /* 0x0000000405057299 */
/* 0x000fe4000800063f */
/*01a0*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fc4000fffe03f */
/*01b0*/ IADD3 R4, P0, R2, R19, RZ ; /* 0x0000001302047210 */
/* 0x021fc80007f1e0ff */
/*01c0*/ LEA.HI.X.SX32 R5, R19, R3, 0x1, P0 ; /* 0x0000000313057211 */
/* 0x000fca00000f0eff */
/*01d0*/ LD.E.U8 R4, [R4.64] ; /* 0x0000000604047980 */
/* 0x000ea4000c101100 */
/*01e0*/ IADD3 R6, P0, R4, c[0x4][0x0], RZ ; /* 0x0100000004067a10 */
/* 0x004fca0007f1e0ff */
/*01f0*/ IMAD.X R7, RZ, RZ, c[0x4][0x4], P0 ; /* 0x01000100ff077624 */
/* 0x000fcc00000e06ff */
/*0200*/ LDG.E.U8.CONSTANT R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e9100 */
/*0210*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe20007ffe0ff */
/*0220*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B0, 0x900 ; /* 0x000006c000007945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0012 */
/*0250*/ ISETP.GE.U32.AND P2, PT, R19, 0x64, PT ; /* 0x000000641300780c */
/* 0x000fe20003f46070 */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, R16 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0010 */
/*0270*/ IMAD.MOV.U32 R12, RZ, RZ, R17 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0011 */
/*0280*/ IMAD.MOV.U32 R13, RZ, RZ, R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000f */
/*0290*/ CS2R R16, SRZ ; /* 0x0000000000107805 */
/* 0x000fe2000001ff00 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fc400078e000e */
/*02b0*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*02c0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x004fda0003f04070 */
/*02e0*/ @P0 BRA 0x8f0 ; /* 0x0000060000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R0, P0, -R7, 0x3, RZ ; /* 0x0000000307007810 */
/* 0x000fe20007f1e1ff */
/*0300*/ IMAD.SHL.U32 R16, R11, 0x4, RZ ; /* 0x000000040b107824 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3 R18, R10, 0x1, RZ ; /* 0x000000010a127810 */
/* 0x000fe40007ffe0ff */
/*0320*/ SHF.R.U64 R15, R13, 0x2, R4.reuse ; /* 0x000000020d0f7819 */
/* 0x100fe20000001204 */
/*0330*/ IMAD.X R5, RZ, RZ, -0x1, P0 ; /* 0xffffffffff057424 */
/* 0x000fe200000e06ff */
/*0340*/ ISETP.GE.AND P0, PT, R18, c[0x0][0x168], PT ; /* 0x00005a0012007a0c */
/* 0x000fe40003f06270 */
/*0350*/ SHF.R.U32.HI R14, RZ, 0x2, R4 ; /* 0x00000002ff0e7819 */
/* 0x000fe40000011604 */
/*0360*/ SHF.L.U64.HI R5, R0, UR4, R5 ; /* 0x0000000400057c19 */
/* 0x000fc40008010205 */
/*0370*/ SHF.L.U32 R0, R0, UR4, RZ ; /* 0x0000000400007c19 */
/* 0x000fe400080006ff */
/*0380*/ SHF.L.U64.HI R17, R11, 0x2, R12 ; /* 0x000000020b117819 */
/* 0x000fe4000001020c */
/*0390*/ LOP3.LUT R16, R16, UR5, R7, 0x32, !PT ; /* 0x0000000510107c12 */
/* 0x000fe4000f8e3207 */
/*03a0*/ LOP3.LUT R15, R0, R15, RZ, 0xfc, !PT ; /* 0x0000000f000f7212 */
/* 0x000fe400078efcff */
/*03b0*/ LOP3.LUT R14, R5, R14, RZ, 0xfc, !PT ; /* 0x0000000e050e7212 */
/* 0x000fe400078efcff */
/*03c0*/ LOP3.LUT R17, R17, UR8, RZ, 0x30, !PT ; /* 0x0000000811117c12 */
/* 0x000fe2000f8e30ff */
/*03d0*/ @!P0 BRA 0x8f0 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R0, [R8.64+-0x8] ; /* 0xfffff80608007981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000806080a7981 */
/* 0x000ee2000c1e1b00 */
/*0400*/ ISETP.LT.U32.AND P0, PT, R16, R15, PT ; /* 0x0000000f1000720c */
/* 0x000fc80003f01070 */
/*0410*/ ISETP.LT.U32.AND.EX P0, PT, R17, R14, PT, P0 ; /* 0x0000000e1100720c */
/* 0x000fc80003f01100 */
/*0420*/ SEL R6, R16, R15, P0 ; /* 0x0000000f10067207 */
/* 0x000fe40000000000 */
/*0430*/ SEL R7, R17, R14, P0 ; /* 0x0000000e11077207 */
/* 0x000fe40000000000 */
/*0440*/ LOP3.LUT R13, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff0d7212 */
/* 0x000fe400078e33ff */
/*0450*/ LOP3.LUT R12, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0c7212 */
/* 0x000fe400078e33ff */
/*0460*/ LEA R13, P0, R6, R13, 0x15 ; /* 0x0000000d060d7211 */
/* 0x000fc8000780a8ff */
/*0470*/ LEA.HI.X R12, R6, R12, R7, 0x15, P0 ; /* 0x0000000c060c7211 */
/* 0x000fc800000fac07 */
/*0480*/ SHF.R.U32.HI R5, RZ, 0x18, R12.reuse ; /* 0x00000018ff057819 */
/* 0x100fe4000001160c */
/*0490*/ SHF.R.U64 R4, R13, 0x18, R12 ; /* 0x000000180d047819 */
/* 0x000fe4000000120c */
/*04a0*/ LOP3.LUT R5, R5, R12, RZ, 0x3c, !PT ; /* 0x0000000c05057212 */
/* 0x000fe400078e3cff */
/*04b0*/ LOP3.LUT R4, R4, R13, RZ, 0x3c, !PT ; /* 0x0000000d04047212 */
/* 0x000fc600078e3cff */
/*04c0*/ IMAD R13, R5, 0x109, RZ ; /* 0x00000109050d7824 */
/* 0x000fe400078e02ff */
/*04d0*/ IMAD.WIDE.U32 R4, R4, 0x109, RZ ; /* 0x0000010904047825 */
/* 0x000fc800078e00ff */
/*04e0*/ IMAD.IADD R12, R5, 0x1, R13 ; /* 0x00000001050c7824 */
/* 0x000fca00078e020d */
/*04f0*/ SHF.R.U32.HI R5, RZ, 0xe, R12.reuse ; /* 0x0000000eff057819 */
/* 0x100fe4000001160c */
/*0500*/ SHF.R.U64 R13, R4, 0xe, R12 ; /* 0x0000000e040d7819 */
/* 0x000fe4000000120c */
/*0510*/ LOP3.LUT R5, R5, R12, RZ, 0x3c, !PT ; /* 0x0000000c05057212 */
/* 0x000fe400078e3cff */
/*0520*/ LOP3.LUT R4, R13, R4, RZ, 0x3c, !PT ; /* 0x000000040d047212 */
/* 0x000fc600078e3cff */
/*0530*/ IMAD R13, R5, 0x15, RZ ; /* 0x00000015050d7824 */
/* 0x000fe400078e02ff */
/*0540*/ IMAD.WIDE.U32 R4, R4, 0x15, RZ ; /* 0x0000001504047825 */
/* 0x000fc800078e00ff */
/*0550*/ IMAD.IADD R5, R5, 0x1, R13 ; /* 0x0000000105057824 */
/* 0x000fca00078e020d */
/*0560*/ SHF.R.U64 R5, R4, 0x1c, R5 ; /* 0x0000001c04057819 */
/* 0x000fc80000001205 */
/*0570*/ LOP3.LUT R4, R5, R4, RZ, 0x3c, !PT ; /* 0x0000000405047212 */
/* 0x000fca00078e3cff */
/*0580*/ IMAD R4, R4, 0x1e3779b9, RZ ; /* 0x1e3779b904047824 */
/* 0x000fe200078e02ff */
/*0590*/ IADD3 R5, -R0, 0x20, RZ ; /* 0x0000002000057810 */
/* 0x004fc80007ffe1ff */
/*05a0*/ SHF.R.U32.HI R0, RZ, R5, R4 ; /* 0x00000005ff007219 */
/* 0x000fe40000011604 */
/*05b0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc6000001ff00 */
/*05c0*/ IMAD.WIDE.U32 R10, R0, 0x8, R10 ; /* 0x00000008000a7825 */
/* 0x008fca00078e000a */
/*05d0*/ ATOM.E.CAS.64.STRONG.GPU P0, R12, [R10], R4, R6 ; /* 0x000000040a0c738b */
/* 0x000ea2000010e506 */
/*05e0*/ BSSY B1, 0x670 ; /* 0x0000008000017945 */
/* 0x000fe20003800000 */
/*05f0*/ @P0 BRA 0x660 ; /* 0x0000006000000947 */
/* 0x004fea0003800000 */
/*0600*/ LD.E.64 R12, [R10] ; /* 0x000000000a0c7980 */
/* 0x000ea40000100b00 */
/*0610*/ ISETP.EQ.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x004fc80003f02070 */
/*0620*/ ISETP.EQ.U32.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fc80003f02100 */
/*0630*/ SEL R4, R6, R12, P0 ; /* 0x0000000c06047207 */
/* 0x000fe40000000000 */
/*0640*/ SEL R5, R7, R13, P0 ; /* 0x0000000d07057207 */
/* 0x000fca0000000000 */
/*0650*/ ST.E.64 [R10], R4 ; /* 0x000000000a007385 */
/* 0x0001e40000100b04 */
/*0660*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.NE.U32.AND P0, PT, R12.reuse, R6, PT ; /* 0x000000060c00720c */
/* 0x040fe20003f05070 */
/*0680*/ IMAD.MOV.U32 R22, RZ, RZ, R0 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0000 */
/*0690*/ ISETP.EQ.U32.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f22070 */
/*06a0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*06b0*/ ISETP.NE.AND.EX P0, PT, R13, R7, PT, P0 ; /* 0x000000070d00720c */
/* 0x000fc80003f05300 */
/*06c0*/ ISETP.EQ.OR.EX P0, PT, R13, RZ, !P0, P1 ; /* 0x000000ff0d00720c */
/* 0x000fda0004702710 */
/*06d0*/ @P0 BRA 0x8a0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*06e0*/ PRMT R4, RZ, 0x7610, R4 ; /* 0x00007610ff047816 */
/* 0x001fe20000000004 */
/*06f0*/ IMAD.MOV.U32 R22, RZ, RZ, R0 ; /* 0x000000ffff167224 */
/* 0x000fc600078e0000 */
/*0700*/ LOP3.LUT P0, RZ, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04ff7812 */
/* 0x000fe2000780c0ff */
/*0710*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fd80003800000 */
/*0720*/ @P0 BRA 0x8f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0730*/ LDG.E R4, [R8.64+-0x8] ; /* 0xfffff80608047981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000806080a7981 */
/* 0x000ee2000c1e1b00 */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fe200078e00ff */
/*0760*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fc80007ffe0ff */
/*0770*/ SHF.L.U32 R5, R5, R4, RZ ; /* 0x0000000405057219 */
/* 0x004fc800000006ff */
/*0780*/ LOP3.LUT R22, R22, R5, RZ, 0x30, !PT ; /* 0x0000000516167212 */
/* 0x000fe400078e30ff */
/*0790*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc6000001ff00 */
/*07a0*/ IMAD.WIDE.U32 R10, R22, 0x8, R10 ; /* 0x00000008160a7825 */
/* 0x008fca00078e000a */
/*07b0*/ ATOM.E.CAS.64.STRONG.GPU P1, R12, [R10], R4, R6 ; /* 0x000000040a0c738b */
/* 0x000ea8000012e506 */
/*07c0*/ @!P1 LD.E.64 R12, [R10] ; /* 0x000000000a0c9980 */
/* 0x004ea20000100b00 */
/*07d0*/ ISETP.NE.AND P3, PT, R22, R0, PT ; /* 0x000000001600720c */
/* 0x000fe20003f65270 */
/*07e0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fc600078e00ff */
/*07f0*/ SEL R4, RZ, 0x1, P3 ; /* 0x00000001ff047807 */
/* 0x000fe40001800000 */
/*0800*/ @!P1 ISETP.EQ.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00920c */
/* 0x004fc80003f02070 */
/*0810*/ @!P1 ISETP.EQ.U32.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00920c */
/* 0x000fc80003f02100 */
/*0820*/ @!P1 SEL R20, R6, R12, P0 ; /* 0x0000000c06149207 */
/* 0x000fe40000000000 */
/*0830*/ @!P1 SEL R21, R7, R13, P0 ; /* 0x0000000d07159207 */
/* 0x000fe40000000000 */
/*0840*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc60003f05070 */
/*0850*/ @!P1 ST.E.64 [R10], R20 ; /* 0x000000000a009385 */
/* 0x0001e20000100b14 */
/*0860*/ ISETP.NE.U32.AND P1, PT, R12, R6, PT ; /* 0x000000060c00720c */
/* 0x000fe40003f25070 */
/*0870*/ ISETP.NE.AND.EX P0, PT, R13.reuse, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x040fe40003f05300 */
/*0880*/ ISETP.NE.AND.EX P1, PT, R13, R7, PT, P1 ; /* 0x000000070d00720c */
/* 0x000fda0003f25310 */
/*0890*/ @P1 BRA P0, 0x700 ; /* 0xfffffe6000001947 */
/* 0x001fea000003ffff */
/*08a0*/ LDG.E.64 R4, [R8.64+0x10] ; /* 0x0000100608047981 */
/* 0x001ea2000c1e1b00 */
/*08b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*08c0*/ LEA R4, P0, R22, R4, 0x2 ; /* 0x0000000416047211 */
/* 0x004fc800078010ff */
/*08d0*/ LEA.HI.X R5, R22, R5, R23, 0x2, P0 ; /* 0x0000000516057211 */
/* 0x000fca00000f1417 */
/*08e0*/ ATOM.E.ADD.STRONG.GPU PT, RZ, [R4.64], R7 ; /* 0x0000000704ff798a */
/* 0x0001e800081ee1c6 */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ @!P2 BRA 0x1b0 ; /* 0xfffff8a00000a947 */
/* 0x000fea000383ffff */
/*0910*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22kernel_count_seq_kmersP9HashTableiPPc
.globl _Z22kernel_count_seq_kmersP9HashTableiPPc
.p2align 8
.type _Z22kernel_count_seq_kmersP9HashTableiPPc,@function
_Z22kernel_count_seq_kmersP9HashTableiPPc:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x8
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s5, v1
s_cbranch_execz .LBB0_14
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_load_b32 s1, s[0:1], 0x8
s_mov_b32 s6, 0
s_mov_b32 s8, 0
v_mov_b32_e32 v7, 0
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_lshl_b32 s0, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], -1, s0
global_load_b64 v[4:5], v[0:1], off
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v14, 1
s_not_b64 s[4:5], s[4:5]
s_add_i32 s7, s0, -2
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s9
v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v13, v9
v_dual_mov_b32 v0, v10 :: v_dual_mov_b32 v1, v11
v_mov_b32_e32 v12, v8
s_add_i32 s8, s8, 1
s_cmpk_lg_i32 s8, 0x64
s_cbranch_scc0 .LBB0_14
.LBB0_4:
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, _ZL13seq_nt4_table@rel32@lo+4
s_addc_u32 s11, s11, _ZL13seq_nt4_table@rel32@hi+12
v_mov_b32_e32 v15, v7
s_mov_b32 s9, exec_lo
flat_load_u8 v3, v[8:9]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v3, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, v3, s10
v_add_co_ci_u32_e64 v9, null, 0, s11, s0
global_load_u8 v3, v[8:9], off
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
s_waitcnt vmcnt(0)
v_cmpx_gt_u16_e32 4, v3
s_cbranch_execz .LBB0_3
v_xor_b32_e32 v6, 3, v3
v_lshlrev_b64 v[8:9], 2, v[12:13]
v_mov_b32_e32 v11, s6
v_and_b32_e32 v3, 0xffff, v3
v_lshrrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v10, 0xffff, v6
v_add_nc_u32_e32 v15, 1, v2
v_and_b32_e32 v9, s5, v9
v_or_b32_e32 v3, v8, v3
s_mov_b32 s10, exec_lo
v_lshlrev_b64 v[10:11], s7, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v8, s4, v3
v_or_b32_e32 v11, v11, v1
s_delay_alu instid0(VALU_DEP_3)
v_or_b32_e32 v10, v10, v0
v_cmpx_le_i32_e64 s1, v15
s_cbranch_execz .LBB0_2
global_load_b32 v6, v7, s[2:3]
v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[10:11]
s_mov_b32 s12, 0
s_mov_b32 s11, 0
v_dual_cndmask_b32 v1, v11, v9 :: v_dual_cndmask_b32 v0, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_not_b32_e32 v13, v1
v_lshlrev_b64 v[2:3], 21, v[0:1]
v_not_b32_e32 v12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b64 v[12:13], 24, v[2:3]
v_xor_b32_e32 v2, v12, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, v13, v3
v_mad_u64_u32 v[16:17], null, v2, 0x109, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v17
v_mad_u64_u32 v[12:13], null, v3, 0x109, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v17, v12
v_lshrrev_b64 v[2:3], 14, v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v16
v_xor_b32_e32 v3, v3, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v2, 21, 0
v_mov_b32_e32 v2, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[16:17], null, v3, 21, v[2:3]
v_mov_b32_e32 v2, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v2, v2, v12, 28
v_xor_b32_e32 v2, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, 0x1e3779b9
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v3, 32, v6
v_lshrrev_b32_e32 v12, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v12
s_branch .LBB0_8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s14
s_xor_b32 s0, s0, -1
s_mov_b32 s12, s13
s_and_b32 s0, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s11, s0, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_2
.LBB0_8:
global_load_b64 v[16:17], v7, s[2:3] offset:16
v_lshlrev_b64 v[18:19], 3, v[6:7]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mov_b32_e32 v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v16, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v17, vcc_lo, v17, v19, vcc_lo
flat_atomic_cmpswap_b64 v[2:3], v[16:17], v[0:3] glc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, 0, v[2:3]
v_cmp_ne_u64_e64 s0, v[2:3], v[0:1]
s_and_b32 s14, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_12
s_xor_b32 s16, s12, -1
s_mov_b32 s0, 0
s_mov_b32 s15, s12
s_and_saveexec_b32 s13, s16
s_cbranch_execz .LBB0_11
global_load_b32 v2, v7, s[2:3]
v_add_nc_u32_e32 v3, 1, v6
s_and_not1_b32 s15, s12, exec_lo
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_u32 v6, v3, 0, v2
v_cmp_eq_u32_e32 vcc_lo, v6, v12
s_and_b32 s16, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s15, s15, s16
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_and_b32 s13, s15, exec_lo
.LBB0_12:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_7
global_load_b64 v[2:3], v7, s[2:3] offset:24
v_lshlrev_b64 v[16:17], 2, v[6:7]
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s12, s12, exec_lo
s_and_not1_b32 s0, s0, exec_lo
s_or_b32 s13, s13, s12
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, v16
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
flat_atomic_add_u32 v[2:3], v14
s_branch .LBB0_7
.LBB0_14:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22kernel_count_seq_kmersP9HashTableiPPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22kernel_count_seq_kmersP9HashTableiPPc, .Lfunc_end0-_Z22kernel_count_seq_kmersP9HashTableiPPc
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17kernel_print_histPK9HashTablePj
.globl _Z17kernel_print_histPK9HashTablePj
.p2align 8
.type _Z17kernel_print_histPK9HashTablePj,@function
_Z17kernel_print_histPK9HashTablePj:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_load_b32 s5, s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_lshrrev_b32_e32 v0, s5, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[2:3], s[2:3], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
flat_load_b32 v0, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x8
v_min_u32_e32 v0, 0xff, v0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v1, 1 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_print_histPK9HashTablePj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17kernel_print_histPK9HashTablePj, .Lfunc_end1-_Z17kernel_print_histPK9HashTablePj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type _ZL13seq_nt4_table,@object
.section .rodata,"a",@progbits
.p2align 4, 0x0
_ZL13seq_nt4_table:
.ascii "\000\001\002\003\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\000\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004\004\000\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.size _ZL13seq_nt4_table, 256
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22kernel_count_seq_kmersP9HashTableiPPc
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z22kernel_count_seq_kmersP9HashTableiPPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_print_histPK9HashTablePj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_print_histPK9HashTablePj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169cf9_00000000-6_cuda-slow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2457:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2457:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11hash_uint64y
.type _Z11hash_uint64y, @function
_Z11hash_uint64y:
.LFB2448:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2448:
.size _Z11hash_uint64y, .-_Z11hash_uint64y
.globl _Z14HashTable_initjj
.type _Z14HashTable_initjj, @function
_Z14HashTable_initjj:
.LFB2449:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movl %esi, %ebp
movl $32, %esi
movl $1, %edi
call calloc@PLT
movl %ebp, 8(%rax)
movl %ebx, (%rax)
movl $0, 4(%rax)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2449:
.size _Z14HashTable_initjj, .-_Z14HashTable_initjj
.globl _Z17HashTable_destoryP9HashTable
.type _Z17HashTable_destoryP9HashTable, @function
_Z17HashTable_destoryP9HashTable:
.LFB2450:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L10
subq $8, %rsp
.cfi_def_cfa_offset 16
call free@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L10:
ret
.cfi_endproc
.LFE2450:
.size _Z17HashTable_destoryP9HashTable, .-_Z17HashTable_destoryP9HashTable
.globl _Z3h2bjj
.type _Z3h2bjj, @function
_Z3h2bjj:
.LFB2451:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2451:
.size _Z3h2bjj, .-_Z3h2bjj
.globl _Z11hash_insertP9HashTabley
.type _Z11hash_insertP9HashTabley, @function
_Z11hash_insertP9HashTabley:
.LFB2452:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2452:
.size _Z11hash_insertP9HashTabley, .-_Z11hash_insertP9HashTabley
.globl _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
.type _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc, @function
_Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc:
.LFB2479:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22kernel_count_seq_kmersP9HashTableiPPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2479:
.size _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc, .-_Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
.globl _Z22kernel_count_seq_kmersP9HashTableiPPc
.type _Z22kernel_count_seq_kmersP9HashTableiPPc, @function
_Z22kernel_count_seq_kmersP9HashTableiPPc:
.LFB2480:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2480:
.size _Z22kernel_count_seq_kmersP9HashTableiPPc, .-_Z22kernel_count_seq_kmersP9HashTableiPPc
.globl _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
.type _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj, @function
_Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj:
.LFB2481:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17kernel_print_histPK9HashTablePj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2481:
.size _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj, .-_Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
.globl _Z17kernel_print_histPK9HashTablePj
.type _Z17kernel_print_histPK9HashTablePj, @function
_Z17kernel_print_histPK9HashTablePj:
.LFB2482:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2482:
.size _Z17kernel_print_histPK9HashTablePj, .-_Z17kernel_print_histPK9HashTablePj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d\n"
.LC2:
.string "%s"
.LC3:
.string "total reads: %d\n"
.LC6:
.string "GPU time: %fs\n"
.LC7:
.string "COUNT: %d\n\n"
.LC8:
.string "%d\t%d\n"
.text
.type _ZL10count_filePKcij, @function
_ZL10count_filePKcij:
.LFB2453:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1192, %rsp
.cfi_def_cfa_offset 1248
movl %esi, 44(%rsp)
movl %edx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 1176(%rsp)
xorl %eax, %eax
movl $1, %eax
movl %edx, %ecx
sall %cl, %eax
movl %eax, 40(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L59
movq %rax, %r12
movl $0, %r15d
movq $0, (%rsp)
movl $0, %esi
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
movq %r12, 8(%rsp)
movl %esi, %r12d
jmp .L34
.L59:
movl $1, %edi
call exit@PLT
.L51:
movq %rbx, %r15
.L35:
movq %rbx, (%rsp)
.L34:
leaq 72(%rsp), %rdi
movq 8(%rsp), %rcx
movl $10, %edx
movq 16(%rsp), %rsi
call __getdelim@PLT
movq %rax, %rbp
cmpq $-1, %rax
je .L60
addl $1, %r12d
movl $24, %edi
call malloc@PLT
movq %rax, %rbx
movq 72(%rsp), %r14
movq %r14, %rdi
call strlen@PLT
movq %rax, %r13
movq %rax, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq %r13, %rdx
movq %r14, %rsi
call __strcpy_chk@PLT
movl %ebp, 8(%rbx)
movq $0, 16(%rbx)
testq %r15, %r15
je .L51
movq (%rsp), %rax
movq %rbx, 16(%rax)
jmp .L35
.L60:
movl %r12d, (%rsp)
movq 8(%rsp), %r12
movq %r12, %rdi
call fclose@PLT
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .L37
call free@PLT
.L37:
movl (%rsp), %ebx
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
testq %r15, %r15
je .L38
movq %r15, %rbx
movl $0, %ebp
leaq .LC2(%rip), %r14
.L39:
movl 8(%rbx), %r12d
movq %r12, %rdi
call malloc@PLT
movq %rax, %rdi
movl %ebp, %eax
movq %rdi, 0(%r13,%rax,8)
movq (%rbx), %r8
movq %r14, %rcx
movq %r12, %rdx
movl $2, %esi
movl $0, %eax
call __sprintf_chk@PLT
addl $1, %ebp
movq 16(%rbx), %rbx
testq %rbx, %rbx
jne .L39
.L38:
movl (%rsp), %r12d
movl %r12d, %esi
movl 24(%rsp), %edi
call _Z14HashTable_initjj
movq %rax, %r14
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl 40(%rsp), %ebx
leaq 0(,%rbx,8), %rbp
movq %rbp, 24(%rsp)
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
salq $2, %rbx
movq %rbx, 32(%rsp)
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
movq %rbp, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movl $0, %esi
movq 96(%rsp), %rdi
call cudaMemset@PLT
movl $1024, %edx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movq 88(%rsp), %rax
movq %rax, 16(%r14)
movq 96(%rsp), %rax
movq %rax, 24(%r14)
movl $1, %ecx
movl $32, %edx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call malloc@PLT
movq %rax, %rbx
movq %rax, 16(%rsp)
testl %r12d, %r12d
je .L40
movq %rax, %rbp
movq 8(%rsp), %rax
leaq (%rax,%rbx), %r12
.L41:
movl 8(%r15), %esi
movq %rbx, %rdi
call cudaMalloc@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L41
leaq 56(%rsp), %rdi
movq 8(%rsp), %r12
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
addq %r13, %r12
.L42:
movl 8(%r15), %edx
movq (%rbx), %rsi
movq 0(%rbp), %rdi
movl $1, %ecx
call cudaMemcpy@PLT
addq $8, %rbx
addq $8, %rbp
cmpq %rbx, %r12
jne .L42
.L48:
movq 16(%rsp), %rdi
call free@PLT
movl (%rsp), %ebx
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl %ebx, %eax
shrl $10, %eax
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L43:
call cudaDeviceSynchronize@PLT
movl $1024, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl 40(%rsp), %eax
shrl $10, %eax
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L44:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
movq 112(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 132(%rsp)
leaq 132(%rsp), %rdi
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 132(%rsp), %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $32, %edx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 16(%r14), %rdi
movl $2, %ecx
movq 24(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%r14), %rdi
movl $2, %ecx
movq 32(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaMemcpy@PLT
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%r14), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC8(%rip), %rbp
.L45:
movl 144(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L45
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
testq %r15, %r15
je .L46
movl $0, %ebx
.L47:
movq (%r15), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movl %ebx, %eax
movq 0(%r13,%rax,8), %rdi
call free@PLT
addl $1, %ebx
movq 16(%r15), %r15
testq %r15, %r15
jne .L47
.L46:
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call _Z17HashTable_destoryP9HashTable
movq 1176(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $1192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movq 56(%rsp), %rdx
movl 44(%rsp), %esi
movq 48(%rsp), %rdi
call _Z55__device_stub__Z22kernel_count_seq_kmersP9HashTableiPPcP9HashTableiPPc
jmp .L43
.L62:
movq 64(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z49__device_stub__Z17kernel_print_histPK9HashTablePjPK9HashTablePj
jmp .L44
.L40:
leaq 56(%rsp), %rdi
movl $0, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $0, %edx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L48
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2453:
.size _ZL10count_filePKcij, .-_ZL10count_filePKcij
.globl main
.type main, @function
main:
.LFB2454:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 24(%rbp), %rdi
movl %eax, %edx
movl %ebx, %esi
call _ZL10count_filePKcij
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2454:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "_Z17kernel_print_histPK9HashTablePj"
.align 8
.LC10:
.string "_Z22kernel_count_seq_kmersP9HashTableiPPc"
.section .rodata.str1.1
.LC11:
.string "seq_nt4_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2484:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_print_histPK9HashTablePj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kernel_count_seq_kmersP9HashTableiPPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13seq_nt4_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2484:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.align 32
.type _ZL13seq_nt4_table, @object
.size _ZL13seq_nt4_table, 256
_ZL13seq_nt4_table:
.string ""
.string "\001\002\003\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.string "\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\001\004\004\004\002\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\003\003\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004\004\004\004\004\004\004\004"
.ascii "\004\004\004\004\004\004\004\004"
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-slow.hip"
.globl _Z14HashTable_initjj # -- Begin function _Z14HashTable_initjj
.p2align 4, 0x90
.type _Z14HashTable_initjj,@function
_Z14HashTable_initjj: # @_Z14HashTable_initjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movl $1, %edi
movl $32, %esi
callq calloc
movl %ebx, 8(%rax)
movl %ebp, (%rax)
movl $0, 4(%rax)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z14HashTable_initjj, .Lfunc_end0-_Z14HashTable_initjj
.cfi_endproc
# -- End function
.globl _Z17HashTable_destoryP9HashTable # -- Begin function _Z17HashTable_destoryP9HashTable
.p2align 4, 0x90
.type _Z17HashTable_destoryP9HashTable,@function
_Z17HashTable_destoryP9HashTable: # @_Z17HashTable_destoryP9HashTable
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
jne free # TAILCALL
# %bb.1:
retq
.Lfunc_end1:
.size _Z17HashTable_destoryP9HashTable, .Lfunc_end1-_Z17HashTable_destoryP9HashTable
.cfi_endproc
# -- End function
.globl _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc # -- Begin function _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.p2align 4, 0x90
.type _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc,@function
_Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc: # @_Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22kernel_count_seq_kmersP9HashTableiPPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc, .Lfunc_end2-_Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.cfi_endproc
# -- End function
.globl _Z32__device_stub__kernel_print_histPK9HashTablePj # -- Begin function _Z32__device_stub__kernel_print_histPK9HashTablePj
.p2align 4, 0x90
.type _Z32__device_stub__kernel_print_histPK9HashTablePj,@function
_Z32__device_stub__kernel_print_histPK9HashTablePj: # @_Z32__device_stub__kernel_print_histPK9HashTablePj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17kernel_print_histPK9HashTablePj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z32__device_stub__kernel_print_histPK9HashTablePj, .Lfunc_end3-_Z32__device_stub__kernel_print_histPK9HashTablePj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1240, %rsp # imm = 0x4D8
.cfi_def_cfa_offset 1296
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $1, %eax
movl %r15d, %ecx
shll %cl, %eax
movq %rax, 160(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
movq $0, 72(%rsp)
movq $0, 176(%rsp)
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB4_3
# %bb.1: # %.preheader.i
movq %r15, 88(%rsp) # 8-byte Spill
movq %r14, 184(%rsp) # 8-byte Spill
leaq 72(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $10, %edx
movq %rax, 48(%rsp) # 8-byte Spill
movq %rax, %rcx
callq __getdelim
cmpq $-1, %rax
je .LBB4_2
# %bb.4: # %.lr.ph.i.preheader
movq %rax, %r13
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %r14d, %r14d
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_5 Depth=1
leaq 72(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $10, %edx
movq 48(%rsp), %rcx # 8-byte Reload
callq __getdelim
movq %rax, %r13
movq 8(%rsp), %rax # 8-byte Reload
incl %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq %rbx, %r12
movq %rbp, %r14
cmpq $-1, %r13
je .LBB4_8
.LBB4_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $24, %edi
callq malloc
movq %rax, %rbx
movq 72(%rsp), %r15
movq %r15, %rdi
callq strlen
movq %rax, %rdi
callq malloc
movq %rax, (%rbx)
movq %rax, %rdi
movq %r15, %rsi
callq strcpy
movl %r13d, 8(%rbx)
movq $0, 16(%rbx)
movq %rbx, %rbp
testq %r14, %r14
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_5 Depth=1
movq %rbx, 16(%r12)
movq %r14, %rbp
jmp .LBB4_7
.LBB4_2:
xorl %ebp, %ebp
.LBB4_8: # %._crit_edge.i
movq 48(%rsp), %rdi # 8-byte Reload
callq fclose
movq 72(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_10
# %bb.9:
callq free
.LBB4_10:
xorl %r12d, %r12d
movl $.L.str.1, %edi
movq 8(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, %eax
movq %rax, 192(%rsp) # 8-byte Spill
leaq (,%rax,8), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
testq %rbp, %rbp
je .LBB4_13
# %bb.11: # %.lr.ph129.i.preheader
movq %rbp, %r15
.p2align 4, 0x90
.LBB4_12: # %.lr.ph129.i
# =>This Inner Loop Header: Depth=1
movl 8(%r15), %edi
callq malloc
movl %r12d, %ecx
movq %rax, (%r14,%rcx,8)
movq (%r15), %rsi
movq %rax, %rdi
callq strcpy
incl %r12d
movq 16(%r15), %r15
testq %r15, %r15
jne .LBB4_12
.LBB4_13: # %._crit_edge130.i
movl $1, %edi
movl $32, %esi
callq calloc
movq %rax, %r15
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 8(%r15)
movq 88(%rsp), %rax # 8-byte Reload
movl %eax, (%r15)
movl $0, 4(%r15)
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movl 160(%rsp), %r12d # 4-byte Reload
leaq (,%r12,8), %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
shlq $2, %r12
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 64(%rsp), %rdi
xorl %esi, %esi
movq %rbx, 200(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq hipMemset
movq 56(%rsp), %rdi
xorl %esi, %esi
movq %r12, 88(%rsp) # 8-byte Spill
movq %r12, %rdx
callq hipMemset
movq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
xorl %esi, %esi
callq hipMemset
movq 64(%rsp), %rax
movq %rax, 16(%r15)
movq 56(%rsp), %rax
movq %rax, 24(%r15)
movq 24(%rsp), %rdi
movl $32, %edx
movq %r15, 48(%rsp) # 8-byte Spill
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r13, %rdi
callq malloc
movq %rax, %r12
cmpl $0, 8(%rsp) # 4-byte Folded Reload
je .LBB4_19
# %bb.14: # %.lr.ph133.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_15: # =>This Inner Loop Header: Depth=1
leaq (%r12,%r15), %rdi
movl 8(%rbp), %esi
callq hipMalloc
addq $8, %r15
cmpq %r15, %r13
jne .LBB4_15
# %bb.16: # %._crit_edge134.i
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $0, 8(%rsp) # 4-byte Folded Reload
movq 192(%rsp), %rbx # 8-byte Reload
je .LBB4_20
# %bb.17: # %.lr.ph137.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_18: # =>This Inner Loop Header: Depth=1
movq (%r12,%r15,8), %rdi
movq (%r14,%r15,8), %rsi
movl 8(%rbp), %edx
movl $1, %ecx
callq hipMemcpy
incq %r15
cmpq %r15, %rbx
jne .LBB4_18
jmp .LBB4_20
.LBB4_19: # %._crit_edge138.i.critedge
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
.LBB4_20: # %._crit_edge138.i
movabsq $4294967296, %r13 # imm = 0x100000000
movq %r12, %rdi
callq free
movl $.L.str.3, %edi
movq 8(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 168(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 168(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
shrl $10, %ebx
orq %r13, %rbx
leaq 1024(%r13), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_22
# %bb.21:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 144(%rsp)
movq 184(%rsp), %rax # 8-byte Reload
movl %eax, 156(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 156(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rax
movq %rax, 224(%rsp)
leaq 32(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z22kernel_count_seq_kmersP9HashTableiPPc, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_22:
callq hipDeviceSynchronize
movq 160(%rsp), %rdi # 8-byte Reload
shrl $10, %edi
orq %r13, %rdi
addq $1024, %r13 # imm = 0x400
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 48(%rsp), %r15 # 8-byte Reload
jne .LBB4_24
# %bb.23:
movq 24(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z17kernel_print_histPK9HashTablePj, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_24:
callq hipDeviceSynchronize
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 168(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rsi
movl $32, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%r15), %rdi
movq 64(%rsp), %rsi
movq 200(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 24(%r15), %rdi
movq 56(%rsp), %rsi
movq 88(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 80(%rsp), %rsi
leaq 208(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movl 4(%r15), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $1, %r12d
.p2align 4, 0x90
.LBB4_25: # =>This Inner Loop Header: Depth=1
movl 208(%rsp,%r12,4), %edx
movl $.L.str.6, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $256, %r12 # imm = 0x100
jne .LBB4_25
# %bb.26:
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
testq %rbp, %rbp
je .LBB4_29
# %bb.27: # %.lr.ph144.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_28: # %.lr.ph144.i
# =>This Inner Loop Header: Depth=1
movq (%rbp), %rdi
callq free
movq %rbp, %rdi
callq free
movl %ebx, %eax
movq (%r14,%rax,8), %rdi
callq free
incl %ebx
movq 16(%rbp), %rbp
testq %rbp, %rbp
jne .LBB4_28
.LBB4_29: # %_ZL10count_filePKcij.exit
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1240, %rsp # imm = 0x4D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_3:
.cfi_def_cfa_offset 1296
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22kernel_count_seq_kmersP9HashTableiPPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_print_histPK9HashTablePj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22kernel_count_seq_kmersP9HashTableiPPc,@object # @_Z22kernel_count_seq_kmersP9HashTableiPPc
.section .rodata,"a",@progbits
.globl _Z22kernel_count_seq_kmersP9HashTableiPPc
.p2align 3, 0x0
_Z22kernel_count_seq_kmersP9HashTableiPPc:
.quad _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.size _Z22kernel_count_seq_kmersP9HashTableiPPc, 8
.type _Z17kernel_print_histPK9HashTablePj,@object # @_Z17kernel_print_histPK9HashTablePj
.globl _Z17kernel_print_histPK9HashTablePj
.p2align 3, 0x0
_Z17kernel_print_histPK9HashTablePj:
.quad _Z32__device_stub__kernel_print_histPK9HashTablePj
.size _Z17kernel_print_histPK9HashTablePj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "total reads: %d\n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU time: %fs\n"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "COUNT: %d\n\n"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d\t%d\n"
.size .L.str.6, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22kernel_count_seq_kmersP9HashTableiPPc"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17kernel_print_histPK9HashTablePj"
.size .L__unnamed_2, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__kernel_count_seq_kmersP9HashTableiPPc
.addrsig_sym _Z32__device_stub__kernel_print_histPK9HashTablePj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22kernel_count_seq_kmersP9HashTableiPPc
.addrsig_sym _Z17kernel_print_histPK9HashTablePj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
#include<math.h>
#include<float.h>
#define CUDA_CALL(x) do { cudaError_t err=(x); \
if(err!=cudaSuccess) { \
printf("Error %s at %s: %d",cudaGetErrorString(err),__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define W 64 // Input DIM
#define D 3 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define TILE_W 8 //input tile width
#define n1 3 //Range for weights(log2) from INQ
#define n2 1 //where n1 > n2
#define BAND 3 // range for weights
#define STRIDE_LENGTH 1 //STRIDE_LENGTH
#define OWS (W- T + 1) // Output DIM
#define OW (((W - T)/STRIDE_LENGTH) + 1) //output width
__global__ void cudaConvolve(float* output, int* kernel, unsigned char *matrix){
/*
one block loads its required tile from the matrix collaboritively
and calculates the values for the number of kernels equalling to blockdim.x
*/
__shared__ float shmatrix[TILE_W+T-1][TILE_W+T-1][D];
__shared__ int shkernel[D][T][T][D][2];
float Sum[BAND];
float ds=0.0;
long i=0,j=0,k=0,m=0;
long ty = threadIdx.y;
long tx = threadIdx.x;
long tz = threadIdx.z;
long z = blockIdx.z*TILE_W+tz;
long y = blockIdx.y*TILE_W+ty;
long x = blockIdx.x*blockDim.x + tx;
//kernel contains the abs log of weight and the sign
if (ty<T && tz<T){
for(k=0;k<D;++k){
shkernel[k][tz][ty][tx][0] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx];
shkernel[k][tz][ty][tx][1] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx+1];
}
}
__syncthreads();
if ( z>=0 && z <W && y>=0 && y <W){
shmatrix[tz][ty][tx] = matrix[z*D*W + y* D+ tx];
}
else
shmatrix[tz][ty][tx] = 0.0f;
__syncthreads();
//sum array stores the sum of matrix element sharing the same weights
for(m=0;m<BAND;m++){
Sum[m]=0.0;
}
if(y%STRIDE_LENGTH == 0 && z%STRIDE_LENGTH == 0){
if (ty<TILE_W && tz<TILE_W){
for(k=0;k<D;++k){
for(i=0;i<T;++i){
for(j=0;j<T;++j){
if(shkernel[tx][i][j][k][1] > 0){
Sum[shkernel[tx][i][j][k][0] - n2] += shmatrix[i+tz][ty+j][k];
}
if(shkernel[tx][i][j][k][1] < 0){
Sum[shkernel[tx][i][j][k][0] - n2] -= shmatrix[i+tz][ty+j][k];
}
}
}
}
}
for(m=0;m<BAND;m++){
if(m + n2 > 0){
ds+=Sum[m]*(1<<(m + n2));
}
else{
ds+=Sum[m]/(1<<((-1)*(m + n2)));
}
}
__syncthreads();
if (z<OWS && y<OWS && ty<TILE_W && tz<TILE_W){
output[x*OW*OW + (z/STRIDE_LENGTH)*OW + (y/STRIDE_LENGTH)] = ds;
}
}
}
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(int *kernel){
int (*t)[T][T][D][2]=(int (*)[T][T][D][2])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l][0]=((i+j+T+D)%n1 + n2);
t[i][j][k][l][1]=(pow(-1,i+j));
}
}
}
}
}
void printtofile(float *m){
const char *fname = "GPU_TAST";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++){
for(unsigned k=0;k<OW;k++){
fprintf(f,"%4.4f ", mat[i][j][k]);
}
fprintf(f, "\n");
}
fprintf(f,"\n");
}
fclose(f);
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
int *kernel=(int*)malloc(sizeof(int)*T*T*D*N*2);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;
cudaMalloc(&Dmatrix,sizeof(unsigned char)*W*W*D);
int *Dkernel;
cudaMalloc(&Dkernel,sizeof(int)*N*T*T*D*2);
float *Doutput;
cudaMalloc(&Doutput,sizeof(float)*N*OW*OW);
cudaMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,cudaMemcpyHostToDevice);
cudaMemcpy(Dkernel, kernel, sizeof(int)*T*T*D*N*2,cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
//Kernel Call
dim3 threads(D,TILE_W+T-1,TILE_W+T-1);
dim3 blocks(N/D, (W+TILE_W-1)/TILE_W , (W+TILE_W-1)/TILE_W );
cudaConvolve<<< blocks, threads >>>(Doutput, Dkernel, Dmatrix);
CUDA_CALL(cudaGetLastError());
cudaDeviceSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
cudaMemcpy(output, Doutput, sizeof(float)*N*OW*OW,cudaMemcpyDeviceToHost);
//printtofile(output);
} | .file "tmpxft_001208e6_00000000-6_stridedConvolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fillMatrixPh
.type _Z10fillMatrixPh, @function
_Z10fillMatrixPh:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbp
movl $0, %r12d
movl $0, %ebx
jmp .L4
.L11:
addl $1, %edi
addl %r11d, %r9d
addq $3, %rsi
cmpl $64, %edi
je .L6
.L8:
leal (%r10,%rdi), %r8d
movl %r9d, %edx
movl $0, %ecx
.L5:
movslq %edx, %rax
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %r13d
sarl $31, %r13d
subl %r13d, %eax
movl %eax, %r13d
sall $8, %r13d
subl %eax, %r13d
movl %edx, %eax
subl %r13d, %eax
movb %al, (%rsi,%rcx)
addq $1, %rcx
addl %r8d, %edx
cmpq $3, %rcx
jne .L5
jmp .L11
.L6:
addl $1, %ebx
addl $2, %r12d
addq $192, %rbp
cmpl $64, %ebx
je .L3
.L4:
leal 3(%rbx), %r11d
movq %rbp, %rsi
movl %r12d, %r9d
movl $0, %edi
leal 4(%rbx), %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10fillMatrixPh, .-_Z10fillMatrixPh
.globl _Z10fillKernelPi
.type _Z10fillKernelPi, @function
_Z10fillKernelPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, (%rsp)
movl $0, 12(%rsp)
jmp .L13
.L22:
addq $24, %r13
cmpq %r14, %r13
je .L15
.L17:
movq %r13, %rbx
movl $3, %ebp
.L14:
movl %r12d, (%rbx)
pxor %xmm1, %xmm1
cvtsi2sdl 8(%rsp), %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, 4(%rbx)
addq $8, %rbx
subl $1, %ebp
jne .L14
jmp .L22
.L15:
addl $1, %r15d
addq $120, %r14
movq (%rsp), %rax
addq $720, %rax
cmpq %rax, %r14
je .L16
.L19:
movl %r15d, 8(%rsp)
leal 8(%r15), %r12d
movslq %r12d, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %r12d, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
subl %eax, %r12d
addl $1, %r12d
leaq -120(%r14), %r13
jmp .L17
.L16:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
addq $600, (%rsp)
cmpl $128, %eax
je .L12
.L13:
movl 12(%rsp), %r15d
movq (%rsp), %rax
leaq 120(%rax), %r14
jmp .L19
.L12:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10fillKernelPi, .-_Z10fillKernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "w"
.LC2:
.string "GPU_TAST"
.LC3:
.string "%4.4f "
.LC4:
.string "\n"
.text
.globl _Z11printtofilePf
.type _Z11printtofilePf, @function
_Z11printtofilePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbx, (%rsp)
leaq 1843200(%rbx), %rax
movq %rax, 8(%rsp)
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
jmp .L24
.L26:
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $14400, (%rsp)
movq (%rsp), %rax
movq 8(%rsp), %rcx
cmpq %rcx, %rax
je .L27
.L24:
movq (%rsp), %rax
leaq 240(%rax), %rbp
leaq 14640(%rax), %r15
.L28:
leaq -240(%rbp), %rbx
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L25
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $240, %rbp
cmpq %r15, %rbp
jne .L28
jmp .L26
.L27:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11printtofilePf, .-_Z11printtofilePf
.globl _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
.type _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh, @function
_Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cudaConvolvePfPiPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh, .-_Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
.globl _Z12cudaConvolvePfPiPh
.type _Z12cudaConvolvePfPiPh, @function
_Z12cudaConvolvePfPiPh:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12cudaConvolvePfPiPh, .-_Z12cudaConvolvePfPiPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/MohammedKhandwawala/INQ-GPU-Convolution/master/codes/stridedConvolution.cu"
.section .rodata.str1.1
.LC7:
.string "Error %s at %s: %d"
.LC8:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $12288, %edi
call malloc@PLT
movq %rax, %rbp
movl $76800, %edi
call malloc@PLT
movq %rax, %rbx
movl $1843200, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z10fillMatrixPh
movq %rbx, %rdi
call _Z10fillKernelPi
leaq 8(%rsp), %rdi
movl $12288, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $76800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1843200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $12288, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $76800, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 4(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $3, 48(%rsp)
movl $12, 52(%rsp)
movl $42, 60(%rsp)
movl $8, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $12, %ecx
movq 60(%rsp), %rdi
movl $8, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L40:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L46
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $1843200, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L39:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L47
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
jmp .L40
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $194, %r8d
leaq .LC6(%rip), %rcx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L39
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12cudaConvolvePfPiPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cudaConvolvePfPiPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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