system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
#include<math.h>
#include<float.h>
#define CUDA_CALL(x) do { cudaError_t err=(x); \
if(err!=cudaSuccess) { \
printf("Error %s at %s: %d",cudaGetErrorString(err),__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define W 64 // Input DIM
#define D 3 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define TILE_W 8 //input tile width
#define n1 3 //Range for weights(log2) from INQ
#define n2 1 //where n1 > n2
#define BAND 3 // range for weights
#define STRIDE_LENGTH 1 //STRIDE_LENGTH
#define OWS (W- T + 1) // Output DIM
#define OW (((W - T)/STRIDE_LENGTH) + 1) //output width
__global__ void cudaConvolve(float* output, int* kernel, unsigned char *matrix){
/*
one block loads its required tile from the matrix collaboritively
and calculates the values for the number of kernels equalling to blockdim.x
*/
__shared__ float shmatrix[TILE_W+T-1][TILE_W+T-1][D];
__shared__ int shkernel[D][T][T][D][2];
float Sum[BAND];
float ds=0.0;
long i=0,j=0,k=0,m=0;
long ty = threadIdx.y;
long tx = threadIdx.x;
long tz = threadIdx.z;
long z = blockIdx.z*TILE_W+tz;
long y = blockIdx.y*TILE_W+ty;
long x = blockIdx.x*blockDim.x + tx;
//kernel contains the abs log of weight and the sign
if (ty<T && tz<T){
for(k=0;k<D;++k){
shkernel[k][tz][ty][tx][0] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx];
shkernel[k][tz][ty][tx][1] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx+1];
}
}
__syncthreads();
if ( z>=0 && z <W && y>=0 && y <W){
shmatrix[tz][ty][tx] = matrix[z*D*W + y* D+ tx];
}
else
shmatrix[tz][ty][tx] = 0.0f;
__syncthreads();
//sum array stores the sum of matrix element sharing the same weights
for(m=0;m<BAND;m++){
Sum[m]=0.0;
}
if(y%STRIDE_LENGTH == 0 && z%STRIDE_LENGTH == 0){
if (ty<TILE_W && tz<TILE_W){
for(k=0;k<D;++k){
for(i=0;i<T;++i){
for(j=0;j<T;++j){
if(shkernel[tx][i][j][k][1] > 0){
Sum[shkernel[tx][i][j][k][0] - n2] += shmatrix[i+tz][ty+j][k];
}
if(shkernel[tx][i][j][k][1] < 0){
Sum[shkernel[tx][i][j][k][0] - n2] -= shmatrix[i+tz][ty+j][k];
}
}
}
}
}
for(m=0;m<BAND;m++){
if(m + n2 > 0){
ds+=Sum[m]*(1<<(m + n2));
}
else{
ds+=Sum[m]/(1<<((-1)*(m + n2)));
}
}
__syncthreads();
if (z<OWS && y<OWS && ty<TILE_W && tz<TILE_W){
output[x*OW*OW + (z/STRIDE_LENGTH)*OW + (y/STRIDE_LENGTH)] = ds;
}
}
}
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(int *kernel){
int (*t)[T][T][D][2]=(int (*)[T][T][D][2])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l][0]=((i+j+T+D)%n1 + n2);
t[i][j][k][l][1]=(pow(-1,i+j));
}
}
}
}
}
void printtofile(float *m){
const char *fname = "GPU_TAST";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++){
for(unsigned k=0;k<OW;k++){
fprintf(f,"%4.4f ", mat[i][j][k]);
}
fprintf(f, "\n");
}
fprintf(f,"\n");
}
fclose(f);
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
int *kernel=(int*)malloc(sizeof(int)*T*T*D*N*2);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;
cudaMalloc(&Dmatrix,sizeof(unsigned char)*W*W*D);
int *Dkernel;
cudaMalloc(&Dkernel,sizeof(int)*N*T*T*D*2);
float *Doutput;
cudaMalloc(&Doutput,sizeof(float)*N*OW*OW);
cudaMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,cudaMemcpyHostToDevice);
cudaMemcpy(Dkernel, kernel, sizeof(int)*T*T*D*N*2,cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float milliseconds = 0;
cudaEventRecord(start,0);
//Kernel Call
dim3 threads(D,TILE_W+T-1,TILE_W+T-1);
dim3 blocks(N/D, (W+TILE_W-1)/TILE_W , (W+TILE_W-1)/TILE_W );
cudaConvolve<<< blocks, threads >>>(Doutput, Dkernel, Dmatrix);
CUDA_CALL(cudaGetLastError());
cudaDeviceSynchronize();
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
cudaMemcpy(output, Doutput, sizeof(float)*N*OW*OW,cudaMemcpyDeviceToHost);
//printtofile(output);
} | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#include<float.h>
#define CUDA_CALL(x) do { hipError_t err=(x); \
if(err!=hipSuccess) { \
printf("Error %s at %s: %d",hipGetErrorString(err),__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define W 64 // Input DIM
#define D 3 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define TILE_W 8 //input tile width
#define n1 3 //Range for weights(log2) from INQ
#define n2 1 //where n1 > n2
#define BAND 3 // range for weights
#define STRIDE_LENGTH 1 //STRIDE_LENGTH
#define OWS (W- T + 1) // Output DIM
#define OW (((W - T)/STRIDE_LENGTH) + 1) //output width
__global__ void cudaConvolve(float* output, int* kernel, unsigned char *matrix){
/*
one block loads its required tile from the matrix collaboritively
and calculates the values for the number of kernels equalling to blockdim.x
*/
__shared__ float shmatrix[TILE_W+T-1][TILE_W+T-1][D];
__shared__ int shkernel[D][T][T][D][2];
float Sum[BAND];
float ds=0.0;
long i=0,j=0,k=0,m=0;
long ty = threadIdx.y;
long tx = threadIdx.x;
long tz = threadIdx.z;
long z = blockIdx.z*TILE_W+tz;
long y = blockIdx.y*TILE_W+ty;
long x = blockIdx.x*blockDim.x + tx;
//kernel contains the abs log of weight and the sign
if (ty<T && tz<T){
for(k=0;k<D;++k){
shkernel[k][tz][ty][tx][0] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx];
shkernel[k][tz][ty][tx][1] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx+1];
}
}
__syncthreads();
if ( z>=0 && z <W && y>=0 && y <W){
shmatrix[tz][ty][tx] = matrix[z*D*W + y* D+ tx];
}
else
shmatrix[tz][ty][tx] = 0.0f;
__syncthreads();
//sum array stores the sum of matrix element sharing the same weights
for(m=0;m<BAND;m++){
Sum[m]=0.0;
}
if(y%STRIDE_LENGTH == 0 && z%STRIDE_LENGTH == 0){
if (ty<TILE_W && tz<TILE_W){
for(k=0;k<D;++k){
for(i=0;i<T;++i){
for(j=0;j<T;++j){
if(shkernel[tx][i][j][k][1] > 0){
Sum[shkernel[tx][i][j][k][0] - n2] += shmatrix[i+tz][ty+j][k];
}
if(shkernel[tx][i][j][k][1] < 0){
Sum[shkernel[tx][i][j][k][0] - n2] -= shmatrix[i+tz][ty+j][k];
}
}
}
}
}
for(m=0;m<BAND;m++){
if(m + n2 > 0){
ds+=Sum[m]*(1<<(m + n2));
}
else{
ds+=Sum[m]/(1<<((-1)*(m + n2)));
}
}
__syncthreads();
if (z<OWS && y<OWS && ty<TILE_W && tz<TILE_W){
output[x*OW*OW + (z/STRIDE_LENGTH)*OW + (y/STRIDE_LENGTH)] = ds;
}
}
}
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(int *kernel){
int (*t)[T][T][D][2]=(int (*)[T][T][D][2])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l][0]=((i+j+T+D)%n1 + n2);
t[i][j][k][l][1]=(pow(-1,i+j));
}
}
}
}
}
void printtofile(float *m){
const char *fname = "GPU_TAST";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++){
for(unsigned k=0;k<OW;k++){
fprintf(f,"%4.4f ", mat[i][j][k]);
}
fprintf(f, "\n");
}
fprintf(f,"\n");
}
fclose(f);
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
int *kernel=(int*)malloc(sizeof(int)*T*T*D*N*2);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;
hipMalloc(&Dmatrix,sizeof(unsigned char)*W*W*D);
int *Dkernel;
hipMalloc(&Dkernel,sizeof(int)*N*T*T*D*2);
float *Doutput;
hipMalloc(&Doutput,sizeof(float)*N*OW*OW);
hipMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,hipMemcpyHostToDevice);
hipMemcpy(Dkernel, kernel, sizeof(int)*T*T*D*N*2,hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
//Kernel Call
dim3 threads(D,TILE_W+T-1,TILE_W+T-1);
dim3 blocks(N/D, (W+TILE_W-1)/TILE_W , (W+TILE_W-1)/TILE_W );
cudaConvolve<<< blocks, threads >>>(Doutput, Dkernel, Dmatrix);
CUDA_CALL(hipGetLastError());
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
hipMemcpy(output, Doutput, sizeof(float)*N*OW*OW,hipMemcpyDeviceToHost);
//printtofile(output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#include<float.h>
#define CUDA_CALL(x) do { hipError_t err=(x); \
if(err!=hipSuccess) { \
printf("Error %s at %s: %d",hipGetErrorString(err),__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define W 64 // Input DIM
#define D 3 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define TILE_W 8 //input tile width
#define n1 3 //Range for weights(log2) from INQ
#define n2 1 //where n1 > n2
#define BAND 3 // range for weights
#define STRIDE_LENGTH 1 //STRIDE_LENGTH
#define OWS (W- T + 1) // Output DIM
#define OW (((W - T)/STRIDE_LENGTH) + 1) //output width
__global__ void cudaConvolve(float* output, int* kernel, unsigned char *matrix){
/*
one block loads its required tile from the matrix collaboritively
and calculates the values for the number of kernels equalling to blockdim.x
*/
__shared__ float shmatrix[TILE_W+T-1][TILE_W+T-1][D];
__shared__ int shkernel[D][T][T][D][2];
float Sum[BAND];
float ds=0.0;
long i=0,j=0,k=0,m=0;
long ty = threadIdx.y;
long tx = threadIdx.x;
long tz = threadIdx.z;
long z = blockIdx.z*TILE_W+tz;
long y = blockIdx.y*TILE_W+ty;
long x = blockIdx.x*blockDim.x + tx;
//kernel contains the abs log of weight and the sign
if (ty<T && tz<T){
for(k=0;k<D;++k){
shkernel[k][tz][ty][tx][0] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx];
shkernel[k][tz][ty][tx][1] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx+1];
}
}
__syncthreads();
if ( z>=0 && z <W && y>=0 && y <W){
shmatrix[tz][ty][tx] = matrix[z*D*W + y* D+ tx];
}
else
shmatrix[tz][ty][tx] = 0.0f;
__syncthreads();
//sum array stores the sum of matrix element sharing the same weights
for(m=0;m<BAND;m++){
Sum[m]=0.0;
}
if(y%STRIDE_LENGTH == 0 && z%STRIDE_LENGTH == 0){
if (ty<TILE_W && tz<TILE_W){
for(k=0;k<D;++k){
for(i=0;i<T;++i){
for(j=0;j<T;++j){
if(shkernel[tx][i][j][k][1] > 0){
Sum[shkernel[tx][i][j][k][0] - n2] += shmatrix[i+tz][ty+j][k];
}
if(shkernel[tx][i][j][k][1] < 0){
Sum[shkernel[tx][i][j][k][0] - n2] -= shmatrix[i+tz][ty+j][k];
}
}
}
}
}
for(m=0;m<BAND;m++){
if(m + n2 > 0){
ds+=Sum[m]*(1<<(m + n2));
}
else{
ds+=Sum[m]/(1<<((-1)*(m + n2)));
}
}
__syncthreads();
if (z<OWS && y<OWS && ty<TILE_W && tz<TILE_W){
output[x*OW*OW + (z/STRIDE_LENGTH)*OW + (y/STRIDE_LENGTH)] = ds;
}
}
}
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(int *kernel){
int (*t)[T][T][D][2]=(int (*)[T][T][D][2])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l][0]=((i+j+T+D)%n1 + n2);
t[i][j][k][l][1]=(pow(-1,i+j));
}
}
}
}
}
void printtofile(float *m){
const char *fname = "GPU_TAST";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++){
for(unsigned k=0;k<OW;k++){
fprintf(f,"%4.4f ", mat[i][j][k]);
}
fprintf(f, "\n");
}
fprintf(f,"\n");
}
fclose(f);
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
int *kernel=(int*)malloc(sizeof(int)*T*T*D*N*2);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;
hipMalloc(&Dmatrix,sizeof(unsigned char)*W*W*D);
int *Dkernel;
hipMalloc(&Dkernel,sizeof(int)*N*T*T*D*2);
float *Doutput;
hipMalloc(&Doutput,sizeof(float)*N*OW*OW);
hipMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,hipMemcpyHostToDevice);
hipMemcpy(Dkernel, kernel, sizeof(int)*T*T*D*N*2,hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
//Kernel Call
dim3 threads(D,TILE_W+T-1,TILE_W+T-1);
dim3 blocks(N/D, (W+TILE_W-1)/TILE_W , (W+TILE_W-1)/TILE_W );
cudaConvolve<<< blocks, threads >>>(Doutput, Dkernel, Dmatrix);
CUDA_CALL(hipGetLastError());
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
hipMemcpy(output, Doutput, sizeof(float)*N*OW*OW,hipMemcpyDeviceToHost);
//printtofile(output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cudaConvolvePfPiPh
.globl _Z12cudaConvolvePfPiPh
.p2align 8
.type _Z12cudaConvolvePfPiPh,@function
_Z12cudaConvolvePfPiPh:
s_load_b32 s2, s[0:1], 0x24
v_bfe_u32 v8, v0, 10, 10
v_bfe_u32 v9, v0, 20, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_max_u32_e32 v1, v8, v9
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s13, s13, s2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 5, v1
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 3, v0
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_u32_u24_e32 v5, 6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[1:2], null, s13, 0x258, v[3:4]
v_mul_u32_u24_e32 v4, 30, v9
v_lshlrev_b32_e32 v5, 2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v4, 2, v4
v_add_co_u32 v1, vcc_lo, v1, v5
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_mul_u32_u24_e32 v5, 0x78, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, v1, v4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_mul_u32_u24_e32 v4, 24, v8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v3, v5, v4, v3
s_mov_b64 s[2:3], 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v1, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
s_add_u32 s2, s2, 0x258
s_addc_u32 s3, s3, 0
s_cmp_lg_u64 s[2:3], 0x708
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b64 v3, v[4:5]
v_add_nc_u32_e32 v3, 0x258, v3
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s2, s15, 3
v_mov_b32_e32 v1, 0
v_add_co_u32 v3, s2, s2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, 0, 0, s2
s_lshl_b32 s2, s14, 3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s2, s2, v8
v_add_co_ci_u32_e64 v6, null, 0, 0, s2
v_cmp_gt_u64_e32 vcc_lo, 64, v[3:4]
s_barrier
buffer_gl0_inv
v_cmp_gt_u64_e64 s2, 64, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, v3, 0xc0, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v2, v4, 0xc0, v2
v_mad_u64_u32 v[10:11], null, v5, 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u32_u24 v2, v6, 3, v11
v_add_co_u32 v1, vcc_lo, v10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_load_u8 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v1, v1
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v2, 2, v0
v_mul_u32_u24_e32 v7, 12, v8
v_mul_u32_u24_e32 v10, 0x90, v9
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v10, v7, v2
ds_store_b32 v2, v1 offset:1808
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_6:
s_cmp_lg_u32 s2, 2
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s2, 1
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s2, 0
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s2, s2, 1
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[2:3], 3
s_cbranch_scc1 .LBB0_6
v_or_b32_e32 v10, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, 8, v10
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_18
v_mul_u32_u24_e32 v9, 0x90, v9
v_mul_u32_u24_e32 v10, 12, v8
v_mul_u32_u24_e32 v8, 0x258, v0
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v9, v9, v10, 0x710
s_branch .LBB0_10
.LBB0_9:
s_add_u32 s4, s4, 1
v_add_nc_u32_e32 v8, 8, v8
v_add_nc_u32_e32 v9, 4, v9
s_addc_u32 s5, s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[4:5], 3
s_cbranch_scc0 .LBB0_18
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v11, v8
s_mov_b64 s[6:7], 0
s_branch .LBB0_12
.LBB0_11:
s_add_u32 s6, s6, 1
v_add_nc_u32_e32 v11, 0x78, v11
v_add_nc_u32_e32 v10, 0x90, v10
s_addc_u32 s7, s7, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[6:7], 5
s_cbranch_scc0 .LBB0_9
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v13, v11
s_mov_b64 s[8:9], 5
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s11
s_add_u32 s8, s8, -1
v_add_nc_u32_e32 v13, 24, v13
v_add_nc_u32_e32 v12, 12, v12
s_addc_u32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u64 s[8:9], 0
s_cbranch_scc0 .LBB0_11
.LBB0_14:
ds_load_b32 v14, v13 offset:4
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e32 0, v14
s_cbranch_execz .LBB0_16
ds_load_b32 v15, v13
ds_load_b32 v16, v12
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v15, -1, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 1, v15
v_cmp_eq_u32_e64 s3, 2, v15
v_cndmask_b32_e64 v17, v7, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v17, v17, v2, s3
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v16, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, v1, v16, s2
v_cmp_eq_u32_e64 s2, 0, v15
v_cndmask_b32_e64 v2, v2, v16, s3
v_cndmask_b32_e64 v7, v7, v16, s2
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s11, exec_lo
v_cmpx_gt_i32_e32 0, v14
s_cbranch_execz .LBB0_13
ds_load_b32 v14, v13
ds_load_b32 v15, v12
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v14, -1, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e64 s2, 1, v14
v_cmp_eq_u32_e64 s3, 2, v14
v_cndmask_b32_e64 v16, v7, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v16, v16, v2, s3
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v15, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, v1, v15, s2
v_cmp_eq_u32_e64 s2, 0, v14
v_cndmask_b32_e64 v2, v2, v15, s3
v_cndmask_b32_e64 v7, v7, v15, s2
s_branch .LBB0_13
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v8, 0
s_mov_b64 s[4:5], 0
.LBB0_19:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s4, 1
s_addc_u32 s7, s5, 0
s_cmp_eq_u32 s4, 1
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s4, 2
v_cndmask_b32_e64 v9, v7, v1, s2
s_cselect_b32 s2, -1, 0
s_lshl_b32 s3, 1, s6
s_cmp_lg_u64 s[6:7], 3
v_cvt_f32_i32_e32 v10, s3
v_cndmask_b32_e64 v9, v9, v2, s2
s_mov_b64 s[4:5], s[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v10
s_cbranch_scc1 .LBB0_19
v_cmp_gt_u64_e64 s2, 60, v[3:4]
v_cmp_gt_u64_e64 s3, 60, v[5:6]
s_barrier
buffer_gl0_inv
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_22
s_load_b64 s[0:1], s[0:1], 0x0
v_add_co_u32 v2, s2, s13, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v7, null, 0, 0, s2
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, 0x3840, s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v1, v7, 0x3840, v1
v_mad_u64_u32 v[9:10], null, v3, 0xf0, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u32_u24 v2, v4, 0xf0, v10
v_add_co_u32 v0, vcc_lo, v9, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cudaConvolvePfPiPh
.amdhsa_group_segment_fixed_size 3536
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cudaConvolvePfPiPh, .Lfunc_end0-_Z12cudaConvolvePfPiPh
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 3536
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cudaConvolvePfPiPh
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cudaConvolvePfPiPh.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#include<float.h>
#define CUDA_CALL(x) do { hipError_t err=(x); \
if(err!=hipSuccess) { \
printf("Error %s at %s: %d",hipGetErrorString(err),__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define W 64 // Input DIM
#define D 3 // Input and Kernel Depth
#define T 5 // Kernel DIM
#define N 128 // Number of kernels
#define TILE_W 8 //input tile width
#define n1 3 //Range for weights(log2) from INQ
#define n2 1 //where n1 > n2
#define BAND 3 // range for weights
#define STRIDE_LENGTH 1 //STRIDE_LENGTH
#define OWS (W- T + 1) // Output DIM
#define OW (((W - T)/STRIDE_LENGTH) + 1) //output width
__global__ void cudaConvolve(float* output, int* kernel, unsigned char *matrix){
/*
one block loads its required tile from the matrix collaboritively
and calculates the values for the number of kernels equalling to blockdim.x
*/
__shared__ float shmatrix[TILE_W+T-1][TILE_W+T-1][D];
__shared__ int shkernel[D][T][T][D][2];
float Sum[BAND];
float ds=0.0;
long i=0,j=0,k=0,m=0;
long ty = threadIdx.y;
long tx = threadIdx.x;
long tz = threadIdx.z;
long z = blockIdx.z*TILE_W+tz;
long y = blockIdx.y*TILE_W+ty;
long x = blockIdx.x*blockDim.x + tx;
//kernel contains the abs log of weight and the sign
if (ty<T && tz<T){
for(k=0;k<D;++k){
shkernel[k][tz][ty][tx][0] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx];
shkernel[k][tz][ty][tx][1] = kernel[(x-tx+k)*2*D*T*T + tz*2*D*T+ ty*2*D+ 2*tx+1];
}
}
__syncthreads();
if ( z>=0 && z <W && y>=0 && y <W){
shmatrix[tz][ty][tx] = matrix[z*D*W + y* D+ tx];
}
else
shmatrix[tz][ty][tx] = 0.0f;
__syncthreads();
//sum array stores the sum of matrix element sharing the same weights
for(m=0;m<BAND;m++){
Sum[m]=0.0;
}
if(y%STRIDE_LENGTH == 0 && z%STRIDE_LENGTH == 0){
if (ty<TILE_W && tz<TILE_W){
for(k=0;k<D;++k){
for(i=0;i<T;++i){
for(j=0;j<T;++j){
if(shkernel[tx][i][j][k][1] > 0){
Sum[shkernel[tx][i][j][k][0] - n2] += shmatrix[i+tz][ty+j][k];
}
if(shkernel[tx][i][j][k][1] < 0){
Sum[shkernel[tx][i][j][k][0] - n2] -= shmatrix[i+tz][ty+j][k];
}
}
}
}
}
for(m=0;m<BAND;m++){
if(m + n2 > 0){
ds+=Sum[m]*(1<<(m + n2));
}
else{
ds+=Sum[m]/(1<<((-1)*(m + n2)));
}
}
__syncthreads();
if (z<OWS && y<OWS && ty<TILE_W && tz<TILE_W){
output[x*OW*OW + (z/STRIDE_LENGTH)*OW + (y/STRIDE_LENGTH)] = ds;
}
}
}
void fillMatrix(unsigned char *matrix){
unsigned char (*m)[W][D]=(unsigned char (*)[W][D])matrix;
for(int i=0;i<W;i++){
for(int j=0;j<W;j++){
for(int k=0;k<D;k++){
m[i][j][k]=(i*j+j*k+i*k+i*2+j*3+k*4)%255;
}
}
}
}
void fillKernel(int *kernel){
int (*t)[T][T][D][2]=(int (*)[T][T][D][2])kernel;
for(int i=0;i<N;i++){
for(int j=0;j<T;j++){
for(int k=0;k<T;k++){
for(int l=0;l<D;l++){
t[i][j][k][l][0]=((i+j+T+D)%n1 + n2);
t[i][j][k][l][1]=(pow(-1,i+j));
}
}
}
}
}
void printtofile(float *m){
const char *fname = "GPU_TAST";
FILE *f = fopen(fname, "w");
float (*mat)[OW][OW]=(float (*)[OW][OW])m;
for(unsigned i=0; i < N; i++) {
for(unsigned j=0; j < OW; j++){
for(unsigned k=0;k<OW;k++){
fprintf(f,"%4.4f ", mat[i][j][k]);
}
fprintf(f, "\n");
}
fprintf(f,"\n");
}
fclose(f);
}
int main()
{
unsigned char *matrix=(unsigned char*)malloc(sizeof(unsigned char)*W*W*D);
int *kernel=(int*)malloc(sizeof(int)*T*T*D*N*2);
float *output=(float *)malloc(sizeof(float)*N*OW*OW);
fillMatrix(matrix);
fillKernel(kernel);
unsigned char *Dmatrix;
hipMalloc(&Dmatrix,sizeof(unsigned char)*W*W*D);
int *Dkernel;
hipMalloc(&Dkernel,sizeof(int)*N*T*T*D*2);
float *Doutput;
hipMalloc(&Doutput,sizeof(float)*N*OW*OW);
hipMemcpy(Dmatrix, matrix, sizeof(unsigned char)*W*W*D,hipMemcpyHostToDevice);
hipMemcpy(Dkernel, kernel, sizeof(int)*T*T*D*N*2,hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float milliseconds = 0;
hipEventRecord(start,0);
//Kernel Call
dim3 threads(D,TILE_W+T-1,TILE_W+T-1);
dim3 blocks(N/D, (W+TILE_W-1)/TILE_W , (W+TILE_W-1)/TILE_W );
cudaConvolve<<< blocks, threads >>>(Doutput, Dkernel, Dmatrix);
CUDA_CALL(hipGetLastError());
hipDeviceSynchronize();
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n",milliseconds);
hipMemcpy(output, Doutput, sizeof(float)*N*OW*OW,hipMemcpyDeviceToHost);
//printtofile(output);
} | .text
.file "stridedConvolution.hip"
.globl _Z27__device_stub__cudaConvolvePfPiPh # -- Begin function _Z27__device_stub__cudaConvolvePfPiPh
.p2align 4, 0x90
.type _Z27__device_stub__cudaConvolvePfPiPh,@function
_Z27__device_stub__cudaConvolvePfPiPh: # @_Z27__device_stub__cudaConvolvePfPiPh
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cudaConvolvePfPiPh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__cudaConvolvePfPiPh, .Lfunc_end0-_Z27__device_stub__cudaConvolvePfPiPh
.cfi_endproc
# -- End function
.globl _Z10fillMatrixPh # -- Begin function _Z10fillMatrixPh
.p2align 4, 0x90
.type _Z10fillMatrixPh,@function
_Z10fillMatrixPh: # @_Z10fillMatrixPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
movq $-3, %r14
movl %r10d, %ebp
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, 3(%r11,%r14)
addl %r9d, %ebp
incq %r14
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
incq %rbx
addq $3, %r11
addl %ecx, %r10d
incl %r9d
cmpq $64, %rbx
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %r8
addq $192, %rdi
addl $2, %eax
incl %ecx
incl %edx
cmpq $64, %r8
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10fillMatrixPh, .Lfunc_end1-_Z10fillMatrixPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10fillKernelPi
.LCPI2_0:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z10fillKernelPi
.p2align 4, 0x90
.type _Z10fillKernelPi,@function
_Z10fillKernelPi: # @_Z10fillKernelPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
addq $4, %rbx
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_1: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
# Child Loop BB2_4 Depth 4
movq %rbx, 8(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader25
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
# Child Loop BB2_4 Depth 4
movq (%rsp), %rcx # 8-byte Reload
leal (%rcx,%r13), %eax
leal (%rcx,%r13), %ebp
addl $8, %ebp
movq %rbp, %rcx
movl $2863311531, %edx # imm = 0xAAAAAAAB
imulq %rdx, %rcx
shrq $33, %rcx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %ebp
incl %ebp
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movq %rbx, %r12
xorl %r15d, %r15d
movsd %xmm1, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_4 Depth 4
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# Parent Loop BB2_3 Depth=3
# => This Inner Loop Header: Depth=4
movl %ebp, -4(%r12,%r14,8)
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq pow
cvttsd2si %xmm0, %eax
movl %eax, (%r12,%r14,8)
incq %r14
cmpq $3, %r14
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=3
incq %r15
addq $24, %r12
cmpq $5, %r15
jne .LBB2_3
# %bb.6: # in Loop: Header=BB2_2 Depth=2
incq %r13
addq $120, %rbx
cmpq $5, %r13
jne .LBB2_2
# %bb.7: # in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rcx # 8-byte Reload
incq %rcx
movq 8(%rsp), %rbx # 8-byte Reload
addq $600, %rbx # imm = 0x258
movq %rcx, %rax
movq %rcx, (%rsp) # 8-byte Spill
cmpq $128, %rcx
jne .LBB2_1
# %bb.8:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10fillKernelPi, .Lfunc_end2-_Z10fillKernelPi
.cfi_endproc
# -- End function
.globl _Z11printtofilePf # -- Begin function _Z11printtofilePf
.p2align 4, 0x90
.type _Z11printtofilePf,@function
_Z11printtofilePf: # @_Z11printtofilePf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # %.preheader18
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
# Child Loop BB3_3 Depth 3
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_3 Depth 3
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $60, %rbp
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=2
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r13
addq $240, %r12
cmpq $60, %r13
jne .LBB3_2
# %bb.5: # in Loop: Header=BB3_1 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addq $14400, %rbx # imm = 0x3840
cmpq $128, %r15
jne .LBB3_1
# %bb.6:
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z11printtofilePf, .Lfunc_end3-_Z11printtofilePf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0xbff0000000000000 # double -1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $12288, %edi # imm = 0x3000
callq malloc
movq %rax, %rbx
movl $76800, %edi # imm = 0x12C00
callq malloc
movq %rax, %r12
movl $1843200, %edi # imm = 0x1C2000
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
movq %rbx, 72(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_1: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
movl %r10d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, (%r11,%r14)
incq %r14
addl %r9d, %ebp
cmpq $3, %r14
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rbx
addq $3, %r11
addl %ecx, %r10d
incl %r9d
cmpq $64, %rbx
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %r8
addq $192, %rdi
addl $2, %eax
incl %ecx
incl %edx
cmpq $64, %r8
jne .LBB4_1
# %bb.6: # %.preheader26.i.preheader
movq %r12, 80(%rsp) # 8-byte Spill
movq %r12, %r14
addq $4, %r14
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_7: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
movq %r14, 88(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_8: # %.preheader25.i
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
movq 16(%rsp), %rcx # 8-byte Reload
leal (%rbx,%rcx), %eax
leal (%rbx,%rcx), %r15d
addl $8, %r15d
movq %r15, %rcx
movl $2863311531, %edx # imm = 0xAAAAAAAB
imulq %rdx, %rcx
shrq $33, %rcx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %r15d
incl %r15d
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movq %r14, %r12
xorl %ebp, %ebp
movsd %xmm1, 96(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_9: # %.preheader.i17
# Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_10 Depth 4
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# Parent Loop BB4_9 Depth=3
# => This Inner Loop Header: Depth=4
movl %r15d, -4(%r12,%r13,8)
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 96(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq pow
cvttsd2si %xmm0, %eax
movl %eax, (%r12,%r13,8)
incq %r13
cmpq $3, %r13
jne .LBB4_10
# %bb.11: # in Loop: Header=BB4_9 Depth=3
incq %rbp
addq $24, %r12
cmpq $5, %rbp
jne .LBB4_9
# %bb.12: # in Loop: Header=BB4_8 Depth=2
incq %rbx
addq $120, %r14
cmpq $5, %rbx
jne .LBB4_8
# %bb.13: # in Loop: Header=BB4_7 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
incq %rcx
movq 88(%rsp), %r14 # 8-byte Reload
addq $600, %r14 # imm = 0x258
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpq $128, %rcx
jne .LBB4_7
# %bb.14: # %_Z10fillKernelPi.exit
leaq 56(%rsp), %rdi
movl $12288, %esi # imm = 0x3000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $76800, %esi # imm = 0x12C00
callq hipMalloc
leaq 40(%rsp), %rdi
movl $1843200, %esi # imm = 0x1C2000
callq hipMalloc
movq 56(%rsp), %rdi
movl $12288, %edx # imm = 0x3000
movq 72(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $76800, %edx # imm = 0x12C00
movq 80(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movq 32(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movabsq $34359738410, %rdi # imm = 0x80000002A
movabsq $51539607555, %rdx # imm = 0xC00000003
movl $8, %esi
movl $12, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z12cudaConvolvePfPiPh, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipGetLastError
movl %eax, %ebp
testl %eax, %eax
je .LBB4_18
# %bb.17:
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.5, %edx
movq %rax, %rsi
movl $194, %ecx
xorl %eax, %eax
callq printf
movl $1, %r14d
.LBB4_18:
testl %ebp, %ebp
jne .LBB4_20
# %bb.19:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rsi
movl $1843200, %edx # imm = 0x1C2000
movq 64(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.LBB4_20:
movl %r14d, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cudaConvolvePfPiPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12cudaConvolvePfPiPh,@object # @_Z12cudaConvolvePfPiPh
.section .rodata,"a",@progbits
.globl _Z12cudaConvolvePfPiPh
.p2align 3, 0x0
_Z12cudaConvolvePfPiPh:
.quad _Z27__device_stub__cudaConvolvePfPiPh
.size _Z12cudaConvolvePfPiPh, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU_TAST"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %s at %s: %d"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/MohammedKhandwawala/INQ-GPU-Convolution/master/codes/stridedConvolution.hip"
.size .L.str.5, 133
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%f\n"
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12cudaConvolvePfPiPh"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cudaConvolvePfPiPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12cudaConvolvePfPiPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001208e6_00000000-6_stridedConvolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10fillMatrixPh
.type _Z10fillMatrixPh, @function
_Z10fillMatrixPh:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbp
movl $0, %r12d
movl $0, %ebx
jmp .L4
.L11:
addl $1, %edi
addl %r11d, %r9d
addq $3, %rsi
cmpl $64, %edi
je .L6
.L8:
leal (%r10,%rdi), %r8d
movl %r9d, %edx
movl $0, %ecx
.L5:
movslq %edx, %rax
imulq $-2139062143, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $7, %eax
movl %edx, %r13d
sarl $31, %r13d
subl %r13d, %eax
movl %eax, %r13d
sall $8, %r13d
subl %eax, %r13d
movl %edx, %eax
subl %r13d, %eax
movb %al, (%rsi,%rcx)
addq $1, %rcx
addl %r8d, %edx
cmpq $3, %rcx
jne .L5
jmp .L11
.L6:
addl $1, %ebx
addl $2, %r12d
addq $192, %rbp
cmpl $64, %ebx
je .L3
.L4:
leal 3(%rbx), %r11d
movq %rbp, %rsi
movl %r12d, %r9d
movl $0, %edi
leal 4(%rbx), %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10fillMatrixPh, .-_Z10fillMatrixPh
.globl _Z10fillKernelPi
.type _Z10fillKernelPi, @function
_Z10fillKernelPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, (%rsp)
movl $0, 12(%rsp)
jmp .L13
.L22:
addq $24, %r13
cmpq %r14, %r13
je .L15
.L17:
movq %r13, %rbx
movl $3, %ebp
.L14:
movl %r12d, (%rbx)
pxor %xmm1, %xmm1
cvtsi2sdl 8(%rsp), %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %eax
movl %eax, 4(%rbx)
addq $8, %rbx
subl $1, %ebp
jne .L14
jmp .L22
.L15:
addl $1, %r15d
addq $120, %r14
movq (%rsp), %rax
addq $720, %rax
cmpq %rax, %r14
je .L16
.L19:
movl %r15d, 8(%rsp)
leal 8(%r15), %r12d
movslq %r12d, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %r12d, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
subl %eax, %r12d
addl $1, %r12d
leaq -120(%r14), %r13
jmp .L17
.L16:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
addq $600, (%rsp)
cmpl $128, %eax
je .L12
.L13:
movl 12(%rsp), %r15d
movq (%rsp), %rax
leaq 120(%rax), %r14
jmp .L19
.L12:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10fillKernelPi, .-_Z10fillKernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "w"
.LC2:
.string "GPU_TAST"
.LC3:
.string "%4.4f "
.LC4:
.string "\n"
.text
.globl _Z11printtofilePf
.type _Z11printtofilePf, @function
_Z11printtofilePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbx, (%rsp)
leaq 1843200(%rbx), %rax
movq %rax, 8(%rsp)
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
jmp .L24
.L26:
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $14400, (%rsp)
movq (%rsp), %rax
movq 8(%rsp), %rcx
cmpq %rcx, %rax
je .L27
.L24:
movq (%rsp), %rax
leaq 240(%rax), %rbp
leaq 14640(%rax), %r15
.L28:
leaq -240(%rbp), %rbx
.L25:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L25
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $240, %rbp
cmpq %r15, %rbp
jne .L28
jmp .L26
.L27:
movq %r12, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11printtofilePf, .-_Z11printtofilePf
.globl _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
.type _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh, @function
_Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cudaConvolvePfPiPh(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh, .-_Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
.globl _Z12cudaConvolvePfPiPh
.type _Z12cudaConvolvePfPiPh, @function
_Z12cudaConvolvePfPiPh:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12cudaConvolvePfPiPh, .-_Z12cudaConvolvePfPiPh
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/MohammedKhandwawala/INQ-GPU-Convolution/master/codes/stridedConvolution.cu"
.section .rodata.str1.1
.LC7:
.string "Error %s at %s: %d"
.LC8:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $12288, %edi
call malloc@PLT
movq %rax, %rbp
movl $76800, %edi
call malloc@PLT
movq %rax, %rbx
movl $1843200, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z10fillMatrixPh
movq %rbx, %rdi
call _Z10fillKernelPi
leaq 8(%rsp), %rdi
movl $12288, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $76800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1843200, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $12288, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $76800, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, 4(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $3, 48(%rsp)
movl $12, 52(%rsp)
movl $42, 60(%rsp)
movl $8, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $12, %ecx
movq 60(%rsp), %rdi
movl $8, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L40:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L46
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $1843200, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L39:
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L47
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z12cudaConvolvePfPiPhPfPiPh
jmp .L40
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $194, %r8d
leaq .LC6(%rip), %rcx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L39
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z12cudaConvolvePfPiPh"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cudaConvolvePfPiPh(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stridedConvolution.hip"
.globl _Z27__device_stub__cudaConvolvePfPiPh # -- Begin function _Z27__device_stub__cudaConvolvePfPiPh
.p2align 4, 0x90
.type _Z27__device_stub__cudaConvolvePfPiPh,@function
_Z27__device_stub__cudaConvolvePfPiPh: # @_Z27__device_stub__cudaConvolvePfPiPh
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cudaConvolvePfPiPh, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__cudaConvolvePfPiPh, .Lfunc_end0-_Z27__device_stub__cudaConvolvePfPiPh
.cfi_endproc
# -- End function
.globl _Z10fillMatrixPh # -- Begin function _Z10fillMatrixPh
.p2align 4, 0x90
.type _Z10fillMatrixPh,@function
_Z10fillMatrixPh: # @_Z10fillMatrixPh
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
movq $-3, %r14
movl %r10d, %ebp
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, 3(%r11,%r14)
addl %r9d, %ebp
incq %r14
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
incq %rbx
addq $3, %r11
addl %ecx, %r10d
incl %r9d
cmpq $64, %rbx
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %r8
addq $192, %rdi
addl $2, %eax
incl %ecx
incl %edx
cmpq $64, %r8
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10fillMatrixPh, .Lfunc_end1-_Z10fillMatrixPh
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10fillKernelPi
.LCPI2_0:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z10fillKernelPi
.p2align 4, 0x90
.type _Z10fillKernelPi,@function
_Z10fillKernelPi: # @_Z10fillKernelPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
addq $4, %rbx
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_1: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
# Child Loop BB2_4 Depth 4
movq %rbx, 8(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_2: # %.preheader25
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
# Child Loop BB2_4 Depth 4
movq (%rsp), %rcx # 8-byte Reload
leal (%rcx,%r13), %eax
leal (%rcx,%r13), %ebp
addl $8, %ebp
movq %rbp, %rcx
movl $2863311531, %edx # imm = 0xAAAAAAAB
imulq %rdx, %rcx
shrq $33, %rcx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %ebp
incl %ebp
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movq %rbx, %r12
xorl %r15d, %r15d
movsd %xmm1, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_3: # %.preheader
# Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_4 Depth 4
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# Parent Loop BB2_3 Depth=3
# => This Inner Loop Header: Depth=4
movl %ebp, -4(%r12,%r14,8)
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq pow
cvttsd2si %xmm0, %eax
movl %eax, (%r12,%r14,8)
incq %r14
cmpq $3, %r14
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=3
incq %r15
addq $24, %r12
cmpq $5, %r15
jne .LBB2_3
# %bb.6: # in Loop: Header=BB2_2 Depth=2
incq %r13
addq $120, %rbx
cmpq $5, %r13
jne .LBB2_2
# %bb.7: # in Loop: Header=BB2_1 Depth=1
movq (%rsp), %rcx # 8-byte Reload
incq %rcx
movq 8(%rsp), %rbx # 8-byte Reload
addq $600, %rbx # imm = 0x258
movq %rcx, %rax
movq %rcx, (%rsp) # 8-byte Spill
cmpq $128, %rcx
jne .LBB2_1
# %bb.8:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10fillKernelPi, .Lfunc_end2-_Z10fillKernelPi
.cfi_endproc
# -- End function
.globl _Z11printtofilePf # -- Begin function _Z11printtofilePf
.p2align 4, 0x90
.type _Z11printtofilePf,@function
_Z11printtofilePf: # @_Z11printtofilePf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_1: # %.preheader18
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
# Child Loop BB3_3 Depth 3
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_3 Depth 3
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq $60, %rbp
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=2
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r13
addq $240, %r12
cmpq $60, %r13
jne .LBB3_2
# %bb.5: # in Loop: Header=BB3_1 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addq $14400, %rbx # imm = 0x3840
cmpq $128, %r15
jne .LBB3_1
# %bb.6:
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z11printtofilePf, .Lfunc_end3-_Z11printtofilePf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0xbff0000000000000 # double -1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $12288, %edi # imm = 0x3000
callq malloc
movq %rax, %rbx
movl $76800, %edi # imm = 0x12C00
callq malloc
movq %rax, %r12
movl $1843200, %edi # imm = 0x1C2000
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
xorl %eax, %eax
movl $3, %ecx
movl $4, %edx
movl $2155905153, %esi # imm = 0x80808081
movq %rbx, 72(%rsp) # 8-byte Spill
movq %rbx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_1: # %.preheader23.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movl %edx, %r9d
movl %eax, %r10d
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
movl %r10d, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movl %ebp, %r15d
imulq %rsi, %r15
shrq $39, %r15
addb %bpl, %r15b
movb %r15b, (%r11,%r14)
incq %r14
addl %r9d, %ebp
cmpq $3, %r14
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rbx
addq $3, %r11
addl %ecx, %r10d
incl %r9d
cmpq $64, %rbx
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %r8
addq $192, %rdi
addl $2, %eax
incl %ecx
incl %edx
cmpq $64, %r8
jne .LBB4_1
# %bb.6: # %.preheader26.i.preheader
movq %r12, 80(%rsp) # 8-byte Spill
movq %r12, %r14
addq $4, %r14
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_7: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
movq %r14, 88(%rsp) # 8-byte Spill
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_8: # %.preheader25.i
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
# Child Loop BB4_10 Depth 4
movq 16(%rsp), %rcx # 8-byte Reload
leal (%rbx,%rcx), %eax
leal (%rbx,%rcx), %r15d
addl $8, %r15d
movq %r15, %rcx
movl $2863311531, %edx # imm = 0xAAAAAAAB
imulq %rdx, %rcx
shrq $33, %rcx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %r15d
incl %r15d
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movq %r14, %r12
xorl %ebp, %ebp
movsd %xmm1, 96(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_9: # %.preheader.i17
# Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_10 Depth 4
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_10: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# Parent Loop BB4_9 Depth=3
# => This Inner Loop Header: Depth=4
movl %r15d, -4(%r12,%r13,8)
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd 96(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq pow
cvttsd2si %xmm0, %eax
movl %eax, (%r12,%r13,8)
incq %r13
cmpq $3, %r13
jne .LBB4_10
# %bb.11: # in Loop: Header=BB4_9 Depth=3
incq %rbp
addq $24, %r12
cmpq $5, %rbp
jne .LBB4_9
# %bb.12: # in Loop: Header=BB4_8 Depth=2
incq %rbx
addq $120, %r14
cmpq $5, %rbx
jne .LBB4_8
# %bb.13: # in Loop: Header=BB4_7 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
incq %rcx
movq 88(%rsp), %r14 # 8-byte Reload
addq $600, %r14 # imm = 0x258
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpq $128, %rcx
jne .LBB4_7
# %bb.14: # %_Z10fillKernelPi.exit
leaq 56(%rsp), %rdi
movl $12288, %esi # imm = 0x3000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $76800, %esi # imm = 0x12C00
callq hipMalloc
leaq 40(%rsp), %rdi
movl $1843200, %esi # imm = 0x1C2000
callq hipMalloc
movq 56(%rsp), %rdi
movl $12288, %edx # imm = 0x3000
movq 72(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $76800, %edx # imm = 0x12C00
movq 80(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $0, 12(%rsp)
movq 32(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movabsq $34359738410, %rdi # imm = 0x80000002A
movabsq $51539607555, %rdx # imm = 0xC00000003
movl $8, %esi
movl $12, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_16
# %bb.15:
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z12cudaConvolvePfPiPh, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_16:
callq hipGetLastError
movl %eax, %ebp
testl %eax, %eax
je .LBB4_18
# %bb.17:
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.5, %edx
movq %rax, %rsi
movl $194, %ecx
xorl %eax, %eax
callq printf
movl $1, %r14d
.LBB4_18:
testl %ebp, %ebp
jne .LBB4_20
# %bb.19:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rsi
movl $1843200, %edx # imm = 0x1C2000
movq 64(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.LBB4_20:
movl %r14d, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cudaConvolvePfPiPh, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12cudaConvolvePfPiPh,@object # @_Z12cudaConvolvePfPiPh
.section .rodata,"a",@progbits
.globl _Z12cudaConvolvePfPiPh
.p2align 3, 0x0
_Z12cudaConvolvePfPiPh:
.quad _Z27__device_stub__cudaConvolvePfPiPh
.size _Z12cudaConvolvePfPiPh, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU_TAST"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%4.4f "
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %s at %s: %d"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/MohammedKhandwawala/INQ-GPU-Convolution/master/codes/stridedConvolution.hip"
.size .L.str.5, 133
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%f\n"
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12cudaConvolvePfPiPh"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cudaConvolvePfPiPh
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12cudaConvolvePfPiPh
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cmath>
#include <cuda.h>
#include <curand_kernel.h>
#include <ctime>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MCpoints(int* d_out, int n, int n_for, curandState* state)
{
const int myID = blockIdx.x*blockDim.x + threadIdx.x;
curand_init(1234, myID, 0, &state[myID]);
curandState localState = state[myID];
d_out[myID] = 0;
for (int i=0; i<n_for; i++)
{
float x = curand_uniform(&localState);
float y = curand_uniform(&localState);
if (sqrt(x*x+y*y)<1)
{
d_out[myID]++;
}
//printf("d_out[%d] = %d\n",myID,d_out[myID]);
}
}
int main()
{
const long int N = pow(2,31);
const int B = 1024;
const int TPB = 32;
const int T = (B*TPB);
const int n_for = N/T;
int counter = 0;
int* out = (int*) calloc(T,sizeof(int));
int* d_out = 0;
cudaMalloc(&d_out, T*sizeof(int));
curandState *devStates;
cudaMalloc(&devStates, T*sizeof(int));
auto t1 = std::chrono::high_resolution_clock::now();
MCpoints<<<B, TPB>>>(d_out, T, n_for, devStates);
gpuErrchk( cudaMemcpy(out, d_out, T*sizeof(int), cudaMemcpyDeviceToHost) );
for (int i=0; i<T; i++)
{
counter += out[i];
}
double pi = 4*double(counter)/double(N);
auto t2 = std::chrono::high_resolution_clock::now();
auto t_elapsed = std::chrono::duration<double>(t2-t1).count();
printf("samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n",N,counter,pi,t_elapsed);
cudaFree(d_out);
cudaFree(devStates);
free(out);
} | .file "tmpxft_0010d048_00000000-6_pi_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2378:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2378:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
.type _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW, @function
_Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW:
.LFB2400:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8MCpointsPiiiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2400:
.size _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW, .-_Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
.globl _Z8MCpointsPiiiP17curandStateXORWOW
.type _Z8MCpointsPiiiP17curandStateXORWOW, @function
_Z8MCpointsPiiiP17curandStateXORWOW:
.LFB2401:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2401:
.size _Z8MCpointsPiiiP17curandStateXORWOW, .-_Z8MCpointsPiiiP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/timadjordan/Gitpository/Yggdrasil/MC_pi/pi_cuda.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2371:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $32768, %edi
call calloc@PLT
movq %rax, %rbp
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $2, %ecx
movl $131072, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L19
movq %rbp, %rax
leaq 131072(%rbp), %rcx
movl $0, %edx
.L14:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L14
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC3(%rip), %xmm0
movsd %xmm0, 8(%rsp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd 8(%rsp), %xmm0
movl %ebx, %ecx
movl $2147483648, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rcx
movl $65536, %edx
movl $32768, %esi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
jmp .L12
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $61, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2371:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z8MCpointsPiiiP17curandStateXORWOW"
.section .rodata.str1.1
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2403:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MCpointsPiiiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2403:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1074790400
.align 8
.LC3:
.long 0
.long 1040187392
.align 8
.LC4:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cmath>
#include <cuda.h>
#include <curand_kernel.h>
#include <ctime>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MCpoints(int* d_out, int n, int n_for, curandState* state)
{
const int myID = blockIdx.x*blockDim.x + threadIdx.x;
curand_init(1234, myID, 0, &state[myID]);
curandState localState = state[myID];
d_out[myID] = 0;
for (int i=0; i<n_for; i++)
{
float x = curand_uniform(&localState);
float y = curand_uniform(&localState);
if (sqrt(x*x+y*y)<1)
{
d_out[myID]++;
}
//printf("d_out[%d] = %d\n",myID,d_out[myID]);
}
}
int main()
{
const long int N = pow(2,31);
const int B = 1024;
const int TPB = 32;
const int T = (B*TPB);
const int n_for = N/T;
int counter = 0;
int* out = (int*) calloc(T,sizeof(int));
int* d_out = 0;
cudaMalloc(&d_out, T*sizeof(int));
curandState *devStates;
cudaMalloc(&devStates, T*sizeof(int));
auto t1 = std::chrono::high_resolution_clock::now();
MCpoints<<<B, TPB>>>(d_out, T, n_for, devStates);
gpuErrchk( cudaMemcpy(out, d_out, T*sizeof(int), cudaMemcpyDeviceToHost) );
for (int i=0; i<T; i++)
{
counter += out[i];
}
double pi = 4*double(counter)/double(N);
auto t2 = std::chrono::high_resolution_clock::now();
auto t_elapsed = std::chrono::duration<double>(t2-t1).count();
printf("samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n",N,counter,pi,t_elapsed);
cudaFree(d_out);
cudaFree(devStates);
free(out);
} | #include <stdio.h>
#include <cmath>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <ctime>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MCpoints(int* d_out, int n, int n_for, hiprandState* state)
{
const int myID = blockIdx.x*blockDim.x + threadIdx.x;
hiprand_init(1234, myID, 0, &state[myID]);
hiprandState localState = state[myID];
d_out[myID] = 0;
for (int i=0; i<n_for; i++)
{
float x = hiprand_uniform(&localState);
float y = hiprand_uniform(&localState);
if (sqrt(x*x+y*y)<1)
{
d_out[myID]++;
}
//printf("d_out[%d] = %d\n",myID,d_out[myID]);
}
}
int main()
{
const long int N = pow(2,31);
const int B = 1024;
const int TPB = 32;
const int T = (B*TPB);
const int n_for = N/T;
int counter = 0;
int* out = (int*) calloc(T,sizeof(int));
int* d_out = 0;
hipMalloc(&d_out, T*sizeof(int));
hiprandState *devStates;
hipMalloc(&devStates, T*sizeof(int));
auto t1 = std::chrono::high_resolution_clock::now();
MCpoints<<<B, TPB>>>(d_out, T, n_for, devStates);
gpuErrchk( hipMemcpy(out, d_out, T*sizeof(int), hipMemcpyDeviceToHost) );
for (int i=0; i<T; i++)
{
counter += out[i];
}
double pi = 4*double(counter)/double(N);
auto t2 = std::chrono::high_resolution_clock::now();
auto t_elapsed = std::chrono::duration<double>(t2-t1).count();
printf("samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n",N,counter,pi,t_elapsed);
hipFree(d_out);
hipFree(devStates);
free(out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <cmath>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <ctime>
#include <chrono>
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void MCpoints(int* d_out, int n, int n_for, hiprandState* state)
{
const int myID = blockIdx.x*blockDim.x + threadIdx.x;
hiprand_init(1234, myID, 0, &state[myID]);
hiprandState localState = state[myID];
d_out[myID] = 0;
for (int i=0; i<n_for; i++)
{
float x = hiprand_uniform(&localState);
float y = hiprand_uniform(&localState);
if (sqrt(x*x+y*y)<1)
{
d_out[myID]++;
}
//printf("d_out[%d] = %d\n",myID,d_out[myID]);
}
}
int main()
{
const long int N = pow(2,31);
const int B = 1024;
const int TPB = 32;
const int T = (B*TPB);
const int n_for = N/T;
int counter = 0;
int* out = (int*) calloc(T,sizeof(int));
int* d_out = 0;
hipMalloc(&d_out, T*sizeof(int));
hiprandState *devStates;
hipMalloc(&devStates, T*sizeof(int));
auto t1 = std::chrono::high_resolution_clock::now();
MCpoints<<<B, TPB>>>(d_out, T, n_for, devStates);
gpuErrchk( hipMemcpy(out, d_out, T*sizeof(int), hipMemcpyDeviceToHost) );
for (int i=0; i<T; i++)
{
counter += out[i];
}
double pi = 4*double(counter)/double(N);
auto t2 = std::chrono::high_resolution_clock::now();
auto t_elapsed = std::chrono::duration<double>(t2-t1).count();
printf("samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n",N,counter,pi,t_elapsed);
hipFree(d_out);
hipFree(devStates);
free(out);
} | .text
.file "pi_cuda.hip"
.globl _Z23__device_stub__MCpointsPiiiP12hiprandState # -- Begin function _Z23__device_stub__MCpointsPiiiP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__MCpointsPiiiP12hiprandState,@function
_Z23__device_stub__MCpointsPiiiP12hiprandState: # @_Z23__device_stub__MCpointsPiiiP12hiprandState
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8MCpointsPiiiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__MCpointsPiiiP12hiprandState, .Lfunc_end0-_Z23__device_stub__MCpointsPiiiP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4010000000000000 # double 4
.LCPI1_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI1_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $32768, %edi # imm = 0x8000
movl $4, %esi
callq calloc
movq %rax, %rbx
movq $0, (%rsp)
movq %rsp, %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 992(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movl $32768, 12(%rsp) # imm = 0x8000
movl $65536, 8(%rsp) # imm = 0x10000
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8MCpointsPiiiP12hiprandState, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # %_Z9gpuAssert10hipError_tPKcib.exit
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB1_4
# %bb.5:
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
cvtsi2sd %rax, %xmm1
divsd .LCPI1_2(%rip), %xmm1
movl $.L.str.1, %edi
movl $2147483648, %esi # imm = 0x80000000
movl %ebp, %edx
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MCpointsPiiiP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MCpointsPiiiP12hiprandState,@object # @_Z8MCpointsPiiiP12hiprandState
.section .rodata,"a",@progbits
.globl _Z8MCpointsPiiiP12hiprandState
.p2align 3, 0x0
_Z8MCpointsPiiiP12hiprandState:
.quad _Z23__device_stub__MCpointsPiiiP12hiprandState
.size _Z8MCpointsPiiiP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/timadjordan/Gitpository/Yggdrasil/MC_pi/pi_cuda.hip"
.size .L.str, 109
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n"
.size .L.str.1, 60
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MCpointsPiiiP12hiprandState"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MCpointsPiiiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MCpointsPiiiP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010d048_00000000-6_pi_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2378:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2378:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
.type _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW, @function
_Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW:
.LFB2400:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8MCpointsPiiiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2400:
.size _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW, .-_Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
.globl _Z8MCpointsPiiiP17curandStateXORWOW
.type _Z8MCpointsPiiiP17curandStateXORWOW, @function
_Z8MCpointsPiiiP17curandStateXORWOW:
.LFB2401:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2401:
.size _Z8MCpointsPiiiP17curandStateXORWOW, .-_Z8MCpointsPiiiP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/timadjordan/Gitpository/Yggdrasil/MC_pi/pi_cuda.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2371:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $32768, %edi
call calloc@PLT
movq %rax, %rbp
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $2, %ecx
movl $131072, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L19
movq %rbp, %rax
leaq 131072(%rbp), %rcx
movl $0, %edx
.L14:
movl %edx, %ebx
addl (%rax), %ebx
movl %ebx, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L14
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC3(%rip), %xmm0
movsd %xmm0, 8(%rsp)
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r12, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC4(%rip), %xmm1
movsd 8(%rsp), %xmm0
movl %ebx, %ecx
movl $2147483648, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rcx
movl $65536, %edx
movl $32768, %esi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z8MCpointsPiiiP17curandStateXORWOWPiiiP17curandStateXORWOW
jmp .L12
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $61, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2371:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z8MCpointsPiiiP17curandStateXORWOW"
.section .rodata.str1.1
.LC7:
.string "precalc_xorwow_matrix"
.LC8:
.string "precalc_xorwow_offset_matrix"
.LC9:
.string "mrg32k3aM1"
.LC10:
.string "mrg32k3aM2"
.LC11:
.string "mrg32k3aM1SubSeq"
.LC12:
.string "mrg32k3aM2SubSeq"
.LC13:
.string "mrg32k3aM1Seq"
.LC14:
.string "mrg32k3aM2Seq"
.LC15:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2403:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MCpointsPiiiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2403:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1074790400
.align 8
.LC3:
.long 0
.long 1040187392
.align 8
.LC4:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pi_cuda.hip"
.globl _Z23__device_stub__MCpointsPiiiP12hiprandState # -- Begin function _Z23__device_stub__MCpointsPiiiP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__MCpointsPiiiP12hiprandState,@function
_Z23__device_stub__MCpointsPiiiP12hiprandState: # @_Z23__device_stub__MCpointsPiiiP12hiprandState
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8MCpointsPiiiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__MCpointsPiiiP12hiprandState, .Lfunc_end0-_Z23__device_stub__MCpointsPiiiP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4010000000000000 # double 4
.LCPI1_1:
.quad 0x3e00000000000000 # double 4.6566128730773926E-10
.LCPI1_2:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $32768, %edi # imm = 0x8000
movl $4, %esi
callq calloc
movq %rax, %rbx
movq $0, (%rsp)
movq %rsp, %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movabsq $4294967328, %rdx # imm = 0x100000020
leaq 992(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movl $32768, 12(%rsp) # imm = 0x8000
movl $65536, 8(%rsp) # imm = 0x10000
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8MCpointsPiiiP12hiprandState, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.3: # %_Z9gpuAssert10hipError_tPKcib.exit.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # %_Z9gpuAssert10hipError_tPKcib.exit
# =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $32768, %rax # imm = 0x8000
jne .LBB1_4
# %bb.5:
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
mulsd .LCPI1_1(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %r14, %rax
cvtsi2sd %rax, %xmm1
divsd .LCPI1_2(%rip), %xmm1
movl $.L.str.1, %edi
movl $2147483648, %esi # imm = 0x80000000
movl %ebp, %edx
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $2, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_6:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %r8d
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MCpointsPiiiP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MCpointsPiiiP12hiprandState,@object # @_Z8MCpointsPiiiP12hiprandState
.section .rodata,"a",@progbits
.globl _Z8MCpointsPiiiP12hiprandState
.p2align 3, 0x0
_Z8MCpointsPiiiP12hiprandState:
.quad _Z23__device_stub__MCpointsPiiiP12hiprandState
.size _Z8MCpointsPiiiP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/timadjordan/Gitpository/Yggdrasil/MC_pi/pi_cuda.hip"
.size .L.str, 109
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "samples = %ld\ncounter = %d\npi = %f\ntime elapsed: %1.4f sec\n"
.size .L.str.1, 60
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MCpointsPiiiP12hiprandState"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MCpointsPiiiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MCpointsPiiiP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
// a struct
typedef struct
{
int size;
char *_string;
} string_t;
__global__ void string_append(string_t*, string_t*, string_t*);
int main(void)
{
string_t *str1, *str2, *str3;
size_t size1 = strlen("Hello, ");
size_t size2 = sizeof("world!");
// allocate memory for str1, str2, and str3
// and for their string members.
cudaMallocManaged(&str1, sizeof(string_t));
cudaMallocManaged(&(str1->_string), size1*sizeof(char));
cudaMallocManaged(&str2, sizeof(string_t));
cudaMallocManaged(&(str2->_string), size2*sizeof(char));
cudaMallocManaged(&str3, sizeof(string_t));
cudaMallocManaged(&(str3->_string), (size1+size2) * sizeof(char));
// the CPU and the GPU can directly access memory allocated to str's
//In the following 4 lines the Host is accessing
// the memory allocated via cudaMallocManaged().
str1->size = size1;
memcpy(str1->_string, "Hello, ", size1);
str2->size = size2;
memcpy(str2->_string, "world!", size2);
// Since the kernel has been declared/defined with
// "__global__" keyword we are sure it will run on the device.
// So the device will be accessing memory allocated via cudaMallocManaged().
string_append<<<1, 1>>>(str1, str2, str3);
// the device and the host should be synchronized
// before we call printf in the host.
cudaDeviceSynchronize();
printf("%s\n", str3->_string);
exit(EXIT_SUCCESS);
}
// a kernel to append 2 strings in a 3rd string.
__global__ void string_append(string_t *s1, string_t *s2, string_t *s3)
{
memcpy(s3->_string, s1->_string, s1->size);
memcpy(s3->_string+(s1->size), s2->_string, s2->size);
} | code for sm_80
Function : _Z13string_appendP8string_tS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fc80000000a00 */
/*0050*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1900 */
/*0060*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000ff1e03f */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*00a0*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe4000f8e00ff */
/*00b0*/ LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080604027981 */
/* 0x000162000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fe2000f8e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 BRA 0x540 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0100*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x001ea2000c1e1b00 */
/*0110*/ ISETP.GT.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04070 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0130*/ SHF.R.S32.HI R13, RZ, 0x1f, R10 ; /* 0x0000001fff0d7819 */
/* 0x000fe2000001140a */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 IADD3 R14, P1, R8, R11, RZ ; /* 0x0000000b080e8210 */
/* 0x004fca0007f3e0ff */
/*0170*/ @!P0 IMAD.X R15, R9, 0x1, R0, P1 ; /* 0x00000001090f8824 */
/* 0x000fca00008e0600 */
/*0180*/ @!P0 LDG.E.U8 R17, [R14.64] ; /* 0x000000060e118981 */
/* 0x0000a4000c1e1100 */
/*0190*/ @!P0 IADD3 R14, P1, R11, R2, RZ ; /* 0x000000020b0e8210 */
/* 0x021fe20007f3e0ff */
/*01a0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b8424 */
/* 0x000fc800078e00ff */
/*01b0*/ @!P0 IMAD.X R15, R0, 0x1, R3, P1 ; /* 0x00000001000f8824 */
/* 0x000fe200008e0603 */
/*01c0*/ IADD3 R12, P3, R10.reuse, -R11.reuse, RZ ; /* 0x8000000b0a0c7210 */
/* 0x0c0fe20007f7e0ff */
/*01d0*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff008224 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe40003f44070 */
/*01f0*/ ISETP.LE.U32.AND P1, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe20003f23070 */
/*0200*/ IMAD.X R12, R13.reuse, 0x1, ~R0, P3 ; /* 0x000000010d0c7824 */
/* 0x040fe200018e0e00 */
/*0210*/ ISETP.GT.U32.AND.EX P2, PT, R13, R0, PT, P2 ; /* 0x000000000d00720c */
/* 0x000fc80003f44120 */
/*0220*/ ISETP.LE.U32.OR.EX P1, PT, R12, RZ, !P2, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe20005723510 */
/*0230*/ @!P0 STG.E.U8 [R14.64], R17 ; /* 0x000000110e008986 */
/* 0x0041d8000c101106 */
/*0240*/ @P1 BRA 0x390 ; /* 0x0000014000001947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R12, P1, R10, -0x3, RZ ; /* 0xfffffffd0a0c7810 */
/* 0x000fe40007f3e0ff */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0270*/ IADD3.X R27, R13, -0x1, RZ, P1, !PT ; /* 0xffffffff0d1b7810 */
/* 0x000fe40000ffe4ff */
/*0280*/ IADD3 R16, P1, R8, R11, RZ ; /* 0x0000000b08107210 */
/* 0x000fca0007f3e0ff */
/*0290*/ IMAD.X R17, R9, 0x1, R0, P1 ; /* 0x0000000109117824 */
/* 0x001fca00008e0600 */
/*02a0*/ LDG.E.U8 R19, [R16.64] ; /* 0x0000000610137981 */
/* 0x000ea2000c1e1100 */
/*02b0*/ IADD3 R14, P1, R11, R2, RZ ; /* 0x000000020b0e7210 */
/* 0x000fca0007f3e0ff */
/*02c0*/ IMAD.X R15, R0, 0x1, R3, P1 ; /* 0x00000001000f7824 */
/* 0x000fca00008e0603 */
/*02d0*/ STG.E.U8 [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0041e8000c101106 */
/*02e0*/ LDG.E.U8 R21, [R16.64+0x1] ; /* 0x0000010610157981 */
/* 0x000ea8000c1e1100 */
/*02f0*/ STG.E.U8 [R14.64+0x1], R21 ; /* 0x000001150e007986 */
/* 0x0041e8000c101106 */
/*0300*/ LDG.E.U8 R23, [R16.64+0x2] ; /* 0x0000020610177981 */
/* 0x000ea2000c1e1100 */
/*0310*/ IADD3 R11, P2, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc80007f5e0ff */
/*0320*/ ISETP.GE.U32.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe20003f26070 */
/*0330*/ IMAD.X R0, RZ, RZ, R0, P2 ; /* 0x000000ffff007224 */
/* 0x000fca00010e0600 */
/*0340*/ ISETP.GE.U32.AND.EX P1, PT, R0, R27, PT, P1 ; /* 0x0000001b0000720c */
/* 0x000fe20003f26110 */
/*0350*/ STG.E.U8 [R14.64+0x2], R23 ; /* 0x000002170e007986 */
/* 0x0041e8000c101106 */
/*0360*/ LDG.E.U8 R25, [R16.64+0x3] ; /* 0x0000030610197981 */
/* 0x000ea8000c1e1100 */
/*0370*/ STG.E.U8 [R14.64+0x3], R25 ; /* 0x000003190e007986 */
/* 0x0041e8000c101106 */
/*0380*/ @!P1 BRA 0x280 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*0390*/ IADD3 R12, P3, R10.reuse, -R11.reuse, RZ ; /* 0x8000000b0a0c7210 */
/* 0x0c0fe40007f7e0ff */
/*03a0*/ ISETP.GT.U32.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fc40003f44070 */
/*03b0*/ ISETP.LE.U32.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe20003f23070 */
/*03c0*/ IMAD.X R12, R13.reuse, 0x1, ~R0, P3 ; /* 0x000000010d0c7824 */
/* 0x040fe200018e0e00 */
/*03d0*/ ISETP.GT.U32.AND.EX P2, PT, R13, R0, PT, P2 ; /* 0x000000000d00720c */
/* 0x000fc80003f44120 */
/*03e0*/ ISETP.LE.U32.OR.EX P1, PT, R12, RZ, !P2, P1 ; /* 0x000000ff0c00720c */
/* 0x000fda0005723510 */
/*03f0*/ @!P1 IADD3 R14, P2, R8, R11, RZ ; /* 0x0000000b080e9210 */
/* 0x001fca0007f5e0ff */
/*0400*/ @!P1 IMAD.X R15, R9, 0x1, R0, P2 ; /* 0x00000001090f9824 */
/* 0x000fca00010e0600 */
/*0410*/ @!P1 LDG.E.U8 R19, [R14.64] ; /* 0x000000060e139981 */
/* 0x000ea2000c1e1100 */
/*0420*/ @!P1 IADD3 R16, P2, R11, R2, RZ ; /* 0x000000020b109210 */
/* 0x000fca0007f5e0ff */
/*0430*/ @!P1 IMAD.X R17, R0, 0x1, R3, P2 ; /* 0x0000000100119824 */
/* 0x000fe200010e0603 */
/*0440*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe40003f0e170 */
/*0450*/ @!P1 IADD3 R11, P3, R11, 0x2, RZ ; /* 0x000000020b0b9810 */
/* 0x000fc80007f7e0ff */
/*0460*/ ISETP.LT.U32.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fe20003f41070 */
/*0470*/ @!P1 IMAD.X R0, RZ, RZ, R0, P3 ; /* 0x000000ffff009224 */
/* 0x000fcc00018e0600 */
/*0480*/ ISETP.LT.U32.OR.EX P0, PT, R0, R13, P0, P2 ; /* 0x0000000d0000720c */
/* 0x000fe20000701520 */
/*0490*/ @!P1 STG.E.U8 [R16.64], R19 ; /* 0x0000001310009986 */
/* 0x0041e8000c101106 */
/*04a0*/ @!P1 LDG.E.U8 R21, [R14.64+0x1] ; /* 0x000001060e159981 */
/* 0x000eb0000c1e1100 */
/*04b0*/ @P0 IADD3 R8, P2, R8, R11, RZ ; /* 0x0000000b08080210 */
/* 0x000fca0007f5e0ff */
/*04c0*/ @P0 IMAD.X R9, R9, 0x1, R0, P2 ; /* 0x0000000109090824 */
/* 0x000fe200010e0600 */
/*04d0*/ @!P1 STG.E.U8 [R16.64+0x1], R21 ; /* 0x0000011510009986 */
/* 0x0041ea000c101106 */
/*04e0*/ @P0 LDG.E.U8 R9, [R8.64] ; /* 0x0000000608090981 */
/* 0x000ea2000c1e1100 */
/*04f0*/ @P0 IADD3 R10, P1, R11, R2, RZ ; /* 0x000000020b0a0210 */
/* 0x000fca0007f3e0ff */
/*0500*/ @P0 IMAD.X R11, R0, 0x1, R3, P1 ; /* 0x00000001000b0824 */
/* 0x000fca00008e0603 */
/*0510*/ @P0 STG.E.U8 [R10.64], R9 ; /* 0x000000090a000986 */
/* 0x0041e8000c101106 */
/*0520*/ LDG.E R12, [R6.64+-0x8] ; /* 0xfffff806060c7981 */
/* 0x000168000c1e1900 */
/*0530*/ LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080604027981 */
/* 0x000164000c1e1b00 */
/*0540*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x001fe400078e00ff */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0560*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea4000c1e1900 */
/*0570*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0580*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.64 R4, [R4.64+0x8] ; /* 0x0000080604047981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ ISETP.GT.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f04070 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*05c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R0 ; /* 0x0000001fff087819 */
/* 0x000fe20000011400 */
/*05d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*05e0*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04100 */
/*05f0*/ @!P0 IADD3 R10, P1, R4, R9, RZ ; /* 0x00000009040a8210 */
/* 0x004fca0007f3e0ff */
/*0600*/ @!P0 IMAD.X R11, R5, 0x1, R7, P1 ; /* 0x00000001050b8824 */
/* 0x000fca00008e0607 */
/*0610*/ @!P0 LDG.E.U8 R13, [R10.64] ; /* 0x000000060a0d8981 */
/* 0x0000a2000c1e1100 */
/*0620*/ IADD3 R6, P1, R12, R2, RZ ; /* 0x000000020c067210 */
/* 0x020fc80007f3e0ff */
/*0630*/ LEA.HI.X.SX32 R2, R12, R3, 0x1, P1 ; /* 0x000000030c027211 */
/* 0x000fe400008f0eff */
/*0640*/ @!P0 IADD3 R10, P1, R9, R6, RZ ; /* 0x00000006090a8210 */
/* 0x001fe20007f3e0ff */
/*0650*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff098424 */
/* 0x000fc800078e00ff */
/*0660*/ @!P0 IMAD.X R11, R7, 0x1, R2, P1 ; /* 0x00000001070b8824 */
/* 0x000fe200008e0602 */
/*0670*/ IADD3 R3, P3, R0.reuse, -R9.reuse, RZ ; /* 0x8000000900037210 */
/* 0x0c0fe20007f7e0ff */
/*0680*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0690*/ ISETP.GT.U32.AND P2, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f44070 */
/*06a0*/ ISETP.LE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f23070 */
/*06b0*/ IMAD.X R3, R8.reuse, 0x1, ~R7, P3 ; /* 0x0000000108037824 */
/* 0x040fe200018e0e07 */
/*06c0*/ ISETP.GT.U32.AND.EX P2, PT, R8, R7, PT, P2 ; /* 0x000000070800720c */
/* 0x000fc80003f44120 */
/*06d0*/ ISETP.LE.U32.OR.EX P1, PT, R3, RZ, !P2, P1 ; /* 0x000000ff0300720c */
/* 0x000fe20005723510 */
/*06e0*/ @!P0 STG.E.U8 [R10.64], R13 ; /* 0x0000000d0a008986 */
/* 0x0041d8000c101106 */
/*06f0*/ @P1 BRA 0x840 ; /* 0x0000014000001947 */
/* 0x000fea0003800000 */
/*0700*/ IADD3 R14, P1, R0, -0x3, RZ ; /* 0xfffffffd000e7810 */
/* 0x000fe40007f3e0ff */
/*0710*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0720*/ IADD3.X R16, R8, -0x1, RZ, P1, !PT ; /* 0xffffffff08107810 */
/* 0x000fe40000ffe4ff */
/*0730*/ IADD3 R12, P1, R4, R9, RZ ; /* 0x00000009040c7210 */
/* 0x000fca0007f3e0ff */
/*0740*/ IMAD.X R13, R5, 0x1, R7, P1 ; /* 0x00000001050d7824 */
/* 0x001fca00008e0607 */
/*0750*/ LDG.E.U8 R3, [R12.64] ; /* 0x000000060c037981 */
/* 0x000ea2000c1e1100 */
/*0760*/ IADD3 R10, P1, R9, R6, RZ ; /* 0x00000006090a7210 */
/* 0x000fca0007f3e0ff */
/*0770*/ IMAD.X R11, R7, 0x1, R2, P1 ; /* 0x00000001070b7824 */
/* 0x000fca00008e0602 */
/*0780*/ STG.E.U8 [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x0041e8000c101106 */
/*0790*/ LDG.E.U8 R15, [R12.64+0x1] ; /* 0x000001060c0f7981 */
/* 0x000ea8000c1e1100 */
/*07a0*/ STG.E.U8 [R10.64+0x1], R15 ; /* 0x0000010f0a007986 */
/* 0x0041e8000c101106 */
/*07b0*/ LDG.E.U8 R17, [R12.64+0x2] ; /* 0x000002060c117981 */
/* 0x000ea2000c1e1100 */
/*07c0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc80007f5e0ff */
/*07d0*/ ISETP.GE.U32.AND P1, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fe20003f26070 */
/*07e0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fca00010e0607 */
/*07f0*/ ISETP.GE.U32.AND.EX P1, PT, R7, R16, PT, P1 ; /* 0x000000100700720c */
/* 0x000fe20003f26110 */
/*0800*/ STG.E.U8 [R10.64+0x2], R17 ; /* 0x000002110a007986 */
/* 0x0041e8000c101106 */
/*0810*/ LDG.E.U8 R19, [R12.64+0x3] ; /* 0x000003060c137981 */
/* 0x000ea8000c1e1100 */
/*0820*/ STG.E.U8 [R10.64+0x3], R19 ; /* 0x000003130a007986 */
/* 0x0041e8000c101106 */
/*0830*/ @!P1 BRA 0x730 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*0840*/ IADD3 R3, P3, R0.reuse, -R9.reuse, RZ ; /* 0x8000000900037210 */
/* 0x0c1fe40007f7e0ff */
/*0850*/ ISETP.GT.U32.AND P2, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fc40003f44070 */
/*0860*/ ISETP.LE.U32.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f23070 */
/*0870*/ IMAD.X R3, R8.reuse, 0x1, ~R7, P3 ; /* 0x0000000108037824 */
/* 0x040fe200018e0e07 */
/*0880*/ ISETP.GT.U32.AND.EX P2, PT, R8, R7, PT, P2 ; /* 0x000000070800720c */
/* 0x000fc80003f44120 */
/*0890*/ ISETP.LE.U32.OR.EX P1, PT, R3, RZ, !P2, P1 ; /* 0x000000ff0300720c */
/* 0x000fda0005723510 */
/*08a0*/ @!P1 IADD3 R10, P2, R4, R9, RZ ; /* 0x00000009040a9210 */
/* 0x000fca0007f5e0ff */
/*08b0*/ @!P1 IMAD.X R11, R5, 0x1, R7, P2 ; /* 0x00000001050b9824 */
/* 0x000fca00010e0607 */
/*08c0*/ @!P1 LDG.E.U8 R3, [R10.64] ; /* 0x000000060a039981 */
/* 0x000ea2000c1e1100 */
/*08d0*/ @!P1 IADD3 R12, P2, R9, R6, RZ ; /* 0x00000006090c9210 */
/* 0x000fca0007f5e0ff */
/*08e0*/ @!P1 IMAD.X R13, R7, 0x1, R2, P2 ; /* 0x00000001070d9824 */
/* 0x000fe200010e0602 */
/*08f0*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe40003f0e170 */
/*0900*/ @!P1 IADD3 R9, P3, R9, 0x2, RZ ; /* 0x0000000209099810 */
/* 0x000fc80007f7e0ff */
/*0910*/ ISETP.LT.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f41070 */
/*0920*/ @!P1 IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff079224 */
/* 0x000fe200018e0607 */
/*0930*/ @!P1 STG.E.U8 [R12.64], R3 ; /* 0x000000030c009986 */
/* 0x0041e8000c101106 */
/*0940*/ @!P1 LDG.E.U8 R15, [R10.64+0x1] ; /* 0x000001060a0f9981 */
/* 0x000ea2000c1e1100 */
/*0950*/ ISETP.LT.U32.OR.EX P0, PT, R7, R8, P0, P2 ; /* 0x000000080700720c */
/* 0x000fc60000701520 */
/*0960*/ @!P1 STG.E.U8 [R12.64+0x1], R15 ; /* 0x0000010f0c009986 */
/* 0x0041f4000c101106 */
/*0970*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0980*/ IADD3 R4, P0, R4, R9, RZ ; /* 0x0000000904047210 */
/* 0x000fca0007f1e0ff */
/*0990*/ IMAD.X R5, R5, 0x1, R7, P0 ; /* 0x0000000105057824 */
/* 0x000fcc00000e0607 */
/*09a0*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1100 */
/*09b0*/ IADD3 R6, P0, R9, R6, RZ ; /* 0x0000000609067210 */
/* 0x000fca0007f1e0ff */
/*09c0*/ IMAD.X R7, R7, 0x1, R2, P0 ; /* 0x0000000107077824 */
/* 0x000fca00000e0602 */
/*09d0*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101106 */
/*09e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
// a struct
typedef struct
{
int size;
char *_string;
} string_t;
__global__ void string_append(string_t*, string_t*, string_t*);
int main(void)
{
string_t *str1, *str2, *str3;
size_t size1 = strlen("Hello, ");
size_t size2 = sizeof("world!");
// allocate memory for str1, str2, and str3
// and for their string members.
cudaMallocManaged(&str1, sizeof(string_t));
cudaMallocManaged(&(str1->_string), size1*sizeof(char));
cudaMallocManaged(&str2, sizeof(string_t));
cudaMallocManaged(&(str2->_string), size2*sizeof(char));
cudaMallocManaged(&str3, sizeof(string_t));
cudaMallocManaged(&(str3->_string), (size1+size2) * sizeof(char));
// the CPU and the GPU can directly access memory allocated to str's
//In the following 4 lines the Host is accessing
// the memory allocated via cudaMallocManaged().
str1->size = size1;
memcpy(str1->_string, "Hello, ", size1);
str2->size = size2;
memcpy(str2->_string, "world!", size2);
// Since the kernel has been declared/defined with
// "__global__" keyword we are sure it will run on the device.
// So the device will be accessing memory allocated via cudaMallocManaged().
string_append<<<1, 1>>>(str1, str2, str3);
// the device and the host should be synchronized
// before we call printf in the host.
cudaDeviceSynchronize();
printf("%s\n", str3->_string);
exit(EXIT_SUCCESS);
}
// a kernel to append 2 strings in a 3rd string.
__global__ void string_append(string_t *s1, string_t *s2, string_t *s3)
{
memcpy(s3->_string, s1->_string, s1->size);
memcpy(s3->_string+(s1->size), s2->_string, s2->size);
} | .file "tmpxft_000f5b43_00000000-6_unifMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
.type _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_, @function
_Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13string_appendP8string_tS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_, .-_Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
.globl _Z13string_appendP8string_tS0_S0_
.type _Z13string_appendP8string_tS0_S0_, @function
_Z13string_appendP8string_tS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13string_appendP8string_tS0_S0_, .-_Z13string_appendP8string_tS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %edx
movl $7, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 16(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %edx
movl $7, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 24(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %edx
movl $14, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
movl $7, (%rax)
movq 8(%rsp), %rax
movq 8(%rax), %rax
movl $1819043144, (%rax)
movl $539783020, 3(%rax)
movq 16(%rsp), %rax
movl $7, (%rax)
movq 16(%rsp), %rax
movq 8(%rax), %rax
movl $1819438967, (%rax)
movl $2188396, 3(%rax)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
movq 8(%rax), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L15:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z13string_appendP8string_tS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13string_appendP8string_tS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
// a struct
typedef struct
{
int size;
char *_string;
} string_t;
__global__ void string_append(string_t*, string_t*, string_t*);
int main(void)
{
string_t *str1, *str2, *str3;
size_t size1 = strlen("Hello, ");
size_t size2 = sizeof("world!");
// allocate memory for str1, str2, and str3
// and for their string members.
cudaMallocManaged(&str1, sizeof(string_t));
cudaMallocManaged(&(str1->_string), size1*sizeof(char));
cudaMallocManaged(&str2, sizeof(string_t));
cudaMallocManaged(&(str2->_string), size2*sizeof(char));
cudaMallocManaged(&str3, sizeof(string_t));
cudaMallocManaged(&(str3->_string), (size1+size2) * sizeof(char));
// the CPU and the GPU can directly access memory allocated to str's
//In the following 4 lines the Host is accessing
// the memory allocated via cudaMallocManaged().
str1->size = size1;
memcpy(str1->_string, "Hello, ", size1);
str2->size = size2;
memcpy(str2->_string, "world!", size2);
// Since the kernel has been declared/defined with
// "__global__" keyword we are sure it will run on the device.
// So the device will be accessing memory allocated via cudaMallocManaged().
string_append<<<1, 1>>>(str1, str2, str3);
// the device and the host should be synchronized
// before we call printf in the host.
cudaDeviceSynchronize();
printf("%s\n", str3->_string);
exit(EXIT_SUCCESS);
}
// a kernel to append 2 strings in a 3rd string.
__global__ void string_append(string_t *s1, string_t *s2, string_t *s3)
{
memcpy(s3->_string, s1->_string, s1->size);
memcpy(s3->_string+(s1->size), s2->_string, s2->size);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
// a struct
typedef struct
{
int size;
char *_string;
} string_t;
__global__ void string_append(string_t*, string_t*, string_t*);
int main(void)
{
string_t *str1, *str2, *str3;
size_t size1 = strlen("Hello, ");
size_t size2 = sizeof("world!");
// allocate memory for str1, str2, and str3
// and for their string members.
hipMallocManaged(&str1, sizeof(string_t));
hipMallocManaged(&(str1->_string), size1*sizeof(char));
hipMallocManaged(&str2, sizeof(string_t));
hipMallocManaged(&(str2->_string), size2*sizeof(char));
hipMallocManaged(&str3, sizeof(string_t));
hipMallocManaged(&(str3->_string), (size1+size2) * sizeof(char));
// the CPU and the GPU can directly access memory allocated to str's
//In the following 4 lines the Host is accessing
// the memory allocated via cudaMallocManaged().
str1->size = size1;
memcpy(str1->_string, "Hello, ", size1);
str2->size = size2;
memcpy(str2->_string, "world!", size2);
// Since the kernel has been declared/defined with
// "__global__" keyword we are sure it will run on the device.
// So the device will be accessing memory allocated via cudaMallocManaged().
string_append<<<1, 1>>>(str1, str2, str3);
// the device and the host should be synchronized
// before we call printf in the host.
hipDeviceSynchronize();
printf("%s\n", str3->_string);
exit(EXIT_SUCCESS);
}
// a kernel to append 2 strings in a 3rd string.
__global__ void string_append(string_t *s1, string_t *s2, string_t *s3)
{
memcpy(s3->_string, s1->_string, s1->size);
memcpy(s3->_string+(s1->size), s2->_string, s2->size);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
// a struct
typedef struct
{
int size;
char *_string;
} string_t;
__global__ void string_append(string_t*, string_t*, string_t*);
int main(void)
{
string_t *str1, *str2, *str3;
size_t size1 = strlen("Hello, ");
size_t size2 = sizeof("world!");
// allocate memory for str1, str2, and str3
// and for their string members.
hipMallocManaged(&str1, sizeof(string_t));
hipMallocManaged(&(str1->_string), size1*sizeof(char));
hipMallocManaged(&str2, sizeof(string_t));
hipMallocManaged(&(str2->_string), size2*sizeof(char));
hipMallocManaged(&str3, sizeof(string_t));
hipMallocManaged(&(str3->_string), (size1+size2) * sizeof(char));
// the CPU and the GPU can directly access memory allocated to str's
//In the following 4 lines the Host is accessing
// the memory allocated via cudaMallocManaged().
str1->size = size1;
memcpy(str1->_string, "Hello, ", size1);
str2->size = size2;
memcpy(str2->_string, "world!", size2);
// Since the kernel has been declared/defined with
// "__global__" keyword we are sure it will run on the device.
// So the device will be accessing memory allocated via cudaMallocManaged().
string_append<<<1, 1>>>(str1, str2, str3);
// the device and the host should be synchronized
// before we call printf in the host.
hipDeviceSynchronize();
printf("%s\n", str3->_string);
exit(EXIT_SUCCESS);
}
// a kernel to append 2 strings in a 3rd string.
__global__ void string_append(string_t *s1, string_t *s2, string_t *s3)
{
memcpy(s3->_string, s1->_string, s1->size);
memcpy(s3->_string+(s1->size), s2->_string, s2->size);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13string_appendP8string_tS0_S0_
.globl _Z13string_appendP8string_tS0_S0_
.p2align 8
.type _Z13string_appendP8string_tS0_S0_,@function
_Z13string_appendP8string_tS0_S0_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[2:3], 0x0
s_load_b64 s[6:7], s[4:5], 0x8
s_load_b64 s[8:9], s[2:3], 0x8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u64_e64 s12, s[10:11], 4
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
.p2align 6
.LBB0_1:
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_add_u32 s10, s10, -4
s_addc_u32 s11, s11, -1
flat_load_u8 v4, v[0:1]
v_cmp_gt_u64_e64 s12, s[10:11], 3
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v4
flat_load_u8 v4, v[0:1] offset:1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v4 offset:1
flat_load_u8 v4, v[0:1] offset:2
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v4 offset:2
flat_load_u8 v0, v[0:1] offset:3
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v0 offset:3
s_cbranch_vccnz .LBB0_1
.LBB0_2:
v_cmp_lt_i64_e64 s12, s[10:11], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_8
v_cmp_gt_i64_e64 s12, s[10:11], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_mov_b32 s12, -1
s_cbranch_vccz .LBB0_6
s_cmp_eq_u64 s[10:11], 3
s_mov_b32 s12, 0
s_cbranch_scc0 .LBB0_6
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
s_mov_b32 s12, -1
flat_load_u8 v2, v[0:1] offset:2
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[0:1], v2 offset:2
.LBB0_6:
s_mov_b32 s13, 0
s_and_b32 vcc_lo, exec_lo, s12
s_mov_b32 s12, 0
s_cbranch_vccz .LBB0_9
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
s_mov_b32 s12, -1
flat_load_u8 v2, v[0:1] offset:1
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[0:1], v2 offset:1
s_branch .LBB0_9
.LBB0_8:
s_mov_b32 s13, -1
s_mov_b32 s12, 0
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccz .LBB0_11
s_cmp_eq_u64 s[10:11], 1
s_cselect_b32 s12, -1, 0
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_13
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
flat_load_u8 v2, v[0:1]
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[0:1], v2
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x3
global_load_b32 v4, v0, s[0:1]
global_load_b32 v6, v0, s[2:3]
global_load_b64 v[2:3], v0, s[4:5] offset:8
global_load_b64 v[0:1], v0, s[0:1] offset:8
s_waitcnt vmcnt(3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(2)
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt vmcnt(1)
v_add_co_u32 v2, s0, v2, v6
v_cmp_gt_u64_e32 vcc_lo, 4, v[4:5]
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, v3, v7, s0
s_cbranch_vccnz .LBB0_15
.p2align 6
.LBB0_14:
s_waitcnt vmcnt(0)
flat_load_u8 v6, v[0:1]
v_add_co_u32 v4, vcc_lo, v4, -4
v_add_co_ci_u32_e32 v5, vcc_lo, -1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u64_e32 vcc_lo, 3, v[4:5]
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6
flat_load_u8 v6, v[0:1] offset:1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:1
flat_load_u8 v6, v[0:1] offset:2
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:2
flat_load_u8 v6, v[0:1] offset:3
v_add_co_u32 v0, s0, v0, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:3
v_add_co_u32 v2, s0, v2, 4
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_cbranch_vccnz .LBB0_14
.LBB0_15:
v_cmp_gt_i64_e32 vcc_lo, 2, v[4:5]
s_cbranch_vccnz .LBB0_21
v_cmp_lt_i64_e32 vcc_lo, 2, v[4:5]
s_mov_b32 s0, -1
s_cbranch_vccz .LBB0_19
v_cmp_eq_u64_e32 vcc_lo, 3, v[4:5]
s_mov_b32 s0, 0
s_cbranch_vccz .LBB0_19
s_waitcnt vmcnt(0)
flat_load_u8 v6, v[0:1] offset:2
s_mov_b32 s0, -1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:2
.LBB0_19:
s_mov_b32 s1, 0
s_and_b32 vcc_lo, exec_lo, s0
s_mov_b32 s0, 0
s_cbranch_vccz .LBB0_22
s_waitcnt vmcnt(0)
flat_load_u8 v6, v[0:1] offset:1
s_mov_b32 s0, -1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:1
s_branch .LBB0_22
.LBB0_21:
s_mov_b32 s1, -1
s_mov_b32 s0, 0
.LBB0_22:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_25
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_26
.LBB0_24:
s_endpgm
.LBB0_25:
v_cmp_eq_u64_e64 s0, 1, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_24
.LBB0_26:
s_waitcnt vmcnt(0)
flat_load_u8 v0, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v0
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13string_appendP8string_tS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13string_appendP8string_tS0_S0_, .Lfunc_end0-_Z13string_appendP8string_tS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13string_appendP8string_tS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z13string_appendP8string_tS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
// a struct
typedef struct
{
int size;
char *_string;
} string_t;
__global__ void string_append(string_t*, string_t*, string_t*);
int main(void)
{
string_t *str1, *str2, *str3;
size_t size1 = strlen("Hello, ");
size_t size2 = sizeof("world!");
// allocate memory for str1, str2, and str3
// and for their string members.
hipMallocManaged(&str1, sizeof(string_t));
hipMallocManaged(&(str1->_string), size1*sizeof(char));
hipMallocManaged(&str2, sizeof(string_t));
hipMallocManaged(&(str2->_string), size2*sizeof(char));
hipMallocManaged(&str3, sizeof(string_t));
hipMallocManaged(&(str3->_string), (size1+size2) * sizeof(char));
// the CPU and the GPU can directly access memory allocated to str's
//In the following 4 lines the Host is accessing
// the memory allocated via cudaMallocManaged().
str1->size = size1;
memcpy(str1->_string, "Hello, ", size1);
str2->size = size2;
memcpy(str2->_string, "world!", size2);
// Since the kernel has been declared/defined with
// "__global__" keyword we are sure it will run on the device.
// So the device will be accessing memory allocated via cudaMallocManaged().
string_append<<<1, 1>>>(str1, str2, str3);
// the device and the host should be synchronized
// before we call printf in the host.
hipDeviceSynchronize();
printf("%s\n", str3->_string);
exit(EXIT_SUCCESS);
}
// a kernel to append 2 strings in a 3rd string.
__global__ void string_append(string_t *s1, string_t *s2, string_t *s3)
{
memcpy(s3->_string, s1->_string, s1->size);
memcpy(s3->_string+(s1->size), s2->_string, s2->size);
} | .text
.file "unifMem.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 16(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
addq $8, %rdi
movl $7, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
addq $8, %rdi
movl $7, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rdi
addq $8, %rdi
movl $14, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movl $7, (%rax)
movq 8(%rax), %rax
movl $539783020, 3(%rax) # imm = 0x202C6F6C
movl $1819043144, (%rax) # imm = 0x6C6C6548
movq 8(%rsp), %rax
movl $7, (%rax)
movq 8(%rax), %rax
movl $1819438967, (%rax) # imm = 0x6C726F77
movl $2188396, 3(%rax) # imm = 0x21646C
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13string_appendP8string_tS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movq (%rsp), %rax
movq 8(%rax), %rdi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z28__device_stub__string_appendP8string_tS0_S0_ # -- Begin function _Z28__device_stub__string_appendP8string_tS0_S0_
.p2align 4, 0x90
.type _Z28__device_stub__string_appendP8string_tS0_S0_,@function
_Z28__device_stub__string_appendP8string_tS0_S0_: # @_Z28__device_stub__string_appendP8string_tS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13string_appendP8string_tS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__string_appendP8string_tS0_S0_, .Lfunc_end1-_Z28__device_stub__string_appendP8string_tS0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13string_appendP8string_tS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello, "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "world!"
.size .L.str.1, 7
.type _Z13string_appendP8string_tS0_S0_,@object # @_Z13string_appendP8string_tS0_S0_
.section .rodata,"a",@progbits
.globl _Z13string_appendP8string_tS0_S0_
.p2align 3, 0x0
_Z13string_appendP8string_tS0_S0_:
.quad _Z28__device_stub__string_appendP8string_tS0_S0_
.size _Z13string_appendP8string_tS0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13string_appendP8string_tS0_S0_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__string_appendP8string_tS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13string_appendP8string_tS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13string_appendP8string_tS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0a7624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0b7624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fc80000000a00 */
/*0050*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1900 */
/*0060*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000ff1e03f */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*00a0*/ IMAD.U32 R6, RZ, RZ, UR4 ; /* 0x00000004ff067e24 */
/* 0x000fe4000f8e00ff */
/*00b0*/ LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080604027981 */
/* 0x000162000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x000fe2000f8e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 BRA 0x540 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*0100*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x001ea2000c1e1b00 */
/*0110*/ ISETP.GT.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04070 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0130*/ SHF.R.S32.HI R13, RZ, 0x1f, R10 ; /* 0x0000001fff0d7819 */
/* 0x000fe2000001140a */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 IADD3 R14, P1, R8, R11, RZ ; /* 0x0000000b080e8210 */
/* 0x004fca0007f3e0ff */
/*0170*/ @!P0 IMAD.X R15, R9, 0x1, R0, P1 ; /* 0x00000001090f8824 */
/* 0x000fca00008e0600 */
/*0180*/ @!P0 LDG.E.U8 R17, [R14.64] ; /* 0x000000060e118981 */
/* 0x0000a4000c1e1100 */
/*0190*/ @!P0 IADD3 R14, P1, R11, R2, RZ ; /* 0x000000020b0e8210 */
/* 0x021fe20007f3e0ff */
/*01a0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b8424 */
/* 0x000fc800078e00ff */
/*01b0*/ @!P0 IMAD.X R15, R0, 0x1, R3, P1 ; /* 0x00000001000f8824 */
/* 0x000fe200008e0603 */
/*01c0*/ IADD3 R12, P3, R10.reuse, -R11.reuse, RZ ; /* 0x8000000b0a0c7210 */
/* 0x0c0fe20007f7e0ff */
/*01d0*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff008224 */
/* 0x000fe200078e00ff */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fe40003f44070 */
/*01f0*/ ISETP.LE.U32.AND P1, PT, R12, 0x3, PT ; /* 0x000000030c00780c */
/* 0x000fe20003f23070 */
/*0200*/ IMAD.X R12, R13.reuse, 0x1, ~R0, P3 ; /* 0x000000010d0c7824 */
/* 0x040fe200018e0e00 */
/*0210*/ ISETP.GT.U32.AND.EX P2, PT, R13, R0, PT, P2 ; /* 0x000000000d00720c */
/* 0x000fc80003f44120 */
/*0220*/ ISETP.LE.U32.OR.EX P1, PT, R12, RZ, !P2, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe20005723510 */
/*0230*/ @!P0 STG.E.U8 [R14.64], R17 ; /* 0x000000110e008986 */
/* 0x0041d8000c101106 */
/*0240*/ @P1 BRA 0x390 ; /* 0x0000014000001947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R12, P1, R10, -0x3, RZ ; /* 0xfffffffd0a0c7810 */
/* 0x000fe40007f3e0ff */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0270*/ IADD3.X R27, R13, -0x1, RZ, P1, !PT ; /* 0xffffffff0d1b7810 */
/* 0x000fe40000ffe4ff */
/*0280*/ IADD3 R16, P1, R8, R11, RZ ; /* 0x0000000b08107210 */
/* 0x000fca0007f3e0ff */
/*0290*/ IMAD.X R17, R9, 0x1, R0, P1 ; /* 0x0000000109117824 */
/* 0x001fca00008e0600 */
/*02a0*/ LDG.E.U8 R19, [R16.64] ; /* 0x0000000610137981 */
/* 0x000ea2000c1e1100 */
/*02b0*/ IADD3 R14, P1, R11, R2, RZ ; /* 0x000000020b0e7210 */
/* 0x000fca0007f3e0ff */
/*02c0*/ IMAD.X R15, R0, 0x1, R3, P1 ; /* 0x00000001000f7824 */
/* 0x000fca00008e0603 */
/*02d0*/ STG.E.U8 [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0041e8000c101106 */
/*02e0*/ LDG.E.U8 R21, [R16.64+0x1] ; /* 0x0000010610157981 */
/* 0x000ea8000c1e1100 */
/*02f0*/ STG.E.U8 [R14.64+0x1], R21 ; /* 0x000001150e007986 */
/* 0x0041e8000c101106 */
/*0300*/ LDG.E.U8 R23, [R16.64+0x2] ; /* 0x0000020610177981 */
/* 0x000ea2000c1e1100 */
/*0310*/ IADD3 R11, P2, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc80007f5e0ff */
/*0320*/ ISETP.GE.U32.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe20003f26070 */
/*0330*/ IMAD.X R0, RZ, RZ, R0, P2 ; /* 0x000000ffff007224 */
/* 0x000fca00010e0600 */
/*0340*/ ISETP.GE.U32.AND.EX P1, PT, R0, R27, PT, P1 ; /* 0x0000001b0000720c */
/* 0x000fe20003f26110 */
/*0350*/ STG.E.U8 [R14.64+0x2], R23 ; /* 0x000002170e007986 */
/* 0x0041e8000c101106 */
/*0360*/ LDG.E.U8 R25, [R16.64+0x3] ; /* 0x0000030610197981 */
/* 0x000ea8000c1e1100 */
/*0370*/ STG.E.U8 [R14.64+0x3], R25 ; /* 0x000003190e007986 */
/* 0x0041e8000c101106 */
/*0380*/ @!P1 BRA 0x280 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*0390*/ IADD3 R12, P3, R10.reuse, -R11.reuse, RZ ; /* 0x8000000b0a0c7210 */
/* 0x0c0fe40007f7e0ff */
/*03a0*/ ISETP.GT.U32.AND P2, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fc40003f44070 */
/*03b0*/ ISETP.LE.U32.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fe20003f23070 */
/*03c0*/ IMAD.X R12, R13.reuse, 0x1, ~R0, P3 ; /* 0x000000010d0c7824 */
/* 0x040fe200018e0e00 */
/*03d0*/ ISETP.GT.U32.AND.EX P2, PT, R13, R0, PT, P2 ; /* 0x000000000d00720c */
/* 0x000fc80003f44120 */
/*03e0*/ ISETP.LE.U32.OR.EX P1, PT, R12, RZ, !P2, P1 ; /* 0x000000ff0c00720c */
/* 0x000fda0005723510 */
/*03f0*/ @!P1 IADD3 R14, P2, R8, R11, RZ ; /* 0x0000000b080e9210 */
/* 0x001fca0007f5e0ff */
/*0400*/ @!P1 IMAD.X R15, R9, 0x1, R0, P2 ; /* 0x00000001090f9824 */
/* 0x000fca00010e0600 */
/*0410*/ @!P1 LDG.E.U8 R19, [R14.64] ; /* 0x000000060e139981 */
/* 0x000ea2000c1e1100 */
/*0420*/ @!P1 IADD3 R16, P2, R11, R2, RZ ; /* 0x000000020b109210 */
/* 0x000fca0007f5e0ff */
/*0430*/ @!P1 IMAD.X R17, R0, 0x1, R3, P2 ; /* 0x0000000100119824 */
/* 0x000fe200010e0603 */
/*0440*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe40003f0e170 */
/*0450*/ @!P1 IADD3 R11, P3, R11, 0x2, RZ ; /* 0x000000020b0b9810 */
/* 0x000fc80007f7e0ff */
/*0460*/ ISETP.LT.U32.AND P2, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fe20003f41070 */
/*0470*/ @!P1 IMAD.X R0, RZ, RZ, R0, P3 ; /* 0x000000ffff009224 */
/* 0x000fcc00018e0600 */
/*0480*/ ISETP.LT.U32.OR.EX P0, PT, R0, R13, P0, P2 ; /* 0x0000000d0000720c */
/* 0x000fe20000701520 */
/*0490*/ @!P1 STG.E.U8 [R16.64], R19 ; /* 0x0000001310009986 */
/* 0x0041e8000c101106 */
/*04a0*/ @!P1 LDG.E.U8 R21, [R14.64+0x1] ; /* 0x000001060e159981 */
/* 0x000eb0000c1e1100 */
/*04b0*/ @P0 IADD3 R8, P2, R8, R11, RZ ; /* 0x0000000b08080210 */
/* 0x000fca0007f5e0ff */
/*04c0*/ @P0 IMAD.X R9, R9, 0x1, R0, P2 ; /* 0x0000000109090824 */
/* 0x000fe200010e0600 */
/*04d0*/ @!P1 STG.E.U8 [R16.64+0x1], R21 ; /* 0x0000011510009986 */
/* 0x0041ea000c101106 */
/*04e0*/ @P0 LDG.E.U8 R9, [R8.64] ; /* 0x0000000608090981 */
/* 0x000ea2000c1e1100 */
/*04f0*/ @P0 IADD3 R10, P1, R11, R2, RZ ; /* 0x000000020b0a0210 */
/* 0x000fca0007f3e0ff */
/*0500*/ @P0 IMAD.X R11, R0, 0x1, R3, P1 ; /* 0x00000001000b0824 */
/* 0x000fca00008e0603 */
/*0510*/ @P0 STG.E.U8 [R10.64], R9 ; /* 0x000000090a000986 */
/* 0x0041e8000c101106 */
/*0520*/ LDG.E R12, [R6.64+-0x8] ; /* 0xfffff806060c7981 */
/* 0x000168000c1e1900 */
/*0530*/ LDG.E.64 R2, [R4.64+0x8] ; /* 0x0000080604027981 */
/* 0x000164000c1e1b00 */
/*0540*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x001fe400078e00ff */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0560*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea4000c1e1900 */
/*0570*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0580*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0590*/ LDG.E.64 R4, [R4.64+0x8] ; /* 0x0000080604047981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ ISETP.GT.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f04070 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*05c0*/ SHF.R.S32.HI R8, RZ, 0x1f, R0 ; /* 0x0000001fff087819 */
/* 0x000fe20000011400 */
/*05d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*05e0*/ ISETP.GT.U32.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04100 */
/*05f0*/ @!P0 IADD3 R10, P1, R4, R9, RZ ; /* 0x00000009040a8210 */
/* 0x004fca0007f3e0ff */
/*0600*/ @!P0 IMAD.X R11, R5, 0x1, R7, P1 ; /* 0x00000001050b8824 */
/* 0x000fca00008e0607 */
/*0610*/ @!P0 LDG.E.U8 R13, [R10.64] ; /* 0x000000060a0d8981 */
/* 0x0000a2000c1e1100 */
/*0620*/ IADD3 R6, P1, R12, R2, RZ ; /* 0x000000020c067210 */
/* 0x020fc80007f3e0ff */
/*0630*/ LEA.HI.X.SX32 R2, R12, R3, 0x1, P1 ; /* 0x000000030c027211 */
/* 0x000fe400008f0eff */
/*0640*/ @!P0 IADD3 R10, P1, R9, R6, RZ ; /* 0x00000006090a8210 */
/* 0x001fe20007f3e0ff */
/*0650*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff098424 */
/* 0x000fc800078e00ff */
/*0660*/ @!P0 IMAD.X R11, R7, 0x1, R2, P1 ; /* 0x00000001070b8824 */
/* 0x000fe200008e0602 */
/*0670*/ IADD3 R3, P3, R0.reuse, -R9.reuse, RZ ; /* 0x8000000900037210 */
/* 0x0c0fe20007f7e0ff */
/*0680*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*0690*/ ISETP.GT.U32.AND P2, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f44070 */
/*06a0*/ ISETP.LE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f23070 */
/*06b0*/ IMAD.X R3, R8.reuse, 0x1, ~R7, P3 ; /* 0x0000000108037824 */
/* 0x040fe200018e0e07 */
/*06c0*/ ISETP.GT.U32.AND.EX P2, PT, R8, R7, PT, P2 ; /* 0x000000070800720c */
/* 0x000fc80003f44120 */
/*06d0*/ ISETP.LE.U32.OR.EX P1, PT, R3, RZ, !P2, P1 ; /* 0x000000ff0300720c */
/* 0x000fe20005723510 */
/*06e0*/ @!P0 STG.E.U8 [R10.64], R13 ; /* 0x0000000d0a008986 */
/* 0x0041d8000c101106 */
/*06f0*/ @P1 BRA 0x840 ; /* 0x0000014000001947 */
/* 0x000fea0003800000 */
/*0700*/ IADD3 R14, P1, R0, -0x3, RZ ; /* 0xfffffffd000e7810 */
/* 0x000fe40007f3e0ff */
/*0710*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0720*/ IADD3.X R16, R8, -0x1, RZ, P1, !PT ; /* 0xffffffff08107810 */
/* 0x000fe40000ffe4ff */
/*0730*/ IADD3 R12, P1, R4, R9, RZ ; /* 0x00000009040c7210 */
/* 0x000fca0007f3e0ff */
/*0740*/ IMAD.X R13, R5, 0x1, R7, P1 ; /* 0x00000001050d7824 */
/* 0x001fca00008e0607 */
/*0750*/ LDG.E.U8 R3, [R12.64] ; /* 0x000000060c037981 */
/* 0x000ea2000c1e1100 */
/*0760*/ IADD3 R10, P1, R9, R6, RZ ; /* 0x00000006090a7210 */
/* 0x000fca0007f3e0ff */
/*0770*/ IMAD.X R11, R7, 0x1, R2, P1 ; /* 0x00000001070b7824 */
/* 0x000fca00008e0602 */
/*0780*/ STG.E.U8 [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x0041e8000c101106 */
/*0790*/ LDG.E.U8 R15, [R12.64+0x1] ; /* 0x000001060c0f7981 */
/* 0x000ea8000c1e1100 */
/*07a0*/ STG.E.U8 [R10.64+0x1], R15 ; /* 0x0000010f0a007986 */
/* 0x0041e8000c101106 */
/*07b0*/ LDG.E.U8 R17, [R12.64+0x2] ; /* 0x000002060c117981 */
/* 0x000ea2000c1e1100 */
/*07c0*/ IADD3 R9, P2, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc80007f5e0ff */
/*07d0*/ ISETP.GE.U32.AND P1, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fe20003f26070 */
/*07e0*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fca00010e0607 */
/*07f0*/ ISETP.GE.U32.AND.EX P1, PT, R7, R16, PT, P1 ; /* 0x000000100700720c */
/* 0x000fe20003f26110 */
/*0800*/ STG.E.U8 [R10.64+0x2], R17 ; /* 0x000002110a007986 */
/* 0x0041e8000c101106 */
/*0810*/ LDG.E.U8 R19, [R12.64+0x3] ; /* 0x000003060c137981 */
/* 0x000ea8000c1e1100 */
/*0820*/ STG.E.U8 [R10.64+0x3], R19 ; /* 0x000003130a007986 */
/* 0x0041e8000c101106 */
/*0830*/ @!P1 BRA 0x730 ; /* 0xfffffef000009947 */
/* 0x000fea000383ffff */
/*0840*/ IADD3 R3, P3, R0.reuse, -R9.reuse, RZ ; /* 0x8000000900037210 */
/* 0x0c1fe40007f7e0ff */
/*0850*/ ISETP.GT.U32.AND P2, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fc40003f44070 */
/*0860*/ ISETP.LE.U32.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f23070 */
/*0870*/ IMAD.X R3, R8.reuse, 0x1, ~R7, P3 ; /* 0x0000000108037824 */
/* 0x040fe200018e0e07 */
/*0880*/ ISETP.GT.U32.AND.EX P2, PT, R8, R7, PT, P2 ; /* 0x000000070800720c */
/* 0x000fc80003f44120 */
/*0890*/ ISETP.LE.U32.OR.EX P1, PT, R3, RZ, !P2, P1 ; /* 0x000000ff0300720c */
/* 0x000fda0005723510 */
/*08a0*/ @!P1 IADD3 R10, P2, R4, R9, RZ ; /* 0x00000009040a9210 */
/* 0x000fca0007f5e0ff */
/*08b0*/ @!P1 IMAD.X R11, R5, 0x1, R7, P2 ; /* 0x00000001050b9824 */
/* 0x000fca00010e0607 */
/*08c0*/ @!P1 LDG.E.U8 R3, [R10.64] ; /* 0x000000060a039981 */
/* 0x000ea2000c1e1100 */
/*08d0*/ @!P1 IADD3 R12, P2, R9, R6, RZ ; /* 0x00000006090c9210 */
/* 0x000fca0007f5e0ff */
/*08e0*/ @!P1 IMAD.X R13, R7, 0x1, R2, P2 ; /* 0x00000001070d9824 */
/* 0x000fe200010e0602 */
/*08f0*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe40003f0e170 */
/*0900*/ @!P1 IADD3 R9, P3, R9, 0x2, RZ ; /* 0x0000000209099810 */
/* 0x000fc80007f7e0ff */
/*0910*/ ISETP.LT.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe20003f41070 */
/*0920*/ @!P1 IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff079224 */
/* 0x000fe200018e0607 */
/*0930*/ @!P1 STG.E.U8 [R12.64], R3 ; /* 0x000000030c009986 */
/* 0x0041e8000c101106 */
/*0940*/ @!P1 LDG.E.U8 R15, [R10.64+0x1] ; /* 0x000001060a0f9981 */
/* 0x000ea2000c1e1100 */
/*0950*/ ISETP.LT.U32.OR.EX P0, PT, R7, R8, P0, P2 ; /* 0x000000080700720c */
/* 0x000fc60000701520 */
/*0960*/ @!P1 STG.E.U8 [R12.64+0x1], R15 ; /* 0x0000010f0c009986 */
/* 0x0041f4000c101106 */
/*0970*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0980*/ IADD3 R4, P0, R4, R9, RZ ; /* 0x0000000904047210 */
/* 0x000fca0007f1e0ff */
/*0990*/ IMAD.X R5, R5, 0x1, R7, P0 ; /* 0x0000000105057824 */
/* 0x000fcc00000e0607 */
/*09a0*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1100 */
/*09b0*/ IADD3 R6, P0, R9, R6, RZ ; /* 0x0000000609067210 */
/* 0x000fca0007f1e0ff */
/*09c0*/ IMAD.X R7, R7, 0x1, R2, P0 ; /* 0x0000000107077824 */
/* 0x000fca00000e0602 */
/*09d0*/ STG.E.U8 [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101106 */
/*09e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13string_appendP8string_tS0_S0_
.globl _Z13string_appendP8string_tS0_S0_
.p2align 8
.type _Z13string_appendP8string_tS0_S0_,@function
_Z13string_appendP8string_tS0_S0_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[2:3], 0x0
s_load_b64 s[6:7], s[4:5], 0x8
s_load_b64 s[8:9], s[2:3], 0x8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u64_e64 s12, s[10:11], 4
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
.p2align 6
.LBB0_1:
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_add_u32 s10, s10, -4
s_addc_u32 s11, s11, -1
flat_load_u8 v4, v[0:1]
v_cmp_gt_u64_e64 s12, s[10:11], 3
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v4
flat_load_u8 v4, v[0:1] offset:1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v4 offset:1
flat_load_u8 v4, v[0:1] offset:2
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v4 offset:2
flat_load_u8 v0, v[0:1] offset:3
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v0 offset:3
s_cbranch_vccnz .LBB0_1
.LBB0_2:
v_cmp_lt_i64_e64 s12, s[10:11], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_8
v_cmp_gt_i64_e64 s12, s[10:11], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s12
s_mov_b32 s12, -1
s_cbranch_vccz .LBB0_6
s_cmp_eq_u64 s[10:11], 3
s_mov_b32 s12, 0
s_cbranch_scc0 .LBB0_6
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
s_mov_b32 s12, -1
flat_load_u8 v2, v[0:1] offset:2
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[0:1], v2 offset:2
.LBB0_6:
s_mov_b32 s13, 0
s_and_b32 vcc_lo, exec_lo, s12
s_mov_b32 s12, 0
s_cbranch_vccz .LBB0_9
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
s_mov_b32 s12, -1
flat_load_u8 v2, v[0:1] offset:1
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[0:1], v2 offset:1
s_branch .LBB0_9
.LBB0_8:
s_mov_b32 s13, -1
s_mov_b32 s12, 0
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s13
s_cbranch_vccz .LBB0_11
s_cmp_eq_u64 s[10:11], 1
s_cselect_b32 s12, -1, 0
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_13
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
flat_load_u8 v2, v[0:1]
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[0:1], v2
.LBB0_13:
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_clause 0x3
global_load_b32 v4, v0, s[0:1]
global_load_b32 v6, v0, s[2:3]
global_load_b64 v[2:3], v0, s[4:5] offset:8
global_load_b64 v[0:1], v0, s[0:1] offset:8
s_waitcnt vmcnt(3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt vmcnt(2)
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt vmcnt(1)
v_add_co_u32 v2, s0, v2, v6
v_cmp_gt_u64_e32 vcc_lo, 4, v[4:5]
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, v3, v7, s0
s_cbranch_vccnz .LBB0_15
.p2align 6
.LBB0_14:
s_waitcnt vmcnt(0)
flat_load_u8 v6, v[0:1]
v_add_co_u32 v4, vcc_lo, v4, -4
v_add_co_ci_u32_e32 v5, vcc_lo, -1, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u64_e32 vcc_lo, 3, v[4:5]
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6
flat_load_u8 v6, v[0:1] offset:1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:1
flat_load_u8 v6, v[0:1] offset:2
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:2
flat_load_u8 v6, v[0:1] offset:3
v_add_co_u32 v0, s0, v0, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:3
v_add_co_u32 v2, s0, v2, 4
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_cbranch_vccnz .LBB0_14
.LBB0_15:
v_cmp_gt_i64_e32 vcc_lo, 2, v[4:5]
s_cbranch_vccnz .LBB0_21
v_cmp_lt_i64_e32 vcc_lo, 2, v[4:5]
s_mov_b32 s0, -1
s_cbranch_vccz .LBB0_19
v_cmp_eq_u64_e32 vcc_lo, 3, v[4:5]
s_mov_b32 s0, 0
s_cbranch_vccz .LBB0_19
s_waitcnt vmcnt(0)
flat_load_u8 v6, v[0:1] offset:2
s_mov_b32 s0, -1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:2
.LBB0_19:
s_mov_b32 s1, 0
s_and_b32 vcc_lo, exec_lo, s0
s_mov_b32 s0, 0
s_cbranch_vccz .LBB0_22
s_waitcnt vmcnt(0)
flat_load_u8 v6, v[0:1] offset:1
s_mov_b32 s0, -1
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v6 offset:1
s_branch .LBB0_22
.LBB0_21:
s_mov_b32 s1, -1
s_mov_b32 s0, 0
.LBB0_22:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_25
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_26
.LBB0_24:
s_endpgm
.LBB0_25:
v_cmp_eq_u64_e64 s0, 1, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_24
.LBB0_26:
s_waitcnt vmcnt(0)
flat_load_u8 v0, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b8 v[2:3], v0
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13string_appendP8string_tS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13string_appendP8string_tS0_S0_, .Lfunc_end0-_Z13string_appendP8string_tS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13string_appendP8string_tS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z13string_appendP8string_tS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5b43_00000000-6_unifMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
.type _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_, @function
_Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13string_appendP8string_tS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_, .-_Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
.globl _Z13string_appendP8string_tS0_S0_
.type _Z13string_appendP8string_tS0_S0_, @function
_Z13string_appendP8string_tS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13string_appendP8string_tS0_S0_, .-_Z13string_appendP8string_tS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %edx
movl $7, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 16(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %edx
movl $7, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16, %esi
call cudaMallocManaged@PLT
movq 24(%rsp), %rax
leaq 8(%rax), %rdi
movl $1, %edx
movl $14, %esi
call cudaMallocManaged@PLT
movq 8(%rsp), %rax
movl $7, (%rax)
movq 8(%rsp), %rax
movq 8(%rax), %rax
movl $1819043144, (%rax)
movl $539783020, 3(%rax)
movq 16(%rsp), %rax
movl $7, (%rax)
movq 16(%rsp), %rax
movq 8(%rax), %rax
movl $1819438967, (%rax)
movl $2188396, 3(%rax)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
movq 8(%rax), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L15:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z47__device_stub__Z13string_appendP8string_tS0_S0_P8string_tS0_S0_
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z13string_appendP8string_tS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13string_appendP8string_tS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unifMem.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 16(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rdi
addq $8, %rdi
movl $7, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
addq $8, %rdi
movl $7, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $16, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rdi
addq $8, %rdi
movl $14, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movl $7, (%rax)
movq 8(%rax), %rax
movl $539783020, 3(%rax) # imm = 0x202C6F6C
movl $1819043144, (%rax) # imm = 0x6C6C6548
movq 8(%rsp), %rax
movl $7, (%rax)
movq 8(%rax), %rax
movl $1819438967, (%rax) # imm = 0x6C726F77
movl $2188396, 3(%rax) # imm = 0x21646C
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13string_appendP8string_tS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movq (%rsp), %rax
movq 8(%rax), %rdi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z28__device_stub__string_appendP8string_tS0_S0_ # -- Begin function _Z28__device_stub__string_appendP8string_tS0_S0_
.p2align 4, 0x90
.type _Z28__device_stub__string_appendP8string_tS0_S0_,@function
_Z28__device_stub__string_appendP8string_tS0_S0_: # @_Z28__device_stub__string_appendP8string_tS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13string_appendP8string_tS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z28__device_stub__string_appendP8string_tS0_S0_, .Lfunc_end1-_Z28__device_stub__string_appendP8string_tS0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13string_appendP8string_tS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello, "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "world!"
.size .L.str.1, 7
.type _Z13string_appendP8string_tS0_S0_,@object # @_Z13string_appendP8string_tS0_S0_
.section .rodata,"a",@progbits
.globl _Z13string_appendP8string_tS0_S0_
.p2align 3, 0x0
_Z13string_appendP8string_tS0_S0_:
.quad _Z28__device_stub__string_appendP8string_tS0_S0_
.size _Z13string_appendP8string_tS0_S0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13string_appendP8string_tS0_S0_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__string_appendP8string_tS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13string_appendP8string_tS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | .file "tmpxft_000f5a21_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gitPratikSingh/Parallel-Computing/master/lakegpu.cu"
.align 8
.LC1:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L15
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L16
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L17
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L18
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L19
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L20
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L21
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L22
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L23
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $75, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $76, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $77, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $82, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $87, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $88, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $89, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $95, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $96, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} | .text
.file "lakegpu.hip"
.globl _Z7run_gpuPdS_S_S_iddi # -- Begin function _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit2
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit4
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z14__cudaSafeCall10hipError_tPKci.exit6
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z14__cudaSafeCall10hipError_tPKci.exit8
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z14__cudaSafeCall10hipError_tPKci.exit10
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z14__cudaSafeCall10hipError_tPKci.exit12
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit14
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit16
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $75, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $76, %ecx
jmp .LBB0_2
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $77, %ecx
jmp .LBB0_2
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $82, %ecx
jmp .LBB0_2
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $87, %ecx
jmp .LBB0_2
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $88, %ecx
jmp .LBB0_2
.LBB0_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $89, %ecx
jmp .LBB0_2
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $95, %ecx
jmp .LBB0_2
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $96, %ecx
.LBB0_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end0-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gitPratikSingh/Parallel-Computing/master/lakegpu.hip"
.size .L.str, 110
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5a21_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/gitPratikSingh/Parallel-Computing/master/lakegpu.cu"
.align 8
.LC1:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L15
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L16
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L17
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L18
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L19
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L20
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L21
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L22
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L23
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $75, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $76, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $77, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $82, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $87, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $88, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $89, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $95, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $96, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lakegpu.hip"
.globl _Z7run_gpuPdS_S_S_iddi # -- Begin function _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit2
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit4
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z14__cudaSafeCall10hipError_tPKci.exit6
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_10
# %bb.11: # %_Z14__cudaSafeCall10hipError_tPKci.exit8
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_12
# %bb.13: # %_Z14__cudaSafeCall10hipError_tPKci.exit10
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_14
# %bb.15: # %_Z14__cudaSafeCall10hipError_tPKci.exit12
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit14
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB0_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit16
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $75, %ecx
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $76, %ecx
jmp .LBB0_2
.LBB0_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $77, %ecx
jmp .LBB0_2
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $82, %ecx
jmp .LBB0_2
.LBB0_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $87, %ecx
jmp .LBB0_2
.LBB0_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $88, %ecx
jmp .LBB0_2
.LBB0_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $89, %ecx
jmp .LBB0_2
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $95, %ecx
jmp .LBB0_2
.LBB0_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $96, %ecx
.LBB0_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end0-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/gitPratikSingh/Parallel-Computing/master/lakegpu.hip"
.size .L.str, 110
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#include <math.h>
#define VSQR 0.1
#define TSCALE 1.0
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
int tpdt(double *t, double dt, double tf);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__device__ double f1(double p, double t)
{
return -expf(-TSCALE * t) * p;
}
__global__ void evolve_gpu(double *un,double *uc, double *u0, double *pebbles, int *n, double *h, double *dt,double *t){
int idx = (blockDim.x * blockIdx.x) + threadIdx.x;
int i = idx/(*n);
int j= idx%(*n);
if(i == 0 || i == ((*n)-1) || j == 0 || j == ((*n) -1) ){
un[idx]=0;
}
else {
un[idx] = 2*uc[idx] - u0[idx] + VSQR *((*dt) * (*dt)) *((uc[idx-1] + uc[idx+1] +
uc[idx + (*n)] + uc[idx - (*n)] +0.25*(uc[idx - (*n) + 1] + uc[idx + (*n) -1 ]
+ uc[idx - (*n) - 1]+uc[idx + (*n) + 1]) - 5 * uc[idx])/((*h) * (*h)) + f1(pebbles[idx],(*t)));
}
}
/*int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}*/
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double* u_d;
double* u0_d;
double* u1_d;
double* peb_d;
int *n_d;
double *h_d;
double *dt_d;
double *t_d;
double t=0.,dt=h/2.;
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
cudaMalloc((void **)&u_d,n*n*sizeof(double));
cudaMalloc((void **)&u0_d,n*n*sizeof(double));
cudaMalloc((void **)&u1_d,n*n*sizeof(double));
cudaMalloc((void **)&peb_d,n*n*sizeof(double));
cudaMalloc((void **)&n_d,sizeof(int));
cudaMalloc((void **)&h_d,sizeof(double));
cudaMalloc((void **)&dt_d,sizeof(double));
cudaMalloc((void **)&t_d,sizeof(double));
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
cudaMemcpy(u0_d,u0,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(u1_d,u1,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(peb_d,pebbles,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(n_d,&n,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(h_d,&h,sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(dt_d,&dt,sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(t_d,&t,sizeof(double),cudaMemcpyHostToDevice);
int block = n/nthreads;
block*=block;
int threads = nthreads*nthreads;
/* HW2: Add main lake simulation loop here */
while(1){
evolve_gpu<<<block,threads>>>(u_d,u1_d,u0_d,peb_d,n_d,h_d,dt_d,t_d);
u0_d = u1_d;
u1_d = u_d;
if(!tpdt(&t,dt,end_time)) break;
cudaMemcpy(t_d,&t,sizeof(double),cudaMemcpyHostToDevice);
}
cudaMemcpy(u,u_d,sizeof(double)*n*n,cudaMemcpyDeviceToHost);
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
cudaFree(u_d);
cudaFree(u0_d);
cudaFree(u1_d);
cudaFree(peb_d);
cudaFree(n_d);
cudaFree(h_d);
cudaFree(dt_d);
cudaFree(t_d);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | code for sm_80
Function : _Z10evolve_gpuPdS_S_S_PiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0207 */
/*0090*/ IMAD.WIDE R16, R0, R19, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fe200078e0213 */
/*00a0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe40000000000 */
/*00b0*/ IABS R9, R15.reuse ; /* 0x0000000f00097213 */
/* 0x084fe40000000000 */
/*00c0*/ IABS R8, R15 ; /* 0x0000000f00087213 */
/* 0x000fe40000000000 */
/*00d0*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R2, RZ, RZ, -R5 ; /* 0x000000ffff027224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R3, R2, R9, RZ ; /* 0x0000000902037224 */
/* 0x000fe400078e02ff */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0150*/ IMAD.HI.U32 R5, R5, R3, R4 ; /* 0x0000000305057227 */
/* 0x000fc800078e0004 */
/*0160*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a08 */
/*0170*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R2, R5, R3, R2 ; /* 0x0000000305027224 */
/* 0x000fe200078e0202 */
/*0190*/ IADD3 R3, R15, -0x1, RZ ; /* 0xffffffff0f037810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a09 */
/*01c0*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f25270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*01f0*/ LOP3.LUT R2, R0, R15, RZ, 0x3c, !PT ; /* 0x0000000f00027212 */
/* 0x000fc800078e3cff */
/*0200*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*0210*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fcc0007ffe0ff */
/*0220*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*0230*/ @!P1 LOP3.LUT R5, RZ, R15, RZ, 0x33, !PT ; /* 0x0000000fff059212 */
/* 0x000fc800078e33ff */
/*0240*/ ISETP.NE.AND P0, PT, R5, R3, PT ; /* 0x000000030500720c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.MOV R2, RZ, RZ, -R5 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a05 */
/*0260*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fe20004702670 */
/*0270*/ IMAD R2, R15, R2, R0 ; /* 0x000000020f027224 */
/* 0x000fca00078e0200 */
/*0280*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fc80000702670 */
/*0290*/ ISETP.EQ.OR P0, PT, R2, R3, P0 ; /* 0x000000030200720c */
/* 0x000fda0000702670 */
/*02a0*/ @P0 BRA 0x7e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R2, R0, 0x8, RZ ; /* 0x0000000800027824 */
/* 0x000fe200078e00ff */
/*02c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*02d0*/ SHF.L.U64.HI R3, R0, 0x3, R3 ; /* 0x0000000300037819 */
/* 0x000fe40000010203 */
/*02e0*/ IADD3 R20, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002147a10 */
/* 0x000fc80007f1e0ff */
/*02f0*/ IADD3.X R21, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003157a10 */
/* 0x000fca00007fe4ff */
/*0300*/ LDG.E.64 R24, [R20.64+0x8] ; /* 0x0000080414187981 */
/* 0x0000a8000c1e1b00 */
/*0310*/ LDG.E.64 R22, [R20.64+-0x8] ; /* 0xfffff80414167981 */
/* 0x0000a2000c1e1b00 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff047624 */
/* 0x000fe200078e00ff */
/*0330*/ IADD3 R28, R0, -0x1, R15 ; /* 0xffffffff001c7810 */
/* 0x000fe20007ffe00f */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fe200078e00ff */
/*0350*/ IADD3 R26, -R15, 0x1, R0 ; /* 0x000000010f1a7810 */
/* 0x000fc60007ffe100 */
/*0360*/ IMAD.WIDE R28, R28, R19.reuse, c[0x0][0x168] ; /* 0x00005a001c1c7625 */
/* 0x080fe400078e0213 */
/*0370*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1b00 */
/*0380*/ IMAD.WIDE R26, R26, R19, c[0x0][0x168] ; /* 0x00005a001a1a7625 */
/* 0x000fe400078e0213 */
/*0390*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000f28000c1e1b00 */
/*03a0*/ LDG.E.64 R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000322000c1e1b00 */
/*03b0*/ IMAD.WIDE R10, R15, 0x8, R20 ; /* 0x000000080f0a7825 */
/* 0x000fc600078e0214 */
/*03c0*/ LDG.E.64 R12, [R26.64+-0x10] ; /* 0xfffff0041a0c7981 */
/* 0x000362000c1e1b00 */
/*03d0*/ IMAD.IADD R14, R0, 0x1, -R15 ; /* 0x00000001000e7824 */
/* 0x000fc600078e0a0f */
/*03e0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*03f0*/ IMAD.WIDE R14, R14, R19, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fc600078e0213 */
/*0400*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f68000c1e1b00 */
/*0410*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1b00 */
/*0420*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x001f62000c1e1b00 */
/*0430*/ IADD3 R26, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c00021a7a10 */
/* 0x002fc80007f1e0ff */
/*0440*/ IADD3.X R27, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00031b7a10 */
/* 0x000fcc00007fe4ff */
/*0450*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1b00 */
/*0460*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x0041e40000000016 */
/*0470*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff187624 */
/* 0x001fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff197624 */
/* 0x000fcc00078e00ff */
/*0490*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x008e080000000000 */
/*04b0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x0101640000000008 */
/*04c0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e220000001800 */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*04e0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x020fc8000000000c */
/*04f0*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x000fc8000000000a */
/*0500*/ DFMA R12, -R4, R6, 1 ; /* 0x3ff00000040c742b */
/* 0x001e0c0000000106 */
/*0510*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e08000000000c */
/*0520*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x000fc8000000000e */
/*0530*/ DFMA R12, R6, R12, R6 ; /* 0x0000000c060c722b */
/* 0x001e080000000006 */
/*0540*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x000e480000000012 */
/*0550*/ DFMA R14, -R4, R12, 1 ; /* 0x3ff00000040e742b */
/* 0x001e08000000010c */
/*0560*/ DFMA R6, R8, 0.25, R10 ; /* 0x3fd000000806782b */
/* 0x002e48000000000a */
/*0570*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001fc8000000000c */
/*0580*/ DFMA R6, R20, -5, R6 ; /* 0xc01400001406782b */
/* 0x002e0c0000000006 */
/*0590*/ DMUL R8, R6, R14 ; /* 0x0000000e06087228 */
/* 0x001e0c0000000000 */
/*05a0*/ DFMA R10, -R4, R8, R6 ; /* 0x00000008040a722b */
/* 0x001e0c0000000106 */
/*05b0*/ DFMA R8, R14, R10, R8 ; /* 0x0000000a0e08722b */
/* 0x001e220000000008 */
/*05c0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fd20003f2e200 */
/*05d0*/ FFMA R0, RZ, R5, R9 ; /* 0x00000005ff007223 */
/* 0x001fca0000000009 */
/*05e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fe20003f04200 */
/*05f0*/ DADD R14, R20, R20 ; /* 0x00000000140e7229 */
/* 0x000e220000000014 */
/*0600*/ BSSY B0, 0x680 ; /* 0x0000007000007945 */
/* 0x000fea0003800000 */
/*0610*/ DADD R14, R14, -R26 ; /* 0x000000000e0e7229 */
/* 0x001fc8000000081a */
/*0620*/ DMUL R12, R24, R24 ; /* 0x00000018180c7228 */
/* 0x004e0c0000000000 */
/*0630*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x001e220000000000 */
/*0640*/ @P0 BRA P1, 0x670 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0650*/ MOV R0, 0x670 ; /* 0x0000067000007802 */
/* 0x000fca0000000f00 */
/*0660*/ CALL.REL.NOINC 0x800 ; /* 0x0000019000007944 */
/* 0x001fea0003c00000 */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff047624 */
/* 0x000fe400078e00ff */
/*0690*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff057624 */
/* 0x000fcc00078e00ff */
/*06a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*06b0*/ IADD3 R2, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc80007f1e0ff */
/*06c0*/ IADD3.X R3, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003037a10 */
/* 0x000fcc00007fe4ff */
/*06d0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1b00 */
/*06e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff077424 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff0b7424 */
/* 0x000fe200078e00ff */
/*0700*/ F2F.F32.F64 R0, R4 ; /* 0x0000000400007310 */
/* 0x004e640000301000 */
/*0710*/ FFMA.SAT R6, -R0, R7, 0.5 ; /* 0x3f00000000067423 */
/* 0x002fc80000002107 */
/*0720*/ FFMA.RM R6, R6, R11, 12582913 ; /* 0x4b40000106067423 */
/* 0x000fc8000000400b */
/*0730*/ FADD R7, R6.reuse, -12583039 ; /* 0xcb40007f06077421 */
/* 0x040fe40000000000 */
/*0740*/ IMAD.SHL.U32 R6, R6, 0x800000, RZ ; /* 0x0080000006067824 */
/* 0x000fe400078e00ff */
/*0750*/ FFMA R7, -R0, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b00077823 */
/* 0x000fc80000000907 */
/*0760*/ FFMA R7, -R0, 1.925963033500011079e-08, R7 ; /* 0x32a5706000077823 */
/* 0x000fcc0000000107 */
/*0770*/ MUFU.EX2 R7, R7 ; /* 0x0000000700077308 */
/* 0x000e640000000800 */
/*0780*/ FMUL R6, R6, R7 ; /* 0x0000000706067220 */
/* 0x002fcc0000400000 */
/*0790*/ F2F.F64.F32 R4, R6 ; /* 0x0000000600047310 */
/* 0x000ee40000201800 */
/*07a0*/ DFMA R2, R4, -R2, R8 ; /* 0x800000020402722b */
/* 0x008e4c0000000008 */
/*07b0*/ DFMA R2, R12, R2, R14 ; /* 0x000000020c02722b */
/* 0x003e0e000000000e */
/*07c0*/ STG.E.64 [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x001fe2000c101b04 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ STG.E.64 [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x000fe2000c101b04 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0820*/ LOP3.LUT R10, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff050a7812 */
/* 0x000fe200078ec0ff */
/*0830*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0840*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0850*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*0860*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0870*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0880*/ LOP3.LUT R4, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007047812 */
/* 0x000fe200078ec0ff */
/*0890*/ BSSY B1, 0xdb0 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*08a0*/ LOP3.LUT R27, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000051b7812 */
/* 0x000fe200078ec0ff */
/*08b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff057424 */
/* 0x000fc400078e00ff */
/*08c0*/ @!P0 DMUL R10, R8, 8.98846567431157953865e+307 ; /* 0x7fe00000080a8828 */
/* 0x000e220000000000 */
/*08d0*/ ISETP.GE.U32.AND P1, PT, R4, R27, PT ; /* 0x0000001b0400720c */
/* 0x000fc60003f26070 */
/*08e0*/ @!P2 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000915a812 */
/* 0x000fe200078ec0ff */
/*08f0*/ @!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff18a224 */
/* 0x000fe200078e00ff */
/*0900*/ MUFU.RCP64H R23, R11 ; /* 0x0000000b00177308 */
/* 0x001e240000001800 */
/*0910*/ @!P2 ISETP.GE.U32.AND P3, PT, R4, R21, PT ; /* 0x000000150400a20c */
/* 0x000fe40003f66070 */
/*0920*/ SEL R21, R5.reuse, 0x63400000, !P1 ; /* 0x6340000005157807 */
/* 0x040fe40004800000 */
/*0930*/ @!P2 SEL R25, R5, 0x63400000, !P3 ; /* 0x634000000519a807 */
/* 0x000fe40005800000 */
/*0940*/ @!P0 LOP3.LUT R27, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1b8812 */
/* 0x000fc400078ec0ff */
/*0950*/ @!P2 LOP3.LUT R25, R25, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001919a812 */
/* 0x000fc800078ef807 */
/*0960*/ @!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001919a812 */
/* 0x000fe200078efcff */
/*0970*/ DFMA R18, R22, -R10, 1 ; /* 0x3ff000001612742b */
/* 0x001e0c000000080a */
/*0980*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0990*/ DFMA R22, R22, R18, R22 ; /* 0x000000121616722b */
/* 0x0010640000000016 */
/*09a0*/ LOP3.LUT R19, R21, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff15137812 */
/* 0x001fe200078ef807 */
/*09b0*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0006 */
/*09c0*/ DFMA R20, R22, -R10, 1 ; /* 0x3ff000001614742b */
/* 0x002e08000000080a */
/*09d0*/ @!P2 DFMA R18, R18, 2, -R24 ; /* 0x400000001212a82b */
/* 0x000fc80000000818 */
/*09e0*/ DFMA R20, R22, R20, R22 ; /* 0x000000141614722b */
/* 0x001e0c0000000016 */
/*09f0*/ DMUL R22, R20, R18 ; /* 0x0000001214167228 */
/* 0x001e0c0000000000 */
/*0a00*/ DFMA R24, R22, -R10, R18 ; /* 0x8000000a1618722b */
/* 0x001e0c0000000012 */
/*0a10*/ DFMA R24, R20, R24, R22 ; /* 0x000000181418722b */
/* 0x0010640000000016 */
/*0a20*/ IMAD.MOV.U32 R20, RZ, RZ, R4 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0004 */
/*0a30*/ @!P2 LOP3.LUT R20, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001314a812 */
/* 0x000fe400078ec0ff */
/*0a40*/ IADD3 R22, R27, -0x1, RZ ; /* 0xffffffff1b167810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ IADD3 R21, R20, -0x1, RZ ; /* 0xffffffff14157810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.GT.U32.AND P0, PT, R21, 0x7feffffe, PT ; /* 0x7feffffe1500780c */
/* 0x000fc80003f04070 */
/*0a70*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fda0000704470 */
/*0a80*/ @P0 BRA 0xc50 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0a90*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x002fe200078ec0ff */
/*0aa0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*0ab0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0ac0*/ IMAD.IADD R6, R4, 0x1, -R7 ; /* 0x0000000104067824 */
/* 0x000fc600078e0a07 */
/*0ad0*/ SEL R5, R5, 0x63400000, !P0 ; /* 0x6340000005057807 */
/* 0x000fe40004000000 */
/*0ae0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0af0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0b00*/ IMAD.IADD R6, R6, 0x1, -R5 ; /* 0x0000000106067824 */
/* 0x000fca00078e0a05 */
/*0b10*/ IADD3 R21, R6, 0x7fe00000, RZ ; /* 0x7fe0000006157810 */
/* 0x000fcc0007ffe0ff */
/*0b20*/ DMUL R4, R24, R20 ; /* 0x0000001418047228 */
/* 0x000e140000000000 */
/*0b30*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0b40*/ @P0 BRA 0xda0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0b50*/ DFMA R10, R24, -R10, R18 ; /* 0x8000000a180a722b */
/* 0x000e220000000012 */
/*0b60*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0b70*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x041fe40003f0d000 */
/*0b80*/ LOP3.LUT R7, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fc800078e4809 */
/*0b90*/ LOP3.LUT R21, R7, R21, RZ, 0xfc, !PT ; /* 0x0000001507157212 */
/* 0x000fce00078efcff */
/*0ba0*/ @!P0 BRA 0xda0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a06 */
/*0bc0*/ DMUL.RP R20, R24, R20 ; /* 0x0000001418147228 */
/* 0x000e220000008000 */
/*0bd0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*0be0*/ DFMA R8, R4, -R8, R24 ; /* 0x800000080408722b */
/* 0x000e460000000018 */
/*0bf0*/ LOP3.LUT R7, R21, R7, RZ, 0x3c, !PT ; /* 0x0000000715077212 */
/* 0x001fc600078e3cff */
/*0c00*/ IADD3 R8, -R6, -0x43300000, RZ ; /* 0xbcd0000006087810 */
/* 0x002fc80007ffe1ff */
/*0c10*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0c20*/ FSEL R4, R20, R4, !P0 ; /* 0x0000000414047208 */
/* 0x000fe40004000000 */
/*0c30*/ FSEL R5, R7, R5, !P0 ; /* 0x0000000507057208 */
/* 0x000fe20004000000 */
/*0c40*/ BRA 0xda0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0c50*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x002e1c0003f08000 */
/*0c60*/ @P0 BRA 0xd80 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0c70*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0c80*/ @P0 BRA 0xd50 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0c90*/ ISETP.NE.AND P0, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fe20003f05270 */
/*0ca0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0cb0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0cc0*/ @!P0 BRA 0xda0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0ce0*/ LOP3.LUT R5, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007057812 */
/* 0x000fe400078e4809 */
/*0cf0*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*0d00*/ @P0 LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005060812 */
/* 0x000fe200078efcff */
/*0d10*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0d20*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0d30*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0006 */
/*0d40*/ BRA 0xda0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d50*/ LOP3.LUT R5, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009057812 */
/* 0x000fe200078efcff */
/*0d60*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0d70*/ BRA 0xda0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R5, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007057812 */
/* 0x000fe200078efcff */
/*0d90*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0da0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0db0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0dc0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0005 */
/*0dd0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0de0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0df0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff20004007950 */
/* 0x000fea0003c3ffff */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#include <math.h>
#define VSQR 0.1
#define TSCALE 1.0
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
int tpdt(double *t, double dt, double tf);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__device__ double f1(double p, double t)
{
return -expf(-TSCALE * t) * p;
}
__global__ void evolve_gpu(double *un,double *uc, double *u0, double *pebbles, int *n, double *h, double *dt,double *t){
int idx = (blockDim.x * blockIdx.x) + threadIdx.x;
int i = idx/(*n);
int j= idx%(*n);
if(i == 0 || i == ((*n)-1) || j == 0 || j == ((*n) -1) ){
un[idx]=0;
}
else {
un[idx] = 2*uc[idx] - u0[idx] + VSQR *((*dt) * (*dt)) *((uc[idx-1] + uc[idx+1] +
uc[idx + (*n)] + uc[idx - (*n)] +0.25*(uc[idx - (*n) + 1] + uc[idx + (*n) -1 ]
+ uc[idx - (*n) - 1]+uc[idx + (*n) + 1]) - 5 * uc[idx])/((*h) * (*h)) + f1(pebbles[idx],(*t)));
}
}
/*int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}*/
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double* u_d;
double* u0_d;
double* u1_d;
double* peb_d;
int *n_d;
double *h_d;
double *dt_d;
double *t_d;
double t=0.,dt=h/2.;
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
cudaMalloc((void **)&u_d,n*n*sizeof(double));
cudaMalloc((void **)&u0_d,n*n*sizeof(double));
cudaMalloc((void **)&u1_d,n*n*sizeof(double));
cudaMalloc((void **)&peb_d,n*n*sizeof(double));
cudaMalloc((void **)&n_d,sizeof(int));
cudaMalloc((void **)&h_d,sizeof(double));
cudaMalloc((void **)&dt_d,sizeof(double));
cudaMalloc((void **)&t_d,sizeof(double));
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
cudaMemcpy(u0_d,u0,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(u1_d,u1,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(peb_d,pebbles,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(n_d,&n,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(h_d,&h,sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(dt_d,&dt,sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(t_d,&t,sizeof(double),cudaMemcpyHostToDevice);
int block = n/nthreads;
block*=block;
int threads = nthreads*nthreads;
/* HW2: Add main lake simulation loop here */
while(1){
evolve_gpu<<<block,threads>>>(u_d,u1_d,u0_d,peb_d,n_d,h_d,dt_d,t_d);
u0_d = u1_d;
u1_d = u_d;
if(!tpdt(&t,dt,end_time)) break;
cudaMemcpy(t_d,&t,sizeof(double),cudaMemcpyHostToDevice);
}
cudaMemcpy(u,u_d,sizeof(double)*n*n,cudaMemcpyDeviceToHost);
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
cudaFree(u_d);
cudaFree(u0_d);
cudaFree(u1_d);
cudaFree(peb_d);
cudaFree(n_d);
cudaFree(h_d);
cudaFree(dt_d);
cudaFree(t_d);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | .file "tmpxft_0004948a_00000000-6_backup_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2f1dd
.type _Z2f1dd, @function
_Z2f1dd:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z2f1dd, .-_Z2f1dd
.globl _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
.type _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_, @function
_Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10evolve_gpuPdS_S_S_PiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_, .-_Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
.globl _Z10evolve_gpuPdS_S_S_PiS_S_S_
.type _Z10evolve_gpuPdS_S_S_PiS_S_S_, @function
_Z10evolve_gpuPdS_S_S_PiS_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10evolve_gpuPdS_S_S_PiS_S_S_, .-_Z10evolve_gpuPdS_S_S_PiS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/abhashjain/CSC548/master/a2q3/backup_gpu.cu"
.align 8
.LC3:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $160, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r12
movq %rcx, %rbx
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq $0x000000000, 112(%rsp)
mulsd .LC1(%rip), %xmm0
movsd %xmm0, 120(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L28
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L29
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L30
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L31
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 28(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl 28(%rsp), %eax
cltd
idivl %ebp
imull %eax, %eax
movl %eax, %r12d
imull %ebp, %ebp
leaq 112(%rsp), %rbx
jmp .L20
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $118, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $119, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $120, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $133, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movq 64(%rsp), %rax
movq %rax, 56(%rsp)
movq 48(%rsp), %rdx
movq %rdx, 64(%rsp)
movsd 8(%rsp), %xmm1
movsd 120(%rsp), %xmm0
movq %rbx, %rdi
call _Z4tpdtPddd@PLT
testl %eax, %eax
je .L19
movl $1, %ecx
movl $8, %edx
movq %rbx, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
.L20:
movl %ebp, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r12d, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
pushq 104(%rsp)
.cfi_def_cfa_offset 216
pushq 104(%rsp)
.cfi_def_cfa_offset 224
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 88(%rsp), %rcx
movq 72(%rsp), %rdx
movq 80(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L18
.L19:
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L32
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L33
leaq 140(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L34
pxor %xmm0, %xmm0
cvtss2sd 140(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L35
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L36
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $158, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $159, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $160, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $173, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $174, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z10evolve_gpuPdS_S_S_PiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10evolve_gpuPdS_S_S_PiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#include <math.h>
#define VSQR 0.1
#define TSCALE 1.0
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
int tpdt(double *t, double dt, double tf);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__device__ double f1(double p, double t)
{
return -expf(-TSCALE * t) * p;
}
__global__ void evolve_gpu(double *un,double *uc, double *u0, double *pebbles, int *n, double *h, double *dt,double *t){
int idx = (blockDim.x * blockIdx.x) + threadIdx.x;
int i = idx/(*n);
int j= idx%(*n);
if(i == 0 || i == ((*n)-1) || j == 0 || j == ((*n) -1) ){
un[idx]=0;
}
else {
un[idx] = 2*uc[idx] - u0[idx] + VSQR *((*dt) * (*dt)) *((uc[idx-1] + uc[idx+1] +
uc[idx + (*n)] + uc[idx - (*n)] +0.25*(uc[idx - (*n) + 1] + uc[idx + (*n) -1 ]
+ uc[idx - (*n) - 1]+uc[idx + (*n) + 1]) - 5 * uc[idx])/((*h) * (*h)) + f1(pebbles[idx],(*t)));
}
}
/*int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}*/
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double* u_d;
double* u0_d;
double* u1_d;
double* peb_d;
int *n_d;
double *h_d;
double *dt_d;
double *t_d;
double t=0.,dt=h/2.;
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
cudaMalloc((void **)&u_d,n*n*sizeof(double));
cudaMalloc((void **)&u0_d,n*n*sizeof(double));
cudaMalloc((void **)&u1_d,n*n*sizeof(double));
cudaMalloc((void **)&peb_d,n*n*sizeof(double));
cudaMalloc((void **)&n_d,sizeof(int));
cudaMalloc((void **)&h_d,sizeof(double));
cudaMalloc((void **)&dt_d,sizeof(double));
cudaMalloc((void **)&t_d,sizeof(double));
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
cudaMemcpy(u0_d,u0,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(u1_d,u1,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(peb_d,pebbles,sizeof(double)*n*n,cudaMemcpyHostToDevice);
cudaMemcpy(n_d,&n,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(h_d,&h,sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(dt_d,&dt,sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(t_d,&t,sizeof(double),cudaMemcpyHostToDevice);
int block = n/nthreads;
block*=block;
int threads = nthreads*nthreads;
/* HW2: Add main lake simulation loop here */
while(1){
evolve_gpu<<<block,threads>>>(u_d,u1_d,u0_d,peb_d,n_d,h_d,dt_d,t_d);
u0_d = u1_d;
u1_d = u_d;
if(!tpdt(&t,dt,end_time)) break;
cudaMemcpy(t_d,&t,sizeof(double),cudaMemcpyHostToDevice);
}
cudaMemcpy(u,u_d,sizeof(double)*n*n,cudaMemcpyDeviceToHost);
/* Stop GPU computation timer */
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
cudaFree(u_d);
cudaFree(u0_d);
cudaFree(u1_d);
cudaFree(peb_d);
cudaFree(n_d);
cudaFree(h_d);
cudaFree(dt_d);
cudaFree(t_d);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
} | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <math.h>
#define VSQR 0.1
#define TSCALE 1.0
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
int tpdt(double *t, double dt, double tf);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__device__ double f1(double p, double t)
{
return -expf(-TSCALE * t) * p;
}
__global__ void evolve_gpu(double *un,double *uc, double *u0, double *pebbles, int *n, double *h, double *dt,double *t){
int idx = (blockDim.x * blockIdx.x) + threadIdx.x;
int i = idx/(*n);
int j= idx%(*n);
if(i == 0 || i == ((*n)-1) || j == 0 || j == ((*n) -1) ){
un[idx]=0;
}
else {
un[idx] = 2*uc[idx] - u0[idx] + VSQR *((*dt) * (*dt)) *((uc[idx-1] + uc[idx+1] +
uc[idx + (*n)] + uc[idx - (*n)] +0.25*(uc[idx - (*n) + 1] + uc[idx + (*n) -1 ]
+ uc[idx - (*n) - 1]+uc[idx + (*n) + 1]) - 5 * uc[idx])/((*h) * (*h)) + f1(pebbles[idx],(*t)));
}
}
/*int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}*/
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double* u_d;
double* u0_d;
double* u1_d;
double* peb_d;
int *n_d;
double *h_d;
double *dt_d;
double *t_d;
double t=0.,dt=h/2.;
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
hipMalloc((void **)&u_d,n*n*sizeof(double));
hipMalloc((void **)&u0_d,n*n*sizeof(double));
hipMalloc((void **)&u1_d,n*n*sizeof(double));
hipMalloc((void **)&peb_d,n*n*sizeof(double));
hipMalloc((void **)&n_d,sizeof(int));
hipMalloc((void **)&h_d,sizeof(double));
hipMalloc((void **)&dt_d,sizeof(double));
hipMalloc((void **)&t_d,sizeof(double));
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
hipMemcpy(u0_d,u0,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(u1_d,u1,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(peb_d,pebbles,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(n_d,&n,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(h_d,&h,sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(dt_d,&dt,sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(t_d,&t,sizeof(double),hipMemcpyHostToDevice);
int block = n/nthreads;
block*=block;
int threads = nthreads*nthreads;
/* HW2: Add main lake simulation loop here */
while(1){
evolve_gpu<<<block,threads>>>(u_d,u1_d,u0_d,peb_d,n_d,h_d,dt_d,t_d);
u0_d = u1_d;
u1_d = u_d;
if(!tpdt(&t,dt,end_time)) break;
hipMemcpy(t_d,&t,sizeof(double),hipMemcpyHostToDevice);
}
hipMemcpy(u,u_d,sizeof(double)*n*n,hipMemcpyDeviceToHost);
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
hipFree(u_d);
hipFree(u0_d);
hipFree(u1_d);
hipFree(peb_d);
hipFree(n_d);
hipFree(h_d);
hipFree(dt_d);
hipFree(t_d);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <math.h>
#define VSQR 0.1
#define TSCALE 1.0
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
int tpdt(double *t, double dt, double tf);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__device__ double f1(double p, double t)
{
return -expf(-TSCALE * t) * p;
}
__global__ void evolve_gpu(double *un,double *uc, double *u0, double *pebbles, int *n, double *h, double *dt,double *t){
int idx = (blockDim.x * blockIdx.x) + threadIdx.x;
int i = idx/(*n);
int j= idx%(*n);
if(i == 0 || i == ((*n)-1) || j == 0 || j == ((*n) -1) ){
un[idx]=0;
}
else {
un[idx] = 2*uc[idx] - u0[idx] + VSQR *((*dt) * (*dt)) *((uc[idx-1] + uc[idx+1] +
uc[idx + (*n)] + uc[idx - (*n)] +0.25*(uc[idx - (*n) + 1] + uc[idx + (*n) -1 ]
+ uc[idx - (*n) - 1]+uc[idx + (*n) + 1]) - 5 * uc[idx])/((*h) * (*h)) + f1(pebbles[idx],(*t)));
}
}
/*int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}*/
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double* u_d;
double* u0_d;
double* u1_d;
double* peb_d;
int *n_d;
double *h_d;
double *dt_d;
double *t_d;
double t=0.,dt=h/2.;
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
hipMalloc((void **)&u_d,n*n*sizeof(double));
hipMalloc((void **)&u0_d,n*n*sizeof(double));
hipMalloc((void **)&u1_d,n*n*sizeof(double));
hipMalloc((void **)&peb_d,n*n*sizeof(double));
hipMalloc((void **)&n_d,sizeof(int));
hipMalloc((void **)&h_d,sizeof(double));
hipMalloc((void **)&dt_d,sizeof(double));
hipMalloc((void **)&t_d,sizeof(double));
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
hipMemcpy(u0_d,u0,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(u1_d,u1,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(peb_d,pebbles,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(n_d,&n,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(h_d,&h,sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(dt_d,&dt,sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(t_d,&t,sizeof(double),hipMemcpyHostToDevice);
int block = n/nthreads;
block*=block;
int threads = nthreads*nthreads;
/* HW2: Add main lake simulation loop here */
while(1){
evolve_gpu<<<block,threads>>>(u_d,u1_d,u0_d,peb_d,n_d,h_d,dt_d,t_d);
u0_d = u1_d;
u1_d = u_d;
if(!tpdt(&t,dt,end_time)) break;
hipMemcpy(t_d,&t,sizeof(double),hipMemcpyHostToDevice);
}
hipMemcpy(u,u_d,sizeof(double)*n*n,hipMemcpyDeviceToHost);
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
hipFree(u_d);
hipFree(u0_d);
hipFree(u1_d);
hipFree(peb_d);
hipFree(n_d);
hipFree(h_d);
hipFree(dt_d);
hipFree(t_d);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10evolve_gpuPdS_S_S_PiS_S_S_
.globl _Z10evolve_gpuPdS_S_S_PiS_S_S_
.p2align 8
.type _Z10evolve_gpuPdS_S_S_PiS_S_S_,@function
_Z10evolve_gpuPdS_S_S_PiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x4c
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s10, s2
s_xor_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s3
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_eq_u32_e64 s8, 0, v0
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v2, v0, s10
s_add_i32 s3, s10, -1
s_mov_b32 s4, -1
v_cmp_ne_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_ne_u32_e64 s2, 0, v2
v_cmp_ne_u32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_add_nc_u32_e32 v3, s10, v1
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v5, s10, v1
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x18
s_load_b128 s[12:15], s[0:1], 0x28
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[15:16], 3, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v6, vcc_lo
s_clause 0x5
global_load_b128 v[3:6], v[7:8], off
global_load_b64 v[19:20], v[7:8], off offset:-8
global_load_b64 v[21:22], v[11:12], off offset:-8
global_load_b128 v[7:10], v[17:18], off
global_load_b128 v[11:14], v[11:12], off
global_load_b64 v[17:18], v[17:18], off offset:-8
s_load_b64 s[4:5], s[0:1], 0x38
s_load_b64 s[12:13], s[12:13], 0x0
s_waitcnt vmcnt(4)
v_add_f64 v[5:6], v[19:20], v[5:6]
s_waitcnt vmcnt(2)
v_add_f64 v[9:10], v[9:10], v[21:22]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[11:12]
s_waitcnt vmcnt(0)
v_add_f64 v[9:10], v[9:10], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[9:10], v[13:14]
v_add_co_u32 v13, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s10, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e64 v0, -s[4:5]
s_load_b64 s[4:5], s[14:15], 0x0
v_fma_f64 v[5:6], v[7:8], 0x3fd00000, v[5:6]
v_mul_f64 v[7:8], s[12:13], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[3:4], 0xc0140000, v[5:6]
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[5:6]
v_div_scale_f64 v[19:20], vcc_lo, v[5:6], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_waitcnt vmcnt(1)
v_fma_f64 v[3:4], v[3:4], 2.0, -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[17:18], v[19:20]
v_mul_f32_e32 v19, 0x3fb8aa3b, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_rndne_f32_e32 v20, v19
v_fma_f32 v21, v0, 0x3fb8aa3b, -v19
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmamk_f32 v12, v0, 0x32a5705f, v21 :: v_dual_sub_f32 v11, v19, v20
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
v_add_f32_e32 v11, v11, v12
v_cvt_i32_f32_e32 v12, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v11, v11, v12
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v0, 0x7f800000, v11, vcc_lo
s_waitcnt lgkmcnt(0)
v_mul_f64 v[11:12], s[4:5], s[4:5]
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
v_div_fixup_f64 v[5:6], v[9:10], v[7:8], v[5:6]
v_cvt_f64_f32_e32 v[7:8], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[9:10], v[11:12], s[4:5]
s_xor_b32 s4, exec_lo, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], -v[15:16], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[5:6], v[3:4]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s8, exec_lo
s_and_b32 s3, s4, exec_lo
s_or_b32 s8, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10evolve_gpuPdS_S_S_PiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10evolve_gpuPdS_S_S_PiS_S_S_, .Lfunc_end0-_Z10evolve_gpuPdS_S_S_PiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10evolve_gpuPdS_S_S_PiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10evolve_gpuPdS_S_S_PiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <math.h>
#define VSQR 0.1
#define TSCALE 1.0
#define __DEBUG
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
int tpdt(double *t, double dt, double tf);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__device__ double f1(double p, double t)
{
return -expf(-TSCALE * t) * p;
}
__global__ void evolve_gpu(double *un,double *uc, double *u0, double *pebbles, int *n, double *h, double *dt,double *t){
int idx = (blockDim.x * blockIdx.x) + threadIdx.x;
int i = idx/(*n);
int j= idx%(*n);
if(i == 0 || i == ((*n)-1) || j == 0 || j == ((*n) -1) ){
un[idx]=0;
}
else {
un[idx] = 2*uc[idx] - u0[idx] + VSQR *((*dt) * (*dt)) *((uc[idx-1] + uc[idx+1] +
uc[idx + (*n)] + uc[idx - (*n)] +0.25*(uc[idx - (*n) + 1] + uc[idx + (*n) -1 ]
+ uc[idx - (*n) - 1]+uc[idx + (*n) + 1]) - 5 * uc[idx])/((*h) * (*h)) + f1(pebbles[idx],(*t)));
}
}
/*int tpdt(double *t, double dt, double tf)
{
if((*t) + dt > tf) return 0;
(*t) = (*t) + dt;
return 1;
}*/
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double* u_d;
double* u0_d;
double* u1_d;
double* peb_d;
int *n_d;
double *h_d;
double *dt_d;
double *t_d;
double t=0.,dt=h/2.;
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
hipMalloc((void **)&u_d,n*n*sizeof(double));
hipMalloc((void **)&u0_d,n*n*sizeof(double));
hipMalloc((void **)&u1_d,n*n*sizeof(double));
hipMalloc((void **)&peb_d,n*n*sizeof(double));
hipMalloc((void **)&n_d,sizeof(int));
hipMalloc((void **)&h_d,sizeof(double));
hipMalloc((void **)&dt_d,sizeof(double));
hipMalloc((void **)&t_d,sizeof(double));
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
hipMemcpy(u0_d,u0,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(u1_d,u1,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(peb_d,pebbles,sizeof(double)*n*n,hipMemcpyHostToDevice);
hipMemcpy(n_d,&n,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(h_d,&h,sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(dt_d,&dt,sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(t_d,&t,sizeof(double),hipMemcpyHostToDevice);
int block = n/nthreads;
block*=block;
int threads = nthreads*nthreads;
/* HW2: Add main lake simulation loop here */
while(1){
evolve_gpu<<<block,threads>>>(u_d,u1_d,u0_d,peb_d,n_d,h_d,dt_d,t_d);
u0_d = u1_d;
u1_d = u_d;
if(!tpdt(&t,dt,end_time)) break;
hipMemcpy(t_d,&t,sizeof(double),hipMemcpyHostToDevice);
}
hipMemcpy(u,u_d,sizeof(double)*n*n,hipMemcpyDeviceToHost);
/* Stop GPU computation timer */
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
hipFree(u_d);
hipFree(u0_d);
hipFree(u1_d);
hipFree(peb_d);
hipFree(n_d);
hipFree(h_d);
hipFree(dt_d);
hipFree(t_d);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
} | .text
.file "backup_gpu.hip"
.globl _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_ # -- Begin function _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_,@function
_Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_: # @_Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10evolve_gpuPdS_S_S_PiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_, .Lfunc_end0-_Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movsd %xmm1, 104(%rsp) # 8-byte Spill
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movl %r8d, 4(%rsp)
movsd %xmm0, 120(%rsp)
movq $0, 112(%rsp)
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 88(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 80(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit15
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit17
movq %rbx, 96(%rsp) # 8-byte Spill
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
leaq 64(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z14__cudaSafeCall10hipError_tPKci.exit19
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
leaq 120(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 112(%rsp), %r15
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
cltd
idivl %r14d
movl %eax, %r12d
imull %r12d, %r12d
imull %r14d, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r14
leaq 136(%rsp), %rbx
leaq 128(%rsp), %r13
leaq 240(%rsp), %rbp
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movq 32(%rsp), %rax
movq %rax, 232(%rsp)
movq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq 24(%rsp), %rax
movq %rax, 216(%rsp)
movq 72(%rsp), %rax
movq %rax, 208(%rsp)
movq 64(%rsp), %rax
movq %rax, 200(%rsp)
movq 56(%rsp), %rax
movq %rax, 192(%rsp)
movq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 192(%rsp), %rax
movq %rax, 280(%rsp)
leaq 184(%rsp), %rax
movq %rax, 288(%rsp)
leaq 176(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
movq %rbx, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z10evolve_gpuPdS_S_S_PiS_S_S_, %edi
movq %rbp, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
movq 8(%rsp), %rax
movq %rax, 24(%rsp)
movq 32(%rsp), %rax
movq %rax, 8(%rsp)
movsd 88(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %r15, %rdi
movsd 104(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq _Z4tpdtPddd
testl %eax, %eax
je .LBB1_14
# %bb.13: # in Loop: Header=BB1_10 Depth=1
movq 16(%rsp), %rdi
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
jmp .LBB1_10
.LBB1_14:
movq 32(%rsp), %rsi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq 96(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_15
# %bb.16: # %_Z14__cudaSafeCall10hipError_tPKci.exit21
movq 40(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_17
# %bb.18: # %_Z14__cudaSafeCall10hipError_tPKci.exit23
movq 80(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_19
# %bb.20: # %_Z14__cudaSafeCall10hipError_tPKci.exit25
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_21
# %bb.22: # %_Z14__cudaSafeCall10hipError_tPKci.exit27
movq 40(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_23
# %bb.24: # %_Z14__cudaSafeCall10hipError_tPKci.exit29
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 368
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $118, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $119, %ecx
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $120, %ecx
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $133, %ecx
jmp .LBB1_2
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $158, %ecx
jmp .LBB1_2
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $159, %ecx
jmp .LBB1_2
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $160, %ecx
jmp .LBB1_2
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $173, %ecx
jmp .LBB1_2
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $174, %ecx
.LBB1_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end1-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10evolve_gpuPdS_S_S_PiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10evolve_gpuPdS_S_S_PiS_S_S_,@object # @_Z10evolve_gpuPdS_S_S_PiS_S_S_
.section .rodata,"a",@progbits
.globl _Z10evolve_gpuPdS_S_S_PiS_S_S_
.p2align 3, 0x0
_Z10evolve_gpuPdS_S_S_PiS_S_S_:
.quad _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.size _Z10evolve_gpuPdS_S_S_PiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/abhashjain/CSC548/master/a2q3/backup_gpu.hip"
.size .L.str, 102
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10evolve_gpuPdS_S_S_PiS_S_S_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10evolve_gpuPdS_S_S_PiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10evolve_gpuPdS_S_S_PiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R19, RZ, RZ, 0x8 ; /* 0x00000008ff137424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0207 */
/*0090*/ IMAD.WIDE R16, R0, R19, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fe200078e0213 */
/*00a0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe40000000000 */
/*00b0*/ IABS R9, R15.reuse ; /* 0x0000000f00097213 */
/* 0x084fe40000000000 */
/*00c0*/ IABS R8, R15 ; /* 0x0000000f00087213 */
/* 0x000fe40000000000 */
/*00d0*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R2, RZ, RZ, -R5 ; /* 0x000000ffff027224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R3, R2, R9, RZ ; /* 0x0000000902037224 */
/* 0x000fe400078e02ff */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0150*/ IMAD.HI.U32 R5, R5, R3, R4 ; /* 0x0000000305057227 */
/* 0x000fc800078e0004 */
/*0160*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a08 */
/*0170*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R2, R5, R3, R2 ; /* 0x0000000305027224 */
/* 0x000fe200078e0202 */
/*0190*/ IADD3 R3, R15, -0x1, RZ ; /* 0xffffffff0f037810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R9 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a09 */
/*01c0*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f25270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*01f0*/ LOP3.LUT R2, R0, R15, RZ, 0x3c, !PT ; /* 0x0000000f00027212 */
/* 0x000fc800078e3cff */
/*0200*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*0210*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fcc0007ffe0ff */
/*0220*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*0230*/ @!P1 LOP3.LUT R5, RZ, R15, RZ, 0x33, !PT ; /* 0x0000000fff059212 */
/* 0x000fc800078e33ff */
/*0240*/ ISETP.NE.AND P0, PT, R5, R3, PT ; /* 0x000000030500720c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.MOV R2, RZ, RZ, -R5 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a05 */
/*0260*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fe20004702670 */
/*0270*/ IMAD R2, R15, R2, R0 ; /* 0x000000020f027224 */
/* 0x000fca00078e0200 */
/*0280*/ ISETP.EQ.OR P0, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fc80000702670 */
/*0290*/ ISETP.EQ.OR P0, PT, R2, R3, P0 ; /* 0x000000030200720c */
/* 0x000fda0000702670 */
/*02a0*/ @P0 BRA 0x7e0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R2, R0, 0x8, RZ ; /* 0x0000000800027824 */
/* 0x000fe200078e00ff */
/*02c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*02d0*/ SHF.L.U64.HI R3, R0, 0x3, R3 ; /* 0x0000000300037819 */
/* 0x000fe40000010203 */
/*02e0*/ IADD3 R20, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002147a10 */
/* 0x000fc80007f1e0ff */
/*02f0*/ IADD3.X R21, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003157a10 */
/* 0x000fca00007fe4ff */
/*0300*/ LDG.E.64 R24, [R20.64+0x8] ; /* 0x0000080414187981 */
/* 0x0000a8000c1e1b00 */
/*0310*/ LDG.E.64 R22, [R20.64+-0x8] ; /* 0xfffff80414167981 */
/* 0x0000a2000c1e1b00 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff047624 */
/* 0x000fe200078e00ff */
/*0330*/ IADD3 R28, R0, -0x1, R15 ; /* 0xffffffff001c7810 */
/* 0x000fe20007ffe00f */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fe200078e00ff */
/*0350*/ IADD3 R26, -R15, 0x1, R0 ; /* 0x000000010f1a7810 */
/* 0x000fc60007ffe100 */
/*0360*/ IMAD.WIDE R28, R28, R19.reuse, c[0x0][0x168] ; /* 0x00005a001c1c7625 */
/* 0x080fe400078e0213 */
/*0370*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee4000c1e1b00 */
/*0380*/ IMAD.WIDE R26, R26, R19, c[0x0][0x168] ; /* 0x00005a001a1a7625 */
/* 0x000fe400078e0213 */
/*0390*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000f28000c1e1b00 */
/*03a0*/ LDG.E.64 R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000322000c1e1b00 */
/*03b0*/ IMAD.WIDE R10, R15, 0x8, R20 ; /* 0x000000080f0a7825 */
/* 0x000fc600078e0214 */
/*03c0*/ LDG.E.64 R12, [R26.64+-0x10] ; /* 0xfffff0041a0c7981 */
/* 0x000362000c1e1b00 */
/*03d0*/ IMAD.IADD R14, R0, 0x1, -R15 ; /* 0x00000001000e7824 */
/* 0x000fc600078e0a0f */
/*03e0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*03f0*/ IMAD.WIDE R14, R14, R19, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fc600078e0213 */
/*0400*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f68000c1e1b00 */
/*0410*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1b00 */
/*0420*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x001f62000c1e1b00 */
/*0430*/ IADD3 R26, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c00021a7a10 */
/* 0x002fc80007f1e0ff */
/*0440*/ IADD3.X R27, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00031b7a10 */
/* 0x000fcc00007fe4ff */
/*0450*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1b00 */
/*0460*/ DADD R22, R24, R22 ; /* 0x0000000018167229 */
/* 0x0041e40000000016 */
/*0470*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff187624 */
/* 0x001fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R25, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff197624 */
/* 0x000fcc00078e00ff */
/*0490*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x008e080000000000 */
/*04b0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x0101640000000008 */
/*04c0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e220000001800 */
/*04d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*04e0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x020fc8000000000c */
/*04f0*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x000fc8000000000a */
/*0500*/ DFMA R12, -R4, R6, 1 ; /* 0x3ff00000040c742b */
/* 0x001e0c0000000106 */
/*0510*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e08000000000c */
/*0520*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x000fc8000000000e */
/*0530*/ DFMA R12, R6, R12, R6 ; /* 0x0000000c060c722b */
/* 0x001e080000000006 */
/*0540*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x000e480000000012 */
/*0550*/ DFMA R14, -R4, R12, 1 ; /* 0x3ff00000040e742b */
/* 0x001e08000000010c */
/*0560*/ DFMA R6, R8, 0.25, R10 ; /* 0x3fd000000806782b */
/* 0x002e48000000000a */
/*0570*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x001fc8000000000c */
/*0580*/ DFMA R6, R20, -5, R6 ; /* 0xc01400001406782b */
/* 0x002e0c0000000006 */
/*0590*/ DMUL R8, R6, R14 ; /* 0x0000000e06087228 */
/* 0x001e0c0000000000 */
/*05a0*/ DFMA R10, -R4, R8, R6 ; /* 0x00000008040a722b */
/* 0x001e0c0000000106 */
/*05b0*/ DFMA R8, R14, R10, R8 ; /* 0x0000000a0e08722b */
/* 0x001e220000000008 */
/*05c0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fd20003f2e200 */
/*05d0*/ FFMA R0, RZ, R5, R9 ; /* 0x00000005ff007223 */
/* 0x001fca0000000009 */
/*05e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fe20003f04200 */
/*05f0*/ DADD R14, R20, R20 ; /* 0x00000000140e7229 */
/* 0x000e220000000014 */
/*0600*/ BSSY B0, 0x680 ; /* 0x0000007000007945 */
/* 0x000fea0003800000 */
/*0610*/ DADD R14, R14, -R26 ; /* 0x000000000e0e7229 */
/* 0x001fc8000000081a */
/*0620*/ DMUL R12, R24, R24 ; /* 0x00000018180c7228 */
/* 0x004e0c0000000000 */
/*0630*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x001e220000000000 */
/*0640*/ @P0 BRA P1, 0x670 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0650*/ MOV R0, 0x670 ; /* 0x0000067000007802 */
/* 0x000fca0000000f00 */
/*0660*/ CALL.REL.NOINC 0x800 ; /* 0x0000019000007944 */
/* 0x001fea0003c00000 */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0680*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff047624 */
/* 0x000fe400078e00ff */
/*0690*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff057624 */
/* 0x000fcc00078e00ff */
/*06a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*06b0*/ IADD3 R2, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fc80007f1e0ff */
/*06c0*/ IADD3.X R3, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003037a10 */
/* 0x000fcc00007fe4ff */
/*06d0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1b00 */
/*06e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff077424 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff0b7424 */
/* 0x000fe200078e00ff */
/*0700*/ F2F.F32.F64 R0, R4 ; /* 0x0000000400007310 */
/* 0x004e640000301000 */
/*0710*/ FFMA.SAT R6, -R0, R7, 0.5 ; /* 0x3f00000000067423 */
/* 0x002fc80000002107 */
/*0720*/ FFMA.RM R6, R6, R11, 12582913 ; /* 0x4b40000106067423 */
/* 0x000fc8000000400b */
/*0730*/ FADD R7, R6.reuse, -12583039 ; /* 0xcb40007f06077421 */
/* 0x040fe40000000000 */
/*0740*/ IMAD.SHL.U32 R6, R6, 0x800000, RZ ; /* 0x0080000006067824 */
/* 0x000fe400078e00ff */
/*0750*/ FFMA R7, -R0, 1.4426950216293334961, -R7 ; /* 0x3fb8aa3b00077823 */
/* 0x000fc80000000907 */
/*0760*/ FFMA R7, -R0, 1.925963033500011079e-08, R7 ; /* 0x32a5706000077823 */
/* 0x000fcc0000000107 */
/*0770*/ MUFU.EX2 R7, R7 ; /* 0x0000000700077308 */
/* 0x000e640000000800 */
/*0780*/ FMUL R6, R6, R7 ; /* 0x0000000706067220 */
/* 0x002fcc0000400000 */
/*0790*/ F2F.F64.F32 R4, R6 ; /* 0x0000000600047310 */
/* 0x000ee40000201800 */
/*07a0*/ DFMA R2, R4, -R2, R8 ; /* 0x800000020402722b */
/* 0x008e4c0000000008 */
/*07b0*/ DFMA R2, R12, R2, R14 ; /* 0x000000020c02722b */
/* 0x003e0e000000000e */
/*07c0*/ STG.E.64 [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x001fe2000c101b04 */
/*07d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07e0*/ STG.E.64 [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x000fe2000c101b04 */
/*07f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0800*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0820*/ LOP3.LUT R10, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff050a7812 */
/* 0x000fe200078ec0ff */
/*0830*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0840*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0850*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*0860*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*0870*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*0880*/ LOP3.LUT R4, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007047812 */
/* 0x000fe200078ec0ff */
/*0890*/ BSSY B1, 0xdb0 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*08a0*/ LOP3.LUT R27, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000051b7812 */
/* 0x000fe200078ec0ff */
/*08b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff057424 */
/* 0x000fc400078e00ff */
/*08c0*/ @!P0 DMUL R10, R8, 8.98846567431157953865e+307 ; /* 0x7fe00000080a8828 */
/* 0x000e220000000000 */
/*08d0*/ ISETP.GE.U32.AND P1, PT, R4, R27, PT ; /* 0x0000001b0400720c */
/* 0x000fc60003f26070 */
/*08e0*/ @!P2 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000915a812 */
/* 0x000fe200078ec0ff */
/*08f0*/ @!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff18a224 */
/* 0x000fe200078e00ff */
/*0900*/ MUFU.RCP64H R23, R11 ; /* 0x0000000b00177308 */
/* 0x001e240000001800 */
/*0910*/ @!P2 ISETP.GE.U32.AND P3, PT, R4, R21, PT ; /* 0x000000150400a20c */
/* 0x000fe40003f66070 */
/*0920*/ SEL R21, R5.reuse, 0x63400000, !P1 ; /* 0x6340000005157807 */
/* 0x040fe40004800000 */
/*0930*/ @!P2 SEL R25, R5, 0x63400000, !P3 ; /* 0x634000000519a807 */
/* 0x000fe40005800000 */
/*0940*/ @!P0 LOP3.LUT R27, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1b8812 */
/* 0x000fc400078ec0ff */
/*0950*/ @!P2 LOP3.LUT R25, R25, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001919a812 */
/* 0x000fc800078ef807 */
/*0960*/ @!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001919a812 */
/* 0x000fe200078efcff */
/*0970*/ DFMA R18, R22, -R10, 1 ; /* 0x3ff000001612742b */
/* 0x001e0c000000080a */
/*0980*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0990*/ DFMA R22, R22, R18, R22 ; /* 0x000000121616722b */
/* 0x0010640000000016 */
/*09a0*/ LOP3.LUT R19, R21, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff15137812 */
/* 0x001fe200078ef807 */
/*09b0*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0006 */
/*09c0*/ DFMA R20, R22, -R10, 1 ; /* 0x3ff000001614742b */
/* 0x002e08000000080a */
/*09d0*/ @!P2 DFMA R18, R18, 2, -R24 ; /* 0x400000001212a82b */
/* 0x000fc80000000818 */
/*09e0*/ DFMA R20, R22, R20, R22 ; /* 0x000000141614722b */
/* 0x001e0c0000000016 */
/*09f0*/ DMUL R22, R20, R18 ; /* 0x0000001214167228 */
/* 0x001e0c0000000000 */
/*0a00*/ DFMA R24, R22, -R10, R18 ; /* 0x8000000a1618722b */
/* 0x001e0c0000000012 */
/*0a10*/ DFMA R24, R20, R24, R22 ; /* 0x000000181418722b */
/* 0x0010640000000016 */
/*0a20*/ IMAD.MOV.U32 R20, RZ, RZ, R4 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0004 */
/*0a30*/ @!P2 LOP3.LUT R20, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001314a812 */
/* 0x000fe400078ec0ff */
/*0a40*/ IADD3 R22, R27, -0x1, RZ ; /* 0xffffffff1b167810 */
/* 0x000fe40007ffe0ff */
/*0a50*/ IADD3 R21, R20, -0x1, RZ ; /* 0xffffffff14157810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.GT.U32.AND P0, PT, R21, 0x7feffffe, PT ; /* 0x7feffffe1500780c */
/* 0x000fc80003f04070 */
/*0a70*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fda0000704470 */
/*0a80*/ @P0 BRA 0xc50 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0a90*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x002fe200078ec0ff */
/*0aa0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*0ab0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0ac0*/ IMAD.IADD R6, R4, 0x1, -R7 ; /* 0x0000000104067824 */
/* 0x000fc600078e0a07 */
/*0ad0*/ SEL R5, R5, 0x63400000, !P0 ; /* 0x6340000005057807 */
/* 0x000fe40004000000 */
/*0ae0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0af0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0b00*/ IMAD.IADD R6, R6, 0x1, -R5 ; /* 0x0000000106067824 */
/* 0x000fca00078e0a05 */
/*0b10*/ IADD3 R21, R6, 0x7fe00000, RZ ; /* 0x7fe0000006157810 */
/* 0x000fcc0007ffe0ff */
/*0b20*/ DMUL R4, R24, R20 ; /* 0x0000001418047228 */
/* 0x000e140000000000 */
/*0b30*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0b40*/ @P0 BRA 0xda0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0b50*/ DFMA R10, R24, -R10, R18 ; /* 0x8000000a180a722b */
/* 0x000e220000000012 */
/*0b60*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0b70*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x041fe40003f0d000 */
/*0b80*/ LOP3.LUT R7, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fc800078e4809 */
/*0b90*/ LOP3.LUT R21, R7, R21, RZ, 0xfc, !PT ; /* 0x0000001507157212 */
/* 0x000fce00078efcff */
/*0ba0*/ @!P0 BRA 0xda0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0bb0*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a06 */
/*0bc0*/ DMUL.RP R20, R24, R20 ; /* 0x0000001418147228 */
/* 0x000e220000008000 */
/*0bd0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*0be0*/ DFMA R8, R4, -R8, R24 ; /* 0x800000080408722b */
/* 0x000e460000000018 */
/*0bf0*/ LOP3.LUT R7, R21, R7, RZ, 0x3c, !PT ; /* 0x0000000715077212 */
/* 0x001fc600078e3cff */
/*0c00*/ IADD3 R8, -R6, -0x43300000, RZ ; /* 0xbcd0000006087810 */
/* 0x002fc80007ffe1ff */
/*0c10*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0c20*/ FSEL R4, R20, R4, !P0 ; /* 0x0000000414047208 */
/* 0x000fe40004000000 */
/*0c30*/ FSEL R5, R7, R5, !P0 ; /* 0x0000000507057208 */
/* 0x000fe20004000000 */
/*0c40*/ BRA 0xda0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0c50*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x002e1c0003f08000 */
/*0c60*/ @P0 BRA 0xd80 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0c70*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0c80*/ @P0 BRA 0xd50 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0c90*/ ISETP.NE.AND P0, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fe20003f05270 */
/*0ca0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0cb0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0cc0*/ @!P0 BRA 0xda0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0cd0*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0ce0*/ LOP3.LUT R5, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007057812 */
/* 0x000fe400078e4809 */
/*0cf0*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*0d00*/ @P0 LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005060812 */
/* 0x000fe200078efcff */
/*0d10*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0d20*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0d30*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0006 */
/*0d40*/ BRA 0xda0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d50*/ LOP3.LUT R5, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009057812 */
/* 0x000fe200078efcff */
/*0d60*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0d70*/ BRA 0xda0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R5, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007057812 */
/* 0x000fe200078efcff */
/*0d90*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0da0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0db0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0dc0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0005 */
/*0dd0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0de0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0df0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff20004007950 */
/* 0x000fea0003c3ffff */
/*0e00*/ BRA 0xe00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10evolve_gpuPdS_S_S_PiS_S_S_
.globl _Z10evolve_gpuPdS_S_S_PiS_S_S_
.p2align 8
.type _Z10evolve_gpuPdS_S_S_PiS_S_S_,@function
_Z10evolve_gpuPdS_S_S_PiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x4c
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s10, s[2:3], 0x0
s_and_b32 s4, s4, 0xffff
s_waitcnt lgkmcnt(0)
s_ashr_i32 s2, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s10, s2
s_xor_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s3
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_cmp_eq_u32_e64 s8, 0, v0
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v2, v0, s10
s_add_i32 s3, s10, -1
s_mov_b32 s4, -1
v_cmp_ne_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_ne_u32_e64 s2, 0, v2
v_cmp_ne_u32_e64 s3, s3, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_add_nc_u32_e32 v3, s10, v1
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v5, s10, v1
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x18
s_load_b128 s[12:15], s[0:1], 0x28
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[15:16], 3, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v6, vcc_lo
s_clause 0x5
global_load_b128 v[3:6], v[7:8], off
global_load_b64 v[19:20], v[7:8], off offset:-8
global_load_b64 v[21:22], v[11:12], off offset:-8
global_load_b128 v[7:10], v[17:18], off
global_load_b128 v[11:14], v[11:12], off
global_load_b64 v[17:18], v[17:18], off offset:-8
s_load_b64 s[4:5], s[0:1], 0x38
s_load_b64 s[12:13], s[12:13], 0x0
s_waitcnt vmcnt(4)
v_add_f64 v[5:6], v[19:20], v[5:6]
s_waitcnt vmcnt(2)
v_add_f64 v[9:10], v[9:10], v[21:22]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[11:12]
s_waitcnt vmcnt(0)
v_add_f64 v[9:10], v[9:10], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[9:10], v[13:14]
v_add_co_u32 v13, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s10, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e64 v0, -s[4:5]
s_load_b64 s[4:5], s[14:15], 0x0
v_fma_f64 v[5:6], v[7:8], 0x3fd00000, v[5:6]
v_mul_f64 v[7:8], s[12:13], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[3:4], 0xc0140000, v[5:6]
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[5:6]
v_div_scale_f64 v[19:20], vcc_lo, v[5:6], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_waitcnt vmcnt(1)
v_fma_f64 v[3:4], v[3:4], 2.0, -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[17:18], v[19:20]
v_mul_f32_e32 v19, 0x3fb8aa3b, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_rndne_f32_e32 v20, v19
v_fma_f32 v21, v0, 0x3fb8aa3b, -v19
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmamk_f32 v12, v0, 0x32a5705f, v21 :: v_dual_sub_f32 v11, v19, v20
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
v_add_f32_e32 v11, v11, v12
v_cvt_i32_f32_e32 v12, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v11, v11, v12
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v0, 0x7f800000, v11, vcc_lo
s_waitcnt lgkmcnt(0)
v_mul_f64 v[11:12], s[4:5], s[4:5]
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
v_div_fixup_f64 v[5:6], v[9:10], v[7:8], v[5:6]
v_cvt_f64_f32_e32 v[7:8], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[9:10], v[11:12], s[4:5]
s_xor_b32 s4, exec_lo, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], -v[15:16], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[5:6], v[3:4]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s8, exec_lo
s_and_b32 s3, s4, exec_lo
s_or_b32 s8, s2, s3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10evolve_gpuPdS_S_S_PiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10evolve_gpuPdS_S_S_PiS_S_S_, .Lfunc_end0-_Z10evolve_gpuPdS_S_S_PiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10evolve_gpuPdS_S_S_PiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10evolve_gpuPdS_S_S_PiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004948a_00000000-6_backup_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2f1dd
.type _Z2f1dd, @function
_Z2f1dd:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z2f1dd, .-_Z2f1dd
.globl _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
.type _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_, @function
_Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10evolve_gpuPdS_S_S_PiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_, .-_Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
.globl _Z10evolve_gpuPdS_S_S_PiS_S_S_
.type _Z10evolve_gpuPdS_S_S_PiS_S_S_, @function
_Z10evolve_gpuPdS_S_S_PiS_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10evolve_gpuPdS_S_S_PiS_S_S_, .-_Z10evolve_gpuPdS_S_S_PiS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/abhashjain/CSC548/master/a2q3/backup_gpu.cu"
.align 8
.LC3:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $160, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r12
movq %rcx, %rbx
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movl %r9d, %ebp
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq $0x000000000, 112(%rsp)
mulsd .LC1(%rip), %xmm0
movsd %xmm0, 120(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L28
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L29
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L30
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movl 28(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $3, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L31
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 28(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
leaq 120(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl 28(%rsp), %eax
cltd
idivl %ebp
imull %eax, %eax
movl %eax, %r12d
imull %ebp, %ebp
leaq 112(%rsp), %rbx
jmp .L20
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $118, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $119, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $120, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $133, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movq 64(%rsp), %rax
movq %rax, 56(%rsp)
movq 48(%rsp), %rdx
movq %rdx, 64(%rsp)
movsd 8(%rsp), %xmm1
movsd 120(%rsp), %xmm0
movq %rbx, %rdi
call _Z4tpdtPddd@PLT
testl %eax, %eax
je .L19
movl $1, %ecx
movl $8, %edx
movq %rbx, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
.L20:
movl %ebp, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r12d, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
pushq 104(%rsp)
.cfi_def_cfa_offset 216
pushq 104(%rsp)
.cfi_def_cfa_offset 224
movq 104(%rsp), %r9
movq 96(%rsp), %r8
movq 88(%rsp), %rcx
movq 72(%rsp), %rdx
movq 80(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z44__device_stub__Z10evolve_gpuPdS_S_S_PiS_S_S_PdS_S_S_PiS_S_S_
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L18
.L19:
movslq 28(%rsp), %rdx
imulq %rdx, %rdx
salq $3, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L32
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L33
leaq 140(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L34
pxor %xmm0, %xmm0
cvtss2sd 140(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L35
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L36
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $158, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $159, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $160, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $173, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L36:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $174, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z10evolve_gpuPdS_S_S_PiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10evolve_gpuPdS_S_S_PiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "backup_gpu.hip"
.globl _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_ # -- Begin function _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_,@function
_Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_: # @_Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10evolve_gpuPdS_S_S_PiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_, .Lfunc_end0-_Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movsd %xmm1, 104(%rsp) # 8-byte Spill
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movl %r8d, 4(%rsp)
movsd %xmm0, 120(%rsp)
movq $0, 112(%rsp)
mulsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 88(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 80(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit15
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit17
movq %rbx, 96(%rsp) # 8-byte Spill
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shlq $3, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
leaq 64(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 56(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
movl $8, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z14__cudaSafeCall10hipError_tPKci.exit19
movq 24(%rsp), %rdi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
leaq 120(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
leaq 88(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 112(%rsp), %r15
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
cltd
idivl %r14d
movl %eax, %r12d
imull %r12d, %r12d
imull %r14d, %r14d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
orq %rax, %r14
leaq 136(%rsp), %rbx
leaq 128(%rsp), %r13
leaq 240(%rsp), %rbp
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_12
# %bb.11: # in Loop: Header=BB1_10 Depth=1
movq 32(%rsp), %rax
movq %rax, 232(%rsp)
movq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq 24(%rsp), %rax
movq %rax, 216(%rsp)
movq 72(%rsp), %rax
movq %rax, 208(%rsp)
movq 64(%rsp), %rax
movq %rax, 200(%rsp)
movq 56(%rsp), %rax
movq %rax, 192(%rsp)
movq 48(%rsp), %rax
movq %rax, 184(%rsp)
movq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 200(%rsp), %rax
movq %rax, 272(%rsp)
leaq 192(%rsp), %rax
movq %rax, 280(%rsp)
leaq 184(%rsp), %rax
movq %rax, 288(%rsp)
leaq 176(%rsp), %rax
movq %rax, 296(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
movq %rbx, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
movl $_Z10evolve_gpuPdS_S_S_PiS_S_S_, %edi
movq %rbp, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_12: # in Loop: Header=BB1_10 Depth=1
movq 8(%rsp), %rax
movq %rax, 24(%rsp)
movq 32(%rsp), %rax
movq %rax, 8(%rsp)
movsd 88(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %r15, %rdi
movsd 104(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq _Z4tpdtPddd
testl %eax, %eax
je .LBB1_14
# %bb.13: # in Loop: Header=BB1_10 Depth=1
movq 16(%rsp), %rdi
movl $8, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
jmp .LBB1_10
.LBB1_14:
movq 32(%rsp), %rsi
movslq 4(%rsp), %rdx
imulq %rdx, %rdx
shlq $3, %rdx
movq 96(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_15
# %bb.16: # %_Z14__cudaSafeCall10hipError_tPKci.exit21
movq 40(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_17
# %bb.18: # %_Z14__cudaSafeCall10hipError_tPKci.exit23
movq 80(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_19
# %bb.20: # %_Z14__cudaSafeCall10hipError_tPKci.exit25
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_21
# %bb.22: # %_Z14__cudaSafeCall10hipError_tPKci.exit27
movq 40(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_23
# %bb.24: # %_Z14__cudaSafeCall10hipError_tPKci.exit29
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 368
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $118, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $119, %ecx
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $120, %ecx
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $133, %ecx
jmp .LBB1_2
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $158, %ecx
jmp .LBB1_2
.LBB1_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $159, %ecx
jmp .LBB1_2
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $160, %ecx
jmp .LBB1_2
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $173, %ecx
jmp .LBB1_2
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $174, %ecx
.LBB1_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end1-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10evolve_gpuPdS_S_S_PiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10evolve_gpuPdS_S_S_PiS_S_S_,@object # @_Z10evolve_gpuPdS_S_S_PiS_S_S_
.section .rodata,"a",@progbits
.globl _Z10evolve_gpuPdS_S_S_PiS_S_S_
.p2align 3, 0x0
_Z10evolve_gpuPdS_S_S_PiS_S_S_:
.quad _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.size _Z10evolve_gpuPdS_S_S_PiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/abhashjain/CSC548/master/a2q3/backup_gpu.hip"
.size .L.str, 102
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10evolve_gpuPdS_S_S_PiS_S_S_"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__evolve_gpuPdS_S_S_PiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10evolve_gpuPdS_S_S_PiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void transposeUnroll4Col(int *in, int *out, const int nx, const int ny)
{
// set thread id.
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x * 4;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int ti = iy * nx + ix; // access in rows.
unsigned int to = ix * ny + iy; // access in cols.
if (ix + 3 * blockDim.x < nx && iy < ny)
{
out[ti] = in[to];
out[ti + blockDim.x] = in[to + ny * blockDim.x];
out[ti + blockDim.x * 2] = in[to + ny * blockDim.x * 2];
out[ti + blockDim.x * 3] = in[to + ny * blockDim.x * 3];
}
} | code for sm_80
Function : _Z19transposeUnroll4ColPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0030*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fc60000000f00 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ SHF.L.U32 R0, R12, 0x2, RZ ; /* 0x000000020c007819 */
/* 0x000fc600000006ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fe400078e0202 */
/*0080*/ IMAD R4, R0, UR4, R3 ; /* 0x0000000400047c24 */
/* 0x001fc6000f8e0203 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD R0, R12, 0x3, R4 ; /* 0x000000030c007824 */
/* 0x000fca00078e0204 */
/*00b0*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD R7, R4, c[0x0][0x174], R5 ; /* 0x00005d0004077a24 */
/* 0x000fe200078e0205 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0100*/ IMAD.WIDE.U32 R2, R7, R0, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0000 */
/*0110*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R9, R5, c[0x0][0x170], R4 ; /* 0x00005c0005097a24 */
/* 0x000fe400078e0204 */
/*0130*/ IMAD R11, R12, c[0x0][0x174], R7 ; /* 0x00005d000c0b7a24 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.WIDE.U32 R4, R9, R0, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fc800078e0000 */
/*0150*/ IMAD.WIDE.U32 R6, R11, R0, c[0x0][0x160] ; /* 0x000058000b067625 */
/* 0x000fe200078e0000 */
/*0160*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0041e8000c101904 */
/*0170*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R17, R9, c[0x0][0x0], RZ ; /* 0x0000000009117a10 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD R19, R12, c[0x0][0x174], R11 ; /* 0x00005d000c137a24 */
/* 0x000fc800078e020b */
/*01a0*/ IMAD.WIDE.U32 R8, R17, R0, c[0x0][0x168] ; /* 0x00005a0011087625 */
/* 0x000fc800078e0000 */
/*01b0*/ IMAD.WIDE.U32 R10, R19, R0, c[0x0][0x160] ; /* 0x00005800130a7625 */
/* 0x000fe200078e0000 */
/*01c0*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x004fea000c101904 */
/*01d0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R17, R17, c[0x0][0x0], RZ ; /* 0x0000000011117a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD R19, R12, c[0x0][0x174], R19 ; /* 0x00005d000c137a24 */
/* 0x000fc800078e0213 */
/*0200*/ IMAD.WIDE.U32 R2, R17, R0, c[0x0][0x168] ; /* 0x00005a0011027625 */
/* 0x000fc800078e0000 */
/*0210*/ IMAD.WIDE.U32 R4, R19, R0, c[0x0][0x160] ; /* 0x0000580013047625 */
/* 0x001fe200078e0000 */
/*0220*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fea000c101904 */
/*0230*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R7, R17, c[0x0][0x0], RZ ; /* 0x0000000011077a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0000 */
/*0260*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void transposeUnroll4Col(int *in, int *out, const int nx, const int ny)
{
// set thread id.
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x * 4;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int ti = iy * nx + ix; // access in rows.
unsigned int to = ix * ny + iy; // access in cols.
if (ix + 3 * blockDim.x < nx && iy < ny)
{
out[ti] = in[to];
out[ti + blockDim.x] = in[to + ny * blockDim.x];
out[ti + blockDim.x * 2] = in[to + ny * blockDim.x * 2];
out[ti + blockDim.x * 3] = in[to + ny * blockDim.x * 3];
}
} | .file "tmpxft_000b2a71_00000000-6_transposeUnroll4Col.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii
.type _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii, @function
_Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19transposeUnroll4ColPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii, .-_Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii
.globl _Z19transposeUnroll4ColPiS_ii
.type _Z19transposeUnroll4ColPiS_ii, @function
_Z19transposeUnroll4ColPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19transposeUnroll4ColPiS_ii, .-_Z19transposeUnroll4ColPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19transposeUnroll4ColPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19transposeUnroll4ColPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void transposeUnroll4Col(int *in, int *out, const int nx, const int ny)
{
// set thread id.
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x * 4;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int ti = iy * nx + ix; // access in rows.
unsigned int to = ix * ny + iy; // access in cols.
if (ix + 3 * blockDim.x < nx && iy < ny)
{
out[ti] = in[to];
out[ti + blockDim.x] = in[to + ny * blockDim.x];
out[ti + blockDim.x * 2] = in[to + ny * blockDim.x * 2];
out[ti + blockDim.x * 3] = in[to + ny * blockDim.x * 3];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeUnroll4Col(int *in, int *out, const int nx, const int ny)
{
// set thread id.
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x * 4;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int ti = iy * nx + ix; // access in rows.
unsigned int to = ix * ny + iy; // access in cols.
if (ix + 3 * blockDim.x < nx && iy < ny)
{
out[ti] = in[to];
out[ti + blockDim.x] = in[to + ny * blockDim.x];
out[ti + blockDim.x * 2] = in[to + ny * blockDim.x * 2];
out[ti + blockDim.x * 3] = in[to + ny * blockDim.x * 3];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeUnroll4Col(int *in, int *out, const int nx, const int ny)
{
// set thread id.
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x * 4;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int ti = iy * nx + ix; // access in rows.
unsigned int to = ix * ny + iy; // access in cols.
if (ix + 3 * blockDim.x < nx && iy < ny)
{
out[ti] = in[to];
out[ti + blockDim.x] = in[to + ny * blockDim.x];
out[ti + blockDim.x * 2] = in[to + ny * blockDim.x * 2];
out[ti + blockDim.x * 3] = in[to + ny * blockDim.x * 3];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19transposeUnroll4ColPiS_ii
.globl _Z19transposeUnroll4ColPiS_ii
.p2align 8
.type _Z19transposeUnroll4ColPiS_ii,@function
_Z19transposeUnroll4ColPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s7
s_mul_i32 s6, s7, 3
v_lshl_add_u32 v0, s14, 2, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s6, v0
v_cmp_gt_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s4, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v7, v[4:5], off
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
s_mul_i32 s4, s7, s5
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v0, s4, v2
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v7, off
global_load_b32 v7, v[0:1], off
v_dual_mov_b32 v1, v3 :: v_dual_add_nc_u32 v0, s7, v4
v_lshl_add_u32 v5, s4, 1, v2
v_mov_b32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v7, v[5:6], off
v_lshl_add_u32 v0, s7, 1, v4
v_mov_b32_e32 v1, v3
v_mad_u64_u32 v[5:6], null, s4, 3, v[2:3]
v_add_nc_u32_e32 v2, s6, v4
v_mov_b32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v5, v[5:6], off
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19transposeUnroll4ColPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19transposeUnroll4ColPiS_ii, .Lfunc_end0-_Z19transposeUnroll4ColPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19transposeUnroll4ColPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19transposeUnroll4ColPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeUnroll4Col(int *in, int *out, const int nx, const int ny)
{
// set thread id.
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x * 4;
unsigned int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int ti = iy * nx + ix; // access in rows.
unsigned int to = ix * ny + iy; // access in cols.
if (ix + 3 * blockDim.x < nx && iy < ny)
{
out[ti] = in[to];
out[ti + blockDim.x] = in[to + ny * blockDim.x];
out[ti + blockDim.x * 2] = in[to + ny * blockDim.x * 2];
out[ti + blockDim.x * 3] = in[to + ny * blockDim.x * 3];
}
} | .text
.file "transposeUnroll4Col.hip"
.globl _Z34__device_stub__transposeUnroll4ColPiS_ii # -- Begin function _Z34__device_stub__transposeUnroll4ColPiS_ii
.p2align 4, 0x90
.type _Z34__device_stub__transposeUnroll4ColPiS_ii,@function
_Z34__device_stub__transposeUnroll4ColPiS_ii: # @_Z34__device_stub__transposeUnroll4ColPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19transposeUnroll4ColPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__transposeUnroll4ColPiS_ii, .Lfunc_end0-_Z34__device_stub__transposeUnroll4ColPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19transposeUnroll4ColPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19transposeUnroll4ColPiS_ii,@object # @_Z19transposeUnroll4ColPiS_ii
.section .rodata,"a",@progbits
.globl _Z19transposeUnroll4ColPiS_ii
.p2align 3, 0x0
_Z19transposeUnroll4ColPiS_ii:
.quad _Z34__device_stub__transposeUnroll4ColPiS_ii
.size _Z19transposeUnroll4ColPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19transposeUnroll4ColPiS_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__transposeUnroll4ColPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19transposeUnroll4ColPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19transposeUnroll4ColPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002600 */
/*0030*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fc60000000f00 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ SHF.L.U32 R0, R12, 0x2, RZ ; /* 0x000000020c007819 */
/* 0x000fc600000006ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fe400078e0202 */
/*0080*/ IMAD R4, R0, UR4, R3 ; /* 0x0000000400047c24 */
/* 0x001fc6000f8e0203 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD R0, R12, 0x3, R4 ; /* 0x000000030c007824 */
/* 0x000fca00078e0204 */
/*00b0*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD R7, R4, c[0x0][0x174], R5 ; /* 0x00005d0004077a24 */
/* 0x000fe200078e0205 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0100*/ IMAD.WIDE.U32 R2, R7, R0, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0000 */
/*0110*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD R9, R5, c[0x0][0x170], R4 ; /* 0x00005c0005097a24 */
/* 0x000fe400078e0204 */
/*0130*/ IMAD R11, R12, c[0x0][0x174], R7 ; /* 0x00005d000c0b7a24 */
/* 0x000fe400078e0207 */
/*0140*/ IMAD.WIDE.U32 R4, R9, R0, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fc800078e0000 */
/*0150*/ IMAD.WIDE.U32 R6, R11, R0, c[0x0][0x160] ; /* 0x000058000b067625 */
/* 0x000fe200078e0000 */
/*0160*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0041e8000c101904 */
/*0170*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IADD3 R17, R9, c[0x0][0x0], RZ ; /* 0x0000000009117a10 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD R19, R12, c[0x0][0x174], R11 ; /* 0x00005d000c137a24 */
/* 0x000fc800078e020b */
/*01a0*/ IMAD.WIDE.U32 R8, R17, R0, c[0x0][0x168] ; /* 0x00005a0011087625 */
/* 0x000fc800078e0000 */
/*01b0*/ IMAD.WIDE.U32 R10, R19, R0, c[0x0][0x160] ; /* 0x00005800130a7625 */
/* 0x000fe200078e0000 */
/*01c0*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x004fea000c101904 */
/*01d0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R17, R17, c[0x0][0x0], RZ ; /* 0x0000000011117a10 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD R19, R12, c[0x0][0x174], R19 ; /* 0x00005d000c137a24 */
/* 0x000fc800078e0213 */
/*0200*/ IMAD.WIDE.U32 R2, R17, R0, c[0x0][0x168] ; /* 0x00005a0011027625 */
/* 0x000fc800078e0000 */
/*0210*/ IMAD.WIDE.U32 R4, R19, R0, c[0x0][0x160] ; /* 0x0000580013047625 */
/* 0x001fe200078e0000 */
/*0220*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fea000c101904 */
/*0230*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R7, R17, c[0x0][0x0], RZ ; /* 0x0000000011077a10 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fca00078e0000 */
/*0260*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19transposeUnroll4ColPiS_ii
.globl _Z19transposeUnroll4ColPiS_ii
.p2align 8
.type _Z19transposeUnroll4ColPiS_ii,@function
_Z19transposeUnroll4ColPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s7
s_mul_i32 s6, s7, 3
v_lshl_add_u32 v0, s14, 2, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s6, v0
v_cmp_gt_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s4, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v7, v[4:5], off
v_mad_u64_u32 v[4:5], null, v1, s4, v[0:1]
s_mul_i32 s4, s7, s5
v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v0, s4, v2
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v7, off
global_load_b32 v7, v[0:1], off
v_dual_mov_b32 v1, v3 :: v_dual_add_nc_u32 v0, s7, v4
v_lshl_add_u32 v5, s4, 1, v2
v_mov_b32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v7, v[5:6], off
v_lshl_add_u32 v0, s7, 1, v4
v_mov_b32_e32 v1, v3
v_mad_u64_u32 v[5:6], null, s4, 3, v[2:3]
v_add_nc_u32_e32 v2, s6, v4
v_mov_b32_e32 v6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v5, v[5:6], off
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19transposeUnroll4ColPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19transposeUnroll4ColPiS_ii, .Lfunc_end0-_Z19transposeUnroll4ColPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19transposeUnroll4ColPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19transposeUnroll4ColPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2a71_00000000-6_transposeUnroll4Col.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii
.type _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii, @function
_Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19transposeUnroll4ColPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii, .-_Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii
.globl _Z19transposeUnroll4ColPiS_ii
.type _Z19transposeUnroll4ColPiS_ii, @function
_Z19transposeUnroll4ColPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19transposeUnroll4ColPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19transposeUnroll4ColPiS_ii, .-_Z19transposeUnroll4ColPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19transposeUnroll4ColPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19transposeUnroll4ColPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transposeUnroll4Col.hip"
.globl _Z34__device_stub__transposeUnroll4ColPiS_ii # -- Begin function _Z34__device_stub__transposeUnroll4ColPiS_ii
.p2align 4, 0x90
.type _Z34__device_stub__transposeUnroll4ColPiS_ii,@function
_Z34__device_stub__transposeUnroll4ColPiS_ii: # @_Z34__device_stub__transposeUnroll4ColPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19transposeUnroll4ColPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__transposeUnroll4ColPiS_ii, .Lfunc_end0-_Z34__device_stub__transposeUnroll4ColPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19transposeUnroll4ColPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19transposeUnroll4ColPiS_ii,@object # @_Z19transposeUnroll4ColPiS_ii
.section .rodata,"a",@progbits
.globl _Z19transposeUnroll4ColPiS_ii
.p2align 3, 0x0
_Z19transposeUnroll4ColPiS_ii:
.quad _Z34__device_stub__transposeUnroll4ColPiS_ii
.size _Z19transposeUnroll4ColPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19transposeUnroll4ColPiS_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__transposeUnroll4ColPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19transposeUnroll4ColPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
/* *
HW2 by Jiongfeng Chen
Parallelize the sequential version of Rabin-Karp String matching algorithm
on GPU: Searching for multiple patterns in the input sequence
Test Case:
input string:"Hello, 297 Class!"
pattern 1:"alxxl";
pattern 2:"llo";
pattern 3:", 297";
pattern 4:"97 Cl";
Output:
Kernel Execution Time: 5336 cycles
Total cycles: 5336
Kernel Execution Time: 5336 cycles
Searching for multiple patterns in the input sequence
Input string: Hello, 297 Class!
Pattern: "llo" was found.
Pattern: ", 297" was found.
Pattern: "97 Cl" was found.
run:nvcc -I/usr/local/cuda/include -I. -lineinfo -arch=sm_53 --ptxas-options=-v -g -c cmpe297_hw2_rabin_karp_multiPattern.cu -o cmpe297_hw2_rabin_karp_multiPattern.o
*/
#include<stdio.h>
#include<iostream>
#include <cuda_runtime.h>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__device__ int
memcpy(char* input, int index, char* pattern, int pattern_length)
{
for(int i = 0; i< pattern_length; i++)
if(pattern[i] != input[index+i])
return 1;
return 0;
}
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int* patternLength, int* patHashes, int* result, int *runtime)
{
int start_time = clock64();
int tid = threadIdx.x;
int inputHash = 0;
int searchSpaceIndex[4];
int patternIndex[4];
for(int i = 0; i< 4; i++)
result[i]=0;
for(int i = 0; i< 4; i++)
searchSpaceIndex[i]=0;
for (int i = 0; i < 4; i++)
if(i==0)
searchSpaceIndex[i] = input_length - patternLength[i] +1 ;
else
searchSpaceIndex[i] = searchSpaceIndex[i-1] + input_length - patternLength[i] +1 ;
//printf("C----tid-=%d--------%d-%d-%d-%d\n", tid,searchSpaceIndex[0],searchSpaceIndex[1] ,searchSpaceIndex[2] ,searchSpaceIndex[3] );
for(int i = 0; i < 4; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternLength[i-1];
int searchStart;
if(tid>=0 && tid <searchSpaceIndex[0])
{
searchStart =tid-searchSpaceIndex[0] +patternIndex[0];
for(int i = searchStart; i< searchStart +patternLength[0]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[0] && 1)
result[0]=1;
}
if(tid>=searchSpaceIndex[0] && tid <searchSpaceIndex[1])
{
searchStart =tid-searchSpaceIndex[1] +patternIndex[1];
for(int i = searchStart; i< searchStart +patternLength[1]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[1] && 1)
result[1]=1;
}
if(tid>=searchSpaceIndex[1] && tid <searchSpaceIndex[2])
{
searchStart =tid-searchSpaceIndex[2] +patternIndex[2];
for(int i = searchStart; i< searchStart +patternLength[2]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[2] && memcpy(&(input[searchStart]),0, pattern+patternIndex[2], patternLength[2])==0)
result[2]=1;
}
if(tid>=searchSpaceIndex[2] && tid <searchSpaceIndex[3])
{
searchStart =tid-searchSpaceIndex[3] +patternIndex[3];
for(int i = searchStart; i< searchStart +patternLength[3]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[3] && memcpy(&(input[searchStart]),0, pattern+patternIndex[3], patternLength[3])==0)
result[3]=1;
}
int stop_time = clock64();
runtime[tid] = (int)(stop_time - start_time);
}
int main()
{
// host variables
//char input[] = "HEABAL"; /*Sample Input*/
char input[] = "Hello, 297 Class!"; /*Multiple Patter Version: Input string*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int input_length = 17; /*Input Length*/
/*ADD CODE HERE*/;
int pattern_number = 4; /*Multiple Patter Version: Pattern Number*/
//int pattern_length = 2; /*Pattern Length*/
int match_times = 0; /*Match Times*/
cudaError_t err = cudaSuccess;
int * patternsLength;
int patHashes[4]; /*hash for the pattern*/
int patternFound[4]; /*Multiple Patter Version: Result Array*/
char* patterns[4]; /*Multiple Patter Version: Pattern String*/
patterns[0] ="alxxl";
patterns[1] ="llo";
patterns[2] =", 297";
patterns[3] ="97 Cl";
// device variables
char* d_input;
char* d_pattern;
int* d_result;
int* d_runtime;
int* d_patHashes;
int* d_patternsLength;
char* d_patterns;
//convert the string arrary to 1D string and pass to cuda fucntion
//1D string
char patternLong[100] = "";
int* patternIndex;
int p_size = 4*sizeof(int);
patternsLength = (int *) malloc(p_size);
memset(patternsLength, 0, p_size);
for(int i = 0; i < pattern_number; i++)
patternsLength[i] = strlen(patterns[i]);
patternIndex = (int *) malloc(pattern_number*sizeof(int));
for(int i = 0; i < pattern_number; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternsLength[i-1];
for(int i = 0; i < pattern_number; i++)
strcat(patternLong, patterns[i]);
printf("Pattern: \"%s\" ...\n", patternLong);
printf("Pattern: \"%s\"\n", patterns[0]);
for(int i = 0; i < pattern_number; i++)
printf("Pattern: \"%s\", lenth: %d.\n", patterns[i], patternsLength[i]);
int totalPatternLength=0;
for(int i = 0; i < pattern_number; i++)
totalPatternLength += patternsLength[i];
// measure the execution time by using clock() api in the kernel as we did in Lab3
/*ADD CODE HERE*/;
match_times=0;
for (int i = 0; i < pattern_number; i++)
match_times += strlen(input) - patternsLength[i] +1 ;
int runtime_size = match_times*sizeof(int);
cudaMalloc((void**)&d_runtime, runtime_size);
runtime = (int *) malloc(runtime_size);
memset(runtime, 0, runtime_size);
result = (int *) malloc((match_times)*sizeof(int));
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_number; i++)
{
int tmp=patternIndex[i];
patHashes[i] =0;
for (int j = 0; j < patternsLength[i]; j++)
{
//if(i==3) printf("xxx %c \n", patternLong[tmp+j]);
patHashes[i] = (patHashes[i] * 256 + patternLong[tmp+j]) % 997;
}
printf("patHash %d \n", patHashes[i]);
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
int size = input_length*sizeof(char);
err = cudaMalloc((void**)&d_input, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input string from the host memory to the CUDA device\n");
err = cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
size = totalPatternLength*sizeof(char);
err = cudaMalloc((void**)&d_pattern, size);
printf("Copy pattern string from the host memory to the CUDA device\n");
err = cudaMemcpy(d_pattern, patternLong, size, cudaMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = cudaMalloc((void**)&d_patHashes, size);
printf("Copy Hashes from the host memory to the CUDA device\n");
err = cudaMemcpy(d_patHashes, patHashes, size, cudaMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = cudaMalloc((void**)&d_patternsLength, size);
printf("Copy patternsLength from the host memory to the CUDA device\n");
err = cudaMemcpy(d_patternsLength, patternsLength, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
size = pattern_number*sizeof(int);
err = cudaMalloc((void**)&d_result, size);
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocksPerGrid = 1;// FILL HERE
int threadsPerBlock = match_times;// FILL HERE
//printf("C--------=%d--------%s\n",match_times, "");
findIfExistsCu<<<blocksPerGrid, threadsPerBlock>>>(d_input, input_length, d_pattern, d_patternsLength, d_patHashes, d_result,d_runtime);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaThreadSynchronize();
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
// Copy the device result device memory to the host result matrix
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(result, d_result, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy result from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaThreadSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
cudaMemcpy(runtime, d_runtime, runtime_size, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
/*RUN TIME calculation*//*ADD CODE HERE:*/
unsigned long long elapsed_time = 0;
for(int i = 0; i < match_times; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
//Print
printf("Kernel Execution Time: %llu cycles\n", elapsed_time);
printf("Total cycles: %d \n", elapsed_time);
printf("Kernel Execution Time: %d cycles\n", elapsed_time);
printf("Searching for multiple patterns in the input sequence\n");
printf("Input string: %s\n", input);
//Print Result[];
for(int i = 0; i < pattern_number; i++)
if(result[i]==1)
printf("Pattern: \"%s\" was found.\n", patterns[i]);
// Free device memory
cudaFree(d_input);
cudaFree(d_pattern);
cudaFree(d_result);
cudaFree(d_runtime);
cudaFree(d_patHashes);
cudaFree(d_patternsLength);
cudaFree(d_patterns);
// Free host memory
free(result);
free(runtime);
return 0;
} | .file "tmpxft_001a5b74_00000000-6_cmpe297_hw2_rabin_karp_multiPattern.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6memcpyPciS_i
.type _Z6memcpyPciS_i, @function
_Z6memcpyPciS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z6memcpyPciS_i, .-_Z6memcpyPciS_i
.globl _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
.type _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_, @function
_Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14findIfExistsCuPciS_PiS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_, .-_Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
.globl _Z14findIfExistsCuPciS_PiS0_S0_S0_
.type _Z14findIfExistsCuPciS_PiS0_S0_S0_, @function
_Z14findIfExistsCuPciS_PiS0_S0_S0_:
.LFB3696:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z14findIfExistsCuPciS_PiS0_S0_S0_, .-_Z14findIfExistsCuPciS_PiS0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "alxxl"
.LC1:
.string "llo"
.LC2:
.string ", 297"
.LC3:
.string "97 Cl"
.LC4:
.string "Pattern: \"%s\" ...\n"
.LC5:
.string "Pattern: \"%s\"\n"
.LC6:
.string "Pattern: \"%s\", lenth: %d.\n"
.LC7:
.string "patHash %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Failed to allocate device d_input(error code %s)!\n"
.align 8
.LC9:
.string "Copy input string from the host memory to the CUDA device\n"
.align 8
.LC10:
.string "Copy pattern string from the host memory to the CUDA device\n"
.align 8
.LC11:
.string "Copy Hashes from the host memory to the CUDA device\n"
.align 8
.LC12:
.string "Copy patternsLength from the host memory to the CUDA device\n"
.align 8
.LC13:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC14:
.string "Copy output data from the CUDA device to the host memory\n"
.align 8
.LC15:
.string "Failed to copy result from device to host (error code %s)!\n"
.align 8
.LC16:
.string "Kernel Execution Time: %llu cycles\n"
.section .rodata.str1.1
.LC17:
.string "Total cycles: %d \n"
.section .rodata.str1.8
.align 8
.LC18:
.string "Kernel Execution Time: %d cycles\n"
.align 8
.LC19:
.string "Searching for multiple patterns in the input sequence\n"
.section .rodata.str1.1
.LC20:
.string "Input string: %s\n"
.LC21:
.string "Pattern: \"%s\" was found.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $312, %rsp
.cfi_def_cfa_offset 368
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
movabsq $3611935758223172936, %rax
movabsq $8319100054293985081, %rdx
movq %rax, 160(%rsp)
movq %rdx, 168(%rsp)
movw $33, 176(%rsp)
leaq .LC0(%rip), %rax
movq %rax, 128(%rsp)
leaq .LC1(%rip), %rax
movq %rax, 136(%rsp)
leaq .LC2(%rip), %rax
movq %rax, 144(%rsp)
leaq .LC3(%rip), %rax
movq %rax, 152(%rsp)
movq $0, 192(%rsp)
movq $0, 200(%rsp)
movq $0, 208(%rsp)
movq $0, 216(%rsp)
movq $0, 224(%rsp)
movq $0, 232(%rsp)
movq $0, 240(%rsp)
movq $0, 248(%rsp)
movq $0, 256(%rsp)
movq $0, 264(%rsp)
movq $0, 272(%rsp)
movq $0, 280(%rsp)
movl $0, 288(%rsp)
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
movups %xmm0, (%rax)
movl $0, %ebp
.L14:
movq 128(%rsp,%rbp,8), %rdi
call strlen@PLT
movl %eax, (%rbx,%rbp,4)
addq $1, %rbp
cmpq $4, %rbp
jne .L14
movl $16, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
jmp .L18
.L45:
movl $0, (%r14)
addq $1, %rax
.L18:
testl %eax, %eax
je .L45
movl -4(%rbx,%rax,4), %edx
addl -4(%r14,%rax,4), %edx
movl %edx, (%r14,%rax,4)
addq $1, %rax
cmpq $4, %rax
jne .L18
leaq 128(%rsp), %rbp
leaq 160(%rsp), %r13
leaq 192(%rsp), %r12
.L19:
movq 0(%rbp), %rsi
movl $100, %edx
movq %r12, %rdi
call __strcat_chk@PLT
addq $8, %rbp
cmpq %r13, %rbp
jne .L19
leaq 192(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC0(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC6(%rip), %r12
.L20:
movl (%rbx,%rbp,4), %ecx
movq 128(%rsp,%rbp,8), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq $4, %rbp
jne .L20
movl 4(%rbx), %eax
addl (%rbx), %eax
addl 8(%rbx), %eax
addl 12(%rbx), %eax
movl %eax, 28(%rsp)
leaq 160(%rsp), %rdi
call strlen@PLT
movq %rbx, %rdx
leaq 16(%rbx), %rsi
movl $0, %ecx
addl $1, %eax
.L21:
movl %eax, %r12d
subl (%rdx), %r12d
addl %ecx, %r12d
movl %r12d, %ecx
addq $4, %rdx
cmpq %rsi, %rdx
jne .L21
movslq %r12d, %rbp
leal 0(,%r12,4), %eax
movslq %eax, %r15
movq %r15, 8(%rsp)
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq %r15, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %r15, %rcx
movq %r15, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 0(,%rbp,4), %rax
movq %rax, 16(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r15
leaq 112(%rsp), %r13
movl $0, %ebp
.L24:
movl (%r14,%rbp), %eax
movq %r13, %rdi
movl $0, 0(%r13)
movl (%rbx,%rbp), %esi
testl %esi, %esi
jle .L22
cltq
leaq 192(%rsp), %rdx
leaq (%rdx,%rax), %rcx
movslq %esi, %rsi
addq %rax, %rsi
addq %rdx, %rsi
movl $0, %eax
.L23:
sall $8, %eax
movsbl (%rcx), %edx
addl %eax, %edx
movslq %edx, %rax
imulq $-2089327119, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $9, %eax
movl %edx, %r8d
sarl $31, %r8d
subl %r8d, %eax
imull $997, %eax, %r8d
movl %edx, %eax
subl %r8d, %eax
addq $1, %rcx
cmpq %rsi, %rcx
jne .L23
movl %eax, (%rdi)
.L22:
movl (%rdi), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
addq $4, %rbp
cmpq $16, %rbp
jne .L24
leaq 40(%rsp), %rdi
movl $17, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 160(%rsp), %rsi
movl $1, %ecx
movl $17, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 192(%rsp), %rsi
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 72(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
leaq 56(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl %r12d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L27:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L49
call cudaThreadSynchronize@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $16, %edx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 64(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
testl %r12d, %r12d
jle .L35
movq %rbx, %rax
movq 16(%rsp), %rcx
addq %rbx, %rcx
movl $0, %ebx
.L31:
movslq (%rax), %rdx
cmpq %rdx, %rbx
cmovb %rdx, %rbx
addq $4, %rax
cmpq %rax, %rcx
jne .L31
.L30:
movq %rbx, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 160(%rsp), %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L33
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
subq $8, %rsp
.cfi_def_cfa_offset 376
pushq 72(%rsp)
.cfi_def_cfa_offset 384
movq 72(%rsp), %r9
movq 88(%rsp), %r8
movq 96(%rsp), %rcx
movq 64(%rsp), %rdx
movl $17, %esi
movq 56(%rsp), %rdi
call _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L27
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl $0, %ebx
jmp .L30
.L32:
addq $1, %rbx
cmpq $4, %rbx
je .L51
.L33:
cmpl $1, (%r15,%rbx,4)
jne .L32
movq 128(%rsp,%rbx,8), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L51:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC22:
.string "_Z14findIfExistsCuPciS_PiS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z14findIfExistsCuPciS_PiS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
/* *
HW2 by Jiongfeng Chen
Parallelize the sequential version of Rabin-Karp String matching algorithm
on GPU: Searching for multiple patterns in the input sequence
Test Case:
input string:"Hello, 297 Class!"
pattern 1:"alxxl";
pattern 2:"llo";
pattern 3:", 297";
pattern 4:"97 Cl";
Output:
Kernel Execution Time: 5336 cycles
Total cycles: 5336
Kernel Execution Time: 5336 cycles
Searching for multiple patterns in the input sequence
Input string: Hello, 297 Class!
Pattern: "llo" was found.
Pattern: ", 297" was found.
Pattern: "97 Cl" was found.
run:nvcc -I/usr/local/cuda/include -I. -lineinfo -arch=sm_53 --ptxas-options=-v -g -c cmpe297_hw2_rabin_karp_multiPattern.cu -o cmpe297_hw2_rabin_karp_multiPattern.o
*/
#include<stdio.h>
#include<iostream>
#include <cuda_runtime.h>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__device__ int
memcpy(char* input, int index, char* pattern, int pattern_length)
{
for(int i = 0; i< pattern_length; i++)
if(pattern[i] != input[index+i])
return 1;
return 0;
}
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int* patternLength, int* patHashes, int* result, int *runtime)
{
int start_time = clock64();
int tid = threadIdx.x;
int inputHash = 0;
int searchSpaceIndex[4];
int patternIndex[4];
for(int i = 0; i< 4; i++)
result[i]=0;
for(int i = 0; i< 4; i++)
searchSpaceIndex[i]=0;
for (int i = 0; i < 4; i++)
if(i==0)
searchSpaceIndex[i] = input_length - patternLength[i] +1 ;
else
searchSpaceIndex[i] = searchSpaceIndex[i-1] + input_length - patternLength[i] +1 ;
//printf("C----tid-=%d--------%d-%d-%d-%d\n", tid,searchSpaceIndex[0],searchSpaceIndex[1] ,searchSpaceIndex[2] ,searchSpaceIndex[3] );
for(int i = 0; i < 4; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternLength[i-1];
int searchStart;
if(tid>=0 && tid <searchSpaceIndex[0])
{
searchStart =tid-searchSpaceIndex[0] +patternIndex[0];
for(int i = searchStart; i< searchStart +patternLength[0]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[0] && 1)
result[0]=1;
}
if(tid>=searchSpaceIndex[0] && tid <searchSpaceIndex[1])
{
searchStart =tid-searchSpaceIndex[1] +patternIndex[1];
for(int i = searchStart; i< searchStart +patternLength[1]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[1] && 1)
result[1]=1;
}
if(tid>=searchSpaceIndex[1] && tid <searchSpaceIndex[2])
{
searchStart =tid-searchSpaceIndex[2] +patternIndex[2];
for(int i = searchStart; i< searchStart +patternLength[2]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[2] && memcpy(&(input[searchStart]),0, pattern+patternIndex[2], patternLength[2])==0)
result[2]=1;
}
if(tid>=searchSpaceIndex[2] && tid <searchSpaceIndex[3])
{
searchStart =tid-searchSpaceIndex[3] +patternIndex[3];
for(int i = searchStart; i< searchStart +patternLength[3]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[3] && memcpy(&(input[searchStart]),0, pattern+patternIndex[3], patternLength[3])==0)
result[3]=1;
}
int stop_time = clock64();
runtime[tid] = (int)(stop_time - start_time);
}
int main()
{
// host variables
//char input[] = "HEABAL"; /*Sample Input*/
char input[] = "Hello, 297 Class!"; /*Multiple Patter Version: Input string*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int input_length = 17; /*Input Length*/
/*ADD CODE HERE*/;
int pattern_number = 4; /*Multiple Patter Version: Pattern Number*/
//int pattern_length = 2; /*Pattern Length*/
int match_times = 0; /*Match Times*/
cudaError_t err = cudaSuccess;
int * patternsLength;
int patHashes[4]; /*hash for the pattern*/
int patternFound[4]; /*Multiple Patter Version: Result Array*/
char* patterns[4]; /*Multiple Patter Version: Pattern String*/
patterns[0] ="alxxl";
patterns[1] ="llo";
patterns[2] =", 297";
patterns[3] ="97 Cl";
// device variables
char* d_input;
char* d_pattern;
int* d_result;
int* d_runtime;
int* d_patHashes;
int* d_patternsLength;
char* d_patterns;
//convert the string arrary to 1D string and pass to cuda fucntion
//1D string
char patternLong[100] = "";
int* patternIndex;
int p_size = 4*sizeof(int);
patternsLength = (int *) malloc(p_size);
memset(patternsLength, 0, p_size);
for(int i = 0; i < pattern_number; i++)
patternsLength[i] = strlen(patterns[i]);
patternIndex = (int *) malloc(pattern_number*sizeof(int));
for(int i = 0; i < pattern_number; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternsLength[i-1];
for(int i = 0; i < pattern_number; i++)
strcat(patternLong, patterns[i]);
printf("Pattern: \"%s\" ...\n", patternLong);
printf("Pattern: \"%s\"\n", patterns[0]);
for(int i = 0; i < pattern_number; i++)
printf("Pattern: \"%s\", lenth: %d.\n", patterns[i], patternsLength[i]);
int totalPatternLength=0;
for(int i = 0; i < pattern_number; i++)
totalPatternLength += patternsLength[i];
// measure the execution time by using clock() api in the kernel as we did in Lab3
/*ADD CODE HERE*/;
match_times=0;
for (int i = 0; i < pattern_number; i++)
match_times += strlen(input) - patternsLength[i] +1 ;
int runtime_size = match_times*sizeof(int);
cudaMalloc((void**)&d_runtime, runtime_size);
runtime = (int *) malloc(runtime_size);
memset(runtime, 0, runtime_size);
result = (int *) malloc((match_times)*sizeof(int));
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_number; i++)
{
int tmp=patternIndex[i];
patHashes[i] =0;
for (int j = 0; j < patternsLength[i]; j++)
{
//if(i==3) printf("xxx %c \n", patternLong[tmp+j]);
patHashes[i] = (patHashes[i] * 256 + patternLong[tmp+j]) % 997;
}
printf("patHash %d \n", patHashes[i]);
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
int size = input_length*sizeof(char);
err = cudaMalloc((void**)&d_input, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input string from the host memory to the CUDA device\n");
err = cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
size = totalPatternLength*sizeof(char);
err = cudaMalloc((void**)&d_pattern, size);
printf("Copy pattern string from the host memory to the CUDA device\n");
err = cudaMemcpy(d_pattern, patternLong, size, cudaMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = cudaMalloc((void**)&d_patHashes, size);
printf("Copy Hashes from the host memory to the CUDA device\n");
err = cudaMemcpy(d_patHashes, patHashes, size, cudaMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = cudaMalloc((void**)&d_patternsLength, size);
printf("Copy patternsLength from the host memory to the CUDA device\n");
err = cudaMemcpy(d_patternsLength, patternsLength, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
size = pattern_number*sizeof(int);
err = cudaMalloc((void**)&d_result, size);
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocksPerGrid = 1;// FILL HERE
int threadsPerBlock = match_times;// FILL HERE
//printf("C--------=%d--------%s\n",match_times, "");
findIfExistsCu<<<blocksPerGrid, threadsPerBlock>>>(d_input, input_length, d_pattern, d_patternsLength, d_patHashes, d_result,d_runtime);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaThreadSynchronize();
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
// Copy the device result device memory to the host result matrix
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
err = cudaMemcpy(result, d_result, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy result from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaThreadSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
cudaMemcpy(runtime, d_runtime, runtime_size, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
/*RUN TIME calculation*//*ADD CODE HERE:*/
unsigned long long elapsed_time = 0;
for(int i = 0; i < match_times; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
//Print
printf("Kernel Execution Time: %llu cycles\n", elapsed_time);
printf("Total cycles: %d \n", elapsed_time);
printf("Kernel Execution Time: %d cycles\n", elapsed_time);
printf("Searching for multiple patterns in the input sequence\n");
printf("Input string: %s\n", input);
//Print Result[];
for(int i = 0; i < pattern_number; i++)
if(result[i]==1)
printf("Pattern: \"%s\" was found.\n", patterns[i]);
// Free device memory
cudaFree(d_input);
cudaFree(d_pattern);
cudaFree(d_result);
cudaFree(d_runtime);
cudaFree(d_patHashes);
cudaFree(d_patternsLength);
cudaFree(d_patterns);
// Free host memory
free(result);
free(runtime);
return 0;
} | // CMPE297-6 HW2
// CUDA version Rabin-Karp
/* *
HW2 by Jiongfeng Chen
Parallelize the sequential version of Rabin-Karp String matching algorithm
on GPU: Searching for multiple patterns in the input sequence
Test Case:
input string:"Hello, 297 Class!"
pattern 1:"alxxl";
pattern 2:"llo";
pattern 3:", 297";
pattern 4:"97 Cl";
Output:
Kernel Execution Time: 5336 cycles
Total cycles: 5336
Kernel Execution Time: 5336 cycles
Searching for multiple patterns in the input sequence
Input string: Hello, 297 Class!
Pattern: "llo" was found.
Pattern: ", 297" was found.
Pattern: "97 Cl" was found.
run:nvcc -I/usr/local/cuda/include -I. -lineinfo -arch=sm_53 --ptxas-options=-v -g -c cmpe297_hw2_rabin_karp_multiPattern.cu -o cmpe297_hw2_rabin_karp_multiPattern.o
*/
#include<stdio.h>
#include<iostream>
#include <hip/hip_runtime.h>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__device__ int
memcpy(char* input, int index, char* pattern, int pattern_length)
{
for(int i = 0; i< pattern_length; i++)
if(pattern[i] != input[index+i])
return 1;
return 0;
}
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int* patternLength, int* patHashes, int* result, int *runtime)
{
int start_time = clock64();
int tid = threadIdx.x;
int inputHash = 0;
int searchSpaceIndex[4];
int patternIndex[4];
for(int i = 0; i< 4; i++)
result[i]=0;
for(int i = 0; i< 4; i++)
searchSpaceIndex[i]=0;
for (int i = 0; i < 4; i++)
if(i==0)
searchSpaceIndex[i] = input_length - patternLength[i] +1 ;
else
searchSpaceIndex[i] = searchSpaceIndex[i-1] + input_length - patternLength[i] +1 ;
//printf("C----tid-=%d--------%d-%d-%d-%d\n", tid,searchSpaceIndex[0],searchSpaceIndex[1] ,searchSpaceIndex[2] ,searchSpaceIndex[3] );
for(int i = 0; i < 4; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternLength[i-1];
int searchStart;
if(tid>=0 && tid <searchSpaceIndex[0])
{
searchStart =tid-searchSpaceIndex[0] +patternIndex[0];
for(int i = searchStart; i< searchStart +patternLength[0]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[0] && 1)
result[0]=1;
}
if(tid>=searchSpaceIndex[0] && tid <searchSpaceIndex[1])
{
searchStart =tid-searchSpaceIndex[1] +patternIndex[1];
for(int i = searchStart; i< searchStart +patternLength[1]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[1] && 1)
result[1]=1;
}
if(tid>=searchSpaceIndex[1] && tid <searchSpaceIndex[2])
{
searchStart =tid-searchSpaceIndex[2] +patternIndex[2];
for(int i = searchStart; i< searchStart +patternLength[2]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[2] && memcpy(&(input[searchStart]),0, pattern+patternIndex[2], patternLength[2])==0)
result[2]=1;
}
if(tid>=searchSpaceIndex[2] && tid <searchSpaceIndex[3])
{
searchStart =tid-searchSpaceIndex[3] +patternIndex[3];
for(int i = searchStart; i< searchStart +patternLength[3]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[3] && memcpy(&(input[searchStart]),0, pattern+patternIndex[3], patternLength[3])==0)
result[3]=1;
}
int stop_time = clock64();
runtime[tid] = (int)(stop_time - start_time);
}
int main()
{
// host variables
//char input[] = "HEABAL"; /*Sample Input*/
char input[] = "Hello, 297 Class!"; /*Multiple Patter Version: Input string*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int input_length = 17; /*Input Length*/
/*ADD CODE HERE*/;
int pattern_number = 4; /*Multiple Patter Version: Pattern Number*/
//int pattern_length = 2; /*Pattern Length*/
int match_times = 0; /*Match Times*/
hipError_t err = hipSuccess;
int * patternsLength;
int patHashes[4]; /*hash for the pattern*/
int patternFound[4]; /*Multiple Patter Version: Result Array*/
char* patterns[4]; /*Multiple Patter Version: Pattern String*/
patterns[0] ="alxxl";
patterns[1] ="llo";
patterns[2] =", 297";
patterns[3] ="97 Cl";
// device variables
char* d_input;
char* d_pattern;
int* d_result;
int* d_runtime;
int* d_patHashes;
int* d_patternsLength;
char* d_patterns;
//convert the string arrary to 1D string and pass to cuda fucntion
//1D string
char patternLong[100] = "";
int* patternIndex;
int p_size = 4*sizeof(int);
patternsLength = (int *) malloc(p_size);
memset(patternsLength, 0, p_size);
for(int i = 0; i < pattern_number; i++)
patternsLength[i] = strlen(patterns[i]);
patternIndex = (int *) malloc(pattern_number*sizeof(int));
for(int i = 0; i < pattern_number; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternsLength[i-1];
for(int i = 0; i < pattern_number; i++)
strcat(patternLong, patterns[i]);
printf("Pattern: \"%s\" ...\n", patternLong);
printf("Pattern: \"%s\"\n", patterns[0]);
for(int i = 0; i < pattern_number; i++)
printf("Pattern: \"%s\", lenth: %d.\n", patterns[i], patternsLength[i]);
int totalPatternLength=0;
for(int i = 0; i < pattern_number; i++)
totalPatternLength += patternsLength[i];
// measure the execution time by using clock() api in the kernel as we did in Lab3
/*ADD CODE HERE*/;
match_times=0;
for (int i = 0; i < pattern_number; i++)
match_times += strlen(input) - patternsLength[i] +1 ;
int runtime_size = match_times*sizeof(int);
hipMalloc((void**)&d_runtime, runtime_size);
runtime = (int *) malloc(runtime_size);
memset(runtime, 0, runtime_size);
result = (int *) malloc((match_times)*sizeof(int));
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_number; i++)
{
int tmp=patternIndex[i];
patHashes[i] =0;
for (int j = 0; j < patternsLength[i]; j++)
{
//if(i==3) printf("xxx %c \n", patternLong[tmp+j]);
patHashes[i] = (patHashes[i] * 256 + patternLong[tmp+j]) % 997;
}
printf("patHash %d \n", patHashes[i]);
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
int size = input_length*sizeof(char);
err = hipMalloc((void**)&d_input, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input string from the host memory to the CUDA device\n");
err = hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
size = totalPatternLength*sizeof(char);
err = hipMalloc((void**)&d_pattern, size);
printf("Copy pattern string from the host memory to the CUDA device\n");
err = hipMemcpy(d_pattern, patternLong, size, hipMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_patHashes, size);
printf("Copy Hashes from the host memory to the CUDA device\n");
err = hipMemcpy(d_patHashes, patHashes, size, hipMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_patternsLength, size);
printf("Copy patternsLength from the host memory to the CUDA device\n");
err = hipMemcpy(d_patternsLength, patternsLength, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_result, size);
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocksPerGrid = 1;// FILL HERE
int threadsPerBlock = match_times;// FILL HERE
//printf("C--------=%d--------%s\n",match_times, "");
findIfExistsCu<<<blocksPerGrid, threadsPerBlock>>>(d_input, input_length, d_pattern, d_patternsLength, d_patHashes, d_result,d_runtime);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
// Copy the device result device memory to the host result matrix
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(result, d_result, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy result from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
hipMemcpy(runtime, d_runtime, runtime_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
/*RUN TIME calculation*//*ADD CODE HERE:*/
unsigned long long elapsed_time = 0;
for(int i = 0; i < match_times; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
//Print
printf("Kernel Execution Time: %llu cycles\n", elapsed_time);
printf("Total cycles: %d \n", elapsed_time);
printf("Kernel Execution Time: %d cycles\n", elapsed_time);
printf("Searching for multiple patterns in the input sequence\n");
printf("Input string: %s\n", input);
//Print Result[];
for(int i = 0; i < pattern_number; i++)
if(result[i]==1)
printf("Pattern: \"%s\" was found.\n", patterns[i]);
// Free device memory
hipFree(d_input);
hipFree(d_pattern);
hipFree(d_result);
hipFree(d_runtime);
hipFree(d_patHashes);
hipFree(d_patternsLength);
hipFree(d_patterns);
// Free host memory
free(result);
free(runtime);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
/* *
HW2 by Jiongfeng Chen
Parallelize the sequential version of Rabin-Karp String matching algorithm
on GPU: Searching for multiple patterns in the input sequence
Test Case:
input string:"Hello, 297 Class!"
pattern 1:"alxxl";
pattern 2:"llo";
pattern 3:", 297";
pattern 4:"97 Cl";
Output:
Kernel Execution Time: 5336 cycles
Total cycles: 5336
Kernel Execution Time: 5336 cycles
Searching for multiple patterns in the input sequence
Input string: Hello, 297 Class!
Pattern: "llo" was found.
Pattern: ", 297" was found.
Pattern: "97 Cl" was found.
run:nvcc -I/usr/local/cuda/include -I. -lineinfo -arch=sm_53 --ptxas-options=-v -g -c cmpe297_hw2_rabin_karp_multiPattern.cu -o cmpe297_hw2_rabin_karp_multiPattern.o
*/
#include<stdio.h>
#include<iostream>
#include <hip/hip_runtime.h>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__device__ int
memcpy(char* input, int index, char* pattern, int pattern_length)
{
for(int i = 0; i< pattern_length; i++)
if(pattern[i] != input[index+i])
return 1;
return 0;
}
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int* patternLength, int* patHashes, int* result, int *runtime)
{
int start_time = clock64();
int tid = threadIdx.x;
int inputHash = 0;
int searchSpaceIndex[4];
int patternIndex[4];
for(int i = 0; i< 4; i++)
result[i]=0;
for(int i = 0; i< 4; i++)
searchSpaceIndex[i]=0;
for (int i = 0; i < 4; i++)
if(i==0)
searchSpaceIndex[i] = input_length - patternLength[i] +1 ;
else
searchSpaceIndex[i] = searchSpaceIndex[i-1] + input_length - patternLength[i] +1 ;
//printf("C----tid-=%d--------%d-%d-%d-%d\n", tid,searchSpaceIndex[0],searchSpaceIndex[1] ,searchSpaceIndex[2] ,searchSpaceIndex[3] );
for(int i = 0; i < 4; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternLength[i-1];
int searchStart;
if(tid>=0 && tid <searchSpaceIndex[0])
{
searchStart =tid-searchSpaceIndex[0] +patternIndex[0];
for(int i = searchStart; i< searchStart +patternLength[0]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[0] && 1)
result[0]=1;
}
if(tid>=searchSpaceIndex[0] && tid <searchSpaceIndex[1])
{
searchStart =tid-searchSpaceIndex[1] +patternIndex[1];
for(int i = searchStart; i< searchStart +patternLength[1]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[1] && 1)
result[1]=1;
}
if(tid>=searchSpaceIndex[1] && tid <searchSpaceIndex[2])
{
searchStart =tid-searchSpaceIndex[2] +patternIndex[2];
for(int i = searchStart; i< searchStart +patternLength[2]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[2] && memcpy(&(input[searchStart]),0, pattern+patternIndex[2], patternLength[2])==0)
result[2]=1;
}
if(tid>=searchSpaceIndex[2] && tid <searchSpaceIndex[3])
{
searchStart =tid-searchSpaceIndex[3] +patternIndex[3];
for(int i = searchStart; i< searchStart +patternLength[3]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[3] && memcpy(&(input[searchStart]),0, pattern+patternIndex[3], patternLength[3])==0)
result[3]=1;
}
int stop_time = clock64();
runtime[tid] = (int)(stop_time - start_time);
}
int main()
{
// host variables
//char input[] = "HEABAL"; /*Sample Input*/
char input[] = "Hello, 297 Class!"; /*Multiple Patter Version: Input string*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int input_length = 17; /*Input Length*/
/*ADD CODE HERE*/;
int pattern_number = 4; /*Multiple Patter Version: Pattern Number*/
//int pattern_length = 2; /*Pattern Length*/
int match_times = 0; /*Match Times*/
hipError_t err = hipSuccess;
int * patternsLength;
int patHashes[4]; /*hash for the pattern*/
int patternFound[4]; /*Multiple Patter Version: Result Array*/
char* patterns[4]; /*Multiple Patter Version: Pattern String*/
patterns[0] ="alxxl";
patterns[1] ="llo";
patterns[2] =", 297";
patterns[3] ="97 Cl";
// device variables
char* d_input;
char* d_pattern;
int* d_result;
int* d_runtime;
int* d_patHashes;
int* d_patternsLength;
char* d_patterns;
//convert the string arrary to 1D string and pass to cuda fucntion
//1D string
char patternLong[100] = "";
int* patternIndex;
int p_size = 4*sizeof(int);
patternsLength = (int *) malloc(p_size);
memset(patternsLength, 0, p_size);
for(int i = 0; i < pattern_number; i++)
patternsLength[i] = strlen(patterns[i]);
patternIndex = (int *) malloc(pattern_number*sizeof(int));
for(int i = 0; i < pattern_number; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternsLength[i-1];
for(int i = 0; i < pattern_number; i++)
strcat(patternLong, patterns[i]);
printf("Pattern: \"%s\" ...\n", patternLong);
printf("Pattern: \"%s\"\n", patterns[0]);
for(int i = 0; i < pattern_number; i++)
printf("Pattern: \"%s\", lenth: %d.\n", patterns[i], patternsLength[i]);
int totalPatternLength=0;
for(int i = 0; i < pattern_number; i++)
totalPatternLength += patternsLength[i];
// measure the execution time by using clock() api in the kernel as we did in Lab3
/*ADD CODE HERE*/;
match_times=0;
for (int i = 0; i < pattern_number; i++)
match_times += strlen(input) - patternsLength[i] +1 ;
int runtime_size = match_times*sizeof(int);
hipMalloc((void**)&d_runtime, runtime_size);
runtime = (int *) malloc(runtime_size);
memset(runtime, 0, runtime_size);
result = (int *) malloc((match_times)*sizeof(int));
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_number; i++)
{
int tmp=patternIndex[i];
patHashes[i] =0;
for (int j = 0; j < patternsLength[i]; j++)
{
//if(i==3) printf("xxx %c \n", patternLong[tmp+j]);
patHashes[i] = (patHashes[i] * 256 + patternLong[tmp+j]) % 997;
}
printf("patHash %d \n", patHashes[i]);
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
int size = input_length*sizeof(char);
err = hipMalloc((void**)&d_input, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input string from the host memory to the CUDA device\n");
err = hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
size = totalPatternLength*sizeof(char);
err = hipMalloc((void**)&d_pattern, size);
printf("Copy pattern string from the host memory to the CUDA device\n");
err = hipMemcpy(d_pattern, patternLong, size, hipMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_patHashes, size);
printf("Copy Hashes from the host memory to the CUDA device\n");
err = hipMemcpy(d_patHashes, patHashes, size, hipMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_patternsLength, size);
printf("Copy patternsLength from the host memory to the CUDA device\n");
err = hipMemcpy(d_patternsLength, patternsLength, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_result, size);
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocksPerGrid = 1;// FILL HERE
int threadsPerBlock = match_times;// FILL HERE
//printf("C--------=%d--------%s\n",match_times, "");
findIfExistsCu<<<blocksPerGrid, threadsPerBlock>>>(d_input, input_length, d_pattern, d_patternsLength, d_patHashes, d_result,d_runtime);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
// Copy the device result device memory to the host result matrix
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(result, d_result, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy result from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
hipMemcpy(runtime, d_runtime, runtime_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
/*RUN TIME calculation*//*ADD CODE HERE:*/
unsigned long long elapsed_time = 0;
for(int i = 0; i < match_times; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
//Print
printf("Kernel Execution Time: %llu cycles\n", elapsed_time);
printf("Total cycles: %d \n", elapsed_time);
printf("Kernel Execution Time: %d cycles\n", elapsed_time);
printf("Searching for multiple patterns in the input sequence\n");
printf("Input string: %s\n", input);
//Print Result[];
for(int i = 0; i < pattern_number; i++)
if(result[i]==1)
printf("Pattern: \"%s\" was found.\n", patterns[i]);
// Free device memory
hipFree(d_input);
hipFree(d_pattern);
hipFree(d_result);
hipFree(d_runtime);
hipFree(d_patHashes);
hipFree(d_patternsLength);
hipFree(d_patterns);
// Free host memory
free(result);
free(runtime);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14findIfExistsCuPciS_PiS0_S0_S0_
.globl _Z14findIfExistsCuPciS_PiS0_S0_S0_
.p2align 8
.type _Z14findIfExistsCuPciS_PiS0_S0_S0_,@function
_Z14findIfExistsCuPciS_PiS0_S0_S0_:
s_load_b64 s[16:17], s[0:1], 0x28
v_mov_b32_e32 v1, 0
s_getreg_b32 s22, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b64 s[2:3], 0
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s16, s2
s_addc_u32 s5, s17, s3
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 16
global_store_b32 v1, v1, s[4:5]
s_cbranch_scc1 .LBB0_1
s_mov_b64 s[2:3], 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 3
s_cselect_b32 s7, s7, 0
s_cmp_lg_u32 s2, 2
s_cselect_b32 s6, s6, 0
s_cmp_lg_u32 s2, 1
s_cselect_b32 s5, s5, 0
s_cmp_lg_u32 s2, 0
s_cselect_b32 s4, s4, 0
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 4
s_cbranch_scc0 .LBB0_3
s_clause 0x1
s_load_b32 s14, s[0:1], 0x8
s_load_b64 s[18:19], s[0:1], 0x18
v_mov_b32_e32 v1, 0
s_mov_b64 s[2:3], 0
s_waitcnt lgkmcnt(0)
s_add_i32 s14, s14, 1
s_mov_b64 s[12:13], s[18:19]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_5:
s_cmp_lg_u32 s2, 0
s_mov_b32 s15, -1
s_cbranch_scc0 .LBB0_7
global_load_b32 v2, v1, s[12:13]
s_add_i32 s8, s2, -1
s_mov_b32 s15, 0
s_cmp_eq_u32 s8, 1
s_cselect_b32 s9, s5, s4
s_cmp_eq_u32 s8, 2
s_cselect_b32 s9, s6, s9
s_cmp_eq_u32 s8, 3
s_cselect_b32 s9, s7, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_i32 s9, s14, s9
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_sub_i32 s8, s9, s8
s_cmp_eq_u32 s2, 3
s_cselect_b32 s11, s8, s7
s_cmp_eq_u32 s2, 2
s_cselect_b32 s10, s8, s6
s_cmp_eq_u32 s2, 1
s_cselect_b32 s9, s8, s5
s_cmp_eq_u32 s2, 0
s_cselect_b32 s8, s8, s4
.LBB0_7:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_9
global_load_b32 v2, v1, s[18:19]
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v2
s_delay_alu instid0(VALU_DEP_1)
s_sub_i32 s4, s14, s4
s_mov_b64 s[10:11], s[6:7]
s_mov_b64 s[8:9], s[4:5]
.LBB0_9:
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_add_u32 s12, s12, 4
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s2, 4
s_cbranch_scc0 .LBB0_11
s_mov_b64 s[4:5], s[8:9]
s_mov_b64 s[6:7], s[10:11]
s_branch .LBB0_5
.LBB0_11:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v1, 0
s_add_u32 s2, s18, -4
s_addc_u32 s3, s19, -1
s_mov_b64 s[20:21], 0
s_mov_b32 s23, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_12:
s_cmp_lg_u32 s20, 0
s_mov_b32 s24, -1
s_cbranch_scc0 .LBB0_14
global_load_b32 v2, v1, s[2:3]
s_add_i32 s4, s20, -1
s_mov_b32 s24, 0
s_cmp_eq_u32 s4, 1
s_cselect_b32 s5, s13, s12
s_cmp_eq_u32 s4, 2
s_cselect_b32 s5, s14, s5
s_cmp_eq_u32 s4, 3
s_cselect_b32 s4, s15, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s6, v2
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s4, s6, s4
s_cmp_eq_u32 s20, 3
s_cselect_b32 s7, s4, s15
s_cmp_eq_u32 s20, 2
s_cselect_b32 s6, s4, s14
s_cmp_eq_u32 s20, 1
s_cselect_b32 s5, s4, s13
s_cmp_eq_u32 s20, 0
s_cselect_b32 s4, s4, s12
.LBB0_14:
s_and_not1_b32 vcc_lo, exec_lo, s24
s_cbranch_vccnz .LBB0_16
s_mov_b32 s12, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[4:5], s[12:13]
s_mov_b64 s[6:7], s[14:15]
.LBB0_16:
s_add_u32 s20, s20, 1
s_addc_u32 s21, s21, 0
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s20, 4
s_cbranch_scc0 .LBB0_18
s_mov_b64 s[14:15], s[6:7]
s_mov_b64 s[12:13], s[4:5]
s_branch .LBB0_12
.LBB0_18:
s_set_inst_prefetch_distance 0x2
s_clause 0x1
s_load_b64 s[12:13], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x20
v_cmp_le_i32_e64 s2, s8, v0
v_mov_b32_e32 v5, 0
s_mov_b32 s20, exec_lo
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v5, 0
global_load_b32 v1, v5, s[18:19]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB0_23
v_subrev_nc_u32_e32 v2, s8, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s4, v2
s_mov_b32 s4, 0
v_ashrrev_i32_e32 v2, 31, v3
v_add_nc_u32_e32 v4, v1, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
.p2align 6
.LBB0_21:
global_load_i8 v6, v[1:2], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s3, v3, v4
s_or_b32 s4, s3, s4
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v6, v5, 0x837765f1
v_add_nc_u32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 9, v6
v_add_nc_u32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v6, 0x3e5, v6
v_sub_nc_u32_e32 v5, v5, v6
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_21
s_or_b32 exec_lo, exec_lo, s4
.LBB0_23:
v_mov_b32_e32 v1, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[14:15]
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v5, v2
s_cbranch_execz .LBB0_25
v_mov_b32_e32 v2, 1
global_store_b32 v1, v2, s[16:17]
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_36
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_35
v_mov_b32_e32 v1, 0
global_load_b32 v1, v1, s[18:19] offset:4
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB0_32
v_subrev_nc_u32_e32 v2, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s5, v2
s_mov_b32 s5, 0
v_ashrrev_i32_e32 v2, 31, v3
v_add_nc_u32_e32 v4, v1, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
.p2align 6
.LBB0_30:
global_load_i8 v6, v[1:2], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v3, v4
s_or_b32 s5, s2, s5
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v6, v5, 0x837765f1
v_add_nc_u32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 9, v6
v_add_nc_u32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v6, 0x3e5, v6
v_sub_nc_u32_e32 v5, v5, v6
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_30
s_or_b32 exec_lo, exec_lo, s5
.LBB0_32:
v_mov_b32_e32 v1, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[14:15] offset:4
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v5, v2
s_cbranch_execz .LBB0_34
v_mov_b32_e32 v2, 1
global_store_b32 v1, v2, s[16:17] offset:4
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_35:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_36:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s23, exec_lo
v_cmpx_le_i32_e64 s9, v0
s_cbranch_execz .LBB0_56
s_mov_b32 s24, exec_lo
v_cmpx_gt_i32_e64 s10, v0
s_cbranch_execz .LBB0_55
v_mov_b32_e32 v1, 0
v_subrev_nc_u32_e32 v2, s10, v0
global_load_b32 v1, v1, s[18:19] offset:8
v_add_nc_u32_e32 v3, s6, v2
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
v_readfirstlane_b32 s25, v1
s_cbranch_vccnz .LBB0_42
v_ashrrev_i32_e32 v2, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s12, v3
v_add_nc_u32_e32 v4, s25, v3
v_mov_b32_e32 v6, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
s_mov_b32 s3, 0
.p2align 6
.LBB0_40:
global_load_i8 v7, v[1:2], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v6, v4
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v7, v5, 0x837765f1
v_add_nc_u32_e32 v7, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 9, v7
v_add_nc_u32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v7, 0x3e5, v7
v_sub_nc_u32_e32 v5, v5, v7
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_40
s_or_b32 exec_lo, exec_lo, s3
.LBB0_42:
v_mov_b32_e32 v1, 0
s_mov_b32 s26, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[14:15] offset:8
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v5, v1
s_cbranch_execz .LBB0_54
s_cmp_gt_i32 s25, 0
s_cselect_b32 s27, -1, 0
s_cmp_lt_i32 s25, 1
s_cbranch_scc1 .LBB0_52
v_ashrrev_i32_e32 v2, 31, v3
v_add_co_u32 v1, vcc_lo, s12, v3
v_mov_b32_e32 v6, 0
s_ashr_i32 s3, s6, 31
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
s_add_u32 s2, s4, s6
s_addc_u32 s3, s5, s3
global_load_u8 v3, v6, s[2:3]
global_load_u8 v4, v[1:2], off
s_mov_b32 s6, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e64 v3, v4
s_cbranch_execz .LBB0_51
s_mov_b32 s28, 0
s_mov_b64 s[8:9], 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_48
.p2align 6
.LBB0_46:
v_add_co_u32 v3, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
s_add_u32 s20, s2, s8
s_addc_u32 s21, s3, s9
global_load_u8 v7, v6, s[20:21]
global_load_u8 v3, v[3:4], off
s_add_u32 s20, s8, 1
s_addc_u32 s21, s9, 0
s_and_not1_b32 s29, s29, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v7, v3
s_and_b32 s30, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s29, s29, s30
.LBB0_47:
v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9
s_and_b32 s30, exec_lo, s29
s_mov_b64 s[8:9], s[20:21]
s_or_b32 s28, s30, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execz .LBB0_50
.LBB0_48:
s_or_b32 s29, s29, exec_lo
s_cmp_eq_u32 s25, s8
s_cbranch_scc0 .LBB0_46
s_branch .LBB0_47
.LBB0_50:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s28
v_cmp_gt_i32_e32 vcc_lo, s25, v3
s_and_not1_b32 s2, s27, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s27, s2, s3
.LBB0_51:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_52:
s_xor_b32 s2, s27, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_54
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1
global_store_b32 v1, v2, s[16:17] offset:8
.LBB0_54:
s_or_b32 exec_lo, exec_lo, s26
.LBB0_55:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s24
.LBB0_56:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s23
s_mov_b32 s8, exec_lo
v_cmpx_le_i32_e64 s10, v0
s_cbranch_execz .LBB0_74
v_cmp_gt_i32_e32 vcc_lo, s11, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_74
v_mov_b32_e32 v1, 0
v_subrev_nc_u32_e32 v2, s11, v0
global_load_b32 v1, v1, s[18:19] offset:12
v_add_nc_u32_e32 v3, s7, v2
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v1
v_readfirstlane_b32 s9, v1
s_cbranch_vccnz .LBB0_62
v_ashrrev_i32_e32 v2, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s12, v3
v_add_nc_u32_e32 v4, s9, v3
v_mov_b32_e32 v6, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
s_mov_b32 s3, 0
.p2align 6
.LBB0_60:
global_load_i8 v7, v[1:2], off
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v6, v4
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v7, v5, 0x837765f1
v_add_nc_u32_e32 v7, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 31, v7
v_ashrrev_i32_e32 v7, 9, v7
v_add_nc_u32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v7, 0x3e5, v7
v_sub_nc_u32_e32 v5, v5, v7
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_60
s_or_b32 exec_lo, exec_lo, s3
.LBB0_62:
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[14:15] offset:12
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_74
s_cmp_gt_i32 s9, 0
s_cselect_b32 s10, -1, 0
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_72
v_ashrrev_i32_e32 v2, 31, v3
v_add_co_u32 v1, vcc_lo, s12, v3
v_mov_b32_e32 v5, 0
s_ashr_i32 s3, s7, 31
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
s_add_u32 s2, s4, s7
s_addc_u32 s3, s5, s3
global_load_u8 v3, v5, s[2:3]
global_load_u8 v4, v[1:2], off
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e64 v3, v4
s_cbranch_execz .LBB0_71
s_mov_b32 s12, 0
s_mov_b64 s[4:5], 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_68
.p2align 6
.LBB0_66:
v_add_co_u32 v3, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_add_u32 s6, s2, s4
s_addc_u32 s7, s3, s5
global_load_u8 v6, v5, s[6:7]
global_load_u8 v3, v[3:4], off
s_add_u32 s6, s4, 1
s_addc_u32 s7, s5, 0
s_and_not1_b32 s13, s13, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v6, v3
s_and_b32 s14, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s14
.LBB0_67:
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
s_and_b32 s14, exec_lo, s13
s_mov_b64 s[4:5], s[6:7]
s_or_b32 s12, s14, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_70
.LBB0_68:
s_or_b32 s13, s13, exec_lo
s_cmp_eq_u32 s9, s4
s_cbranch_scc0 .LBB0_66
s_branch .LBB0_67
.LBB0_70:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s12
v_cmp_gt_i32_e32 vcc_lo, s9, v3
s_and_not1_b32 s2, s10, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s10, s2, s3
.LBB0_71:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_72:
s_xor_b32 s2, s10, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_74
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1
global_store_b32 v1, v2, s[16:17] offset:12
.LBB0_74:
s_or_b32 exec_lo, exec_lo, s8
s_load_b64 s[0:1], s[0:1], 0x30
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s2, s2, s22
v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14findIfExistsCuPciS_PiS0_S0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14findIfExistsCuPciS_PiS0_S0_S0_, .Lfunc_end0-_Z14findIfExistsCuPciS_PiS0_S0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14findIfExistsCuPciS_PiS0_S0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z14findIfExistsCuPciS_PiS0_S0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // CMPE297-6 HW2
// CUDA version Rabin-Karp
/* *
HW2 by Jiongfeng Chen
Parallelize the sequential version of Rabin-Karp String matching algorithm
on GPU: Searching for multiple patterns in the input sequence
Test Case:
input string:"Hello, 297 Class!"
pattern 1:"alxxl";
pattern 2:"llo";
pattern 3:", 297";
pattern 4:"97 Cl";
Output:
Kernel Execution Time: 5336 cycles
Total cycles: 5336
Kernel Execution Time: 5336 cycles
Searching for multiple patterns in the input sequence
Input string: Hello, 297 Class!
Pattern: "llo" was found.
Pattern: ", 297" was found.
Pattern: "97 Cl" was found.
run:nvcc -I/usr/local/cuda/include -I. -lineinfo -arch=sm_53 --ptxas-options=-v -g -c cmpe297_hw2_rabin_karp_multiPattern.cu -o cmpe297_hw2_rabin_karp_multiPattern.o
*/
#include<stdio.h>
#include<iostream>
#include <hip/hip_runtime.h>
/*ADD CODE HERE: Implement the parallel version of the sequential Rabin-Karp*/
__device__ int
memcpy(char* input, int index, char* pattern, int pattern_length)
{
for(int i = 0; i< pattern_length; i++)
if(pattern[i] != input[index+i])
return 1;
return 0;
}
__global__ void
findIfExistsCu(char* input, int input_length, char* pattern, int* patternLength, int* patHashes, int* result, int *runtime)
{
int start_time = clock64();
int tid = threadIdx.x;
int inputHash = 0;
int searchSpaceIndex[4];
int patternIndex[4];
for(int i = 0; i< 4; i++)
result[i]=0;
for(int i = 0; i< 4; i++)
searchSpaceIndex[i]=0;
for (int i = 0; i < 4; i++)
if(i==0)
searchSpaceIndex[i] = input_length - patternLength[i] +1 ;
else
searchSpaceIndex[i] = searchSpaceIndex[i-1] + input_length - patternLength[i] +1 ;
//printf("C----tid-=%d--------%d-%d-%d-%d\n", tid,searchSpaceIndex[0],searchSpaceIndex[1] ,searchSpaceIndex[2] ,searchSpaceIndex[3] );
for(int i = 0; i < 4; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternLength[i-1];
int searchStart;
if(tid>=0 && tid <searchSpaceIndex[0])
{
searchStart =tid-searchSpaceIndex[0] +patternIndex[0];
for(int i = searchStart; i< searchStart +patternLength[0]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[0] && 1)
result[0]=1;
}
if(tid>=searchSpaceIndex[0] && tid <searchSpaceIndex[1])
{
searchStart =tid-searchSpaceIndex[1] +patternIndex[1];
for(int i = searchStart; i< searchStart +patternLength[1]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[1] && 1)
result[1]=1;
}
if(tid>=searchSpaceIndex[1] && tid <searchSpaceIndex[2])
{
searchStart =tid-searchSpaceIndex[2] +patternIndex[2];
for(int i = searchStart; i< searchStart +patternLength[2]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[2] && memcpy(&(input[searchStart]),0, pattern+patternIndex[2], patternLength[2])==0)
result[2]=1;
}
if(tid>=searchSpaceIndex[2] && tid <searchSpaceIndex[3])
{
searchStart =tid-searchSpaceIndex[3] +patternIndex[3];
for(int i = searchStart; i< searchStart +patternLength[3]; i++)
inputHash = (inputHash*256 + input[i]) % 997;
if(inputHash == patHashes[3] && memcpy(&(input[searchStart]),0, pattern+patternIndex[3], patternLength[3])==0)
result[3]=1;
}
int stop_time = clock64();
runtime[tid] = (int)(stop_time - start_time);
}
int main()
{
// host variables
//char input[] = "HEABAL"; /*Sample Input*/
char input[] = "Hello, 297 Class!"; /*Multiple Patter Version: Input string*/
char pattern[] = "AB"; /*Sample Pattern*/
int patHash = 0; /*hash for the pattern*/
int* result; /*Result array*/
int* runtime; /*Exection cycles*/
int input_length = 17; /*Input Length*/
/*ADD CODE HERE*/;
int pattern_number = 4; /*Multiple Patter Version: Pattern Number*/
//int pattern_length = 2; /*Pattern Length*/
int match_times = 0; /*Match Times*/
hipError_t err = hipSuccess;
int * patternsLength;
int patHashes[4]; /*hash for the pattern*/
int patternFound[4]; /*Multiple Patter Version: Result Array*/
char* patterns[4]; /*Multiple Patter Version: Pattern String*/
patterns[0] ="alxxl";
patterns[1] ="llo";
patterns[2] =", 297";
patterns[3] ="97 Cl";
// device variables
char* d_input;
char* d_pattern;
int* d_result;
int* d_runtime;
int* d_patHashes;
int* d_patternsLength;
char* d_patterns;
//convert the string arrary to 1D string and pass to cuda fucntion
//1D string
char patternLong[100] = "";
int* patternIndex;
int p_size = 4*sizeof(int);
patternsLength = (int *) malloc(p_size);
memset(patternsLength, 0, p_size);
for(int i = 0; i < pattern_number; i++)
patternsLength[i] = strlen(patterns[i]);
patternIndex = (int *) malloc(pattern_number*sizeof(int));
for(int i = 0; i < pattern_number; i++)
if(i == 0)
patternIndex[i] = 0;
else
patternIndex[i] = patternIndex[i-1] + patternsLength[i-1];
for(int i = 0; i < pattern_number; i++)
strcat(patternLong, patterns[i]);
printf("Pattern: \"%s\" ...\n", patternLong);
printf("Pattern: \"%s\"\n", patterns[0]);
for(int i = 0; i < pattern_number; i++)
printf("Pattern: \"%s\", lenth: %d.\n", patterns[i], patternsLength[i]);
int totalPatternLength=0;
for(int i = 0; i < pattern_number; i++)
totalPatternLength += patternsLength[i];
// measure the execution time by using clock() api in the kernel as we did in Lab3
/*ADD CODE HERE*/;
match_times=0;
for (int i = 0; i < pattern_number; i++)
match_times += strlen(input) - patternsLength[i] +1 ;
int runtime_size = match_times*sizeof(int);
hipMalloc((void**)&d_runtime, runtime_size);
runtime = (int *) malloc(runtime_size);
memset(runtime, 0, runtime_size);
result = (int *) malloc((match_times)*sizeof(int));
/*Calculate the hash of the pattern*/
for (int i = 0; i < pattern_number; i++)
{
int tmp=patternIndex[i];
patHashes[i] =0;
for (int j = 0; j < patternsLength[i]; j++)
{
//if(i==3) printf("xxx %c \n", patternLong[tmp+j]);
patHashes[i] = (patHashes[i] * 256 + patternLong[tmp+j]) % 997;
}
printf("patHash %d \n", patHashes[i]);
}
/*ADD CODE HERE: Allocate memory on the GPU and copy or set the appropriate values from the HOST*/
int size = input_length*sizeof(char);
err = hipMalloc((void**)&d_input, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Copy input string from the host memory to the CUDA device\n");
err = hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
size = totalPatternLength*sizeof(char);
err = hipMalloc((void**)&d_pattern, size);
printf("Copy pattern string from the host memory to the CUDA device\n");
err = hipMemcpy(d_pattern, patternLong, size, hipMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_patHashes, size);
printf("Copy Hashes from the host memory to the CUDA device\n");
err = hipMemcpy(d_patHashes, patHashes, size, hipMemcpyHostToDevice);
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_patternsLength, size);
printf("Copy patternsLength from the host memory to the CUDA device\n");
err = hipMemcpy(d_patternsLength, patternsLength, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device d_input(error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
size = pattern_number*sizeof(int);
err = hipMalloc((void**)&d_result, size);
/*ADD CODE HERE: Launch the kernel and pass the arguments*/
int blocksPerGrid = 1;// FILL HERE
int threadsPerBlock = match_times;// FILL HERE
//printf("C--------=%d--------%s\n",match_times, "");
findIfExistsCu<<<blocksPerGrid, threadsPerBlock>>>(d_input, input_length, d_pattern, d_patternsLength, d_patHashes, d_result,d_runtime);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: COPY the result and print the result as in the HW description*/
// Copy the device result device memory to the host result matrix
// in host memory.
printf("Copy output data from the CUDA device to the host memory\n");
err = hipMemcpy(result, d_result, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy result from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
/*ADD CODE HERE: Copy the execution times from the GPU memory to HOST Code*/
hipMemcpy(runtime, d_runtime, runtime_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
/*RUN TIME calculation*//*ADD CODE HERE:*/
unsigned long long elapsed_time = 0;
for(int i = 0; i < match_times; i++)
if(elapsed_time < runtime[i])
elapsed_time = runtime[i];
//Print
printf("Kernel Execution Time: %llu cycles\n", elapsed_time);
printf("Total cycles: %d \n", elapsed_time);
printf("Kernel Execution Time: %d cycles\n", elapsed_time);
printf("Searching for multiple patterns in the input sequence\n");
printf("Input string: %s\n", input);
//Print Result[];
for(int i = 0; i < pattern_number; i++)
if(result[i]==1)
printf("Pattern: \"%s\" was found.\n", patterns[i]);
// Free device memory
hipFree(d_input);
hipFree(d_pattern);
hipFree(d_result);
hipFree(d_runtime);
hipFree(d_patHashes);
hipFree(d_patternsLength);
hipFree(d_patterns);
// Free host memory
free(result);
free(runtime);
return 0;
} | .text
.file "cmpe297_hw2_rabin_karp_multiPattern.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_ # -- Begin function _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.p2align 4, 0x90
.type _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_,@function
_Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_: # @_Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14findIfExistsCuPciS_PiS0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_, .Lfunc_end0-_Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.byte 72 # 0x48
.byte 101 # 0x65
.byte 108 # 0x6c
.byte 108 # 0x6c
.byte 111 # 0x6f
.byte 44 # 0x2c
.byte 32 # 0x20
.byte 50 # 0x32
.byte 57 # 0x39
.byte 55 # 0x37
.byte 32 # 0x20
.byte 67 # 0x43
.byte 108 # 0x6c
.byte 97 # 0x61
.byte 115 # 0x73
.byte 115 # 0x73
.LCPI1_1:
.zero 16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [72,101,108,108,111,44,32,50,57,55,32,67,108,97,115,115]
movaps %xmm0, 80(%rsp)
movw $33, 96(%rsp)
movq $.L.str, 112(%rsp)
movq $.L.str.1, 120(%rsp)
movq $.L.str.2, 128(%rsp)
movq $.L.str.3, 136(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 400(%rsp)
movaps %xmm0, 384(%rsp)
movaps %xmm0, 368(%rsp)
movaps %xmm0, 352(%rsp)
movaps %xmm0, 336(%rsp)
movaps %xmm0, 320(%rsp)
movl $0, 416(%rsp)
movl $16, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rdi
callq strlen
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq $4, %rbx
jne .LBB1_1
# %bb.2:
movl $16, %edi
callq malloc
movq %rax, %r13
xorl %eax, %eax
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movl -4(%r15,%rax,4), %ecx
addl -4(%r13,%rax,4), %ecx
movl %ecx, (%r13,%rax,4)
.LBB1_6: # in Loop: Header=BB1_3 Depth=1
incq %rax
cmpq $4, %rax
je .LBB1_7
.LBB1_3: # =>This Inner Loop Header: Depth=1
testq %rax, %rax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $0, (%r13)
jmp .LBB1_6
.LBB1_7: # %.preheader149.preheader
xorl %r14d, %r14d
leaq 320(%rsp), %rbx
.p2align 4, 0x90
.LBB1_8: # %.preheader149
# =>This Inner Loop Header: Depth=1
movq 112(%rsp,%r14,8), %rsi
movq %rbx, %rdi
callq strcat
incq %r14
cmpq $4, %r14
jne .LBB1_8
# %bb.9:
leaq 320(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $.L.str, %esi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rsi
movl (%r15,%rbx,4), %edx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_10
# %bb.11: # %.preheader148.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_12: # %.preheader148
# =>This Inner Loop Header: Depth=1
movslq (%r15,%rax,4), %rcx
movslq %ebp, %rbp
addq %rcx, %rbp
incq %rax
cmpq $4, %rax
jne .LBB1_12
# %bb.13: # %.preheader
leaq 80(%rsp), %rdi
callq strlen
xorl %ecx, %ecx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
subl (%r15,%rcx,4), %r12d
addl %eax, %r12d
incl %r12d
incq %rcx
cmpq $4, %rcx
jne .LBB1_14
# %bb.15:
movslq %r12d, %rbx
leaq (,%rbx,4), %r14
shlq $34, %rbx
sarq $32, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
movq %r14, %rdi
callq malloc
movq %rax, %r14
xorl %ebx, %ebx
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_16 Depth=1
movl 64(%rsp,%rbx,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
je .LBB1_21
.LBB1_16: # =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movslq (%r13,%rbx,4), %rdx
movl $0, 64(%rsp,%rbx,4)
movl (%r15,%rbx,4), %eax
testl %eax, %eax
jle .LBB1_20
# %bb.17: # %.lr.ph
# in Loop: Header=BB1_16 Depth=1
movl 64(%rsp,%rbx,4), %ecx
addq %rsp, %rdx
addq $320, %rdx # imm = 0x140
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
shll $8, %ecx
movsbl (%rdx,%rsi), %edi
addl %ecx, %edi
movslq %edi, %rcx
imulq $-2089327119, %rcx, %rdi # imm = 0x837765F1
shrq $32, %rdi
addl %ecx, %edi
movl %edi, %r8d
shrl $31, %r8d
sarl $9, %edi
addl %r8d, %edi
imull $997, %edi, %edi # imm = 0x3E5
subl %edi, %ecx
incq %rsi
cmpq %rsi, %rax
jne .LBB1_18
# %bb.19: # %._crit_edge
# in Loop: Header=BB1_16 Depth=1
movl %ecx, 64(%rsp,%rbx,4)
jmp .LBB1_20
.LBB1_21:
leaq 48(%rsp), %rdi
movl $17, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_22
# %bb.24:
movl $.Lstr, %edi
callq puts@PLT
movq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $17, %edx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movl $.Lstr.1, %edi
callq puts@PLT
movq 40(%rsp), %rdi
leaq 320(%rsp), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movl $.Lstr.2, %edi
callq puts@PLT
movq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $16, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.25:
leaq 32(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movl %r12d, %r13d
movabsq $4294967296, %rdi # imm = 0x100000000
leaq (%rdi,%r13), %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB1_27
# %bb.26:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
movq 24(%rsp), %r8
movq %rax, 248(%rsp)
movl $17, 60(%rsp)
movq %rcx, 240(%rsp)
movq %rdx, 232(%rsp)
movq %rsi, 224(%rsp)
movq %rdi, 216(%rsp)
movq %r8, 208(%rsp)
leaq 248(%rsp), %rax
movq %rax, 256(%rsp)
leaq 60(%rsp), %rax
movq %rax, 264(%rsp)
leaq 240(%rsp), %rax
movq %rax, 272(%rsp)
leaq 232(%rsp), %rax
movq %rax, 280(%rsp)
leaq 224(%rsp), %rax
movq %rax, 288(%rsp)
leaq 216(%rsp), %rax
movq %rax, 296(%rsp)
leaq 208(%rsp), %rax
movq %rax, 304(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z14findIfExistsCuPciS_PiS0_S0_S0_, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_27:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_28
# %bb.29:
callq hipDeviceSynchronize
movl $.Lstr.4, %edi
callq puts@PLT
movq 32(%rsp), %rsi
movl $16, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_30
# %bb.31:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %rbp, %rdi
movq 144(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
testl %r12d, %r12d
jle .LBB1_32
# %bb.38: # %.lr.ph163.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_39: # %.lr.ph163
# =>This Inner Loop Header: Depth=1
movslq (%rbp,%rax,4), %r15
cmpq %r15, %rcx
cmovaq %rcx, %r15
incq %rax
movq %r15, %rcx
cmpq %rax, %r13
jne .LBB1_39
jmp .LBB1_33
.LBB1_32:
xorl %r15d, %r15d
.LBB1_33: # %._crit_edge164
movl $.L.str.16, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.17, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.18, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
leaq 80(%rsp), %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_36: # in Loop: Header=BB1_34 Depth=1
incq %rbx
cmpq $4, %rbx
je .LBB1_37
.LBB1_34: # =>This Inner Loop Header: Depth=1
cmpl $1, (%r14,%rbx,4)
jne .LBB1_36
# %bb.35: # in Loop: Header=BB1_34 Depth=1
movq 112(%rsp,%rbx,8), %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_36
.LBB1_37:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipFree
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 480
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_23
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB1_23
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
.LBB1_23:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14findIfExistsCuPciS_PiS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14findIfExistsCuPciS_PiS0_S0_S0_,@object # @_Z14findIfExistsCuPciS_PiS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z14findIfExistsCuPciS_PiS0_S0_S0_
.p2align 3, 0x0
_Z14findIfExistsCuPciS_PiS0_S0_S0_:
.quad _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.size _Z14findIfExistsCuPciS_PiS0_S0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "alxxl"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "llo"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", 297"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "97 Cl"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Pattern: \"%s\" ...\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Pattern: \"%s\"\n"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Pattern: \"%s\", lenth: %d.\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "patHash %d \n"
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device d_input(error code %s)!\n"
.size .L.str.8, 51
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.13, 42
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed to copy result from device to host (error code %s)!\n"
.size .L.str.15, 60
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Kernel Execution Time: %llu cycles\n"
.size .L.str.16, 36
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Total cycles: %d \n"
.size .L.str.17, 19
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel Execution Time: %d cycles\n"
.size .L.str.18, 34
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Input string: %s\n"
.size .L.str.20, 18
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Pattern: \"%s\" was found.\n"
.size .L.str.21, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14findIfExistsCuPciS_PiS0_S0_S0_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copy input string from the host memory to the CUDA device"
.size .Lstr, 58
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copy pattern string from the host memory to the CUDA device"
.size .Lstr.1, 60
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copy Hashes from the host memory to the CUDA device"
.size .Lstr.2, 52
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Copy patternsLength from the host memory to the CUDA device"
.size .Lstr.3, 60
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Copy output data from the CUDA device to the host memory"
.size .Lstr.4, 57
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Searching for multiple patterns in the input sequence"
.size .Lstr.5, 54
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14findIfExistsCuPciS_PiS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a5b74_00000000-6_cmpe297_hw2_rabin_karp_multiPattern.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6memcpyPciS_i
.type _Z6memcpyPciS_i, @function
_Z6memcpyPciS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z6memcpyPciS_i, .-_Z6memcpyPciS_i
.globl _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
.type _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_, @function
_Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 216
pushq 72(%rsp)
.cfi_def_cfa_offset 224
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14findIfExistsCuPciS_PiS0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_, .-_Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
.globl _Z14findIfExistsCuPciS_PiS0_S0_S0_
.type _Z14findIfExistsCuPciS_PiS0_S0_S0_, @function
_Z14findIfExistsCuPciS_PiS0_S0_S0_:
.LFB3696:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z14findIfExistsCuPciS_PiS0_S0_S0_, .-_Z14findIfExistsCuPciS_PiS0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "alxxl"
.LC1:
.string "llo"
.LC2:
.string ", 297"
.LC3:
.string "97 Cl"
.LC4:
.string "Pattern: \"%s\" ...\n"
.LC5:
.string "Pattern: \"%s\"\n"
.LC6:
.string "Pattern: \"%s\", lenth: %d.\n"
.LC7:
.string "patHash %d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Failed to allocate device d_input(error code %s)!\n"
.align 8
.LC9:
.string "Copy input string from the host memory to the CUDA device\n"
.align 8
.LC10:
.string "Copy pattern string from the host memory to the CUDA device\n"
.align 8
.LC11:
.string "Copy Hashes from the host memory to the CUDA device\n"
.align 8
.LC12:
.string "Copy patternsLength from the host memory to the CUDA device\n"
.align 8
.LC13:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC14:
.string "Copy output data from the CUDA device to the host memory\n"
.align 8
.LC15:
.string "Failed to copy result from device to host (error code %s)!\n"
.align 8
.LC16:
.string "Kernel Execution Time: %llu cycles\n"
.section .rodata.str1.1
.LC17:
.string "Total cycles: %d \n"
.section .rodata.str1.8
.align 8
.LC18:
.string "Kernel Execution Time: %d cycles\n"
.align 8
.LC19:
.string "Searching for multiple patterns in the input sequence\n"
.section .rodata.str1.1
.LC20:
.string "Input string: %s\n"
.LC21:
.string "Pattern: \"%s\" was found.\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $312, %rsp
.cfi_def_cfa_offset 368
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
movabsq $3611935758223172936, %rax
movabsq $8319100054293985081, %rdx
movq %rax, 160(%rsp)
movq %rdx, 168(%rsp)
movw $33, 176(%rsp)
leaq .LC0(%rip), %rax
movq %rax, 128(%rsp)
leaq .LC1(%rip), %rax
movq %rax, 136(%rsp)
leaq .LC2(%rip), %rax
movq %rax, 144(%rsp)
leaq .LC3(%rip), %rax
movq %rax, 152(%rsp)
movq $0, 192(%rsp)
movq $0, 200(%rsp)
movq $0, 208(%rsp)
movq $0, 216(%rsp)
movq $0, 224(%rsp)
movq $0, 232(%rsp)
movq $0, 240(%rsp)
movq $0, 248(%rsp)
movq $0, 256(%rsp)
movq $0, 264(%rsp)
movq $0, 272(%rsp)
movq $0, 280(%rsp)
movl $0, 288(%rsp)
movl $16, %edi
call malloc@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
movups %xmm0, (%rax)
movl $0, %ebp
.L14:
movq 128(%rsp,%rbp,8), %rdi
call strlen@PLT
movl %eax, (%rbx,%rbp,4)
addq $1, %rbp
cmpq $4, %rbp
jne .L14
movl $16, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
jmp .L18
.L45:
movl $0, (%r14)
addq $1, %rax
.L18:
testl %eax, %eax
je .L45
movl -4(%rbx,%rax,4), %edx
addl -4(%r14,%rax,4), %edx
movl %edx, (%r14,%rax,4)
addq $1, %rax
cmpq $4, %rax
jne .L18
leaq 128(%rsp), %rbp
leaq 160(%rsp), %r13
leaq 192(%rsp), %r12
.L19:
movq 0(%rbp), %rsi
movl $100, %edx
movq %r12, %rdi
call __strcat_chk@PLT
addq $8, %rbp
cmpq %r13, %rbp
jne .L19
leaq 192(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC0(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC6(%rip), %r12
.L20:
movl (%rbx,%rbp,4), %ecx
movq 128(%rsp,%rbp,8), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq $4, %rbp
jne .L20
movl 4(%rbx), %eax
addl (%rbx), %eax
addl 8(%rbx), %eax
addl 12(%rbx), %eax
movl %eax, 28(%rsp)
leaq 160(%rsp), %rdi
call strlen@PLT
movq %rbx, %rdx
leaq 16(%rbx), %rsi
movl $0, %ecx
addl $1, %eax
.L21:
movl %eax, %r12d
subl (%rdx), %r12d
addl %ecx, %r12d
movl %r12d, %ecx
addq $4, %rdx
cmpq %rsi, %rdx
jne .L21
movslq %r12d, %rbp
leal 0(,%r12,4), %eax
movslq %eax, %r15
movq %r15, 8(%rsp)
leaq 64(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq %r15, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %r15, %rcx
movq %r15, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq 0(,%rbp,4), %rax
movq %rax, 16(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r15
leaq 112(%rsp), %r13
movl $0, %ebp
.L24:
movl (%r14,%rbp), %eax
movq %r13, %rdi
movl $0, 0(%r13)
movl (%rbx,%rbp), %esi
testl %esi, %esi
jle .L22
cltq
leaq 192(%rsp), %rdx
leaq (%rdx,%rax), %rcx
movslq %esi, %rsi
addq %rax, %rsi
addq %rdx, %rsi
movl $0, %eax
.L23:
sall $8, %eax
movsbl (%rcx), %edx
addl %eax, %edx
movslq %edx, %rax
imulq $-2089327119, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $9, %eax
movl %edx, %r8d
sarl $31, %r8d
subl %r8d, %eax
imull $997, %eax, %r8d
movl %edx, %eax
subl %r8d, %eax
addq $1, %rcx
cmpq %rsi, %rcx
jne .L23
movl %eax, (%rdi)
.L22:
movl (%rdi), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %r13
addq $4, %rbp
cmpq $16, %rbp
jne .L24
leaq 40(%rsp), %rdi
movl $17, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 160(%rsp), %rsi
movl $1, %ecx
movl $17, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movslq 28(%rsp), %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 192(%rsp), %rsi
movl $1, %ecx
movq %rbp, %rdx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 72(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $16, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
leaq 56(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl %r12d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L27:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L49
call cudaThreadSynchronize@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $16, %edx
movq 56(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L50
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 64(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
testl %r12d, %r12d
jle .L35
movq %rbx, %rax
movq 16(%rsp), %rcx
addq %rbx, %rcx
movl $0, %ebx
.L31:
movslq (%rax), %rdx
cmpq %rdx, %rbx
cmovb %rdx, %rbx
addq $4, %rax
cmpq %rax, %rcx
jne .L31
.L30:
movq %rbx, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 160(%rsp), %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L33
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
subq $8, %rsp
.cfi_def_cfa_offset 376
pushq 72(%rsp)
.cfi_def_cfa_offset 384
movq 72(%rsp), %r9
movq 88(%rsp), %r8
movq 96(%rsp), %rcx
movq 64(%rsp), %rdx
movl $17, %esi
movq 56(%rsp), %rdi
call _Z48__device_stub__Z14findIfExistsCuPciS_PiS0_S0_S0_PciS_PiS0_S0_S0_
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L27
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl $0, %ebx
jmp .L30
.L32:
addq $1, %rbx
cmpq $4, %rbx
je .L51
.L33:
cmpl $1, (%r15,%rbx,4)
jne .L32
movq 128(%rsp,%rbx,8), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L51:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC22:
.string "_Z14findIfExistsCuPciS_PiS0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z14findIfExistsCuPciS_PiS0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cmpe297_hw2_rabin_karp_multiPattern.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_ # -- Begin function _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.p2align 4, 0x90
.type _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_,@function
_Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_: # @_Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14findIfExistsCuPciS_PiS0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_, .Lfunc_end0-_Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.byte 72 # 0x48
.byte 101 # 0x65
.byte 108 # 0x6c
.byte 108 # 0x6c
.byte 111 # 0x6f
.byte 44 # 0x2c
.byte 32 # 0x20
.byte 50 # 0x32
.byte 57 # 0x39
.byte 55 # 0x37
.byte 32 # 0x20
.byte 67 # 0x43
.byte 108 # 0x6c
.byte 97 # 0x61
.byte 115 # 0x73
.byte 115 # 0x73
.LCPI1_1:
.zero 16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 480
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [72,101,108,108,111,44,32,50,57,55,32,67,108,97,115,115]
movaps %xmm0, 80(%rsp)
movw $33, 96(%rsp)
movq $.L.str, 112(%rsp)
movq $.L.str.1, 120(%rsp)
movq $.L.str.2, 128(%rsp)
movq $.L.str.3, 136(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 400(%rsp)
movaps %xmm0, 384(%rsp)
movaps %xmm0, 368(%rsp)
movaps %xmm0, 352(%rsp)
movaps %xmm0, 336(%rsp)
movaps %xmm0, 320(%rsp)
movl $0, 416(%rsp)
movl $16, %edi
callq malloc
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rdi
callq strlen
movl %eax, (%r15,%rbx,4)
incq %rbx
cmpq $4, %rbx
jne .LBB1_1
# %bb.2:
movl $16, %edi
callq malloc
movq %rax, %r13
xorl %eax, %eax
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movl -4(%r15,%rax,4), %ecx
addl -4(%r13,%rax,4), %ecx
movl %ecx, (%r13,%rax,4)
.LBB1_6: # in Loop: Header=BB1_3 Depth=1
incq %rax
cmpq $4, %rax
je .LBB1_7
.LBB1_3: # =>This Inner Loop Header: Depth=1
testq %rax, %rax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl $0, (%r13)
jmp .LBB1_6
.LBB1_7: # %.preheader149.preheader
xorl %r14d, %r14d
leaq 320(%rsp), %rbx
.p2align 4, 0x90
.LBB1_8: # %.preheader149
# =>This Inner Loop Header: Depth=1
movq 112(%rsp,%r14,8), %rsi
movq %rbx, %rdi
callq strcat
incq %r14
cmpq $4, %r14
jne .LBB1_8
# %bb.9:
leaq 320(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $.L.str.5, %edi
movl $.L.str, %esi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movq 112(%rsp,%rbx,8), %rsi
movl (%r15,%rbx,4), %edx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
jne .LBB1_10
# %bb.11: # %.preheader148.preheader
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_12: # %.preheader148
# =>This Inner Loop Header: Depth=1
movslq (%r15,%rax,4), %rcx
movslq %ebp, %rbp
addq %rcx, %rbp
incq %rax
cmpq $4, %rax
jne .LBB1_12
# %bb.13: # %.preheader
leaq 80(%rsp), %rdi
callq strlen
xorl %ecx, %ecx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
subl (%r15,%rcx,4), %r12d
addl %eax, %r12d
incl %r12d
incq %rcx
cmpq $4, %rcx
jne .LBB1_14
# %bb.15:
movslq %r12d, %rbx
leaq (,%rbx,4), %r14
shlq $34, %rbx
sarq $32, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 144(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
movq %r14, %rdi
callq malloc
movq %rax, %r14
xorl %ebx, %ebx
jmp .LBB1_16
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_16 Depth=1
movl 64(%rsp,%rbx,4), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4, %rbx
je .LBB1_21
.LBB1_16: # =>This Loop Header: Depth=1
# Child Loop BB1_18 Depth 2
movslq (%r13,%rbx,4), %rdx
movl $0, 64(%rsp,%rbx,4)
movl (%r15,%rbx,4), %eax
testl %eax, %eax
jle .LBB1_20
# %bb.17: # %.lr.ph
# in Loop: Header=BB1_16 Depth=1
movl 64(%rsp,%rbx,4), %ecx
addq %rsp, %rdx
addq $320, %rdx # imm = 0x140
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_18: # Parent Loop BB1_16 Depth=1
# => This Inner Loop Header: Depth=2
shll $8, %ecx
movsbl (%rdx,%rsi), %edi
addl %ecx, %edi
movslq %edi, %rcx
imulq $-2089327119, %rcx, %rdi # imm = 0x837765F1
shrq $32, %rdi
addl %ecx, %edi
movl %edi, %r8d
shrl $31, %r8d
sarl $9, %edi
addl %r8d, %edi
imull $997, %edi, %edi # imm = 0x3E5
subl %edi, %ecx
incq %rsi
cmpq %rsi, %rax
jne .LBB1_18
# %bb.19: # %._crit_edge
# in Loop: Header=BB1_16 Depth=1
movl %ecx, 64(%rsp,%rbx,4)
jmp .LBB1_20
.LBB1_21:
leaq 48(%rsp), %rdi
movl $17, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_22
# %bb.24:
movl $.Lstr, %edi
callq puts@PLT
movq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $17, %edx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movl $.Lstr.1, %edi
callq puts@PLT
movq 40(%rsp), %rdi
leaq 320(%rsp), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movl $.Lstr.2, %edi
callq puts@PLT
movq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movl $.Lstr.3, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $16, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.25:
leaq 32(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movl %r12d, %r13d
movabsq $4294967296, %rdi # imm = 0x100000000
leaq (%rdi,%r13), %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB1_27
# %bb.26:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
movq 24(%rsp), %r8
movq %rax, 248(%rsp)
movl $17, 60(%rsp)
movq %rcx, 240(%rsp)
movq %rdx, 232(%rsp)
movq %rsi, 224(%rsp)
movq %rdi, 216(%rsp)
movq %r8, 208(%rsp)
leaq 248(%rsp), %rax
movq %rax, 256(%rsp)
leaq 60(%rsp), %rax
movq %rax, 264(%rsp)
leaq 240(%rsp), %rax
movq %rax, 272(%rsp)
leaq 232(%rsp), %rax
movq %rax, 280(%rsp)
leaq 224(%rsp), %rax
movq %rax, 288(%rsp)
leaq 216(%rsp), %rax
movq %rax, 296(%rsp)
leaq 208(%rsp), %rax
movq %rax, 304(%rsp)
leaq 192(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 168(%rsp), %rdx
leaq 160(%rsp), %rcx
callq __hipPopCallConfiguration
movq 192(%rsp), %rsi
movl 200(%rsp), %edx
movq 176(%rsp), %rcx
movl 184(%rsp), %r8d
leaq 256(%rsp), %r9
movl $_Z14findIfExistsCuPciS_PiS0_S0_S0_, %edi
pushq 160(%rsp)
.cfi_adjust_cfa_offset 8
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_27:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_28
# %bb.29:
callq hipDeviceSynchronize
movl $.Lstr.4, %edi
callq puts@PLT
movq 32(%rsp), %rsi
movl $16, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_30
# %bb.31:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %rbp, %rdi
movq 144(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
testl %r12d, %r12d
jle .LBB1_32
# %bb.38: # %.lr.ph163.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_39: # %.lr.ph163
# =>This Inner Loop Header: Depth=1
movslq (%rbp,%rax,4), %r15
cmpq %r15, %rcx
cmovaq %rcx, %r15
incq %rax
movq %r15, %rcx
cmpq %rax, %r13
jne .LBB1_39
jmp .LBB1_33
.LBB1_32:
xorl %r15d, %r15d
.LBB1_33: # %._crit_edge164
movl $.L.str.16, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.17, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.L.str.18, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
movl $.Lstr.5, %edi
callq puts@PLT
leaq 80(%rsp), %rsi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
xorl %ebx, %ebx
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_36: # in Loop: Header=BB1_34 Depth=1
incq %rbx
cmpq $4, %rbx
je .LBB1_37
.LBB1_34: # =>This Inner Loop Header: Depth=1
cmpl $1, (%r14,%rbx,4)
jne .LBB1_36
# %bb.35: # in Loop: Header=BB1_34 Depth=1
movq 112(%rsp,%rbx,8), %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_36
.LBB1_37:
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipFree
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
xorl %eax, %eax
addq $424, %rsp # imm = 0x1A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 480
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_23
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.13, %esi
jmp .LBB1_23
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.15, %esi
.LBB1_23:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14findIfExistsCuPciS_PiS0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14findIfExistsCuPciS_PiS0_S0_S0_,@object # @_Z14findIfExistsCuPciS_PiS0_S0_S0_
.section .rodata,"a",@progbits
.globl _Z14findIfExistsCuPciS_PiS0_S0_S0_
.p2align 3, 0x0
_Z14findIfExistsCuPciS_PiS0_S0_S0_:
.quad _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.size _Z14findIfExistsCuPciS_PiS0_S0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "alxxl"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "llo"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", 297"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "97 Cl"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Pattern: \"%s\" ...\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Pattern: \"%s\"\n"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Pattern: \"%s\", lenth: %d.\n"
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "patHash %d \n"
.size .L.str.7, 13
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to allocate device d_input(error code %s)!\n"
.size .L.str.8, 51
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.13, 42
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Failed to copy result from device to host (error code %s)!\n"
.size .L.str.15, 60
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Kernel Execution Time: %llu cycles\n"
.size .L.str.16, 36
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Total cycles: %d \n"
.size .L.str.17, 19
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel Execution Time: %d cycles\n"
.size .L.str.18, 34
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Input string: %s\n"
.size .L.str.20, 18
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Pattern: \"%s\" was found.\n"
.size .L.str.21, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14findIfExistsCuPciS_PiS0_S0_S0_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Copy input string from the host memory to the CUDA device"
.size .Lstr, 58
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Copy pattern string from the host memory to the CUDA device"
.size .Lstr.1, 60
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Copy Hashes from the host memory to the CUDA device"
.size .Lstr.2, 52
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Copy patternsLength from the host memory to the CUDA device"
.size .Lstr.3, 60
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Copy output data from the CUDA device to the host memory"
.size .Lstr.4, 57
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Searching for multiple patterns in the input sequence"
.size .Lstr.5, 54
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__findIfExistsCuPciS_PiS0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14findIfExistsCuPciS_PiS0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <stdio.h>
#define TILE_SZ 16
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
* Use shared memory for tiling
*
********************************************************************/
// INSERT KERNEL CODE HERE
unsigned int TiRow = threadIdx.y;
unsigned int TiCol = threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float As[TILE_SZ][TILE_SZ];
__shared__ float Bs[TILE_SZ][TILE_SZ];
float sum = 0;
for(unsigned int TiNum = 0; TiNum < (k-1)/TILE_SZ+1; TiNum++){
if((row < m) && (TiNum * TILE_SZ + TiCol) < k)
As[TiRow][TiCol]= A[row * k + TiNum * TILE_SZ + TiCol];
else
As[TiRow][TiCol] = 0;
if((TiNum * TILE_SZ + TiRow) < k && col < n)
Bs[TiRow][TiCol] = B[(TiNum * TILE_SZ + TiRow) * n + col];
else
Bs[TiRow][TiCol] = 0;
__syncthreads();
//Calculate inner product for the tile
//Checking for matrix size to lower power and practice green computing
if(row < m && col < n)
for(unsigned int TiElem = 0; TiElem < TILE_SZ; TiElem++)
sum = sum + As[TiRow][TiElem]*Bs[TiElem][TiCol];
__syncthreads();
}
//Prevent writing of output to an undefined block
if (row < m && col < n)
C[row * n + col] = sum;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
//INSERT CODE HERE
const unsigned int BLOCK_SIZE = TILE_SZ; //use 16 x 16 thread blocks
dim3 block(BLOCK_SIZE, BLOCK_SIZE ,1);
dim3 grid((n + BLOCK_SIZE - 1)/BLOCK_SIZE, (m + BLOCK_SIZE -1)/BLOCK_SIZE, 1);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<< grid, block>>>(m, n, k, A, B, C);
} | code for sm_80
Function : _Z7mysgemmiiiPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0020*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e220000002200 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0070*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fc60008011404 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0090*/ ULEA.HI UR5, UR5, UR4, URZ, 0x4 ; /* 0x0000000405057291 */
/* 0x000fc6000f8f203f */
/*00a0*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e620000002100 */
/*00b0*/ ULEA.HI.SX32 UR5, UR5, 0x1, 0x1c ; /* 0x0000000105057891 */
/* 0x000fcc000f8fe23f */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf05270 */
/*00d0*/ IMAD R2, R3, c[0x0][0x4], R16 ; /* 0x0000010003027a24 */
/* 0x001fe400078e0210 */
/*00e0*/ IMAD R3, R0, c[0x0][0x0], R17 ; /* 0x0000000000037a24 */
/* 0x002fd400078e0211 */
/*00f0*/ @!P0 BRA 0x5a0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD R18, R16.reuse, c[0x0][0x164], R3 ; /* 0x0000590010127a24 */
/* 0x040fe200078e0203 */
/*0120*/ LEA R0, R16, R17, 0x4 ; /* 0x0000001110007211 */
/* 0x000fe200078e20ff */
/*0130*/ IMAD R19, R2.reuse, c[0x0][0x168], R17 ; /* 0x00005a0002137a24 */
/* 0x040fe200078e0211 */
/*0140*/ ISETP.LT.U32.AND P0, PT, R2, c[0x0][0x160], !P0 ; /* 0x0000580002007a0c */
/* 0x000fe40004701070 */
/*0150*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0170*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fc400000006ff */
/*0180*/ ISETP.GE.U32.AND P2, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fe20003f46070 */
/*0190*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R16, c[0x0][0x168], PT ; /* 0x00005a0010007a0c */
/* 0x000fc40003f26070 */
/*01b0*/ ISETP.GE.U32.OR P2, PT, R2, c[0x0][0x160], P2 ; /* 0x0000580002007a0c */
/* 0x000fe40001746470 */
/*01c0*/ ISETP.GE.U32.OR P1, PT, R3, c[0x0][0x164], P1 ; /* 0x0000590003007a0c */
/* 0x000fe40000f26470 */
/*01d0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fd20000000f00 */
/*01e0*/ @!P2 MOV R4, 0x4 ; /* 0x000000040004a802 */
/* 0x000fe40000000f00 */
/*01f0*/ @!P1 MOV R7, 0x4 ; /* 0x0000000400079802 */
/* 0x000fc60000000f00 */
/*0200*/ @!P2 IMAD.WIDE.U32 R4, R19, R4, c[0x0][0x170] ; /* 0x00005c001304a625 */
/* 0x000fc800078e0004 */
/*0210*/ @!P1 IMAD.WIDE.U32 R6, R18, R7, c[0x0][0x178] ; /* 0x00005e0012069625 */
/* 0x000fe200078e0007 */
/*0220*/ @!P2 LDG.E R9, [R4.64] ; /* 0x000000060409a981 */
/* 0x000ea8000c1e1900 */
/*0230*/ @!P1 LDG.E R11, [R6.64] ; /* 0x00000006060b9981 */
/* 0x000ee2000c1e1900 */
/*0240*/ BSSY B0, 0x510 ; /* 0x000002c000007945 */
/* 0x000fe60003800000 */
/*0250*/ STS [R0], R9 ; /* 0x0000000900007388 */
/* 0x0041e80000000800 */
/*0260*/ STS [R0+0x400], R11 ; /* 0x0004000b00007388 */
/* 0x0081e80000000800 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ @!P0 BRA 0x500 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0290*/ S2R R23, SR_TID.Y ; /* 0x0000000000177919 */
/* 0x001e280000002200 */
/*02a0*/ S2R R20, SR_TID.X ; /* 0x0000000000147919 */
/* 0x000e620000002100 */
/*02b0*/ SHF.L.U32 R23, R23, 0x6, RZ ; /* 0x0000000617177819 */
/* 0x001fc600000006ff */
/*02c0*/ LDS R22, [R20.X4+0x400] ; /* 0x0004000014167984 */
/* 0x002fe80000004800 */
/*02d0*/ LDS.128 R8, [R23] ; /* 0x0000000017087984 */
/* 0x000e280000000c00 */
/*02e0*/ LDS R24, [R20.X4+0x440] ; /* 0x0004400014187984 */
/* 0x000e680000004800 */
/*02f0*/ LDS R26, [R20.X4+0x480] ; /* 0x00048000141a7984 */
/* 0x000ea80000004800 */
/*0300*/ LDS R14, [R20.X4+0x4c0] ; /* 0x0004c000140e7984 */
/* 0x000ee80000004800 */
/*0310*/ LDS R15, [R20.X4+0x500] ; /* 0x00050000140f7984 */
/* 0x000fe80000004800 */
/*0320*/ LDS.128 R4, [R23+0x10] ; /* 0x0000100017047984 */
/* 0x000f280000000c00 */
/*0330*/ LDS R12, [R20.X4+0x540] ; /* 0x00054000140c7984 */
/* 0x000f680000004800 */
/*0340*/ LDS R13, [R20.X4+0x580] ; /* 0x00058000140d7984 */
/* 0x000f680000004800 */
/*0350*/ LDS R27, [R20.X4+0x680] ; /* 0x00068000141b7984 */
/* 0x000fe20000004800 */
/*0360*/ FFMA R8, R22, R8, R21 ; /* 0x0000000816087223 */
/* 0x001fc60000000015 */
/*0370*/ LDS R22, [R20.X4+0x5c0] ; /* 0x0005c00014167984 */
/* 0x000e220000004800 */
/*0380*/ FFMA R9, R24, R9, R8 ; /* 0x0000000918097223 */
/* 0x002fc60000000008 */
/*0390*/ LDS R21, [R20.X4+0x600] ; /* 0x0006000014157984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R9, R26, R10, R9 ; /* 0x0000000a1a097223 */
/* 0x004fc60000000009 */
/*03b0*/ LDS R24, [R20.X4+0x640] ; /* 0x0006400014187984 */
/* 0x000fe20000004800 */
/*03c0*/ FFMA R14, R14, R11, R9 ; /* 0x0000000b0e0e7223 */
/* 0x008fc60000000009 */
/*03d0*/ LDS.128 R8, [R23+0x20] ; /* 0x0000200017087984 */
/* 0x000e620000000c00 */
/*03e0*/ FFMA R4, R15, R4, R14 ; /* 0x000000040f047223 */
/* 0x010fc8000000000e */
/*03f0*/ FFMA R5, R12, R5, R4 ; /* 0x000000050c057223 */
/* 0x020fe40000000004 */
/*0400*/ LDS R4, [R20.X4+0x6c0] ; /* 0x0006c00014047984 */
/* 0x000ea40000004800 */
/*0410*/ FFMA R6, R13, R6, R5 ; /* 0x000000060d067223 */
/* 0x000fe40000000005 */
/*0420*/ LDS R5, [R20.X4+0x700] ; /* 0x0007000014057984 */
/* 0x000fe80000004800 */
/*0430*/ LDS.128 R12, [R23+0x30] ; /* 0x00003000170c7984 */
/* 0x000ee20000000c00 */
/*0440*/ FFMA R26, R22, R7, R6 ; /* 0x00000007161a7223 */
/* 0x001fc60000000006 */
/*0450*/ LDS R6, [R20.X4+0x740] ; /* 0x0007400014067984 */
/* 0x000e280000004800 */
/*0460*/ LDS R7, [R20.X4+0x780] ; /* 0x0007800014077984 */
/* 0x000f280000004800 */
/*0470*/ LDS R22, [R20.X4+0x7c0] ; /* 0x0007c00014167984 */
/* 0x000f620000004800 */
/*0480*/ FFMA R8, R21, R8, R26 ; /* 0x0000000815087223 */
/* 0x002fc8000000001a */
/*0490*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x000fc80000000008 */
/*04a0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x000fc80000000008 */
/*04b0*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x004fc80000000008 */
/*04c0*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x008fc80000000004 */
/*04d0*/ FFMA R4, R6, R13, R4 ; /* 0x0000000d06047223 */
/* 0x001fc80000000004 */
/*04e0*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x010fc80000000004 */
/*04f0*/ FFMA R21, R22, R15, R4 ; /* 0x0000000f16157223 */
/* 0x020fe40000000004 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0510*/ IADD3 R25, R25, 0x1, RZ ; /* 0x0000000119197810 */
/* 0x000fe20007ffe0ff */
/*0520*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ IADD3 R16, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P1, PT, R25, UR5, PT ; /* 0x0000000519007c0c */
/* 0x000fe4000bf26070 */
/*0560*/ IADD3 R17, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe40007ffe0ff */
/*0580*/ IMAD R18, R5, c[0x0][0x164], R18 ; /* 0x0000590005127a24 */
/* 0x000fce00078e0212 */
/*0590*/ @!P1 BRA 0x180 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fc80003f06070 */
/*05b0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x000fda0000706470 */
/*05c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05d0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*05e0*/ IMAD R2, R2, c[0x0][0x164], R3 ; /* 0x0000590002027a24 */
/* 0x000fc800078e0203 */
/*05f0*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0005 */
/*0600*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <stdio.h>
#define TILE_SZ 16
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
* Use shared memory for tiling
*
********************************************************************/
// INSERT KERNEL CODE HERE
unsigned int TiRow = threadIdx.y;
unsigned int TiCol = threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float As[TILE_SZ][TILE_SZ];
__shared__ float Bs[TILE_SZ][TILE_SZ];
float sum = 0;
for(unsigned int TiNum = 0; TiNum < (k-1)/TILE_SZ+1; TiNum++){
if((row < m) && (TiNum * TILE_SZ + TiCol) < k)
As[TiRow][TiCol]= A[row * k + TiNum * TILE_SZ + TiCol];
else
As[TiRow][TiCol] = 0;
if((TiNum * TILE_SZ + TiRow) < k && col < n)
Bs[TiRow][TiCol] = B[(TiNum * TILE_SZ + TiRow) * n + col];
else
Bs[TiRow][TiCol] = 0;
__syncthreads();
//Calculate inner product for the tile
//Checking for matrix size to lower power and practice green computing
if(row < m && col < n)
for(unsigned int TiElem = 0; TiElem < TILE_SZ; TiElem++)
sum = sum + As[TiRow][TiElem]*Bs[TiElem][TiCol];
__syncthreads();
}
//Prevent writing of output to an undefined block
if (row < m && col < n)
C[row * n + col] = sum;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
//INSERT CODE HERE
const unsigned int BLOCK_SIZE = TILE_SZ; //use 16 x 16 thread blocks
dim3 block(BLOCK_SIZE, BLOCK_SIZE ,1);
dim3 grid((n + BLOCK_SIZE - 1)/BLOCK_SIZE, (m + BLOCK_SIZE -1)/BLOCK_SIZE, 1);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<< grid, block>>>(m, n, k, A, B, C);
} | .file "tmpxft_000ae0f4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
.type _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf, @function
_Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7mysgemmiiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf, .-_Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
.globl _Z7mysgemmiiiPKfS0_Pf
.type _Z7mysgemmiiiPKfS0_Pf, @function
_Z7mysgemmiiiPKfS0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7mysgemmiiiPKfS0_Pf, .-_Z7mysgemmiiiPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "unsupported value of 'transa'\n"
.align 8
.LC1:
.string "unsupported value of 'transb'\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "unsupported value of alpha\n"
.LC6:
.string "unsupported value of beta\n"
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.type _Z10basicSgemmcciiifPKfiS0_ifPfi, @function
_Z10basicSgemmcciiifPKfiS0_ifPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
andl $-33, %edi
cmpb $78, %dil
jne .L26
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movq %r9, %r13
andl $-33, %esi
cmpb $78, %sil
jne .L27
subss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC3(%rip), %xmm0
ja .L15
movsd .LC4(%rip), %xmm2
comisd %xmm0, %xmm2
ja .L15
cvtss2sd %xmm1, %xmm1
comisd .LC3(%rip), %xmm1
ja .L18
movsd .LC4(%rip), %xmm0
comisd %xmm1, %xmm0
jbe .L24
.L18:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $16, 8(%rsp)
movl $16, 12(%rsp)
leal 15(%rcx), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%rdx), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movq 104(%rsp), %r9
movq 88(%rsp), %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .-_Z10basicSgemmcciiifPKfiS0_ifPfi
.section .rodata.str1.1
.LC7:
.string "_Z7mysgemmiiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mysgemmiiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -640172613
.long 1037794527
.align 8
.LC4:
.long -640172613
.long -1109689121
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <stdio.h>
#define TILE_SZ 16
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
* Use shared memory for tiling
*
********************************************************************/
// INSERT KERNEL CODE HERE
unsigned int TiRow = threadIdx.y;
unsigned int TiCol = threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float As[TILE_SZ][TILE_SZ];
__shared__ float Bs[TILE_SZ][TILE_SZ];
float sum = 0;
for(unsigned int TiNum = 0; TiNum < (k-1)/TILE_SZ+1; TiNum++){
if((row < m) && (TiNum * TILE_SZ + TiCol) < k)
As[TiRow][TiCol]= A[row * k + TiNum * TILE_SZ + TiCol];
else
As[TiRow][TiCol] = 0;
if((TiNum * TILE_SZ + TiRow) < k && col < n)
Bs[TiRow][TiCol] = B[(TiNum * TILE_SZ + TiRow) * n + col];
else
Bs[TiRow][TiCol] = 0;
__syncthreads();
//Calculate inner product for the tile
//Checking for matrix size to lower power and practice green computing
if(row < m && col < n)
for(unsigned int TiElem = 0; TiElem < TILE_SZ; TiElem++)
sum = sum + As[TiRow][TiElem]*Bs[TiElem][TiCol];
__syncthreads();
}
//Prevent writing of output to an undefined block
if (row < m && col < n)
C[row * n + col] = sum;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
//INSERT CODE HERE
const unsigned int BLOCK_SIZE = TILE_SZ; //use 16 x 16 thread blocks
dim3 block(BLOCK_SIZE, BLOCK_SIZE ,1);
dim3 grid((n + BLOCK_SIZE - 1)/BLOCK_SIZE, (m + BLOCK_SIZE -1)/BLOCK_SIZE, 1);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<< grid, block>>>(m, n, k, A, B, C);
} | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SZ 16
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
* Use shared memory for tiling
*
********************************************************************/
// INSERT KERNEL CODE HERE
unsigned int TiRow = threadIdx.y;
unsigned int TiCol = threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float As[TILE_SZ][TILE_SZ];
__shared__ float Bs[TILE_SZ][TILE_SZ];
float sum = 0;
for(unsigned int TiNum = 0; TiNum < (k-1)/TILE_SZ+1; TiNum++){
if((row < m) && (TiNum * TILE_SZ + TiCol) < k)
As[TiRow][TiCol]= A[row * k + TiNum * TILE_SZ + TiCol];
else
As[TiRow][TiCol] = 0;
if((TiNum * TILE_SZ + TiRow) < k && col < n)
Bs[TiRow][TiCol] = B[(TiNum * TILE_SZ + TiRow) * n + col];
else
Bs[TiRow][TiCol] = 0;
__syncthreads();
//Calculate inner product for the tile
//Checking for matrix size to lower power and practice green computing
if(row < m && col < n)
for(unsigned int TiElem = 0; TiElem < TILE_SZ; TiElem++)
sum = sum + As[TiRow][TiElem]*Bs[TiElem][TiCol];
__syncthreads();
}
//Prevent writing of output to an undefined block
if (row < m && col < n)
C[row * n + col] = sum;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
//INSERT CODE HERE
const unsigned int BLOCK_SIZE = TILE_SZ; //use 16 x 16 thread blocks
dim3 block(BLOCK_SIZE, BLOCK_SIZE ,1);
dim3 grid((n + BLOCK_SIZE - 1)/BLOCK_SIZE, (m + BLOCK_SIZE -1)/BLOCK_SIZE, 1);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<< grid, block>>>(m, n, k, A, B, C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SZ 16
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
* Use shared memory for tiling
*
********************************************************************/
// INSERT KERNEL CODE HERE
unsigned int TiRow = threadIdx.y;
unsigned int TiCol = threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float As[TILE_SZ][TILE_SZ];
__shared__ float Bs[TILE_SZ][TILE_SZ];
float sum = 0;
for(unsigned int TiNum = 0; TiNum < (k-1)/TILE_SZ+1; TiNum++){
if((row < m) && (TiNum * TILE_SZ + TiCol) < k)
As[TiRow][TiCol]= A[row * k + TiNum * TILE_SZ + TiCol];
else
As[TiRow][TiCol] = 0;
if((TiNum * TILE_SZ + TiRow) < k && col < n)
Bs[TiRow][TiCol] = B[(TiNum * TILE_SZ + TiRow) * n + col];
else
Bs[TiRow][TiCol] = 0;
__syncthreads();
//Calculate inner product for the tile
//Checking for matrix size to lower power and practice green computing
if(row < m && col < n)
for(unsigned int TiElem = 0; TiElem < TILE_SZ; TiElem++)
sum = sum + As[TiRow][TiElem]*Bs[TiElem][TiCol];
__syncthreads();
}
//Prevent writing of output to an undefined block
if (row < m && col < n)
C[row * n + col] = sum;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
//INSERT CODE HERE
const unsigned int BLOCK_SIZE = TILE_SZ; //use 16 x 16 thread blocks
dim3 block(BLOCK_SIZE, BLOCK_SIZE ,1);
dim3 grid((n + BLOCK_SIZE - 1)/BLOCK_SIZE, (m + BLOCK_SIZE -1)/BLOCK_SIZE, 1);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<< grid, block>>>(m, n, k, A, B, C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mysgemmiiiPKfS0_Pf
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 8
.type _Z7mysgemmiiiPKfS0_Pf,@function
_Z7mysgemmiiiPKfS0_Pf:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
v_mov_b32_e32 v2, 0
s_add_i32 s4, s3, 30
s_cmp_lt_u32 s4, 16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, s8, v0
v_cmp_gt_u32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_17
s_load_b128 s[4:7], s[0:1], 0x10
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v2, 2, v4
s_add_i32 s10, s3, -1
v_lshlrev_b32_e32 v8, 6, v3
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v9, 0x400, v2
v_mad_u64_u32 v[5:6], null, v0, s3, v[4:5]
s_lshr_b32 s11, s11, 28
v_add_nc_u32_e32 v10, v8, v2
v_mov_b32_e32 v2, 0
s_add_i32 s10, s10, s11
v_cmp_le_u32_e64 s11, s8, v0
v_add_nc_u32_e32 v11, v9, v8
s_ashr_i32 s10, s10, 4
s_and_b32 s12, vcc_lo, s2
s_mov_b32 s14, 0
s_xor_b32 s13, s2, -1
.LBB0_2:
s_mov_b32 s2, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v6, s17, v4
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s3, v6
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s17, s2
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v10, v7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v6, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, s2, s4, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s2, s5, v14, s2
global_load_b32 v6, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
v_lshl_add_u32 v6, s14, 4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s3, v6
s_or_b32 s2, s13, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s2
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_10
ds_store_b32 v11, v7
.LBB0_10:
s_and_not1_saveexec_b32 s15, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v6, s9, v[1:2]
v_mov_b32_e32 v14, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, s2, s6, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s2, s7, v14, s2
global_load_b32 v6, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v6, v9
s_mov_b32 s15, 0
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v13, s15, v8
s_add_i32 s15, s15, 4
ds_load_b32 v14, v6
ds_load_b32 v13, v13
v_add_nc_u32_e32 v6, 64, v6
s_cmp_lg_u32 s15, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v13, v14
s_cbranch_scc1 .LBB0_14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s14, 1
s_cmp_eq_u32 s14, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
s_mov_b32 s14, s2
s_branch .LBB0_2
.LBB0_17:
v_cmp_gt_u32_e32 vcc_lo, s8, v0
v_cmp_gt_u32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_19
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mysgemmiiiPKfS0_Pf
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z7mysgemmiiiPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mysgemmiiiPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z7mysgemmiiiPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define TILE_SZ 16
__global__ void mysgemm(int m, int n, int k, const float *A, const float *B, float* C) {
/********************************************************************
*
* Compute C = A x B
* where A is a (m x k) matrix
* where B is a (k x n) matrix
* where C is a (m x n) matrix
*
* Use shared memory for tiling
*
********************************************************************/
// INSERT KERNEL CODE HERE
unsigned int TiRow = threadIdx.y;
unsigned int TiCol = threadIdx.x;
unsigned int row = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int col = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float As[TILE_SZ][TILE_SZ];
__shared__ float Bs[TILE_SZ][TILE_SZ];
float sum = 0;
for(unsigned int TiNum = 0; TiNum < (k-1)/TILE_SZ+1; TiNum++){
if((row < m) && (TiNum * TILE_SZ + TiCol) < k)
As[TiRow][TiCol]= A[row * k + TiNum * TILE_SZ + TiCol];
else
As[TiRow][TiCol] = 0;
if((TiNum * TILE_SZ + TiRow) < k && col < n)
Bs[TiRow][TiCol] = B[(TiNum * TILE_SZ + TiRow) * n + col];
else
Bs[TiRow][TiCol] = 0;
__syncthreads();
//Calculate inner product for the tile
//Checking for matrix size to lower power and practice green computing
if(row < m && col < n)
for(unsigned int TiElem = 0; TiElem < TILE_SZ; TiElem++)
sum = sum + As[TiRow][TiElem]*Bs[TiElem][TiCol];
__syncthreads();
}
//Prevent writing of output to an undefined block
if (row < m && col < n)
C[row * n + col] = sum;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
printf("unsupported value of 'transa'\n");
return;
}
if ((transb != 'N') && (transb != 'n')) {
printf("unsupported value of 'transb'\n");
return;
}
if ((alpha - 1.0f > 1e-10) || (alpha - 1.0f < -1e-10)) {
printf("unsupported value of alpha\n");
return;
}
if ((beta - 0.0f > 1e-10) || (beta - 0.0f < -1e-10)) {
printf("unsupported value of beta\n");
return;
}
// Initialize thread block and kernel grid dimensions ---------------------
//INSERT CODE HERE
const unsigned int BLOCK_SIZE = TILE_SZ; //use 16 x 16 thread blocks
dim3 block(BLOCK_SIZE, BLOCK_SIZE ,1);
dim3 grid((n + BLOCK_SIZE - 1)/BLOCK_SIZE, (m + BLOCK_SIZE -1)/BLOCK_SIZE, 1);
// Invoke CUDA kernel -----------------------------------------------------
//INSERT CODE HERE
mysgemm<<< grid, block>>>(m, n, k, A, B, C);
} | .text
.file "kernel.hip"
.globl _Z22__device_stub__mysgemmiiiPKfS0_Pf # -- Begin function _Z22__device_stub__mysgemmiiiPKfS0_Pf
.p2align 4, 0x90
.type _Z22__device_stub__mysgemmiiiPKfS0_Pf,@function
_Z22__device_stub__mysgemmiiiPKfS0_Pf: # @_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10basicSgemmcciiifPKfiS0_ifPfi
.LCPI1_0:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ddb7cdfd9d7bdbb # double 1.0E-10
.LCPI1_2:
.quad 0xbddb7cdfd9d7bdbb # double -1.0E-10
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.p2align 4, 0x90
.type _Z10basicSgemmcciiifPKfiS0_ifPfi,@function
_Z10basicSgemmcciiifPKfiS0_ifPfi: # @_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_startproc
# %bb.0:
andb $-33, %dil
cmpb $78, %dil
jne .LBB1_9
# %bb.1:
andb $-33, %sil
cmpb $78, %sil
jne .LBB1_10
# %bb.2:
addss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm2
ucomisd .LCPI1_1(%rip), %xmm2
ja .LBB1_11
# %bb.3:
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm2, %xmm0
ja .LBB1_11
# %bb.4:
cvtss2sd %xmm1, %xmm1
ucomisd .LCPI1_1(%rip), %xmm1
ja .LBB1_12
# %bb.5:
ucomisd %xmm1, %xmm0
ja .LBB1_12
# %bb.6:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %r14d
movl %r8d, %ebp
movq %r9, %r12
movq 232(%rsp), %r15
movq 216(%rsp), %r13
leal 15(%rbx), %eax
shrl $4, %eax
leal 15(%r14), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movl %r14d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r12, 88(%rsp)
movq %r13, 80(%rsp)
movq %r15, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr.3, %edi
jmp puts@PLT # TAILCALL
.LBB1_10:
movl $.Lstr.2, %edi
jmp puts@PLT # TAILCALL
.LBB1_11:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.LBB1_12:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .Lfunc_end1-_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mysgemmiiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mysgemmiiiPKfS0_Pf,@object # @_Z7mysgemmiiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 3, 0x0
_Z7mysgemmiiiPKfS0_Pf:
.quad _Z22__device_stub__mysgemmiiiPKfS0_Pf
.size _Z7mysgemmiiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mysgemmiiiPKfS0_Pf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "unsupported value of beta"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "unsupported value of alpha"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "unsupported value of 'transb'"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "unsupported value of 'transa'"
.size .Lstr.3, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mysgemmiiiPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0020*/ S2R R16, SR_TID.Y ; /* 0x0000000000107919 */
/* 0x000e220000002200 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0070*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fc60008011404 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0090*/ ULEA.HI UR5, UR5, UR4, URZ, 0x4 ; /* 0x0000000405057291 */
/* 0x000fc6000f8f203f */
/*00a0*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e620000002100 */
/*00b0*/ ULEA.HI.SX32 UR5, UR5, 0x1, 0x1c ; /* 0x0000000105057891 */
/* 0x000fcc000f8fe23f */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf05270 */
/*00d0*/ IMAD R2, R3, c[0x0][0x4], R16 ; /* 0x0000010003027a24 */
/* 0x001fe400078e0210 */
/*00e0*/ IMAD R3, R0, c[0x0][0x0], R17 ; /* 0x0000000000037a24 */
/* 0x002fd400078e0211 */
/*00f0*/ @!P0 BRA 0x5a0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD R18, R16.reuse, c[0x0][0x164], R3 ; /* 0x0000590010127a24 */
/* 0x040fe200078e0203 */
/*0120*/ LEA R0, R16, R17, 0x4 ; /* 0x0000001110007211 */
/* 0x000fe200078e20ff */
/*0130*/ IMAD R19, R2.reuse, c[0x0][0x168], R17 ; /* 0x00005a0002137a24 */
/* 0x040fe200078e0211 */
/*0140*/ ISETP.LT.U32.AND P0, PT, R2, c[0x0][0x160], !P0 ; /* 0x0000580002007a0c */
/* 0x000fe40004701070 */
/*0150*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0170*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fc400000006ff */
/*0180*/ ISETP.GE.U32.AND P2, PT, R17, c[0x0][0x168], PT ; /* 0x00005a0011007a0c */
/* 0x000fe20003f46070 */
/*0190*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R16, c[0x0][0x168], PT ; /* 0x00005a0010007a0c */
/* 0x000fc40003f26070 */
/*01b0*/ ISETP.GE.U32.OR P2, PT, R2, c[0x0][0x160], P2 ; /* 0x0000580002007a0c */
/* 0x000fe40001746470 */
/*01c0*/ ISETP.GE.U32.OR P1, PT, R3, c[0x0][0x164], P1 ; /* 0x0000590003007a0c */
/* 0x000fe40000f26470 */
/*01d0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fd20000000f00 */
/*01e0*/ @!P2 MOV R4, 0x4 ; /* 0x000000040004a802 */
/* 0x000fe40000000f00 */
/*01f0*/ @!P1 MOV R7, 0x4 ; /* 0x0000000400079802 */
/* 0x000fc60000000f00 */
/*0200*/ @!P2 IMAD.WIDE.U32 R4, R19, R4, c[0x0][0x170] ; /* 0x00005c001304a625 */
/* 0x000fc800078e0004 */
/*0210*/ @!P1 IMAD.WIDE.U32 R6, R18, R7, c[0x0][0x178] ; /* 0x00005e0012069625 */
/* 0x000fe200078e0007 */
/*0220*/ @!P2 LDG.E R9, [R4.64] ; /* 0x000000060409a981 */
/* 0x000ea8000c1e1900 */
/*0230*/ @!P1 LDG.E R11, [R6.64] ; /* 0x00000006060b9981 */
/* 0x000ee2000c1e1900 */
/*0240*/ BSSY B0, 0x510 ; /* 0x000002c000007945 */
/* 0x000fe60003800000 */
/*0250*/ STS [R0], R9 ; /* 0x0000000900007388 */
/* 0x0041e80000000800 */
/*0260*/ STS [R0+0x400], R11 ; /* 0x0004000b00007388 */
/* 0x0081e80000000800 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0280*/ @!P0 BRA 0x500 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0290*/ S2R R23, SR_TID.Y ; /* 0x0000000000177919 */
/* 0x001e280000002200 */
/*02a0*/ S2R R20, SR_TID.X ; /* 0x0000000000147919 */
/* 0x000e620000002100 */
/*02b0*/ SHF.L.U32 R23, R23, 0x6, RZ ; /* 0x0000000617177819 */
/* 0x001fc600000006ff */
/*02c0*/ LDS R22, [R20.X4+0x400] ; /* 0x0004000014167984 */
/* 0x002fe80000004800 */
/*02d0*/ LDS.128 R8, [R23] ; /* 0x0000000017087984 */
/* 0x000e280000000c00 */
/*02e0*/ LDS R24, [R20.X4+0x440] ; /* 0x0004400014187984 */
/* 0x000e680000004800 */
/*02f0*/ LDS R26, [R20.X4+0x480] ; /* 0x00048000141a7984 */
/* 0x000ea80000004800 */
/*0300*/ LDS R14, [R20.X4+0x4c0] ; /* 0x0004c000140e7984 */
/* 0x000ee80000004800 */
/*0310*/ LDS R15, [R20.X4+0x500] ; /* 0x00050000140f7984 */
/* 0x000fe80000004800 */
/*0320*/ LDS.128 R4, [R23+0x10] ; /* 0x0000100017047984 */
/* 0x000f280000000c00 */
/*0330*/ LDS R12, [R20.X4+0x540] ; /* 0x00054000140c7984 */
/* 0x000f680000004800 */
/*0340*/ LDS R13, [R20.X4+0x580] ; /* 0x00058000140d7984 */
/* 0x000f680000004800 */
/*0350*/ LDS R27, [R20.X4+0x680] ; /* 0x00068000141b7984 */
/* 0x000fe20000004800 */
/*0360*/ FFMA R8, R22, R8, R21 ; /* 0x0000000816087223 */
/* 0x001fc60000000015 */
/*0370*/ LDS R22, [R20.X4+0x5c0] ; /* 0x0005c00014167984 */
/* 0x000e220000004800 */
/*0380*/ FFMA R9, R24, R9, R8 ; /* 0x0000000918097223 */
/* 0x002fc60000000008 */
/*0390*/ LDS R21, [R20.X4+0x600] ; /* 0x0006000014157984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R9, R26, R10, R9 ; /* 0x0000000a1a097223 */
/* 0x004fc60000000009 */
/*03b0*/ LDS R24, [R20.X4+0x640] ; /* 0x0006400014187984 */
/* 0x000fe20000004800 */
/*03c0*/ FFMA R14, R14, R11, R9 ; /* 0x0000000b0e0e7223 */
/* 0x008fc60000000009 */
/*03d0*/ LDS.128 R8, [R23+0x20] ; /* 0x0000200017087984 */
/* 0x000e620000000c00 */
/*03e0*/ FFMA R4, R15, R4, R14 ; /* 0x000000040f047223 */
/* 0x010fc8000000000e */
/*03f0*/ FFMA R5, R12, R5, R4 ; /* 0x000000050c057223 */
/* 0x020fe40000000004 */
/*0400*/ LDS R4, [R20.X4+0x6c0] ; /* 0x0006c00014047984 */
/* 0x000ea40000004800 */
/*0410*/ FFMA R6, R13, R6, R5 ; /* 0x000000060d067223 */
/* 0x000fe40000000005 */
/*0420*/ LDS R5, [R20.X4+0x700] ; /* 0x0007000014057984 */
/* 0x000fe80000004800 */
/*0430*/ LDS.128 R12, [R23+0x30] ; /* 0x00003000170c7984 */
/* 0x000ee20000000c00 */
/*0440*/ FFMA R26, R22, R7, R6 ; /* 0x00000007161a7223 */
/* 0x001fc60000000006 */
/*0450*/ LDS R6, [R20.X4+0x740] ; /* 0x0007400014067984 */
/* 0x000e280000004800 */
/*0460*/ LDS R7, [R20.X4+0x780] ; /* 0x0007800014077984 */
/* 0x000f280000004800 */
/*0470*/ LDS R22, [R20.X4+0x7c0] ; /* 0x0007c00014167984 */
/* 0x000f620000004800 */
/*0480*/ FFMA R8, R21, R8, R26 ; /* 0x0000000815087223 */
/* 0x002fc8000000001a */
/*0490*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x000fc80000000008 */
/*04a0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x000fc80000000008 */
/*04b0*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x004fc80000000008 */
/*04c0*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x008fc80000000004 */
/*04d0*/ FFMA R4, R6, R13, R4 ; /* 0x0000000d06047223 */
/* 0x001fc80000000004 */
/*04e0*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x010fc80000000004 */
/*04f0*/ FFMA R21, R22, R15, R4 ; /* 0x0000000f16157223 */
/* 0x020fe40000000004 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0510*/ IADD3 R25, R25, 0x1, RZ ; /* 0x0000000119197810 */
/* 0x000fe20007ffe0ff */
/*0520*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0540*/ IADD3 R16, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P1, PT, R25, UR5, PT ; /* 0x0000000519007c0c */
/* 0x000fe4000bf26070 */
/*0560*/ IADD3 R17, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fe40007ffe0ff */
/*0570*/ IADD3 R19, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe40007ffe0ff */
/*0580*/ IMAD R18, R5, c[0x0][0x164], R18 ; /* 0x0000590005127a24 */
/* 0x000fce00078e0212 */
/*0590*/ @!P1 BRA 0x180 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fc80003f06070 */
/*05b0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x000fda0000706470 */
/*05c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05d0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe20000000f00 */
/*05e0*/ IMAD R2, R2, c[0x0][0x164], R3 ; /* 0x0000590002027a24 */
/* 0x000fc800078e0203 */
/*05f0*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0005 */
/*0600*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mysgemmiiiPKfS0_Pf
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 8
.type _Z7mysgemmiiiPKfS0_Pf,@function
_Z7mysgemmiiiPKfS0_Pf:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s2, v[4:5]
v_mov_b32_e32 v2, 0
s_add_i32 s4, s3, 30
s_cmp_lt_u32 s4, 16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, s8, v0
v_cmp_gt_u32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_17
s_load_b128 s[4:7], s[0:1], 0x10
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v2, 2, v4
s_add_i32 s10, s3, -1
v_lshlrev_b32_e32 v8, 6, v3
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v9, 0x400, v2
v_mad_u64_u32 v[5:6], null, v0, s3, v[4:5]
s_lshr_b32 s11, s11, 28
v_add_nc_u32_e32 v10, v8, v2
v_mov_b32_e32 v2, 0
s_add_i32 s10, s10, s11
v_cmp_le_u32_e64 s11, s8, v0
v_add_nc_u32_e32 v11, v9, v8
s_ashr_i32 s10, s10, 4
s_and_b32 s12, vcc_lo, s2
s_mov_b32 s14, 0
s_xor_b32 s13, s2, -1
.LBB0_2:
s_mov_b32 s2, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
s_lshl_b32 s17, s14, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v6, s17, v4
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s11, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s3, v6
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s17, s2
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s16
s_cbranch_execz .LBB0_6
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v10, v7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v6, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[6:7]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, s2, s4, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s2, s5, v14, s2
global_load_b32 v6, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
v_lshl_add_u32 v6, s14, 4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s3, v6
s_or_b32 s2, s13, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s2
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_10
ds_store_b32 v11, v7
.LBB0_10:
s_and_not1_saveexec_b32 s15, s2
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v6, s9, v[1:2]
v_mov_b32_e32 v14, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v13, s2, s6, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s2, s7, v14, s2
global_load_b32 v6, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_15
v_mov_b32_e32 v6, v9
s_mov_b32 s15, 0
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v13, s15, v8
s_add_i32 s15, s15, 4
ds_load_b32 v14, v6
ds_load_b32 v13, v13
v_add_nc_u32_e32 v6, 64, v6
s_cmp_lg_u32 s15, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v13, v14
s_cbranch_scc1 .LBB0_14
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s2, s14, 1
s_cmp_eq_u32 s14, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
s_mov_b32 s14, s2
s_branch .LBB0_2
.LBB0_17:
v_cmp_gt_u32_e32 vcc_lo, s8, v0
v_cmp_gt_u32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_19
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[3:4], null, v0, s9, v[1:2]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mysgemmiiiPKfS0_Pf
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z7mysgemmiiiPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mysgemmiiiPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z7mysgemmiiiPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ae0f4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
.type _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf, @function
_Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7mysgemmiiiPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf, .-_Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
.globl _Z7mysgemmiiiPKfS0_Pf
.type _Z7mysgemmiiiPKfS0_Pf, @function
_Z7mysgemmiiiPKfS0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7mysgemmiiiPKfS0_Pf, .-_Z7mysgemmiiiPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "unsupported value of 'transa'\n"
.align 8
.LC1:
.string "unsupported value of 'transb'\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "unsupported value of alpha\n"
.LC6:
.string "unsupported value of beta\n"
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.type _Z10basicSgemmcciiifPKfiS0_ifPfi, @function
_Z10basicSgemmcciiifPKfiS0_ifPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
andl $-33, %edi
cmpb $78, %dil
jne .L26
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movq %r9, %r13
andl $-33, %esi
cmpb $78, %sil
jne .L27
subss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC3(%rip), %xmm0
ja .L15
movsd .LC4(%rip), %xmm2
comisd %xmm0, %xmm2
ja .L15
cvtss2sd %xmm1, %xmm1
comisd .LC3(%rip), %xmm1
ja .L18
movsd .LC4(%rip), %xmm0
comisd %xmm1, %xmm0
jbe .L24
.L18:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L15:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $16, 8(%rsp)
movl $16, 12(%rsp)
leal 15(%rcx), %eax
shrl $4, %eax
movl %eax, 20(%rsp)
leal 15(%rdx), %eax
shrl $4, %eax
movl %eax, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movq 104(%rsp), %r9
movq 88(%rsp), %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z35__device_stub__Z7mysgemmiiiPKfS0_PfiiiPKfS0_Pf
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .-_Z10basicSgemmcciiifPKfiS0_ifPfi
.section .rodata.str1.1
.LC7:
.string "_Z7mysgemmiiiPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mysgemmiiiPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -640172613
.long 1037794527
.align 8
.LC4:
.long -640172613
.long -1109689121
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z22__device_stub__mysgemmiiiPKfS0_Pf # -- Begin function _Z22__device_stub__mysgemmiiiPKfS0_Pf
.p2align 4, 0x90
.type _Z22__device_stub__mysgemmiiiPKfS0_Pf,@function
_Z22__device_stub__mysgemmiiiPKfS0_Pf: # @_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__mysgemmiiiPKfS0_Pf, .Lfunc_end0-_Z22__device_stub__mysgemmiiiPKfS0_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10basicSgemmcciiifPKfiS0_ifPfi
.LCPI1_0:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ddb7cdfd9d7bdbb # double 1.0E-10
.LCPI1_2:
.quad 0xbddb7cdfd9d7bdbb # double -1.0E-10
.text
.globl _Z10basicSgemmcciiifPKfiS0_ifPfi
.p2align 4, 0x90
.type _Z10basicSgemmcciiifPKfiS0_ifPfi,@function
_Z10basicSgemmcciiifPKfiS0_ifPfi: # @_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_startproc
# %bb.0:
andb $-33, %dil
cmpb $78, %dil
jne .LBB1_9
# %bb.1:
andb $-33, %sil
cmpb $78, %sil
jne .LBB1_10
# %bb.2:
addss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm2
ucomisd .LCPI1_1(%rip), %xmm2
ja .LBB1_11
# %bb.3:
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm2, %xmm0
ja .LBB1_11
# %bb.4:
cvtss2sd %xmm1, %xmm1
ucomisd .LCPI1_1(%rip), %xmm1
ja .LBB1_12
# %bb.5:
ucomisd %xmm1, %xmm0
ja .LBB1_12
# %bb.6:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %r14d
movl %r8d, %ebp
movq %r9, %r12
movq 232(%rsp), %r15
movq 216(%rsp), %r13
leal 15(%rbx), %eax
shrl $4, %eax
leal 15(%r14), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movl %r14d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r12, 88(%rsp)
movq %r13, 80(%rsp)
movq %r15, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7mysgemmiiiPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr.3, %edi
jmp puts@PLT # TAILCALL
.LBB1_10:
movl $.Lstr.2, %edi
jmp puts@PLT # TAILCALL
.LBB1_11:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.LBB1_12:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z10basicSgemmcciiifPKfiS0_ifPfi, .Lfunc_end1-_Z10basicSgemmcciiifPKfiS0_ifPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mysgemmiiiPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mysgemmiiiPKfS0_Pf,@object # @_Z7mysgemmiiiPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z7mysgemmiiiPKfS0_Pf
.p2align 3, 0x0
_Z7mysgemmiiiPKfS0_Pf:
.quad _Z22__device_stub__mysgemmiiiPKfS0_Pf
.size _Z7mysgemmiiiPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7mysgemmiiiPKfS0_Pf"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "unsupported value of beta"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "unsupported value of alpha"
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "unsupported value of 'transb'"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "unsupported value of 'transa'"
.size .Lstr.3, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mysgemmiiiPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void multiplication(int * A,int * B,int * C,int N,int M,int K){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if(row<N && col<K){//Si no me fui del arreglo
int sum=0;
for(int i=0;i<M;i++){
sum+=A[row*N+i]*B[i*M+col];
}
C[row*N+col]=sum;
}
} | code for sm_80
Function : _Z14multiplicationPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void multiplication(int * A,int * B,int * C,int N,int M,int K){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if(row<N && col<K){//Si no me fui del arreglo
int sum=0;
for(int i=0;i<M;i++){
sum+=A[row*N+i]*B[i*M+col];
}
C[row*N+col]=sum;
}
} | .file "tmpxft_000a40a8_00000000-6_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii
.type _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii, @function
_Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14multiplicationPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii, .-_Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii
.globl _Z14multiplicationPiS_S_iii
.type _Z14multiplicationPiS_S_iii, @function
_Z14multiplicationPiS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14multiplicationPiS_S_iii, .-_Z14multiplicationPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14multiplicationPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplicationPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void multiplication(int * A,int * B,int * C,int N,int M,int K){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if(row<N && col<K){//Si no me fui del arreglo
int sum=0;
for(int i=0;i<M;i++){
sum+=A[row*N+i]*B[i*M+col];
}
C[row*N+col]=sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiplication(int * A,int * B,int * C,int N,int M,int K){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if(row<N && col<K){//Si no me fui del arreglo
int sum=0;
for(int i=0;i<M;i++){
sum+=A[row*N+i]*B[i*M+col];
}
C[row*N+col]=sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiplication(int * A,int * B,int * C,int N,int M,int K){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if(row<N && col<K){//Si no me fui del arreglo
int sum=0;
for(int i=0;i<M;i++){
sum+=A[row*N+i]*B[i*M+col];
}
C[row*N+col]=sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplicationPiS_S_iii
.globl _Z14multiplicationPiS_S_iii
.p2align 8
.type _Z14multiplicationPiS_S_iii,@function
_Z14multiplicationPiS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s3
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, s2
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s4, s4, -1
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplicationPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplicationPiS_S_iii, .Lfunc_end0-_Z14multiplicationPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplicationPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14multiplicationPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void multiplication(int * A,int * B,int * C,int N,int M,int K){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
if(row<N && col<K){//Si no me fui del arreglo
int sum=0;
for(int i=0;i<M;i++){
sum+=A[row*N+i]*B[i*M+col];
}
C[row*N+col]=sum;
}
} | .text
.file "multiplication.hip"
.globl _Z29__device_stub__multiplicationPiS_S_iii # -- Begin function _Z29__device_stub__multiplicationPiS_S_iii
.p2align 4, 0x90
.type _Z29__device_stub__multiplicationPiS_S_iii,@function
_Z29__device_stub__multiplicationPiS_S_iii: # @_Z29__device_stub__multiplicationPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14multiplicationPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__multiplicationPiS_S_iii, .Lfunc_end0-_Z29__device_stub__multiplicationPiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplicationPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14multiplicationPiS_S_iii,@object # @_Z14multiplicationPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z14multiplicationPiS_S_iii
.p2align 3, 0x0
_Z14multiplicationPiS_S_iii:
.quad _Z29__device_stub__multiplicationPiS_S_iii
.size _Z14multiplicationPiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14multiplicationPiS_S_iii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplicationPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14multiplicationPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14multiplicationPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14multiplicationPiS_S_iii
.globl _Z14multiplicationPiS_S_iii
.p2align 8
.type _Z14multiplicationPiS_S_iii,@function
_Z14multiplicationPiS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s3
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, s2
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s4, s4, -1
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14multiplicationPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14multiplicationPiS_S_iii, .Lfunc_end0-_Z14multiplicationPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14multiplicationPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14multiplicationPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a40a8_00000000-6_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii
.type _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii, @function
_Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14multiplicationPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii, .-_Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii
.globl _Z14multiplicationPiS_S_iii
.type _Z14multiplicationPiS_S_iii, @function
_Z14multiplicationPiS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14multiplicationPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14multiplicationPiS_S_iii, .-_Z14multiplicationPiS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14multiplicationPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14multiplicationPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiplication.hip"
.globl _Z29__device_stub__multiplicationPiS_S_iii # -- Begin function _Z29__device_stub__multiplicationPiS_S_iii
.p2align 4, 0x90
.type _Z29__device_stub__multiplicationPiS_S_iii,@function
_Z29__device_stub__multiplicationPiS_S_iii: # @_Z29__device_stub__multiplicationPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14multiplicationPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z29__device_stub__multiplicationPiS_S_iii, .Lfunc_end0-_Z29__device_stub__multiplicationPiS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14multiplicationPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14multiplicationPiS_S_iii,@object # @_Z14multiplicationPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z14multiplicationPiS_S_iii
.p2align 3, 0x0
_Z14multiplicationPiS_S_iii:
.quad _Z29__device_stub__multiplicationPiS_S_iii
.size _Z14multiplicationPiS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14multiplicationPiS_S_iii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__multiplicationPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14multiplicationPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scan(float *input, float *output, float *aux, int len) {
//@@declaring shared memeory of size 2*inputSize
__shared__ float XY[2 * BLOCK_SIZE];
//@@X-axis block id
int bx = blockIdx.x;
//@@X-axis thread id
int tx = threadIdx.x;
int i = 2 * bx * blockDim.x + tx;
//@@ loading data from global memory to shared memory stage 1
if (i<len)
XY[tx] = input[i];
//@@ loading data from global memory to shared memory stage 2
if (i + blockDim.x<len)
XY[tx + blockDim.x] = input[i + blockDim.x];
//@@making sure that all threads in a block are done with loading data from global memory to shared memory
//@@before proceeding to the calculations phase
__syncthreads();
for (unsigned int stride = 1; stride <= BLOCK_SIZE; stride *= 2){
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index < 2 * BLOCK_SIZE)
XY[index] += XY[index - stride];
}
for (int stride = BLOCK_SIZE / 2; stride > 0; stride /= 2) {
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index + stride < 2 * BLOCK_SIZE)
XY[index + stride] += XY[index];
}
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
if (i < len)
output[i] = XY[tx];
if (i + blockDim.x < len)
output[i + blockDim.x] = XY[tx + blockDim.x];
//@@storing the block sum to the aux array
if (aux != NULL && tx == 0)
aux[bx] = XY[2 * blockDim.x - 1];
} | code for sm_80
Function : _Z4scanPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x001fc800078e00ff */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x002fca00078e0203 */
/*0060*/ IADD3 R2, R4.reuse, c[0x0][0x0], RZ ; /* 0x0000000004027a10 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f26270 */
/*0080*/ ISETP.GE.U32.AND P2, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fd60003f46070 */
/*0090*/ @!P1 MOV R9, 0x4 ; /* 0x0000000400099802 */
/* 0x000fe40000000f00 */
/*00a0*/ @!P2 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0ba424 */
/* 0x000fc600078e00ff */
/*00b0*/ @!P1 IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004089625 */
/* 0x000fc800078e0209 */
/*00c0*/ @!P2 IMAD.WIDE.U32 R10, R2, R11, c[0x0][0x160] ; /* 0x00005800020aa625 */
/* 0x000fe400078e000b */
/*00d0*/ @!P1 LDG.E R8, [R8.64] ; /* 0x0000000608089981 */
/* 0x0000a8000c1e1900 */
/*00e0*/ @!P2 LDG.E R10, [R10.64] ; /* 0x000000060a0aa981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ IADD3 R5, R3.reuse, c[0x0][0x0], RZ ; /* 0x0000000003057a10 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R6, R3.reuse, 0x2, RZ ; /* 0x0000000203067824 */
/* 0x040fe200078e00ff */
/*0110*/ SHF.L.U32 R7, R3, 0x2, RZ ; /* 0x0000000203077819 */
/* 0x000fc800000006ff */
/*0120*/ ISETP.GT.AND P3, PT, R6.reuse, 0x3fe, PT ; /* 0x000003fe0600780c */
/* 0x040fe40003f64270 */
/*0130*/ IADD3 R9, R7, 0x3, RZ ; /* 0x0000000307097810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IADD3 R7, R6.reuse, 0x2, RZ ; /* 0x0000000206077810 */
/* 0x040fe40007ffe0ff */
/*0150*/ ISETP.GT.AND P0, PT, R9, 0x3ff, PT ; /* 0x000003ff0900780c */
/* 0x000fe40003f04270 */
/*0160*/ SHF.L.U32 R21, R6, 0xb, RZ ; /* 0x0000000b06157819 */
/* 0x000fe200000006ff */
/*0170*/ @!P1 STS [R3.X4], R8 ; /* 0x0000000803009388 */
/* 0x0041e80000004800 */
/*0180*/ @!P2 STS [R5.X4], R10 ; /* 0x0000000a0500a388 */
/* 0x008fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ IMAD.SHL.U32 R8, R7, 0x2, RZ ; /* 0x0000000207087824 */
/* 0x001fc800078e00ff */
/*01b0*/ IMAD.IADD R16, R8, 0x1, R9 ; /* 0x0000000108107824 */
/* 0x000fe200078e0209 */
/*01c0*/ SHF.L.U32 R9, R7, 0x2, RZ ; /* 0x0000000207097819 */
/* 0x000fe200000006ff */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @!P3 LDS.64 R12, [R3.X8] ; /* 0x00000000030cb984 */
/* 0x000e240000008a00 */
/*01f0*/ @!P3 FADD R12, R12, R13 ; /* 0x0000000d0c0cb221 */
/* 0x001fca0000000000 */
/*0200*/ @!P3 STS [R3.X8+0x4], R12 ; /* 0x0000040c0300b388 */
/* 0x000fe80000008800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P3, PT, R16.reuse, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x040fe20003f64270 */
/*0230*/ IMAD.IADD R16, R16, 0x1, R9 ; /* 0x0000000110107824 */
/* 0x000fc800078e0209 */
/*0240*/ @!P0 LDS R10, [R7.X8+-0xc] ; /* 0xfffff400070a8984 */
/* 0x000fe80000008800 */
/*0250*/ @!P0 LDS R11, [R7.X8+-0x4] ; /* 0xfffffc00070b8984 */
/* 0x000e240000008800 */
/*0260*/ @!P0 FADD R14, R10, R11 ; /* 0x0000000b0a0e8221 */
/* 0x001fca0000000000 */
/*0270*/ @!P0 STS [R7.X8+-0x4], R14 ; /* 0xfffffc0e07008388 */
/* 0x000fe80000008800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GT.AND P0, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fca0003f04270 */
/*02a0*/ @!P3 LDS R10, [R7.X16+-0x14] ; /* 0xffffec00070ab984 */
/* 0x000fe8000000c800 */
/*02b0*/ @!P3 LDS R11, [R7.X16+-0x4] ; /* 0xfffffc00070bb984 */
/* 0x000e24000000c800 */
/*02c0*/ @!P3 FADD R16, R10, R11 ; /* 0x0000000b0a10b221 */
/* 0x001fe20000000000 */
/*02d0*/ SHF.L.U32 R11, R7.reuse, 0x4, RZ ; /* 0x00000004070b7819 */
/* 0x040fe200000006ff */
/*02e0*/ IMAD.SHL.U32 R10, R7, 0x20, RZ ; /* 0x00000020070a7824 */
/* 0x000fc600078e00ff */
/*02f0*/ @!P3 STS [R7.X16+-0x4], R16 ; /* 0xfffffc100700b388 */
/* 0x0001e2000000c800 */
/*0300*/ IADD3 R14, R11, -0x1, RZ ; /* 0xffffffff0b0e7810 */
/* 0x000fc60007ffe0ff */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.AND P3, PT, R14, 0x3ff, PT ; /* 0x000003ff0e00780c */
/* 0x000fe40003f64270 */
/*0330*/ IADD3 R16, R10, -0x1, RZ ; /* 0xffffffff0a107810 */
/* 0x001fc60007ffe0ff */
/*0340*/ @!P0 LDS R12, [R10+-0x24] ; /* 0xffffdc000a0c8984 */
/* 0x000fe80000000800 */
/*0350*/ @!P0 LDS R13, [R10+-0x4] ; /* 0xfffffc000a0d8984 */
/* 0x000e240000000800 */
/*0360*/ @!P0 FADD R15, R12, R13 ; /* 0x0000000d0c0f8221 */
/* 0x001fe40000000000 */
/*0370*/ IMAD.SHL.U32 R12, R7, 0x40, RZ ; /* 0x00000040070c7824 */
/* 0x000fc600078e00ff */
/*0380*/ @!P0 STS [R10+-0x4], R15 ; /* 0xfffffc0f0a008388 */
/* 0x000fe80000000800 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.GT.AND P0, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fe40003f04270 */
/*03b0*/ IADD3 R16, R12, -0x1, RZ ; /* 0xffffffff0c107810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ @!P3 LDS R13, [R12+-0x44] ; /* 0xffffbc000c0db984 */
/* 0x000fe80000000800 */
/*03d0*/ @!P3 LDS R14, [R12+-0x4] ; /* 0xfffffc000c0eb984 */
/* 0x000e240000000800 */
/*03e0*/ @!P3 FADD R17, R13, R14 ; /* 0x0000000e0d11b221 */
/* 0x001fe40000000000 */
/*03f0*/ IMAD.SHL.U32 R13, R7, 0x80, RZ ; /* 0x00000080070d7824 */
/* 0x000fc600078e00ff */
/*0400*/ @!P3 STS [R12+-0x4], R17 ; /* 0xfffffc110c00b388 */
/* 0x0001e80000000800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ ISETP.GT.AND P3, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fe40003f64270 */
/*0430*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x001fc60007ffe0ff */
/*0440*/ @!P0 LDS R14, [R13+-0x84] ; /* 0xffff7c000d0e8984 */
/* 0x000fe80000000800 */
/*0450*/ @!P0 LDS R15, [R13+-0x4] ; /* 0xfffffc000d0f8984 */
/* 0x000e240000000800 */
/*0460*/ @!P0 FADD R16, R14, R15 ; /* 0x0000000f0e108221 */
/* 0x001fe20000000000 */
/*0470*/ SHF.L.U32 R14, R7, 0x8, RZ ; /* 0x00000008070e7819 */
/* 0x000fc800000006ff */
/*0480*/ @!P0 STS [R13+-0x4], R16 ; /* 0xfffffc100d008388 */
/* 0x0001e80000000800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04a0*/ ISETP.GT.AND P0, PT, R17, 0x3ff, PT ; /* 0x000003ff1100780c */
/* 0x000fe40003f04270 */
/*04b0*/ IADD3 R16, R14, -0x1, RZ ; /* 0xffffffff0e107810 */
/* 0x001fc60007ffe0ff */
/*04c0*/ @!P3 LDS R15, [R14+-0x104] ; /* 0xfffefc000e0fb984 */
/* 0x000fe80000000800 */
/*04d0*/ @!P3 LDS R18, [R14+-0x4] ; /* 0xfffffc000e12b984 */
/* 0x000e240000000800 */
/*04e0*/ @!P3 FADD R17, R15, R18 ; /* 0x000000120f11b221 */
/* 0x001fe40000000000 */
/*04f0*/ IMAD.SHL.U32 R15, R7, 0x200, RZ ; /* 0x00000200070f7824 */
/* 0x000fc600078e00ff */
/*0500*/ @!P3 STS [R14+-0x4], R17 ; /* 0xfffffc110e00b388 */
/* 0x0001e80000000800 */
/*0510*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0520*/ ISETP.GT.AND P3, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fe20003f64270 */
/*0530*/ IMAD.SHL.U32 R16, R7, 0x400, RZ ; /* 0x0000040007107824 */
/* 0x000fe200078e00ff */
/*0540*/ IADD3 R17, R15, -0x1, RZ ; /* 0xffffffff0f117810 */
/* 0x001fc60007ffe0ff */
/*0550*/ @!P0 LDS R18, [R15+-0x204] ; /* 0xfffdfc000f128984 */
/* 0x000fe80000000800 */
/*0560*/ @!P0 LDS R19, [R15+-0x4] ; /* 0xfffffc000f138984 */
/* 0x000e240000000800 */
/*0570*/ @!P0 FADD R18, R18, R19 ; /* 0x0000001312128221 */
/* 0x001fca0000000000 */
/*0580*/ @!P0 STS [R15+-0x4], R18 ; /* 0xfffffc120f008388 */
/* 0x000fe80000000800 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05a0*/ ISETP.GT.AND P0, PT, R17, 0x3ff, PT ; /* 0x000003ff1100780c */
/* 0x000fca0003f04270 */
/*05b0*/ @!P3 LDS R19, [R16+-0x404] ; /* 0xfffbfc001013b984 */
/* 0x000fe80000000800 */
/*05c0*/ @!P3 LDS R20, [R16+-0x4] ; /* 0xfffffc001014b984 */
/* 0x000e240000000800 */
/*05d0*/ @!P3 FADD R19, R19, R20 ; /* 0x000000141313b221 */
/* 0x001fca0000000000 */
/*05e0*/ @!P3 STS [R16+-0x4], R19 ; /* 0xfffffc131000b388 */
/* 0x000fe80000000800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0600*/ ISETP.GT.AND P3, PT, R14, 0x300, PT ; /* 0x000003000e00780c */
/* 0x000fca0003f64270 */
/*0610*/ @!P0 LDS R6, [R21+0xffc] ; /* 0x000ffc0015068984 */
/* 0x000fe80000000800 */
/*0620*/ @!P0 LDS R17, [R21+0x7fc] ; /* 0x0007fc0015118984 */
/* 0x000e240000000800 */
/*0630*/ @!P0 FADD R6, R6, R17 ; /* 0x0000001106068221 */
/* 0x001fca0000000000 */
/*0640*/ @!P0 STS [R21+0xffc], R6 ; /* 0x000ffc0615008388 */
/* 0x000fe80000000800 */
/*0650*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0660*/ ISETP.GT.AND P0, PT, R13, 0x380, PT ; /* 0x000003800d00780c */
/* 0x000fca0003f04270 */
/*0670*/ @!P3 LDS R17, [R16+0x3fc] ; /* 0x0003fc001011b984 */
/* 0x000fe80000000800 */
/*0680*/ @!P3 LDS R18, [R16+-0x4] ; /* 0xfffffc001012b984 */
/* 0x000e240000000800 */
/*0690*/ @!P3 FADD R17, R17, R18 ; /* 0x000000121111b221 */
/* 0x001fca0000000000 */
/*06a0*/ @!P3 STS [R16+0x3fc], R17 ; /* 0x0003fc111000b388 */
/* 0x000fe80000000800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06c0*/ ISETP.GT.AND P3, PT, R12, 0x3c0, PT ; /* 0x000003c00c00780c */
/* 0x000fca0003f64270 */
/*06d0*/ @!P0 LDS R18, [R15+0x1fc] ; /* 0x0001fc000f128984 */
/* 0x000fe80000000800 */
/*06e0*/ @!P0 LDS R19, [R15+-0x4] ; /* 0xfffffc000f138984 */
/* 0x000e240000000800 */
/*06f0*/ @!P0 FADD R18, R18, R19 ; /* 0x0000001312128221 */
/* 0x001fca0000000000 */
/*0700*/ @!P0 STS [R15+0x1fc], R18 ; /* 0x0001fc120f008388 */
/* 0x000fe80000000800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ ISETP.GT.AND P0, PT, R10, 0x3e0, PT ; /* 0x000003e00a00780c */
/* 0x000fca0003f04270 */
/*0730*/ @!P3 LDS R6, [R14+0xfc] ; /* 0x0000fc000e06b984 */
/* 0x000fe80000000800 */
/*0740*/ @!P3 LDS R19, [R14+-0x4] ; /* 0xfffffc000e13b984 */
/* 0x000e240000000800 */
/*0750*/ @!P3 FADD R19, R6, R19 ; /* 0x000000130613b221 */
/* 0x001fca0000000000 */
/*0760*/ @!P3 STS [R14+0xfc], R19 ; /* 0x0000fc130e00b388 */
/* 0x000fe80000000800 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0780*/ ISETP.GT.AND P3, PT, R11, 0x3f0, PT ; /* 0x000003f00b00780c */
/* 0x000fca0003f64270 */
/*0790*/ @!P0 LDS R6, [R13+0x7c] ; /* 0x00007c000d068984 */
/* 0x000fe80000000800 */
/*07a0*/ @!P0 LDS R17, [R13+-0x4] ; /* 0xfffffc000d118984 */
/* 0x000e240000000800 */
/*07b0*/ @!P0 FADD R16, R6, R17 ; /* 0x0000001106108221 */
/* 0x001fe40000000000 */
/*07c0*/ IMAD.SHL.U32 R6, R7, 0x8, RZ ; /* 0x0000000807067824 */
/* 0x000fc600078e00ff */
/*07d0*/ @!P0 STS [R13+0x7c], R16 ; /* 0x00007c100d008388 */
/* 0x000fe80000000800 */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07f0*/ ISETP.GT.AND P0, PT, R6, 0x3f8, PT ; /* 0x000003f80600780c */
/* 0x000fca0003f04270 */
/*0800*/ @!P3 LDS R11, [R12+0x3c] ; /* 0x00003c000c0bb984 */
/* 0x000fe80000000800 */
/*0810*/ @!P3 LDS R18, [R12+-0x4] ; /* 0xfffffc000c12b984 */
/* 0x000e240000000800 */
/*0820*/ @!P3 FADD R11, R11, R18 ; /* 0x000000120b0bb221 */
/* 0x001fca0000000000 */
/*0830*/ @!P3 STS [R12+0x3c], R11 ; /* 0x00003c0b0c00b388 */
/* 0x000fe80000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0850*/ ISETP.GT.AND P3, PT, R9, 0x3fc, PT ; /* 0x000003fc0900780c */
/* 0x000fca0003f64270 */
/*0860*/ @!P0 LDS R6, [R10+0x1c] ; /* 0x00001c000a068984 */
/* 0x000fe80000000800 */
/*0870*/ @!P0 LDS R15, [R10+-0x4] ; /* 0xfffffc000a0f8984 */
/* 0x000e240000000800 */
/*0880*/ @!P0 FADD R15, R6, R15 ; /* 0x0000000f060f8221 */
/* 0x001fca0000000000 */
/*0890*/ @!P0 STS [R10+0x1c], R15 ; /* 0x00001c0f0a008388 */
/* 0x000fe80000000800 */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08b0*/ ISETP.GT.AND P0, PT, R8, 0x3fe, PT ; /* 0x000003fe0800780c */
/* 0x000fca0003f04270 */
/*08c0*/ @!P3 LDS R6, [R7.X16+0xc] ; /* 0x00000c000706b984 */
/* 0x000fe8000000c800 */
/*08d0*/ @!P3 LDS R9, [R7.X16+-0x4] ; /* 0xfffffc000709b984 */
/* 0x000e24000000c800 */
/*08e0*/ @!P3 FADD R6, R6, R9 ; /* 0x000000090606b221 */
/* 0x001fca0000000000 */
/*08f0*/ @!P3 STS [R7.X16+0xc], R6 ; /* 0x00000c060700b388 */
/* 0x000fe8000000c800 */
/*0900*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0910*/ ISETP.GT.AND P3, PT, R7, 0x3ff, PT ; /* 0x000003ff0700780c */
/* 0x000fca0003f64270 */
/*0920*/ @!P0 LDS R8, [R7.X8+0x4] ; /* 0x0000040007088984 */
/* 0x000fe80000008800 */
/*0930*/ @!P0 LDS R9, [R7.X8+-0x4] ; /* 0xfffffc0007098984 */
/* 0x000e240000008800 */
/*0940*/ @!P0 FADD R8, R8, R9 ; /* 0x0000000908088221 */
/* 0x001fca0000000000 */
/*0950*/ @!P0 STS [R7.X8+0x4], R8 ; /* 0x0000040807008388 */
/* 0x0001e80000008800 */
/*0960*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0970*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc80003f05070 */
/*0980*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f05300 */
/*0990*/ @!P1 MOV R7, 0x4 ; /* 0x0000000400079802 */
/* 0x001fe40000000f00 */
/*09a0*/ ISETP.NE.OR P0, PT, R3, RZ, !P0 ; /* 0x000000ff0300720c */
/* 0x000fc60004705670 */
/*09b0*/ @!P1 IMAD.WIDE R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004069625 */
/* 0x000fe200078e0207 */
/*09c0*/ @!P3 LDS R9, [R3.X8+0x8] ; /* 0x000008000309b984 */
/* 0x000fe80000008800 */
/*09d0*/ @!P3 LDS R10, [R3.X8+0x4] ; /* 0x00000400030ab984 */
/* 0x000e240000008800 */
/*09e0*/ @!P3 FADD R10, R9, R10 ; /* 0x0000000a090ab221 */
/* 0x001fe40000000000 */
/*09f0*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff09a424 */
/* 0x000fc600078e00ff */
/*0a00*/ @!P3 STS [R3.X8+0x8], R10 ; /* 0x0000080a0300b388 */
/* 0x000fe20000008800 */
/*0a10*/ @!P2 IMAD.WIDE.U32 R8, R2, R9, c[0x0][0x168] ; /* 0x00005a000208a625 */
/* 0x000fc600078e0009 */
/*0a20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a30*/ @!P1 LDS R11, [R3.X4] ; /* 0x00000000030b9984 */
/* 0x000e280000004800 */
/*0a40*/ @!P2 LDS R5, [R5.X4] ; /* 0x000000000505a984 */
/* 0x000e680000004800 */
/*0a50*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0011e8000c101906 */
/*0a60*/ @!P2 STG.E [R8.64], R5 ; /* 0x000000050800a986 */
/* 0x0021e2000c101906 */
/*0a70*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a80*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0a90*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0aa0*/ ULEA UR4, UR4, 0xfffffffc, 0x3 ; /* 0xfffffffc04047891 */
/* 0x000fd2000f8e183f */
/*0ab0*/ LDS R5, [UR4] ; /* 0x00000004ff057984 */
/* 0x001e220008000800 */
/*0ac0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0ad0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scan(float *input, float *output, float *aux, int len) {
//@@declaring shared memeory of size 2*inputSize
__shared__ float XY[2 * BLOCK_SIZE];
//@@X-axis block id
int bx = blockIdx.x;
//@@X-axis thread id
int tx = threadIdx.x;
int i = 2 * bx * blockDim.x + tx;
//@@ loading data from global memory to shared memory stage 1
if (i<len)
XY[tx] = input[i];
//@@ loading data from global memory to shared memory stage 2
if (i + blockDim.x<len)
XY[tx + blockDim.x] = input[i + blockDim.x];
//@@making sure that all threads in a block are done with loading data from global memory to shared memory
//@@before proceeding to the calculations phase
__syncthreads();
for (unsigned int stride = 1; stride <= BLOCK_SIZE; stride *= 2){
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index < 2 * BLOCK_SIZE)
XY[index] += XY[index - stride];
}
for (int stride = BLOCK_SIZE / 2; stride > 0; stride /= 2) {
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index + stride < 2 * BLOCK_SIZE)
XY[index + stride] += XY[index];
}
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
if (i < len)
output[i] = XY[tx];
if (i + blockDim.x < len)
output[i + blockDim.x] = XY[tx + blockDim.x];
//@@storing the block sum to the aux array
if (aux != NULL && tx == 0)
aux[bx] = XY[2 * blockDim.x - 1];
} | .file "tmpxft_000e4e09_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4scanPfS_S_iPfS_S_i
.type _Z28__device_stub__Z4scanPfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4scanPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4scanPfS_S_iPfS_S_i, .-_Z28__device_stub__Z4scanPfS_S_iPfS_S_i
.globl _Z4scanPfS_S_i
.type _Z4scanPfS_S_i, @function
_Z4scanPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4scanPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4scanPfS_S_i, .-_Z4scanPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4scanPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scan(float *input, float *output, float *aux, int len) {
//@@declaring shared memeory of size 2*inputSize
__shared__ float XY[2 * BLOCK_SIZE];
//@@X-axis block id
int bx = blockIdx.x;
//@@X-axis thread id
int tx = threadIdx.x;
int i = 2 * bx * blockDim.x + tx;
//@@ loading data from global memory to shared memory stage 1
if (i<len)
XY[tx] = input[i];
//@@ loading data from global memory to shared memory stage 2
if (i + blockDim.x<len)
XY[tx + blockDim.x] = input[i + blockDim.x];
//@@making sure that all threads in a block are done with loading data from global memory to shared memory
//@@before proceeding to the calculations phase
__syncthreads();
for (unsigned int stride = 1; stride <= BLOCK_SIZE; stride *= 2){
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index < 2 * BLOCK_SIZE)
XY[index] += XY[index - stride];
}
for (int stride = BLOCK_SIZE / 2; stride > 0; stride /= 2) {
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index + stride < 2 * BLOCK_SIZE)
XY[index + stride] += XY[index];
}
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
if (i < len)
output[i] = XY[tx];
if (i + blockDim.x < len)
output[i + blockDim.x] = XY[tx + blockDim.x];
//@@storing the block sum to the aux array
if (aux != NULL && tx == 0)
aux[bx] = XY[2 * blockDim.x - 1];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float *input, float *output, float *aux, int len) {
//@@declaring shared memeory of size 2*inputSize
__shared__ float XY[2 * BLOCK_SIZE];
//@@X-axis block id
int bx = blockIdx.x;
//@@X-axis thread id
int tx = threadIdx.x;
int i = 2 * bx * blockDim.x + tx;
//@@ loading data from global memory to shared memory stage 1
if (i<len)
XY[tx] = input[i];
//@@ loading data from global memory to shared memory stage 2
if (i + blockDim.x<len)
XY[tx + blockDim.x] = input[i + blockDim.x];
//@@making sure that all threads in a block are done with loading data from global memory to shared memory
//@@before proceeding to the calculations phase
__syncthreads();
for (unsigned int stride = 1; stride <= BLOCK_SIZE; stride *= 2){
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index < 2 * BLOCK_SIZE)
XY[index] += XY[index - stride];
}
for (int stride = BLOCK_SIZE / 2; stride > 0; stride /= 2) {
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index + stride < 2 * BLOCK_SIZE)
XY[index + stride] += XY[index];
}
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
if (i < len)
output[i] = XY[tx];
if (i + blockDim.x < len)
output[i + blockDim.x] = XY[tx + blockDim.x];
//@@storing the block sum to the aux array
if (aux != NULL && tx == 0)
aux[bx] = XY[2 * blockDim.x - 1];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float *input, float *output, float *aux, int len) {
//@@declaring shared memeory of size 2*inputSize
__shared__ float XY[2 * BLOCK_SIZE];
//@@X-axis block id
int bx = blockIdx.x;
//@@X-axis thread id
int tx = threadIdx.x;
int i = 2 * bx * blockDim.x + tx;
//@@ loading data from global memory to shared memory stage 1
if (i<len)
XY[tx] = input[i];
//@@ loading data from global memory to shared memory stage 2
if (i + blockDim.x<len)
XY[tx + blockDim.x] = input[i + blockDim.x];
//@@making sure that all threads in a block are done with loading data from global memory to shared memory
//@@before proceeding to the calculations phase
__syncthreads();
for (unsigned int stride = 1; stride <= BLOCK_SIZE; stride *= 2){
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index < 2 * BLOCK_SIZE)
XY[index] += XY[index - stride];
}
for (int stride = BLOCK_SIZE / 2; stride > 0; stride /= 2) {
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index + stride < 2 * BLOCK_SIZE)
XY[index + stride] += XY[index];
}
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
if (i < len)
output[i] = XY[tx];
if (i + blockDim.x < len)
output[i + blockDim.x] = XY[tx + blockDim.x];
//@@storing the block sum to the aux array
if (aux != NULL && tx == 0)
aux[bx] = XY[2 * blockDim.x - 1];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPfS_S_i
.globl _Z4scanPfS_S_i
.p2align 8
.type _Z4scanPfS_S_i,@function
_Z4scanPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s5
v_lshl_add_u32 v1, s2, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v3, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v3
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s3, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s3, s7, v5, s3
global_load_b32 v4, v[4:5], off
v_add_lshl_u32 v5, v0, s5, 2
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v4, 1, v0
s_mov_b32 s6, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s3, s6, 1
s_cmpk_gt_u32 s6, 0x100
s_mov_b32 s6, s3
s_cbranch_scc1 .LBB0_8
.LBB0_6:
v_mul_lo_u32 v5, s6, v4
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x201, v5
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v5, v5, 1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s6, v5
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v4, v0, 1, 2
s_movk_i32 s6, 0x100
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s3, s6, 1
s_cmp_lt_u32 s6, 2
s_mov_b32 s6, s3
s_cbranch_scc1 .LBB0_12
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v6, v4, s6, -1
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v5, s6, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400, v5
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_9
.LBB0_12:
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v4, 2, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
ds_load_b32 v4, v4
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v4, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
v_add_lshl_u32 v1, v0, s5, 2
v_mov_b32_e32 v4, 0
ds_load_b32 v5, v1
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v5, off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u64 s[0:1], 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_lshl_b32 s2, s5, 3
s_ashr_i32 s5, s4, 31
s_add_i32 s2, s2, -4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
s_lshl_b64 s[2:3], s[4:5], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPfS_S_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPfS_S_i, .Lfunc_end0-_Z4scanPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4scanPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float *input, float *output, float *aux, int len) {
//@@declaring shared memeory of size 2*inputSize
__shared__ float XY[2 * BLOCK_SIZE];
//@@X-axis block id
int bx = blockIdx.x;
//@@X-axis thread id
int tx = threadIdx.x;
int i = 2 * bx * blockDim.x + tx;
//@@ loading data from global memory to shared memory stage 1
if (i<len)
XY[tx] = input[i];
//@@ loading data from global memory to shared memory stage 2
if (i + blockDim.x<len)
XY[tx + blockDim.x] = input[i + blockDim.x];
//@@making sure that all threads in a block are done with loading data from global memory to shared memory
//@@before proceeding to the calculations phase
__syncthreads();
for (unsigned int stride = 1; stride <= BLOCK_SIZE; stride *= 2){
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index < 2 * BLOCK_SIZE)
XY[index] += XY[index - stride];
}
for (int stride = BLOCK_SIZE / 2; stride > 0; stride /= 2) {
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
int index = (tx + 1)*stride * 2 - 1;
if (index + stride < 2 * BLOCK_SIZE)
XY[index + stride] += XY[index];
}
//@@making sure that all threads in a block are done with previous step before starting the next
__syncthreads();
if (i < len)
output[i] = XY[tx];
if (i + blockDim.x < len)
output[i + blockDim.x] = XY[tx + blockDim.x];
//@@storing the block sum to the aux array
if (aux != NULL && tx == 0)
aux[bx] = XY[2 * blockDim.x - 1];
} | .text
.file "scan.hip"
.globl _Z19__device_stub__scanPfS_S_i # -- Begin function _Z19__device_stub__scanPfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPfS_S_i,@function
_Z19__device_stub__scanPfS_S_i: # @_Z19__device_stub__scanPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPfS_S_i, .Lfunc_end0-_Z19__device_stub__scanPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPfS_S_i,@object # @_Z4scanPfS_S_i
.section .rodata,"a",@progbits
.globl _Z4scanPfS_S_i
.p2align 3, 0x0
_Z4scanPfS_S_i:
.quad _Z19__device_stub__scanPfS_S_i
.size _Z4scanPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4scanPfS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4scanPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.SHL.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047824 */
/* 0x001fc800078e00ff */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x002fca00078e0203 */
/*0060*/ IADD3 R2, R4.reuse, c[0x0][0x0], RZ ; /* 0x0000000004027a10 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe40003f26270 */
/*0080*/ ISETP.GE.U32.AND P2, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fd60003f46070 */
/*0090*/ @!P1 MOV R9, 0x4 ; /* 0x0000000400099802 */
/* 0x000fe40000000f00 */
/*00a0*/ @!P2 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0ba424 */
/* 0x000fc600078e00ff */
/*00b0*/ @!P1 IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004089625 */
/* 0x000fc800078e0209 */
/*00c0*/ @!P2 IMAD.WIDE.U32 R10, R2, R11, c[0x0][0x160] ; /* 0x00005800020aa625 */
/* 0x000fe400078e000b */
/*00d0*/ @!P1 LDG.E R8, [R8.64] ; /* 0x0000000608089981 */
/* 0x0000a8000c1e1900 */
/*00e0*/ @!P2 LDG.E R10, [R10.64] ; /* 0x000000060a0aa981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ IADD3 R5, R3.reuse, c[0x0][0x0], RZ ; /* 0x0000000003057a10 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R6, R3.reuse, 0x2, RZ ; /* 0x0000000203067824 */
/* 0x040fe200078e00ff */
/*0110*/ SHF.L.U32 R7, R3, 0x2, RZ ; /* 0x0000000203077819 */
/* 0x000fc800000006ff */
/*0120*/ ISETP.GT.AND P3, PT, R6.reuse, 0x3fe, PT ; /* 0x000003fe0600780c */
/* 0x040fe40003f64270 */
/*0130*/ IADD3 R9, R7, 0x3, RZ ; /* 0x0000000307097810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IADD3 R7, R6.reuse, 0x2, RZ ; /* 0x0000000206077810 */
/* 0x040fe40007ffe0ff */
/*0150*/ ISETP.GT.AND P0, PT, R9, 0x3ff, PT ; /* 0x000003ff0900780c */
/* 0x000fe40003f04270 */
/*0160*/ SHF.L.U32 R21, R6, 0xb, RZ ; /* 0x0000000b06157819 */
/* 0x000fe200000006ff */
/*0170*/ @!P1 STS [R3.X4], R8 ; /* 0x0000000803009388 */
/* 0x0041e80000004800 */
/*0180*/ @!P2 STS [R5.X4], R10 ; /* 0x0000000a0500a388 */
/* 0x008fe80000004800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ IMAD.SHL.U32 R8, R7, 0x2, RZ ; /* 0x0000000207087824 */
/* 0x001fc800078e00ff */
/*01b0*/ IMAD.IADD R16, R8, 0x1, R9 ; /* 0x0000000108107824 */
/* 0x000fe200078e0209 */
/*01c0*/ SHF.L.U32 R9, R7, 0x2, RZ ; /* 0x0000000207097819 */
/* 0x000fe200000006ff */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @!P3 LDS.64 R12, [R3.X8] ; /* 0x00000000030cb984 */
/* 0x000e240000008a00 */
/*01f0*/ @!P3 FADD R12, R12, R13 ; /* 0x0000000d0c0cb221 */
/* 0x001fca0000000000 */
/*0200*/ @!P3 STS [R3.X8+0x4], R12 ; /* 0x0000040c0300b388 */
/* 0x000fe80000008800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P3, PT, R16.reuse, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x040fe20003f64270 */
/*0230*/ IMAD.IADD R16, R16, 0x1, R9 ; /* 0x0000000110107824 */
/* 0x000fc800078e0209 */
/*0240*/ @!P0 LDS R10, [R7.X8+-0xc] ; /* 0xfffff400070a8984 */
/* 0x000fe80000008800 */
/*0250*/ @!P0 LDS R11, [R7.X8+-0x4] ; /* 0xfffffc00070b8984 */
/* 0x000e240000008800 */
/*0260*/ @!P0 FADD R14, R10, R11 ; /* 0x0000000b0a0e8221 */
/* 0x001fca0000000000 */
/*0270*/ @!P0 STS [R7.X8+-0x4], R14 ; /* 0xfffffc0e07008388 */
/* 0x000fe80000008800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GT.AND P0, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fca0003f04270 */
/*02a0*/ @!P3 LDS R10, [R7.X16+-0x14] ; /* 0xffffec00070ab984 */
/* 0x000fe8000000c800 */
/*02b0*/ @!P3 LDS R11, [R7.X16+-0x4] ; /* 0xfffffc00070bb984 */
/* 0x000e24000000c800 */
/*02c0*/ @!P3 FADD R16, R10, R11 ; /* 0x0000000b0a10b221 */
/* 0x001fe20000000000 */
/*02d0*/ SHF.L.U32 R11, R7.reuse, 0x4, RZ ; /* 0x00000004070b7819 */
/* 0x040fe200000006ff */
/*02e0*/ IMAD.SHL.U32 R10, R7, 0x20, RZ ; /* 0x00000020070a7824 */
/* 0x000fc600078e00ff */
/*02f0*/ @!P3 STS [R7.X16+-0x4], R16 ; /* 0xfffffc100700b388 */
/* 0x0001e2000000c800 */
/*0300*/ IADD3 R14, R11, -0x1, RZ ; /* 0xffffffff0b0e7810 */
/* 0x000fc60007ffe0ff */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GT.AND P3, PT, R14, 0x3ff, PT ; /* 0x000003ff0e00780c */
/* 0x000fe40003f64270 */
/*0330*/ IADD3 R16, R10, -0x1, RZ ; /* 0xffffffff0a107810 */
/* 0x001fc60007ffe0ff */
/*0340*/ @!P0 LDS R12, [R10+-0x24] ; /* 0xffffdc000a0c8984 */
/* 0x000fe80000000800 */
/*0350*/ @!P0 LDS R13, [R10+-0x4] ; /* 0xfffffc000a0d8984 */
/* 0x000e240000000800 */
/*0360*/ @!P0 FADD R15, R12, R13 ; /* 0x0000000d0c0f8221 */
/* 0x001fe40000000000 */
/*0370*/ IMAD.SHL.U32 R12, R7, 0x40, RZ ; /* 0x00000040070c7824 */
/* 0x000fc600078e00ff */
/*0380*/ @!P0 STS [R10+-0x4], R15 ; /* 0xfffffc0f0a008388 */
/* 0x000fe80000000800 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03a0*/ ISETP.GT.AND P0, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fe40003f04270 */
/*03b0*/ IADD3 R16, R12, -0x1, RZ ; /* 0xffffffff0c107810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ @!P3 LDS R13, [R12+-0x44] ; /* 0xffffbc000c0db984 */
/* 0x000fe80000000800 */
/*03d0*/ @!P3 LDS R14, [R12+-0x4] ; /* 0xfffffc000c0eb984 */
/* 0x000e240000000800 */
/*03e0*/ @!P3 FADD R17, R13, R14 ; /* 0x0000000e0d11b221 */
/* 0x001fe40000000000 */
/*03f0*/ IMAD.SHL.U32 R13, R7, 0x80, RZ ; /* 0x00000080070d7824 */
/* 0x000fc600078e00ff */
/*0400*/ @!P3 STS [R12+-0x4], R17 ; /* 0xfffffc110c00b388 */
/* 0x0001e80000000800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ ISETP.GT.AND P3, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fe40003f64270 */
/*0430*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x001fc60007ffe0ff */
/*0440*/ @!P0 LDS R14, [R13+-0x84] ; /* 0xffff7c000d0e8984 */
/* 0x000fe80000000800 */
/*0450*/ @!P0 LDS R15, [R13+-0x4] ; /* 0xfffffc000d0f8984 */
/* 0x000e240000000800 */
/*0460*/ @!P0 FADD R16, R14, R15 ; /* 0x0000000f0e108221 */
/* 0x001fe20000000000 */
/*0470*/ SHF.L.U32 R14, R7, 0x8, RZ ; /* 0x00000008070e7819 */
/* 0x000fc800000006ff */
/*0480*/ @!P0 STS [R13+-0x4], R16 ; /* 0xfffffc100d008388 */
/* 0x0001e80000000800 */
/*0490*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04a0*/ ISETP.GT.AND P0, PT, R17, 0x3ff, PT ; /* 0x000003ff1100780c */
/* 0x000fe40003f04270 */
/*04b0*/ IADD3 R16, R14, -0x1, RZ ; /* 0xffffffff0e107810 */
/* 0x001fc60007ffe0ff */
/*04c0*/ @!P3 LDS R15, [R14+-0x104] ; /* 0xfffefc000e0fb984 */
/* 0x000fe80000000800 */
/*04d0*/ @!P3 LDS R18, [R14+-0x4] ; /* 0xfffffc000e12b984 */
/* 0x000e240000000800 */
/*04e0*/ @!P3 FADD R17, R15, R18 ; /* 0x000000120f11b221 */
/* 0x001fe40000000000 */
/*04f0*/ IMAD.SHL.U32 R15, R7, 0x200, RZ ; /* 0x00000200070f7824 */
/* 0x000fc600078e00ff */
/*0500*/ @!P3 STS [R14+-0x4], R17 ; /* 0xfffffc110e00b388 */
/* 0x0001e80000000800 */
/*0510*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0520*/ ISETP.GT.AND P3, PT, R16, 0x3ff, PT ; /* 0x000003ff1000780c */
/* 0x000fe20003f64270 */
/*0530*/ IMAD.SHL.U32 R16, R7, 0x400, RZ ; /* 0x0000040007107824 */
/* 0x000fe200078e00ff */
/*0540*/ IADD3 R17, R15, -0x1, RZ ; /* 0xffffffff0f117810 */
/* 0x001fc60007ffe0ff */
/*0550*/ @!P0 LDS R18, [R15+-0x204] ; /* 0xfffdfc000f128984 */
/* 0x000fe80000000800 */
/*0560*/ @!P0 LDS R19, [R15+-0x4] ; /* 0xfffffc000f138984 */
/* 0x000e240000000800 */
/*0570*/ @!P0 FADD R18, R18, R19 ; /* 0x0000001312128221 */
/* 0x001fca0000000000 */
/*0580*/ @!P0 STS [R15+-0x4], R18 ; /* 0xfffffc120f008388 */
/* 0x000fe80000000800 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05a0*/ ISETP.GT.AND P0, PT, R17, 0x3ff, PT ; /* 0x000003ff1100780c */
/* 0x000fca0003f04270 */
/*05b0*/ @!P3 LDS R19, [R16+-0x404] ; /* 0xfffbfc001013b984 */
/* 0x000fe80000000800 */
/*05c0*/ @!P3 LDS R20, [R16+-0x4] ; /* 0xfffffc001014b984 */
/* 0x000e240000000800 */
/*05d0*/ @!P3 FADD R19, R19, R20 ; /* 0x000000141313b221 */
/* 0x001fca0000000000 */
/*05e0*/ @!P3 STS [R16+-0x4], R19 ; /* 0xfffffc131000b388 */
/* 0x000fe80000000800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0600*/ ISETP.GT.AND P3, PT, R14, 0x300, PT ; /* 0x000003000e00780c */
/* 0x000fca0003f64270 */
/*0610*/ @!P0 LDS R6, [R21+0xffc] ; /* 0x000ffc0015068984 */
/* 0x000fe80000000800 */
/*0620*/ @!P0 LDS R17, [R21+0x7fc] ; /* 0x0007fc0015118984 */
/* 0x000e240000000800 */
/*0630*/ @!P0 FADD R6, R6, R17 ; /* 0x0000001106068221 */
/* 0x001fca0000000000 */
/*0640*/ @!P0 STS [R21+0xffc], R6 ; /* 0x000ffc0615008388 */
/* 0x000fe80000000800 */
/*0650*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0660*/ ISETP.GT.AND P0, PT, R13, 0x380, PT ; /* 0x000003800d00780c */
/* 0x000fca0003f04270 */
/*0670*/ @!P3 LDS R17, [R16+0x3fc] ; /* 0x0003fc001011b984 */
/* 0x000fe80000000800 */
/*0680*/ @!P3 LDS R18, [R16+-0x4] ; /* 0xfffffc001012b984 */
/* 0x000e240000000800 */
/*0690*/ @!P3 FADD R17, R17, R18 ; /* 0x000000121111b221 */
/* 0x001fca0000000000 */
/*06a0*/ @!P3 STS [R16+0x3fc], R17 ; /* 0x0003fc111000b388 */
/* 0x000fe80000000800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06c0*/ ISETP.GT.AND P3, PT, R12, 0x3c0, PT ; /* 0x000003c00c00780c */
/* 0x000fca0003f64270 */
/*06d0*/ @!P0 LDS R18, [R15+0x1fc] ; /* 0x0001fc000f128984 */
/* 0x000fe80000000800 */
/*06e0*/ @!P0 LDS R19, [R15+-0x4] ; /* 0xfffffc000f138984 */
/* 0x000e240000000800 */
/*06f0*/ @!P0 FADD R18, R18, R19 ; /* 0x0000001312128221 */
/* 0x001fca0000000000 */
/*0700*/ @!P0 STS [R15+0x1fc], R18 ; /* 0x0001fc120f008388 */
/* 0x000fe80000000800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0720*/ ISETP.GT.AND P0, PT, R10, 0x3e0, PT ; /* 0x000003e00a00780c */
/* 0x000fca0003f04270 */
/*0730*/ @!P3 LDS R6, [R14+0xfc] ; /* 0x0000fc000e06b984 */
/* 0x000fe80000000800 */
/*0740*/ @!P3 LDS R19, [R14+-0x4] ; /* 0xfffffc000e13b984 */
/* 0x000e240000000800 */
/*0750*/ @!P3 FADD R19, R6, R19 ; /* 0x000000130613b221 */
/* 0x001fca0000000000 */
/*0760*/ @!P3 STS [R14+0xfc], R19 ; /* 0x0000fc130e00b388 */
/* 0x000fe80000000800 */
/*0770*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0780*/ ISETP.GT.AND P3, PT, R11, 0x3f0, PT ; /* 0x000003f00b00780c */
/* 0x000fca0003f64270 */
/*0790*/ @!P0 LDS R6, [R13+0x7c] ; /* 0x00007c000d068984 */
/* 0x000fe80000000800 */
/*07a0*/ @!P0 LDS R17, [R13+-0x4] ; /* 0xfffffc000d118984 */
/* 0x000e240000000800 */
/*07b0*/ @!P0 FADD R16, R6, R17 ; /* 0x0000001106108221 */
/* 0x001fe40000000000 */
/*07c0*/ IMAD.SHL.U32 R6, R7, 0x8, RZ ; /* 0x0000000807067824 */
/* 0x000fc600078e00ff */
/*07d0*/ @!P0 STS [R13+0x7c], R16 ; /* 0x00007c100d008388 */
/* 0x000fe80000000800 */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07f0*/ ISETP.GT.AND P0, PT, R6, 0x3f8, PT ; /* 0x000003f80600780c */
/* 0x000fca0003f04270 */
/*0800*/ @!P3 LDS R11, [R12+0x3c] ; /* 0x00003c000c0bb984 */
/* 0x000fe80000000800 */
/*0810*/ @!P3 LDS R18, [R12+-0x4] ; /* 0xfffffc000c12b984 */
/* 0x000e240000000800 */
/*0820*/ @!P3 FADD R11, R11, R18 ; /* 0x000000120b0bb221 */
/* 0x001fca0000000000 */
/*0830*/ @!P3 STS [R12+0x3c], R11 ; /* 0x00003c0b0c00b388 */
/* 0x000fe80000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0850*/ ISETP.GT.AND P3, PT, R9, 0x3fc, PT ; /* 0x000003fc0900780c */
/* 0x000fca0003f64270 */
/*0860*/ @!P0 LDS R6, [R10+0x1c] ; /* 0x00001c000a068984 */
/* 0x000fe80000000800 */
/*0870*/ @!P0 LDS R15, [R10+-0x4] ; /* 0xfffffc000a0f8984 */
/* 0x000e240000000800 */
/*0880*/ @!P0 FADD R15, R6, R15 ; /* 0x0000000f060f8221 */
/* 0x001fca0000000000 */
/*0890*/ @!P0 STS [R10+0x1c], R15 ; /* 0x00001c0f0a008388 */
/* 0x000fe80000000800 */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08b0*/ ISETP.GT.AND P0, PT, R8, 0x3fe, PT ; /* 0x000003fe0800780c */
/* 0x000fca0003f04270 */
/*08c0*/ @!P3 LDS R6, [R7.X16+0xc] ; /* 0x00000c000706b984 */
/* 0x000fe8000000c800 */
/*08d0*/ @!P3 LDS R9, [R7.X16+-0x4] ; /* 0xfffffc000709b984 */
/* 0x000e24000000c800 */
/*08e0*/ @!P3 FADD R6, R6, R9 ; /* 0x000000090606b221 */
/* 0x001fca0000000000 */
/*08f0*/ @!P3 STS [R7.X16+0xc], R6 ; /* 0x00000c060700b388 */
/* 0x000fe8000000c800 */
/*0900*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0910*/ ISETP.GT.AND P3, PT, R7, 0x3ff, PT ; /* 0x000003ff0700780c */
/* 0x000fca0003f64270 */
/*0920*/ @!P0 LDS R8, [R7.X8+0x4] ; /* 0x0000040007088984 */
/* 0x000fe80000008800 */
/*0930*/ @!P0 LDS R9, [R7.X8+-0x4] ; /* 0xfffffc0007098984 */
/* 0x000e240000008800 */
/*0940*/ @!P0 FADD R8, R8, R9 ; /* 0x0000000908088221 */
/* 0x001fca0000000000 */
/*0950*/ @!P0 STS [R7.X8+0x4], R8 ; /* 0x0000040807008388 */
/* 0x0001e80000008800 */
/*0960*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0970*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc80003f05070 */
/*0980*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f05300 */
/*0990*/ @!P1 MOV R7, 0x4 ; /* 0x0000000400079802 */
/* 0x001fe40000000f00 */
/*09a0*/ ISETP.NE.OR P0, PT, R3, RZ, !P0 ; /* 0x000000ff0300720c */
/* 0x000fc60004705670 */
/*09b0*/ @!P1 IMAD.WIDE R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004069625 */
/* 0x000fe200078e0207 */
/*09c0*/ @!P3 LDS R9, [R3.X8+0x8] ; /* 0x000008000309b984 */
/* 0x000fe80000008800 */
/*09d0*/ @!P3 LDS R10, [R3.X8+0x4] ; /* 0x00000400030ab984 */
/* 0x000e240000008800 */
/*09e0*/ @!P3 FADD R10, R9, R10 ; /* 0x0000000a090ab221 */
/* 0x001fe40000000000 */
/*09f0*/ @!P2 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff09a424 */
/* 0x000fc600078e00ff */
/*0a00*/ @!P3 STS [R3.X8+0x8], R10 ; /* 0x0000080a0300b388 */
/* 0x000fe20000008800 */
/*0a10*/ @!P2 IMAD.WIDE.U32 R8, R2, R9, c[0x0][0x168] ; /* 0x00005a000208a625 */
/* 0x000fc600078e0009 */
/*0a20*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a30*/ @!P1 LDS R11, [R3.X4] ; /* 0x00000000030b9984 */
/* 0x000e280000004800 */
/*0a40*/ @!P2 LDS R5, [R5.X4] ; /* 0x000000000505a984 */
/* 0x000e680000004800 */
/*0a50*/ @!P1 STG.E [R6.64], R11 ; /* 0x0000000b06009986 */
/* 0x0011e8000c101906 */
/*0a60*/ @!P2 STG.E [R8.64], R5 ; /* 0x000000050800a986 */
/* 0x0021e2000c101906 */
/*0a70*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a80*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0a90*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0aa0*/ ULEA UR4, UR4, 0xfffffffc, 0x3 ; /* 0xfffffffc04047891 */
/* 0x000fd2000f8e183f */
/*0ab0*/ LDS R5, [UR4] ; /* 0x00000004ff057984 */
/* 0x001e220008000800 */
/*0ac0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0ad0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPfS_S_i
.globl _Z4scanPfS_S_i
.p2align 8
.type _Z4scanPfS_S_i,@function
_Z4scanPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s5
v_lshl_add_u32 v1, s2, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v3, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v3
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, s3, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s3, s7, v5, s3
global_load_b32 v4, v[4:5], off
v_add_lshl_u32 v5, v0, s5, 2
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v4, 1, v0
s_mov_b32 s6, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s3, s6, 1
s_cmpk_gt_u32 s6, 0x100
s_mov_b32 s6, s3
s_cbranch_scc1 .LBB0_8
.LBB0_6:
v_mul_lo_u32 v5, s6, v4
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 0x201, v5
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v5, v5, 1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s6, v5
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_5
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_lshl_add_u32 v4, v0, 1, 2
s_movk_i32 s6, 0x100
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s3, s6, 1
s_cmp_lt_u32 s6, 2
s_mov_b32 s6, s3
s_cbranch_scc1 .LBB0_12
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_mad_u32_u24 v6, v4, s6, -1
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v5, s6, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400, v5
s_cbranch_execz .LBB0_9
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_9
.LBB0_12:
s_load_b64 s[6:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v4, 2, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
ds_load_b32 v4, v4
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v4, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
v_add_lshl_u32 v1, v0, s5, 2
v_mov_b32_e32 v4, 0
ds_load_b32 v5, v1
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v5, off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u64 s[0:1], 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_lshl_b32 s2, s5, 3
s_ashr_i32 s5, s4, 31
s_add_i32 s2, s2, -4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
s_lshl_b64 s[2:3], s[4:5], 2
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPfS_S_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPfS_S_i, .Lfunc_end0-_Z4scanPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4scanPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e4e09_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4scanPfS_S_iPfS_S_i
.type _Z28__device_stub__Z4scanPfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4scanPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4scanPfS_S_iPfS_S_i, .-_Z28__device_stub__Z4scanPfS_S_iPfS_S_i
.globl _Z4scanPfS_S_i
.type _Z4scanPfS_S_i, @function
_Z4scanPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4scanPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4scanPfS_S_i, .-_Z4scanPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4scanPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
.globl _Z19__device_stub__scanPfS_S_i # -- Begin function _Z19__device_stub__scanPfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPfS_S_i,@function
_Z19__device_stub__scanPfS_S_i: # @_Z19__device_stub__scanPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPfS_S_i, .Lfunc_end0-_Z19__device_stub__scanPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPfS_S_i,@object # @_Z4scanPfS_S_i
.section .rodata,"a",@progbits
.globl _Z4scanPfS_S_i
.p2align 3, 0x0
_Z4scanPfS_S_i:
.quad _Z19__device_stub__scanPfS_S_i
.size _Z4scanPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4scanPfS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
// main program for the CPU: compiled by MS-VC++
int main(void) {
// host-side data
const int WIDTH = 5;
int a[WIDTH][WIDTH];
int b[WIDTH][WIDTH];
int c[WIDTH][WIDTH] = { 0 };
// make a, b matrices
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
a[y][x] = y * 10 + x;
b[y][x] = (y * 10 + x) * 100;
}
}
// calculate
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
c[y][x] = a[y][x] + b[y][x];
}
}
// print the result
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
printf("%5d", c[y][x]);
}
printf("\n");
}
// done
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
// main program for the CPU: compiled by MS-VC++
int main(void) {
// host-side data
const int WIDTH = 5;
int a[WIDTH][WIDTH];
int b[WIDTH][WIDTH];
int c[WIDTH][WIDTH] = { 0 };
// make a, b matrices
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
a[y][x] = y * 10 + x;
b[y][x] = (y * 10 + x) * 100;
}
}
// calculate
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
c[y][x] = a[y][x] + b[y][x];
}
}
// print the result
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
printf("%5d", c[y][x]);
}
printf("\n");
}
// done
return 0;
} | .file "tmpxft_0008a595_00000000-6_04B-1-matadd-host.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5d"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $336, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 224(%rsp), %rdi
movl $12, %ecx
rep stosq
movl $0, (%rdi)
movq %rsp, %r8
leaq 112(%rsp), %rdi
movl $0, %esi
movl $0, %r9d
.L4:
movl %r9d, %edx
movl $0, %eax
.L5:
leal (%rsi,%rax), %ecx
movl %ecx, (%r8,%rax,4)
movl %edx, (%rdi,%rax,4)
addq $1, %rax
addl $100, %edx
cmpq $5, %rax
jne .L5
addl $1000, %r9d
addl $10, %esi
addq $20, %r8
addq $20, %rdi
cmpl $50, %esi
jne .L4
movl $20, %ecx
.L6:
leaq -20(%rcx), %rax
.L7:
movl 112(%rsp,%rax), %edx
addl (%rsp,%rax), %edx
movl %edx, 224(%rsp,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L7
addq $20, %rcx
cmpq $120, %rcx
jne .L6
leaq 224(%rsp), %rbp
leaq 324(%rsp), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L8:
movl $0, %ebx
.L9:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L9
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $20, %rbp
cmpq %rbp, %r14
jne .L8
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $336, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
// main program for the CPU: compiled by MS-VC++
int main(void) {
// host-side data
const int WIDTH = 5;
int a[WIDTH][WIDTH];
int b[WIDTH][WIDTH];
int c[WIDTH][WIDTH] = { 0 };
// make a, b matrices
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
a[y][x] = y * 10 + x;
b[y][x] = (y * 10 + x) * 100;
}
}
// calculate
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
c[y][x] = a[y][x] + b[y][x];
}
}
// print the result
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
printf("%5d", c[y][x]);
}
printf("\n");
}
// done
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
// main program for the CPU: compiled by MS-VC++
int main(void) {
// host-side data
const int WIDTH = 5;
int a[WIDTH][WIDTH];
int b[WIDTH][WIDTH];
int c[WIDTH][WIDTH] = { 0 };
// make a, b matrices
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
a[y][x] = y * 10 + x;
b[y][x] = (y * 10 + x) * 100;
}
}
// calculate
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
c[y][x] = a[y][x] + b[y][x];
}
}
// print the result
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
printf("%5d", c[y][x]);
}
printf("\n");
}
// done
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
// main program for the CPU: compiled by MS-VC++
int main(void) {
// host-side data
const int WIDTH = 5;
int a[WIDTH][WIDTH];
int b[WIDTH][WIDTH];
int c[WIDTH][WIDTH] = { 0 };
// make a, b matrices
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
a[y][x] = y * 10 + x;
b[y][x] = (y * 10 + x) * 100;
}
}
// calculate
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
c[y][x] = a[y][x] + b[y][x];
}
}
// print the result
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
printf("%5d", c[y][x]);
}
printf("\n");
}
// done
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
// main program for the CPU: compiled by MS-VC++
int main(void) {
// host-side data
const int WIDTH = 5;
int a[WIDTH][WIDTH];
int b[WIDTH][WIDTH];
int c[WIDTH][WIDTH] = { 0 };
// make a, b matrices
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
a[y][x] = y * 10 + x;
b[y][x] = (y * 10 + x) * 100;
}
}
// calculate
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
c[y][x] = a[y][x] + b[y][x];
}
}
// print the result
for (int y = 0; y < WIDTH; ++y) {
for (int x = 0; x < WIDTH; ++x) {
printf("%5d", c[y][x]);
}
printf("\n");
}
// done
return 0;
} | .text
.file "04B-1-matadd-host.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movaps %xmm0, 16(%rsp)
movaps %xmm0, (%rsp)
movl $0, 96(%rsp)
xorl %eax, %eax
leaq 224(%rsp), %rcx
leaq 112(%rsp), %rdx
xorl %esi, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_1: # %.preheader37
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movl %esi, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r9), %r10d
movl %r10d, (%rcx,%r9,4)
movl %r8d, (%rdx,%r9,4)
incq %r9
addl $100, %r8d
cmpq $5, %r9
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rdi
addl $1000, %esi # imm = 0x3E8
addq $10, %rax
addq $20, %rcx
addq $20, %rdx
cmpq $5, %rdi
jne .LBB0_1
# %bb.4: # %.preheader35.preheader
leaq 224(%rsp), %rax
leaq 112(%rsp), %rcx
movq %rsp, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_5: # %.preheader35
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rdi,4), %r8d
addl (%rax,%rdi,4), %r8d
movl %r8d, (%rdx,%rdi,4)
incq %rdi
cmpq $5, %rdi
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
incq %rsi
addq $20, %rax
addq $20, %rcx
addq $20, %rdx
cmpq $5, %rsi
jne .LBB0_5
# %bb.8: # %.preheader.preheader
movq %rsp, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $20, %rbx
cmpq $5, %r14
jne .LBB0_9
# %bb.12:
xorl %eax, %eax
addq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5d"
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008a595_00000000-6_04B-1-matadd-host.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%5d"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $336, %rsp
.cfi_def_cfa_offset 384
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 224(%rsp), %rdi
movl $12, %ecx
rep stosq
movl $0, (%rdi)
movq %rsp, %r8
leaq 112(%rsp), %rdi
movl $0, %esi
movl $0, %r9d
.L4:
movl %r9d, %edx
movl $0, %eax
.L5:
leal (%rsi,%rax), %ecx
movl %ecx, (%r8,%rax,4)
movl %edx, (%rdi,%rax,4)
addq $1, %rax
addl $100, %edx
cmpq $5, %rax
jne .L5
addl $1000, %r9d
addl $10, %esi
addq $20, %r8
addq $20, %rdi
cmpl $50, %esi
jne .L4
movl $20, %ecx
.L6:
leaq -20(%rcx), %rax
.L7:
movl 112(%rsp,%rax), %edx
addl (%rsp,%rax), %edx
movl %edx, 224(%rsp,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L7
addq $20, %rcx
cmpq $120, %rcx
jne .L6
leaq 224(%rsp), %rbp
leaq 324(%rsp), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L8:
movl $0, %ebx
.L9:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L9
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $20, %rbp
cmpq %rbp, %r14
jne .L8
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $336, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "04B-1-matadd-host.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorps %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 64(%rsp)
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movaps %xmm0, 16(%rsp)
movaps %xmm0, (%rsp)
movl $0, 96(%rsp)
xorl %eax, %eax
leaq 224(%rsp), %rcx
leaq 112(%rsp), %rdx
xorl %esi, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_1: # %.preheader37
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movl %esi, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%r9), %r10d
movl %r10d, (%rcx,%r9,4)
movl %r8d, (%rdx,%r9,4)
incq %r9
addl $100, %r8d
cmpq $5, %r9
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rdi
addl $1000, %esi # imm = 0x3E8
addq $10, %rax
addq $20, %rcx
addq $20, %rdx
cmpq $5, %rdi
jne .LBB0_1
# %bb.4: # %.preheader35.preheader
leaq 224(%rsp), %rax
leaq 112(%rsp), %rcx
movq %rsp, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_5: # %.preheader35
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rdi,4), %r8d
addl (%rax,%rdi,4), %r8d
movl %r8d, (%rdx,%rdi,4)
incq %rdi
cmpq $5, %rdi
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
incq %rsi
addq $20, %rax
addq $20, %rcx
addq $20, %rdx
cmpq $5, %rsi
jne .LBB0_5
# %bb.8: # %.preheader.preheader
movq %rsp, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $20, %rbx
cmpq $5, %r14
jne .LBB0_9
# %bb.12:
xorl %eax, %eax
addq $336, %rsp # imm = 0x150
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5d"
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void vec_add(float *A, float *B, float* C, int size)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index<size)
C[index] = A[index] + B[index];
} | code for sm_80
Function : _Z7vec_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void vec_add(float *A, float *B, float* C, int size)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index<size)
C[index] = A[index] + B[index];
} | .file "tmpxft_0000415a_00000000-6_vec_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vec_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i
.globl _Z7vec_addPfS_S_i
.type _Z7vec_addPfS_S_i, @function
_Z7vec_addPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7vec_addPfS_S_i, .-_Z7vec_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7vec_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vec_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void vec_add(float *A, float *B, float* C, int size)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index<size)
C[index] = A[index] + B[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void vec_add(float *A, float *B, float* C, int size)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index<size)
C[index] = A[index] + B[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void vec_add(float *A, float *B, float* C, int size)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index<size)
C[index] = A[index] + B[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vec_addPfS_S_i
.globl _Z7vec_addPfS_S_i
.p2align 8
.type _Z7vec_addPfS_S_i,@function
_Z7vec_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vec_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vec_addPfS_S_i, .Lfunc_end0-_Z7vec_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vec_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vec_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
__global__ void vec_add(float *A, float *B, float* C, int size)
{
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index<size)
C[index] = A[index] + B[index];
} | .text
.file "vec_add.hip"
.globl _Z22__device_stub__vec_addPfS_S_i # -- Begin function _Z22__device_stub__vec_addPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__vec_addPfS_S_i,@function
_Z22__device_stub__vec_addPfS_S_i: # @_Z22__device_stub__vec_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vec_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__vec_addPfS_S_i, .Lfunc_end0-_Z22__device_stub__vec_addPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vec_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vec_addPfS_S_i,@object # @_Z7vec_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z7vec_addPfS_S_i
.p2align 3, 0x0
_Z7vec_addPfS_S_i:
.quad _Z22__device_stub__vec_addPfS_S_i
.size _Z7vec_addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7vec_addPfS_S_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vec_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vec_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7vec_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vec_addPfS_S_i
.globl _Z7vec_addPfS_S_i
.p2align 8
.type _Z7vec_addPfS_S_i,@function
_Z7vec_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7vec_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7vec_addPfS_S_i, .Lfunc_end0-_Z7vec_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7vec_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7vec_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000415a_00000000-6_vec_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7vec_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i
.globl _Z7vec_addPfS_S_i
.type _Z7vec_addPfS_S_i, @function
_Z7vec_addPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7vec_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7vec_addPfS_S_i, .-_Z7vec_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7vec_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vec_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_add.hip"
.globl _Z22__device_stub__vec_addPfS_S_i # -- Begin function _Z22__device_stub__vec_addPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__vec_addPfS_S_i,@function
_Z22__device_stub__vec_addPfS_S_i: # @_Z22__device_stub__vec_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7vec_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__vec_addPfS_S_i, .Lfunc_end0-_Z22__device_stub__vec_addPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7vec_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7vec_addPfS_S_i,@object # @_Z7vec_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z7vec_addPfS_S_i
.p2align 3, 0x0
_Z7vec_addPfS_S_i:
.quad _Z22__device_stub__vec_addPfS_S_i
.size _Z7vec_addPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7vec_addPfS_S_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__vec_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7vec_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
struct StringData {
char str[11];
};
unsigned int *devDataInput;
StringData *devStringDataOutput;
unsigned int dataCount;
template< typename T >
void check(T result, char const *const func, const char *const file, int const line)
{
if (result)
{
fprintf(stderr, "CUDA error at %s:%d code=%d(%s) \"%s\" \n",
file, line, static_cast<unsigned int>(result), cudaGetErrorString(result), func);
// Make sure we call CUDA Device Reset before exiting
cudaDeviceReset();
exit(EXIT_FAILURE);
}
}
#define checkCudaErrors(val) check ( (val), #val, __FILE__, __LINE__ )
bool cdInit(unsigned int dataCountArg, void **hostInputMemory, void **hostOutputMemory, bool allocPinnedMemory)
{
dataCount = dataCountArg;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaSetDevice error: %d\r\n", (int)cudaStatus);
return false;
}
if(allocPinnedMemory)
{
checkCudaErrors(cudaHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), cudaHostAllocWriteCombined));
checkCudaErrors(cudaHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0));
}
else
{
*hostInputMemory = (void *)malloc(dataCount * sizeof(unsigned int));
*hostOutputMemory = (void *)malloc(dataCount * sizeof(StringData));
}
cudaStatus = cudaMalloc((void**)&devDataInput, dataCount * sizeof(unsigned int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
cudaStatus = cudaMalloc((void**)&devStringDataOutput, dataCount * sizeof(StringData));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
}
__device__ void uintToStringDevice(unsigned int x, char *output)
{
const int bufSize = 11;
char buf[bufSize];
buf[bufSize - 1] = 0;
int ind = bufSize - 2;
do {
buf[ind] = '0' + x % 10;
x /= 10;
--ind;
} while (x != 0);
++ind;
int i;
for(i = 0; buf[ind] != 0; ++i, ++ind)
{
output[i] = buf[ind];
}
output[i] = 0;
}
__global__ void cdItoaDevice(unsigned int *dataInput, StringData *stringDataOutput)
{
int threadIndex = blockIdx.x * blockDim.x + threadIdx.x;
uintToStringDevice(dataInput[threadIndex], stringDataOutput[threadIndex].str);
}
bool cdItoa(unsigned int *dataInput, StringData *stringDataOutput)
{
cudaError_t cudaStatus=cudaSuccess;
cudaStatus = cudaMemcpy(devDataInput, dataInput, dataCount * sizeof(unsigned int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
int numberOfBlocks = 1024;
int threadsPerBlock = dataCount / numberOfBlocks;
cdItoaDevice<<<numberOfBlocks, threadsPerBlock>>>(devDataInput, devStringDataOutput);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cuda error: %s\r\n", cudaGetErrorString(cudaStatus));
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaDeviceSynchronize error: %d %s\r\n", (int)cudaStatus, cudaGetErrorString(cudaStatus));
return false;
}
cudaStatus = cudaMemcpy(stringDataOutput, devStringDataOutput, dataCount * sizeof(StringData), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
} | code for sm_80
Function : _Z12cdItoaDevicePjP10StringData
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0204 */
/*0080*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.36441802978515625e-07 ; /* 0x00000009ff007435 */
/* 0x000fe200000001ff */
/*00a0*/ BSSY B0, 0x190 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe20000011403 */
/*00c0*/ STL.U8 [R1+0xa], RZ ; /* 0x00000aff01007387 */
/* 0x0001e80000100000 */
/*00d0*/ IMAD.WIDE.U32 R4, R6.reuse, -0x33333333, RZ ; /* 0xcccccccd06047825 */
/* 0x061fe200078e00ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fc60003f04070 */
/*00f0*/ IMAD.IADD R7, R1, 0x1, R0.reuse ; /* 0x0000000101077824 */
/* 0x100fe200078e0200 */
/*0100*/ SHF.R.U32.HI R9, RZ, 0x3, R5 ; /* 0x00000003ff097819 */
/* 0x000fe20000011605 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0000 */
/*0120*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc60007ffe0ff */
/*0130*/ IMAD R4, R9, -0xa, R6 ; /* 0xfffffff609047824 */
/* 0x000fe200078e0206 */
/*0140*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fc80000000f00 */
/*0150*/ LOP3.LUT R4, R4, 0x30, RZ, 0xfc, !PT ; /* 0x0000003004047812 */
/* 0x000fca00078efcff */
/*0160*/ STL.U8 [R7], R4 ; /* 0x0000000407007387 */
/* 0x0001e20000100000 */
/*0170*/ @P0 BRA 0xd0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, 0xb ; /* 0x0000000bff007424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x2b0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD R11, R2, 0xb, RZ ; /* 0x0000000b020b7824 */
/* 0x000fe200078e02ff */
/*01c0*/ PRMT R7, R4, 0x7610, R7 ; /* 0x0000761004077816 */
/* 0x001fe20000000007 */
/*01d0*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0000 */
/*01e0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0005 */
/*0200*/ IMAD.IADD R8, R3, 0x1, R11 ; /* 0x0000000103087824 */
/* 0x000fe400078e020b */
/*0210*/ IADD3 R4, P0, R9.reuse, R2, RZ ; /* 0x0000000209047210 */
/* 0x040fe40007f1e0ff */
/*0220*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0230*/ LEA.HI.X.SX32 R5, R9, R8, 0x1, P0 ; /* 0x0000000809057211 */
/* 0x000fe400000f0eff */
/*0240*/ IADD3 R6, R1, R0, RZ ; /* 0x0000000001067210 */
/* 0x000fc60007ffe0ff */
/*0250*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101104 */
/*0260*/ LDL.U8 R7, [R6] ; /* 0x0000000006077983 */
/* 0x001ea20000100000 */
/*0270*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x004fda0003f05270 */
/*0290*/ @P0 BRA 0x210 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ STG.E.U8 [R4.64+0x1], RZ ; /* 0x000001ff04007986 */
/* 0x000fe2000c101104 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
struct StringData {
char str[11];
};
unsigned int *devDataInput;
StringData *devStringDataOutput;
unsigned int dataCount;
template< typename T >
void check(T result, char const *const func, const char *const file, int const line)
{
if (result)
{
fprintf(stderr, "CUDA error at %s:%d code=%d(%s) \"%s\" \n",
file, line, static_cast<unsigned int>(result), cudaGetErrorString(result), func);
// Make sure we call CUDA Device Reset before exiting
cudaDeviceReset();
exit(EXIT_FAILURE);
}
}
#define checkCudaErrors(val) check ( (val), #val, __FILE__, __LINE__ )
bool cdInit(unsigned int dataCountArg, void **hostInputMemory, void **hostOutputMemory, bool allocPinnedMemory)
{
dataCount = dataCountArg;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaSetDevice error: %d\r\n", (int)cudaStatus);
return false;
}
if(allocPinnedMemory)
{
checkCudaErrors(cudaHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), cudaHostAllocWriteCombined));
checkCudaErrors(cudaHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0));
}
else
{
*hostInputMemory = (void *)malloc(dataCount * sizeof(unsigned int));
*hostOutputMemory = (void *)malloc(dataCount * sizeof(StringData));
}
cudaStatus = cudaMalloc((void**)&devDataInput, dataCount * sizeof(unsigned int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
cudaStatus = cudaMalloc((void**)&devStringDataOutput, dataCount * sizeof(StringData));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
}
__device__ void uintToStringDevice(unsigned int x, char *output)
{
const int bufSize = 11;
char buf[bufSize];
buf[bufSize - 1] = 0;
int ind = bufSize - 2;
do {
buf[ind] = '0' + x % 10;
x /= 10;
--ind;
} while (x != 0);
++ind;
int i;
for(i = 0; buf[ind] != 0; ++i, ++ind)
{
output[i] = buf[ind];
}
output[i] = 0;
}
__global__ void cdItoaDevice(unsigned int *dataInput, StringData *stringDataOutput)
{
int threadIndex = blockIdx.x * blockDim.x + threadIdx.x;
uintToStringDevice(dataInput[threadIndex], stringDataOutput[threadIndex].str);
}
bool cdItoa(unsigned int *dataInput, StringData *stringDataOutput)
{
cudaError_t cudaStatus=cudaSuccess;
cudaStatus = cudaMemcpy(devDataInput, dataInput, dataCount * sizeof(unsigned int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
int numberOfBlocks = 1024;
int threadsPerBlock = dataCount / numberOfBlocks;
cdItoaDevice<<<numberOfBlocks, threadsPerBlock>>>(devDataInput, devStringDataOutput);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cuda error: %s\r\n", cudaGetErrorString(cudaStatus));
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaDeviceSynchronize error: %d %s\r\n", (int)cudaStatus, cudaGetErrorString(cudaStatus));
return false;
}
cudaStatus = cudaMemcpy(stringDataOutput, devStringDataOutput, dataCount * sizeof(StringData), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
} | .file "tmpxft_0017446d_00000000-6_cuda_itoa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18uintToStringDevicejPc
.type _Z18uintToStringDevicejPc, @function
_Z18uintToStringDevicejPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z18uintToStringDevicejPc, .-_Z18uintToStringDevicejPc
.globl _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
.type _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData, @function
_Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12cdItoaDevicePjP10StringData(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData, .-_Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
.globl _Z12cdItoaDevicePjP10StringData
.type _Z12cdItoaDevicePjP10StringData, @function
_Z12cdItoaDevicePjP10StringData:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12cdItoaDevicePjP10StringData, .-_Z12cdItoaDevicePjP10StringData
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMemcpy error: %d\r\n"
.LC1:
.string "cuda error: %s\r\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cudaDeviceSynchronize error: %d %s\r\n"
.text
.globl _Z6cdItoaPjP10StringData
.type _Z6cdItoaPjP10StringData, @function
_Z6cdItoaPjP10StringData:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movl dataCount(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq devDataInput(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
movl dataCount(%rip), %eax
shrl $10, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L24
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movl $2, %ecx
movq devStringDataOutput(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
je .L13
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L13
.L21:
movl %eax, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
.L13:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq devStringDataOutput(%rip), %rsi
movq devDataInput(%rip), %rdi
call _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
jmp .L16
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L13
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L13
.cfi_endproc
.LFE2060:
.size _Z6cdItoaPjP10StringData, .-_Z6cdItoaPjP10StringData
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z12cdItoaDevicePjP10StringData"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cdItoaDevicePjP10StringData(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z5checkI9cudaErrorEvT_PKcS3_i.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "CUDA error at %s:%d code=%d(%s) \"%s\" \n"
.section .text._Z5checkI9cudaErrorEvT_PKcS3_i,"axG",@progbits,_Z5checkI9cudaErrorEvT_PKcS3_i,comdat
.weak _Z5checkI9cudaErrorEvT_PKcS3_i
.type _Z5checkI9cudaErrorEvT_PKcS3_i, @function
_Z5checkI9cudaErrorEvT_PKcS3_i:
.LFB2134:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L32
ret
.L32:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movq %rdx, %rbp
movl %ecx, %r12d
call cudaGetErrorString@PLT
pushq %r13
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
movl %ebx, %r9d
movl %r12d, %r8d
movq %rbp, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 48
call cudaDeviceReset@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2134:
.size _Z5checkI9cudaErrorEvT_PKcS3_i, .-_Z5checkI9cudaErrorEvT_PKcS3_i
.section .rodata.str1.1
.LC5:
.string "cudaSetDevice error: %d\r\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/vovaprog/learn/master/tools/cuda/cuda_itoa/cuda_itoa.cu"
.align 8
.LC7:
.string "cudaHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), cudaHostAllocWriteCombined)"
.align 8
.LC8:
.string "cudaHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0)"
.section .rodata.str1.1
.LC9:
.string "cudaMalloc error: %d\r\n"
.text
.globl _Z6cdInitjPPvS0_b
.type _Z6cdInitjPPvS0_b, @function
_Z6cdInitjPPvS0_b:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %ebx
movl %edi, dataCount(%rip)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L41
testb %bl, %bl
je .L36
movl dataCount(%rip), %esi
salq $2, %rsi
movl $4, %edx
movq %r12, %rdi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $41, %ecx
leaq .LC6(%rip), %rbx
movq %rbx, %rdx
leaq .LC7(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rsi
movl $0, %edx
movq %rbp, %rdi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $42, %ecx
movq %rbx, %rdx
leaq .LC8(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
.L37:
movl dataCount(%rip), %esi
salq $2, %rsi
leaq devDataInput(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rsi
leaq devStringDataOutput(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .L43
.L33:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %eax, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L33
.L36:
movl dataCount(%rip), %r13d
leaq 0(,%r13,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r12)
addq %r13, %rbx
leaq 0(%r13,%rbx,2), %rdi
call malloc@PLT
movq %rax, 0(%rbp)
jmp .L37
.L42:
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L33
.L43:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L33
.cfi_endproc
.LFE2058:
.size _Z6cdInitjPPvS0_b, .-_Z6cdInitjPPvS0_b
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dataCount
.bss
.align 4
.type dataCount, @object
.size dataCount, 4
dataCount:
.zero 4
.globl devStringDataOutput
.align 8
.type devStringDataOutput, @object
.size devStringDataOutput, 8
devStringDataOutput:
.zero 8
.globl devDataInput
.align 8
.type devDataInput, @object
.size devDataInput, 8
devDataInput:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
struct StringData {
char str[11];
};
unsigned int *devDataInput;
StringData *devStringDataOutput;
unsigned int dataCount;
template< typename T >
void check(T result, char const *const func, const char *const file, int const line)
{
if (result)
{
fprintf(stderr, "CUDA error at %s:%d code=%d(%s) \"%s\" \n",
file, line, static_cast<unsigned int>(result), cudaGetErrorString(result), func);
// Make sure we call CUDA Device Reset before exiting
cudaDeviceReset();
exit(EXIT_FAILURE);
}
}
#define checkCudaErrors(val) check ( (val), #val, __FILE__, __LINE__ )
bool cdInit(unsigned int dataCountArg, void **hostInputMemory, void **hostOutputMemory, bool allocPinnedMemory)
{
dataCount = dataCountArg;
cudaError_t cudaStatus;
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaSetDevice error: %d\r\n", (int)cudaStatus);
return false;
}
if(allocPinnedMemory)
{
checkCudaErrors(cudaHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), cudaHostAllocWriteCombined));
checkCudaErrors(cudaHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0));
}
else
{
*hostInputMemory = (void *)malloc(dataCount * sizeof(unsigned int));
*hostOutputMemory = (void *)malloc(dataCount * sizeof(StringData));
}
cudaStatus = cudaMalloc((void**)&devDataInput, dataCount * sizeof(unsigned int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
cudaStatus = cudaMalloc((void**)&devStringDataOutput, dataCount * sizeof(StringData));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
}
__device__ void uintToStringDevice(unsigned int x, char *output)
{
const int bufSize = 11;
char buf[bufSize];
buf[bufSize - 1] = 0;
int ind = bufSize - 2;
do {
buf[ind] = '0' + x % 10;
x /= 10;
--ind;
} while (x != 0);
++ind;
int i;
for(i = 0; buf[ind] != 0; ++i, ++ind)
{
output[i] = buf[ind];
}
output[i] = 0;
}
__global__ void cdItoaDevice(unsigned int *dataInput, StringData *stringDataOutput)
{
int threadIndex = blockIdx.x * blockDim.x + threadIdx.x;
uintToStringDevice(dataInput[threadIndex], stringDataOutput[threadIndex].str);
}
bool cdItoa(unsigned int *dataInput, StringData *stringDataOutput)
{
cudaError_t cudaStatus=cudaSuccess;
cudaStatus = cudaMemcpy(devDataInput, dataInput, dataCount * sizeof(unsigned int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
int numberOfBlocks = 1024;
int threadsPerBlock = dataCount / numberOfBlocks;
cdItoaDevice<<<numberOfBlocks, threadsPerBlock>>>(devDataInput, devStringDataOutput);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cuda error: %s\r\n", cudaGetErrorString(cudaStatus));
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaDeviceSynchronize error: %d %s\r\n", (int)cudaStatus, cudaGetErrorString(cudaStatus));
return false;
}
cudaStatus = cudaMemcpy(stringDataOutput, devStringDataOutput, dataCount * sizeof(StringData), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
struct StringData {
char str[11];
};
unsigned int *devDataInput;
StringData *devStringDataOutput;
unsigned int dataCount;
template< typename T >
void check(T result, char const *const func, const char *const file, int const line)
{
if (result)
{
fprintf(stderr, "CUDA error at %s:%d code=%d(%s) \"%s\" \n",
file, line, static_cast<unsigned int>(result), hipGetErrorString(result), func);
// Make sure we call CUDA Device Reset before exiting
hipDeviceReset();
exit(EXIT_FAILURE);
}
}
#define checkCudaErrors(val) check ( (val), #val, __FILE__, __LINE__ )
bool cdInit(unsigned int dataCountArg, void **hostInputMemory, void **hostOutputMemory, bool allocPinnedMemory)
{
dataCount = dataCountArg;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipSetDevice error: %d\r\n", (int)cudaStatus);
return false;
}
if(allocPinnedMemory)
{
checkCudaErrors(hipHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), hipHostMallocWriteCombined));
checkCudaErrors(hipHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0));
}
else
{
*hostInputMemory = (void *)malloc(dataCount * sizeof(unsigned int));
*hostOutputMemory = (void *)malloc(dataCount * sizeof(StringData));
}
cudaStatus = hipMalloc((void**)&devDataInput, dataCount * sizeof(unsigned int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
cudaStatus = hipMalloc((void**)&devStringDataOutput, dataCount * sizeof(StringData));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
}
__device__ void uintToStringDevice(unsigned int x, char *output)
{
const int bufSize = 11;
char buf[bufSize];
buf[bufSize - 1] = 0;
int ind = bufSize - 2;
do {
buf[ind] = '0' + x % 10;
x /= 10;
--ind;
} while (x != 0);
++ind;
int i;
for(i = 0; buf[ind] != 0; ++i, ++ind)
{
output[i] = buf[ind];
}
output[i] = 0;
}
__global__ void cdItoaDevice(unsigned int *dataInput, StringData *stringDataOutput)
{
int threadIndex = blockIdx.x * blockDim.x + threadIdx.x;
uintToStringDevice(dataInput[threadIndex], stringDataOutput[threadIndex].str);
}
bool cdItoa(unsigned int *dataInput, StringData *stringDataOutput)
{
hipError_t cudaStatus=hipSuccess;
cudaStatus = hipMemcpy(devDataInput, dataInput, dataCount * sizeof(unsigned int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
int numberOfBlocks = 1024;
int threadsPerBlock = dataCount / numberOfBlocks;
cdItoaDevice<<<numberOfBlocks, threadsPerBlock>>>(devDataInput, devStringDataOutput);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "cuda error: %s\r\n", hipGetErrorString(cudaStatus));
return false;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipDeviceSynchronize error: %d %s\r\n", (int)cudaStatus, hipGetErrorString(cudaStatus));
return false;
}
cudaStatus = hipMemcpy(stringDataOutput, devStringDataOutput, dataCount * sizeof(StringData), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
struct StringData {
char str[11];
};
unsigned int *devDataInput;
StringData *devStringDataOutput;
unsigned int dataCount;
template< typename T >
void check(T result, char const *const func, const char *const file, int const line)
{
if (result)
{
fprintf(stderr, "CUDA error at %s:%d code=%d(%s) \"%s\" \n",
file, line, static_cast<unsigned int>(result), hipGetErrorString(result), func);
// Make sure we call CUDA Device Reset before exiting
hipDeviceReset();
exit(EXIT_FAILURE);
}
}
#define checkCudaErrors(val) check ( (val), #val, __FILE__, __LINE__ )
bool cdInit(unsigned int dataCountArg, void **hostInputMemory, void **hostOutputMemory, bool allocPinnedMemory)
{
dataCount = dataCountArg;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipSetDevice error: %d\r\n", (int)cudaStatus);
return false;
}
if(allocPinnedMemory)
{
checkCudaErrors(hipHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), hipHostMallocWriteCombined));
checkCudaErrors(hipHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0));
}
else
{
*hostInputMemory = (void *)malloc(dataCount * sizeof(unsigned int));
*hostOutputMemory = (void *)malloc(dataCount * sizeof(StringData));
}
cudaStatus = hipMalloc((void**)&devDataInput, dataCount * sizeof(unsigned int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
cudaStatus = hipMalloc((void**)&devStringDataOutput, dataCount * sizeof(StringData));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
}
__device__ void uintToStringDevice(unsigned int x, char *output)
{
const int bufSize = 11;
char buf[bufSize];
buf[bufSize - 1] = 0;
int ind = bufSize - 2;
do {
buf[ind] = '0' + x % 10;
x /= 10;
--ind;
} while (x != 0);
++ind;
int i;
for(i = 0; buf[ind] != 0; ++i, ++ind)
{
output[i] = buf[ind];
}
output[i] = 0;
}
__global__ void cdItoaDevice(unsigned int *dataInput, StringData *stringDataOutput)
{
int threadIndex = blockIdx.x * blockDim.x + threadIdx.x;
uintToStringDevice(dataInput[threadIndex], stringDataOutput[threadIndex].str);
}
bool cdItoa(unsigned int *dataInput, StringData *stringDataOutput)
{
hipError_t cudaStatus=hipSuccess;
cudaStatus = hipMemcpy(devDataInput, dataInput, dataCount * sizeof(unsigned int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
int numberOfBlocks = 1024;
int threadsPerBlock = dataCount / numberOfBlocks;
cdItoaDevice<<<numberOfBlocks, threadsPerBlock>>>(devDataInput, devStringDataOutput);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "cuda error: %s\r\n", hipGetErrorString(cudaStatus));
return false;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipDeviceSynchronize error: %d %s\r\n", (int)cudaStatus, hipGetErrorString(cudaStatus));
return false;
}
cudaStatus = hipMemcpy(stringDataOutput, devStringDataOutput, dataCount * sizeof(StringData), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cdItoaDevicePjP10StringData
.globl _Z12cdItoaDevicePjP10StringData
.p2align 8
.type _Z12cdItoaDevicePjP10StringData,@function
_Z12cdItoaDevicePjP10StringData:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b64 s[6:7], 9
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_1:
v_lshlrev_b16 v4, 8, v9
v_and_b32_e32 v9, 0xff, v12
v_lshlrev_b16 v12, 8, v13
s_waitcnt vmcnt(0)
v_mul_hi_u32 v13, v2, 0xcccccccd
v_lshlrev_b16 v5, 8, v16
v_and_b32_e32 v11, 0xff, v11
v_lshlrev_b16 v8, 8, v8
v_and_b32_e32 v10, 0xff, v10
s_cmp_eq_u32 s6, 5
v_cmp_gt_u32_e32 vcc_lo, 10, v2
s_cselect_b32 s2, -1, 0
v_or_b32_e32 v11, v11, v8
v_and_b32_e32 v8, 0xffff, v5
v_or_b32_e32 v5, v9, v5
v_lshrrev_b32_e32 v9, 3, v13
v_and_b32_e32 v3, 0xff, v14
v_or_b32_e32 v10, v10, v12
s_cmp_eq_u32 s6, 3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v13, v9, 10
v_or_b32_e32 v14, v3, v4
v_and_b32_e32 v4, 0xffff, v11
v_lshlrev_b32_e32 v12, 16, v10
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s6, 10
v_lshlrev_b32_e32 v3, 16, v14
s_cselect_b32 s4, -1, 0
v_or_b32_e32 v4, v4, v12
v_lshrrev_b32_e32 v16, 24, v12
s_cmp_eq_u32 s6, 9
v_or_b32_e32 v8, v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v12, 8, v4
v_lshrrev_b64 v[3:4], 24, v[3:4]
v_lshrrev_b32_e32 v4, 8, v8
v_sub_nc_u32_e32 v8, v2, v13
v_mov_b32_e32 v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v15, 48, v8
v_cndmask_b32_e64 v8, v12, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 8
v_cndmask_b32_e64 v7, v7, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 6
v_cndmask_b32_e64 v6, v6, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 4
v_cndmask_b32_e64 v10, v10, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 2
v_cndmask_b32_e64 v11, v11, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 0
v_cndmask_b32_e64 v14, v14, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 7
v_cndmask_b32_e64 v12, v5, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 1
v_cndmask_b32_e64 v13, v16, v15, s2
s_cselect_b32 s2, -1, 0
s_add_u32 s6, s6, -1
v_cndmask_b32_e64 v9, v3, v15, s3
v_cndmask_b32_e64 v0, v0, v15, s4
s_addc_u32 s7, s7, -1
v_cndmask_b32_e64 v16, v4, v15, s2
v_mov_b32_e32 v4, s6
s_or_b32 s5, vcc_lo, s5
v_mov_b32_e32 v5, s7
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 11, s[0:1]
v_add_nc_u32_e32 v1, 2, v4
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 1, v1
global_store_b8 v[2:3], v15, off
v_cndmask_b32_e32 v4, v12, v16, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v1
v_cndmask_b32_e32 v4, v4, v14, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v1
v_cndmask_b32_e32 v4, v4, v11, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 6, v1
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v13, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 8, v1
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 10, v1
v_add_nc_u32_e32 v1, 1, v1
v_cndmask_b32_e32 v15, v4, v0, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, 0xff, v15
v_cmp_eq_u16_e64 s0, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v0, 0
global_store_b8 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cdItoaDevicePjP10StringData
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cdItoaDevicePjP10StringData, .Lfunc_end0-_Z12cdItoaDevicePjP10StringData
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cdItoaDevicePjP10StringData
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cdItoaDevicePjP10StringData.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
struct StringData {
char str[11];
};
unsigned int *devDataInput;
StringData *devStringDataOutput;
unsigned int dataCount;
template< typename T >
void check(T result, char const *const func, const char *const file, int const line)
{
if (result)
{
fprintf(stderr, "CUDA error at %s:%d code=%d(%s) \"%s\" \n",
file, line, static_cast<unsigned int>(result), hipGetErrorString(result), func);
// Make sure we call CUDA Device Reset before exiting
hipDeviceReset();
exit(EXIT_FAILURE);
}
}
#define checkCudaErrors(val) check ( (val), #val, __FILE__, __LINE__ )
bool cdInit(unsigned int dataCountArg, void **hostInputMemory, void **hostOutputMemory, bool allocPinnedMemory)
{
dataCount = dataCountArg;
hipError_t cudaStatus;
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipSetDevice error: %d\r\n", (int)cudaStatus);
return false;
}
if(allocPinnedMemory)
{
checkCudaErrors(hipHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), hipHostMallocWriteCombined));
checkCudaErrors(hipHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0));
}
else
{
*hostInputMemory = (void *)malloc(dataCount * sizeof(unsigned int));
*hostOutputMemory = (void *)malloc(dataCount * sizeof(StringData));
}
cudaStatus = hipMalloc((void**)&devDataInput, dataCount * sizeof(unsigned int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
cudaStatus = hipMalloc((void**)&devStringDataOutput, dataCount * sizeof(StringData));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
}
__device__ void uintToStringDevice(unsigned int x, char *output)
{
const int bufSize = 11;
char buf[bufSize];
buf[bufSize - 1] = 0;
int ind = bufSize - 2;
do {
buf[ind] = '0' + x % 10;
x /= 10;
--ind;
} while (x != 0);
++ind;
int i;
for(i = 0; buf[ind] != 0; ++i, ++ind)
{
output[i] = buf[ind];
}
output[i] = 0;
}
__global__ void cdItoaDevice(unsigned int *dataInput, StringData *stringDataOutput)
{
int threadIndex = blockIdx.x * blockDim.x + threadIdx.x;
uintToStringDevice(dataInput[threadIndex], stringDataOutput[threadIndex].str);
}
bool cdItoa(unsigned int *dataInput, StringData *stringDataOutput)
{
hipError_t cudaStatus=hipSuccess;
cudaStatus = hipMemcpy(devDataInput, dataInput, dataCount * sizeof(unsigned int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
int numberOfBlocks = 1024;
int threadsPerBlock = dataCount / numberOfBlocks;
cdItoaDevice<<<numberOfBlocks, threadsPerBlock>>>(devDataInput, devStringDataOutput);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "cuda error: %s\r\n", hipGetErrorString(cudaStatus));
return false;
}
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipDeviceSynchronize error: %d %s\r\n", (int)cudaStatus, hipGetErrorString(cudaStatus));
return false;
}
cudaStatus = hipMemcpy(stringDataOutput, devStringDataOutput, dataCount * sizeof(StringData), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy error: %d\r\n", (int)cudaStatus);
return false;
}
return true;
} | .text
.file "cuda_itoa.hip"
.globl _Z6cdInitjPPvS0_b # -- Begin function _Z6cdInitjPPvS0_b
.p2align 4, 0x90
.type _Z6cdInitjPPvS0_b,@function
_Z6cdInitjPPvS0_b: # @_Z6cdInitjPPvS0_b
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, dataCount(%rip)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.2:
movl dataCount(%rip), %r15d
leaq (,%r15,4), %rsi
testb %bpl, %bpl
je .LBB0_8
# %bb.3:
movq %r14, %rdi
movl $4, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB0_4
# %bb.6: # %_Z5checkI10hipError_tEvT_PKcS3_i.exit
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rsi
movq %rbx, %rdi
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
je .LBB0_9
# %bb.7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movq $.L.str.3, (%rsp)
movl $.L.str.8, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $44, %ecx
jmp .LBB0_5
.LBB0_8:
movq %rsi, %rdi
callq malloc
movq %rax, (%r14)
leaq (%r15,%r15,4), %rax
leaq (%r15,%rax,2), %rdi
callq malloc
movq %rax, (%rbx)
.LBB0_9: # %_Z5checkI10hipError_tEvT_PKcS3_i.exit18
movl dataCount(%rip), %esi
shlq $2, %rsi
movl $devDataInput, %edi
callq hipMalloc
testl %eax, %eax
jne .LBB0_11
# %bb.10:
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rsi
movl $devStringDataOutput, %edi
callq hipMalloc
movb $1, %bl
testl %eax, %eax
jne .LBB0_11
.LBB0_13:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str.4, %esi
jmp .LBB0_12
.LBB0_1:
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str, %esi
.LBB0_12:
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB0_13
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movq $.L.str.1, (%rsp)
movl $.L.str.8, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $43, %ecx
.LBB0_5:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
callq hipDeviceReset
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z6cdInitjPPvS0_b, .Lfunc_end0-_Z6cdInitjPPvS0_b
.cfi_endproc
# -- End function
.globl _Z27__device_stub__cdItoaDevicePjP10StringData # -- Begin function _Z27__device_stub__cdItoaDevicePjP10StringData
.p2align 4, 0x90
.type _Z27__device_stub__cdItoaDevicePjP10StringData,@function
_Z27__device_stub__cdItoaDevicePjP10StringData: # @_Z27__device_stub__cdItoaDevicePjP10StringData
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12cdItoaDevicePjP10StringData, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__cdItoaDevicePjP10StringData, .Lfunc_end1-_Z27__device_stub__cdItoaDevicePjP10StringData
.cfi_endproc
# -- End function
.globl _Z6cdItoaPjP10StringData # -- Begin function _Z6cdItoaPjP10StringData
.p2align 4, 0x90
.type _Z6cdItoaPjP10StringData,@function
_Z6cdItoaPjP10StringData: # @_Z6cdItoaPjP10StringData
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %rsi
movq devDataInput(%rip), %rdi
movl dataCount(%rip), %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.1:
movl dataCount(%rip), %edx
shrl $10, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1024, %rdi # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq devDataInput(%rip), %rax
movq devStringDataOutput(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12cdItoaDevicePjP10StringData, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq devStringDataOutput(%rip), %rsi
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movb $1, %bl
testl %eax, %eax
jne .LBB2_8
.LBB2_9:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str.5, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.LBB2_4:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.LBB2_6:
movq stderr(%rip), %r14
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str.7, %esi
movq %r14, %rdi
movl %ebp, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.Lfunc_end2:
.size _Z6cdItoaPjP10StringData, .Lfunc_end2-_Z6cdItoaPjP10StringData
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cdItoaDevicePjP10StringData, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type devDataInput,@object # @devDataInput
.bss
.globl devDataInput
.p2align 3, 0x0
devDataInput:
.quad 0
.size devDataInput, 8
.type devStringDataOutput,@object # @devStringDataOutput
.globl devStringDataOutput
.p2align 3, 0x0
devStringDataOutput:
.quad 0
.size devStringDataOutput, 8
.type dataCount,@object # @dataCount
.globl dataCount
.p2align 2, 0x0
dataCount:
.long 0 # 0x0
.size dataCount, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipSetDevice error: %d\r\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), hipHostMallocWriteCombined)"
.size .L.str.1, 101
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/vovaprog/learn/master/tools/cuda/cuda_itoa/cuda_itoa.hip"
.size .L.str.2, 114
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0)"
.size .L.str.3, 75
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc error: %d\r\n"
.size .L.str.4, 22
.type _Z12cdItoaDevicePjP10StringData,@object # @_Z12cdItoaDevicePjP10StringData
.section .rodata,"a",@progbits
.globl _Z12cdItoaDevicePjP10StringData
.p2align 3, 0x0
_Z12cdItoaDevicePjP10StringData:
.quad _Z27__device_stub__cdItoaDevicePjP10StringData
.size _Z12cdItoaDevicePjP10StringData, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "hipMemcpy error: %d\r\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "cuda error: %s\r\n"
.size .L.str.6, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceSynchronize error: %d %s\r\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CUDA error at %s:%d code=%d(%s) \"%s\" \n"
.size .L.str.8, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12cdItoaDevicePjP10StringData"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cdItoaDevicePjP10StringData
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym devDataInput
.addrsig_sym devStringDataOutput
.addrsig_sym _Z12cdItoaDevicePjP10StringData
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12cdItoaDevicePjP10StringData
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0204 */
/*0080*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*0090*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.36441802978515625e-07 ; /* 0x00000009ff007435 */
/* 0x000fe200000001ff */
/*00a0*/ BSSY B0, 0x190 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe20000011403 */
/*00c0*/ STL.U8 [R1+0xa], RZ ; /* 0x00000aff01007387 */
/* 0x0001e80000100000 */
/*00d0*/ IMAD.WIDE.U32 R4, R6.reuse, -0x33333333, RZ ; /* 0xcccccccd06047825 */
/* 0x061fe200078e00ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fc60003f04070 */
/*00f0*/ IMAD.IADD R7, R1, 0x1, R0.reuse ; /* 0x0000000101077824 */
/* 0x100fe200078e0200 */
/*0100*/ SHF.R.U32.HI R9, RZ, 0x3, R5 ; /* 0x00000003ff097819 */
/* 0x000fe20000011605 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0000 */
/*0120*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc60007ffe0ff */
/*0130*/ IMAD R4, R9, -0xa, R6 ; /* 0xfffffff609047824 */
/* 0x000fe200078e0206 */
/*0140*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fc80000000f00 */
/*0150*/ LOP3.LUT R4, R4, 0x30, RZ, 0xfc, !PT ; /* 0x0000003004047812 */
/* 0x000fca00078efcff */
/*0160*/ STL.U8 [R7], R4 ; /* 0x0000000407007387 */
/* 0x0001e20000100000 */
/*0170*/ @P0 BRA 0xd0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, 0xb ; /* 0x0000000bff007424 */
/* 0x000fe200078e00ff */
/*01a0*/ BSSY B0, 0x2b0 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD R11, R2, 0xb, RZ ; /* 0x0000000b020b7824 */
/* 0x000fe200078e02ff */
/*01c0*/ PRMT R7, R4, 0x7610, R7 ; /* 0x0000761004077816 */
/* 0x001fe20000000007 */
/*01d0*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0000 */
/*01e0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0005 */
/*0200*/ IMAD.IADD R8, R3, 0x1, R11 ; /* 0x0000000103087824 */
/* 0x000fe400078e020b */
/*0210*/ IADD3 R4, P0, R9.reuse, R2, RZ ; /* 0x0000000209047210 */
/* 0x040fe40007f1e0ff */
/*0220*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0230*/ LEA.HI.X.SX32 R5, R9, R8, 0x1, P0 ; /* 0x0000000809057211 */
/* 0x000fe400000f0eff */
/*0240*/ IADD3 R6, R1, R0, RZ ; /* 0x0000000001067210 */
/* 0x000fc60007ffe0ff */
/*0250*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c101104 */
/*0260*/ LDL.U8 R7, [R6] ; /* 0x0000000006077983 */
/* 0x001ea20000100000 */
/*0270*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x004fda0003f05270 */
/*0290*/ @P0 BRA 0x210 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ STG.E.U8 [R4.64+0x1], RZ ; /* 0x000001ff04007986 */
/* 0x000fe2000c101104 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cdItoaDevicePjP10StringData
.globl _Z12cdItoaDevicePjP10StringData
.p2align 8
.type _Z12cdItoaDevicePjP10StringData,@function
_Z12cdItoaDevicePjP10StringData:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b64 s[6:7], 9
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_1:
v_lshlrev_b16 v4, 8, v9
v_and_b32_e32 v9, 0xff, v12
v_lshlrev_b16 v12, 8, v13
s_waitcnt vmcnt(0)
v_mul_hi_u32 v13, v2, 0xcccccccd
v_lshlrev_b16 v5, 8, v16
v_and_b32_e32 v11, 0xff, v11
v_lshlrev_b16 v8, 8, v8
v_and_b32_e32 v10, 0xff, v10
s_cmp_eq_u32 s6, 5
v_cmp_gt_u32_e32 vcc_lo, 10, v2
s_cselect_b32 s2, -1, 0
v_or_b32_e32 v11, v11, v8
v_and_b32_e32 v8, 0xffff, v5
v_or_b32_e32 v5, v9, v5
v_lshrrev_b32_e32 v9, 3, v13
v_and_b32_e32 v3, 0xff, v14
v_or_b32_e32 v10, v10, v12
s_cmp_eq_u32 s6, 3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v13, v9, 10
v_or_b32_e32 v14, v3, v4
v_and_b32_e32 v4, 0xffff, v11
v_lshlrev_b32_e32 v12, 16, v10
s_cselect_b32 s3, -1, 0
s_cmp_eq_u32 s6, 10
v_lshlrev_b32_e32 v3, 16, v14
s_cselect_b32 s4, -1, 0
v_or_b32_e32 v4, v4, v12
v_lshrrev_b32_e32 v16, 24, v12
s_cmp_eq_u32 s6, 9
v_or_b32_e32 v8, v8, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v12, 8, v4
v_lshrrev_b64 v[3:4], 24, v[3:4]
v_lshrrev_b32_e32 v4, 8, v8
v_sub_nc_u32_e32 v8, v2, v13
v_mov_b32_e32 v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v15, 48, v8
v_cndmask_b32_e64 v8, v12, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 8
v_cndmask_b32_e64 v7, v7, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 6
v_cndmask_b32_e64 v6, v6, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 4
v_cndmask_b32_e64 v10, v10, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 2
v_cndmask_b32_e64 v11, v11, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 0
v_cndmask_b32_e64 v14, v14, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 7
v_cndmask_b32_e64 v12, v5, v15, s2
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 1
v_cndmask_b32_e64 v13, v16, v15, s2
s_cselect_b32 s2, -1, 0
s_add_u32 s6, s6, -1
v_cndmask_b32_e64 v9, v3, v15, s3
v_cndmask_b32_e64 v0, v0, v15, s4
s_addc_u32 s7, s7, -1
v_cndmask_b32_e64 v16, v4, v15, s2
v_mov_b32_e32 v4, s6
s_or_b32 s5, vcc_lo, s5
v_mov_b32_e32 v5, s7
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 11, s[0:1]
v_add_nc_u32_e32 v1, 2, v4
s_mov_b32 s1, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 1, v1
global_store_b8 v[2:3], v15, off
v_cndmask_b32_e32 v4, v12, v16, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 2, v1
v_cndmask_b32_e32 v4, v4, v14, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v1
v_cndmask_b32_e32 v4, v4, v11, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 6, v1
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 7, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v13, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 8, v1
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 10, v1
v_add_nc_u32_e32 v1, 1, v1
v_cndmask_b32_e32 v15, v4, v0, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, 0xff, v15
v_cmp_eq_u16_e64 s0, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v0, 0
global_store_b8 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cdItoaDevicePjP10StringData
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cdItoaDevicePjP10StringData, .Lfunc_end0-_Z12cdItoaDevicePjP10StringData
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cdItoaDevicePjP10StringData
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cdItoaDevicePjP10StringData.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017446d_00000000-6_cuda_itoa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18uintToStringDevicejPc
.type _Z18uintToStringDevicejPc, @function
_Z18uintToStringDevicejPc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z18uintToStringDevicejPc, .-_Z18uintToStringDevicejPc
.globl _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
.type _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData, @function
_Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12cdItoaDevicePjP10StringData(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData, .-_Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
.globl _Z12cdItoaDevicePjP10StringData
.type _Z12cdItoaDevicePjP10StringData, @function
_Z12cdItoaDevicePjP10StringData:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12cdItoaDevicePjP10StringData, .-_Z12cdItoaDevicePjP10StringData
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMemcpy error: %d\r\n"
.LC1:
.string "cuda error: %s\r\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cudaDeviceSynchronize error: %d %s\r\n"
.text
.globl _Z6cdItoaPjP10StringData
.type _Z6cdItoaPjP10StringData, @function
_Z6cdItoaPjP10StringData:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %rbx
movl dataCount(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq devDataInput(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
movl dataCount(%rip), %eax
shrl $10, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L23
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L24
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rdx
movl $2, %ecx
movq devStringDataOutput(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
je .L13
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L13
.L21:
movl %eax, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
.L13:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq devStringDataOutput(%rip), %rsi
movq devDataInput(%rip), %rdi
call _Z45__device_stub__Z12cdItoaDevicePjP10StringDataPjP10StringData
jmp .L16
.L23:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L13
.L24:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L13
.cfi_endproc
.LFE2060:
.size _Z6cdItoaPjP10StringData, .-_Z6cdItoaPjP10StringData
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z12cdItoaDevicePjP10StringData"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cdItoaDevicePjP10StringData(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z5checkI9cudaErrorEvT_PKcS3_i.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "CUDA error at %s:%d code=%d(%s) \"%s\" \n"
.section .text._Z5checkI9cudaErrorEvT_PKcS3_i,"axG",@progbits,_Z5checkI9cudaErrorEvT_PKcS3_i,comdat
.weak _Z5checkI9cudaErrorEvT_PKcS3_i
.type _Z5checkI9cudaErrorEvT_PKcS3_i, @function
_Z5checkI9cudaErrorEvT_PKcS3_i:
.LFB2134:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L32
ret
.L32:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movq %rdx, %rbp
movl %ecx, %r12d
call cudaGetErrorString@PLT
pushq %r13
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
movl %ebx, %r9d
movl %r12d, %r8d
movq %rbp, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 48
call cudaDeviceReset@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2134:
.size _Z5checkI9cudaErrorEvT_PKcS3_i, .-_Z5checkI9cudaErrorEvT_PKcS3_i
.section .rodata.str1.1
.LC5:
.string "cudaSetDevice error: %d\r\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/vovaprog/learn/master/tools/cuda/cuda_itoa/cuda_itoa.cu"
.align 8
.LC7:
.string "cudaHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), cudaHostAllocWriteCombined)"
.align 8
.LC8:
.string "cudaHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0)"
.section .rodata.str1.1
.LC9:
.string "cudaMalloc error: %d\r\n"
.text
.globl _Z6cdInitjPPvS0_b
.type _Z6cdInitjPPvS0_b, @function
_Z6cdInitjPPvS0_b:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movq %rdx, %rbp
movl %ecx, %ebx
movl %edi, dataCount(%rip)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L41
testb %bl, %bl
je .L36
movl dataCount(%rip), %esi
salq $2, %rsi
movl $4, %edx
movq %r12, %rdi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $41, %ecx
leaq .LC6(%rip), %rbx
movq %rbx, %rdx
leaq .LC7(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rsi
movl $0, %edx
movq %rbp, %rdi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $42, %ecx
movq %rbx, %rdx
leaq .LC8(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
.L37:
movl dataCount(%rip), %esi
salq $2, %rsi
leaq devDataInput(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rdx
leaq (%rax,%rdx,2), %rsi
leaq devStringDataOutput(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .L43
.L33:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %eax, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L33
.L36:
movl dataCount(%rip), %r13d
leaq 0(,%r13,4), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%r12)
addq %r13, %rbx
leaq 0(%r13,%rbx,2), %rdi
call malloc@PLT
movq %rax, 0(%rbp)
jmp .L37
.L42:
movl %eax, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L33
.L43:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
jmp .L33
.cfi_endproc
.LFE2058:
.size _Z6cdInitjPPvS0_b, .-_Z6cdInitjPPvS0_b
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dataCount
.bss
.align 4
.type dataCount, @object
.size dataCount, 4
dataCount:
.zero 4
.globl devStringDataOutput
.align 8
.type devStringDataOutput, @object
.size devStringDataOutput, 8
devStringDataOutput:
.zero 8
.globl devDataInput
.align 8
.type devDataInput, @object
.size devDataInput, 8
devDataInput:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_itoa.hip"
.globl _Z6cdInitjPPvS0_b # -- Begin function _Z6cdInitjPPvS0_b
.p2align 4, 0x90
.type _Z6cdInitjPPvS0_b,@function
_Z6cdInitjPPvS0_b: # @_Z6cdInitjPPvS0_b
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, dataCount(%rip)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.2:
movl dataCount(%rip), %r15d
leaq (,%r15,4), %rsi
testb %bpl, %bpl
je .LBB0_8
# %bb.3:
movq %r14, %rdi
movl $4, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB0_4
# %bb.6: # %_Z5checkI10hipError_tEvT_PKcS3_i.exit
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rsi
movq %rbx, %rdi
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
je .LBB0_9
# %bb.7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movq $.L.str.3, (%rsp)
movl $.L.str.8, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $44, %ecx
jmp .LBB0_5
.LBB0_8:
movq %rsi, %rdi
callq malloc
movq %rax, (%r14)
leaq (%r15,%r15,4), %rax
leaq (%r15,%rax,2), %rdi
callq malloc
movq %rax, (%rbx)
.LBB0_9: # %_Z5checkI10hipError_tEvT_PKcS3_i.exit18
movl dataCount(%rip), %esi
shlq $2, %rsi
movl $devDataInput, %edi
callq hipMalloc
testl %eax, %eax
jne .LBB0_11
# %bb.10:
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rsi
movl $devStringDataOutput, %edi
callq hipMalloc
movb $1, %bl
testl %eax, %eax
jne .LBB0_11
.LBB0_13:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str.4, %esi
jmp .LBB0_12
.LBB0_1:
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str, %esi
.LBB0_12:
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB0_13
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movq $.L.str.1, (%rsp)
movl $.L.str.8, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $43, %ecx
.LBB0_5:
movl %ebp, %r8d
movq %rax, %r9
xorl %eax, %eax
callq fprintf
callq hipDeviceReset
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z6cdInitjPPvS0_b, .Lfunc_end0-_Z6cdInitjPPvS0_b
.cfi_endproc
# -- End function
.globl _Z27__device_stub__cdItoaDevicePjP10StringData # -- Begin function _Z27__device_stub__cdItoaDevicePjP10StringData
.p2align 4, 0x90
.type _Z27__device_stub__cdItoaDevicePjP10StringData,@function
_Z27__device_stub__cdItoaDevicePjP10StringData: # @_Z27__device_stub__cdItoaDevicePjP10StringData
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12cdItoaDevicePjP10StringData, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__cdItoaDevicePjP10StringData, .Lfunc_end1-_Z27__device_stub__cdItoaDevicePjP10StringData
.cfi_endproc
# -- End function
.globl _Z6cdItoaPjP10StringData # -- Begin function _Z6cdItoaPjP10StringData
.p2align 4, 0x90
.type _Z6cdItoaPjP10StringData,@function
_Z6cdItoaPjP10StringData: # @_Z6cdItoaPjP10StringData
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %rsi
movq devDataInput(%rip), %rdi
movl dataCount(%rip), %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.1:
movl dataCount(%rip), %edx
shrl $10, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1024, %rdi # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq devDataInput(%rip), %rax
movq devStringDataOutput(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12cdItoaDevicePjP10StringData, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_4
# %bb.5:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq devStringDataOutput(%rip), %rsi
movl dataCount(%rip), %eax
leaq (%rax,%rax,4), %rcx
leaq (%rax,%rcx,2), %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movb $1, %bl
testl %eax, %eax
jne .LBB2_8
.LBB2_9:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rdi
xorl %ebx, %ebx
movl $.L.str.5, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.LBB2_4:
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str.6, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.LBB2_6:
movq stderr(%rip), %r14
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
xorl %ebx, %ebx
movl $.L.str.7, %esi
movq %r14, %rdi
movl %ebp, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
jmp .LBB2_9
.Lfunc_end2:
.size _Z6cdItoaPjP10StringData, .Lfunc_end2-_Z6cdItoaPjP10StringData
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cdItoaDevicePjP10StringData, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type devDataInput,@object # @devDataInput
.bss
.globl devDataInput
.p2align 3, 0x0
devDataInput:
.quad 0
.size devDataInput, 8
.type devStringDataOutput,@object # @devStringDataOutput
.globl devStringDataOutput
.p2align 3, 0x0
devStringDataOutput:
.quad 0
.size devStringDataOutput, 8
.type dataCount,@object # @dataCount
.globl dataCount
.p2align 2, 0x0
dataCount:
.long 0 # 0x0
.size dataCount, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipSetDevice error: %d\r\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipHostAlloc((void **)hostInputMemory, dataCount * sizeof(unsigned int), hipHostMallocWriteCombined)"
.size .L.str.1, 101
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/vovaprog/learn/master/tools/cuda/cuda_itoa/cuda_itoa.hip"
.size .L.str.2, 114
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipHostAlloc((void **)hostOutputMemory, dataCount * sizeof(StringData), 0)"
.size .L.str.3, 75
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc error: %d\r\n"
.size .L.str.4, 22
.type _Z12cdItoaDevicePjP10StringData,@object # @_Z12cdItoaDevicePjP10StringData
.section .rodata,"a",@progbits
.globl _Z12cdItoaDevicePjP10StringData
.p2align 3, 0x0
_Z12cdItoaDevicePjP10StringData:
.quad _Z27__device_stub__cdItoaDevicePjP10StringData
.size _Z12cdItoaDevicePjP10StringData, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "hipMemcpy error: %d\r\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "cuda error: %s\r\n"
.size .L.str.6, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipDeviceSynchronize error: %d %s\r\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CUDA error at %s:%d code=%d(%s) \"%s\" \n"
.size .L.str.8, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12cdItoaDevicePjP10StringData"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cdItoaDevicePjP10StringData
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym devDataInput
.addrsig_sym devStringDataOutput
.addrsig_sym _Z12cdItoaDevicePjP10StringData
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
#include <cstdio>
#include <ctime>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void sum_shared_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
// Share among threads within the same block
__shared__ float sh_array[1024];
sh_array[idx] = array[idx];
// Syncronize threads within the same block
__syncthreads();
for (int i=0; i<=idx; i++){
sum+= sh_array[i];
}
__syncthreads();
array[idx] = sum;
}
__global__ void sum_global_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
for (int i=0; i<=idx; i++){
sum+= array[i];
}
__syncthreads();
array[idx] = sum;
}
int main(void)
{
std::clock_t start_time;
double duration01;
double duration02;
double duration03;
const int ARR_BYTES = 1024*sizeof(float);
// Clock start
start_time = std::clock();
// Declare and alloc array on host
float h_array[1024];
// initialize input array
for (int i=0; i<1024; i++){
h_array[i] = float(i);
}
// Declare and alloc array on device
float *d_array;
cudaMalloc(&d_array, ARR_BYTES);
// Transfer to device
cudaMemcpy(d_array, h_array, ARR_BYTES, cudaMemcpyHostToDevice);
// Clock stop 01
duration01 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time before Kernel call: "<< duration01 << "s" << std::endl;
// Call kernel function with shared memory
sum_shared_mem<<<1, 1024>>>(d_array);
// Call kernel function with shared memory
// sum_global_mem<<<1, 1024>>>(d_array);
// Clock stop 02
duration02 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after Kernel call: "<< duration02 << "s" << std::endl;
// Transfer results to host
cudaMemcpy(h_array, d_array, ARR_BYTES, cudaMemcpyDeviceToHost);
// Clock stop 03
duration03 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after memory copy: "<< duration03 << "s" << std::endl;
// Output results
for(int ii=0; ii<10; ii++){
std::cout<< h_array[ii]<< ", ";
}
std::cout<< std::endl;
return 0;
} | code for sm_80
Function : _Z14sum_global_memPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0x820 ; /* 0x000007e000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f06270 */
/*0060*/ @!P0 BRA 0x810 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x3, PT ; /* 0x000000030000780c */
/* 0x040fe20003f06070 */
/*0080*/ BSSY B1, 0x740 ; /* 0x000006b000017945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00c0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fce00078ec0ff */
/*00d0*/ @!P0 BRA 0x730 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R7, -R5, R0, RZ ; /* 0x0000000005077210 */
/* 0x000fe20007ffe1ff */
/*00f0*/ BSSY B0, 0x630 ; /* 0x0000053000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GT.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fd60000000f00 */
/*0150*/ @!P0 BRA 0x620 ; /* 0x000004c000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x000fe20007ffe0ff */
/*0170*/ BSSY B3, 0x430 ; /* 0x000002b000037945 */
/* 0x000fe20003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01a0*/ @!P1 BRA 0x420 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x0000a8000c1e1900 */
/*01d0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x0000e8000c1e1900 */
/*01e0*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000128000c1e1900 */
/*01f0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000168000c1e1900 */
/*0200*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000168000c1e1900 */
/*0210*/ LDG.E R26, [R2.64+0x14] ; /* 0x00001404021a7981 */
/* 0x000168000c1e1900 */
/*0220*/ LDG.E R28, [R2.64+0x18] ; /* 0x00001804021c7981 */
/* 0x000168000c1e1900 */
/*0230*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000168000c1e1900 */
/*0240*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R12, [R2.64+0x2c] ; /* 0x00002c04020c7981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R11, [R2.64+0x30] ; /* 0x00003004020b7981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R10, [R2.64+0x38] ; /* 0x00003804020a7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0402087981 */
/* 0x000162000c1e1900 */
/*02c0*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GT.AND P1, PT, R7, 0xb, PT ; /* 0x0000000b0700780c */
/* 0x000fe40003f24270 */
/*02f0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*0300*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0310*/ FADD R17, R17, R4 ; /* 0x0000000411117221 */
/* 0x004fc80000000000 */
/*0320*/ FADD R17, R17, R18 ; /* 0x0000001211117221 */
/* 0x008fc80000000000 */
/*0330*/ FADD R17, R17, R20 ; /* 0x0000001411117221 */
/* 0x010fc80000000000 */
/*0340*/ FADD R17, R17, R22 ; /* 0x0000001611117221 */
/* 0x020fc80000000000 */
/*0350*/ FADD R17, R17, R24 ; /* 0x0000001811117221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R17, R17, R26 ; /* 0x0000001a11117221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R17, R17, R28 ; /* 0x0000001c11117221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R15, R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R14, R15, R14 ; /* 0x0000000e0f0e7221 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R13, R14, R13 ; /* 0x0000000d0e0d7221 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x000fc80000000000 */
/*03d0*/ FADD R12, R12, R11 ; /* 0x0000000b0c0c7221 */
/* 0x000fc80000000000 */
/*03e0*/ FADD R9, R12, R9 ; /* 0x000000090c097221 */
/* 0x000fc80000000000 */
/*03f0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x000fc80000000000 */
/*0400*/ FADD R4, R9, R8 ; /* 0x0000000809047221 */
/* 0x000fe20000000000 */
/*0410*/ @P1 BRA 0x1c0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x000fe20007ffe0ff */
/*0440*/ BSSY B3, 0x5f0 ; /* 0x000001a000037945 */
/* 0x000fe60003800000 */
/*0450*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0460*/ @!P1 BRA 0x5e0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*0490*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000f28000c1e1900 */
/*04a0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000168000c1e1900 */
/*04b0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R19, [R2.64+0x18] ; /* 0x0000180402137981 */
/* 0x000168000c1e1900 */
/*04e0*/ LDG.E R21, [R2.64+0x1c] ; /* 0x00001c0402157981 */
/* 0x000162000c1e1900 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0500*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0510*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0520*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x004fc80000000000 */
/*0530*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x008fe20000000000 */
/*0540*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fc60007f3e0ff */
/*0550*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x010fe20000000000 */
/*0560*/ IADD3.X R10, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0a7210 */
/* 0x000fe20000ffe4ff */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0009 */
/*0580*/ FADD R8, R8, R13 ; /* 0x0000000d08087221 */
/* 0x020fe20000000000 */
/*0590*/ MOV R3, R10 ; /* 0x0000000a00037202 */
/* 0x000fc60000000f00 */
/*05a0*/ FADD R8, R8, R15 ; /* 0x0000000f08087221 */
/* 0x000fc80000000000 */
/*05b0*/ FADD R8, R8, R17 ; /* 0x0000001108087221 */
/* 0x000fc80000000000 */
/*05c0*/ FADD R8, R8, R19 ; /* 0x0000001308087221 */
/* 0x000fc80000000000 */
/*05d0*/ FADD R4, R8, R21 ; /* 0x0000001508047221 */
/* 0x000fe40000000000 */
/*05e0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.OR P0, PT, R7, -0x1, P0 ; /* 0xffffffff0700780c */
/* 0x000fda0000705670 */
/*0600*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0610*/ @!P0 BRA 0x730 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000f28000c1e1900 */
/*0660*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000162000c1e1900 */
/*0670*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fe20003f05270 */
/*06a0*/ FADD R9, R9, R4 ; /* 0x0000000409097221 */
/* 0x004fc80000000000 */
/*06b0*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x008fe20000000000 */
/*06c0*/ IADD3 R9, P1, R2, 0x10, RZ ; /* 0x0000001002097810 */
/* 0x000fc60007f3e0ff */
/*06d0*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x010fe20000000000 */
/*06e0*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x001fe20000000f00 */
/*06f0*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe400008e0603 */
/*0700*/ FADD R4, R8, R13 ; /* 0x0000000d08047221 */
/* 0x020fe40000000000 */
/*0710*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0720*/ @P0 BRA 0x630 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0730*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0750*/ @!P0 BRA 0x810 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0760*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0770*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0790*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fca0000000f00 */
/*07a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*07d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*07e0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*07f0*/ FADD R4, R3, R4 ; /* 0x0000000403047221 */
/* 0x004fd40000000000 */
/*0800*/ @P0 BRA 0x780 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0810*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0820*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0830*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0840*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0850*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0860*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101904 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14sum_shared_memPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R22, R3, R22, c[0x0][0x160] ; /* 0x0000580003167625 */
/* 0x001fca00078e0216 */
/*0050*/ LDG.E R2, [R22.64] ; /* 0x0000000416027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0070*/ BSSY B2, 0x660 ; /* 0x000005e000027945 */
/* 0x000fe20003800000 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0090*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x0041e80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ @!P0 BRA 0x650 ; /* 0x0000059000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x041fe20003f06070 */
/*00d0*/ BSSY B1, 0x5c0 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*00e0*/ IADD3 R21, R3, 0x1, RZ ; /* 0x0000000103157810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fc40000000f00 */
/*0110*/ LOP3.LUT R21, R21, 0x3, RZ, 0xc0, !PT ; /* 0x0000000315157812 */
/* 0x000fce00078ec0ff */
/*0120*/ @!P0 BRA 0x5b0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.IADD R3, R3, 0x1, -R21 ; /* 0x0000000103037824 */
/* 0x000fe200078e0a15 */
/*0140*/ BSSY B0, 0x510 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0150*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0160*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0180*/ ISETP.GT.AND P0, PT, R3, -0x1, PT ; /* 0xffffffff0300780c */
/* 0x000fda0003f04270 */
/*0190*/ @!P0 BRA 0x500 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B3, 0x3a0 ; /* 0x000001e000037945 */
/* 0x000fe20003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01d0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*01e0*/ @!P1 BRA 0x390 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDS.128 R4, [R20] ; /* 0x0000000014047984 */
/* 0x000e220000000c00 */
/*0210*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDS.128 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x000e620000000c00 */
/*0240*/ ISETP.GT.AND P1, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fc60003f24270 */
/*0250*/ LDS.128 R12, [R20+0x20] ; /* 0x00002000140c7984 */
/* 0x000ea80000000c00 */
/*0260*/ LDS.128 R16, [R20+0x30] ; /* 0x0000300014107984 */
/* 0x0007240000000c00 */
/*0270*/ IADD3 R20, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x008fe20007ffe0ff */
/*0280*/ FADD R4, R4, R0 ; /* 0x0000000004047221 */
/* 0x001fc80000000000 */
/*0290*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*02a0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*02b0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02c0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fc80000000000 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0300*/ FADD R12, R11, R12 ; /* 0x0000000c0b0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x010fc80000000000 */
/*0350*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R0, R18, R19 ; /* 0x0000001312007221 */
/* 0x000fe20000000000 */
/*0380*/ @P1 BRA 0x200 ; /* 0xfffffe7000001947 */
/* 0x000fea000383ffff */
/*0390*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B3, 0x4d0 ; /* 0x0000011000037945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*03d0*/ @!P1 BRA 0x4c0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*03e0*/ LDS.128 R4, [R20] ; /* 0x0000000014047984 */
/* 0x000e220000000c00 */
/*03f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0400*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe20007ffe0ff */
/*0410*/ LDS.128 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x0002a20000000c00 */
/*0420*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R20, R20, 0x20, RZ ; /* 0x0000002014147810 */
/* 0x002fe20007ffe0ff */
/*0440*/ FADD R4, R0, R4 ; /* 0x0000000400047221 */
/* 0x001fc80000000000 */
/*0450*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R0, R10, R11 ; /* 0x0000000b0a007221 */
/* 0x000fe40000000000 */
/*04c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.OR P0, PT, R3, -0x1, P0 ; /* 0xffffffff0300780c */
/* 0x000fda0000705670 */
/*04e0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x5b0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ LDS.128 R4, [R20] ; /* 0x0000000014047984 */
/* 0x0000620000000c00 */
/*0520*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R3, -0x1, PT ; /* 0xffffffff0300780c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x001fe20007ffe0ff */
/*0560*/ FADD R4, R4, R0 ; /* 0x0000000004047221 */
/* 0x002fc80000000000 */
/*0570*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0580*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0590*/ FADD R0, R6, R7 ; /* 0x0000000706007221 */
/* 0x000fe20000000000 */
/*05a0*/ @P0 BRA 0x510 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*05b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*05d0*/ @!P0 BRA 0x650 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*05e0*/ SHF.L.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027819 */
/* 0x000fca00000006ff */
/*05f0*/ LDS R3, [R2] ; /* 0x0000000002037984 */
/* 0x0000620000000800 */
/*0600*/ IADD3 R21, R21, -0x1, RZ ; /* 0xffffffff15157810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05270 */
/*0620*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe20007ffe0ff */
/*0630*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x002fd40000000000 */
/*0640*/ @P0 BRA 0x5f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0650*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0660*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ STG.E [R22.64], R0 ; /* 0x0000000016007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <cstdio>
#include <ctime>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void sum_shared_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
// Share among threads within the same block
__shared__ float sh_array[1024];
sh_array[idx] = array[idx];
// Syncronize threads within the same block
__syncthreads();
for (int i=0; i<=idx; i++){
sum+= sh_array[i];
}
__syncthreads();
array[idx] = sum;
}
__global__ void sum_global_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
for (int i=0; i<=idx; i++){
sum+= array[i];
}
__syncthreads();
array[idx] = sum;
}
int main(void)
{
std::clock_t start_time;
double duration01;
double duration02;
double duration03;
const int ARR_BYTES = 1024*sizeof(float);
// Clock start
start_time = std::clock();
// Declare and alloc array on host
float h_array[1024];
// initialize input array
for (int i=0; i<1024; i++){
h_array[i] = float(i);
}
// Declare and alloc array on device
float *d_array;
cudaMalloc(&d_array, ARR_BYTES);
// Transfer to device
cudaMemcpy(d_array, h_array, ARR_BYTES, cudaMemcpyHostToDevice);
// Clock stop 01
duration01 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time before Kernel call: "<< duration01 << "s" << std::endl;
// Call kernel function with shared memory
sum_shared_mem<<<1, 1024>>>(d_array);
// Call kernel function with shared memory
// sum_global_mem<<<1, 1024>>>(d_array);
// Clock stop 02
duration02 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after Kernel call: "<< duration02 << "s" << std::endl;
// Transfer results to host
cudaMemcpy(h_array, d_array, ARR_BYTES, cudaMemcpyDeviceToHost);
// Clock stop 03
duration03 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after memory copy: "<< duration03 << "s" << std::endl;
// Output results
for(int ii=0; ii<10; ii++){
std::cout<< h_array[ii]<< ", ";
}
std::cout<< std::endl;
return 0;
} | .file "tmpxft_00137eaa_00000000-6_shared_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14sum_shared_memPfPf
.type _Z34__device_stub__Z14sum_shared_memPfPf, @function
_Z34__device_stub__Z14sum_shared_memPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14sum_shared_memPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z34__device_stub__Z14sum_shared_memPfPf, .-_Z34__device_stub__Z14sum_shared_memPfPf
.globl _Z14sum_shared_memPf
.type _Z14sum_shared_memPf, @function
_Z14sum_shared_memPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14sum_shared_memPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14sum_shared_memPf, .-_Z14sum_shared_memPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Computing time before Kernel call: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "s"
.section .rodata.str1.8
.align 8
.LC3:
.string "Computing time after Kernel call: "
.align 8
.LC4:
.string "Computing time after memory copy: "
.section .rodata.str1.1
.LC5:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $4096, %rsp
.cfi_def_cfa_offset 4136
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 4192
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbp
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 72(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC5(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L14
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $4152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z34__device_stub__Z14sum_shared_memPfPf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z34__device_stub__Z14sum_global_memPfPf
.type _Z34__device_stub__Z14sum_global_memPfPf, @function
_Z34__device_stub__Z14sum_global_memPfPf:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14sum_global_memPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z14sum_global_memPfPf, .-_Z34__device_stub__Z14sum_global_memPfPf
.globl _Z14sum_global_memPf
.type _Z14sum_global_memPf, @function
_Z14sum_global_memPf:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14sum_global_memPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z14sum_global_memPf, .-_Z14sum_global_memPf
.section .rodata.str1.1
.LC6:
.string "_Z14sum_global_memPf"
.LC7:
.string "_Z14sum_shared_memPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sum_global_memPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sum_shared_memPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <cstdio>
#include <ctime>
#include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
__global__ void sum_shared_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
// Share among threads within the same block
__shared__ float sh_array[1024];
sh_array[idx] = array[idx];
// Syncronize threads within the same block
__syncthreads();
for (int i=0; i<=idx; i++){
sum+= sh_array[i];
}
__syncthreads();
array[idx] = sum;
}
__global__ void sum_global_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
for (int i=0; i<=idx; i++){
sum+= array[i];
}
__syncthreads();
array[idx] = sum;
}
int main(void)
{
std::clock_t start_time;
double duration01;
double duration02;
double duration03;
const int ARR_BYTES = 1024*sizeof(float);
// Clock start
start_time = std::clock();
// Declare and alloc array on host
float h_array[1024];
// initialize input array
for (int i=0; i<1024; i++){
h_array[i] = float(i);
}
// Declare and alloc array on device
float *d_array;
cudaMalloc(&d_array, ARR_BYTES);
// Transfer to device
cudaMemcpy(d_array, h_array, ARR_BYTES, cudaMemcpyHostToDevice);
// Clock stop 01
duration01 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time before Kernel call: "<< duration01 << "s" << std::endl;
// Call kernel function with shared memory
sum_shared_mem<<<1, 1024>>>(d_array);
// Call kernel function with shared memory
// sum_global_mem<<<1, 1024>>>(d_array);
// Clock stop 02
duration02 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after Kernel call: "<< duration02 << "s" << std::endl;
// Transfer results to host
cudaMemcpy(h_array, d_array, ARR_BYTES, cudaMemcpyDeviceToHost);
// Clock stop 03
duration03 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after memory copy: "<< duration03 << "s" << std::endl;
// Output results
for(int ii=0; ii<10; ii++){
std::cout<< h_array[ii]<< ", ";
}
std::cout<< std::endl;
return 0;
} | #include <cmath>
#include <cstdio>
#include <ctime>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void sum_shared_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
// Share among threads within the same block
__shared__ float sh_array[1024];
sh_array[idx] = array[idx];
// Syncronize threads within the same block
__syncthreads();
for (int i=0; i<=idx; i++){
sum+= sh_array[i];
}
__syncthreads();
array[idx] = sum;
}
__global__ void sum_global_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
for (int i=0; i<=idx; i++){
sum+= array[i];
}
__syncthreads();
array[idx] = sum;
}
int main(void)
{
std::clock_t start_time;
double duration01;
double duration02;
double duration03;
const int ARR_BYTES = 1024*sizeof(float);
// Clock start
start_time = std::clock();
// Declare and alloc array on host
float h_array[1024];
// initialize input array
for (int i=0; i<1024; i++){
h_array[i] = float(i);
}
// Declare and alloc array on device
float *d_array;
hipMalloc(&d_array, ARR_BYTES);
// Transfer to device
hipMemcpy(d_array, h_array, ARR_BYTES, hipMemcpyHostToDevice);
// Clock stop 01
duration01 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time before Kernel call: "<< duration01 << "s" << std::endl;
// Call kernel function with shared memory
sum_shared_mem<<<1, 1024>>>(d_array);
// Call kernel function with shared memory
// sum_global_mem<<<1, 1024>>>(d_array);
// Clock stop 02
duration02 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after Kernel call: "<< duration02 << "s" << std::endl;
// Transfer results to host
hipMemcpy(h_array, d_array, ARR_BYTES, hipMemcpyDeviceToHost);
// Clock stop 03
duration03 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after memory copy: "<< duration03 << "s" << std::endl;
// Output results
for(int ii=0; ii<10; ii++){
std::cout<< h_array[ii]<< ", ";
}
std::cout<< std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cmath>
#include <cstdio>
#include <ctime>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void sum_shared_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
// Share among threads within the same block
__shared__ float sh_array[1024];
sh_array[idx] = array[idx];
// Syncronize threads within the same block
__syncthreads();
for (int i=0; i<=idx; i++){
sum+= sh_array[i];
}
__syncthreads();
array[idx] = sum;
}
__global__ void sum_global_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
for (int i=0; i<=idx; i++){
sum+= array[i];
}
__syncthreads();
array[idx] = sum;
}
int main(void)
{
std::clock_t start_time;
double duration01;
double duration02;
double duration03;
const int ARR_BYTES = 1024*sizeof(float);
// Clock start
start_time = std::clock();
// Declare and alloc array on host
float h_array[1024];
// initialize input array
for (int i=0; i<1024; i++){
h_array[i] = float(i);
}
// Declare and alloc array on device
float *d_array;
hipMalloc(&d_array, ARR_BYTES);
// Transfer to device
hipMemcpy(d_array, h_array, ARR_BYTES, hipMemcpyHostToDevice);
// Clock stop 01
duration01 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time before Kernel call: "<< duration01 << "s" << std::endl;
// Call kernel function with shared memory
sum_shared_mem<<<1, 1024>>>(d_array);
// Call kernel function with shared memory
// sum_global_mem<<<1, 1024>>>(d_array);
// Clock stop 02
duration02 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after Kernel call: "<< duration02 << "s" << std::endl;
// Transfer results to host
hipMemcpy(h_array, d_array, ARR_BYTES, hipMemcpyDeviceToHost);
// Clock stop 03
duration03 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after memory copy: "<< duration03 << "s" << std::endl;
// Output results
for(int ii=0; ii<10; ii++){
std::cout<< h_array[ii]<< ", ";
}
std::cout<< std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sum_shared_memPf
.globl _Z14sum_shared_memPf
.p2align 8
.type _Z14sum_shared_memPf,@function
_Z14sum_shared_memPf:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, 1, v0
s_mov_b32 s1, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v4, s[2:3]
v_add_co_u32 v0, s2, s2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_1:
v_dual_mov_b32 v4, s1 :: v_dual_add_nc_u32 v3, -1, v3
s_add_i32 s1, s1, 4
ds_load_b32 v4, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_or_b32 s0, vcc_lo, s0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s0
s_barrier
buffer_gl0_inv
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sum_shared_memPf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sum_shared_memPf, .Lfunc_end0-_Z14sum_shared_memPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14sum_global_memPf
.globl _Z14sum_global_memPf
.p2align 8
.type _Z14sum_global_memPf,@function
_Z14sum_global_memPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[2:3], s[0:1]
.LBB1_1:
s_load_b32 s5, s[2:3], 0x0
v_add_nc_u32_e32 v2, -1, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, s5, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB1_1
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v0, 2, v0
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sum_global_memPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14sum_global_memPf, .Lfunc_end1-_Z14sum_global_memPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sum_shared_memPf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14sum_shared_memPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sum_global_memPf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14sum_global_memPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cmath>
#include <cstdio>
#include <ctime>
#include <iostream>
#include <hip/hip_runtime.h>
__global__ void sum_shared_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
// Share among threads within the same block
__shared__ float sh_array[1024];
sh_array[idx] = array[idx];
// Syncronize threads within the same block
__syncthreads();
for (int i=0; i<=idx; i++){
sum+= sh_array[i];
}
__syncthreads();
array[idx] = sum;
}
__global__ void sum_global_mem(float *array)
{
int idx = threadIdx.x;
float sum=0.0f;
for (int i=0; i<=idx; i++){
sum+= array[i];
}
__syncthreads();
array[idx] = sum;
}
int main(void)
{
std::clock_t start_time;
double duration01;
double duration02;
double duration03;
const int ARR_BYTES = 1024*sizeof(float);
// Clock start
start_time = std::clock();
// Declare and alloc array on host
float h_array[1024];
// initialize input array
for (int i=0; i<1024; i++){
h_array[i] = float(i);
}
// Declare and alloc array on device
float *d_array;
hipMalloc(&d_array, ARR_BYTES);
// Transfer to device
hipMemcpy(d_array, h_array, ARR_BYTES, hipMemcpyHostToDevice);
// Clock stop 01
duration01 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time before Kernel call: "<< duration01 << "s" << std::endl;
// Call kernel function with shared memory
sum_shared_mem<<<1, 1024>>>(d_array);
// Call kernel function with shared memory
// sum_global_mem<<<1, 1024>>>(d_array);
// Clock stop 02
duration02 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after Kernel call: "<< duration02 << "s" << std::endl;
// Transfer results to host
hipMemcpy(h_array, d_array, ARR_BYTES, hipMemcpyDeviceToHost);
// Clock stop 03
duration03 = ( std::clock() - start_time ) / (double) CLOCKS_PER_SEC;
std::cout<<"Computing time after memory copy: "<< duration03 << "s" << std::endl;
// Output results
for(int ii=0; ii<10; ii++){
std::cout<< h_array[ii]<< ", ";
}
std::cout<< std::endl;
return 0;
} | .text
.file "shared_memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__sum_shared_memPf # -- Begin function _Z29__device_stub__sum_shared_memPf
.p2align 4, 0x90
.type _Z29__device_stub__sum_shared_memPf,@function
_Z29__device_stub__sum_shared_memPf: # @_Z29__device_stub__sum_shared_memPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14sum_shared_memPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__sum_shared_memPf, .Lfunc_end0-_Z29__device_stub__sum_shared_memPf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__sum_global_memPf # -- Begin function _Z29__device_stub__sum_global_memPf
.p2align 4, 0x90
.type _Z29__device_stub__sum_global_memPf,@function
_Z29__device_stub__sum_global_memPf: # @_Z29__device_stub__sum_global_memPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14sum_global_memPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z29__device_stub__sum_global_memPf, .Lfunc_end1-_Z29__device_stub__sum_global_memPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 4208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq clock
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 80(%rsp,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_23
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB2_6
.LBB2_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14sum_shared_memPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_23
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r15)
je .LBB2_11
# %bb.10:
movzbl 67(%r15), %eax
jmp .LBB2_12
.LBB2_11:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_23
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%r14)
je .LBB2_15
# %bb.14:
movzbl 67(%r14), %eax
jmp .LBB2_16
.LBB2_15:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB2_17
# %bb.18:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB2_21
# %bb.20:
movzbl 67(%rbx), %eax
jmp .LBB2_22
.LBB2_21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_23:
.cfi_def_cfa_offset 4208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sum_shared_memPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sum_global_memPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sum_shared_memPf,@object # @_Z14sum_shared_memPf
.section .rodata,"a",@progbits
.globl _Z14sum_shared_memPf
.p2align 3, 0x0
_Z14sum_shared_memPf:
.quad _Z29__device_stub__sum_shared_memPf
.size _Z14sum_shared_memPf, 8
.type _Z14sum_global_memPf,@object # @_Z14sum_global_memPf
.globl _Z14sum_global_memPf
.p2align 3, 0x0
_Z14sum_global_memPf:
.quad _Z29__device_stub__sum_global_memPf
.size _Z14sum_global_memPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Computing time before Kernel call: "
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computing time after Kernel call: "
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Computing time after memory copy: "
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ", "
.size .L.str.4, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14sum_shared_memPf"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14sum_global_memPf"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sum_shared_memPf
.addrsig_sym _Z29__device_stub__sum_global_memPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sum_shared_memPf
.addrsig_sym _Z14sum_global_memPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14sum_global_memPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B2, 0x820 ; /* 0x000007e000027945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f06270 */
/*0060*/ @!P0 BRA 0x810 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x3, PT ; /* 0x000000030000780c */
/* 0x040fe20003f06070 */
/*0080*/ BSSY B1, 0x740 ; /* 0x000006b000017945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00c0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fce00078ec0ff */
/*00d0*/ @!P0 BRA 0x730 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R7, -R5, R0, RZ ; /* 0x0000000005077210 */
/* 0x000fe20007ffe1ff */
/*00f0*/ BSSY B0, 0x630 ; /* 0x0000053000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GT.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fd60000000f00 */
/*0150*/ @!P0 BRA 0x620 ; /* 0x000004c000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x000fe20007ffe0ff */
/*0170*/ BSSY B3, 0x430 ; /* 0x000002b000037945 */
/* 0x000fe20003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01a0*/ @!P1 BRA 0x420 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x0000a8000c1e1900 */
/*01d0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x0000e8000c1e1900 */
/*01e0*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000128000c1e1900 */
/*01f0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000168000c1e1900 */
/*0200*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000168000c1e1900 */
/*0210*/ LDG.E R26, [R2.64+0x14] ; /* 0x00001404021a7981 */
/* 0x000168000c1e1900 */
/*0220*/ LDG.E R28, [R2.64+0x18] ; /* 0x00001804021c7981 */
/* 0x000168000c1e1900 */
/*0230*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000168000c1e1900 */
/*0240*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000168000c1e1900 */
/*0250*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000168000c1e1900 */
/*0260*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000168000c1e1900 */
/*0270*/ LDG.E R12, [R2.64+0x2c] ; /* 0x00002c04020c7981 */
/* 0x000168000c1e1900 */
/*0280*/ LDG.E R11, [R2.64+0x30] ; /* 0x00003004020b7981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R10, [R2.64+0x38] ; /* 0x00003804020a7981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0402087981 */
/* 0x000162000c1e1900 */
/*02c0*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GT.AND P1, PT, R7, 0xb, PT ; /* 0x0000000b0700780c */
/* 0x000fe40003f24270 */
/*02f0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*0300*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0310*/ FADD R17, R17, R4 ; /* 0x0000000411117221 */
/* 0x004fc80000000000 */
/*0320*/ FADD R17, R17, R18 ; /* 0x0000001211117221 */
/* 0x008fc80000000000 */
/*0330*/ FADD R17, R17, R20 ; /* 0x0000001411117221 */
/* 0x010fc80000000000 */
/*0340*/ FADD R17, R17, R22 ; /* 0x0000001611117221 */
/* 0x020fc80000000000 */
/*0350*/ FADD R17, R17, R24 ; /* 0x0000001811117221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R17, R17, R26 ; /* 0x0000001a11117221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R17, R17, R28 ; /* 0x0000001c11117221 */
/* 0x000fc80000000000 */
/*0380*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x000fc80000000000 */
/*0390*/ FADD R15, R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc80000000000 */
/*03a0*/ FADD R14, R15, R14 ; /* 0x0000000e0f0e7221 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R13, R14, R13 ; /* 0x0000000d0e0d7221 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R12, R13, R12 ; /* 0x0000000c0d0c7221 */
/* 0x000fc80000000000 */
/*03d0*/ FADD R12, R12, R11 ; /* 0x0000000b0c0c7221 */
/* 0x000fc80000000000 */
/*03e0*/ FADD R9, R12, R9 ; /* 0x000000090c097221 */
/* 0x000fc80000000000 */
/*03f0*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x000fc80000000000 */
/*0400*/ FADD R4, R9, R8 ; /* 0x0000000809047221 */
/* 0x000fe20000000000 */
/*0410*/ @P1 BRA 0x1c0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0430*/ IADD3 R8, R7, 0x1, RZ ; /* 0x0000000107087810 */
/* 0x000fe20007ffe0ff */
/*0440*/ BSSY B3, 0x5f0 ; /* 0x000001a000037945 */
/* 0x000fe60003800000 */
/*0450*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0460*/ @!P1 BRA 0x5e0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*0490*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000f28000c1e1900 */
/*04a0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000168000c1e1900 */
/*04b0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000168000c1e1900 */
/*04c0*/ LDG.E R17, [R2.64+0x14] ; /* 0x0000140402117981 */
/* 0x000168000c1e1900 */
/*04d0*/ LDG.E R19, [R2.64+0x18] ; /* 0x0000180402137981 */
/* 0x000168000c1e1900 */
/*04e0*/ LDG.E R21, [R2.64+0x1c] ; /* 0x00001c0402157981 */
/* 0x000162000c1e1900 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0500*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0510*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0520*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x004fc80000000000 */
/*0530*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x008fe20000000000 */
/*0540*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fc60007f3e0ff */
/*0550*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x010fe20000000000 */
/*0560*/ IADD3.X R10, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0a7210 */
/* 0x000fe20000ffe4ff */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0009 */
/*0580*/ FADD R8, R8, R13 ; /* 0x0000000d08087221 */
/* 0x020fe20000000000 */
/*0590*/ MOV R3, R10 ; /* 0x0000000a00037202 */
/* 0x000fc60000000f00 */
/*05a0*/ FADD R8, R8, R15 ; /* 0x0000000f08087221 */
/* 0x000fc80000000000 */
/*05b0*/ FADD R8, R8, R17 ; /* 0x0000001108087221 */
/* 0x000fc80000000000 */
/*05c0*/ FADD R8, R8, R19 ; /* 0x0000001308087221 */
/* 0x000fc80000000000 */
/*05d0*/ FADD R4, R8, R21 ; /* 0x0000001508047221 */
/* 0x000fe40000000000 */
/*05e0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.OR P0, PT, R7, -0x1, P0 ; /* 0xffffffff0700780c */
/* 0x000fda0000705670 */
/*0600*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0610*/ @!P0 BRA 0x730 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000f28000c1e1900 */
/*0660*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000162000c1e1900 */
/*0670*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*0680*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0690*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x000fe20003f05270 */
/*06a0*/ FADD R9, R9, R4 ; /* 0x0000000409097221 */
/* 0x004fc80000000000 */
/*06b0*/ FADD R8, R9, R8 ; /* 0x0000000809087221 */
/* 0x008fe20000000000 */
/*06c0*/ IADD3 R9, P1, R2, 0x10, RZ ; /* 0x0000001002097810 */
/* 0x000fc60007f3e0ff */
/*06d0*/ FADD R8, R8, R11 ; /* 0x0000000b08087221 */
/* 0x010fe20000000000 */
/*06e0*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x001fe20000000f00 */
/*06f0*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe400008e0603 */
/*0700*/ FADD R4, R8, R13 ; /* 0x0000000d08047221 */
/* 0x020fe40000000000 */
/*0710*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0720*/ @P0 BRA 0x630 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0730*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0750*/ @!P0 BRA 0x810 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0760*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fd400000001ff */
/*0770*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0790*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fca0000000f00 */
/*07a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*07d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*07e0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*07f0*/ FADD R4, R3, R4 ; /* 0x0000000403047221 */
/* 0x004fd40000000000 */
/*0800*/ @P0 BRA 0x780 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0810*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0820*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0830*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0840*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0850*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0860*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101904 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14sum_shared_memPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R22, R3, R22, c[0x0][0x160] ; /* 0x0000580003167625 */
/* 0x001fca00078e0216 */
/*0050*/ LDG.E R2, [R22.64] ; /* 0x0000000416027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0070*/ BSSY B2, 0x660 ; /* 0x000005e000027945 */
/* 0x000fe20003800000 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0090*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x0041e80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ @!P0 BRA 0x650 ; /* 0x0000059000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x041fe20003f06070 */
/*00d0*/ BSSY B1, 0x5c0 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*00e0*/ IADD3 R21, R3, 0x1, RZ ; /* 0x0000000103157810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fc40000000f00 */
/*0110*/ LOP3.LUT R21, R21, 0x3, RZ, 0xc0, !PT ; /* 0x0000000315157812 */
/* 0x000fce00078ec0ff */
/*0120*/ @!P0 BRA 0x5b0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.IADD R3, R3, 0x1, -R21 ; /* 0x0000000103037824 */
/* 0x000fe200078e0a15 */
/*0140*/ BSSY B0, 0x510 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0150*/ HFMA2.MMA R20, -RZ, RZ, 0, 0 ; /* 0x00000000ff147435 */
/* 0x000fe200000001ff */
/*0160*/ MOV R0, RZ ; /* 0x000000ff00007202 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0180*/ ISETP.GT.AND P0, PT, R3, -0x1, PT ; /* 0xffffffff0300780c */
/* 0x000fda0003f04270 */
/*0190*/ @!P0 BRA 0x500 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B3, 0x3a0 ; /* 0x000001e000037945 */
/* 0x000fe20003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01d0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*01e0*/ @!P1 BRA 0x390 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDS.128 R4, [R20] ; /* 0x0000000014047984 */
/* 0x000e220000000c00 */
/*0210*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDS.128 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x000e620000000c00 */
/*0240*/ ISETP.GT.AND P1, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fc60003f24270 */
/*0250*/ LDS.128 R12, [R20+0x20] ; /* 0x00002000140c7984 */
/* 0x000ea80000000c00 */
/*0260*/ LDS.128 R16, [R20+0x30] ; /* 0x0000300014107984 */
/* 0x0007240000000c00 */
/*0270*/ IADD3 R20, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x008fe20007ffe0ff */
/*0280*/ FADD R4, R4, R0 ; /* 0x0000000004047221 */
/* 0x001fc80000000000 */
/*0290*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*02a0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*02b0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02c0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fc80000000000 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0300*/ FADD R12, R11, R12 ; /* 0x0000000c0b0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x010fc80000000000 */
/*0350*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R0, R18, R19 ; /* 0x0000001312007221 */
/* 0x000fe20000000000 */
/*0380*/ @P1 BRA 0x200 ; /* 0xfffffe7000001947 */
/* 0x000fea000383ffff */
/*0390*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B3, 0x4d0 ; /* 0x0000011000037945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*03d0*/ @!P1 BRA 0x4c0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*03e0*/ LDS.128 R4, [R20] ; /* 0x0000000014047984 */
/* 0x000e220000000c00 */
/*03f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0400*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe20007ffe0ff */
/*0410*/ LDS.128 R8, [R20+0x10] ; /* 0x0000100014087984 */
/* 0x0002a20000000c00 */
/*0420*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R20, R20, 0x20, RZ ; /* 0x0000002014147810 */
/* 0x002fe20007ffe0ff */
/*0440*/ FADD R4, R0, R4 ; /* 0x0000000400047221 */
/* 0x001fc80000000000 */
/*0450*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R0, R10, R11 ; /* 0x0000000b0a007221 */
/* 0x000fe40000000000 */
/*04c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.OR P0, PT, R3, -0x1, P0 ; /* 0xffffffff0300780c */
/* 0x000fda0000705670 */
/*04e0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x5b0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ LDS.128 R4, [R20] ; /* 0x0000000014047984 */
/* 0x0000620000000c00 */
/*0520*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe40007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R3, -0x1, PT ; /* 0xffffffff0300780c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x001fe20007ffe0ff */
/*0560*/ FADD R4, R4, R0 ; /* 0x0000000004047221 */
/* 0x002fc80000000000 */
/*0570*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0580*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0590*/ FADD R0, R6, R7 ; /* 0x0000000706007221 */
/* 0x000fe20000000000 */
/*05a0*/ @P0 BRA 0x510 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*05b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fda0003f05270 */
/*05d0*/ @!P0 BRA 0x650 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*05e0*/ SHF.L.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027819 */
/* 0x000fca00000006ff */
/*05f0*/ LDS R3, [R2] ; /* 0x0000000002037984 */
/* 0x0000620000000800 */
/*0600*/ IADD3 R21, R21, -0x1, RZ ; /* 0xffffffff15157810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.NE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f05270 */
/*0620*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe20007ffe0ff */
/*0630*/ FADD R0, R3, R0 ; /* 0x0000000003007221 */
/* 0x002fd40000000000 */
/*0640*/ @P0 BRA 0x5f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0650*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0660*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ STG.E [R22.64], R0 ; /* 0x0000000016007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ BRA 0x6a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sum_shared_memPf
.globl _Z14sum_shared_memPf
.p2align 8
.type _Z14sum_shared_memPf,@function
_Z14sum_shared_memPf:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v0
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, 1, v0
s_mov_b32 s1, 0
s_mov_b32 s0, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v4, s[2:3]
v_add_co_u32 v0, s2, s2, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_1:
v_dual_mov_b32 v4, s1 :: v_dual_add_nc_u32 v3, -1, v3
s_add_i32 s1, s1, 4
ds_load_b32 v4, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_or_b32 s0, vcc_lo, s0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v4
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s0
s_barrier
buffer_gl0_inv
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sum_shared_memPf
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sum_shared_memPf, .Lfunc_end0-_Z14sum_shared_memPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14sum_global_memPf
.globl _Z14sum_global_memPf
.p2align 8
.type _Z14sum_global_memPf,@function
_Z14sum_global_memPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
s_mov_b32 s4, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[2:3], s[0:1]
.LBB1_1:
s_load_b32 s5, s[2:3], 0x0
v_add_nc_u32_e32 v2, -1, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, s5, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB1_1
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v0, 2, v0
s_barrier
buffer_gl0_inv
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sum_global_memPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14sum_global_memPf, .Lfunc_end1-_Z14sum_global_memPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sum_shared_memPf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14sum_shared_memPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sum_global_memPf
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14sum_global_memPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00137eaa_00000000-6_shared_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14sum_shared_memPfPf
.type _Z34__device_stub__Z14sum_shared_memPfPf, @function
_Z34__device_stub__Z14sum_shared_memPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14sum_shared_memPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z34__device_stub__Z14sum_shared_memPfPf, .-_Z34__device_stub__Z14sum_shared_memPfPf
.globl _Z14sum_shared_memPf
.type _Z14sum_shared_memPf, @function
_Z14sum_shared_memPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14sum_shared_memPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14sum_shared_memPf, .-_Z14sum_shared_memPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Computing time before Kernel call: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "s"
.section .rodata.str1.8
.align 8
.LC3:
.string "Computing time after Kernel call: "
.align 8
.LC4:
.string "Computing time after memory copy: "
.section .rodata.str1.1
.LC5:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $4096, %rsp
.cfi_def_cfa_offset 4136
orq $0, (%rsp)
subq $56, %rsp
.cfi_def_cfa_offset 4192
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L12
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbp
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 72(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC5(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L14
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $4152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rdi
call _Z34__device_stub__Z14sum_shared_memPfPf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z34__device_stub__Z14sum_global_memPfPf
.type _Z34__device_stub__Z14sum_global_memPfPf, @function
_Z34__device_stub__Z14sum_global_memPfPf:
.LFB3696:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14sum_global_memPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z14sum_global_memPfPf, .-_Z34__device_stub__Z14sum_global_memPfPf
.globl _Z14sum_global_memPf
.type _Z14sum_global_memPf, @function
_Z14sum_global_memPf:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14sum_global_memPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z14sum_global_memPf, .-_Z14sum_global_memPf
.section .rodata.str1.1
.LC6:
.string "_Z14sum_global_memPf"
.LC7:
.string "_Z14sum_shared_memPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sum_global_memPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sum_shared_memPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "shared_memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__sum_shared_memPf # -- Begin function _Z29__device_stub__sum_shared_memPf
.p2align 4, 0x90
.type _Z29__device_stub__sum_shared_memPf,@function
_Z29__device_stub__sum_shared_memPf: # @_Z29__device_stub__sum_shared_memPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14sum_shared_memPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__sum_shared_memPf, .Lfunc_end0-_Z29__device_stub__sum_shared_memPf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__sum_global_memPf # -- Begin function _Z29__device_stub__sum_global_memPf
.p2align 4, 0x90
.type _Z29__device_stub__sum_global_memPf,@function
_Z29__device_stub__sum_global_memPf: # @_Z29__device_stub__sum_global_memPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14sum_global_memPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z29__device_stub__sum_global_memPf, .Lfunc_end1-_Z29__device_stub__sum_global_memPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 4208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq clock
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 80(%rsp,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_23
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB2_6
.LBB2_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14sum_shared_memPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_23
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r15)
je .LBB2_11
# %bb.10:
movzbl 67(%r15), %eax
jmp .LBB2_12
.LBB2_11:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_23
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%r14)
je .LBB2_15
# %bb.14:
movzbl 67(%r14), %eax
jmp .LBB2_16
.LBB2_15:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $10, %rbx
jne .LBB2_17
# %bb.18:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
cmpb $0, 56(%rbx)
je .LBB2_21
# %bb.20:
movzbl 67(%rbx), %eax
jmp .LBB2_22
.LBB2_21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_23:
.cfi_def_cfa_offset 4208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sum_shared_memPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sum_global_memPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sum_shared_memPf,@object # @_Z14sum_shared_memPf
.section .rodata,"a",@progbits
.globl _Z14sum_shared_memPf
.p2align 3, 0x0
_Z14sum_shared_memPf:
.quad _Z29__device_stub__sum_shared_memPf
.size _Z14sum_shared_memPf, 8
.type _Z14sum_global_memPf,@object # @_Z14sum_global_memPf
.globl _Z14sum_global_memPf
.p2align 3, 0x0
_Z14sum_global_memPf:
.quad _Z29__device_stub__sum_global_memPf
.size _Z14sum_global_memPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Computing time before Kernel call: "
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computing time after Kernel call: "
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Computing time after memory copy: "
.size .L.str.3, 35
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ", "
.size .L.str.4, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14sum_shared_memPf"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14sum_global_memPf"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sum_shared_memPf
.addrsig_sym _Z29__device_stub__sum_global_memPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sum_shared_memPf
.addrsig_sym _Z14sum_global_memPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A , int Acount, int Acols, float * out0 , int out0count, int out0cols, const float row_id)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id+(int)row_id*Acols];
}
} | code for sm_80
Function : _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ F2I.TRUNC.NTZ R3, c[0x0][0x180] ; /* 0x0000600000037b05 */
/* 0x000e22000020f100 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x001fd000078e0200 */
/*00c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0204 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A , int Acount, int Acols, float * out0 , int out0count, int out0cols, const float row_id)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id+(int)row_id*Acols];
}
} | .file "tmpxft_0002f151_00000000-6_Matrix_getRow_FloatId_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.type _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, @function
_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, .-_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, @function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A , int Acount, int Acols, float * out0 , int out0count, int out0cols, const float row_id)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id+(int)row_id*Acols];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A , int Acount, int Acols, float * out0 , int out0count, int out0cols, const float row_id)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id+(int)row_id*Acols];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A , int Acount, int Acols, float * out0 , int out0count, int out0cols, const float row_id)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id+(int)row_id*Acols];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 8
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Matrix_getRow_FloatId_naive(const float * A , int Acount, int Acols, float * out0 , int out0count, int out0cols, const float row_id)
{
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id<Acols)
{
out0[id] = A[id+(int)row_id*Acols];
}
} | .text
.file "Matrix_getRow_FloatId_naive.hip"
.globl _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif # -- Begin function _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 4, 0x90
.type _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif: # @_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@object # @_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata,"a",@progbits
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 3, 0x0
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.quad _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ F2I.TRUNC.NTZ R3, c[0x0][0x180] ; /* 0x0000600000037b05 */
/* 0x000e22000020f100 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD R3, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003037a24 */
/* 0x001fd000078e0200 */
/*00c0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R0, R4, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0204 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 8
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x28
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27Matrix_getRow_FloatId_naivePKfiiPfiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002f151_00000000-6_Matrix_getRow_FloatId_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.type _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, @function
_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif, .-_Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, @function
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27Matrix_getRow_FloatId_naivePKfiiPfiifPKfiiPfiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, .-_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27Matrix_getRow_FloatId_naivePKfiiPfiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix_getRow_FloatId_naive.hip"
.globl _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif # -- Begin function _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 4, 0x90
.type _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif,@function
_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif: # @_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif, .Lfunc_end0-_Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27Matrix_getRow_FloatId_naivePKfiiPfiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27Matrix_getRow_FloatId_naivePKfiiPfiif,@object # @_Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.section .rodata,"a",@progbits
.globl _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.p2align 3, 0x0
_Z27Matrix_getRow_FloatId_naivePKfiiPfiif:
.quad _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.size _Z27Matrix_getRow_FloatId_naivePKfiiPfiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27Matrix_getRow_FloatId_naivePKfiiPfiif"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27Matrix_getRow_FloatId_naivePKfiiPfiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x; // how big is one thread
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20; // 1M elements
float *x, *y;
// Allocate Unified Memory
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// 256 Threads
add<<<1, 256>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2d0 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fca00078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R9, 0x4 ; /* 0x0000000400097802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0002 */
/*0200*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0209 */
/*0210*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*0220*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a2000c1e1900 */
/*0240*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.WIDE R4, R9, c[0x0][0x0], R4 ; /* 0x0000000009047a25 */
/* 0x001fc800078e0204 */
/*0280*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fca0000000000 */
/*0290*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*02a0*/ IMAD.WIDE R2, R9, c[0x0][0x0], R2 ; /* 0x0000000009027a25 */
/* 0x001fe200078e0202 */
/*02b0*/ @P0 BRA 0x220 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02e0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fd400000001ff */
/*02f0*/ IMAD.WIDE R2, R0, R21, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0215 */
/*0300*/ IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x001fe200078e0215 */
/*0310*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0330*/ IMAD.WIDE R8, R21, c[0x0][0x0], R4 ; /* 0x0000000015087a25 */
/* 0x000fc800078e0204 */
/*0340*/ FADD R15, R6, R7 ; /* 0x00000007060f7221 */
/* 0x004fe40000000000 */
/*0350*/ IMAD.WIDE R6, R21, c[0x0][0x0], R2 ; /* 0x0000000015067a25 */
/* 0x000fc600078e0202 */
/*0360*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0370*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IMAD.WIDE R12, R21, c[0x0][0x0], R8 ; /* 0x00000000150c7a25 */
/* 0x000fc800078e0208 */
/*03a0*/ FADD R17, R10, R11 ; /* 0x0000000b0a117221 */
/* 0x004fe40000000000 */
/*03b0*/ IMAD.WIDE R10, R21, c[0x0][0x0], R6 ; /* 0x00000000150a7a25 */
/* 0x000fc600078e0206 */
/*03c0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R21, c[0x0][0x0], R12 ; /* 0x0000000015047a25 */
/* 0x001fc800078e020c */
/*0400*/ FADD R19, R2, R3 ; /* 0x0000000302137221 */
/* 0x004fe40000000000 */
/*0410*/ IMAD.WIDE R2, R21, c[0x0][0x0], R10 ; /* 0x0000000015027a25 */
/* 0x000fc600078e020a */
/*0420*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0450*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x002fc600078e00ff */
/*0470*/ LEA R0, R15, R0, 0x1 ; /* 0x000000000f007211 */
/* 0x000fc800078e08ff */
/*0480*/ LEA R0, R9, R0, 0x1 ; /* 0x0000000009007211 */
/* 0x000fc800078e08ff */
/*0490*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*04a0*/ FADD R7, R6, R3 ; /* 0x0000000306077221 */
/* 0x004fca0000000000 */
/*04b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101904 */
/*04c0*/ @!P0 BRA 0x2e0 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x; // how big is one thread
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20; // 1M elements
float *x, *y;
// Allocate Unified Memory
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// 256 Threads
add<<<1, 256>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_0009f81c_00000000-6_parallel_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movq (%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x; // how big is one thread
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20; // 1M elements
float *x, *y;
// Allocate Unified Memory
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// 256 Threads
add<<<1, 256>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x; // how big is one thread
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20; // 1M elements
float *x, *y;
// Allocate Unified Memory
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// 256 Threads
add<<<1, 256>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Free memory
hipFree(x);
hipFree(y);
return 0;
} |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.