system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x; // how big is one thread
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20; // 1M elements
float *x, *y;
// Allocate Unified Memory
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// 256 Threads
add<<<1, 256>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_load_b32 s2, s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
s_mov_b32 s3, 0
s_lshl_b32 s8, s1, 2
s_mov_b32 s9, s3
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s1, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_u32 v1, vcc_lo, v1, s8
v_cmp_le_i32_e64 s0, s2, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s9, s0, s9
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[5:6], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x; // how big is one thread
for (int i = index; i < n; i += stride)
y[i] = x[i] + y[i];
}
int main(void)
{
int N = 1<<20; // 1M elements
float *x, *y;
// Allocate Unified Memory
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// 256 Threads
add<<<1, 256>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "parallel_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0050*/ LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff047212 */
/* 0x000fe200078e33ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*0080*/ BSSY B0, 0x2d0 ; /* 0x0000024000007945 */
/* 0x000fe20003800000 */
/*0090*/ IADD3 R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fc60007ffe0ff */
/*00a0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00f0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fca00078e02ff */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0130*/ IMAD R4, R5, c[0x0][0x0], R4 ; /* 0x0000000005047a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0180*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0190*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*01a0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*01c0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01d0*/ @!P0 BRA 0x2c0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*01e0*/ MOV R9, 0x4 ; /* 0x0000000400097802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0002 */
/*0200*/ IMAD.WIDE R2, R0, R9, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0209 */
/*0210*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*0220*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x0000a2000c1e1900 */
/*0240*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.WIDE R4, R9, c[0x0][0x0], R4 ; /* 0x0000000009047a25 */
/* 0x001fc800078e0204 */
/*0280*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fca0000000000 */
/*0290*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*02a0*/ IMAD.WIDE R2, R9, c[0x0][0x0], R2 ; /* 0x0000000009027a25 */
/* 0x001fe200078e0202 */
/*02b0*/ @P0 BRA 0x220 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02e0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fd400000001ff */
/*02f0*/ IMAD.WIDE R2, R0, R21, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0215 */
/*0300*/ IMAD.WIDE R4, R0, R21, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x001fe200078e0215 */
/*0310*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0330*/ IMAD.WIDE R8, R21, c[0x0][0x0], R4 ; /* 0x0000000015087a25 */
/* 0x000fc800078e0204 */
/*0340*/ FADD R15, R6, R7 ; /* 0x00000007060f7221 */
/* 0x004fe40000000000 */
/*0350*/ IMAD.WIDE R6, R21, c[0x0][0x0], R2 ; /* 0x0000000015067a25 */
/* 0x000fc600078e0202 */
/*0360*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101904 */
/*0370*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IMAD.WIDE R12, R21, c[0x0][0x0], R8 ; /* 0x00000000150c7a25 */
/* 0x000fc800078e0208 */
/*03a0*/ FADD R17, R10, R11 ; /* 0x0000000b0a117221 */
/* 0x004fe40000000000 */
/*03b0*/ IMAD.WIDE R10, R21, c[0x0][0x0], R6 ; /* 0x00000000150a7a25 */
/* 0x000fc600078e0206 */
/*03c0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ IMAD.WIDE R4, R21, c[0x0][0x0], R12 ; /* 0x0000000015047a25 */
/* 0x001fc800078e020c */
/*0400*/ FADD R19, R2, R3 ; /* 0x0000000302137221 */
/* 0x004fe40000000000 */
/*0410*/ IMAD.WIDE R2, R21, c[0x0][0x0], R10 ; /* 0x0000000015027a25 */
/* 0x000fc600078e020a */
/*0420*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*0450*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe20000000f00 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x002fc600078e00ff */
/*0470*/ LEA R0, R15, R0, 0x1 ; /* 0x000000000f007211 */
/* 0x000fc800078e08ff */
/*0480*/ LEA R0, R9, R0, 0x1 ; /* 0x0000000009007211 */
/* 0x000fc800078e08ff */
/*0490*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*04a0*/ FADD R7, R6, R3 ; /* 0x0000000306077221 */
/* 0x004fca0000000000 */
/*04b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101904 */
/*04c0*/ @!P0 BRA 0x2e0 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_load_b32 s2, s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
s_mov_b32 s3, 0
s_lshl_b32 s8, s1, 2
s_mov_b32 s9, s3
.p2align 6
.LBB0_2:
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v0, s1, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_u32 v1, vcc_lo, v1, s8
v_cmp_le_i32_e64 s0, s2, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s9, s0, s9
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[5:6], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009f81c_00000000-6_parallel_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L12:
movq (%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallel_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <random>
#include <iostream>
#include <stdio.h>
#include <vector_types.h>
#define L 2048
#define M 2048
#define N 2048
using copy4_t = int4;
constexpr int l = L;
constexpr int m = M;
constexpr int n = N;
//constexpr int SHMEM_SIZE = 2 >> 14; // 32kB
constexpr int tbp = 512;
constexpr int nblocks = l * n / tbp;
// This kernel is actually 10x faster than NaiveCOrdered because of memory coalescing.
__global__
void matrixMultiplyNaive(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[k + row * m] * B[col + k * n];
C[col + n * row] = tmp;
}
__global__
void matrixMultiplyNaiveBColOrdered(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[k + row * m] * B[k + col * m];
C[col + n * row] = tmp;
}
__global__
void matrixMultiplyNaiveAColOrdered(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[row + k * m] * B[col + k * n];
C[col + n * row] = tmp;
}
/*
// This is a convenience function for allocating a pair of a host and device pointer
template<typename T>
std::pair<T*, T*> cudaAlloc(size_t nobj) {
T* host_ptr = new T[nobj * sizeof(T)];
T* device_ptr;
cudaError_t err;
if ((err = cudaMalloc((void **) &device_ptr, nobj * sizeof(T))) != cudaSuccess) {
std::cout << "CUDA error: " << cudaGetErrorString(err) << std::endl;
exit(1):
}
return {host_ptr, device_ptr};
}
*/
//constexpr int TILE_WIDTH = 32;
#define TILE_WIDTH 32
// We are going to create a (k x k) tiling - k must divide n and l
__global__
void matrixMultiplyShmem(float* A, float* B, float* C, int l, int m, int n) {
// Declare some shared memory. We'll load from global mem into these buffers.
__shared__ float bufA[TILE_WIDTH][TILE_WIDTH];
__shared__ float bufB[TILE_WIDTH][TILE_WIDTH];
const int row = blockDim.y * blockIdx.y + threadIdx.y;
const int col = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0; // This variable will store the result of matrix mult
for (int tile_idx = 0; tile_idx < M / TILE_WIDTH; ++tile_idx) {
// Load the tile from global memory into shared memory and wait until all
// threads have performed the load
bufA[threadIdx.y][threadIdx.x] = A[row * m + tile_idx * TILE_WIDTH + threadIdx.x];
bufB[threadIdx.y][threadIdx.x] = B[n * (tile_idx * TILE_WIDTH + threadIdx.y) + col];
__syncthreads();
// Add the contribution from this tile
#pragma unroll
for (int k = 0; k < TILE_WIDTH; ++k)
result += bufA[threadIdx.y][k] * bufB[k][threadIdx.x];
// I don't think this barrier is strictly necessary, but if it is not here,
// we may not be able to coalesce global memory accesses.
// COMPLETE: See what happens to kernel benchmarks if I remove it.
// RESULT: Actually, the code breaks and gives incorrect results if I don't include this.
// Kirk+Hwu, p.93 explains why. If it's not here, then a thread may modify shared memory
// while other threads are still using it.
__syncthreads();
}
C[col + n * row] = result;
}
/*
* Steps:
* 1. Copy C into shared memory
* 2. Put C from shared memory into an accumulator fragment
*/
constexpr int BITS_PER_BYTE = 8;
constexpr int THREADS_PER_WARP = 32;
constexpr int WMMA_BIT_ALIGNMENT = 128;
//constexpr int SHMEM_HALF_BANK_OFFSET = WMMA_BIT_ALIGNMENT / (BITS_PER_BYTE * sizeof(half));
constexpr int SHMEM_FLOAT_BANK_OFFSET = WMMA_BIT_ALIGNMENT / (BITS_PER_BYTE * sizeof(float));
// How should we create tiles of the output matrix and assign threads/warps to those
// tiles? What part of the output is each thread/warp responsible for?
//
// Definitions:
// 1) A WMMA tile is the portion of a matrix handled by the wmma::fragment type and its
// associated operations
// 2) A warp tile is a (WARP_ROWS x WARP_COLS) block of WMMA tiles of the output matrix.
// Each warp is responsible for computing the matrix elements in its warp tile.
// 3) A block tile is comprised of (BLOCK_WARP_ROWS x BLOCK_ROW_COLS) warp tiles. This
// is the portion of the output matrix that each thread block is computing.
// 4) A constant labeled with {A}_TILE_WIDTH or {A}_TILE_HEIGHT is referring to a number
// of matrix elements along the rows or columns, respectively, of a tile of type A
// 5) A constant labeled with {A}_{B}_ROWS or {A}_{B}_COLS is referring to the number of
// tiles of type B along the rows or columns, respectively, of a tile of type A.
constexpr int WARP_WMMA_COLS = 2;
constexpr int WARP_WMMA_ROWS = 4;
constexpr int BLOCK_WARP_ROWS = 2;
constexpr int BLOCK_WARP_COLS = 4;
constexpr int BLOCK_WMMA_ROWS = BLOCK_WARP_ROWS * WARP_WMMA_ROWS; // 8
constexpr int BLOCK_WMMA_COLS = BLOCK_WARP_COLS * WARP_WMMA_COLS; // 8
// This is the number of WMMA fragments along the M-dimension for the tiles of A and B
constexpr int BLOCK_WMMA_M_DIM = 4;
constexpr int WMMA_TILE_WIDTH = 16;
constexpr int WMMA_TILE_HEIGHT = 16;
constexpr int IRRELEVANT_DIM = 16;
constexpr int WARP_TILE_WIDTH = WARP_WMMA_COLS * WMMA_TILE_WIDTH;
constexpr int WARP_TILE_HEIGHT = WARP_WMMA_ROWS * WMMA_TILE_HEIGHT;
constexpr int BLOCK_TILE_WIDTH = WMMA_TILE_WIDTH * WARP_WMMA_COLS * BLOCK_WARP_COLS; // 16 * 2 * 4 = 128
constexpr int BLOCK_TILE_HEIGHT = WMMA_TILE_HEIGHT * WARP_WMMA_ROWS * BLOCK_WARP_ROWS; // 16 * 4 * 2 = 128
constexpr int WARPS_PER_BLOCK = BLOCK_WMMA_ROWS * BLOCK_WMMA_COLS / (WARP_WMMA_COLS * WARP_WMMA_ROWS);
constexpr int THREADS_PER_BLOCK = THREADS_PER_WARP * WARPS_PER_BLOCK;
// Since we only have 65kB of shared memory available per block,
// we choose l and m such that:
// l * m * 16 * 16 * 2 * 2 <= 65kB => l * m <= 64
// We choose l = 8 and m = 4.
/*
template<typename T>
__device__
inline T* offset(T* ptr, int rows, int cols, int stride) {
return ptr + stride * rows + cols;
}
// Args:
// A: Row major ordered matrix of size l x m
// B: Row major ordered matrix of size m x n
// C: Row major ordered matrix of size l x n
__global__
void matrixMultiplyWmma(float* A, float* B, float* C, int l, int m, int n) {
extern __shared__ half shmem[][WMMA_TILE_WIDTH * BLOCK_WMMA_M_DIM + SHMEM_HALF_BANK_OFFSET];
const int tid = threadIdx.x + threadIdx.y * blockDim.x;
const int block_warp_x = (tid / THREADS_PER_WARP) % BLOCK_WARP_COLS;
const int block_warp_y = (tid / THREADS_PER_WARP) / BLOCK_WARP_COLS;
const int lane_id = tid % THREADS_PER_WARP;
const int warp_id = tid / THREADS_PER_WARP;
const int tile_col_offset = blockIdx.x * BLOCK_TILE_WIDTH;
const int tile_row_offset = blockIdx.y * BLOCK_TILE_HEIGHT;
// This is where the current warp will write C to in shmem
float *shmem_float_ptr = offset(
(float *)&shmem[0][0],
warp_id * WMMA_TILE_HEIGHT,
0,
BLOCK_TILE_WIDTH
);
// Each warp copies a 16x128 chunk of the C matrix, one row at a time.
// Each thread copies 4 entries (32 bytes) at a time from glmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_HEIGHT; ++i) {
float* shmem_ptr = offset(shmem_float_ptr, warp_id * WMMA_TILE_HEIGHT + i, 0, BLOCK_TILE_WIDTH);
float* glmem_ptr = offset(C, tile_row_offset + warp_id * WMMA_TILE_HEIGHT + i, tile_col_offset, n);
*((copy4_t *)shmem_ptr + lane_id) = *((copy4_t *)glmem_ptr + lane_id);
// May want to try out a syncthreads in here, rather than after the loop
}
__syncthreads();
wmma::fragment<wmma::accumulator, WMMA_TILE_HEIGHT, WMMA_TILE_WIDTH, IRRELEVANT_DIM, float> c_frag[WARP_WMMA_ROWS][WARP_WMMA_COLS];
// Load the tiles into the fragments
float* tile_ptr;
#pragma unroll
for (int i = 0; i < BLOCK_WARP_ROWS; ++i) {
#pragma unroll
for (int j = 0; j < BLOCK_WARP_COLS; ++j) {
tile_ptr = offset(shmem_float_ptr, i + block_warp_y * WARP_TILE_HEIGHT, j * WMMA_TILE_WIDTH + block_warp_x * WARP_TILE_WIDTH, BLOCK_TILE_WIDTH);
wmma::load_matrix_sync(c_frag[i][j], tile_ptr, BLOCK_TILE_WIDTH, wmma::mem_row_major);
}
}
__syncthreads();
wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag[WARP_WMMA_ROWS];
wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag[WARP_WMMA_COLS];
// Loop for sliding through tiles on A and B.
for (int tile_idx = 0; tile_idx < m / TILE_WIDTH; ++tile_idx) {
// Copy A and B from global memory into shared memory.
// 1. All warps with block_warp_y = 0 copy A, and those with block_warp_y = 1 copy B
if (block_warp_y == 0) {
#pragma unroll
for (int i = 0; i < 2 * WMMA_TILE_HEIGHT; i += 4) {
half* shmem_ptr_half = offset(
&shmem[0][0],
block_warp_x * 2 * WMMA_TILE_HEIGHT + lane_id / 8 + i,
0,
BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET
);
half* glmem_ptr_half = offset(
A,
tile_row_offset + block_warp_x * 2 * WMMA_TILE_HEIGHT + lane_id / 8 + i,
tile_idx * BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH,
l
)
*((copy4_t *)shmem_ptr_half + lane_id % 8) = *((copy4_t *)glmem_ptr_half + lane_id % 8)
}
}
else {
}
__syncthreads();
// These three loops are performing the actual matrix multiplication over the global tile.
#pragma unroll
for (int k = 0; k < WMMA_TILE_K; ++k) {
#pragma unroll
for (int j = 0; j < WARP_WMMA_COLS; ++j) {
tile_ptr = &shmem[idx_b + block_warp_x * WARP_TILE_WIDTH + j * WMMA_TILE_WIDTH][k * WMMA_TILE_WIDTH];
wmma::load_matrix_sync(b[j], tile_ptr, BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET, wmma:mem_col_major);
#pragma unroll
for (int i = 0; i < WARP_WMMA_ROWS; ++i) {
if (j == 0) {
tile_ptr = &shmem[block_warp_y * WARP_TILE_HEIGHT + i * WMMA_TILE_HEIGHT][k * WMMA_TILE_WIDTH];
wmma::load_matrix_sync(a[i], tile_ptr, BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET, wmma:mem_row_major);
}
// Perform the matrix multiplication of the WMMA tile
wmma::mma_sync(c_frag[i][j], a_frag[i], b_frag[j], c_frag[i][j]);
}
}
}
}
// Memory access patterns for wmma::store_matrix_sync are basically random
// and will not allow us to coalesce. In that case, we first load the result
// into shared memory, then into global memory.
// Copy tiles into shmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_ROWS; ++i) {
#pragma unroll
for (int j = 0; j < WMMA_TILE_COLS; ++j) {
// TODO: Compute ptr...
wmma::store_matrix_sync(shmem_ptr, c[i][j], stride, wmma::mem_row_major);
}
}
// Copy from shmem into glmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_HEIGHT; ++i) {
float* shmem_ptr = offset(shmem_float_ptr, i, 0, BLOCK_TILE_WIDTH);
float* glmem_ptr = offset(C, i + tile_row_offset + warp_id * WMMA_TILE_HEIGHT, tile_col_offset, n);
*((copy4_t *)shmem_ptr + lane_id) = *((copy4_t *)glmem_ptr + lane_id);
// May want to try out a syncthreads in here, rather than after the loop
}
__syncthreads();
}
*/
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
void colOrderFrom(float* row_ordered, float* col_ordered, int rows, int cols) {
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
col_ordered[i + rows * j] = row_ordered[j + cols * i];
}
}
}
void initRandMatrixColOrdered(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[i + rows * j] = dis(gen);
}
}
return;
}
void printMatrix(float* mem, int rows, int cols) {
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
std::cout << mem[j + cols * i] << " ";
}
std::cout << std::endl;
}
}
int main(void) {
//cudaFuncSetAttribute(matrixMultiplyWmma, cudaFuncAttributeMaxDynamicSharedMemorySize, BLOCK_TILE_HEIGHT * BLOCK_TILE_WIDTH * sizeof(float));
float* h_A = new float[l * m];
float* h_Acol = new float[l * m];
float* h_B = new float[m * n];
float* h_Bcol = new float[m * n];
float* h_C = new float[l * n];
float* h_C3 = new float[l * n];
float* h_Ccol = new float[l * n];
float* h_Ccol2 = new float[l * n];
float *d_A, *d_Acol, *d_B, *d_Bcol, *d_C, *d_Ccol, *d_Ccol2, *d_C3;
cudaError_t err_A = cudaMalloc((void **) &d_A, l * m * sizeof(float));
cudaError_t err_Acol = cudaMalloc((void **) &d_Acol, l * m * sizeof(float));
cudaError_t err_B = cudaMalloc((void **) &d_B, m * n * sizeof(float));
cudaError_t err_Bcol = cudaMalloc((void **) &d_Bcol, m * n * sizeof(float));
cudaError_t err_C = cudaMalloc((void **) &d_C, l * n * sizeof(float));
cudaError_t err_Ccol = cudaMalloc((void **) &d_Ccol, l * n * sizeof(float));
cudaError_t err_C3 = cudaMalloc((void **) &d_C3, l * n * sizeof(float));
initRandMatrix(h_A, l, m);
initRandMatrix(h_B, m, n);
colOrderFrom(h_B, h_Bcol, m, n);
colOrderFrom(h_A, h_Acol, l, m);
//printMatrix(h_A, l, m);
//printMatrix(h_B, m, n);
cudaMemcpy(d_A, h_A, l * m * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_Acol, h_Acol, l * m * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, m * n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_Bcol, h_Bcol, m * n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemset(d_C, 0, l * n * sizeof(float));
cudaMemset(d_Ccol, 0, l * n * sizeof(float));
cudaMemset(d_C3, 0, l * n * sizeof(float));
matrixMultiplyNaive<<<nblocks, tbp>>>(d_A, d_B, d_C, l, m, n);
matrixMultiplyNaiveBColOrdered<<<nblocks, tbp>>>(d_A, d_Bcol, d_Ccol, l, m, n);
//matrixMultiplyNaiveAColOrdered<<<nblocks, tbp>>>(d_Acol, d_B, d_Ccol2, l, m, n);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(n / TILE_WIDTH, l / TILE_WIDTH);
matrixMultiplyShmem<<<dimGrid, dimBlock>>>(d_A, d_B, d_C3, l, m, n);
dim3 dimBlock2(THREADS_PER_WARP * BLOCK_WARP_COLS, BLOCK_WARP_ROWS);
dim3 dimGrid2(n / BLOCK_TILE_WIDTH, l / BLOCK_TILE_HEIGHT);
// matrixMultiplyWmma<<<dimGrid2, dimBlock2, BLOCK_TILE_WIDTH * BLOCK_TILE_HEIGHT * sizeof(float) >>>(d_A, d_B, d_C3, l, m, n);
cudaMemcpy(h_C, d_C, l * n * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(h_C3, d_C3, l * n * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(h_Ccol, d_Ccol, l * n * sizeof(float), cudaMemcpyDeviceToHost);
//cudaMemcpy(h_Ccol2, d_Ccol2, l * n * sizeof(float), cudaMemcpyDeviceToHost);
bool agrees = true;
for (int i = 0; i < l; ++i) {
for (int j = 0; j < n; ++j) {
if (h_Ccol[j + n * i] != h_C[j + n * i])
agrees = false;
}
}
std::cout << agrees << std::endl;
for (int i = 0; i < l; ++i) {
for (int j = 0; j < n; ++j) {
if (h_C3[j + n * i] != h_C[j + n * i])
agrees = false;
}
}
std::cout << agrees << std::endl;
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) std::cout << "CUDA error: " << cudaGetErrorString(err) << std::endl;
delete [] h_A;
delete [] h_B;
delete [] h_Bcol;
delete [] h_C;
delete [] h_C3;
delete [] h_Ccol;
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_Bcol);
cudaFree(d_C);
cudaFree(d_C3);
cudaFree(d_Ccol);
} | #include <hip/hip_runtime.h>
#include <random>
#include <iostream>
#include <stdio.h>
#include <hip/hip_vector_types.h>
#define L 2048
#define M 2048
#define N 2048
using copy4_t = int4;
constexpr int l = L;
constexpr int m = M;
constexpr int n = N;
//constexpr int SHMEM_SIZE = 2 >> 14; // 32kB
constexpr int tbp = 512;
constexpr int nblocks = l * n / tbp;
// This kernel is actually 10x faster than NaiveCOrdered because of memory coalescing.
__global__
void matrixMultiplyNaive(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[k + row * m] * B[col + k * n];
C[col + n * row] = tmp;
}
__global__
void matrixMultiplyNaiveBColOrdered(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[k + row * m] * B[k + col * m];
C[col + n * row] = tmp;
}
__global__
void matrixMultiplyNaiveAColOrdered(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[row + k * m] * B[col + k * n];
C[col + n * row] = tmp;
}
/*
// This is a convenience function for allocating a pair of a host and device pointer
template<typename T>
std::pair<T*, T*> cudaAlloc(size_t nobj) {
T* host_ptr = new T[nobj * sizeof(T)];
T* device_ptr;
cudaError_t err;
if ((err = cudaMalloc((void **) &device_ptr, nobj * sizeof(T))) != cudaSuccess) {
std::cout << "CUDA error: " << cudaGetErrorString(err) << std::endl;
exit(1):
}
return {host_ptr, device_ptr};
}
*/
//constexpr int TILE_WIDTH = 32;
#define TILE_WIDTH 32
// We are going to create a (k x k) tiling - k must divide n and l
__global__
void matrixMultiplyShmem(float* A, float* B, float* C, int l, int m, int n) {
// Declare some shared memory. We'll load from global mem into these buffers.
__shared__ float bufA[TILE_WIDTH][TILE_WIDTH];
__shared__ float bufB[TILE_WIDTH][TILE_WIDTH];
const int row = blockDim.y * blockIdx.y + threadIdx.y;
const int col = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0; // This variable will store the result of matrix mult
for (int tile_idx = 0; tile_idx < M / TILE_WIDTH; ++tile_idx) {
// Load the tile from global memory into shared memory and wait until all
// threads have performed the load
bufA[threadIdx.y][threadIdx.x] = A[row * m + tile_idx * TILE_WIDTH + threadIdx.x];
bufB[threadIdx.y][threadIdx.x] = B[n * (tile_idx * TILE_WIDTH + threadIdx.y) + col];
__syncthreads();
// Add the contribution from this tile
#pragma unroll
for (int k = 0; k < TILE_WIDTH; ++k)
result += bufA[threadIdx.y][k] * bufB[k][threadIdx.x];
// I don't think this barrier is strictly necessary, but if it is not here,
// we may not be able to coalesce global memory accesses.
// COMPLETE: See what happens to kernel benchmarks if I remove it.
// RESULT: Actually, the code breaks and gives incorrect results if I don't include this.
// Kirk+Hwu, p.93 explains why. If it's not here, then a thread may modify shared memory
// while other threads are still using it.
__syncthreads();
}
C[col + n * row] = result;
}
/*
* Steps:
* 1. Copy C into shared memory
* 2. Put C from shared memory into an accumulator fragment
*/
constexpr int BITS_PER_BYTE = 8;
constexpr int THREADS_PER_WARP = 32;
constexpr int WMMA_BIT_ALIGNMENT = 128;
//constexpr int SHMEM_HALF_BANK_OFFSET = WMMA_BIT_ALIGNMENT / (BITS_PER_BYTE * sizeof(half));
constexpr int SHMEM_FLOAT_BANK_OFFSET = WMMA_BIT_ALIGNMENT / (BITS_PER_BYTE * sizeof(float));
// How should we create tiles of the output matrix and assign threads/warps to those
// tiles? What part of the output is each thread/warp responsible for?
//
// Definitions:
// 1) A WMMA tile is the portion of a matrix handled by the wmma::fragment type and its
// associated operations
// 2) A warp tile is a (WARP_ROWS x WARP_COLS) block of WMMA tiles of the output matrix.
// Each warp is responsible for computing the matrix elements in its warp tile.
// 3) A block tile is comprised of (BLOCK_WARP_ROWS x BLOCK_ROW_COLS) warp tiles. This
// is the portion of the output matrix that each thread block is computing.
// 4) A constant labeled with {A}_TILE_WIDTH or {A}_TILE_HEIGHT is referring to a number
// of matrix elements along the rows or columns, respectively, of a tile of type A
// 5) A constant labeled with {A}_{B}_ROWS or {A}_{B}_COLS is referring to the number of
// tiles of type B along the rows or columns, respectively, of a tile of type A.
constexpr int WARP_WMMA_COLS = 2;
constexpr int WARP_WMMA_ROWS = 4;
constexpr int BLOCK_WARP_ROWS = 2;
constexpr int BLOCK_WARP_COLS = 4;
constexpr int BLOCK_WMMA_ROWS = BLOCK_WARP_ROWS * WARP_WMMA_ROWS; // 8
constexpr int BLOCK_WMMA_COLS = BLOCK_WARP_COLS * WARP_WMMA_COLS; // 8
// This is the number of WMMA fragments along the M-dimension for the tiles of A and B
constexpr int BLOCK_WMMA_M_DIM = 4;
constexpr int WMMA_TILE_WIDTH = 16;
constexpr int WMMA_TILE_HEIGHT = 16;
constexpr int IRRELEVANT_DIM = 16;
constexpr int WARP_TILE_WIDTH = WARP_WMMA_COLS * WMMA_TILE_WIDTH;
constexpr int WARP_TILE_HEIGHT = WARP_WMMA_ROWS * WMMA_TILE_HEIGHT;
constexpr int BLOCK_TILE_WIDTH = WMMA_TILE_WIDTH * WARP_WMMA_COLS * BLOCK_WARP_COLS; // 16 * 2 * 4 = 128
constexpr int BLOCK_TILE_HEIGHT = WMMA_TILE_HEIGHT * WARP_WMMA_ROWS * BLOCK_WARP_ROWS; // 16 * 4 * 2 = 128
constexpr int WARPS_PER_BLOCK = BLOCK_WMMA_ROWS * BLOCK_WMMA_COLS / (WARP_WMMA_COLS * WARP_WMMA_ROWS);
constexpr int THREADS_PER_BLOCK = THREADS_PER_WARP * WARPS_PER_BLOCK;
// Since we only have 65kB of shared memory available per block,
// we choose l and m such that:
// l * m * 16 * 16 * 2 * 2 <= 65kB => l * m <= 64
// We choose l = 8 and m = 4.
/*
template<typename T>
__device__
inline T* offset(T* ptr, int rows, int cols, int stride) {
return ptr + stride * rows + cols;
}
// Args:
// A: Row major ordered matrix of size l x m
// B: Row major ordered matrix of size m x n
// C: Row major ordered matrix of size l x n
__global__
void matrixMultiplyWmma(float* A, float* B, float* C, int l, int m, int n) {
extern __shared__ half shmem[][WMMA_TILE_WIDTH * BLOCK_WMMA_M_DIM + SHMEM_HALF_BANK_OFFSET];
const int tid = threadIdx.x + threadIdx.y * blockDim.x;
const int block_warp_x = (tid / THREADS_PER_WARP) % BLOCK_WARP_COLS;
const int block_warp_y = (tid / THREADS_PER_WARP) / BLOCK_WARP_COLS;
const int lane_id = tid % THREADS_PER_WARP;
const int warp_id = tid / THREADS_PER_WARP;
const int tile_col_offset = blockIdx.x * BLOCK_TILE_WIDTH;
const int tile_row_offset = blockIdx.y * BLOCK_TILE_HEIGHT;
// This is where the current warp will write C to in shmem
float *shmem_float_ptr = offset(
(float *)&shmem[0][0],
warp_id * WMMA_TILE_HEIGHT,
0,
BLOCK_TILE_WIDTH
);
// Each warp copies a 16x128 chunk of the C matrix, one row at a time.
// Each thread copies 4 entries (32 bytes) at a time from glmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_HEIGHT; ++i) {
float* shmem_ptr = offset(shmem_float_ptr, warp_id * WMMA_TILE_HEIGHT + i, 0, BLOCK_TILE_WIDTH);
float* glmem_ptr = offset(C, tile_row_offset + warp_id * WMMA_TILE_HEIGHT + i, tile_col_offset, n);
*((copy4_t *)shmem_ptr + lane_id) = *((copy4_t *)glmem_ptr + lane_id);
// May want to try out a syncthreads in here, rather than after the loop
}
__syncthreads();
wmma::fragment<wmma::accumulator, WMMA_TILE_HEIGHT, WMMA_TILE_WIDTH, IRRELEVANT_DIM, float> c_frag[WARP_WMMA_ROWS][WARP_WMMA_COLS];
// Load the tiles into the fragments
float* tile_ptr;
#pragma unroll
for (int i = 0; i < BLOCK_WARP_ROWS; ++i) {
#pragma unroll
for (int j = 0; j < BLOCK_WARP_COLS; ++j) {
tile_ptr = offset(shmem_float_ptr, i + block_warp_y * WARP_TILE_HEIGHT, j * WMMA_TILE_WIDTH + block_warp_x * WARP_TILE_WIDTH, BLOCK_TILE_WIDTH);
wmma::load_matrix_sync(c_frag[i][j], tile_ptr, BLOCK_TILE_WIDTH, wmma::mem_row_major);
}
}
__syncthreads();
wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag[WARP_WMMA_ROWS];
wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag[WARP_WMMA_COLS];
// Loop for sliding through tiles on A and B.
for (int tile_idx = 0; tile_idx < m / TILE_WIDTH; ++tile_idx) {
// Copy A and B from global memory into shared memory.
// 1. All warps with block_warp_y = 0 copy A, and those with block_warp_y = 1 copy B
if (block_warp_y == 0) {
#pragma unroll
for (int i = 0; i < 2 * WMMA_TILE_HEIGHT; i += 4) {
half* shmem_ptr_half = offset(
&shmem[0][0],
block_warp_x * 2 * WMMA_TILE_HEIGHT + lane_id / 8 + i,
0,
BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET
);
half* glmem_ptr_half = offset(
A,
tile_row_offset + block_warp_x * 2 * WMMA_TILE_HEIGHT + lane_id / 8 + i,
tile_idx * BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH,
l
)
*((copy4_t *)shmem_ptr_half + lane_id % 8) = *((copy4_t *)glmem_ptr_half + lane_id % 8)
}
}
else {
}
__syncthreads();
// These three loops are performing the actual matrix multiplication over the global tile.
#pragma unroll
for (int k = 0; k < WMMA_TILE_K; ++k) {
#pragma unroll
for (int j = 0; j < WARP_WMMA_COLS; ++j) {
tile_ptr = &shmem[idx_b + block_warp_x * WARP_TILE_WIDTH + j * WMMA_TILE_WIDTH][k * WMMA_TILE_WIDTH];
wmma::load_matrix_sync(b[j], tile_ptr, BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET, wmma:mem_col_major);
#pragma unroll
for (int i = 0; i < WARP_WMMA_ROWS; ++i) {
if (j == 0) {
tile_ptr = &shmem[block_warp_y * WARP_TILE_HEIGHT + i * WMMA_TILE_HEIGHT][k * WMMA_TILE_WIDTH];
wmma::load_matrix_sync(a[i], tile_ptr, BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET, wmma:mem_row_major);
}
// Perform the matrix multiplication of the WMMA tile
wmma::mma_sync(c_frag[i][j], a_frag[i], b_frag[j], c_frag[i][j]);
}
}
}
}
// Memory access patterns for wmma::store_matrix_sync are basically random
// and will not allow us to coalesce. In that case, we first load the result
// into shared memory, then into global memory.
// Copy tiles into shmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_ROWS; ++i) {
#pragma unroll
for (int j = 0; j < WMMA_TILE_COLS; ++j) {
// TODO: Compute ptr...
wmma::store_matrix_sync(shmem_ptr, c[i][j], stride, wmma::mem_row_major);
}
}
// Copy from shmem into glmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_HEIGHT; ++i) {
float* shmem_ptr = offset(shmem_float_ptr, i, 0, BLOCK_TILE_WIDTH);
float* glmem_ptr = offset(C, i + tile_row_offset + warp_id * WMMA_TILE_HEIGHT, tile_col_offset, n);
*((copy4_t *)shmem_ptr + lane_id) = *((copy4_t *)glmem_ptr + lane_id);
// May want to try out a syncthreads in here, rather than after the loop
}
__syncthreads();
}
*/
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
void colOrderFrom(float* row_ordered, float* col_ordered, int rows, int cols) {
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
col_ordered[i + rows * j] = row_ordered[j + cols * i];
}
}
}
void initRandMatrixColOrdered(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[i + rows * j] = dis(gen);
}
}
return;
}
void printMatrix(float* mem, int rows, int cols) {
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
std::cout << mem[j + cols * i] << " ";
}
std::cout << std::endl;
}
}
int main(void) {
//cudaFuncSetAttribute(matrixMultiplyWmma, cudaFuncAttributeMaxDynamicSharedMemorySize, BLOCK_TILE_HEIGHT * BLOCK_TILE_WIDTH * sizeof(float));
float* h_A = new float[l * m];
float* h_Acol = new float[l * m];
float* h_B = new float[m * n];
float* h_Bcol = new float[m * n];
float* h_C = new float[l * n];
float* h_C3 = new float[l * n];
float* h_Ccol = new float[l * n];
float* h_Ccol2 = new float[l * n];
float *d_A, *d_Acol, *d_B, *d_Bcol, *d_C, *d_Ccol, *d_Ccol2, *d_C3;
hipError_t err_A = hipMalloc((void **) &d_A, l * m * sizeof(float));
hipError_t err_Acol = hipMalloc((void **) &d_Acol, l * m * sizeof(float));
hipError_t err_B = hipMalloc((void **) &d_B, m * n * sizeof(float));
hipError_t err_Bcol = hipMalloc((void **) &d_Bcol, m * n * sizeof(float));
hipError_t err_C = hipMalloc((void **) &d_C, l * n * sizeof(float));
hipError_t err_Ccol = hipMalloc((void **) &d_Ccol, l * n * sizeof(float));
hipError_t err_C3 = hipMalloc((void **) &d_C3, l * n * sizeof(float));
initRandMatrix(h_A, l, m);
initRandMatrix(h_B, m, n);
colOrderFrom(h_B, h_Bcol, m, n);
colOrderFrom(h_A, h_Acol, l, m);
//printMatrix(h_A, l, m);
//printMatrix(h_B, m, n);
hipMemcpy(d_A, h_A, l * m * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_Acol, h_Acol, l * m * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_Bcol, h_Bcol, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemset(d_C, 0, l * n * sizeof(float));
hipMemset(d_Ccol, 0, l * n * sizeof(float));
hipMemset(d_C3, 0, l * n * sizeof(float));
matrixMultiplyNaive<<<nblocks, tbp>>>(d_A, d_B, d_C, l, m, n);
matrixMultiplyNaiveBColOrdered<<<nblocks, tbp>>>(d_A, d_Bcol, d_Ccol, l, m, n);
//matrixMultiplyNaiveAColOrdered<<<nblocks, tbp>>>(d_Acol, d_B, d_Ccol2, l, m, n);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(n / TILE_WIDTH, l / TILE_WIDTH);
matrixMultiplyShmem<<<dimGrid, dimBlock>>>(d_A, d_B, d_C3, l, m, n);
dim3 dimBlock2(THREADS_PER_WARP * BLOCK_WARP_COLS, BLOCK_WARP_ROWS);
dim3 dimGrid2(n / BLOCK_TILE_WIDTH, l / BLOCK_TILE_HEIGHT);
// matrixMultiplyWmma<<<dimGrid2, dimBlock2, BLOCK_TILE_WIDTH * BLOCK_TILE_HEIGHT * sizeof(float) >>>(d_A, d_B, d_C3, l, m, n);
hipMemcpy(h_C, d_C, l * n * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(h_C3, d_C3, l * n * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(h_Ccol, d_Ccol, l * n * sizeof(float), hipMemcpyDeviceToHost);
//cudaMemcpy(h_Ccol2, d_Ccol2, l * n * sizeof(float), cudaMemcpyDeviceToHost);
bool agrees = true;
for (int i = 0; i < l; ++i) {
for (int j = 0; j < n; ++j) {
if (h_Ccol[j + n * i] != h_C[j + n * i])
agrees = false;
}
}
std::cout << agrees << std::endl;
for (int i = 0; i < l; ++i) {
for (int j = 0; j < n; ++j) {
if (h_C3[j + n * i] != h_C[j + n * i])
agrees = false;
}
}
std::cout << agrees << std::endl;
hipError_t err = hipGetLastError();
if (err != hipSuccess) std::cout << "CUDA error: " << hipGetErrorString(err) << std::endl;
delete [] h_A;
delete [] h_B;
delete [] h_Bcol;
delete [] h_C;
delete [] h_C3;
delete [] h_Ccol;
hipFree(d_A);
hipFree(d_B);
hipFree(d_Bcol);
hipFree(d_C);
hipFree(d_C3);
hipFree(d_Ccol);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <random>
#include <iostream>
#include <stdio.h>
#include <hip/hip_vector_types.h>
#define L 2048
#define M 2048
#define N 2048
using copy4_t = int4;
constexpr int l = L;
constexpr int m = M;
constexpr int n = N;
//constexpr int SHMEM_SIZE = 2 >> 14; // 32kB
constexpr int tbp = 512;
constexpr int nblocks = l * n / tbp;
// This kernel is actually 10x faster than NaiveCOrdered because of memory coalescing.
__global__
void matrixMultiplyNaive(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[k + row * m] * B[col + k * n];
C[col + n * row] = tmp;
}
__global__
void matrixMultiplyNaiveBColOrdered(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[k + row * m] * B[k + col * m];
C[col + n * row] = tmp;
}
__global__
void matrixMultiplyNaiveAColOrdered(float* A, float* B, float* C, int l, int m, int n) {
const int row = (blockIdx.x * tbp + threadIdx.x) / n;
const int col = (blockIdx.x * tbp + threadIdx.x) % n;
float tmp = 0;
for (int k = 0; k < m; ++k)
tmp += A[row + k * m] * B[col + k * n];
C[col + n * row] = tmp;
}
/*
// This is a convenience function for allocating a pair of a host and device pointer
template<typename T>
std::pair<T*, T*> cudaAlloc(size_t nobj) {
T* host_ptr = new T[nobj * sizeof(T)];
T* device_ptr;
cudaError_t err;
if ((err = cudaMalloc((void **) &device_ptr, nobj * sizeof(T))) != cudaSuccess) {
std::cout << "CUDA error: " << cudaGetErrorString(err) << std::endl;
exit(1):
}
return {host_ptr, device_ptr};
}
*/
//constexpr int TILE_WIDTH = 32;
#define TILE_WIDTH 32
// We are going to create a (k x k) tiling - k must divide n and l
__global__
void matrixMultiplyShmem(float* A, float* B, float* C, int l, int m, int n) {
// Declare some shared memory. We'll load from global mem into these buffers.
__shared__ float bufA[TILE_WIDTH][TILE_WIDTH];
__shared__ float bufB[TILE_WIDTH][TILE_WIDTH];
const int row = blockDim.y * blockIdx.y + threadIdx.y;
const int col = blockDim.x * blockIdx.x + threadIdx.x;
float result = 0; // This variable will store the result of matrix mult
for (int tile_idx = 0; tile_idx < M / TILE_WIDTH; ++tile_idx) {
// Load the tile from global memory into shared memory and wait until all
// threads have performed the load
bufA[threadIdx.y][threadIdx.x] = A[row * m + tile_idx * TILE_WIDTH + threadIdx.x];
bufB[threadIdx.y][threadIdx.x] = B[n * (tile_idx * TILE_WIDTH + threadIdx.y) + col];
__syncthreads();
// Add the contribution from this tile
#pragma unroll
for (int k = 0; k < TILE_WIDTH; ++k)
result += bufA[threadIdx.y][k] * bufB[k][threadIdx.x];
// I don't think this barrier is strictly necessary, but if it is not here,
// we may not be able to coalesce global memory accesses.
// COMPLETE: See what happens to kernel benchmarks if I remove it.
// RESULT: Actually, the code breaks and gives incorrect results if I don't include this.
// Kirk+Hwu, p.93 explains why. If it's not here, then a thread may modify shared memory
// while other threads are still using it.
__syncthreads();
}
C[col + n * row] = result;
}
/*
* Steps:
* 1. Copy C into shared memory
* 2. Put C from shared memory into an accumulator fragment
*/
constexpr int BITS_PER_BYTE = 8;
constexpr int THREADS_PER_WARP = 32;
constexpr int WMMA_BIT_ALIGNMENT = 128;
//constexpr int SHMEM_HALF_BANK_OFFSET = WMMA_BIT_ALIGNMENT / (BITS_PER_BYTE * sizeof(half));
constexpr int SHMEM_FLOAT_BANK_OFFSET = WMMA_BIT_ALIGNMENT / (BITS_PER_BYTE * sizeof(float));
// How should we create tiles of the output matrix and assign threads/warps to those
// tiles? What part of the output is each thread/warp responsible for?
//
// Definitions:
// 1) A WMMA tile is the portion of a matrix handled by the wmma::fragment type and its
// associated operations
// 2) A warp tile is a (WARP_ROWS x WARP_COLS) block of WMMA tiles of the output matrix.
// Each warp is responsible for computing the matrix elements in its warp tile.
// 3) A block tile is comprised of (BLOCK_WARP_ROWS x BLOCK_ROW_COLS) warp tiles. This
// is the portion of the output matrix that each thread block is computing.
// 4) A constant labeled with {A}_TILE_WIDTH or {A}_TILE_HEIGHT is referring to a number
// of matrix elements along the rows or columns, respectively, of a tile of type A
// 5) A constant labeled with {A}_{B}_ROWS or {A}_{B}_COLS is referring to the number of
// tiles of type B along the rows or columns, respectively, of a tile of type A.
constexpr int WARP_WMMA_COLS = 2;
constexpr int WARP_WMMA_ROWS = 4;
constexpr int BLOCK_WARP_ROWS = 2;
constexpr int BLOCK_WARP_COLS = 4;
constexpr int BLOCK_WMMA_ROWS = BLOCK_WARP_ROWS * WARP_WMMA_ROWS; // 8
constexpr int BLOCK_WMMA_COLS = BLOCK_WARP_COLS * WARP_WMMA_COLS; // 8
// This is the number of WMMA fragments along the M-dimension for the tiles of A and B
constexpr int BLOCK_WMMA_M_DIM = 4;
constexpr int WMMA_TILE_WIDTH = 16;
constexpr int WMMA_TILE_HEIGHT = 16;
constexpr int IRRELEVANT_DIM = 16;
constexpr int WARP_TILE_WIDTH = WARP_WMMA_COLS * WMMA_TILE_WIDTH;
constexpr int WARP_TILE_HEIGHT = WARP_WMMA_ROWS * WMMA_TILE_HEIGHT;
constexpr int BLOCK_TILE_WIDTH = WMMA_TILE_WIDTH * WARP_WMMA_COLS * BLOCK_WARP_COLS; // 16 * 2 * 4 = 128
constexpr int BLOCK_TILE_HEIGHT = WMMA_TILE_HEIGHT * WARP_WMMA_ROWS * BLOCK_WARP_ROWS; // 16 * 4 * 2 = 128
constexpr int WARPS_PER_BLOCK = BLOCK_WMMA_ROWS * BLOCK_WMMA_COLS / (WARP_WMMA_COLS * WARP_WMMA_ROWS);
constexpr int THREADS_PER_BLOCK = THREADS_PER_WARP * WARPS_PER_BLOCK;
// Since we only have 65kB of shared memory available per block,
// we choose l and m such that:
// l * m * 16 * 16 * 2 * 2 <= 65kB => l * m <= 64
// We choose l = 8 and m = 4.
/*
template<typename T>
__device__
inline T* offset(T* ptr, int rows, int cols, int stride) {
return ptr + stride * rows + cols;
}
// Args:
// A: Row major ordered matrix of size l x m
// B: Row major ordered matrix of size m x n
// C: Row major ordered matrix of size l x n
__global__
void matrixMultiplyWmma(float* A, float* B, float* C, int l, int m, int n) {
extern __shared__ half shmem[][WMMA_TILE_WIDTH * BLOCK_WMMA_M_DIM + SHMEM_HALF_BANK_OFFSET];
const int tid = threadIdx.x + threadIdx.y * blockDim.x;
const int block_warp_x = (tid / THREADS_PER_WARP) % BLOCK_WARP_COLS;
const int block_warp_y = (tid / THREADS_PER_WARP) / BLOCK_WARP_COLS;
const int lane_id = tid % THREADS_PER_WARP;
const int warp_id = tid / THREADS_PER_WARP;
const int tile_col_offset = blockIdx.x * BLOCK_TILE_WIDTH;
const int tile_row_offset = blockIdx.y * BLOCK_TILE_HEIGHT;
// This is where the current warp will write C to in shmem
float *shmem_float_ptr = offset(
(float *)&shmem[0][0],
warp_id * WMMA_TILE_HEIGHT,
0,
BLOCK_TILE_WIDTH
);
// Each warp copies a 16x128 chunk of the C matrix, one row at a time.
// Each thread copies 4 entries (32 bytes) at a time from glmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_HEIGHT; ++i) {
float* shmem_ptr = offset(shmem_float_ptr, warp_id * WMMA_TILE_HEIGHT + i, 0, BLOCK_TILE_WIDTH);
float* glmem_ptr = offset(C, tile_row_offset + warp_id * WMMA_TILE_HEIGHT + i, tile_col_offset, n);
*((copy4_t *)shmem_ptr + lane_id) = *((copy4_t *)glmem_ptr + lane_id);
// May want to try out a syncthreads in here, rather than after the loop
}
__syncthreads();
wmma::fragment<wmma::accumulator, WMMA_TILE_HEIGHT, WMMA_TILE_WIDTH, IRRELEVANT_DIM, float> c_frag[WARP_WMMA_ROWS][WARP_WMMA_COLS];
// Load the tiles into the fragments
float* tile_ptr;
#pragma unroll
for (int i = 0; i < BLOCK_WARP_ROWS; ++i) {
#pragma unroll
for (int j = 0; j < BLOCK_WARP_COLS; ++j) {
tile_ptr = offset(shmem_float_ptr, i + block_warp_y * WARP_TILE_HEIGHT, j * WMMA_TILE_WIDTH + block_warp_x * WARP_TILE_WIDTH, BLOCK_TILE_WIDTH);
wmma::load_matrix_sync(c_frag[i][j], tile_ptr, BLOCK_TILE_WIDTH, wmma::mem_row_major);
}
}
__syncthreads();
wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag[WARP_WMMA_ROWS];
wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag[WARP_WMMA_COLS];
// Loop for sliding through tiles on A and B.
for (int tile_idx = 0; tile_idx < m / TILE_WIDTH; ++tile_idx) {
// Copy A and B from global memory into shared memory.
// 1. All warps with block_warp_y = 0 copy A, and those with block_warp_y = 1 copy B
if (block_warp_y == 0) {
#pragma unroll
for (int i = 0; i < 2 * WMMA_TILE_HEIGHT; i += 4) {
half* shmem_ptr_half = offset(
&shmem[0][0],
block_warp_x * 2 * WMMA_TILE_HEIGHT + lane_id / 8 + i,
0,
BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET
);
half* glmem_ptr_half = offset(
A,
tile_row_offset + block_warp_x * 2 * WMMA_TILE_HEIGHT + lane_id / 8 + i,
tile_idx * BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH,
l
)
*((copy4_t *)shmem_ptr_half + lane_id % 8) = *((copy4_t *)glmem_ptr_half + lane_id % 8)
}
}
else {
}
__syncthreads();
// These three loops are performing the actual matrix multiplication over the global tile.
#pragma unroll
for (int k = 0; k < WMMA_TILE_K; ++k) {
#pragma unroll
for (int j = 0; j < WARP_WMMA_COLS; ++j) {
tile_ptr = &shmem[idx_b + block_warp_x * WARP_TILE_WIDTH + j * WMMA_TILE_WIDTH][k * WMMA_TILE_WIDTH];
wmma::load_matrix_sync(b[j], tile_ptr, BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET, wmma:mem_col_major);
#pragma unroll
for (int i = 0; i < WARP_WMMA_ROWS; ++i) {
if (j == 0) {
tile_ptr = &shmem[block_warp_y * WARP_TILE_HEIGHT + i * WMMA_TILE_HEIGHT][k * WMMA_TILE_WIDTH];
wmma::load_matrix_sync(a[i], tile_ptr, BLOCK_WMMA_M_DIM * WMMA_TILE_WIDTH + SHMEM_HALF_BANK_OFFSET, wmma:mem_row_major);
}
// Perform the matrix multiplication of the WMMA tile
wmma::mma_sync(c_frag[i][j], a_frag[i], b_frag[j], c_frag[i][j]);
}
}
}
}
// Memory access patterns for wmma::store_matrix_sync are basically random
// and will not allow us to coalesce. In that case, we first load the result
// into shared memory, then into global memory.
// Copy tiles into shmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_ROWS; ++i) {
#pragma unroll
for (int j = 0; j < WMMA_TILE_COLS; ++j) {
// TODO: Compute ptr...
wmma::store_matrix_sync(shmem_ptr, c[i][j], stride, wmma::mem_row_major);
}
}
// Copy from shmem into glmem
#pragma unroll
for (int i = 0; i < WMMA_TILE_HEIGHT; ++i) {
float* shmem_ptr = offset(shmem_float_ptr, i, 0, BLOCK_TILE_WIDTH);
float* glmem_ptr = offset(C, i + tile_row_offset + warp_id * WMMA_TILE_HEIGHT, tile_col_offset, n);
*((copy4_t *)shmem_ptr + lane_id) = *((copy4_t *)glmem_ptr + lane_id);
// May want to try out a syncthreads in here, rather than after the loop
}
__syncthreads();
}
*/
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
void colOrderFrom(float* row_ordered, float* col_ordered, int rows, int cols) {
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
col_ordered[i + rows * j] = row_ordered[j + cols * i];
}
}
}
void initRandMatrixColOrdered(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[i + rows * j] = dis(gen);
}
}
return;
}
void printMatrix(float* mem, int rows, int cols) {
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
std::cout << mem[j + cols * i] << " ";
}
std::cout << std::endl;
}
}
int main(void) {
//cudaFuncSetAttribute(matrixMultiplyWmma, cudaFuncAttributeMaxDynamicSharedMemorySize, BLOCK_TILE_HEIGHT * BLOCK_TILE_WIDTH * sizeof(float));
float* h_A = new float[l * m];
float* h_Acol = new float[l * m];
float* h_B = new float[m * n];
float* h_Bcol = new float[m * n];
float* h_C = new float[l * n];
float* h_C3 = new float[l * n];
float* h_Ccol = new float[l * n];
float* h_Ccol2 = new float[l * n];
float *d_A, *d_Acol, *d_B, *d_Bcol, *d_C, *d_Ccol, *d_Ccol2, *d_C3;
hipError_t err_A = hipMalloc((void **) &d_A, l * m * sizeof(float));
hipError_t err_Acol = hipMalloc((void **) &d_Acol, l * m * sizeof(float));
hipError_t err_B = hipMalloc((void **) &d_B, m * n * sizeof(float));
hipError_t err_Bcol = hipMalloc((void **) &d_Bcol, m * n * sizeof(float));
hipError_t err_C = hipMalloc((void **) &d_C, l * n * sizeof(float));
hipError_t err_Ccol = hipMalloc((void **) &d_Ccol, l * n * sizeof(float));
hipError_t err_C3 = hipMalloc((void **) &d_C3, l * n * sizeof(float));
initRandMatrix(h_A, l, m);
initRandMatrix(h_B, m, n);
colOrderFrom(h_B, h_Bcol, m, n);
colOrderFrom(h_A, h_Acol, l, m);
//printMatrix(h_A, l, m);
//printMatrix(h_B, m, n);
hipMemcpy(d_A, h_A, l * m * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_Acol, h_Acol, l * m * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_Bcol, h_Bcol, m * n * sizeof(float), hipMemcpyHostToDevice);
hipMemset(d_C, 0, l * n * sizeof(float));
hipMemset(d_Ccol, 0, l * n * sizeof(float));
hipMemset(d_C3, 0, l * n * sizeof(float));
matrixMultiplyNaive<<<nblocks, tbp>>>(d_A, d_B, d_C, l, m, n);
matrixMultiplyNaiveBColOrdered<<<nblocks, tbp>>>(d_A, d_Bcol, d_Ccol, l, m, n);
//matrixMultiplyNaiveAColOrdered<<<nblocks, tbp>>>(d_Acol, d_B, d_Ccol2, l, m, n);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
dim3 dimGrid(n / TILE_WIDTH, l / TILE_WIDTH);
matrixMultiplyShmem<<<dimGrid, dimBlock>>>(d_A, d_B, d_C3, l, m, n);
dim3 dimBlock2(THREADS_PER_WARP * BLOCK_WARP_COLS, BLOCK_WARP_ROWS);
dim3 dimGrid2(n / BLOCK_TILE_WIDTH, l / BLOCK_TILE_HEIGHT);
// matrixMultiplyWmma<<<dimGrid2, dimBlock2, BLOCK_TILE_WIDTH * BLOCK_TILE_HEIGHT * sizeof(float) >>>(d_A, d_B, d_C3, l, m, n);
hipMemcpy(h_C, d_C, l * n * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(h_C3, d_C3, l * n * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(h_Ccol, d_Ccol, l * n * sizeof(float), hipMemcpyDeviceToHost);
//cudaMemcpy(h_Ccol2, d_Ccol2, l * n * sizeof(float), cudaMemcpyDeviceToHost);
bool agrees = true;
for (int i = 0; i < l; ++i) {
for (int j = 0; j < n; ++j) {
if (h_Ccol[j + n * i] != h_C[j + n * i])
agrees = false;
}
}
std::cout << agrees << std::endl;
for (int i = 0; i < l; ++i) {
for (int j = 0; j < n; ++j) {
if (h_C3[j + n * i] != h_C[j + n * i])
agrees = false;
}
}
std::cout << agrees << std::endl;
hipError_t err = hipGetLastError();
if (err != hipSuccess) std::cout << "CUDA error: " << hipGetErrorString(err) << std::endl;
delete [] h_A;
delete [] h_B;
delete [] h_Bcol;
delete [] h_C;
delete [] h_C3;
delete [] h_Ccol;
hipFree(d_A);
hipFree(d_B);
hipFree(d_Bcol);
hipFree(d_C);
hipFree(d_C3);
hipFree(d_Ccol);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19matrixMultiplyNaivePfS_S_iii
.globl _Z19matrixMultiplyNaivePfS_S_iii
.p2align 8
.type _Z19matrixMultiplyNaivePfS_S_iii,@function
_Z19matrixMultiplyNaivePfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v1, v3, vcc_lo
v_mul_lo_u32 v1, v5, s3
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v5, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v5, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19matrixMultiplyNaivePfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19matrixMultiplyNaivePfS_S_iii, .Lfunc_end0-_Z19matrixMultiplyNaivePfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii
.globl _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii
.p2align 8
.type _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii,@function
_Z30matrixMultiplyNaiveBColOrderedPfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v1, v3, vcc_lo
v_mul_lo_u32 v1, v5, s3
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
s_cbranch_scc1 .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_lo_u32 v1, v0, s2
v_mul_lo_u32 v3, v5, s2
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB1_2:
global_load_b32 v7, v[3:4], off
global_load_b32 v8, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v7, v8
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v6, 0
.LBB1_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v5, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii, .Lfunc_end1-_Z30matrixMultiplyNaiveBColOrderedPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii
.globl _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii
.p2align 8
.type _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii,@function
_Z30matrixMultiplyNaiveAColOrderedPfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x1c
v_lshl_add_u32 v3, s15, 9, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v2
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, 1, v0
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v1, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_mul_lo_u32 v1, v0, s3
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v3, v1
s_cbranch_scc1 .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v2
s_ashr_i32 s9, s2, 31
s_mov_b32 s8, s2
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_lshl_b64 s[4:5], s[8:9], 2
.p2align 6
.LBB2_2:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_nc_u32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v8, v6
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
v_mov_b32_e32 v1, 0
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s3, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii, .Lfunc_end2-_Z30matrixMultiplyNaiveAColOrderedPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19matrixMultiplyShmemPfS_S_iii
.globl _Z19matrixMultiplyShmemPfS_S_iii
.p2align 8
.type _Z19matrixMultiplyShmemPfS_S_iii,@function
_Z19matrixMultiplyShmemPfS_S_iii:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x1c
v_dual_mov_b32 v68, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 2, v1
v_lshlrev_b32_e32 v0, 7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v9, 0x1000, v5
v_add_nc_u32_e32 v11, 0x1080, v5
v_add_nc_u32_e32 v8, v0, v5
v_or_b32_e32 v10, 4, v0
v_or_b32_e32 v12, 8, v0
v_add_nc_u32_e32 v13, 0x1100, v5
v_or_b32_e32 v14, 12, v0
v_add_nc_u32_e32 v15, 0x1180, v5
s_waitcnt lgkmcnt(0)
s_lshr_b32 s9, s8, 16
v_mul_lo_u32 v6, v4, s3
v_mad_u64_u32 v[2:3], null, s15, s9, v[4:5]
s_and_b32 s8, s8, 0xffff
v_add_nc_u32_e32 v16, v9, v0
s_mul_i32 s14, s14, s8
v_or_b32_e32 v17, 16, v0
v_add_nc_u32_e32 v18, 0x1200, v5
v_or_b32_e32 v19, 20, v0
v_mad_u64_u32 v[3:4], null, v2, s2, v[1:2]
v_add_nc_u32_e32 v20, 0x1280, v5
v_or_b32_e32 v21, 24, v0
v_add_nc_u32_e32 v22, 0x1300, v5
v_or_b32_e32 v23, 28, v0
v_add_nc_u32_e32 v24, 0x1380, v5
v_or_b32_e32 v25, 32, v0
v_add_nc_u32_e32 v26, 0x1400, v5
v_or_b32_e32 v27, 36, v0
v_add_nc_u32_e32 v28, 0x1480, v5
v_or_b32_e32 v29, 40, v0
v_add_nc_u32_e32 v30, 0x1500, v5
v_or_b32_e32 v31, 44, v0
v_add_nc_u32_e32 v32, 0x1580, v5
v_or_b32_e32 v33, 48, v0
v_add_nc_u32_e32 v34, 0x1600, v5
v_or_b32_e32 v35, 52, v0
v_add_nc_u32_e32 v36, 0x1680, v5
v_or_b32_e32 v37, 56, v0
v_add_nc_u32_e32 v38, 0x1700, v5
v_or_b32_e32 v39, 60, v0
v_add_nc_u32_e32 v40, 0x1780, v5
v_or_b32_e32 v41, 64, v0
v_add_nc_u32_e32 v42, 0x1800, v5
v_or_b32_e32 v43, 0x44, v0
v_add_nc_u32_e32 v44, 0x1880, v5
v_or_b32_e32 v45, 0x48, v0
v_add_nc_u32_e32 v46, 0x1900, v5
v_or_b32_e32 v47, 0x4c, v0
v_add_nc_u32_e32 v48, 0x1980, v5
v_or_b32_e32 v49, 0x50, v0
v_add_nc_u32_e32 v50, 0x1a00, v5
v_or_b32_e32 v51, 0x54, v0
v_add_nc_u32_e32 v52, 0x1a80, v5
v_or_b32_e32 v53, 0x58, v0
v_add_nc_u32_e32 v54, 0x1b00, v5
v_or_b32_e32 v55, 0x5c, v0
v_add_nc_u32_e32 v56, 0x1b80, v5
v_or_b32_e32 v57, 0x60, v0
v_add_nc_u32_e32 v58, 0x1c00, v5
v_or_b32_e32 v59, 0x64, v0
v_add_nc_u32_e32 v60, 0x1c80, v5
v_or_b32_e32 v61, 0x68, v0
v_add_nc_u32_e32 v62, 0x1d00, v5
v_or_b32_e32 v63, 0x6c, v0
v_add_nc_u32_e32 v64, 0x1d80, v5
v_or_b32_e32 v65, 0x70, v0
v_add_nc_u32_e32 v66, 0x1e00, v5
v_or_b32_e32 v67, 0x74, v0
v_add_nc_u32_e32 v69, 0x1e80, v5
v_or_b32_e32 v70, 0x78, v0
v_add_nc_u32_e32 v71, 0x1f00, v5
v_or_b32_e32 v72, 0x7c, v0
v_add_nc_u32_e32 v73, 0x1f80, v5
v_add3_u32 v4, v1, v6, s14
s_lshl_b32 s2, s3, 5
s_mov_b32 s8, 0
.LBB3_1:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v5, v7 :: v_dual_add_nc_u32 v6, s8, v3
s_add_i32 s8, s8, 32
s_cmpk_eq_i32 s8, 0x800
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[74:75], 2, v[6:7]
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v74, vcc_lo, s4, v74
v_add_co_ci_u32_e32 v75, vcc_lo, s5, v75, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v74, v[74:75], off
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(1)
ds_store_b32 v8, v74
s_waitcnt vmcnt(0)
ds_store_b32 v16, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v0
ds_load_b32 v6, v9
ds_load_b32 v74, v10
ds_load_b32 v75, v11
ds_load_b32 v76, v12
ds_load_b32 v77, v13
ds_load_b32 v78, v14
ds_load_b32 v79, v15
ds_load_b32 v80, v17
ds_load_b32 v81, v18
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v5, v6
ds_load_b32 v5, v19
ds_load_b32 v6, v20
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v74, v75
ds_load_b32 v74, v21
ds_load_b32 v75, v22
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v76, v77
ds_load_b32 v76, v23
ds_load_b32 v77, v24
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v78, v79
ds_load_b32 v78, v25
ds_load_b32 v79, v26
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v80, v81
ds_load_b32 v80, v27
ds_load_b32 v81, v28
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v5, v6
ds_load_b32 v5, v29
ds_load_b32 v6, v30
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v74, v75
ds_load_b32 v74, v31
ds_load_b32 v75, v32
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v76, v77
ds_load_b32 v76, v33
ds_load_b32 v77, v34
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v78, v79
ds_load_b32 v78, v35
ds_load_b32 v79, v36
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v80, v81
ds_load_b32 v80, v37
ds_load_b32 v81, v38
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v5, v6
ds_load_b32 v5, v39
ds_load_b32 v6, v40
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v74, v75
ds_load_b32 v74, v41
ds_load_b32 v75, v42
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v76, v77
ds_load_b32 v76, v43
ds_load_b32 v77, v44
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v78, v79
ds_load_b32 v78, v45
ds_load_b32 v79, v46
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v80, v81
ds_load_b32 v80, v47
ds_load_b32 v81, v48
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v5, v6
ds_load_b32 v5, v49
ds_load_b32 v6, v50
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v74, v75
ds_load_b32 v74, v51
ds_load_b32 v75, v52
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v76, v77
ds_load_b32 v76, v53
ds_load_b32 v77, v54
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v78, v79
ds_load_b32 v78, v55
ds_load_b32 v79, v56
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v80, v81
ds_load_b32 v80, v57
ds_load_b32 v81, v58
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v5, v6
ds_load_b32 v5, v59
ds_load_b32 v6, v60
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v74, v75
ds_load_b32 v74, v61
ds_load_b32 v75, v62
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v76, v77
ds_load_b32 v76, v63
ds_load_b32 v77, v64
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v78, v79
ds_load_b32 v78, v65
ds_load_b32 v79, v66
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v80, v81
ds_load_b32 v80, v67
ds_load_b32 v81, v69
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v5, v6
ds_load_b32 v5, v70
ds_load_b32 v6, v71
s_waitcnt lgkmcnt(8)
v_fmac_f32_e32 v68, v74, v75
ds_load_b32 v74, v72
ds_load_b32 v75, v73
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v68, v76, v77
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v68, v78, v79
v_fmac_f32_e32 v68, v80, v81
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v68, v5, v6
v_fmac_f32_e32 v68, v74, v75
s_cbranch_scc0 .LBB3_1
v_mul_lo_u32 v0, v2, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v68, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19matrixMultiplyShmemPfS_S_iii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 82
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z19matrixMultiplyShmemPfS_S_iii, .Lfunc_end3-_Z19matrixMultiplyShmemPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19matrixMultiplyNaivePfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19matrixMultiplyNaivePfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30matrixMultiplyNaiveBColOrderedPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30matrixMultiplyNaiveAColOrderedPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19matrixMultiplyShmemPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19matrixMultiplyShmemPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 82
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void SumSymbolsKernel( float *symbolOne, float *symbolTwo, float *result, int symbolSize )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < symbolSize)
{
result[threadId] = symbolOne[threadId] + symbolTwo[threadId];
}
} | code for sm_80
Function : _Z16SumSymbolsKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void SumSymbolsKernel( float *symbolOne, float *symbolTwo, float *result, int symbolSize )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < symbolSize)
{
result[threadId] = symbolOne[threadId] + symbolTwo[threadId];
}
} | .file "tmpxft_00002ce2_00000000-6_SumSymbolsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i
.type _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16SumSymbolsKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i, .-_Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i
.globl _Z16SumSymbolsKernelPfS_S_i
.type _Z16SumSymbolsKernelPfS_S_i, @function
_Z16SumSymbolsKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16SumSymbolsKernelPfS_S_i, .-_Z16SumSymbolsKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16SumSymbolsKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16SumSymbolsKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void SumSymbolsKernel( float *symbolOne, float *symbolTwo, float *result, int symbolSize )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < symbolSize)
{
result[threadId] = symbolOne[threadId] + symbolTwo[threadId];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SumSymbolsKernel( float *symbolOne, float *symbolTwo, float *result, int symbolSize )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < symbolSize)
{
result[threadId] = symbolOne[threadId] + symbolTwo[threadId];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SumSymbolsKernel( float *symbolOne, float *symbolTwo, float *result, int symbolSize )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < symbolSize)
{
result[threadId] = symbolOne[threadId] + symbolTwo[threadId];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16SumSymbolsKernelPfS_S_i
.globl _Z16SumSymbolsKernelPfS_S_i
.p2align 8
.type _Z16SumSymbolsKernelPfS_S_i,@function
_Z16SumSymbolsKernelPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16SumSymbolsKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16SumSymbolsKernelPfS_S_i, .Lfunc_end0-_Z16SumSymbolsKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16SumSymbolsKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16SumSymbolsKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void SumSymbolsKernel( float *symbolOne, float *symbolTwo, float *result, int symbolSize )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < symbolSize)
{
result[threadId] = symbolOne[threadId] + symbolTwo[threadId];
}
} | .text
.file "SumSymbolsKernel.hip"
.globl _Z31__device_stub__SumSymbolsKernelPfS_S_i # -- Begin function _Z31__device_stub__SumSymbolsKernelPfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__SumSymbolsKernelPfS_S_i,@function
_Z31__device_stub__SumSymbolsKernelPfS_S_i: # @_Z31__device_stub__SumSymbolsKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16SumSymbolsKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__SumSymbolsKernelPfS_S_i, .Lfunc_end0-_Z31__device_stub__SumSymbolsKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16SumSymbolsKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16SumSymbolsKernelPfS_S_i,@object # @_Z16SumSymbolsKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z16SumSymbolsKernelPfS_S_i
.p2align 3, 0x0
_Z16SumSymbolsKernelPfS_S_i:
.quad _Z31__device_stub__SumSymbolsKernelPfS_S_i
.size _Z16SumSymbolsKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16SumSymbolsKernelPfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__SumSymbolsKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16SumSymbolsKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16SumSymbolsKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16SumSymbolsKernelPfS_S_i
.globl _Z16SumSymbolsKernelPfS_S_i
.p2align 8
.type _Z16SumSymbolsKernelPfS_S_i,@function
_Z16SumSymbolsKernelPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16SumSymbolsKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16SumSymbolsKernelPfS_S_i, .Lfunc_end0-_Z16SumSymbolsKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16SumSymbolsKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16SumSymbolsKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00002ce2_00000000-6_SumSymbolsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i
.type _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i, @function
_Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16SumSymbolsKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i, .-_Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i
.globl _Z16SumSymbolsKernelPfS_S_i
.type _Z16SumSymbolsKernelPfS_S_i, @function
_Z16SumSymbolsKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16SumSymbolsKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16SumSymbolsKernelPfS_S_i, .-_Z16SumSymbolsKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16SumSymbolsKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16SumSymbolsKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SumSymbolsKernel.hip"
.globl _Z31__device_stub__SumSymbolsKernelPfS_S_i # -- Begin function _Z31__device_stub__SumSymbolsKernelPfS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__SumSymbolsKernelPfS_S_i,@function
_Z31__device_stub__SumSymbolsKernelPfS_S_i: # @_Z31__device_stub__SumSymbolsKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16SumSymbolsKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__SumSymbolsKernelPfS_S_i, .Lfunc_end0-_Z31__device_stub__SumSymbolsKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16SumSymbolsKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16SumSymbolsKernelPfS_S_i,@object # @_Z16SumSymbolsKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z16SumSymbolsKernelPfS_S_i
.p2align 3, 0x0
_Z16SumSymbolsKernelPfS_S_i:
.quad _Z31__device_stub__SumSymbolsKernelPfS_S_i
.size _Z16SumSymbolsKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16SumSymbolsKernelPfS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__SumSymbolsKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16SumSymbolsKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// #pragma once
using namespace std;
#define NUM_THREADS_PER_BLOCK 512
int* create_shifts (char* pattern);
int linear_horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size,
int num_chunks, int text_size, int pat_len, int myId);
/*
* Driver function
* argv[0] is target pattern string
* argv[1] is text path
*/
__global__ void horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size, int num_chunks, int text_size, int pat_len) {
const int TABLE_SIZ = 126;
int count = 0;
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if(myId > num_chunks){ //if thread is an invalid thread
return;
}
int text_length = (chunk_size * myId) + chunk_size + pat_len - 1;
// don't need to check first pattern_length - 1 characters
int i = (myId*chunk_size) + pat_len - 1;
int k = 0;
while(i < text_length) {
// reset matched character count
k = 0;
if (i >= text_size) {
// break out if i tries to step past text length
break;
}
if (text[i] >= TABLE_SIZ || text[i] < 0) {
// move to next char if unknown char (Unicode, etc.)
++i;
} else {
while(k <= pat_len - 1 && pattern[pat_len - 1 - k] == text[i - k]) {
// increment matched character count
k++;
}
if(k == pat_len) {
// increment pattern count, text index
++count;
++i;
} else {
// add on shift if known char
i = i + shift_table[text[i]];
}
}
}
atomicAdd(num_matches, count);
} | code for sm_80
Function : _Z14horspool_matchPcS_PiPjiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x580 ; /* 0x000004f000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R2, R0.reuse, R3.reuse, c[0x0][0x180] ; /* 0x0000600000027624 */
/* 0x0c0fe400078e0203 */
/*00a0*/ IMAD R3, R0, R3, c[0x0][0x18c] ; /* 0x0000630000037624 */
/* 0x000fc600078e0203 */
/*00b0*/ IADD3 R0, R2, c[0x0][0x18c], RZ ; /* 0x0000630002007a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fc80003f06270 */
/*0100*/ ISETP.GE.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fda0000706670 */
/*0110*/ @P0 BRA 0x570 ; /* 0x0000045000000947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fda0003f01270 */
/*0130*/ @P0 BRA 0x2e0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0140*/ BSSY B1, 0x2d0 ; /* 0x0000018000017945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0160*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003057a11 */
/* 0x000fca00000f0eff */
/*0180*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*0190*/ BSSY B2, 0x290 ; /* 0x000000f000027945 */
/* 0x000fe20003800000 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R4, 0x7d, PT ; /* 0x0000007d0400780c */
/* 0x004fda0003f04070 */
/*01b0*/ @P0 BRA 0x270 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05270 */
/*01d0*/ @!P0 BRA 0x240 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01e0*/ PRMT R4, R4, 0x8880, RZ ; /* 0x0000888004047816 */
/* 0x000fe200000000ff */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0205 */
/*0210*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x004fe200078e0203 */
/*0230*/ BRA 0x280 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*0260*/ BRA 0x280 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0280*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fc80003f06270 */
/*02a0*/ ISETP.GE.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fda0000706670 */
/*02b0*/ @!P0 BRA 0x160 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x570 ; /* 0x0000029000007947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*02f0*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f1e0ff */
/*0300*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003057a11 */
/* 0x000fca00000f0eff */
/*0310*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*0320*/ BSSY B1, 0x540 ; /* 0x0000021000017945 */
/* 0x000fe20003800000 */
/*0330*/ ISETP.GT.U32.AND P0, PT, R4, 0x7d, PT ; /* 0x0000007d0400780c */
/* 0x004fda0003f04070 */
/*0340*/ @P0 BRA 0x520 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0350*/ PRMT R9, R4, 0x8880, RZ ; /* 0x0000888004097816 */
/* 0x000fe200000000ff */
/*0360*/ BSSY B2, 0x480 ; /* 0x0000011000027945 */
/* 0x000fe20003800000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0380*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc60000011409 */
/*0390*/ LOP3.LUT R4, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff047212 */
/* 0x000fe200078e33ff */
/*03a0*/ IMAD.IADD R5, R3, 0x1, -R8 ; /* 0x0000000103057824 */
/* 0x000fc600078e0a08 */
/*03b0*/ IADD3 R7, R4, c[0x0][0x18c], RZ ; /* 0x0000630004077a10 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R4, P1, R5, c[0x0][0x160], RZ ; /* 0x0000580005047a10 */
/* 0x000fe40007f3e0ff */
/*03d0*/ IADD3 R6, P0, R7, c[0x0][0x168], RZ ; /* 0x00005a0007067a10 */
/* 0x000fe40007f1e0ff */
/*03e0*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P1 ; /* 0x0000590005057a11 */
/* 0x000fe400008f0eff */
/*03f0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0007077a11 */
/* 0x000fc600000f0eff */
/*0400*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1100 */
/*0410*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea4000c1e1100 */
/*0420*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f05270 */
/*0430*/ @P0 BRA 0x470 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0450*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x18c], PT ; /* 0x0000630008007a0c */
/* 0x000fda0003f06270 */
/*0460*/ @!P0 BRA 0x390 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0470*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.AND P0, PT, R8, c[0x0][0x18c], PT ; /* 0x0000630008007a0c */
/* 0x000fda0003f05270 */
/*0490*/ @!P0 BRA 0x4f0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*04a0*/ LEA R4, P0, R9, c[0x0][0x170], 0x2 ; /* 0x00005c0009047a11 */
/* 0x000fc800078010ff */
/*04b0*/ LEA.HI.X R5, R9, c[0x0][0x174], R10, 0x2, P0 ; /* 0x00005d0009057a11 */
/* 0x000fca00000f140a */
/*04c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*04d0*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x004fe200078e0203 */
/*04e0*/ BRA 0x530 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0500*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*0510*/ BRA 0x530 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.AND P0, PT, R3.reuse, R0, PT ; /* 0x000000000300720c */
/* 0x040fe40003f06270 */
/*0550*/ ISETP.LT.AND P1, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fda0003f21270 */
/*0560*/ @!P0 BRA P1, 0x2f0 ; /* 0xfffffd8000008947 */
/* 0x000fea000083ffff */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0580*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0590*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x000e62000000c000 */
/*05a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*05c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*05d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*05e0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*05f0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x002fd8000f8e00ff */
/*0600*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400098e */
/* 0x000fe2000c10e186 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// #pragma once
using namespace std;
#define NUM_THREADS_PER_BLOCK 512
int* create_shifts (char* pattern);
int linear_horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size,
int num_chunks, int text_size, int pat_len, int myId);
/*
* Driver function
* argv[0] is target pattern string
* argv[1] is text path
*/
__global__ void horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size, int num_chunks, int text_size, int pat_len) {
const int TABLE_SIZ = 126;
int count = 0;
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if(myId > num_chunks){ //if thread is an invalid thread
return;
}
int text_length = (chunk_size * myId) + chunk_size + pat_len - 1;
// don't need to check first pattern_length - 1 characters
int i = (myId*chunk_size) + pat_len - 1;
int k = 0;
while(i < text_length) {
// reset matched character count
k = 0;
if (i >= text_size) {
// break out if i tries to step past text length
break;
}
if (text[i] >= TABLE_SIZ || text[i] < 0) {
// move to next char if unknown char (Unicode, etc.)
++i;
} else {
while(k <= pat_len - 1 && pattern[pat_len - 1 - k] == text[i - k]) {
// increment matched character count
k++;
}
if(k == pat_len) {
// increment pattern count, text index
++count;
++i;
} else {
// add on shift if known char
i = i + shift_table[text[i]];
}
}
}
atomicAdd(num_matches, count);
} | .file "tmpxft_000b667c_00000000-6_horspool_match.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii
.type _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii, @function
_Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14horspool_matchPcS_PiPjiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii, .-_Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii
.globl _Z14horspool_matchPcS_PiPjiiii
.type _Z14horspool_matchPcS_PiPjiiii, @function
_Z14horspool_matchPcS_PiPjiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14horspool_matchPcS_PiPjiiii, .-_Z14horspool_matchPcS_PiPjiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14horspool_matchPcS_PiPjiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14horspool_matchPcS_PiPjiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// #pragma once
using namespace std;
#define NUM_THREADS_PER_BLOCK 512
int* create_shifts (char* pattern);
int linear_horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size,
int num_chunks, int text_size, int pat_len, int myId);
/*
* Driver function
* argv[0] is target pattern string
* argv[1] is text path
*/
__global__ void horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size, int num_chunks, int text_size, int pat_len) {
const int TABLE_SIZ = 126;
int count = 0;
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if(myId > num_chunks){ //if thread is an invalid thread
return;
}
int text_length = (chunk_size * myId) + chunk_size + pat_len - 1;
// don't need to check first pattern_length - 1 characters
int i = (myId*chunk_size) + pat_len - 1;
int k = 0;
while(i < text_length) {
// reset matched character count
k = 0;
if (i >= text_size) {
// break out if i tries to step past text length
break;
}
if (text[i] >= TABLE_SIZ || text[i] < 0) {
// move to next char if unknown char (Unicode, etc.)
++i;
} else {
while(k <= pat_len - 1 && pattern[pat_len - 1 - k] == text[i - k]) {
// increment matched character count
k++;
}
if(k == pat_len) {
// increment pattern count, text index
++count;
++i;
} else {
// add on shift if known char
i = i + shift_table[text[i]];
}
}
}
atomicAdd(num_matches, count);
} | #include <hip/hip_runtime.h>
#include "includes.h"
// #pragma once
using namespace std;
#define NUM_THREADS_PER_BLOCK 512
int* create_shifts (char* pattern);
int linear_horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size,
int num_chunks, int text_size, int pat_len, int myId);
/*
* Driver function
* argv[0] is target pattern string
* argv[1] is text path
*/
__global__ void horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size, int num_chunks, int text_size, int pat_len) {
const int TABLE_SIZ = 126;
int count = 0;
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if(myId > num_chunks){ //if thread is an invalid thread
return;
}
int text_length = (chunk_size * myId) + chunk_size + pat_len - 1;
// don't need to check first pattern_length - 1 characters
int i = (myId*chunk_size) + pat_len - 1;
int k = 0;
while(i < text_length) {
// reset matched character count
k = 0;
if (i >= text_size) {
// break out if i tries to step past text length
break;
}
if (text[i] >= TABLE_SIZ || text[i] < 0) {
// move to next char if unknown char (Unicode, etc.)
++i;
} else {
while(k <= pat_len - 1 && pattern[pat_len - 1 - k] == text[i - k]) {
// increment matched character count
k++;
}
if(k == pat_len) {
// increment pattern count, text index
++count;
++i;
} else {
// add on shift if known char
i = i + shift_table[text[i]];
}
}
}
atomicAdd(num_matches, count);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// #pragma once
using namespace std;
#define NUM_THREADS_PER_BLOCK 512
int* create_shifts (char* pattern);
int linear_horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size,
int num_chunks, int text_size, int pat_len, int myId);
/*
* Driver function
* argv[0] is target pattern string
* argv[1] is text path
*/
__global__ void horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size, int num_chunks, int text_size, int pat_len) {
const int TABLE_SIZ = 126;
int count = 0;
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if(myId > num_chunks){ //if thread is an invalid thread
return;
}
int text_length = (chunk_size * myId) + chunk_size + pat_len - 1;
// don't need to check first pattern_length - 1 characters
int i = (myId*chunk_size) + pat_len - 1;
int k = 0;
while(i < text_length) {
// reset matched character count
k = 0;
if (i >= text_size) {
// break out if i tries to step past text length
break;
}
if (text[i] >= TABLE_SIZ || text[i] < 0) {
// move to next char if unknown char (Unicode, etc.)
++i;
} else {
while(k <= pat_len - 1 && pattern[pat_len - 1 - k] == text[i - k]) {
// increment matched character count
k++;
}
if(k == pat_len) {
// increment pattern count, text index
++count;
++i;
} else {
// add on shift if known char
i = i + shift_table[text[i]];
}
}
}
atomicAdd(num_matches, count);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14horspool_matchPcS_PiPjiiii
.globl _Z14horspool_matchPcS_PiPjiiii
.p2align 8
.type _Z14horspool_matchPcS_PiPjiiii,@function
_Z14horspool_matchPcS_PiPjiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_24
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v1, s4
s_add_i32 s5, s3, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, s5, s4, v0
v_add_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_min_i32_e32 v4, s2, v1
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_20
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_cmp_gt_i32 s3, 0
s_mov_b32 s11, 0
s_cselect_b32 s10, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_19
.LBB0_4:
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v3
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_u16_e32 0x7e, v6
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_17
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_11
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s14, -1
s_mov_b32 s13, 0
s_mov_b32 s15, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s17, exec_lo, s16
s_or_b32 s13, s17, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_10
.LBB0_8:
s_add_i32 s17, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s19, s17, 31
s_add_u32 s18, s6, s17
s_addc_u32 s19, s7, s19
global_load_u8 v7, v[0:1], off
global_load_u8 v8, v5, s[18:19]
s_or_b32 s16, s16, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v8, v7
v_mov_b32_e32 v7, s15
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_7
s_add_i32 s15, s15, 1
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s3, s15
v_add_co_u32 v0, vcc_lo, v0, -1
s_cselect_b32 s18, -1, 0
v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
v_mov_b32_e32 v7, s3
s_and_not1_b32 s16, s16, exec_lo
s_and_b32 s18, s18, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s16, s16, s18
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_branch .LBB0_12
.LBB0_11:
v_mov_b32_e32 v7, 0
.LBB0_12:
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 s3, v7
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_14
v_and_b32_e32 v0, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v0, v0, s[8:9]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v0, v3
.LBB0_14:
s_and_not1_saveexec_b32 s13, s13
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v3
s_or_b32 exec_lo, exec_lo, s13
.LBB0_17:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v3
s_branch .LBB0_3
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
.LBB0_21:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v2, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_21
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_24
s_load_b64 s[0:1], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14horspool_matchPcS_PiPjiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14horspool_matchPcS_PiPjiiii, .Lfunc_end0-_Z14horspool_matchPcS_PiPjiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14horspool_matchPcS_PiPjiiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z14horspool_matchPcS_PiPjiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// #pragma once
using namespace std;
#define NUM_THREADS_PER_BLOCK 512
int* create_shifts (char* pattern);
int linear_horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size,
int num_chunks, int text_size, int pat_len, int myId);
/*
* Driver function
* argv[0] is target pattern string
* argv[1] is text path
*/
__global__ void horspool_match (char* text, char* pattern, int* shift_table, unsigned int* num_matches, int chunk_size, int num_chunks, int text_size, int pat_len) {
const int TABLE_SIZ = 126;
int count = 0;
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if(myId > num_chunks){ //if thread is an invalid thread
return;
}
int text_length = (chunk_size * myId) + chunk_size + pat_len - 1;
// don't need to check first pattern_length - 1 characters
int i = (myId*chunk_size) + pat_len - 1;
int k = 0;
while(i < text_length) {
// reset matched character count
k = 0;
if (i >= text_size) {
// break out if i tries to step past text length
break;
}
if (text[i] >= TABLE_SIZ || text[i] < 0) {
// move to next char if unknown char (Unicode, etc.)
++i;
} else {
while(k <= pat_len - 1 && pattern[pat_len - 1 - k] == text[i - k]) {
// increment matched character count
k++;
}
if(k == pat_len) {
// increment pattern count, text index
++count;
++i;
} else {
// add on shift if known char
i = i + shift_table[text[i]];
}
}
}
atomicAdd(num_matches, count);
} | .text
.file "horspool_match.hip"
.globl _Z29__device_stub__horspool_matchPcS_PiPjiiii # -- Begin function _Z29__device_stub__horspool_matchPcS_PiPjiiii
.p2align 4, 0x90
.type _Z29__device_stub__horspool_matchPcS_PiPjiiii,@function
_Z29__device_stub__horspool_matchPcS_PiPjiiii: # @_Z29__device_stub__horspool_matchPcS_PiPjiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14horspool_matchPcS_PiPjiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__horspool_matchPcS_PiPjiiii, .Lfunc_end0-_Z29__device_stub__horspool_matchPcS_PiPjiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14horspool_matchPcS_PiPjiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14horspool_matchPcS_PiPjiiii,@object # @_Z14horspool_matchPcS_PiPjiiii
.section .rodata,"a",@progbits
.globl _Z14horspool_matchPcS_PiPjiiii
.p2align 3, 0x0
_Z14horspool_matchPcS_PiPjiiii:
.quad _Z29__device_stub__horspool_matchPcS_PiPjiiii
.size _Z14horspool_matchPcS_PiPjiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14horspool_matchPcS_PiPjiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__horspool_matchPcS_PiPjiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14horspool_matchPcS_PiPjiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14horspool_matchPcS_PiPjiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x580 ; /* 0x000004f000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R2, R0.reuse, R3.reuse, c[0x0][0x180] ; /* 0x0000600000027624 */
/* 0x0c0fe400078e0203 */
/*00a0*/ IMAD R3, R0, R3, c[0x0][0x18c] ; /* 0x0000630000037624 */
/* 0x000fc600078e0203 */
/*00b0*/ IADD3 R0, R2, c[0x0][0x18c], RZ ; /* 0x0000630002007a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fc80003f06270 */
/*0100*/ ISETP.GE.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fda0000706670 */
/*0110*/ @P0 BRA 0x570 ; /* 0x0000045000000947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fda0003f01270 */
/*0130*/ @P0 BRA 0x2e0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0140*/ BSSY B1, 0x2d0 ; /* 0x0000018000017945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*0160*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003057a11 */
/* 0x000fca00000f0eff */
/*0180*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*0190*/ BSSY B2, 0x290 ; /* 0x000000f000027945 */
/* 0x000fe20003800000 */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R4, 0x7d, PT ; /* 0x0000007d0400780c */
/* 0x004fda0003f04070 */
/*01b0*/ @P0 BRA 0x270 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fda0003f05270 */
/*01d0*/ @!P0 BRA 0x240 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01e0*/ PRMT R4, R4, 0x8880, RZ ; /* 0x0000888004047816 */
/* 0x000fe200000000ff */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0205 */
/*0210*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0220*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x004fe200078e0203 */
/*0230*/ BRA 0x280 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*0260*/ BRA 0x280 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0280*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fc80003f06270 */
/*02a0*/ ISETP.GE.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fda0000706670 */
/*02b0*/ @!P0 BRA 0x160 ; /* 0xfffffea000008947 */
/* 0x000fea000383ffff */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x570 ; /* 0x0000029000007947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*02f0*/ IADD3 R4, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f1e0ff */
/*0300*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003057a11 */
/* 0x000fca00000f0eff */
/*0310*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1100 */
/*0320*/ BSSY B1, 0x540 ; /* 0x0000021000017945 */
/* 0x000fe20003800000 */
/*0330*/ ISETP.GT.U32.AND P0, PT, R4, 0x7d, PT ; /* 0x0000007d0400780c */
/* 0x004fda0003f04070 */
/*0340*/ @P0 BRA 0x520 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0350*/ PRMT R9, R4, 0x8880, RZ ; /* 0x0000888004097816 */
/* 0x000fe200000000ff */
/*0360*/ BSSY B2, 0x480 ; /* 0x0000011000027945 */
/* 0x000fe20003800000 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0380*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc60000011409 */
/*0390*/ LOP3.LUT R4, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff047212 */
/* 0x000fe200078e33ff */
/*03a0*/ IMAD.IADD R5, R3, 0x1, -R8 ; /* 0x0000000103057824 */
/* 0x000fc600078e0a08 */
/*03b0*/ IADD3 R7, R4, c[0x0][0x18c], RZ ; /* 0x0000630004077a10 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R4, P1, R5, c[0x0][0x160], RZ ; /* 0x0000580005047a10 */
/* 0x000fe40007f3e0ff */
/*03d0*/ IADD3 R6, P0, R7, c[0x0][0x168], RZ ; /* 0x00005a0007067a10 */
/* 0x000fe40007f1e0ff */
/*03e0*/ LEA.HI.X.SX32 R5, R5, c[0x0][0x164], 0x1, P1 ; /* 0x0000590005057a11 */
/* 0x000fe400008f0eff */
/*03f0*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0007077a11 */
/* 0x000fc600000f0eff */
/*0400*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1100 */
/*0410*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea4000c1e1100 */
/*0420*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f05270 */
/*0430*/ @P0 BRA 0x470 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0450*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x18c], PT ; /* 0x0000630008007a0c */
/* 0x000fda0003f06270 */
/*0460*/ @!P0 BRA 0x390 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0470*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0480*/ ISETP.NE.AND P0, PT, R8, c[0x0][0x18c], PT ; /* 0x0000630008007a0c */
/* 0x000fda0003f05270 */
/*0490*/ @!P0 BRA 0x4f0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*04a0*/ LEA R4, P0, R9, c[0x0][0x170], 0x2 ; /* 0x00005c0009047a11 */
/* 0x000fc800078010ff */
/*04b0*/ LEA.HI.X R5, R9, c[0x0][0x174], R10, 0x2, P0 ; /* 0x00005d0009057a11 */
/* 0x000fca00000f140a */
/*04c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*04d0*/ IMAD.IADD R3, R4, 0x1, R3 ; /* 0x0000000104037824 */
/* 0x004fe200078e0203 */
/*04e0*/ BRA 0x530 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe40007ffe0ff */
/*0500*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe20007ffe0ff */
/*0510*/ BRA 0x530 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fe40007ffe0ff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.AND P0, PT, R3.reuse, R0, PT ; /* 0x000000000300720c */
/* 0x040fe40003f06270 */
/*0550*/ ISETP.LT.AND P1, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fda0003f21270 */
/*0560*/ @!P0 BRA P1, 0x2f0 ; /* 0xfffffd8000008947 */
/* 0x000fea000083ffff */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0580*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0590*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x000e62000000c000 */
/*05a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*05c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*05d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fca00078e00ff */
/*05e0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*05f0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x002fd8000f8e00ff */
/*0600*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400098e */
/* 0x000fe2000c10e186 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14horspool_matchPcS_PiPjiiii
.globl _Z14horspool_matchPcS_PiPjiiii
.p2align 8
.type _Z14horspool_matchPcS_PiPjiiii,@function
_Z14horspool_matchPcS_PiPjiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_24
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x28
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v1, s4
s_add_i32 s5, s3, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, s5, s4, v0
v_add_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_min_i32_e32 v4, s2, v1
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e64 v3, v4
s_cbranch_execz .LBB0_20
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, 0
s_cmp_gt_i32 s3, 0
s_mov_b32 s11, 0
s_cselect_b32 s10, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v4
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_19
.LBB0_4:
v_ashrrev_i32_e32 v1, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v3
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_u16_e32 0x7e, v6
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_17
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_11
v_add_co_u32 v0, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_mov_b32 s14, -1
s_mov_b32 s13, 0
s_mov_b32 s15, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s17, exec_lo, s16
s_or_b32 s13, s17, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_10
.LBB0_8:
s_add_i32 s17, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s19, s17, 31
s_add_u32 s18, s6, s17
s_addc_u32 s19, s7, s19
global_load_u8 v7, v[0:1], off
global_load_u8 v8, v5, s[18:19]
s_or_b32 s16, s16, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v8, v7
v_mov_b32_e32 v7, s15
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_7
s_add_i32 s15, s15, 1
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s3, s15
v_add_co_u32 v0, vcc_lo, v0, -1
s_cselect_b32 s18, -1, 0
v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
v_mov_b32_e32 v7, s3
s_and_not1_b32 s16, s16, exec_lo
s_and_b32 s18, s18, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s16, s16, s18
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_branch .LBB0_12
.LBB0_11:
v_mov_b32_e32 v7, 0
.LBB0_12:
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 s3, v7
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_14
v_and_b32_e32 v0, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v0, v0, s[8:9]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v0, v3
.LBB0_14:
s_and_not1_saveexec_b32 s13, s13
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v3
s_or_b32 exec_lo, exec_lo, s13
.LBB0_17:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v3
s_branch .LBB0_3
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
.LBB0_21:
s_ctz_i32_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v2, s4
s_lshl_b32 s4, 1, s4
s_and_not1_b32 s3, s3, s4
s_delay_alu instid0(VALU_DEP_1)
s_add_i32 s2, s2, s5
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_21
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_24
s_load_b64 s[0:1], s[0:1], 0x18
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14horspool_matchPcS_PiPjiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14horspool_matchPcS_PiPjiiii, .Lfunc_end0-_Z14horspool_matchPcS_PiPjiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14horspool_matchPcS_PiPjiiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z14horspool_matchPcS_PiPjiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b667c_00000000-6_horspool_match.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii
.type _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii, @function
_Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14horspool_matchPcS_PiPjiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii, .-_Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii
.globl _Z14horspool_matchPcS_PiPjiiii
.type _Z14horspool_matchPcS_PiPjiiii, @function
_Z14horspool_matchPcS_PiPjiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z14horspool_matchPcS_PiPjiiiiPcS_PiPjiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14horspool_matchPcS_PiPjiiii, .-_Z14horspool_matchPcS_PiPjiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14horspool_matchPcS_PiPjiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14horspool_matchPcS_PiPjiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "horspool_match.hip"
.globl _Z29__device_stub__horspool_matchPcS_PiPjiiii # -- Begin function _Z29__device_stub__horspool_matchPcS_PiPjiiii
.p2align 4, 0x90
.type _Z29__device_stub__horspool_matchPcS_PiPjiiii,@function
_Z29__device_stub__horspool_matchPcS_PiPjiiii: # @_Z29__device_stub__horspool_matchPcS_PiPjiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14horspool_matchPcS_PiPjiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__horspool_matchPcS_PiPjiiii, .Lfunc_end0-_Z29__device_stub__horspool_matchPcS_PiPjiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14horspool_matchPcS_PiPjiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14horspool_matchPcS_PiPjiiii,@object # @_Z14horspool_matchPcS_PiPjiiii
.section .rodata,"a",@progbits
.globl _Z14horspool_matchPcS_PiPjiiii
.p2align 3, 0x0
_Z14horspool_matchPcS_PiPjiiii:
.quad _Z29__device_stub__horspool_matchPcS_PiPjiiii
.size _Z14horspool_matchPcS_PiPjiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14horspool_matchPcS_PiPjiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__horspool_matchPcS_PiPjiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14horspool_matchPcS_PiPjiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
using namespace std;
#define THREADS_PER_BLOCK 256
__global__ void mean_per_block(int *a_d,int *b_d,int n){
int block = blockDim.x*blockIdx.x;
int mean=0,sum=0;
for(int i=block;i<min(block+blockDim.x,n);i++){
sum+=a_d[i];
}
b_d[blockIdx.x]=sum/blockDim.x;
}
int main() {
int n;
cout<<"Enter the no of elements";
cin>>n;
int *arr = new int[n];
for(int i=0;i<n;i++){
arr[i]=i+1;
}
int no_of_blocks = (n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
int size = n*sizeof(int);
int *arr_d,*b_d;
cudaMalloc(&arr_d,size);
cudaMalloc(&b_d,no_of_blocks*sizeof(int));
cudaMemcpy(arr_d,arr,size,cudaMemcpyHostToDevice);
while(n>1){
mean_per_block<<<no_of_blocks,THREADS_PER_BLOCK>>>(arr_d,b_d,n);
n=(n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
cudaMemcpy(arr_d,b_d,no_of_blocks*sizeof(int),cudaMemcpyDeviceToDevice);
}
int ans;
cudaMemcpy(&ans,arr_d,sizeof(int),cudaMemcpyDeviceToHost);
cout<<ans;
} | code for sm_80
Function : _Z14mean_per_blockPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD R6, R0, c[0x0][0x0], RZ ; /* 0x0000000000067a24 */
/* 0x001fca00078e02ff */
/*0050*/ IADD3 R2, R6, c[0x0][0x0], RZ ; /* 0x0000000006027a10 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX.U32 R3, R2, c[0x0][0x170], PT ; /* 0x00005c0002037a17 */
/* 0x000fc80003800000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0x740 ; /* 0x000006b000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.IADD R3, R3, 0x1, -R6.reuse ; /* 0x0000000103037824 */
/* 0x100fe400078e0a06 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R5, -R5, -0x2, -R6 ; /* 0xfffffffe05057810 */
/* 0x000fc80007ffe906 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*00e0*/ LOP3.LUT R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fd600078ec0ff */
/*00f0*/ @!P0 BRA 0x670 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0100*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fe200078e33ff */
/*0120*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0150*/ IMNMX.U32 R2, R2, UR4, !PT ; /* 0x0000000402027c17 */
/* 0x000fc8000f800000 */
/*0160*/ IADD3 R7, R5, R2, R6 ; /* 0x0000000205077210 */
/* 0x000fe20007ffe006 */
/*0170*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0203 */
/*0180*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fc80007f3e0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f04270 */
/*01b0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fd800008e0603 */
/*01c0*/ @!P0 BRA 0x590 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0200*/ @!P1 BRA 0x410 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff806020d7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc06020c7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R15, [R2.64] ; /* 0x00000006020f7981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000406020e7981 */
/* 0x0000e8000c1e1900 */
/*0260*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080602117981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0602107981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100602137981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140602127981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R21, [R2.64+0x18] ; /* 0x0000180602157981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0602147981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R23, [R2.64+0x20] ; /* 0x0000200602177981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240602167981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002806020b7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c06020a7981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300602097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340602087981 */
/* 0x000162000c1e1900 */
/*0320*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0330*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0340*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0350*/ IADD3 R12, R12, R13, R4 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe004 */
/*0360*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0370*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0380*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0390*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*03a0*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03b0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03c0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*03d0*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03e0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03f0*/ IADD3 R4, R8, R9, R10 ; /* 0x0000000908047210 */
/* 0x000fe20007ffe00a */
/*0400*/ @P1 BRA 0x220 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0410*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0430*/ @!P1 BRA 0x570 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0440*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80602097981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0602087981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x0000e8000c1e1900 */
/*0480*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000806020d7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c06020c7981 */
/* 0x000128000c1e1900 */
/*04a0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001006020f7981 */
/* 0x000168000c1e1900 */
/*04b0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001406020e7981 */
/* 0x000162000c1e1900 */
/*04c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R8, R8, R9, R4 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe004 */
/*0500*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*0510*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0520*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0530*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0550*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0560*/ IADD3 R4, R14, R15, R8 ; /* 0x0000000f0e047210 */
/* 0x020fe40007ffe008 */
/*0570*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0580*/ @!P0 BRA 0x670 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80602097981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0602087981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x0000e2000c1e1900 */
/*05d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*0600*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0620*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0630*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0640*/ IADD3 R4, R8, R9, R4 ; /* 0x0000000908047210 */
/* 0x004fc80007ffe004 */
/*0650*/ IADD3 R4, R10, R11, R4 ; /* 0x0000000b0a047210 */
/* 0x008fe20007ffe004 */
/*0660*/ @P0 BRA 0x590 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0680*/ @!P0 BRA 0x740 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*06c0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0006 */
/*06d0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0700*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f05270 */
/*0710*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0720*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x004fd000078e0204 */
/*0730*/ @P0 BRA 0x6b0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0740*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0750*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fce0003f45070 */
/*0760*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0770*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*0780*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0790*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*07a0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*07b0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*07c0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*07d0*/ IMAD.HI.U32 R7, R3, R4, RZ ; /* 0x0000000403077227 */
/* 0x000fc800078e00ff */
/*07e0*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*07f0*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x000fe400078e0204 */
/*0800*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0810*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fe20003f06070 */
/*0820*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd800078e0003 */
/*0830*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0840*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0860*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0870*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff07aa12 */
/* 0x000fca00078e33ff */
/*0880*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
using namespace std;
#define THREADS_PER_BLOCK 256
__global__ void mean_per_block(int *a_d,int *b_d,int n){
int block = blockDim.x*blockIdx.x;
int mean=0,sum=0;
for(int i=block;i<min(block+blockDim.x,n);i++){
sum+=a_d[i];
}
b_d[blockIdx.x]=sum/blockDim.x;
}
int main() {
int n;
cout<<"Enter the no of elements";
cin>>n;
int *arr = new int[n];
for(int i=0;i<n;i++){
arr[i]=i+1;
}
int no_of_blocks = (n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
int size = n*sizeof(int);
int *arr_d,*b_d;
cudaMalloc(&arr_d,size);
cudaMalloc(&b_d,no_of_blocks*sizeof(int));
cudaMemcpy(arr_d,arr,size,cudaMemcpyHostToDevice);
while(n>1){
mean_per_block<<<no_of_blocks,THREADS_PER_BLOCK>>>(arr_d,b_d,n);
n=(n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
cudaMemcpy(arr_d,b_d,no_of_blocks*sizeof(int),cudaMemcpyDeviceToDevice);
}
int ans;
cudaMemcpy(&ans,arr_d,sizeof(int),cudaMemcpyDeviceToHost);
cout<<ans;
} | .file "tmpxft_00186aa5_00000000-6_3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
.type _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i, @function
_Z37__device_stub__Z14mean_per_blockPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14mean_per_blockPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i, .-_Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
.globl _Z14mean_per_blockPiS_i
.type _Z14mean_per_blockPiS_i, @function
_Z14mean_per_blockPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14mean_per_blockPiS_i, .-_Z14mean_per_blockPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the no of elements"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movslq 12(%rsp), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L12
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
movl 12(%rsp), %esi
movslq %esi, %rcx
movl $1, %eax
testl %esi, %esi
jle .L14
.L16:
movl %eax, -4(%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L16
.L14:
leal 510(%rsi), %ebx
movl %esi, %eax
addl $255, %eax
cmovns %eax, %ebx
sarl $8, %ebx
sall $2, %esi
movslq %esi, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq %ebx, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 12(%rsp)
jg .L19
.L17:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L18:
movl 12(%rsp), %edx
leal 510(%rdx), %eax
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 12(%rsp)
movl $3, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 12(%rsp)
jle .L17
.L19:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14mean_per_blockPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mean_per_blockPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
using namespace std;
#define THREADS_PER_BLOCK 256
__global__ void mean_per_block(int *a_d,int *b_d,int n){
int block = blockDim.x*blockIdx.x;
int mean=0,sum=0;
for(int i=block;i<min(block+blockDim.x,n);i++){
sum+=a_d[i];
}
b_d[blockIdx.x]=sum/blockDim.x;
}
int main() {
int n;
cout<<"Enter the no of elements";
cin>>n;
int *arr = new int[n];
for(int i=0;i<n;i++){
arr[i]=i+1;
}
int no_of_blocks = (n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
int size = n*sizeof(int);
int *arr_d,*b_d;
cudaMalloc(&arr_d,size);
cudaMalloc(&b_d,no_of_blocks*sizeof(int));
cudaMemcpy(arr_d,arr,size,cudaMemcpyHostToDevice);
while(n>1){
mean_per_block<<<no_of_blocks,THREADS_PER_BLOCK>>>(arr_d,b_d,n);
n=(n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
cudaMemcpy(arr_d,b_d,no_of_blocks*sizeof(int),cudaMemcpyDeviceToDevice);
}
int ans;
cudaMemcpy(&ans,arr_d,sizeof(int),cudaMemcpyDeviceToHost);
cout<<ans;
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
#define THREADS_PER_BLOCK 256
__global__ void mean_per_block(int *a_d,int *b_d,int n){
int block = blockDim.x*blockIdx.x;
int mean=0,sum=0;
for(int i=block;i<min(block+blockDim.x,n);i++){
sum+=a_d[i];
}
b_d[blockIdx.x]=sum/blockDim.x;
}
int main() {
int n;
cout<<"Enter the no of elements";
cin>>n;
int *arr = new int[n];
for(int i=0;i<n;i++){
arr[i]=i+1;
}
int no_of_blocks = (n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
int size = n*sizeof(int);
int *arr_d,*b_d;
hipMalloc(&arr_d,size);
hipMalloc(&b_d,no_of_blocks*sizeof(int));
hipMemcpy(arr_d,arr,size,hipMemcpyHostToDevice);
while(n>1){
mean_per_block<<<no_of_blocks,THREADS_PER_BLOCK>>>(arr_d,b_d,n);
n=(n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
hipMemcpy(arr_d,b_d,no_of_blocks*sizeof(int),hipMemcpyDeviceToDevice);
}
int ans;
hipMemcpy(&ans,arr_d,sizeof(int),hipMemcpyDeviceToHost);
cout<<ans;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
#define THREADS_PER_BLOCK 256
__global__ void mean_per_block(int *a_d,int *b_d,int n){
int block = blockDim.x*blockIdx.x;
int mean=0,sum=0;
for(int i=block;i<min(block+blockDim.x,n);i++){
sum+=a_d[i];
}
b_d[blockIdx.x]=sum/blockDim.x;
}
int main() {
int n;
cout<<"Enter the no of elements";
cin>>n;
int *arr = new int[n];
for(int i=0;i<n;i++){
arr[i]=i+1;
}
int no_of_blocks = (n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
int size = n*sizeof(int);
int *arr_d,*b_d;
hipMalloc(&arr_d,size);
hipMalloc(&b_d,no_of_blocks*sizeof(int));
hipMemcpy(arr_d,arr,size,hipMemcpyHostToDevice);
while(n>1){
mean_per_block<<<no_of_blocks,THREADS_PER_BLOCK>>>(arr_d,b_d,n);
n=(n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
hipMemcpy(arr_d,b_d,no_of_blocks*sizeof(int),hipMemcpyDeviceToDevice);
}
int ans;
hipMemcpy(&ans,arr_d,sizeof(int),hipMemcpyDeviceToHost);
cout<<ans;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14mean_per_blockPiS_i
.globl _Z14mean_per_blockPiS_i
.p2align 8
.type _Z14mean_per_blockPiS_i,@function
_Z14mean_per_blockPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cvt_f64_i32_e32 v[0:1], s4
s_mul_i32 s6, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s6, s3
v_cvt_f64_u32_e32 v[2:3], s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_min_f64 v[0:1], v[2:3], v[0:1]
v_cvt_f64_i32_e32 v[2:3], s6
v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
s_cbranch_vccnz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_add_i32 s6, s6, 1
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f64_i32_e32 v[2:3], s6
s_load_b32 s8, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s8, s7
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_i32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
s_cbranch_vccz .LBB0_2
.LBB0_3:
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v0
v_mov_b32_e32 v0, 0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_mov_b32 s3, 0
s_cselect_b32 s4, s6, s4
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, s4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14mean_per_blockPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14mean_per_blockPiS_i, .Lfunc_end0-_Z14mean_per_blockPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14mean_per_blockPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14mean_per_blockPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
#define THREADS_PER_BLOCK 256
__global__ void mean_per_block(int *a_d,int *b_d,int n){
int block = blockDim.x*blockIdx.x;
int mean=0,sum=0;
for(int i=block;i<min(block+blockDim.x,n);i++){
sum+=a_d[i];
}
b_d[blockIdx.x]=sum/blockDim.x;
}
int main() {
int n;
cout<<"Enter the no of elements";
cin>>n;
int *arr = new int[n];
for(int i=0;i<n;i++){
arr[i]=i+1;
}
int no_of_blocks = (n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
int size = n*sizeof(int);
int *arr_d,*b_d;
hipMalloc(&arr_d,size);
hipMalloc(&b_d,no_of_blocks*sizeof(int));
hipMemcpy(arr_d,arr,size,hipMemcpyHostToDevice);
while(n>1){
mean_per_block<<<no_of_blocks,THREADS_PER_BLOCK>>>(arr_d,b_d,n);
n=(n+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK;
hipMemcpy(arr_d,b_d,no_of_blocks*sizeof(int),hipMemcpyDeviceToDevice);
}
int ans;
hipMemcpy(&ans,arr_d,sizeof(int),hipMemcpyDeviceToHost);
cout<<ans;
} | .text
.file "3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__mean_per_blockPiS_i # -- Begin function _Z29__device_stub__mean_per_blockPiS_i
.p2align 4, 0x90
.type _Z29__device_stub__mean_per_blockPiS_i,@function
_Z29__device_stub__mean_per_blockPiS_i: # @_Z29__device_stub__mean_per_blockPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14mean_per_blockPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__mean_per_blockPiS_i, .Lfunc_end0-_Z29__device_stub__mean_per_blockPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 4(%rsp), %rbx
leaq (,%rbx,4), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r14
movl %ebx, %eax
testq %rbx, %rbx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%r14,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
leal 255(%rax), %ecx
leal 510(%rax), %ebp
testl %ecx, %ecx
cmovnsl %ecx, %ebp
sarl $8, %ebp
shll $2, %eax
movslq %eax, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq %ebp, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $2, 4(%rsp)
jl .LBB1_8
# %bb.4: # %.lr.ph19
movabsq $4294967296, %r14 # imm = 0x100000000
movl %ebp, %r15d
orq %r14, %r15
addq $256, %r14 # imm = 0x100
leaq 64(%rsp), %rbp
leaq 56(%rsp), %r12
leaq 32(%rsp), %r13
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movl 4(%rsp), %eax
leal 255(%rax), %ecx
addl $510, %eax # imm = 0x1FE
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $8, %eax
movl %eax, 4(%rsp)
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, 4(%rsp)
jle .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 20(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z14mean_per_blockPiS_i, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge20
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mean_per_blockPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14mean_per_blockPiS_i,@object # @_Z14mean_per_blockPiS_i
.section .rodata,"a",@progbits
.globl _Z14mean_per_blockPiS_i
.p2align 3, 0x0
_Z14mean_per_blockPiS_i:
.quad _Z29__device_stub__mean_per_blockPiS_i
.size _Z14mean_per_blockPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the no of elements"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14mean_per_blockPiS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mean_per_blockPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14mean_per_blockPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14mean_per_blockPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD R6, R0, c[0x0][0x0], RZ ; /* 0x0000000000067a24 */
/* 0x001fca00078e02ff */
/*0050*/ IADD3 R2, R6, c[0x0][0x0], RZ ; /* 0x0000000006027a10 */
/* 0x000fc80007ffe0ff */
/*0060*/ IMNMX.U32 R3, R2, c[0x0][0x170], PT ; /* 0x00005c0002037a17 */
/* 0x000fc80003800000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 BRA 0x740 ; /* 0x000006b000000947 */
/* 0x000fea0003800000 */
/*0090*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe200078e33ff */
/*00a0*/ IMAD.IADD R3, R3, 0x1, -R6.reuse ; /* 0x0000000103037824 */
/* 0x100fe400078e0a06 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R5, -R5, -0x2, -R6 ; /* 0xfffffffe05057810 */
/* 0x000fc80007ffe906 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*00e0*/ LOP3.LUT R5, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303057812 */
/* 0x000fd600078ec0ff */
/*00f0*/ @!P0 BRA 0x670 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0100*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fe200078e33ff */
/*0120*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0150*/ IMNMX.U32 R2, R2, UR4, !PT ; /* 0x0000000402027c17 */
/* 0x000fc8000f800000 */
/*0160*/ IADD3 R7, R5, R2, R6 ; /* 0x0000000205077210 */
/* 0x000fe20007ffe006 */
/*0170*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0203 */
/*0180*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*0190*/ IADD3 R2, P1, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fc80007f3e0ff */
/*01a0*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe20003f04270 */
/*01b0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fd800008e0603 */
/*01c0*/ @!P0 BRA 0x590 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0200*/ @!P1 BRA 0x410 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ LDG.E R13, [R2.64+-0x8] ; /* 0xfffff806020d7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R12, [R2.64+-0x4] ; /* 0xfffffc06020c7981 */
/* 0x000ea8000c1e1900 */
/*0240*/ LDG.E R15, [R2.64] ; /* 0x00000006020f7981 */
/* 0x0000e8000c1e1900 */
/*0250*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000406020e7981 */
/* 0x0000e8000c1e1900 */
/*0260*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080602117981 */
/* 0x000128000c1e1900 */
/*0270*/ LDG.E R16, [R2.64+0xc] ; /* 0x00000c0602107981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100602137981 */
/* 0x000168000c1e1900 */
/*0290*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140602127981 */
/* 0x000168000c1e1900 */
/*02a0*/ LDG.E R21, [R2.64+0x18] ; /* 0x0000180602157981 */
/* 0x000168000c1e1900 */
/*02b0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0602147981 */
/* 0x000168000c1e1900 */
/*02c0*/ LDG.E R23, [R2.64+0x20] ; /* 0x0000200602177981 */
/* 0x000168000c1e1900 */
/*02d0*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240602167981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R11, [R2.64+0x28] ; /* 0x00002806020b7981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c06020a7981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300602097981 */
/* 0x000168000c1e1900 */
/*0310*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340602087981 */
/* 0x000162000c1e1900 */
/*0320*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fc40007ffe0ff */
/*0330*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*0340*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fe40003f24270 */
/*0350*/ IADD3 R12, R12, R13, R4 ; /* 0x0000000d0c0c7210 */
/* 0x004fe40007ffe004 */
/*0360*/ IADD3 R13, P2, R2, 0x40, RZ ; /* 0x00000040020d7810 */
/* 0x000fca0007f5e0ff */
/*0370*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*0380*/ IADD3 R12, R14, R15, R12 ; /* 0x0000000f0e0c7210 */
/* 0x008fe20007ffe00c */
/*0390*/ IMAD.MOV.U32 R2, RZ, RZ, R13 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000d */
/*03a0*/ IADD3 R12, R16, R17, R12 ; /* 0x00000011100c7210 */
/* 0x010fc80007ffe00c */
/*03b0*/ IADD3 R12, R18, R19, R12 ; /* 0x00000013120c7210 */
/* 0x020fc80007ffe00c */
/*03c0*/ IADD3 R12, R20, R21, R12 ; /* 0x00000015140c7210 */
/* 0x000fc80007ffe00c */
/*03d0*/ IADD3 R12, R22, R23, R12 ; /* 0x00000017160c7210 */
/* 0x000fc80007ffe00c */
/*03e0*/ IADD3 R10, R10, R11, R12 ; /* 0x0000000b0a0a7210 */
/* 0x000fc80007ffe00c */
/*03f0*/ IADD3 R4, R8, R9, R10 ; /* 0x0000000908047210 */
/* 0x000fe20007ffe00a */
/*0400*/ @P1 BRA 0x220 ; /* 0xfffffe1000001947 */
/* 0x000fea000383ffff */
/*0410*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0430*/ @!P1 BRA 0x570 ; /* 0x0000013000009947 */
/* 0x000fea0003800000 */
/*0440*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80602097981 */
/* 0x000ea8000c1e1900 */
/*0450*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0602087981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x0000e8000c1e1900 */
/*0470*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x0000e8000c1e1900 */
/*0480*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000806020d7981 */
/* 0x000128000c1e1900 */
/*0490*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c06020c7981 */
/* 0x000128000c1e1900 */
/*04a0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001006020f7981 */
/* 0x000168000c1e1900 */
/*04b0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001406020e7981 */
/* 0x000162000c1e1900 */
/*04c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*04d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R8, R8, R9, R4 ; /* 0x0000000908087210 */
/* 0x004fe40007ffe004 */
/*0500*/ IADD3 R9, P1, R2, 0x20, RZ ; /* 0x0000002002097810 */
/* 0x000fca0007f3e0ff */
/*0510*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0520*/ IADD3 R8, R10, R11, R8 ; /* 0x0000000b0a087210 */
/* 0x008fe20007ffe008 */
/*0530*/ IMAD.X R10, RZ, RZ, R3, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc800008e0603 */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0550*/ IADD3 R8, R12, R13, R8 ; /* 0x0000000d0c087210 */
/* 0x010fc80007ffe008 */
/*0560*/ IADD3 R4, R14, R15, R8 ; /* 0x0000000f0e047210 */
/* 0x020fe40007ffe008 */
/*0570*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0580*/ @!P0 BRA 0x670 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0590*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80602097981 */
/* 0x0000a8000c1e1900 */
/*05a0*/ LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0602087981 */
/* 0x0000a8000c1e1900 */
/*05b0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x0000e8000c1e1900 */
/*05c0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x0000e2000c1e1900 */
/*05d0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc40007ffe0ff */
/*05e0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f05270 */
/*0600*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0603 */
/*0620*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000c */
/*0630*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0640*/ IADD3 R4, R8, R9, R4 ; /* 0x0000000908047210 */
/* 0x004fc80007ffe004 */
/*0650*/ IADD3 R4, R10, R11, R4 ; /* 0x0000000b0a047210 */
/* 0x008fe20007ffe004 */
/*0660*/ @P0 BRA 0x590 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0680*/ @!P0 BRA 0x740 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*06a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*06b0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*06c0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fca00078e0006 */
/*06d0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f3e0ff */
/*0700*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f05270 */
/*0710*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0607 */
/*0720*/ IMAD.IADD R4, R3, 0x1, R4 ; /* 0x0000000103047824 */
/* 0x004fd000078e0204 */
/*0730*/ @P0 BRA 0x6b0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0740*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0750*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fce0003f45070 */
/*0760*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*0770*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x001fcc0007ffe0ff */
/*0780*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0790*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*07a0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*07b0*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*07c0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*07d0*/ IMAD.HI.U32 R7, R3, R4, RZ ; /* 0x0000000403077227 */
/* 0x000fc800078e00ff */
/*07e0*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*07f0*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x000fe400078e0204 */
/*0800*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0810*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fe20003f06070 */
/*0820*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd800078e0003 */
/*0830*/ @P0 IADD3 R4, R4, -c[0x0][0x0], RZ ; /* 0x8000000004040a10 */
/* 0x000fe40007ffe0ff */
/*0840*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f26070 */
/*0860*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0870*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff07aa12 */
/* 0x000fca00078e33ff */
/*0880*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14mean_per_blockPiS_i
.globl _Z14mean_per_blockPiS_i
.p2align 8
.type _Z14mean_per_blockPiS_i,@function
_Z14mean_per_blockPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
v_cvt_f64_i32_e32 v[0:1], s4
s_mul_i32 s6, s15, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s6, s3
v_cvt_f64_u32_e32 v[2:3], s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_min_f64 v[0:1], v[2:3], v[0:1]
v_cvt_f64_i32_e32 v[2:3], s6
v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
s_cbranch_vccnz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_add_i32 s6, s6, 1
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f64_i32_e32 v[2:3], s6
s_load_b32 s8, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s7, s8, s7
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_add_i32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ngt_f64_e32 vcc_lo, v[0:1], v[2:3]
s_cbranch_vccz .LBB0_2
.LBB0_3:
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s5, 0, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s4, v0
v_mov_b32_e32 v0, 0
s_mul_i32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_add_i32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s7, s4
s_mul_i32 s5, s4, s3
s_add_i32 s6, s4, 1
s_sub_i32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s7, s5, s3
s_cmp_ge_u32 s5, s3
s_cselect_b32 s4, s6, s4
s_cselect_b32 s5, s7, s5
s_add_i32 s6, s4, 1
s_cmp_ge_u32 s5, s3
s_mov_b32 s3, 0
s_cselect_b32 s4, s6, s4
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, s4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14mean_per_blockPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14mean_per_blockPiS_i, .Lfunc_end0-_Z14mean_per_blockPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14mean_per_blockPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14mean_per_blockPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00186aa5_00000000-6_3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
.type _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i, @function
_Z37__device_stub__Z14mean_per_blockPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14mean_per_blockPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i, .-_Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
.globl _Z14mean_per_blockPiS_i
.type _Z14mean_per_blockPiS_i, @function
_Z14mean_per_blockPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z14mean_per_blockPiS_i, .-_Z14mean_per_blockPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the no of elements"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 12(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movslq 12(%rsp), %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L12
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
movl 12(%rsp), %esi
movslq %esi, %rcx
movl $1, %eax
testl %esi, %esi
jle .L14
.L16:
movl %eax, -4(%r12,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rcx
jne .L16
.L14:
leal 510(%rsi), %ebx
movl %esi, %eax
addl $255, %eax
cmovns %eax, %ebx
sarl $8, %ebx
sall $2, %esi
movslq %esi, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq %ebx, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 12(%rsp)
jg .L19
.L17:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L15
call __stack_chk_fail@PLT
.L15:
call __cxa_throw_bad_array_new_length@PLT
.L18:
movl 12(%rsp), %edx
leal 510(%rdx), %eax
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 12(%rsp)
movl $3, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, 12(%rsp)
jle .L17
.L19:
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl 12(%rsp), %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z37__device_stub__Z14mean_per_blockPiS_iPiS_i
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14mean_per_blockPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mean_per_blockPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__mean_per_blockPiS_i # -- Begin function _Z29__device_stub__mean_per_blockPiS_i
.p2align 4, 0x90
.type _Z29__device_stub__mean_per_blockPiS_i,@function
_Z29__device_stub__mean_per_blockPiS_i: # @_Z29__device_stub__mean_per_blockPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14mean_per_blockPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__mean_per_blockPiS_i, .Lfunc_end0-_Z29__device_stub__mean_per_blockPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 4(%rsp), %rbx
leaq (,%rbx,4), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r14
movl %ebx, %eax
testq %rbx, %rbx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%r14,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
leal 255(%rax), %ecx
leal 510(%rax), %ebp
testl %ecx, %ecx
cmovnsl %ecx, %ebp
sarl $8, %ebp
shll $2, %eax
movslq %eax, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movslq %ebp, %rbx
shlq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
cmpl $2, 4(%rsp)
jl .LBB1_8
# %bb.4: # %.lr.ph19
movabsq $4294967296, %r14 # imm = 0x100000000
movl %ebp, %r15d
orq %r14, %r15
addq $256, %r14 # imm = 0x100
leaq 64(%rsp), %rbp
leaq 56(%rsp), %r12
leaq 32(%rsp), %r13
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movl 4(%rsp), %eax
leal 255(%rax), %ecx
addl $510, %eax # imm = 0x1FE
testl %ecx, %ecx
cmovnsl %ecx, %eax
sarl $8, %eax
movl %eax, 4(%rsp)
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq %rbx, %rdx
movl $3, %ecx
callq hipMemcpy
cmpl $1, 4(%rsp)
jle .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 20(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z14mean_per_blockPiS_i, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge20
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mean_per_blockPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14mean_per_blockPiS_i,@object # @_Z14mean_per_blockPiS_i
.section .rodata,"a",@progbits
.globl _Z14mean_per_blockPiS_i
.p2align 3, 0x0
_Z14mean_per_blockPiS_i:
.quad _Z29__device_stub__mean_per_blockPiS_i
.size _Z14mean_per_blockPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the no of elements"
.size .L.str, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14mean_per_blockPiS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mean_per_blockPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14mean_per_blockPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void __radixcounts(float *a, int n, int digit, unsigned int *bi) {
__shared__ unsigned int ic[RNDVALS];
int istart = (int)(((long long)blockIdx.x) * n / gridDim.x);
int iend = (int)(((long long)(blockIdx.x+1)) * n / gridDim.x);
int tid = threadIdx.x;
int bibase = RNDVALS * (blockIdx.x + istart / RBIGBLK);
for (int i = istart; i < iend; i += RBIGBLK) {
__syncthreads();
ic[threadIdx.x] = 0;
__syncthreads();
for (int j = i + tid; j < min(iend, i+tid+RBIGBLK); j += RNTHREADS) {
float v = a[j];
unsigned char *cv = (unsigned char *)&v;
atomicInc(&ic[cv[digit]], 65536*32767);
}
__syncthreads();
bi[bibase + threadIdx.x] = ic[threadIdx.x];
bibase += RNDVALS;
}
} | code for sm_80
Function : _Z13__radixcountsPfiiPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR5 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011405 */
/*0050*/ IMAD.WIDE.U32 R6, R0, c[0x0][0x168], RZ ; /* 0x00005a0000067a25 */
/* 0x001fca00078e00ff */
/*0060*/ IMAD R5, R0, UR5, RZ ; /* 0x0000000500057c24 */
/* 0x000fc8000f8e02ff */
/*0070*/ IMAD.IADD R5, R7, 0x1, R5 ; /* 0x0000000107057824 */
/* 0x000fca00078e0205 */
/*0080*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*0090*/ @!P0 BRA 0x100 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, 0xe0 ; /* 0x000000e000047802 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00d0*/ CALL.REL.NOINC 0xa10 ; /* 0x0000093000007944 */
/* 0x000fea0003c00000 */
/*00e0*/ IMAD.MOV.U32 R20, RZ, RZ, R18 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0012 */
/*00f0*/ BRA 0x220 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0100*/ I2F.U32.RP R4, c[0x0][0xc] ; /* 0x0000030000047b06 */
/* 0x000e220000209000 */
/*0110*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fce0003f45070 */
/*0120*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0170*/ IMAD R5, R5, c[0x0][0xc], RZ ; /* 0x0000030005057a24 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0190*/ IMAD.HI.U32 R20, R3, R6, RZ ; /* 0x0000000603147227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R3, RZ, RZ, -R20 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a14 */
/*01b0*/ IMAD R6, R3, c[0x0][0xc], R6 ; /* 0x0000030003067a24 */
/* 0x000fca00078e0206 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f06070 */
/*01d0*/ @P0 IADD3 R6, R6, -c[0x0][0xc], RZ ; /* 0x8000030006060a10 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @P0 IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114140810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114141810 */
/* 0x000fe40007ffe0ff */
/*0210*/ @!P2 LOP3.LUT R20, RZ, c[0x0][0xc], RZ, 0x33, !PT ; /* 0x00000300ff14aa12 */
/* 0x000fe400078e33ff */
/*0220*/ IADD3 R6, R0, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x000fca0007ffe0ff */
/*0230*/ IMAD R5, R6.reuse, UR5, RZ ; /* 0x0000000506057c24 */
/* 0x040fe4000f8e02ff */
/*0240*/ IMAD.WIDE.U32 R6, R6, c[0x0][0x168], RZ ; /* 0x00005a0006067a25 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.IADD R5, R7, 0x1, R5 ; /* 0x0000000107057824 */
/* 0x000fca00078e0205 */
/*0260*/ ISETP.NE.U32.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05070 */
/*0270*/ @!P0 BRA 0x2d0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0280*/ MOV R4, 0x2c0 ; /* 0x000002c000047802 */
/* 0x000fe20000000f00 */
/*0290*/ ULDC UR6, c[0x0][0xc] ; /* 0x0000030000067ab9 */
/* 0x000fe40000000800 */
/*02a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02b0*/ CALL.REL.NOINC 0xa10 ; /* 0x0000075000007944 */
/* 0x000fea0003c00000 */
/*02c0*/ BRA 0x3f0 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*02d0*/ I2F.U32.RP R4, c[0x0][0xc] ; /* 0x0000030000047b06 */
/* 0x000e220000209000 */
/*02e0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fce0003f45070 */
/*02f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0300*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0310*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0320*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0330*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0340*/ IMAD R5, R5, c[0x0][0xc], RZ ; /* 0x0000030005057a24 */
/* 0x000fc800078e02ff */
/*0350*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fcc00078e0002 */
/*0360*/ IMAD.HI.U32 R18, R5, R6, RZ ; /* 0x0000000605127227 */
/* 0x000fc800078e00ff */
/*0370*/ IMAD.MOV R3, RZ, RZ, -R18 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a12 */
/*0380*/ IMAD R6, R3, c[0x0][0xc], R6 ; /* 0x0000030003067a24 */
/* 0x000fca00078e0206 */
/*0390*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f06070 */
/*03a0*/ @P0 IADD3 R6, R6, -c[0x0][0xc], RZ ; /* 0x8000030006060a10 */
/* 0x000fe40007ffe0ff */
/*03b0*/ @P0 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112120810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0xc], PT ; /* 0x0000030006007a0c */
/* 0x000fda0003f26070 */
/*03d0*/ @P1 IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112121810 */
/* 0x000fe40007ffe0ff */
/*03e0*/ @!P2 LOP3.LUT R18, RZ, c[0x0][0xc], RZ, 0x33, !PT ; /* 0x00000300ff12aa12 */
/* 0x000fc800078e33ff */
/*03f0*/ ISETP.GE.AND P0, PT, R20, R18, PT ; /* 0x000000121400720c */
/* 0x000fda0003f06270 */
/*0400*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0410*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e220000002100 */
/*0420*/ SHF.R.S32.HI R3, RZ, 0x1f, R20 ; /* 0x0000001fff037819 */
/* 0x000fe20000011414 */
/*0430*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0440*/ IADD3 R16, R1, c[0x0][0x16c], RZ ; /* 0x00005b0001107a10 */
/* 0x000fe20007ffe0ff */
/*0450*/ UIADD3 UR5, UP0, UR6, 0x800, URZ ; /* 0x0000080006057890 */
/* 0x000fe2000ff1e03f */
/*0460*/ LEA.HI R3, R3, R20, RZ, 0xc ; /* 0x0000001403037211 */
/* 0x000fe200078f60ff */
/*0470*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0480*/ LOP3.LUT R15, RZ, R18, RZ, 0x33, !PT ; /* 0x00000012ff0f7212 */
/* 0x000fe200078e33ff */
/*0490*/ UIADD3.X UR6, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f067290 */
/* 0x000fe200087fe43f */
/*04a0*/ LEA.HI.SX32 R3, R3, R0, 0x14 ; /* 0x0000000003037211 */
/* 0x000fe200078fa2ff */
/*04b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc80000000a00 */
/*04c0*/ IMAD.SHL.U32 R12, R3, 0x100, RZ ; /* 0x00000100030c7824 */
/* 0x000fe200078e00ff */
/*04d0*/ IADD3 R14, -R20.reuse, -0x2, -R17.reuse ; /* 0xfffffffe140e7810 */
/* 0x141fe40007ffe911 */
/*04e0*/ IADD3 R19, -R20, -0x1001, -R17 ; /* 0xffffefff14137810 */
/* 0x000fe40007ffe911 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0500*/ IMAD.IADD R8, R17, 0x1, R20 ; /* 0x0000000111087824 */
/* 0x000fca00078e0214 */
/*0510*/ IADD3 R13, R8, 0x1000, RZ ; /* 0x00001000080d7810 */
/* 0x000fc80007ffe0ff */
/*0520*/ IMNMX R13, R13, R18, PT ; /* 0x000000120d0d7217 */
/* 0x000fc80003800200 */
/*0530*/ ISETP.GE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fe20003f06270 */
/*0540*/ STS [R17.X4], RZ ; /* 0x000000ff11007388 */
/* 0x0011e80000004800 */
/*0550*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0560*/ @P0 BRA 0x940 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0570*/ IADD3 R0, R19, UR4, RZ ; /* 0x0000000413007c10 */
/* 0x001fe2000fffe0ff */
/*0580*/ BSSY B0, 0x760 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*0590*/ IMNMX R3, R15, R0, !PT ; /* 0x000000000f037217 */
/* 0x000fc80007800200 */
/*05a0*/ IADD3 R7, -R3, UR4, R14 ; /* 0x0000000403077c10 */
/* 0x000fc8000fffe10e */
/*05b0*/ LEA.HI R0, R7, 0x1, RZ, 0x18 ; /* 0x0000000107007811 */
/* 0x000fc800078fc0ff */
/*05c0*/ LOP3.LUT P0, R9, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300097812 */
/* 0x000fe2000780c0ff */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fd800078e0008 */
/*05e0*/ @!P0 BRA 0x750 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0600*/ IMAD.WIDE R4, R8, R4, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0204 */
/*0610*/ LDG.E R2, [R4.64] ; /* 0x0000000804027981 */
/* 0x000ea2000c1e1900 */
/*0620*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe20003f05270 */
/*0630*/ IMAD.MOV.U32 R6, RZ, RZ, 0x7fff0000 ; /* 0x7fff0000ff067424 */
/* 0x000fe400078e00ff */
/*0640*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100800 */
/*0650*/ LDL.U8 R3, [R16] ; /* 0x0000000010037983 */
/* 0x000ea20000100000 */
/*0660*/ IADD3 R0, R8, 0x100, RZ ; /* 0x0000010008007810 */
/* 0x000fc60007ffe0ff */
/*0670*/ ATOMS.INC RZ, [R3.X4], R6 ; /* 0x0000000603ff738c */
/* 0x0041e40001804000 */
/*0680*/ @!P0 BRA 0x750 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R2, [R4.64+0x400] ; /* 0x0004000804027981 */
/* 0x001ea2000c1e1900 */
/*06a0*/ ISETP.NE.AND P0, PT, R9, 0x2, PT ; /* 0x000000020900780c */
/* 0x000fc60003f05270 */
/*06b0*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100800 */
/*06c0*/ LDL.U8 R3, [R16] ; /* 0x0000000010037983 */
/* 0x000ea20000100000 */
/*06d0*/ IADD3 R0, R8, 0x200, RZ ; /* 0x0000020008007810 */
/* 0x000fc60007ffe0ff */
/*06e0*/ ATOMS.INC RZ, [R3.X4], R6 ; /* 0x0000000603ff738c */
/* 0x0041e40001804000 */
/*06f0*/ @!P0 BRA 0x750 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E R2, [R4.64+0x800] ; /* 0x0008000804027981 */
/* 0x001ea8000c1e1900 */
/*0710*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100800 */
/*0720*/ LDL.U8 R3, [R16] ; /* 0x0000000010037983 */
/* 0x000ea20000100000 */
/*0730*/ IADD3 R0, R8, 0x300, RZ ; /* 0x0000030008007810 */
/* 0x000fc60007ffe0ff */
/*0740*/ ATOMS.INC RZ, [R3.X4], R6 ; /* 0x0000000603ff738c */
/* 0x0041e80001804000 */
/*0750*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GE.U32.AND P0, PT, R7, 0x300, PT ; /* 0x000003000700780c */
/* 0x000fda0003f06070 */
/*0770*/ @!P0 BRA 0x940 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x001fe4000f8e00ff */
/*0790*/ IMAD.U32 R3, RZ, RZ, UR6 ; /* 0x00000006ff037e24 */
/* 0x000fc8000f8e00ff */
/*07a0*/ IMAD.WIDE R2, R0, 0x4, R2 ; /* 0x0000000400027825 */
/* 0x000fc800078e0202 */
/*07b0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*07c0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0002 */
/*07d0*/ LDG.E R2, [R10.64+-0x800] ; /* 0xfff800080a027981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R4, [R10.64+-0x400] ; /* 0xfffc00080a047981 */
/* 0x002ee8000c1e1900 */
/*07f0*/ LDG.E R6, [R10.64] ; /* 0x000000080a067981 */
/* 0x000f28000c1e1900 */
/*0800*/ LDG.E R8, [R10.64+0x400] ; /* 0x000400080a087981 */
/* 0x000f68000c1e1900 */
/*0810*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100800 */
/*0820*/ LDL.U8 R3, [R16] ; /* 0x0000000010037983 */
/* 0x000ea80000100000 */
/*0830*/ STL [R1], R4 ; /* 0x0000000401007387 */
/* 0x0083e80000100800 */
/*0840*/ LDL.U8 R5, [R16] ; /* 0x0000000010057983 */
/* 0x000ee80000100000 */
/*0850*/ STL [R1], R6 ; /* 0x0000000601007387 */
/* 0x0103e80000100800 */
/*0860*/ LDL.U8 R7, [R16] ; /* 0x0000000010077983 */
/* 0x000f280000100000 */
/*0870*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0203e80000100800 */
/*0880*/ LDL.U8 R9, [R16] ; /* 0x0000000010097983 */
/* 0x000f620000100000 */
/*0890*/ IADD3 R0, R0, 0x400, RZ ; /* 0x0000040000007810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x7fff0000 ; /* 0x7fff0000ff167424 */
/* 0x000fe200078e00ff */
/*08b0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*08c0*/ IADD3 R2, P1, R10, 0x1000, RZ ; /* 0x000010000a027810 */
/* 0x001fc40007f3e0ff */
/*08d0*/ ISETP.GE.AND P0, PT, R0, R13, PT ; /* 0x0000000d0000720c */
/* 0x000fc60003f06270 */
/*08e0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*08f0*/ ATOMS.INC RZ, [R3.X4], R22 ; /* 0x0000001603ff738c */
/* 0x0043e80001804000 */
/*0900*/ ATOMS.INC RZ, [R5.X4], R22 ; /* 0x0000001605ff738c */
/* 0x0083e80001804000 */
/*0910*/ ATOMS.INC RZ, [R7.X4], R22 ; /* 0x0000001607ff738c */
/* 0x0103e80001804000 */
/*0920*/ ATOMS.INC RZ, [R9.X4], R22 ; /* 0x0000001609ff738c */
/* 0x0203e20001804000 */
/*0930*/ @!P0 BRA 0x7c0 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0940*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe40003800000 */
/*0950*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0960*/ IMAD.IADD R2, R17, 0x1, R12 ; /* 0x0000000111027824 */
/* 0x000fe200078e020c */
/*0970*/ IADD3 R20, R20, 0x1000, RZ ; /* 0x0000100014147810 */
/* 0x000fe20007ffe0ff */
/*0980*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x002fe200078e00ff */
/*0990*/ UIADD3 UR4, UR4, -0x1000, URZ ; /* 0xfffff00004047890 */
/* 0x000fe2000fffe03f */
/*09a0*/ IADD3 R12, R12, 0x100, RZ ; /* 0x000001000c0c7810 */
/* 0x000fc40007ffe0ff */
/*09b0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0003 */
/*09c0*/ ISETP.GE.AND P0, PT, R20, R18, PT ; /* 0x000000121400720c */
/* 0x000fe20003f06270 */
/*09d0*/ LDS R5, [R17.X4] ; /* 0x0000000011057984 */
/* 0x000e280000004800 */
/*09e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011f0000c101908 */
/*09f0*/ @!P0 BRA 0x4f0 ; /* 0xfffffaf000008947 */
/* 0x000fea000383ffff */
/*0a00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a10*/ IADD3 R2, P1, RZ, -UR6, RZ ; /* 0x80000006ff027c10 */
/* 0x000fe4000ff3e0ff */
/*0a20*/ ISETP.LE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc4000bf03270 */
/*0a30*/ ISETP.GE.AND P3, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f66270 */
/*0a40*/ IMAD.X R3, RZ, RZ, ~UR4, P1 ; /* 0x80000004ff037e24 */
/* 0x000fe200088e06ff */
/*0a50*/ SEL R2, R2, UR6, !P0 ; /* 0x0000000602027c07 */
/* 0x000fc8000c000000 */
/*0a60*/ SEL R3, R3, UR4, !P0 ; /* 0x0000000403037c07 */
/* 0x000fc8000c000000 */
/*0a70*/ I2F.U64.RP R7, R2 ; /* 0x0000000200077312 */
/* 0x000e300000309000 */
/*0a80*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0a90*/ IADD3 R8, R7, 0x1ffffffe, RZ ; /* 0x1ffffffe07087810 */
/* 0x001fcc0007ffe0ff */
/*0aa0*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*0ab0*/ IMAD.WIDE.U32 R10, R8, R2, RZ ; /* 0x00000002080a7225 */
/* 0x001fc800078e00ff */
/*0ac0*/ IMAD R11, R8, R3, R11 ; /* 0x00000003080b7224 */
/* 0x000fe200078e020b */
/*0ad0*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*0ae0*/ IMAD R11, R9, R2, R11 ; /* 0x00000002090b7224 */
/* 0x000fe400078e020b */
/*0af0*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc800078e00ff */
/*0b00*/ IMAD.X R15, RZ, RZ, ~R11, P0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400000e0e0b */
/*0b10*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0008 */
/*0b20*/ IMAD R17, R9, R15.reuse, RZ ; /* 0x0000000f09117224 */
/* 0x080fe400078e02ff */
/*0b30*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0b40*/ IMAD.HI.U32 R7, R9, R15, RZ ; /* 0x0000000f09077227 */
/* 0x000fc800078e00ff */
/*0b50*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fc8000782000a */
/*0b60*/ IMAD.X R7, R7, 0x1, R9, P0 ; /* 0x0000000107077824 */
/* 0x000fe200000e0609 */
/*0b70*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fc80007f5e0ff */
/*0b80*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*0b90*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD R9, R11, R3, R9 ; /* 0x000000030b097224 */
/* 0x000fe200078e0209 */
/*0bb0*/ IADD3 R13, P0, RZ, -R8, RZ ; /* 0x80000008ff0d7210 */
/* 0x000fc60007f1e0ff */
/*0bc0*/ IMAD R9, R7, R2, R9 ; /* 0x0000000207097224 */
/* 0x000fe400078e0209 */
/*0bd0*/ IMAD.HI.U32 R10, R11, R13, RZ ; /* 0x0000000d0b0a7227 */
/* 0x000fc800078e00ff */
/*0be0*/ IMAD.X R8, RZ, RZ, ~R9, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e09 */
/*0bf0*/ IADD3 R9, P4, RZ, -R6, RZ ; /* 0x80000006ff097210 */
/* 0x000fc60007f9e0ff */
/*0c00*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fe2000780000a */
/*0c10*/ SEL R6, R9, R6, !P3 ; /* 0x0000000609067207 */
/* 0x000fc60005800000 */
/*0c20*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0c30*/ IMAD.HI.U32 R11, P1, R7, R13, R10 ; /* 0x0000000d070b7227 */
/* 0x000fc8000782000a */
/*0c40*/ IMAD R10, R7.reuse, R8.reuse, RZ ; /* 0x00000008070a7224 */
/* 0x0c0fe400078e02ff */
/*0c50*/ IMAD.HI.U32 R8, R7, R8, RZ ; /* 0x0000000807087227 */
/* 0x000fc600078e00ff */
/*0c60*/ IADD3 R11, P2, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x000fe20007f5e0ff */
/*0c70*/ IMAD.X R10, RZ, RZ, ~R5, P4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400020e0e05 */
/*0c80*/ IMAD.X R7, R8, 0x1, R7, P0 ; /* 0x0000000108077824 */
/* 0x000fe400000e0607 */
/*0c90*/ IMAD.HI.U32 R8, R11, R6, RZ ; /* 0x000000060b087227 */
/* 0x000fe200078e00ff */
/*0ca0*/ SEL R10, R10, R5, !P3 ; /* 0x000000050a0a7207 */
/* 0x000fe40005800000 */
/*0cb0*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe400017e2407 */
/*0cc0*/ LOP3.LUT R5, R5, UR4, RZ, 0x3c, !PT ; /* 0x0000000405057c12 */
/* 0x000fe2000f8e3cff */
/*0cd0*/ IMAD.WIDE.U32 R8, R11, R10, R8 ; /* 0x0000000a0b087225 */
/* 0x000fc800078e0008 */
/*0ce0*/ IMAD R11, R7.reuse, R10, RZ ; /* 0x0000000a070b7224 */
/* 0x040fe400078e02ff */
/*0cf0*/ IMAD.HI.U32 R8, P0, R7, R6, R8 ; /* 0x0000000607087227 */
/* 0x000fc80007800008 */
/*0d00*/ IMAD.HI.U32 R7, R7, R10, RZ ; /* 0x0000000a07077227 */
/* 0x000fe200078e00ff */
/*0d10*/ IADD3 R11, P1, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x000fc60007f3e0ff */
/*0d20*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe400000e0607 */
/*0d30*/ IMAD.WIDE.U32 R8, R11, R2, RZ ; /* 0x000000020b087225 */
/* 0x000fc800078e00ff */
/*0d40*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0d50*/ IADD3 R13, P1, -R8, R6, RZ ; /* 0x00000006080d7210 */
/* 0x000fe20007f3e1ff */
/*0d60*/ IMAD R9, R11.reuse, R3, R9 ; /* 0x000000030b097224 */
/* 0x040fe200078e0209 */
/*0d70*/ IADD3 R6, R11, 0x1, RZ ; /* 0x000000010b067810 */
/* 0x000fe40007ffe0ff */
/*0d80*/ ISETP.GE.U32.AND P0, PT, R13, R2.reuse, PT ; /* 0x000000020d00720c */
/* 0x080fe20003f06070 */
/*0d90*/ IMAD R7, R7, R2, R9 ; /* 0x0000000207077224 */
/* 0x000fc800078e0209 */
/*0da0*/ IMAD.X R15, R10, 0x1, ~R7, P1 ; /* 0x000000010a0f7824 */
/* 0x000fe200008e0e07 */
/*0db0*/ IADD3 R7, P1, R13, -R2, RZ ; /* 0x800000020d077210 */
/* 0x000fc80007f3e0ff */
/*0dc0*/ ISETP.GE.U32.AND.EX P0, PT, R15.reuse, R3, PT, P0 ; /* 0x000000030f00720c */
/* 0x040fe20003f06100 */
/*0dd0*/ IMAD.X R9, R15, 0x1, ~R3, P1 ; /* 0x000000010f097824 */
/* 0x000fe200008e0e03 */
/*0de0*/ ISETP.GE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f26270 */
/*0df0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fe200078e00ff */
/*0e00*/ SEL R7, R7, R13, P0 ; /* 0x0000000d07077207 */
/* 0x000fe40000000000 */
/*0e10*/ SEL R9, R9, R15, P0 ; /* 0x0000000f09097207 */
/* 0x000fe40000000000 */
/*0e20*/ SEL R11, R6, R11, P0 ; /* 0x0000000b060b7207 */
/* 0x000fe40000000000 */
/*0e30*/ ISETP.GE.U32.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fc40003f06070 */
/*0e40*/ IADD3 R18, R11, 0x1, RZ ; /* 0x000000010b127810 */
/* 0x000fe40007ffe0ff */
/*0e50*/ ISETP.GE.U32.AND.EX P0, PT, R9, R3, PT, P0 ; /* 0x000000030900720c */
/* 0x000fc80003f06100 */
/*0e60*/ SEL R18, R18, R11, P0 ; /* 0x0000000b12127207 */
/* 0x000fe40000000000 */
/*0e70*/ ISETP.NE.U32.AND P0, PT, RZ, UR6, PT ; /* 0x00000006ff007c0c */
/* 0x000fc6000bf05070 */
/*0e80*/ IMAD.MOV R3, RZ, RZ, -R18 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a12 */
/*0e90*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc8000bf05300 */
/*0ea0*/ SEL R18, R3, R18, !P1 ; /* 0x0000001203127207 */
/* 0x000fc80004800000 */
/*0eb0*/ SEL R18, R18, 0xffffffff, P0 ; /* 0xffffffff12127807 */
/* 0x000fe20000000000 */
/*0ec0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff13004007950 */
/* 0x000fec0003c3ffff */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void __radixcounts(float *a, int n, int digit, unsigned int *bi) {
__shared__ unsigned int ic[RNDVALS];
int istart = (int)(((long long)blockIdx.x) * n / gridDim.x);
int iend = (int)(((long long)(blockIdx.x+1)) * n / gridDim.x);
int tid = threadIdx.x;
int bibase = RNDVALS * (blockIdx.x + istart / RBIGBLK);
for (int i = istart; i < iend; i += RBIGBLK) {
__syncthreads();
ic[threadIdx.x] = 0;
__syncthreads();
for (int j = i + tid; j < min(iend, i+tid+RBIGBLK); j += RNTHREADS) {
float v = a[j];
unsigned char *cv = (unsigned char *)&v;
atomicInc(&ic[cv[digit]], 65536*32767);
}
__syncthreads();
bi[bibase + threadIdx.x] = ic[threadIdx.x];
bibase += RNDVALS;
}
} | .file "tmpxft_00032007_00000000-6___radixcounts.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj
.type _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj, @function
_Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13__radixcountsPfiiPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj, .-_Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj
.globl _Z13__radixcountsPfiiPj
.type _Z13__radixcountsPfiiPj, @function
_Z13__radixcountsPfiiPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13__radixcountsPfiiPj, .-_Z13__radixcountsPfiiPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13__radixcountsPfiiPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13__radixcountsPfiiPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void __radixcounts(float *a, int n, int digit, unsigned int *bi) {
__shared__ unsigned int ic[RNDVALS];
int istart = (int)(((long long)blockIdx.x) * n / gridDim.x);
int iend = (int)(((long long)(blockIdx.x+1)) * n / gridDim.x);
int tid = threadIdx.x;
int bibase = RNDVALS * (blockIdx.x + istart / RBIGBLK);
for (int i = istart; i < iend; i += RBIGBLK) {
__syncthreads();
ic[threadIdx.x] = 0;
__syncthreads();
for (int j = i + tid; j < min(iend, i+tid+RBIGBLK); j += RNTHREADS) {
float v = a[j];
unsigned char *cv = (unsigned char *)&v;
atomicInc(&ic[cv[digit]], 65536*32767);
}
__syncthreads();
bi[bibase + threadIdx.x] = ic[threadIdx.x];
bibase += RNDVALS;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __radixcounts(float *a, int n, int digit, unsigned int *bi) {
__shared__ unsigned int ic[RNDVALS];
int istart = (int)(((long long)blockIdx.x) * n / gridDim.x);
int iend = (int)(((long long)(blockIdx.x+1)) * n / gridDim.x);
int tid = threadIdx.x;
int bibase = RNDVALS * (blockIdx.x + istart / RBIGBLK);
for (int i = istart; i < iend; i += RBIGBLK) {
__syncthreads();
ic[threadIdx.x] = 0;
__syncthreads();
for (int j = i + tid; j < min(iend, i+tid+RBIGBLK); j += RNTHREADS) {
float v = a[j];
unsigned char *cv = (unsigned char *)&v;
atomicInc(&ic[cv[digit]], 65536*32767);
}
__syncthreads();
bi[bibase + threadIdx.x] = ic[threadIdx.x];
bibase += RNDVALS;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __radixcounts(float *a, int n, int digit, unsigned int *bi) {
__shared__ unsigned int ic[RNDVALS];
int istart = (int)(((long long)blockIdx.x) * n / gridDim.x);
int iend = (int)(((long long)(blockIdx.x+1)) * n / gridDim.x);
int tid = threadIdx.x;
int bibase = RNDVALS * (blockIdx.x + istart / RBIGBLK);
for (int i = istart; i < iend; i += RBIGBLK) {
__syncthreads();
ic[threadIdx.x] = 0;
__syncthreads();
for (int j = i + tid; j < min(iend, i+tid+RBIGBLK); j += RNTHREADS) {
float v = a[j];
unsigned char *cv = (unsigned char *)&v;
atomicInc(&ic[cv[digit]], 65536*32767);
}
__syncthreads();
bi[bibase + threadIdx.x] = ic[threadIdx.x];
bibase += RNDVALS;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13__radixcountsPfiiPj
.globl _Z13__radixcountsPfiiPj
.p2align 8
.type _Z13__radixcountsPfiiPj,@function
_Z13__radixcountsPfiiPj:
s_clause 0x1
s_load_b32 s10, s[2:3], 0x8
s_load_b32 s8, s[2:3], 0x18
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, s9
s_waitcnt lgkmcnt(0)
s_ashr_i32 s11, s10, 31
s_mul_hi_u32 s4, s10, s15
s_mul_i32 s5, s11, s15
s_mul_i32 s12, s10, s15
s_add_i32 s7, s4, s5
s_mov_b64 s[4:5], s[8:9]
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_13
v_cvt_f32_ubyte0_e32 v1, 0
v_cvt_f32_u32_e32 v2, s4
s_sub_u32 s13, 0, s4
s_subb_u32 s14, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v1, 0x4f800000, v2
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s6, v2
v_readfirstlane_b32 s8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s16, s13, s6
s_mul_hi_u32 s18, s13, s8
s_mul_i32 s17, s14, s8
s_add_i32 s16, s18, s16
s_mul_i32 s19, s13, s8
s_add_i32 s16, s16, s17
s_mul_hi_u32 s18, s8, s19
s_mul_hi_u32 s20, s6, s19
s_mul_i32 s17, s6, s19
s_mul_hi_u32 s19, s8, s16
s_mul_i32 s8, s8, s16
s_mul_hi_u32 s21, s6, s16
s_add_u32 s8, s18, s8
s_addc_u32 s18, 0, s19
s_add_u32 s8, s8, s17
s_mul_i32 s16, s6, s16
s_addc_u32 s8, s18, s20
s_addc_u32 s17, s21, 0
s_add_u32 s8, s8, s16
s_addc_u32 s16, 0, s17
v_add_co_u32 v1, s8, v1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s8, 0
s_addc_u32 s6, s6, s16
v_readfirstlane_b32 s8, v1
s_mul_i32 s16, s13, s6
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s17, s13, s8
s_mul_i32 s14, s14, s8
s_add_i32 s16, s17, s16
s_mul_i32 s13, s13, s8
s_add_i32 s16, s16, s14
s_mul_hi_u32 s17, s6, s13
s_mul_i32 s18, s6, s13
s_mul_hi_u32 s13, s8, s13
s_mul_hi_u32 s19, s8, s16
s_mul_i32 s8, s8, s16
s_mul_hi_u32 s14, s6, s16
s_add_u32 s8, s13, s8
s_addc_u32 s13, 0, s19
s_add_u32 s8, s8, s18
s_mul_i32 s16, s6, s16
s_addc_u32 s8, s13, s17
s_addc_u32 s13, s14, 0
s_add_u32 s8, s8, s16
s_addc_u32 s13, 0, s13
v_add_co_u32 v1, s8, v1, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s8, 0
s_addc_u32 s8, s6, s13
s_ashr_i32 s16, s7, 31
v_readfirstlane_b32 s13, v1
s_add_u32 s6, s12, s16
s_mov_b32 s17, s16
s_addc_u32 s7, s7, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[6:7], s[6:7], s[16:17]
s_mul_i32 s18, s6, s8
s_mul_hi_u32 s19, s6, s13
s_mul_hi_u32 s14, s6, s8
s_mul_hi_u32 s21, s7, s13
s_mul_i32 s13, s7, s13
s_add_u32 s18, s19, s18
s_addc_u32 s14, 0, s14
s_mul_hi_u32 s20, s7, s8
s_add_u32 s13, s18, s13
s_mul_i32 s8, s7, s8
s_addc_u32 s13, s14, s21
s_addc_u32 s14, s20, 0
s_add_u32 s8, s13, s8
s_addc_u32 s13, 0, s14
s_mul_i32 s18, s4, s8
s_add_u32 s14, s8, 1
v_sub_co_u32 v1, s6, s6, s18
s_mul_hi_u32 s18, s4, s8
s_addc_u32 s19, s13, 0
s_mul_i32 s20, s4, s13
s_delay_alu instid0(VALU_DEP_1)
v_sub_co_u32 v2, s21, v1, s4
s_add_u32 s22, s8, 2
s_addc_u32 s23, s13, 0
s_add_i32 s18, s18, s20
s_cmp_lg_u32 s6, 0
v_readfirstlane_b32 s6, v2
s_subb_u32 s7, s7, s18
s_cmp_lg_u32 s21, 0
s_subb_u32 s18, s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s4
s_cselect_b32 s6, -1, 0
s_cmp_eq_u32 s18, 0
v_readfirstlane_b32 s18, v1
s_cselect_b32 s6, s6, -1
s_cmp_lg_u32 s6, 0
s_cselect_b32 s6, s22, s14
s_cselect_b32 s14, s23, s19
s_cmp_ge_u32 s18, s4
s_cselect_b32 s18, -1, 0
s_cmp_eq_u32 s7, 0
s_cselect_b32 s7, s18, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s7, 0
s_cselect_b32 s7, s14, s13
s_cselect_b32 s6, s6, s8
s_xor_b64 s[6:7], s[6:7], s[16:17]
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_u32 s6, s6, s16
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_3
.LBB0_2:
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s7, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v1
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s12, s6
s_mul_i32 s7, s6, s4
s_add_i32 s8, s6, 1
s_sub_i32 s7, s12, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s4
s_cmp_ge_u32 s7, s4
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s4
s_cselect_b32 s6, s8, s6
.LBB0_3:
s_add_i32 s7, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s11, s7
s_mul_hi_u32 s9, s10, s7
s_mul_i32 s7, s10, s7
s_add_i32 s9, s9, s8
s_mov_b32 s8, 0
s_cmp_lg_u64 s[8:9], 0
s_cbranch_scc0 .LBB0_14
v_cvt_f32_ubyte0_e32 v1, 0
v_cvt_f32_u32_e32 v2, s4
s_sub_u32 s12, 0, s4
s_subb_u32 s5, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v1, 0x4f800000, v2
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s10, v2
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s13, s12, s10
s_mul_hi_u32 s16, s12, s11
s_mul_i32 s14, s5, s11
s_add_i32 s13, s16, s13
s_mul_i32 s17, s12, s11
s_add_i32 s13, s13, s14
s_mul_hi_u32 s16, s11, s17
s_mul_hi_u32 s18, s10, s17
s_mul_i32 s14, s10, s17
s_mul_hi_u32 s17, s11, s13
s_mul_i32 s11, s11, s13
s_mul_hi_u32 s19, s10, s13
s_add_u32 s11, s16, s11
s_addc_u32 s16, 0, s17
s_add_u32 s11, s11, s14
s_mul_i32 s13, s10, s13
s_addc_u32 s11, s16, s18
s_addc_u32 s14, s19, 0
s_add_u32 s11, s11, s13
s_addc_u32 s13, 0, s14
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s10, s10, s13
v_readfirstlane_b32 s11, v1
s_mul_i32 s13, s12, s10
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s14, s12, s11
s_mul_i32 s5, s5, s11
s_add_i32 s13, s14, s13
s_mul_i32 s12, s12, s11
s_add_i32 s13, s13, s5
s_mul_hi_u32 s5, s11, s12
s_mul_hi_u32 s17, s11, s13
s_mul_i32 s11, s11, s13
s_mul_i32 s16, s10, s12
s_add_u32 s5, s5, s11
s_mul_hi_u32 s14, s10, s12
s_addc_u32 s11, 0, s17
s_mul_hi_u32 s12, s10, s13
s_add_u32 s5, s5, s16
s_mul_i32 s13, s10, s13
s_addc_u32 s5, s11, s14
s_addc_u32 s11, s12, 0
s_add_u32 s5, s5, s13
s_addc_u32 s11, 0, s11
v_add_co_u32 v1, s5, v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
s_addc_u32 s5, s10, s11
s_ashr_i32 s10, s9, 31
s_add_u32 s12, s7, s10
s_addc_u32 s13, s9, s10
v_readfirstlane_b32 s9, v1
s_mov_b32 s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[12:13], s[12:13], s[10:11]
s_mul_i32 s14, s12, s5
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s16, s12, s9
s_mul_hi_u32 s11, s12, s5
s_mul_hi_u32 s18, s13, s9
s_mul_i32 s9, s13, s9
s_add_u32 s14, s16, s14
s_addc_u32 s11, 0, s11
s_mul_hi_u32 s17, s13, s5
s_add_u32 s9, s14, s9
s_mul_i32 s5, s13, s5
s_addc_u32 s9, s11, s18
s_addc_u32 s11, s17, 0
s_add_u32 s5, s9, s5
s_addc_u32 s9, 0, s11
s_mul_i32 s16, s4, s5
s_mul_hi_u32 s14, s4, s5
v_sub_co_u32 v1, s12, s12, s16
s_mul_i32 s9, s4, s9
s_add_u32 s11, s5, 1
s_add_i32 s14, s14, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, s9, v1, s4
s_add_u32 s16, s5, 2
s_cmp_lg_u32 s12, 0
v_mov_b32_e32 v3, s16
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_subb_u32 s12, s13, s14
s_cmp_lg_u32 s9, 0
s_subb_u32 s9, s12, 0
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_cmp_eq_u32 s9, 0
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s12, 0
v_cndmask_b32_e32 v2, -1, v2, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
v_cndmask_b32_e32 v1, -1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, s11, v3, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, s5, v2, vcc_lo
v_xor_b32_e32 v1, s10, v1
s_delay_alu instid0(VALU_DEP_1)
v_sub_co_u32 v1, vcc_lo, v1, s10
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_6
.LBB0_5:
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, s6, v1
s_cbranch_vccnz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x4
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v8, 0x3ff, v0
s_clause 0x1
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b32 s7, s[2:3], 0xc
v_bfe_u32 v2, v0, 10, 10
v_dual_mov_b32 v11, 0x7fff0000 :: v_dual_add_nc_u32 v4, s6, v8
s_load_b64 s[2:3], s[2:3], 0x10
v_bfe_u32 v0, v0, 20, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s0, 16
v_mul_u32_u24_e32 v2, s1, v2
s_mul_i32 s0, s0, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, s4, v4
v_mul_lo_u32 v6, s0, v8
s_ashr_i32 s0, s6, 31
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_lshr_b32 s0, s0, 20
s_add_i32 s0, s6, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add3_u32 v2, v6, v2, v0
s_ashr_i32 s0, s0, 12
v_lshlrev_b32_e32 v0, 2, v8
s_add_i32 s0, s0, s15
v_lshl_add_u32 v9, v2, 2, 0x400
s_lshl_b32 s1, s0, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v10, s7, v9
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
v_add_nc_u32_e32 v2, s1, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v12, v0
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_addk_i32 s6, 0x1000
v_add_co_u32 v4, s0, v4, 0x4000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, s6, v1
s_addk_i32 s1, 0x100
s_waitcnt lgkmcnt(0)
global_store_b32 v[6:7], v12, off
s_cbranch_vccnz .LBB0_12
.LBB0_9:
v_add_nc_u32_e32 v2, s6, v8
s_mov_b32 s4, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_store_b32 v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_lt_i32_e64 v2, v1
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v6, 0x1000, v2
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v12, v1, v6
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
.p2align 6
.LBB0_11:
global_load_b32 v13, v[6:7], off
v_add_nc_u32_e32 v2, 0x100, v2
v_add_co_u32 v6, s0, v6, 0x400
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v2, v12
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
ds_load_u8 v13, v10
s_waitcnt lgkmcnt(0)
v_lshlrev_b32_e32 v13, 2, v13
ds_inc_u32 v13, v11
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_11
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_13:
s_branch .LBB0_2
.LBB0_14:
s_branch .LBB0_5
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13__radixcountsPfiiPj
.amdhsa_group_segment_fixed_size 5120
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13__radixcountsPfiiPj, .Lfunc_end0-_Z13__radixcountsPfiiPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 5120
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13__radixcountsPfiiPj
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z13__radixcountsPfiiPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __radixcounts(float *a, int n, int digit, unsigned int *bi) {
__shared__ unsigned int ic[RNDVALS];
int istart = (int)(((long long)blockIdx.x) * n / gridDim.x);
int iend = (int)(((long long)(blockIdx.x+1)) * n / gridDim.x);
int tid = threadIdx.x;
int bibase = RNDVALS * (blockIdx.x + istart / RBIGBLK);
for (int i = istart; i < iend; i += RBIGBLK) {
__syncthreads();
ic[threadIdx.x] = 0;
__syncthreads();
for (int j = i + tid; j < min(iend, i+tid+RBIGBLK); j += RNTHREADS) {
float v = a[j];
unsigned char *cv = (unsigned char *)&v;
atomicInc(&ic[cv[digit]], 65536*32767);
}
__syncthreads();
bi[bibase + threadIdx.x] = ic[threadIdx.x];
bibase += RNDVALS;
}
} | .text
.file "__radixcounts.hip"
.globl _Z28__device_stub____radixcountsPfiiPj # -- Begin function _Z28__device_stub____radixcountsPfiiPj
.p2align 4, 0x90
.type _Z28__device_stub____radixcountsPfiiPj,@function
_Z28__device_stub____radixcountsPfiiPj: # @_Z28__device_stub____radixcountsPfiiPj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13__radixcountsPfiiPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub____radixcountsPfiiPj, .Lfunc_end0-_Z28__device_stub____radixcountsPfiiPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13__radixcountsPfiiPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13__radixcountsPfiiPj,@object # @_Z13__radixcountsPfiiPj
.section .rodata,"a",@progbits
.globl _Z13__radixcountsPfiiPj
.p2align 3, 0x0
_Z13__radixcountsPfiiPj:
.quad _Z28__device_stub____radixcountsPfiiPj
.size _Z13__radixcountsPfiiPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13__radixcountsPfiiPj"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub____radixcountsPfiiPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13__radixcountsPfiiPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00032007_00000000-6___radixcounts.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj
.type _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj, @function
_Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13__radixcountsPfiiPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj, .-_Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj
.globl _Z13__radixcountsPfiiPj
.type _Z13__radixcountsPfiiPj, @function
_Z13__radixcountsPfiiPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13__radixcountsPfiiPjPfiiPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13__radixcountsPfiiPj, .-_Z13__radixcountsPfiiPj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13__radixcountsPfiiPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13__radixcountsPfiiPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "__radixcounts.hip"
.globl _Z28__device_stub____radixcountsPfiiPj # -- Begin function _Z28__device_stub____radixcountsPfiiPj
.p2align 4, 0x90
.type _Z28__device_stub____radixcountsPfiiPj,@function
_Z28__device_stub____radixcountsPfiiPj: # @_Z28__device_stub____radixcountsPfiiPj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13__radixcountsPfiiPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub____radixcountsPfiiPj, .Lfunc_end0-_Z28__device_stub____radixcountsPfiiPj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13__radixcountsPfiiPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13__radixcountsPfiiPj,@object # @_Z13__radixcountsPfiiPj
.section .rodata,"a",@progbits
.globl _Z13__radixcountsPfiiPj
.p2align 3, 0x0
_Z13__radixcountsPfiiPj:
.quad _Z28__device_stub____radixcountsPfiiPj
.size _Z13__radixcountsPfiiPj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13__radixcountsPfiiPj"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub____radixcountsPfiiPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13__radixcountsPfiiPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<stdlib.h>
__global__ void add(int *a,int *b,int *c)
{
int index=blockIdx.x*blockDim.x+threadIdx.x;
c[index]=a[index]+b[index];
}
void random_ints(int *a,int N)
{
int i;
for(i=0;i<N;i++)
{
a[i]=i;
}
}
#define N 2048
#define THREADS_PER_BLOCK 64
int main(void)
{
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int size=N*sizeof(int);
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
a=(int *)malloc(size);random_ints(a,N);
b=(int *)malloc(size);random_ints(b,N);
c=(int *)malloc(size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
int i;
for(i=0;i<N;i++)
{
std::cout<<c[i]<<"\n";
}
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<stdlib.h>
__global__ void add(int *a,int *b,int *c)
{
int index=blockIdx.x*blockDim.x+threadIdx.x;
c[index]=a[index]+b[index];
}
void random_ints(int *a,int N)
{
int i;
for(i=0;i<N;i++)
{
a[i]=i;
}
}
#define N 2048
#define THREADS_PER_BLOCK 64
int main(void)
{
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int size=N*sizeof(int);
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
a=(int *)malloc(size);random_ints(a,N);
b=(int *)malloc(size);random_ints(b,N);
c=(int *)malloc(size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
int i;
for(i=0;i<N;i++)
{
std::cout<<c[i]<<"\n";
}
return 0;
} | .file "tmpxft_00130a97_00000000-6_file.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %r12
movl $2048, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %ecx
movl $8192, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rbx
addq $8192, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r12
.L17:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L17
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<stdlib.h>
__global__ void add(int *a,int *b,int *c)
{
int index=blockIdx.x*blockDim.x+threadIdx.x;
c[index]=a[index]+b[index];
}
void random_ints(int *a,int N)
{
int i;
for(i=0;i<N;i++)
{
a[i]=i;
}
}
#define N 2048
#define THREADS_PER_BLOCK 64
int main(void)
{
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int size=N*sizeof(int);
cudaMalloc((void **)&d_a,size);
cudaMalloc((void **)&d_b,size);
cudaMalloc((void **)&d_c,size);
a=(int *)malloc(size);random_ints(a,N);
b=(int *)malloc(size);random_ints(b,N);
c=(int *)malloc(size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
int i;
for(i=0;i<N;i++)
{
std::cout<<c[i]<<"\n";
}
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<stdlib.h>
__global__ void add(int *a,int *b,int *c)
{
int index=blockIdx.x*blockDim.x+threadIdx.x;
c[index]=a[index]+b[index];
}
void random_ints(int *a,int N)
{
int i;
for(i=0;i<N;i++)
{
a[i]=i;
}
}
#define N 2048
#define THREADS_PER_BLOCK 64
int main(void)
{
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int size=N*sizeof(int);
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
a=(int *)malloc(size);random_ints(a,N);
b=(int *)malloc(size);random_ints(b,N);
c=(int *)malloc(size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
int i;
for(i=0;i<N;i++)
{
std::cout<<c[i]<<"\n";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<stdlib.h>
__global__ void add(int *a,int *b,int *c)
{
int index=blockIdx.x*blockDim.x+threadIdx.x;
c[index]=a[index]+b[index];
}
void random_ints(int *a,int N)
{
int i;
for(i=0;i<N;i++)
{
a[i]=i;
}
}
#define N 2048
#define THREADS_PER_BLOCK 64
int main(void)
{
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int size=N*sizeof(int);
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
a=(int *)malloc(size);random_ints(a,N);
b=(int *)malloc(size);random_ints(b,N);
c=(int *)malloc(size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
int i;
for(i=0;i<N;i++)
{
std::cout<<c[i]<<"\n";
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<stdlib.h>
__global__ void add(int *a,int *b,int *c)
{
int index=blockIdx.x*blockDim.x+threadIdx.x;
c[index]=a[index]+b[index];
}
void random_ints(int *a,int N)
{
int i;
for(i=0;i<N;i++)
{
a[i]=i;
}
}
#define N 2048
#define THREADS_PER_BLOCK 64
int main(void)
{
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int size=N*sizeof(int);
hipMalloc((void **)&d_a,size);
hipMalloc((void **)&d_b,size);
hipMalloc((void **)&d_c,size);
a=(int *)malloc(size);random_ints(a,N);
b=(int *)malloc(size);random_ints(b,N);
c=(int *)malloc(size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
add<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
int i;
for(i=0;i<N;i++)
{
std::cout<<c[i]<<"\n";
}
return 0;
} | .text
.file "file.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i19
# =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit23
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 32(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $2048, %r14 # imm = 0x800
jne .LBB2_7
# %bb.8:
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00130a97_00000000-6_file.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, %r12
movl $2048, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $8192, %edi
call malloc@PLT
movq %rax, %rbx
movl $2048, %esi
movq %rax, %rdi
call _Z11random_intsPii
movl $8192, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, %ecx
movl $8192, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L16:
movl $2, %ecx
movl $8192, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rbx
addq $8192, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r12
.L17:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %rbp
jne .L17
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "file.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq %rsp, %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB2_1
# %bb.2: # %_Z11random_intsPii.exit
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i19
# =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $2048, %rax # imm = 0x800
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit23
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %rbx
movq 16(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 32(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $2048, %r14 # imm = 0x800
jne .LBB2_7
# %bb.8:
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define R 5
#define C 40
__device__ int gpu_strlen(char * s)
{
int i = 0;
while(s[i++] != '\0')
{
}
return i;
}
__device__ int gpu_isAlpha(char ch)
{
if((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z'))
return 1;
else
return 0;
}
__global__ void wordCount2( char **a, int **out, int numLine, int maxLineLen )
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int currLen = gpu_strlen(a[iy]);
__shared__ char s_data[C];
if(ix >= gpu_strlen(a[0]) && iy >= numLine) {
return;
}
s_data[ix] = a[iy][ix];
//each thread process one character within a line
if( ix < currLen && gpu_isAlpha(s_data[ix]) != 1 )
{
out[iy][ix] += 1;
}
__syncthreads();
if(out[iy][ix] == 1 && ix < currLen)
out[iy][ix + 1] = 0;
}
void checkErr()
{
cudaError_t code = cudaGetLastError();
if (code != cudaSuccess)
printf ("Cuda error -- %s\n", cudaGetErrorString(code));
}
void printArr( char **a, int lines )
{
int i;
for(i=0; i<lines; i++)
{
printf("%s\n", a[i]);
}
}
int main()
{
int i, j;
char **d_in, **h_in, **h_out;
int h_count_in[R][C], **h_count_out, **d_count_in;
for(i = 0; i < R; i++)
for(j = 0; j < C; j ++)
h_count_in[i][j] = 0;
//allocate
h_in = (char **)malloc(R * sizeof(char *));
h_out = (char **)malloc(R * sizeof(char *));
h_count_out = (int **)malloc(R * sizeof(int *));
cudaDeviceReset();
cudaMalloc((void ***)&d_in, sizeof(char *) * R);
cudaMalloc((void ***)&d_count_in, sizeof(int *) * R);
//alocate for string data
for(i = 0; i < R; ++i)
{
cudaMalloc((void **) &h_out[i],C * sizeof(char));
h_in[i]=(char *)calloc(C, sizeof(char));//allocate or connect the input data to it
strcpy(h_in[i], "good morning and I'm a good student!");
cudaMemcpy(h_out[i], h_in[i], strlen(h_in[i]) + 1, cudaMemcpyHostToDevice);
}
cudaMemcpy(d_in, h_out, sizeof(char *) * R,cudaMemcpyHostToDevice);
//alocate for output occurrence
for(i = 0; i < R; ++i)
{
cudaMalloc((void **) &h_count_out[i], C * sizeof(int));
cudaMemset(h_count_out[i], 0, C * sizeof(int));
}
cudaMemcpy(d_count_in, h_count_out, sizeof(int *) * R,cudaMemcpyHostToDevice);
printArr(h_in, R);
printf("\n\n");
//set up kernel configuration variables
dim3 grid, block;
block.x = C; //NOTE: differs from last lab6 here, Why?
block.y = 1;
grid.x = ceil((float)C / block.x);
grid.y = ceil((float)R / block.y); //careful must be type cast into float, otherwise, integer division used
printf("grid.x = %d, grid.y=%d\n", grid.x, grid.y );
//printf("block.x = %d, block.y=%d\n", block.x, block.y );
//launch kernel
wordCount2<<<grid, block>>>( d_in, d_count_in, R, C);
checkErr();
//copy data back from device to host
for(i = 0; i < R; ++i) {
cudaMemcpy(h_count_in[i], h_count_out[i], sizeof(int) * C,cudaMemcpyDeviceToHost);
}
printf("Occurrence array obtained from device:\n");
for(i = 0; i < R; i ++) {
for(int j = 0; j < C; j ++)
printf("%4d", h_count_in[i][j]);
printf("\n");
}
return 0;
} | code for sm_80
Function : _Z10wordCount2PPcPPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1b00 */
/*0080*/ BSSY B0, 0x170 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fe20000011404 */
/*00b0*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*00c0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*00e0*/ IADD3 R8, P0, R2, R11, RZ ; /* 0x0000000b02087210 */
/* 0x020fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R9, R11, R3, 0x1, P0 ; /* 0x000000030b097211 */
/* 0x000fca00000f0eff */
/*0100*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0110*/ IADD3 R6, R11, 0x1, RZ ; /* 0x000000010b067810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fc800078e000b */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, R6 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0006 */
/*0140*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0150*/ @P0 BRA 0xe0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fcc00078e00ff */
/*0190*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1b00 */
/*01a0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R10, P0, R8, R13, RZ ; /* 0x0000000d080a7210 */
/* 0x020fc80007f1e0ff */
/*01c0*/ LEA.HI.X.SX32 R11, R13, R9, 0x1, P0 ; /* 0x000000090d0b7211 */
/* 0x000fca00000f0eff */
/*01d0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1100 */
/*01e0*/ IADD3 R6, R13, 0x1, RZ ; /* 0x000000010d067810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0006 */
/*0210*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0220*/ @P0 BRA 0x1b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0230*/ ISETP.GT.AND P0, PT, R0, R15, PT ; /* 0x0000000f0000720c */
/* 0x000fe40003f04270 */
/*0240*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f26270 */
/*0250*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*0260*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ; /* 0x0000001fff0f7819 */
/* 0x000fe40000011400 */
/*0270*/ IADD3 R8, P0, R0, R2, RZ ; /* 0x0000000200087210 */
/* 0x000fca0007f1e0ff */
/*0280*/ IMAD.X R9, R3, 0x1, R15, P0 ; /* 0x0000000103097824 */
/* 0x000fca00000e060f */
/*0290*/ LDG.E.U8 R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea4000c1e1100 */
/*02a0*/ LOP3.LUT R2, R11, 0xdf, RZ, 0xc0, !PT ; /* 0x000000df0b027812 */
/* 0x004fc800078ec0ff */
/*02b0*/ IADD3 R2, R2, -0x41, RZ ; /* 0xffffffbf02027810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02027812 */
/* 0x000fc800078ec0ff */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x1a, PT ; /* 0x0000001a0200780c */
/* 0x000fe40003f06070 */
/*02e0*/ LEA R2, P1, R4, c[0x0][0x168], 0x3 ; /* 0x00005a0004027a11 */
/* 0x000fe400078218ff */
/*02f0*/ ISETP.GT.OR P0, PT, R0, R5, !P0 ; /* 0x000000050000720c */
/* 0x000fe40004704670 */
/*0300*/ LEA.HI.X R3, R4, c[0x0][0x16c], R7, 0x3, P1 ; /* 0x00005b0004037a11 */
/* 0x000fd600008f1c07 */
/*0310*/ @!P0 LDG.E.64 R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ea4000c1e1b00 */
/*0320*/ @!P0 LEA R6, P1, R0, R6, 0x2 ; /* 0x0000000600068211 */
/* 0x004fc800078210ff */
/*0330*/ @!P0 LEA.HI.X R7, R0, R7, R15, 0x2, P1 ; /* 0x0000000700078211 */
/* 0x000fca00008f140f */
/*0340*/ @!P0 LDG.E R4, [R6.64] ; /* 0x0000000406048981 */
/* 0x000ea8000c1e1900 */
/*0350*/ STS.U8 [R0], R11 ; /* 0x0000000b00007388 */
/* 0x0001e20000000000 */
/*0360*/ @!P0 IADD3 R13, R4, 0x1, RZ ; /* 0x00000001040d8810 */
/* 0x004fca0007ffe0ff */
/*0370*/ @!P0 STG.E [R6.64], R13 ; /* 0x0000000d06008986 */
/* 0x0001e8000c101904 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*03a0*/ LEA R8, P0, R0, R8, 0x2 ; /* 0x0000000800087211 */
/* 0x004fc800078010ff */
/*03b0*/ LEA.HI.X R9, R0, R9, R15, 0x2, P0 ; /* 0x0000000900097211 */
/* 0x000fca00000f140f */
/*03c0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fc80003f05270 */
/*03e0*/ ISETP.GT.OR P0, PT, R0, R5, P0 ; /* 0x000000050000720c */
/* 0x000fda0000704670 */
/*03f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0400*/ STG.E [R8.64+0x4], RZ ; /* 0x000004ff08007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define R 5
#define C 40
__device__ int gpu_strlen(char * s)
{
int i = 0;
while(s[i++] != '\0')
{
}
return i;
}
__device__ int gpu_isAlpha(char ch)
{
if((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z'))
return 1;
else
return 0;
}
__global__ void wordCount2( char **a, int **out, int numLine, int maxLineLen )
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int currLen = gpu_strlen(a[iy]);
__shared__ char s_data[C];
if(ix >= gpu_strlen(a[0]) && iy >= numLine) {
return;
}
s_data[ix] = a[iy][ix];
//each thread process one character within a line
if( ix < currLen && gpu_isAlpha(s_data[ix]) != 1 )
{
out[iy][ix] += 1;
}
__syncthreads();
if(out[iy][ix] == 1 && ix < currLen)
out[iy][ix + 1] = 0;
}
void checkErr()
{
cudaError_t code = cudaGetLastError();
if (code != cudaSuccess)
printf ("Cuda error -- %s\n", cudaGetErrorString(code));
}
void printArr( char **a, int lines )
{
int i;
for(i=0; i<lines; i++)
{
printf("%s\n", a[i]);
}
}
int main()
{
int i, j;
char **d_in, **h_in, **h_out;
int h_count_in[R][C], **h_count_out, **d_count_in;
for(i = 0; i < R; i++)
for(j = 0; j < C; j ++)
h_count_in[i][j] = 0;
//allocate
h_in = (char **)malloc(R * sizeof(char *));
h_out = (char **)malloc(R * sizeof(char *));
h_count_out = (int **)malloc(R * sizeof(int *));
cudaDeviceReset();
cudaMalloc((void ***)&d_in, sizeof(char *) * R);
cudaMalloc((void ***)&d_count_in, sizeof(int *) * R);
//alocate for string data
for(i = 0; i < R; ++i)
{
cudaMalloc((void **) &h_out[i],C * sizeof(char));
h_in[i]=(char *)calloc(C, sizeof(char));//allocate or connect the input data to it
strcpy(h_in[i], "good morning and I'm a good student!");
cudaMemcpy(h_out[i], h_in[i], strlen(h_in[i]) + 1, cudaMemcpyHostToDevice);
}
cudaMemcpy(d_in, h_out, sizeof(char *) * R,cudaMemcpyHostToDevice);
//alocate for output occurrence
for(i = 0; i < R; ++i)
{
cudaMalloc((void **) &h_count_out[i], C * sizeof(int));
cudaMemset(h_count_out[i], 0, C * sizeof(int));
}
cudaMemcpy(d_count_in, h_count_out, sizeof(int *) * R,cudaMemcpyHostToDevice);
printArr(h_in, R);
printf("\n\n");
//set up kernel configuration variables
dim3 grid, block;
block.x = C; //NOTE: differs from last lab6 here, Why?
block.y = 1;
grid.x = ceil((float)C / block.x);
grid.y = ceil((float)R / block.y); //careful must be type cast into float, otherwise, integer division used
printf("grid.x = %d, grid.y=%d\n", grid.x, grid.y );
//printf("block.x = %d, block.y=%d\n", block.x, block.y );
//launch kernel
wordCount2<<<grid, block>>>( d_in, d_count_in, R, C);
checkErr();
//copy data back from device to host
for(i = 0; i < R; ++i) {
cudaMemcpy(h_count_in[i], h_count_out[i], sizeof(int) * C,cudaMemcpyDeviceToHost);
}
printf("Occurrence array obtained from device:\n");
for(i = 0; i < R; i ++) {
for(int j = 0; j < C; j ++)
printf("%4d", h_count_in[i][j]);
printf("\n");
}
return 0;
} | .file "tmpxft_0019ba9a_00000000-6_lab8.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10gpu_strlenPc
.type _Z10gpu_strlenPc, @function
_Z10gpu_strlenPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10gpu_strlenPc, .-_Z10gpu_strlenPc
.globl _Z11gpu_isAlphac
.type _Z11gpu_isAlphac, @function
_Z11gpu_isAlphac:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11gpu_isAlphac, .-_Z11gpu_isAlphac
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error -- %s\n"
.text
.globl _Z8checkErrv
.type _Z8checkErrv, @function
_Z8checkErrv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L10
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2059:
.size _Z8checkErrv, .-_Z8checkErrv
.section .rodata.str1.1
.LC1:
.string "%s\n"
.text
.globl _Z8printArrPPci
.type _Z8printArrPPci, @function
_Z8printArrPPci:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r12
leaq .LC1(%rip), %rbp
.L13:
movq (%rbx), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L13
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2060:
.size _Z8printArrPPci, .-_Z8printArrPPci
.globl _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
.type _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii, @function
_Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10wordCount2PPcPPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii, .-_Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
.globl _Z10wordCount2PPcPPiii
.type _Z10wordCount2PPcPPiii, @function
_Z10wordCount2PPcPPiii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10wordCount2PPcPPiii, .-_Z10wordCount2PPcPPiii
.section .rodata.str1.1
.LC2:
.string "\n\n"
.LC3:
.string "grid.x = %d, grid.y=%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Occurrence array obtained from device:\n"
.section .rodata.str1.1
.LC5:
.string "%4d"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $904, %rsp
.cfi_def_cfa_offset 960
movq %fs:40, %rax
movq %rax, 888(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %r13
leaq 240(%rsp), %rbx
leaq 1040(%rsp), %r15
movq %rbx, %rdx
.L28:
leaq -160(%rdx), %rax
.L29:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L29
addq $160, %rdx
cmpq %r15, %rdx
jne .L28
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, 24(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, 8(%rsp)
call cudaDeviceReset@PLT
leaq 40(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movq %rbp, %r12
leaq 40(%rbp), %rax
movq %rax, (%rsp)
.L31:
movl $40, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movl $1, %esi
movl $40, %edi
call calloc@PLT
movq %rax, %rbp
movq %rax, (%r14)
movabsq $8245929428630073191, %rax
movabsq $7236828443033102702, %rdx
movq %rax, 0(%rbp)
movq %rdx, 8(%rbp)
movabsq $7431046177059457312, %rax
movabsq $7238820013881454447, %rdx
movq %rax, 16(%rbp)
movq %rdx, 24(%rbp)
movabsq $9416691727758708, %rax
movq %rax, 29(%rbp)
movq %rbp, %rdi
call strlen@PLT
leaq 1(%rax), %rdx
movq (%r12), %rdi
movl $1, %ecx
movq %rbp, %rsi
call cudaMemcpy@PLT
addq $8, %r12
addq $8, %r14
movq (%rsp), %rax
cmpq %rax, %r12
jne .L31
movl $1, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rbp
movq %rbp, %r12
leaq 40(%rbp), %r14
.L32:
movl $160, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movq 0(%rbp), %rdi
movl $160, %edx
movl $0, %esi
call cudaMemset@PLT
addq $8, %rbp
cmpq %r14, %rbp
jne .L32
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq 16(%rsp), %rdi
call _Z8printArrPPci
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 64(%rsp)
movl $1, 76(%rsp)
movl $5, %ecx
movl $1, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 56(%rsp)
movl $5, 60(%rsp)
movl $40, 68(%rsp)
movl $1, 72(%rsp)
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L33:
call _Z8checkErrv
leaq 800(%r13), %rbp
.L34:
movq (%r12), %rsi
movl $2, %ecx
movl $160, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
addq $8, %r12
addq $160, %r13
cmpq %rbp, %r13
jne .L34
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r13
.L35:
leaq -160(%rbx), %rbp
.L36:
movl 0(%rbp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %rbx, %rbp
jne .L36
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $160, %rbx
cmpq %r15, %rbx
jne .L35
movq 888(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $904, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $40, %ecx
movl $5, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
jmp .L33
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10wordCount2PPcPPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10wordCount2PPcPPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define R 5
#define C 40
__device__ int gpu_strlen(char * s)
{
int i = 0;
while(s[i++] != '\0')
{
}
return i;
}
__device__ int gpu_isAlpha(char ch)
{
if((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z'))
return 1;
else
return 0;
}
__global__ void wordCount2( char **a, int **out, int numLine, int maxLineLen )
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int currLen = gpu_strlen(a[iy]);
__shared__ char s_data[C];
if(ix >= gpu_strlen(a[0]) && iy >= numLine) {
return;
}
s_data[ix] = a[iy][ix];
//each thread process one character within a line
if( ix < currLen && gpu_isAlpha(s_data[ix]) != 1 )
{
out[iy][ix] += 1;
}
__syncthreads();
if(out[iy][ix] == 1 && ix < currLen)
out[iy][ix + 1] = 0;
}
void checkErr()
{
cudaError_t code = cudaGetLastError();
if (code != cudaSuccess)
printf ("Cuda error -- %s\n", cudaGetErrorString(code));
}
void printArr( char **a, int lines )
{
int i;
for(i=0; i<lines; i++)
{
printf("%s\n", a[i]);
}
}
int main()
{
int i, j;
char **d_in, **h_in, **h_out;
int h_count_in[R][C], **h_count_out, **d_count_in;
for(i = 0; i < R; i++)
for(j = 0; j < C; j ++)
h_count_in[i][j] = 0;
//allocate
h_in = (char **)malloc(R * sizeof(char *));
h_out = (char **)malloc(R * sizeof(char *));
h_count_out = (int **)malloc(R * sizeof(int *));
cudaDeviceReset();
cudaMalloc((void ***)&d_in, sizeof(char *) * R);
cudaMalloc((void ***)&d_count_in, sizeof(int *) * R);
//alocate for string data
for(i = 0; i < R; ++i)
{
cudaMalloc((void **) &h_out[i],C * sizeof(char));
h_in[i]=(char *)calloc(C, sizeof(char));//allocate or connect the input data to it
strcpy(h_in[i], "good morning and I'm a good student!");
cudaMemcpy(h_out[i], h_in[i], strlen(h_in[i]) + 1, cudaMemcpyHostToDevice);
}
cudaMemcpy(d_in, h_out, sizeof(char *) * R,cudaMemcpyHostToDevice);
//alocate for output occurrence
for(i = 0; i < R; ++i)
{
cudaMalloc((void **) &h_count_out[i], C * sizeof(int));
cudaMemset(h_count_out[i], 0, C * sizeof(int));
}
cudaMemcpy(d_count_in, h_count_out, sizeof(int *) * R,cudaMemcpyHostToDevice);
printArr(h_in, R);
printf("\n\n");
//set up kernel configuration variables
dim3 grid, block;
block.x = C; //NOTE: differs from last lab6 here, Why?
block.y = 1;
grid.x = ceil((float)C / block.x);
grid.y = ceil((float)R / block.y); //careful must be type cast into float, otherwise, integer division used
printf("grid.x = %d, grid.y=%d\n", grid.x, grid.y );
//printf("block.x = %d, block.y=%d\n", block.x, block.y );
//launch kernel
wordCount2<<<grid, block>>>( d_in, d_count_in, R, C);
checkErr();
//copy data back from device to host
for(i = 0; i < R; ++i) {
cudaMemcpy(h_count_in[i], h_count_out[i], sizeof(int) * C,cudaMemcpyDeviceToHost);
}
printf("Occurrence array obtained from device:\n");
for(i = 0; i < R; i ++) {
for(int j = 0; j < C; j ++)
printf("%4d", h_count_in[i][j]);
printf("\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define R 5
#define C 40
__device__ int gpu_strlen(char * s)
{
int i = 0;
while(s[i++] != '\0')
{
}
return i;
}
__device__ int gpu_isAlpha(char ch)
{
if((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z'))
return 1;
else
return 0;
}
__global__ void wordCount2( char **a, int **out, int numLine, int maxLineLen )
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int currLen = gpu_strlen(a[iy]);
__shared__ char s_data[C];
if(ix >= gpu_strlen(a[0]) && iy >= numLine) {
return;
}
s_data[ix] = a[iy][ix];
//each thread process one character within a line
if( ix < currLen && gpu_isAlpha(s_data[ix]) != 1 )
{
out[iy][ix] += 1;
}
__syncthreads();
if(out[iy][ix] == 1 && ix < currLen)
out[iy][ix + 1] = 0;
}
void checkErr()
{
hipError_t code = hipGetLastError();
if (code != hipSuccess)
printf ("Cuda error -- %s\n", hipGetErrorString(code));
}
void printArr( char **a, int lines )
{
int i;
for(i=0; i<lines; i++)
{
printf("%s\n", a[i]);
}
}
int main()
{
int i, j;
char **d_in, **h_in, **h_out;
int h_count_in[R][C], **h_count_out, **d_count_in;
for(i = 0; i < R; i++)
for(j = 0; j < C; j ++)
h_count_in[i][j] = 0;
//allocate
h_in = (char **)malloc(R * sizeof(char *));
h_out = (char **)malloc(R * sizeof(char *));
h_count_out = (int **)malloc(R * sizeof(int *));
hipDeviceReset();
hipMalloc((void ***)&d_in, sizeof(char *) * R);
hipMalloc((void ***)&d_count_in, sizeof(int *) * R);
//alocate for string data
for(i = 0; i < R; ++i)
{
hipMalloc((void **) &h_out[i],C * sizeof(char));
h_in[i]=(char *)calloc(C, sizeof(char));//allocate or connect the input data to it
strcpy(h_in[i], "good morning and I'm a good student!");
hipMemcpy(h_out[i], h_in[i], strlen(h_in[i]) + 1, hipMemcpyHostToDevice);
}
hipMemcpy(d_in, h_out, sizeof(char *) * R,hipMemcpyHostToDevice);
//alocate for output occurrence
for(i = 0; i < R; ++i)
{
hipMalloc((void **) &h_count_out[i], C * sizeof(int));
hipMemset(h_count_out[i], 0, C * sizeof(int));
}
hipMemcpy(d_count_in, h_count_out, sizeof(int *) * R,hipMemcpyHostToDevice);
printArr(h_in, R);
printf("\n\n");
//set up kernel configuration variables
dim3 grid, block;
block.x = C; //NOTE: differs from last lab6 here, Why?
block.y = 1;
grid.x = ceil((float)C / block.x);
grid.y = ceil((float)R / block.y); //careful must be type cast into float, otherwise, integer division used
printf("grid.x = %d, grid.y=%d\n", grid.x, grid.y );
//printf("block.x = %d, block.y=%d\n", block.x, block.y );
//launch kernel
wordCount2<<<grid, block>>>( d_in, d_count_in, R, C);
checkErr();
//copy data back from device to host
for(i = 0; i < R; ++i) {
hipMemcpy(h_count_in[i], h_count_out[i], sizeof(int) * C,hipMemcpyDeviceToHost);
}
printf("Occurrence array obtained from device:\n");
for(i = 0; i < R; i ++) {
for(int j = 0; j < C; j ++)
printf("%4d", h_count_in[i][j]);
printf("\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define R 5
#define C 40
__device__ int gpu_strlen(char * s)
{
int i = 0;
while(s[i++] != '\0')
{
}
return i;
}
__device__ int gpu_isAlpha(char ch)
{
if((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z'))
return 1;
else
return 0;
}
__global__ void wordCount2( char **a, int **out, int numLine, int maxLineLen )
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int currLen = gpu_strlen(a[iy]);
__shared__ char s_data[C];
if(ix >= gpu_strlen(a[0]) && iy >= numLine) {
return;
}
s_data[ix] = a[iy][ix];
//each thread process one character within a line
if( ix < currLen && gpu_isAlpha(s_data[ix]) != 1 )
{
out[iy][ix] += 1;
}
__syncthreads();
if(out[iy][ix] == 1 && ix < currLen)
out[iy][ix + 1] = 0;
}
void checkErr()
{
hipError_t code = hipGetLastError();
if (code != hipSuccess)
printf ("Cuda error -- %s\n", hipGetErrorString(code));
}
void printArr( char **a, int lines )
{
int i;
for(i=0; i<lines; i++)
{
printf("%s\n", a[i]);
}
}
int main()
{
int i, j;
char **d_in, **h_in, **h_out;
int h_count_in[R][C], **h_count_out, **d_count_in;
for(i = 0; i < R; i++)
for(j = 0; j < C; j ++)
h_count_in[i][j] = 0;
//allocate
h_in = (char **)malloc(R * sizeof(char *));
h_out = (char **)malloc(R * sizeof(char *));
h_count_out = (int **)malloc(R * sizeof(int *));
hipDeviceReset();
hipMalloc((void ***)&d_in, sizeof(char *) * R);
hipMalloc((void ***)&d_count_in, sizeof(int *) * R);
//alocate for string data
for(i = 0; i < R; ++i)
{
hipMalloc((void **) &h_out[i],C * sizeof(char));
h_in[i]=(char *)calloc(C, sizeof(char));//allocate or connect the input data to it
strcpy(h_in[i], "good morning and I'm a good student!");
hipMemcpy(h_out[i], h_in[i], strlen(h_in[i]) + 1, hipMemcpyHostToDevice);
}
hipMemcpy(d_in, h_out, sizeof(char *) * R,hipMemcpyHostToDevice);
//alocate for output occurrence
for(i = 0; i < R; ++i)
{
hipMalloc((void **) &h_count_out[i], C * sizeof(int));
hipMemset(h_count_out[i], 0, C * sizeof(int));
}
hipMemcpy(d_count_in, h_count_out, sizeof(int *) * R,hipMemcpyHostToDevice);
printArr(h_in, R);
printf("\n\n");
//set up kernel configuration variables
dim3 grid, block;
block.x = C; //NOTE: differs from last lab6 here, Why?
block.y = 1;
grid.x = ceil((float)C / block.x);
grid.y = ceil((float)R / block.y); //careful must be type cast into float, otherwise, integer division used
printf("grid.x = %d, grid.y=%d\n", grid.x, grid.y );
//printf("block.x = %d, block.y=%d\n", block.x, block.y );
//launch kernel
wordCount2<<<grid, block>>>( d_in, d_count_in, R, C);
checkErr();
//copy data back from device to host
for(i = 0; i < R; ++i) {
hipMemcpy(h_count_in[i], h_count_out[i], sizeof(int) * C,hipMemcpyDeviceToHost);
}
printf("Occurrence array obtained from device:\n");
for(i = 0; i < R; i ++) {
for(int j = 0; j < C; j ++)
printf("%4d", h_count_in[i][j]);
printf("\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10wordCount2PPcPPiii
.globl _Z10wordCount2PPcPPiii
.p2align 8
.type _Z10wordCount2PPcPPiii,@function
_Z10wordCount2PPcPPiii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
.LBB0_1:
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
flat_load_u8 v5, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v5
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s7
s_load_b64 s[2:3], s[2:3], 0x0
s_mov_b64 s[4:5], 0
s_mov_b32 s7, 0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
flat_load_u8 v5, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v5
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s7
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s3, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s14, s3, v[0:1]
v_add_nc_u32_e32 v0, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v5, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s2, v1
s_or_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x8
v_add_nc_u32_e32 v0, -1, v7
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, v5, v0
v_cmpx_le_i32_e64 v5, v0
s_cbranch_execz .LBB0_8
v_add_co_u32 v3, s0, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, v4, v6, s0
flat_load_u8 v0, v[3:4]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v0, 0xdf, v0
v_add_nc_u16 v0, v0, 0xffa5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0xff, v0
v_cmp_gt_u16_e64 s0, 0xe6, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_add_co_u32 v3, s0, v3, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, v4, v8, s0
flat_load_b32 v0, v[3:4]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
flat_store_b32 v[3:4], v0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_xor_b32 s1, vcc_lo, -1
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_add_co_u32 v0, s0, v0, v2
v_add_co_ci_u32_e64 v1, s0, v1, v3, s0
flat_load_b32 v2, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e64 s0, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v2, 0
flat_store_b32 v[0:1], v2 offset:4
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10wordCount2PPcPPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10wordCount2PPcPPiii, .Lfunc_end0-_Z10wordCount2PPcPPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10wordCount2PPcPPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10wordCount2PPcPPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define R 5
#define C 40
__device__ int gpu_strlen(char * s)
{
int i = 0;
while(s[i++] != '\0')
{
}
return i;
}
__device__ int gpu_isAlpha(char ch)
{
if((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z'))
return 1;
else
return 0;
}
__global__ void wordCount2( char **a, int **out, int numLine, int maxLineLen )
{
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int currLen = gpu_strlen(a[iy]);
__shared__ char s_data[C];
if(ix >= gpu_strlen(a[0]) && iy >= numLine) {
return;
}
s_data[ix] = a[iy][ix];
//each thread process one character within a line
if( ix < currLen && gpu_isAlpha(s_data[ix]) != 1 )
{
out[iy][ix] += 1;
}
__syncthreads();
if(out[iy][ix] == 1 && ix < currLen)
out[iy][ix + 1] = 0;
}
void checkErr()
{
hipError_t code = hipGetLastError();
if (code != hipSuccess)
printf ("Cuda error -- %s\n", hipGetErrorString(code));
}
void printArr( char **a, int lines )
{
int i;
for(i=0; i<lines; i++)
{
printf("%s\n", a[i]);
}
}
int main()
{
int i, j;
char **d_in, **h_in, **h_out;
int h_count_in[R][C], **h_count_out, **d_count_in;
for(i = 0; i < R; i++)
for(j = 0; j < C; j ++)
h_count_in[i][j] = 0;
//allocate
h_in = (char **)malloc(R * sizeof(char *));
h_out = (char **)malloc(R * sizeof(char *));
h_count_out = (int **)malloc(R * sizeof(int *));
hipDeviceReset();
hipMalloc((void ***)&d_in, sizeof(char *) * R);
hipMalloc((void ***)&d_count_in, sizeof(int *) * R);
//alocate for string data
for(i = 0; i < R; ++i)
{
hipMalloc((void **) &h_out[i],C * sizeof(char));
h_in[i]=(char *)calloc(C, sizeof(char));//allocate or connect the input data to it
strcpy(h_in[i], "good morning and I'm a good student!");
hipMemcpy(h_out[i], h_in[i], strlen(h_in[i]) + 1, hipMemcpyHostToDevice);
}
hipMemcpy(d_in, h_out, sizeof(char *) * R,hipMemcpyHostToDevice);
//alocate for output occurrence
for(i = 0; i < R; ++i)
{
hipMalloc((void **) &h_count_out[i], C * sizeof(int));
hipMemset(h_count_out[i], 0, C * sizeof(int));
}
hipMemcpy(d_count_in, h_count_out, sizeof(int *) * R,hipMemcpyHostToDevice);
printArr(h_in, R);
printf("\n\n");
//set up kernel configuration variables
dim3 grid, block;
block.x = C; //NOTE: differs from last lab6 here, Why?
block.y = 1;
grid.x = ceil((float)C / block.x);
grid.y = ceil((float)R / block.y); //careful must be type cast into float, otherwise, integer division used
printf("grid.x = %d, grid.y=%d\n", grid.x, grid.y );
//printf("block.x = %d, block.y=%d\n", block.x, block.y );
//launch kernel
wordCount2<<<grid, block>>>( d_in, d_count_in, R, C);
checkErr();
//copy data back from device to host
for(i = 0; i < R; ++i) {
hipMemcpy(h_count_in[i], h_count_out[i], sizeof(int) * C,hipMemcpyDeviceToHost);
}
printf("Occurrence array obtained from device:\n");
for(i = 0; i < R; i ++) {
for(int j = 0; j < C; j ++)
printf("%4d", h_count_in[i][j]);
printf("\n");
}
return 0;
} | .text
.file "lab8.hip"
.globl _Z25__device_stub__wordCount2PPcPPiii # -- Begin function _Z25__device_stub__wordCount2PPcPPiii
.p2align 4, 0x90
.type _Z25__device_stub__wordCount2PPcPPiii,@function
_Z25__device_stub__wordCount2PPcPPiii: # @_Z25__device_stub__wordCount2PPcPPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10wordCount2PPcPPiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__wordCount2PPcPPiii, .Lfunc_end0-_Z25__device_stub__wordCount2PPcPPiii
.cfi_endproc
# -- End function
.globl _Z8checkErrv # -- Begin function _Z8checkErrv
.p2align 4, 0x90
.type _Z8checkErrv,@function
_Z8checkErrv: # @_Z8checkErrv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
je .LBB1_1
# %bb.2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8checkErrv, .Lfunc_end1-_Z8checkErrv
.cfi_endproc
# -- End function
.globl _Z8printArrPPci # -- Begin function _Z8printArrPPci
.p2align 4, 0x90
.type _Z8printArrPPci,@function
_Z8printArrPPci: # @_Z8printArrPPci
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r15,8), %rdi
callq puts@PLT
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z8printArrPPci, .Lfunc_end2-_Z8printArrPPci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 128(%rsp), %rbx
xorl %r14d, %r14d
movl $800, %edx # imm = 0x320
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $40, %edi
callq malloc
movq %rax, %r15
movl $40, %edi
callq malloc
movq %rax, %r12
movl $40, %edi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
callq hipDeviceReset
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq (%r12,%r14), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
movl $1, %esi
callq calloc
movq %rax, %r13
movq %rax, (%r15,%r14)
movups .L.str.2(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.2+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movabsq $9416691727758708, %rax # imm = 0x21746E65647574
movq %rax, 29(%r13)
movq (%r12,%r14), %rbp
movq %r13, %rdi
callq strlen
leaq 1(%rax), %rdx
movq %rbp, %rdi
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
addq $8, %r14
cmpq $40, %r14
jne .LBB3_1
# %bb.2:
movq 16(%rsp), %rdi
movl $40, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq 24(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
leaq (%r12,%r14), %rdi
movl $160, %esi
callq hipMalloc
movq (%r12,%r14), %rdi
movl $160, %edx
xorl %esi, %esi
callq hipMemset
addq $8, %r14
cmpq $40, %r14
jne .LBB3_3
# %bb.4:
movq 8(%rsp), %rdi
movl $40, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdi
callq puts@PLT
incq %r14
cmpq $5, %r14
jne .LBB3_5
# %bb.6: # %_Z8printArrPPci.exit
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.4, %edi
movl $1, %esi
movl $5, %edx
xorl %eax, %eax
callq printf
movabsq $21474836481, %rdi # imm = 0x500000001
movabsq $4294967336, %rdx # imm = 0x100000028
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $5, 4(%rsp)
movl $40, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10wordCount2PPcPPiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipGetLastError
testl %eax, %eax
je .LBB3_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB3_10: # %_Z8checkErrv.exit.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_11: # %_Z8checkErrv.exit
# =>This Inner Loop Header: Depth=1
movq (%r12,%r14,8), %rsi
movl $160, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
incq %r14
addq $160, %rbx
cmpq $5, %r14
jne .LBB3_11
# %bb.12:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 128(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_14: # Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $40, %r15
jne .LBB3_14
# %bb.15: # in Loop: Header=BB3_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $160, %rbx
cmpq $5, %r14
jne .LBB3_13
# %bb.16:
xorl %eax, %eax
addq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10wordCount2PPcPPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10wordCount2PPcPPiii,@object # @_Z10wordCount2PPcPPiii
.section .rodata,"a",@progbits
.globl _Z10wordCount2PPcPPiii
.p2align 3, 0x0
_Z10wordCount2PPcPPiii:
.quad _Z25__device_stub__wordCount2PPcPPiii
.size _Z10wordCount2PPcPPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error -- %s\n"
.size .L.str, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "good morning and I'm a good student!"
.size .L.str.2, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "grid.x = %d, grid.y=%d\n"
.size .L.str.4, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%4d"
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10wordCount2PPcPPiii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Occurrence array obtained from device:"
.size .Lstr.1, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__wordCount2PPcPPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10wordCount2PPcPPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10wordCount2PPcPPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1b00 */
/*0080*/ BSSY B0, 0x170 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fe20000011404 */
/*00b0*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*00c0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*00d0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0205 */
/*00e0*/ IADD3 R8, P0, R2, R11, RZ ; /* 0x0000000b02087210 */
/* 0x020fc80007f1e0ff */
/*00f0*/ LEA.HI.X.SX32 R9, R11, R3, 0x1, P0 ; /* 0x000000030b097211 */
/* 0x000fca00000f0eff */
/*0100*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1100 */
/*0110*/ IADD3 R6, R11, 0x1, RZ ; /* 0x000000010b067810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fc800078e000b */
/*0130*/ IMAD.MOV.U32 R11, RZ, RZ, R6 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0006 */
/*0140*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0150*/ @P0 BRA 0xe0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fcc00078e00ff */
/*0190*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1b00 */
/*01a0*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R10, P0, R8, R13, RZ ; /* 0x0000000d080a7210 */
/* 0x020fc80007f1e0ff */
/*01c0*/ LEA.HI.X.SX32 R11, R13, R9, 0x1, P0 ; /* 0x000000090d0b7211 */
/* 0x000fca00000f0eff */
/*01d0*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1100 */
/*01e0*/ IADD3 R6, R13, 0x1, RZ ; /* 0x000000010d067810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e000d */
/*0200*/ IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0006 */
/*0210*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0220*/ @P0 BRA 0x1b0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0230*/ ISETP.GT.AND P0, PT, R0, R15, PT ; /* 0x0000000f0000720c */
/* 0x000fe40003f04270 */
/*0240*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f26270 */
/*0250*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*0260*/ SHF.R.S32.HI R15, RZ, 0x1f, R0 ; /* 0x0000001fff0f7819 */
/* 0x000fe40000011400 */
/*0270*/ IADD3 R8, P0, R0, R2, RZ ; /* 0x0000000200087210 */
/* 0x000fca0007f1e0ff */
/*0280*/ IMAD.X R9, R3, 0x1, R15, P0 ; /* 0x0000000103097824 */
/* 0x000fca00000e060f */
/*0290*/ LDG.E.U8 R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea4000c1e1100 */
/*02a0*/ LOP3.LUT R2, R11, 0xdf, RZ, 0xc0, !PT ; /* 0x000000df0b027812 */
/* 0x004fc800078ec0ff */
/*02b0*/ IADD3 R2, R2, -0x41, RZ ; /* 0xffffffbf02027810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ LOP3.LUT R2, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02027812 */
/* 0x000fc800078ec0ff */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x1a, PT ; /* 0x0000001a0200780c */
/* 0x000fe40003f06070 */
/*02e0*/ LEA R2, P1, R4, c[0x0][0x168], 0x3 ; /* 0x00005a0004027a11 */
/* 0x000fe400078218ff */
/*02f0*/ ISETP.GT.OR P0, PT, R0, R5, !P0 ; /* 0x000000050000720c */
/* 0x000fe40004704670 */
/*0300*/ LEA.HI.X R3, R4, c[0x0][0x16c], R7, 0x3, P1 ; /* 0x00005b0004037a11 */
/* 0x000fd600008f1c07 */
/*0310*/ @!P0 LDG.E.64 R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ea4000c1e1b00 */
/*0320*/ @!P0 LEA R6, P1, R0, R6, 0x2 ; /* 0x0000000600068211 */
/* 0x004fc800078210ff */
/*0330*/ @!P0 LEA.HI.X R7, R0, R7, R15, 0x2, P1 ; /* 0x0000000700078211 */
/* 0x000fca00008f140f */
/*0340*/ @!P0 LDG.E R4, [R6.64] ; /* 0x0000000406048981 */
/* 0x000ea8000c1e1900 */
/*0350*/ STS.U8 [R0], R11 ; /* 0x0000000b00007388 */
/* 0x0001e20000000000 */
/*0360*/ @!P0 IADD3 R13, R4, 0x1, RZ ; /* 0x00000001040d8810 */
/* 0x004fca0007ffe0ff */
/*0370*/ @!P0 STG.E [R6.64], R13 ; /* 0x0000000d06008986 */
/* 0x0001e8000c101904 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*03a0*/ LEA R8, P0, R0, R8, 0x2 ; /* 0x0000000800087211 */
/* 0x004fc800078010ff */
/*03b0*/ LEA.HI.X R9, R0, R9, R15, 0x2, P0 ; /* 0x0000000900097211 */
/* 0x000fca00000f140f */
/*03c0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fc80003f05270 */
/*03e0*/ ISETP.GT.OR P0, PT, R0, R5, P0 ; /* 0x000000050000720c */
/* 0x000fda0000704670 */
/*03f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0400*/ STG.E [R8.64+0x4], RZ ; /* 0x000004ff08007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10wordCount2PPcPPiii
.globl _Z10wordCount2PPcPPiii
.p2align 8
.type _Z10wordCount2PPcPPiii,@function
_Z10wordCount2PPcPPiii:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s6, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
.LBB0_1:
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
flat_load_u8 v5, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v5
s_or_b32 s7, vcc_lo, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s7
s_load_b64 s[2:3], s[2:3], 0x0
s_mov_b64 s[4:5], 0
s_mov_b32 s7, 0
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s2, s4
s_addc_u32 s9, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
flat_load_u8 v5, v[5:6]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v5
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s7
s_load_b32 s2, s[0:1], 0x10
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s3, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s14, s3, v[0:1]
v_add_nc_u32_e32 v0, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v5, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s2, v1
s_or_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x8
v_add_nc_u32_e32 v0, -1, v7
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, v5, v0
v_cmpx_le_i32_e64 v5, v0
s_cbranch_execz .LBB0_8
v_add_co_u32 v3, s0, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, v4, v6, s0
flat_load_u8 v0, v[3:4]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v0, 0xdf, v0
v_add_nc_u16 v0, v0, 0xffa5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0xff, v0
v_cmp_gt_u16_e64 s0, 0xe6, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s2, v3
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
global_load_b64 v[3:4], v[3:4], off
s_waitcnt vmcnt(0)
v_add_co_u32 v3, s0, v3, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, v4, v8, s0
flat_load_b32 v0, v[3:4]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
flat_store_b32 v[3:4], v0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_xor_b32 s1, vcc_lo, -1
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, s3, v1, s0
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_add_co_u32 v0, s0, v0, v2
v_add_co_ci_u32_e64 v1, s0, v1, v3, s0
flat_load_b32 v2, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e64 s0, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v2, 0
flat_store_b32 v[0:1], v2 offset:4
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10wordCount2PPcPPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10wordCount2PPcPPiii, .Lfunc_end0-_Z10wordCount2PPcPPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10wordCount2PPcPPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10wordCount2PPcPPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019ba9a_00000000-6_lab8.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10gpu_strlenPc
.type _Z10gpu_strlenPc, @function
_Z10gpu_strlenPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10gpu_strlenPc, .-_Z10gpu_strlenPc
.globl _Z11gpu_isAlphac
.type _Z11gpu_isAlphac, @function
_Z11gpu_isAlphac:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11gpu_isAlphac, .-_Z11gpu_isAlphac
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error -- %s\n"
.text
.globl _Z8checkErrv
.type _Z8checkErrv, @function
_Z8checkErrv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L10
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L7
.cfi_endproc
.LFE2059:
.size _Z8checkErrv, .-_Z8checkErrv
.section .rodata.str1.1
.LC1:
.string "%s\n"
.text
.globl _Z8printArrPPci
.type _Z8printArrPPci, @function
_Z8printArrPPci:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L16
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r12
leaq .LC1(%rip), %rbp
.L13:
movq (%rbx), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L13
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2060:
.size _Z8printArrPPci, .-_Z8printArrPPci
.globl _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
.type _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii, @function
_Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10wordCount2PPcPPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii, .-_Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
.globl _Z10wordCount2PPcPPiii
.type _Z10wordCount2PPcPPiii, @function
_Z10wordCount2PPcPPiii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10wordCount2PPcPPiii, .-_Z10wordCount2PPcPPiii
.section .rodata.str1.1
.LC2:
.string "\n\n"
.LC3:
.string "grid.x = %d, grid.y=%d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Occurrence array obtained from device:\n"
.section .rodata.str1.1
.LC5:
.string "%4d"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $904, %rsp
.cfi_def_cfa_offset 960
movq %fs:40, %rax
movq %rax, 888(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %r13
leaq 240(%rsp), %rbx
leaq 1040(%rsp), %r15
movq %rbx, %rdx
.L28:
leaq -160(%rdx), %rax
.L29:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L29
addq $160, %rdx
cmpq %r15, %rdx
jne .L28
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movq %rax, 24(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, 8(%rsp)
call cudaDeviceReset@PLT
leaq 40(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movq %rbp, %r12
leaq 40(%rbp), %rax
movq %rax, (%rsp)
.L31:
movl $40, %esi
movq %r12, %rdi
call cudaMalloc@PLT
movl $1, %esi
movl $40, %edi
call calloc@PLT
movq %rax, %rbp
movq %rax, (%r14)
movabsq $8245929428630073191, %rax
movabsq $7236828443033102702, %rdx
movq %rax, 0(%rbp)
movq %rdx, 8(%rbp)
movabsq $7431046177059457312, %rax
movabsq $7238820013881454447, %rdx
movq %rax, 16(%rbp)
movq %rdx, 24(%rbp)
movabsq $9416691727758708, %rax
movq %rax, 29(%rbp)
movq %rbp, %rdi
call strlen@PLT
leaq 1(%rax), %rdx
movq (%r12), %rdi
movl $1, %ecx
movq %rbp, %rsi
call cudaMemcpy@PLT
addq $8, %r12
addq $8, %r14
movq (%rsp), %rax
cmpq %rax, %r12
jne .L31
movl $1, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rbp
movq %rbp, %r12
leaq 40(%rbp), %r14
.L32:
movl $160, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movq 0(%rbp), %rdi
movl $160, %edx
movl $0, %esi
call cudaMemset@PLT
addq $8, %rbp
cmpq %r14, %rbp
jne .L32
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, %esi
movq 16(%rsp), %rdi
call _Z8printArrPPci
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 64(%rsp)
movl $1, 76(%rsp)
movl $5, %ecx
movl $1, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 56(%rsp)
movl $5, 60(%rsp)
movl $40, 68(%rsp)
movl $1, 72(%rsp)
movl 76(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movq 56(%rsp), %rdi
movl 64(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L33:
call _Z8checkErrv
leaq 800(%r13), %rbp
.L34:
movq (%r12), %rsi
movl $2, %ecx
movl $160, %edx
movq %r13, %rdi
call cudaMemcpy@PLT
addq $8, %r12
addq $160, %r13
cmpq %rbp, %r13
jne .L34
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %r12
leaq .LC6(%rip), %r13
.L35:
leaq -160(%rbx), %rbp
.L36:
movl 0(%rbp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %rbx, %rbp
jne .L36
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $160, %rbx
cmpq %r15, %rbx
jne .L35
movq 888(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $904, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl $40, %ecx
movl $5, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z10wordCount2PPcPPiiiPPcPPiii
jmp .L33
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z10wordCount2PPcPPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z10wordCount2PPcPPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab8.hip"
.globl _Z25__device_stub__wordCount2PPcPPiii # -- Begin function _Z25__device_stub__wordCount2PPcPPiii
.p2align 4, 0x90
.type _Z25__device_stub__wordCount2PPcPPiii,@function
_Z25__device_stub__wordCount2PPcPPiii: # @_Z25__device_stub__wordCount2PPcPPiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10wordCount2PPcPPiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__wordCount2PPcPPiii, .Lfunc_end0-_Z25__device_stub__wordCount2PPcPPiii
.cfi_endproc
# -- End function
.globl _Z8checkErrv # -- Begin function _Z8checkErrv
.p2align 4, 0x90
.type _Z8checkErrv,@function
_Z8checkErrv: # @_Z8checkErrv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
je .LBB1_1
# %bb.2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8checkErrv, .Lfunc_end1-_Z8checkErrv
.cfi_endproc
# -- End function
.globl _Z8printArrPPci # -- Begin function _Z8printArrPPci
.p2align 4, 0x90
.type _Z8printArrPPci,@function
_Z8printArrPPci: # @_Z8printArrPPci
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r15,8), %rdi
callq puts@PLT
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z8printArrPPci, .Lfunc_end2-_Z8printArrPPci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 992
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 128(%rsp), %rbx
xorl %r14d, %r14d
movl $800, %edx # imm = 0x320
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $40, %edi
callq malloc
movq %rax, %r15
movl $40, %edi
callq malloc
movq %rax, %r12
movl $40, %edi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
callq hipDeviceReset
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq (%r12,%r14), %rdi
movl $40, %esi
callq hipMalloc
movl $40, %edi
movl $1, %esi
callq calloc
movq %rax, %r13
movq %rax, (%r15,%r14)
movups .L.str.2(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.2+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movabsq $9416691727758708, %rax # imm = 0x21746E65647574
movq %rax, 29(%r13)
movq (%r12,%r14), %rbp
movq %r13, %rdi
callq strlen
leaq 1(%rax), %rdx
movq %rbp, %rdi
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
addq $8, %r14
cmpq $40, %r14
jne .LBB3_1
# %bb.2:
movq 16(%rsp), %rdi
movl $40, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq 24(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
leaq (%r12,%r14), %rdi
movl $160, %esi
callq hipMalloc
movq (%r12,%r14), %rdi
movl $160, %edx
xorl %esi, %esi
callq hipMemset
addq $8, %r14
cmpq $40, %r14
jne .LBB3_3
# %bb.4:
movq 8(%rsp), %rdi
movl $40, %edx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdi
callq puts@PLT
incq %r14
cmpq $5, %r14
jne .LBB3_5
# %bb.6: # %_Z8printArrPPci.exit
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.4, %edi
movl $1, %esi
movl $5, %edx
xorl %eax, %eax
callq printf
movabsq $21474836481, %rdi # imm = 0x500000001
movabsq $4294967336, %rdx # imm = 0x100000028
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $5, 4(%rsp)
movl $40, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10wordCount2PPcPPiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipGetLastError
testl %eax, %eax
je .LBB3_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB3_10: # %_Z8checkErrv.exit.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_11: # %_Z8checkErrv.exit
# =>This Inner Loop Header: Depth=1
movq (%r12,%r14,8), %rsi
movl $160, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
incq %r14
addq $160, %rbx
cmpq $5, %r14
jne .LBB3_11
# %bb.12:
movl $.Lstr.1, %edi
callq puts@PLT
leaq 128(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_14: # Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $40, %r15
jne .LBB3_14
# %bb.15: # in Loop: Header=BB3_13 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $160, %rbx
cmpq $5, %r14
jne .LBB3_13
# %bb.16:
xorl %eax, %eax
addq $936, %rsp # imm = 0x3A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10wordCount2PPcPPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10wordCount2PPcPPiii,@object # @_Z10wordCount2PPcPPiii
.section .rodata,"a",@progbits
.globl _Z10wordCount2PPcPPiii
.p2align 3, 0x0
_Z10wordCount2PPcPPiii:
.quad _Z25__device_stub__wordCount2PPcPPiii
.size _Z10wordCount2PPcPPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error -- %s\n"
.size .L.str, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "good morning and I'm a good student!"
.size .L.str.2, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "grid.x = %d, grid.y=%d\n"
.size .L.str.4, 24
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%4d"
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10wordCount2PPcPPiii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Occurrence array obtained from device:"
.size .Lstr.1, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__wordCount2PPcPPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10wordCount2PPcPPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ void mul(double a, double b, double *res)
{
*res = a * b;
// NaN
*res = (*res)-(*res) / (*res)-(*res);
}
__global__ void dot_prod(double *x, double *y, int size)
{
double d;
for (int i=0; i < size; ++i)
{
double tmp;
mul(x[i], y[i], &tmp);
d += tmp;
}
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
printf("dot: %f\n", d);
}
} | code for sm_80
Function : _Z8dot_prodPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff187624 */
/* 0x000fe200078e00ff */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ ISETP.GE.AND P0, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 BRA 0xb30 ; /* 0x00000ae000008947 */
/* 0x000fea0003800000 */
/*0050*/ IADD3 R0, R24.reuse, -0x1, RZ ; /* 0xffffffff18007810 */
/* 0x040fe20007ffe0ff */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0070*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe200078ec0ff */
/*0080*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*00a0*/ @!P0 BRA 0x850 ; /* 0x000007a000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R31, -R24, c[0x0][0x170], RZ ; /* 0x00005c00181f7a10 */
/* 0x000fe20007ffe1ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fe200078e00ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe400078e00ff */
/*0110*/ LDG.E.64 R28, [R6.64] ; /* 0x0000000c061c7981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000c04087981 */
/* 0x000ea4000c1e1b00 */
/*0130*/ DMUL R28, R28, R8 ; /* 0x000000081c1c7228 */
/* 0x0040440000000000 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x001fc800078e00ff */
/*0150*/ MUFU.RCP64H R9, R29 ; /* 0x0000001d00097308 */
/* 0x002e280000001800 */
/*0160*/ FSETP.GEU.AND P1, PT, |R29|, 6.5827683646048100446e-37, PT ; /* 0x036000001d00780b */
/* 0x000fe20003f2e200 */
/*0170*/ DFMA R10, -R28, R8, 1 ; /* 0x3ff000001c0a742b */
/* 0x001e0c0000000108 */
/*0180*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0190*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*01a0*/ DFMA R8, -R28, R10, 1 ; /* 0x3ff000001c08742b */
/* 0x001e0c000000010a */
/*01b0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*01c0*/ DMUL R10, R28, R8 ; /* 0x000000081c0a7228 */
/* 0x001e0c0000000000 */
/*01d0*/ DFMA R12, -R28, R10, R28 ; /* 0x0000000a1c0c722b */
/* 0x001e0c000000011c */
/*01e0*/ DFMA R10, R8, R12, R10 ; /* 0x0000000c080a722b */
/* 0x001e14000000000a */
/*01f0*/ FFMA R0, RZ, R29, R11 ; /* 0x0000001dff007223 */
/* 0x001fca000000000b */
/*0200*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0210*/ @P0 BRA P1, 0x280 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0220*/ IMAD.MOV.U32 R12, RZ, RZ, R28.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e001c */
/*0230*/ MOV R0, 0x280 ; /* 0x0000028000007802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R13, RZ, RZ, R29.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e001d */
/*0250*/ IMAD.MOV.U32 R10, RZ, RZ, R28 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e001c */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, R29 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e001d */
/*0270*/ CALL.REL.NOINC 0xca0 ; /* 0x00000a2000007944 */
/* 0x000fea0003c00000 */
/*0280*/ LDG.E.64 R22, [R6.64+0x8] ; /* 0x0000080c06167981 */
/* 0x000ea8000c1e1b00 */
/*0290*/ LDG.E.64 R8, [R4.64+0x8] ; /* 0x0000080c04087981 */
/* 0x000ea2000c1e1b00 */
/*02a0*/ DADD R10, R28, -R10 ; /* 0x000000001c0a7229 */
/* 0x000e0c000000080a */
/*02b0*/ DADD R28, -R28, R10 ; /* 0x000000001c1c7229 */
/* 0x001e0c000000010a */
/*02c0*/ DADD R28, R28, R2 ; /* 0x000000001c1c7229 */
/* 0x001fc80000000002 */
/*02d0*/ DMUL R22, R22, R8 ; /* 0x0000000816167228 */
/* 0x0040640000000000 */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x001fc800078e00ff */
/*02f0*/ MUFU.RCP64H R9, R23 ; /* 0x0000001700097308 */
/* 0x002e280000001800 */
/*0300*/ FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; /* 0x036000001700780b */
/* 0x000fe20003f2e200 */
/*0310*/ DFMA R12, -R22, R8, 1 ; /* 0x3ff00000160c742b */
/* 0x001e0c0000000108 */
/*0320*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0330*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*0340*/ DFMA R8, -R22, R12, 1 ; /* 0x3ff000001608742b */
/* 0x001e0c000000010c */
/*0350*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x001e0c000000000c */
/*0360*/ DMUL R12, R22, R8 ; /* 0x00000008160c7228 */
/* 0x001e0c0000000000 */
/*0370*/ DFMA R14, -R22, R12, R22 ; /* 0x0000000c160e722b */
/* 0x001e0c0000000116 */
/*0380*/ DFMA R8, R8, R14, R12 ; /* 0x0000000e0808722b */
/* 0x001e14000000000c */
/*0390*/ FFMA R0, RZ, R23, R9 ; /* 0x00000017ff007223 */
/* 0x001fca0000000009 */
/*03a0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*03b0*/ @P0 BRA P1, 0x440 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*03c0*/ IMAD.MOV.U32 R12, RZ, RZ, R22.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0016 */
/*03d0*/ MOV R0, 0x420 ; /* 0x0000042000007802 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R13, RZ, RZ, R23.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e0017 */
/*03f0*/ IMAD.MOV.U32 R10, RZ, RZ, R22 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0016 */
/*0400*/ IMAD.MOV.U32 R11, RZ, RZ, R23 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0017 */
/*0410*/ CALL.REL.NOINC 0xca0 ; /* 0x0000088000007944 */
/* 0x000fea0003c00000 */
/*0420*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000b */
/*0440*/ LDG.E.64 R2, [R6.64+0x10] ; /* 0x0000100c06027981 */
/* 0x000ea8000c1e1b00 */
/*0450*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x0000100c040a7981 */
/* 0x000ea2000c1e1b00 */
/*0460*/ DADD R8, R22, -R8 ; /* 0x0000000016087229 */
/* 0x000e0c0000000808 */
/*0470*/ DADD R8, -R22, R8 ; /* 0x0000000016087229 */
/* 0x001e0c0000000108 */
/*0480*/ DADD R28, R28, R8 ; /* 0x000000001c1c7229 */
/* 0x001fc80000000008 */
/*0490*/ DMUL R2, R2, R10 ; /* 0x0000000a02027228 */
/* 0x0040640000000000 */
/*04a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x001fc800078e00ff */
/*04b0*/ MUFU.RCP64H R11, R3 ; /* 0x00000003000b7308 */
/* 0x002e280000001800 */
/*04c0*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fe20003f2e200 */
/*04d0*/ DFMA R12, -R2, R10, 1 ; /* 0x3ff00000020c742b */
/* 0x001e0c000000010a */
/*04e0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*04f0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0500*/ DFMA R10, -R2, R12, 1 ; /* 0x3ff00000020a742b */
/* 0x001e0c000000010c */
/*0510*/ DFMA R10, R12, R10, R12 ; /* 0x0000000a0c0a722b */
/* 0x001e0c000000000c */
/*0520*/ DMUL R12, R2, R10 ; /* 0x0000000a020c7228 */
/* 0x001e0c0000000000 */
/*0530*/ DFMA R14, -R2, R12, R2 ; /* 0x0000000c020e722b */
/* 0x001e0c0000000102 */
/*0540*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001e14000000000c */
/*0550*/ FFMA R0, RZ, R3, R11 ; /* 0x00000003ff007223 */
/* 0x001fca000000000b */
/*0560*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0570*/ @P0 BRA P1, 0x5e0 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0580*/ IMAD.MOV.U32 R12, RZ, RZ, R2.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0002 */
/*0590*/ MOV R0, 0x5e0 ; /* 0x000005e000007802 */
/* 0x000fe20000000f00 */
/*05a0*/ IMAD.MOV.U32 R13, RZ, RZ, R3.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e0003 */
/*05b0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*05c0*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*05d0*/ CALL.REL.NOINC 0xca0 ; /* 0x000006c000007944 */
/* 0x000fea0003c00000 */
/*05e0*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180c06167981 */
/* 0x000ea8000c1e1b00 */
/*05f0*/ LDG.E.64 R8, [R4.64+0x18] ; /* 0x0000180c04087981 */
/* 0x000ea2000c1e1b00 */
/*0600*/ DADD R10, R2, -R10 ; /* 0x00000000020a7229 */
/* 0x000e0c000000080a */
/*0610*/ DADD R10, -R2, R10 ; /* 0x00000000020a7229 */
/* 0x001e0c000000010a */
/*0620*/ DADD R28, R28, R10 ; /* 0x000000001c1c7229 */
/* 0x001fc8000000000a */
/*0630*/ DMUL R22, R22, R8 ; /* 0x0000000816167228 */
/* 0x0040640000000000 */
/*0640*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x001fc800078e00ff */
/*0650*/ MUFU.RCP64H R9, R23 ; /* 0x0000001700097308 */
/* 0x002e280000001800 */
/*0660*/ FSETP.GEU.AND P1, PT, |R23|, 6.5827683646048100446e-37, PT ; /* 0x036000001700780b */
/* 0x000fe20003f2e200 */
/*0670*/ DFMA R12, -R22, R8, 1 ; /* 0x3ff00000160c742b */
/* 0x001e0c0000000108 */
/*0680*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0690*/ DFMA R12, R8, R12, R8 ; /* 0x0000000c080c722b */
/* 0x001e0c0000000008 */
/*06a0*/ DFMA R8, -R22, R12, 1 ; /* 0x3ff000001608742b */
/* 0x001e0c000000010c */
/*06b0*/ DFMA R8, R12, R8, R12 ; /* 0x000000080c08722b */
/* 0x001e0c000000000c */
/*06c0*/ DMUL R12, R22, R8 ; /* 0x00000008160c7228 */
/* 0x001e0c0000000000 */
/*06d0*/ DFMA R14, -R22, R12, R22 ; /* 0x0000000c160e722b */
/* 0x001e0c0000000116 */
/*06e0*/ DFMA R8, R8, R14, R12 ; /* 0x0000000e0808722b */
/* 0x001e14000000000c */
/*06f0*/ FFMA R0, RZ, R23, R9 ; /* 0x00000017ff007223 */
/* 0x001fca0000000009 */
/*0700*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0710*/ @P0 BRA P1, 0x7a0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0720*/ IMAD.MOV.U32 R12, RZ, RZ, R22.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0016 */
/*0730*/ MOV R0, 0x780 ; /* 0x0000078000007802 */
/* 0x000fe20000000f00 */
/*0740*/ IMAD.MOV.U32 R13, RZ, RZ, R23.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e0017 */
/*0750*/ IMAD.MOV.U32 R10, RZ, RZ, R22 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0016 */
/*0760*/ IMAD.MOV.U32 R11, RZ, RZ, R23 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0017 */
/*0770*/ CALL.REL.NOINC 0xca0 ; /* 0x0000052000007944 */
/* 0x000fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000a */
/*0790*/ IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000b */
/*07a0*/ IADD3 R31, R31, -0x4, RZ ; /* 0xfffffffc1f1f7810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ DADD R8, R22, -R8 ; /* 0x0000000016087229 */
/* 0x000e220000000808 */
/*07c0*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fe20007f3e0ff */
/*07d0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*07e0*/ ISETP.NE.AND P0, PT, R31, RZ, PT ; /* 0x000000ff1f00720c */
/* 0x000fc40003f05270 */
/*07f0*/ IADD3 R6, P2, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fe20007f5e0ff */
/*0800*/ DADD R8, -R22, R8 ; /* 0x0000000016087229 */
/* 0x001e220000000108 */
/*0810*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc600008e0605 */
/*0820*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0830*/ DADD R2, R28, R8 ; /* 0x000000001c027229 */
/* 0x0010480000000008 */
/*0840*/ @P0 BRA 0x110 ; /* 0xfffff8c000000947 */
/* 0x003fea000383ffff */
/*0850*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fda0003f05270 */
/*0860*/ @!P0 BRA 0xb30 ; /* 0x000002c000008947 */
/* 0x000fea0003800000 */
/*0870*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0880*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0890*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*08a0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*08b0*/ UIMAD.WIDE UR8, UR4, UR5, UR8 ; /* 0x00000005040872a5 */
/* 0x000fc8000f8e0208 */
/*08c0*/ IMAD.U32 R10, RZ, RZ, UR6 ; /* 0x00000006ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*08d0*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fc4000f8e00ff */
/*08e0*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fe4000f8e00ff */
/*08f0*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*0900*/ LDG.E.64 R4, [R10.64] ; /* 0x0000000c0a047981 */
/* 0x000ea8000c1e1b00 */
/*0910*/ LDG.E.64 R6, [R12.64] ; /* 0x0000000c0c067981 */
/* 0x000ea4000c1e1b00 */
/*0920*/ DMUL R4, R4, R6 ; /* 0x0000000604047228 */
/* 0x0040640000000000 */
/*0930*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x001fc800078e00ff */
/*0940*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e280000001800 */
/*0950*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fe20003f2e200 */
/*0960*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0970*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0980*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0990*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*09a0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*09b0*/ DMUL R8, R4, R6 ; /* 0x0000000604087228 */
/* 0x001e0c0000000000 */
/*09c0*/ DFMA R10, -R4, R8, R4 ; /* 0x00000008040a722b */
/* 0x001e0c0000000104 */
/*09d0*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x001e140000000008 */
/*09e0*/ FFMA R0, RZ, R5, R7 ; /* 0x00000005ff007223 */
/* 0x001fca0000000007 */
/*09f0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0a00*/ @P0 BRA P1, 0xa90 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0a10*/ IMAD.MOV.U32 R12, RZ, RZ, R4.reuse ; /* 0x000000ffff0c7224 */
/* 0x100fe200078e0004 */
/*0a20*/ MOV R0, 0xa70 ; /* 0x00000a7000007802 */
/* 0x000fe20000000f00 */
/*0a30*/ IMAD.MOV.U32 R13, RZ, RZ, R5.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e0005 */
/*0a40*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0a50*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0005 */
/*0a60*/ CALL.REL.NOINC 0xca0 ; /* 0x0000023000007944 */
/* 0x000fea0003c00000 */
/*0a70*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0a80*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000b */
/*0a90*/ IADD3 R24, R24, -0x1, RZ ; /* 0xffffffff18187810 */
/* 0x000fe20007ffe0ff */
/*0aa0*/ DADD R6, R4, -R6 ; /* 0x0000000004067229 */
/* 0x000e220000000806 */
/*0ab0*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fc4000ff1e03f */
/*0ac0*/ ISETP.NE.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f05270 */
/*0ad0*/ UIADD3 UR8, UP1, UR8, 0x8, URZ ; /* 0x0000000808087890 */
/* 0x000fe4000ff3e03f */
/*0ae0*/ DADD R6, -R4, R6 ; /* 0x0000000004067229 */
/* 0x001e220000000106 */
/*0af0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0b00*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fc60008ffe43f */
/*0b10*/ DADD R2, R6, R2 ; /* 0x0000000006027229 */
/* 0x0010480000000002 */
/*0b20*/ @P0 BRA 0x8c0 ; /* 0xfffffd9000000947 */
/* 0x003fea000383ffff */
/*0b30*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0b40*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0b50*/ ULDC UR10, c[0x0][0x0] ; /* 0x00000000000a7ab9 */
/* 0x000fe20000000800 */
/*0b60*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0b70*/ UIMAD UR5, UR5, UR10, URZ ; /* 0x0000000a050572a4 */
/* 0x001fe2000f8e023f */
/*0b80*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0b90*/ ISETP.NE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf05270 */
/*0ba0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0bb0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0bc0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100a00 */
/*0bd0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0be0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0bf0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0c00*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fca00078e00ff */
/*0c10*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0c20*/ MOV R11, 0xc90 ; /* 0x00000c90000b7802 */
/* 0x000fe40000000f00 */
/*0c30*/ MOV R20, 0xc10 ; /* 0x00000c1000147802 */
/* 0x000fc40000000f00 */
/*0c40*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0c50*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0c60*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0c70*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0c80*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0c90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ca0*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*0cb0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0cc0*/ LOP3.LUT R8, R11.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b087812 */
/* 0x040fe200078ec0ff */
/*0cd0*/ IMAD.MOV.U32 R27, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff1b7424 */
/* 0x000fe200078e00ff */
/*0ce0*/ LOP3.LUT R25, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b197812 */
/* 0x000fe400078ec0ff */
/*0cf0*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*0d00*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*0d10*/ LOP3.LUT R26, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d1a7812 */
/* 0x000fc800078ec0ff */
/*0d20*/ ISETP.GE.U32.AND P1, PT, R26, R25, PT ; /* 0x000000191a00720c */
/* 0x000fe20003f26070 */
/*0d30*/ @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a088828 */
/* 0x000e220000000000 */
/*0d40*/ IMAD.MOV.U32 R30, RZ, RZ, R26 ; /* 0x000000ffff1e7224 */
/* 0x000fca00078e001a */
/*0d50*/ MUFU.RCP64H R17, R9 ; /* 0x0000000900117308 */
/* 0x001e240000001800 */
/*0d60*/ DFMA R14, R16, -R8, 1 ; /* 0x3ff00000100e742b */
/* 0x001e0c0000000808 */
/*0d70*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0d80*/ DFMA R16, R16, R14, R16 ; /* 0x0000000e1010722b */
/* 0x0010640000000010 */
/*0d90*/ SEL R15, R27, 0x63400000, !P1 ; /* 0x634000001b0f7807 */
/* 0x001fe20004800000 */
/*0da0*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0db0*/ FSETP.GEU.AND P1, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x000fe40003f2e200 */
/*0dc0*/ DFMA R18, R16, -R8, 1 ; /* 0x3ff000001012742b */
/* 0x002e220000000808 */
/*0dd0*/ LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fca00078ef80d */
/*0de0*/ DFMA R16, R16, R18, R16 ; /* 0x000000121010722b */
/* 0x00104a0000000010 */
/*0df0*/ @P1 BRA 0xe80 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0e00*/ LOP3.LUT R19, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b137812 */
/* 0x003fe200078ec0ff */
/*0e10*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0e20*/ ISETP.GE.U32.AND P1, PT, R26, R19, PT ; /* 0x000000131a00720c */
/* 0x000fc80003f26070 */
/*0e30*/ SEL R19, R27, 0x63400000, !P1 ; /* 0x634000001b137807 */
/* 0x000fc80004800000 */
/*0e40*/ LOP3.LUT R19, R19, 0x80000000, R13, 0xf8, !PT ; /* 0x8000000013137812 */
/* 0x000fc800078ef80d */
/*0e50*/ LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000013137812 */
/* 0x000fcc00078efcff */
/*0e60*/ DFMA R14, R14, 2, -R18 ; /* 0x400000000e0e782b */
/* 0x000e140000000812 */
/*0e70*/ LOP3.LUT R30, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f1e7812 */
/* 0x001fe400078ec0ff */
/*0e80*/ DMUL R18, R16, R14 ; /* 0x0000000e10127228 */
/* 0x003e220000000000 */
/*0e90*/ @!P0 LOP3.LUT R25, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009198812 */
/* 0x000fca00078ec0ff */
/*0ea0*/ DFMA R20, R18, -R8, R14 ; /* 0x800000081214722b */
/* 0x001e0c000000000e */
/*0eb0*/ DFMA R20, R16, R20, R18 ; /* 0x000000141014722b */
/* 0x0010640000000012 */
/*0ec0*/ IADD3 R16, R30, -0x1, RZ ; /* 0xffffffff1e107810 */
/* 0x001fc80007ffe0ff */
/*0ed0*/ ISETP.GT.U32.AND P0, PT, R16, 0x7feffffe, PT ; /* 0x7feffffe1000780c */
/* 0x000fe40003f04070 */
/*0ee0*/ IADD3 R16, R25, -0x1, RZ ; /* 0xffffffff19107810 */
/* 0x000fc80007ffe0ff */
/*0ef0*/ ISETP.GT.U32.OR P0, PT, R16, 0x7feffffe, P0 ; /* 0x7feffffe1000780c */
/* 0x000fda0000704470 */
/*0f00*/ @P0 BRA 0x10d0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0f10*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x002fe200078ec0ff */
/*0f20*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0f30*/ ISETP.GE.U32.AND P0, PT, R26.reuse, R13, PT ; /* 0x0000000d1a00720c */
/* 0x040fe20003f06070 */
/*0f40*/ IMAD.IADD R12, R26, 0x1, -R13 ; /* 0x000000011a0c7824 */
/* 0x000fc600078e0a0d */
/*0f50*/ SEL R27, R27, 0x63400000, !P0 ; /* 0x634000001b1b7807 */
/* 0x000fe40004000000 */
/*0f60*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*0f70*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0f80*/ IMAD.IADD R12, R12, 0x1, -R27 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0a1b */
/*0f90*/ IADD3 R19, R12, 0x7fe00000, RZ ; /* 0x7fe000000c137810 */
/* 0x000fcc0007ffe0ff */
/*0fa0*/ DMUL R16, R20, R18 ; /* 0x0000001214107228 */
/* 0x000e140000000000 */
/*0fb0*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*0fc0*/ @P0 BRA 0x1220 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0fd0*/ DFMA R8, R20, -R8, R14 ; /* 0x800000081408722b */
/* 0x000e22000000000e */
/*0fe0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fd200078e00ff */
/*0ff0*/ FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720b */
/* 0x041fe40003f0d000 */
/*1000*/ LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fc800078e480b */
/*1010*/ LOP3.LUT R19, R11, R19, RZ, 0xfc, !PT ; /* 0x000000130b137212 */
/* 0x000fce00078efcff */
/*1020*/ @!P0 BRA 0x1220 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*1030*/ IMAD.MOV R9, RZ, RZ, -R12 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0c */
/*1040*/ DMUL.RP R18, R20, R18 ; /* 0x0000001214127228 */
/* 0x000e220000008000 */
/*1050*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*1060*/ DFMA R8, R16, -R8, R20 ; /* 0x800000081008722b */
/* 0x000e460000000014 */
/*1070*/ LOP3.LUT R11, R19, R11, RZ, 0x3c, !PT ; /* 0x0000000b130b7212 */
/* 0x001fc600078e3cff */
/*1080*/ IADD3 R8, -R12, -0x43300000, RZ ; /* 0xbcd000000c087810 */
/* 0x002fc80007ffe1ff */
/*1090*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*10a0*/ FSEL R16, R18, R16, !P0 ; /* 0x0000001012107208 */
/* 0x000fe40004000000 */
/*10b0*/ FSEL R17, R11, R17, !P0 ; /* 0x000000110b117208 */
/* 0x000fe20004000000 */
/*10c0*/ BRA 0x1220 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*10d0*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x002e1c0003f08000 */
/*10e0*/ @P0 BRA 0x1200 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*10f0*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e1c0003f08000 */
/*1100*/ @P0 BRA 0x11d0 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*1110*/ ISETP.NE.AND P0, PT, R30, R25, PT ; /* 0x000000191e00720c */
/* 0x000fe20003f05270 */
/*1120*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*1130*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*1140*/ @!P0 BRA 0x1220 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1150*/ ISETP.NE.AND P0, PT, R30, 0x7ff00000, PT ; /* 0x7ff000001e00780c */
/* 0x000fe40003f05270 */
/*1160*/ LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ; /* 0x800000000d117812 */
/* 0x000fe400078e480b */
/*1170*/ ISETP.EQ.OR P0, PT, R25, RZ, !P0 ; /* 0x000000ff1900720c */
/* 0x000fda0004702670 */
/*1180*/ @P0 LOP3.LUT R8, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011080812 */
/* 0x000fe200078efcff */
/*1190*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*11a0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*11b0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R8 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0008 */
/*11c0*/ BRA 0x1220 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*11d0*/ LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b117812 */
/* 0x000fe200078efcff */
/*11e0*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*11f0*/ BRA 0x1220 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1200*/ LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d117812 */
/* 0x000fe200078efcff */
/*1210*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*1220*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*1230*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc400078e00ff */
/*1240*/ IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0010 */
/*1250*/ IMAD.MOV.U32 R11, RZ, RZ, R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0011 */
/*1260*/ RET.REL.NODEC R8 0x0 ; /* 0xffffed9008007950 */
/* 0x000fec0003c3ffff */
/*1270*/ BRA 0x1270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ void mul(double a, double b, double *res)
{
*res = a * b;
// NaN
*res = (*res)-(*res) / (*res)-(*res);
}
__global__ void dot_prod(double *x, double *y, int size)
{
double d;
for (int i=0; i < size; ++i)
{
double tmp;
mul(x[i], y[i], &tmp);
d += tmp;
}
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
printf("dot: %f\n", d);
}
} | .file "tmpxft_00131be1_00000000-6_dot_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3mulddPd
.type _Z3mulddPd, @function
_Z3mulddPd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z3mulddPd, .-_Z3mulddPd
.globl _Z30__device_stub__Z8dot_prodPdS_iPdS_i
.type _Z30__device_stub__Z8dot_prodPdS_iPdS_i, @function
_Z30__device_stub__Z8dot_prodPdS_iPdS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dot_prodPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8dot_prodPdS_iPdS_i, .-_Z30__device_stub__Z8dot_prodPdS_iPdS_i
.globl _Z8dot_prodPdS_i
.type _Z8dot_prodPdS_i, @function
_Z8dot_prodPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8dot_prodPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8dot_prodPdS_i, .-_Z8dot_prodPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8dot_prodPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dot_prodPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ void mul(double a, double b, double *res)
{
*res = a * b;
// NaN
*res = (*res)-(*res) / (*res)-(*res);
}
__global__ void dot_prod(double *x, double *y, int size)
{
double d;
for (int i=0; i < size; ++i)
{
double tmp;
mul(x[i], y[i], &tmp);
d += tmp;
}
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
printf("dot: %f\n", d);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void mul(double a, double b, double *res)
{
*res = a * b;
// NaN
*res = (*res)-(*res) / (*res)-(*res);
}
__global__ void dot_prod(double *x, double *y, int size)
{
double d;
for (int i=0; i < size; ++i)
{
double tmp;
mul(x[i], y[i], &tmp);
d += tmp;
}
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
printf("dot: %f\n", d);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void mul(double a, double b, double *res)
{
*res = a * b;
// NaN
*res = (*res)-(*res) / (*res)-(*res);
}
__global__ void dot_prod(double *x, double *y, int size)
{
double d;
for (int i=0; i < size; ++i)
{
double tmp;
mul(x[i], y[i], &tmp);
d += tmp;
}
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
printf("dot: %f\n", d);
}
} | .text
.file "dot_product.hip"
.globl _Z23__device_stub__dot_prodPdS_i # -- Begin function _Z23__device_stub__dot_prodPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__dot_prodPdS_i,@function
_Z23__device_stub__dot_prodPdS_i: # @_Z23__device_stub__dot_prodPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8dot_prodPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__dot_prodPdS_i, .Lfunc_end0-_Z23__device_stub__dot_prodPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dot_prodPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dot_prodPdS_i,@object # @_Z8dot_prodPdS_i
.section .rodata,"a",@progbits
.globl _Z8dot_prodPdS_i
.p2align 3, 0x0
_Z8dot_prodPdS_i:
.quad _Z23__device_stub__dot_prodPdS_i
.size _Z8dot_prodPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8dot_prodPdS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dot_prodPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8dot_prodPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00131be1_00000000-6_dot_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3mulddPd
.type _Z3mulddPd, @function
_Z3mulddPd:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z3mulddPd, .-_Z3mulddPd
.globl _Z30__device_stub__Z8dot_prodPdS_iPdS_i
.type _Z30__device_stub__Z8dot_prodPdS_iPdS_i, @function
_Z30__device_stub__Z8dot_prodPdS_iPdS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8dot_prodPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z8dot_prodPdS_iPdS_i, .-_Z30__device_stub__Z8dot_prodPdS_iPdS_i
.globl _Z8dot_prodPdS_i
.type _Z8dot_prodPdS_i, @function
_Z8dot_prodPdS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8dot_prodPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8dot_prodPdS_i, .-_Z8dot_prodPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8dot_prodPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8dot_prodPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dot_product.hip"
.globl _Z23__device_stub__dot_prodPdS_i # -- Begin function _Z23__device_stub__dot_prodPdS_i
.p2align 4, 0x90
.type _Z23__device_stub__dot_prodPdS_i,@function
_Z23__device_stub__dot_prodPdS_i: # @_Z23__device_stub__dot_prodPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8dot_prodPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__dot_prodPdS_i, .Lfunc_end0-_Z23__device_stub__dot_prodPdS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8dot_prodPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8dot_prodPdS_i,@object # @_Z8dot_prodPdS_i
.section .rodata,"a",@progbits
.globl _Z8dot_prodPdS_i
.p2align 3, 0x0
_Z8dot_prodPdS_i:
.quad _Z23__device_stub__dot_prodPdS_i
.size _Z8dot_prodPdS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8dot_prodPdS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__dot_prodPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8dot_prodPdS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
const double pi = 3.14159265358979323846264;
const double L = 550;
const double Diff = 1.;
const int MAX_BLOCK_WIDTH = 32;
// In this method, we use squre cells of threads, but we need to specify the size of the square.
/*
| coordinate system:
-|---------------y
| x = i * d_x
| y = i * d_x
|
x
*/
inline double left(double y) { return 0; }
inline double right(double y) { return 0; }
inline double bottom(double x) { return 0; }
inline double top(double x){ return sinh(pi)*sin(x*pi/L); }
inline double analytical(double x,double y){
return sinh(y*pi/L)*sin(x*pi/L);
}
__global__ void oneIteration(int N, int cell_size, double *cur, double *old, double delta_x,double delta_t){
// Run one step of iteration with multiple blocks of threads
int b_size = blockDim.x, b_id = blockIdx.x, t_id = threadIdx.x, in_cell = cell_size - 2;
int n_cell = (N + in_cell -2)/in_cell;
assert(N > 1);
assert(cell_size <= MAX_BLOCK_WIDTH);
assert(b_size == cell_size*cell_size); // Here we only use square cells
__shared__ double tmp_arr[MAX_BLOCK_WIDTH][MAX_BLOCK_WIDTH]; // Define a buffer in the shared memory of one block of threads
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
// Compute indices in the cell and in the original matrix
int local_i = t_id/cell_size, local_j = t_id%cell_size;
int global_i = (b_id/n_cell)*in_cell + local_i, global_j = (b_id%n_cell)*in_cell + local_j;
// Copy the old data into the buffer array, then synchronize threads
if(global_i>=0 && global_i<=N && global_j>=0 && global_j<=N){
tmp_arr[local_i][local_j] = old[global_i*(N+1) + global_j];
// Maintain the Dirichlet Type Boundary Conditions.
if(!global_i || !global_j || global_i==N || global_j==N) cur[global_i*(N+1)+global_j] = tmp_arr[local_i][local_j];
}
__syncthreads();
// Compute the updated value and store it into *cur
if(local_i && local_i<cell_size-1 && local_j && local_j<cell_size-1 && global_i && global_i<N && global_j && global_j<N){
double nn_diff = 0.;
for(int k=0;k<8;++k) nn_diff += tmp_arr[local_i+dX[k]][local_j+dY[k]];
nn_diff -= 8.*tmp_arr[local_i][local_j];
cur[global_i*(N+1) + global_j] = tmp_arr[local_i][local_j] + Diff*delta_t*nn_diff/3./pow(delta_x, 2.);
}
return;
}
__global__ void iterationWithOneBlock(int N,int N_step, int nx_thread, double *cur, double *tmp, double delta_x, double delta_t){
// Run multiple steps of iterations with one block of threads
int t_id = threadIdx.x, b_size = blockDim.x, t_width = (N-2+nx_thread)/nx_thread;
assert(b_size == nx_thread*nx_thread);
// Define neighbor vectors:
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
int global_i = (t_id/nx_thread)*t_width, globel_j = (t_id%nx_thread)*t_width;
for(int step=0;step<N_step;++step){
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N){
double nn_sum = 0., coeff = Diff*delta_t/3./pow(delta_x, 2.);
for(int k=0;k<8;++k) nn_sum += cur[(i+dX[k])*(N+1) + j+dY[k]];
tmp[i*(N+1) + j] = (1.-8.*coeff)*cur[i*(N+1) + j] + coeff*nn_sum;
}
}
__syncthreads();
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N) cur[i*(N+1) + j] = tmp[i*(N+1) + j];
}
__syncthreads();
}
return;
}
__global__ void cudaGetError(int N, double *ana, double *cur, double *e_sum){
// Parallelly compute the error
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < (N+1)*(N+1)) (*e_sum) += (ana[index] - cur[index])*(ana[index] - cur[index]);
return;
}
class DiffEqnSolver{
int n_grid, array_size, in_cell, cell_size, n_cell;
int t_width, nx_thread;
double d_x, **val, **ana, *cur, *old, *d_ana, *err_sum;
public:
DiffEqnSolver(int N):n_grid(N){
d_x = L/n_grid;
array_size = (n_grid+1)*(n_grid+1);
val = new double* [n_grid + 1];
val[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) val[i] = val[i-1] + n_grid + 1;
ana = new double* [n_grid + 1];
ana[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) ana[i] = ana[i-1] + n_grid + 1;
cudaMalloc((void **)&cur, array_size*sizeof(double));
cudaMalloc((void **)&old, array_size*sizeof(double));
cudaMalloc((void **)&d_ana, array_size*sizeof(double));
cudaMalloc((void **)&err_sum, sizeof(double));
// Setting the boundary conditions
for(int i=0;i<=n_grid;++i){
val[0][i] = left(i*d_x);
val[n_grid][i] = right(i*d_x);
val[i][0] = bottom(i*d_x);
val[i][n_grid] = top(i*d_x);
}
// Get the analytical solution
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j) ana[i][j] = analytical(i*d_x, j*d_x);
}
void init(double init_val){
for(int i=1;i<n_grid;++i) for(int j=1;j<n_grid;++j) val[i][j] = init_val;
}
// Compute errors (L2 norm)
double getError(){
double sum = 0.;
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j)
sum += pow(val[i][j] - ana[i][j],2.);
return sqrt(sum);
}
double getErrorUsingCuda(){
double init_sum = 0.;
cudaMemcpy(d_ana, ana[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(cur, val[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(err_sum, &init_sum, sizeof(double), cudaMemcpyHostToDevice);
int b_sz = min(MAX_BLOCK_WIDTH * MAX_BLOCK_WIDTH, array_size);
int n_blk = (array_size + b_sz - 1)/b_sz;
cudaGetError<<<n_blk, b_sz>>>(n_grid, d_ana, cur, err_sum);
cudaMemcpy(&init_sum, err_sum, sizeof(double), cudaMemcpyDeviceToHost);
return sqrt(init_sum);
}
// Get grid size and block size
void setUpGrid(int c_size){
cell_size = c_size;
assert(cell_size > 2 && cell_size <= MAX_BLOCK_WIDTH);
in_cell = cell_size - 2;
n_cell = (n_grid + in_cell - 2)/in_cell;
}
// One step of iteration with multiple blocks
void oneStep(double d_t){
cudaMemcpy(old, val[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
oneIteration<<<n_cell*n_cell, cell_size*cell_size>>>(n_grid, cell_size, cur, old, d_x, d_t);
cudaMemcpy(val[0], cur, array_size*sizeof(double), cudaMemcpyDeviceToHost);
}
// Run multiple iterations with multiple blocks
double runIterations(int N_step, double d_t){
for(int t=0;t<N_step;++t) oneStep(d_t);
return getError();
}
// Get block size if we use only one block of threads
void setUpBlock(int nx_t){
nx_thread = nx_t;
assert(nx_thread > 0 && nx_thread <= MAX_BLOCK_WIDTH);
t_width = (n_grid-2+nx_thread)/nx_thread;
}
// Run multiple iterations with only one block of threads
double runWithOneBlock(int N_step, double d_t){
cudaMemcpy(cur, val[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
iterationWithOneBlock<<<1, nx_thread*nx_thread>>>(n_grid, N_step, nx_thread, cur, old, d_x, d_t);
cudaMemcpy(val[0], cur, array_size*sizeof(double), cudaMemcpyDeviceToHost);
return getError();
}
void fileOutPut(string filename){
FILE *fp = fopen(filename.c_str(), "w");
if (fp == NULL) {
fprintf(stderr, "Can't open output file %s!\n", filename.c_str());
exit(1);
}
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j){
fprintf(fp, "%lf %lf %lf\n", i*d_x, j*d_x, val[i][j]);
}
fclose(fp);
}
~DiffEqnSolver(){
delete [] val[0];
delete [] val;
delete [] ana[0];
delete [] ana;
cudaFree(cur);
cudaFree(old);
cudaFree(d_ana);
cudaFree(err_sum);
}
};
int main(int argc, char *argv[]){
int block_width = 16;
if(argc > 1) block_width = stoi(argv[1]);
int nL = (int)L;
DiffEqnSolver solver(nL);
solver.init(1.);
int n_batch = 21, n_step = 1000;
double dt = 0.5;
cout<<setprecision(3);
cout<<"Start running iterations:"<<endl;
clock_t start_time = clock(), end_time;
solver.setUpGrid(block_width);
for(int i=1;i<=n_batch;++i){
if(false){
string filename = "data"+to_string(i/4);
solver.fileOutPut(filename);
}
cout<<"Iteration: "<<i<<"\t error:"<<solver.runIterations(n_step, dt)<<endl;
}
//solver.setUpBlock(block_width);
//for(int i=1;i<=n_batch;++i) cout<<"Iteration: "<<i<<"\t error:"<<solver.runWithOneBlock(n_step, dt)<<endl;
end_time = clock();
cout<<"End running iterations!"<<endl<<endl;
cout<<"Time spent during iterations: "<<double(end_time-start_time)/CLOCKS_PER_SEC<<"s\n\n\n";
cout<<"================================================================================"<<endl;
return 0;
} | .file "tmpxft_0013f662_00000000-6_cuda_diff_modi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10882:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10882:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN13DiffEqnSolverC2Ei,"axG",@progbits,_ZN13DiffEqnSolverC5Ei,comdat
.align 2
.weak _ZN13DiffEqnSolverC2Ei
.type _ZN13DiffEqnSolverC2Ei, @function
_ZN13DiffEqnSolverC2Ei:
.LFB10865:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, (%rdi)
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
movsd .LC0(%rip), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 32(%rdi)
leal 1(%rsi), %eax
movl %eax, %edx
imull %eax, %edx
movl %edx, 4(%rdi)
cltq
movq %rax, %rcx
shrq $60, %rcx
jne .L4
movq %rdi, %rbp
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %rbx
movq %rax, 40(%rbp)
movslq 4(%rbp), %rax
movq %rax, %rcx
shrq $60, %rcx
jne .L33
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, (%rbx)
movl 0(%rbp), %eax
movl $0, %edx
movl $1, %ecx
testl %eax, %eax
jle .L8
.L7:
movq 40(%rbp), %rsi
movq %rdx, %rdi
addq $8, %rdx
cltq
movq (%rsi,%rdi), %rdi
leaq 8(%rdi,%rax,8), %rax
movq %rax, (%rsi,%rdx)
addl $1, %ecx
movl 0(%rbp), %eax
cmpl %ecx, %eax
jge .L7
.L8:
addl $1, %eax
cltq
movq %rax, %rcx
shrq $60, %rcx
jne .L9
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, %rbx
movq %rax, 48(%rbp)
movslq 4(%rbp), %rax
movq %rax, %rcx
shrq $60, %rcx
jne .L34
leaq 0(,%rax,8), %rdi
call _Znam@PLT
movq %rax, (%rbx)
movl 0(%rbp), %eax
movl $0, %edx
movl $1, %ecx
testl %eax, %eax
jle .L13
.L12:
movq 48(%rbp), %rsi
movq %rdx, %rdi
addq $8, %rdx
cltq
movq (%rsi,%rdi), %rdi
leaq 8(%rdi,%rax,8), %rax
movq %rax, (%rsi,%rdx)
addl $1, %ecx
movl 0(%rbp), %eax
cmpl %ecx, %eax
jge .L12
.L13:
movslq 4(%rbp), %rsi
salq $3, %rsi
leaq 56(%rbp), %rdi
call cudaMalloc@PLT
movslq 4(%rbp), %rsi
salq $3, %rsi
leaq 64(%rbp), %rdi
call cudaMalloc@PLT
movslq 4(%rbp), %rsi
salq $3, %rsi
leaq 72(%rbp), %rdi
call cudaMalloc@PLT
leaq 80(%rbp), %rdi
movl $8, %esi
call cudaMalloc@PLT
cmpl $0, 0(%rbp)
js .L3
movl $0, %ebx
.L15:
movq 40(%rbp), %rax
movq (%rax), %rax
movq $0x000000000, (%rax,%rbx,8)
movslq 0(%rbp), %rdx
movq 40(%rbp), %rax
movq (%rax,%rdx,8), %rax
movq $0x000000000, (%rax,%rbx,8)
movq 40(%rbp), %rax
movq (%rax,%rbx,8), %rax
movq $0x000000000, (%rax)
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
mulsd 32(%rbp), %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC0(%rip), %xmm0
call sin@PLT
movq 40(%rbp), %rax
movslq 0(%rbp), %rdx
movq (%rax,%rbx,8), %rax
mulsd .LC3(%rip), %xmm0
movsd %xmm0, (%rax,%rdx,8)
movl 0(%rbp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jge .L15
testl %eax, %eax
js .L3
movl $0, %r15d
jmp .L16
.L4:
call __cxa_throw_bad_array_new_length@PLT
.L33:
call __cxa_throw_bad_array_new_length@PLT
.L9:
call __cxa_throw_bad_array_new_length@PLT
.L34:
call __cxa_throw_bad_array_new_length@PLT
.L17:
movq 32(%rbp), %r12
movq 48(%rbp), %rax
movq (%rax,%r14), %rax
leaq (%rax,%rbx,8), %r13
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq %r12, %xmm2
mulsd %xmm2, %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC0(%rip), %xmm0
call sinh@PLT
movsd %xmm0, (%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl 12(%rsp), %xmm0
movq %r12, %xmm3
mulsd %xmm3, %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC0(%rip), %xmm0
call sin@PLT
mulsd (%rsp), %xmm0
movsd %xmm0, 0(%r13)
addq $1, %rbx
cmpl %ebx, 0(%rbp)
jge .L17
.L19:
addq $1, %r15
cmpl %r15d, 0(%rbp)
jl .L3
.L16:
movl %r15d, 12(%rsp)
leaq 0(,%r15,8), %r14
movl $0, %ebx
cmpl $0, 0(%rbp)
jns .L17
jmp .L19
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10865:
.size _ZN13DiffEqnSolverC2Ei, .-_ZN13DiffEqnSolverC2Ei
.weak _ZN13DiffEqnSolverC1Ei
.set _ZN13DiffEqnSolverC1Ei,_ZN13DiffEqnSolverC2Ei
.section .text._ZN13DiffEqnSolverD2Ev,"axG",@progbits,_ZN13DiffEqnSolverD5Ev,comdat
.align 2
.weak _ZN13DiffEqnSolverD2Ev
.type _ZN13DiffEqnSolverD2Ev, @function
_ZN13DiffEqnSolverD2Ev:
.LFB10877:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10877
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 40(%rdi), %rdi
movq (%rdi), %rax
testq %rax, %rax
je .L36
movq %rax, %rdi
call _ZdaPv@PLT
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .L37
.L36:
call _ZdaPv@PLT
.L37:
movq 48(%rbx), %rdi
movq (%rdi), %rax
testq %rax, %rax
je .L38
movq %rax, %rdi
call _ZdaPv@PLT
movq 48(%rbx), %rdi
testq %rdi, %rdi
je .L39
.L38:
call _ZdaPv@PLT
.L39:
movq 56(%rbx), %rdi
call cudaFree@PLT
movq 64(%rbx), %rdi
call cudaFree@PLT
movq 72(%rbx), %rdi
call cudaFree@PLT
movq 80(%rbx), %rdi
call cudaFree@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10877:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN13DiffEqnSolverD2Ev,"aG",@progbits,_ZN13DiffEqnSolverD5Ev,comdat
.LLSDA10877:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10877-.LLSDACSB10877
.LLSDACSB10877:
.LLSDACSE10877:
.section .text._ZN13DiffEqnSolverD2Ev,"axG",@progbits,_ZN13DiffEqnSolverD5Ev,comdat
.size _ZN13DiffEqnSolverD2Ev, .-_ZN13DiffEqnSolverD2Ev
.weak _ZN13DiffEqnSolverD1Ev
.set _ZN13DiffEqnSolverD1Ev,_ZN13DiffEqnSolverD2Ev
.text
.globl _Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd
.type _Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd, @function
_Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd:
.LFB10904:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12oneIterationiiPdS_dd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10904:
.size _Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd, .-_Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd
.globl _Z12oneIterationiiPdS_dd
.type _Z12oneIterationiiPdS_dd, @function
_Z12oneIterationiiPdS_dd:
.LFB10905:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10905:
.size _Z12oneIterationiiPdS_dd, .-_Z12oneIterationiiPdS_dd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "stoi"
.LC7:
.string "Start running iterations:"
.LC8:
.string "Iteration: "
.LC9:
.string "\t error:"
.LC11:
.string "End running iterations!"
.section .rodata.str1.8
.align 8
.LC12:
.string "Time spent during iterations: "
.section .rodata.str1.1
.LC14:
.string "s\n\n\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "================================================================================"
.text
.globl main
.type main, @function
main:
.LFB10879:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10879
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rdx
movq %rdx, 184(%rsp)
xorl %edx, %edx
cmpl $1, %edi
jle .L87
movq 8(%rsi), %rbp
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
testq %rbp, %rbp
je .L102
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 48(%rsp)
cmpq $15, %rax
ja .L103
cmpq $1, %rax
jne .L55
movzbl 0(%rbp), %eax
movb %al, 160(%rsp)
.L56:
movq 48(%rsp), %rax
movq %rax, 152(%rsp)
movq 144(%rsp), %rdx
movb $0, (%rdx,%rax)
movq 144(%rsp), %r13
call __errno_location@PLT
movq %rax, %rbp
movl (%rax), %r12d
movl $0, (%rax)
leaq 48(%rsp), %rsi
movl $10, %edx
movq %r13, %rdi
call __isoc23_strtol@PLT
movq %rax, %rbx
cmpq 48(%rsp), %r13
je .L104
movl 0(%rbp), %edx
cmpl $34, %edx
je .L59
movl $2147483648, %eax
addq %rbx, %rax
movl $4294967295, %ecx
cmpq %rax, %rcx
jb .L59
testl %edx, %edx
jne .L62
movl %r12d, 0(%rbp)
.L62:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L50:
leaq 48(%rsp), %rdi
movl $550, %esi
.LEHB0:
call _ZN13DiffEqnSolverC1Ei
.LEHE0:
movl $8, %esi
movl $1, %edi
movsd .LC6(%rip), %xmm0
cmpl $1, 48(%rsp)
jg .L66
.L67:
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $3, 8(%rdi,%rax)
leaq .LC7(%rip), %rsi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE1:
jmp .L105
.L102:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L106
leaq .LC4(%rip), %rdi
.LEHB2:
call _ZSt19__throw_logic_errorPKc@PLT
.L106:
call __stack_chk_fail@PLT
.L103:
leaq 48(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE2:
movq %rax, %rdi
movq %rax, 144(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
.L54:
movq %rbx, %rdx
movq %rbp, %rsi
call memcpy@PLT
jmp .L56
.L55:
testq %rax, %rax
je .L56
leaq 160(%rsp), %rdi
jmp .L54
.L104:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L107
leaq .LC5(%rip), %rdi
.LEHB3:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L107:
call __stack_chk_fail@PLT
.L59:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L108
leaq .LC5(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE3:
.L92:
endbr64
movq %rax, %rbx
cmpl $0, 0(%rbp)
jne .L64
movl %r12d, 0(%rbp)
.L64:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L65
call __stack_chk_fail@PLT
.L108:
call __stack_chk_fail@PLT
.L65:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L87:
movl $16, %ebx
jmp .L50
.L69:
addl $1, %edi
addq $8, %rsi
cmpl 48(%rsp), %edi
jge .L67
.L66:
movl $8, %edx
movl $1, %eax
cmpl $1, 48(%rsp)
jle .L69
.L68:
movq 88(%rsp), %rcx
movq (%rcx,%rsi), %rcx
movsd %xmm0, (%rcx,%rdx)
addl $1, %eax
addq $8, %rdx
cmpl 48(%rsp), %eax
jl .L68
jmp .L69
.L105:
movq %rax, %rdi
.LEHB5:
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, 8(%rsp)
movl %ebx, 60(%rsp)
subl $2, %ebx
movl %ebx, 56(%rsp)
movl %ebx, %eax
addl 48(%rsp), %eax
subl $2, %eax
cltd
idivl %ebx
movl %eax, 64(%rsp)
movl $1, %ebp
leaq .LC8(%rip), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC9(%rip), %r14
jmp .L83
.L120:
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r15
movl $8, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1000, %ebx
jmp .L71
.L112:
movl 60(%rsp), %eax
imull %eax, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl 64(%rsp), %eax
imull %eax, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L70:
movslq 52(%rsp), %rdx
salq $3, %rdx
movq 88(%rsp), %rax
movq (%rax), %rdi
movl $2, %ecx
movq 104(%rsp), %rsi
call cudaMemcpy@PLT
jmp .L110
.L109:
movsd .LC10(%rip), %xmm1
movsd 80(%rsp), %xmm0
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movl 60(%rsp), %esi
movl 48(%rsp), %edi
call _Z38__device_stub__Z12oneIterationiiPdS_ddiiPdS_dd
jmp .L70
.L110:
subl $1, %ebx
je .L111
.L71:
movslq 52(%rsp), %rdx
salq $3, %rdx
movq 88(%rsp), %rax
movq (%rax), %rsi
movl $1, %ecx
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L112
.L111:
movl 48(%rsp), %eax
testl %eax, %eax
js .L90
movq 88(%rsp), %r9
movq 96(%rsp), %r8
leal 1(%rax), %edx
salq $3, %rdx
movl $0, %edi
pxor %xmm0, %xmm0
jmp .L73
.L113:
addq $8, %rdi
cmpq %rdi, %rdx
je .L75
.L73:
movq (%r9,%rdi), %rsi
movq (%r8,%rdi), %rcx
movl $0, %eax
.L74:
movsd (%rsi,%rax), %xmm1
subsd (%rcx,%rax), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L74
jmp .L113
.L75:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L114
.L72:
sqrtsd %xmm0, %xmm0
.L78:
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L115
.L90:
pxor %xmm0, %xmm0
jmp .L72
.L114:
call sqrt@PLT
jmp .L78
.L115:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L116
cmpb $0, 56(%r15)
je .L81
movzbl 67(%r15), %eax
.L82:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L117
.L116:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L118
call _ZSt16__throw_bad_castv@PLT
.L91:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZN13DiffEqnSolverD1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L85
call __stack_chk_fail@PLT
.L118:
call __stack_chk_fail@PLT
.L81:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
jmp .L82
.L117:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl $22, %ebp
je .L119
.L83:
movl $11, %edx
movq %r13, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L120
.L119:
call clock@PLT
movq %rax, %rbx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
subq %rax, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC13(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE5:
leaq 48(%rsp), %rdi
call _ZN13DiffEqnSolverD1Ev
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L121
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L121:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10879:
.section .gcc_except_table,"a",@progbits
.LLSDA10879:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10879-.LLSDACSB10879
.LLSDACSB10879:
.uleb128 .LEHB0-.LFB10879
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10879
.uleb128 .LEHE1-.LEHB1
.uleb128 .L91-.LFB10879
.uleb128 0
.uleb128 .LEHB2-.LFB10879
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB10879
.uleb128 .LEHE3-.LEHB3
.uleb128 .L92-.LFB10879
.uleb128 0
.uleb128 .LEHB4-.LFB10879
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB10879
.uleb128 .LEHE5-.LEHB5
.uleb128 .L91-.LFB10879
.uleb128 0
.uleb128 .LEHB6-.LFB10879
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE10879:
.text
.size main, .-main
.globl _Z48__device_stub__Z21iterationWithOneBlockiiiPdS_ddiiiPdS_dd
.type _Z48__device_stub__Z21iterationWithOneBlockiiiPdS_ddiiiPdS_dd, @function
_Z48__device_stub__Z21iterationWithOneBlockiiiPdS_ddiiiPdS_dd:
.LFB10906:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L126
.L122:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L127
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L126:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21iterationWithOneBlockiiiPdS_dd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L122
.L127:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10906:
.size _Z48__device_stub__Z21iterationWithOneBlockiiiPdS_ddiiiPdS_dd, .-_Z48__device_stub__Z21iterationWithOneBlockiiiPdS_ddiiiPdS_dd
.globl _Z21iterationWithOneBlockiiiPdS_dd
.type _Z21iterationWithOneBlockiiiPdS_dd, @function
_Z21iterationWithOneBlockiiiPdS_dd:
.LFB10907:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z21iterationWithOneBlockiiiPdS_ddiiiPdS_dd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10907:
.size _Z21iterationWithOneBlockiiiPdS_dd, .-_Z21iterationWithOneBlockiiiPdS_dd
.globl _Z37__device_stub__Z12cudaGetErroriPdS_S_iPdS_S_
.type _Z37__device_stub__Z12cudaGetErroriPdS_S_iPdS_S_, @function
_Z37__device_stub__Z12cudaGetErroriPdS_S_iPdS_S_:
.LFB10908:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L134
.L130:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L135
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L134:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cudaGetErroriPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L130
.L135:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10908:
.size _Z37__device_stub__Z12cudaGetErroriPdS_S_iPdS_S_, .-_Z37__device_stub__Z12cudaGetErroriPdS_S_iPdS_S_
.globl _Z12cudaGetErroriPdS_S_
.type _Z12cudaGetErroriPdS_S_, @function
_Z12cudaGetErroriPdS_S_:
.LFB10909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12cudaGetErroriPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10909:
.size _Z12cudaGetErroriPdS_S_, .-_Z12cudaGetErroriPdS_S_
.section .rodata.str1.1
.LC16:
.string "_Z12cudaGetErroriPdS_S_"
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z21iterationWithOneBlockiiiPdS_dd"
.section .rodata.str1.1
.LC18:
.string "_Z12oneIterationiiPdS_dd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10911:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cudaGetErroriPdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z21iterationWithOneBlockiiiPdS_dd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z12oneIterationiiPdS_dd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10911:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1082208256
.align 8
.LC2:
.long 1413754136
.long 1074340347
.align 8
.LC3:
.long 1567811185
.long 1076304116
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC10:
.long 0
.long 1071644672
.align 8
.LC13:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
const double pi = 3.14159265358979323846264;
const double L = 550;
const double Diff = 1.;
const int MAX_BLOCK_WIDTH = 32;
// In this method, we use squre cells of threads, but we need to specify the size of the square.
/*
| coordinate system:
-|---------------y
| x = i * d_x
| y = i * d_x
|
x
*/
inline double left(double y) { return 0; }
inline double right(double y) { return 0; }
inline double bottom(double x) { return 0; }
inline double top(double x){ return sinh(pi)*sin(x*pi/L); }
inline double analytical(double x,double y){
return sinh(y*pi/L)*sin(x*pi/L);
}
__global__ void oneIteration(int N, int cell_size, double *cur, double *old, double delta_x,double delta_t){
// Run one step of iteration with multiple blocks of threads
int b_size = blockDim.x, b_id = blockIdx.x, t_id = threadIdx.x, in_cell = cell_size - 2;
int n_cell = (N + in_cell -2)/in_cell;
assert(N > 1);
assert(cell_size <= MAX_BLOCK_WIDTH);
assert(b_size == cell_size*cell_size); // Here we only use square cells
__shared__ double tmp_arr[MAX_BLOCK_WIDTH][MAX_BLOCK_WIDTH]; // Define a buffer in the shared memory of one block of threads
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
// Compute indices in the cell and in the original matrix
int local_i = t_id/cell_size, local_j = t_id%cell_size;
int global_i = (b_id/n_cell)*in_cell + local_i, global_j = (b_id%n_cell)*in_cell + local_j;
// Copy the old data into the buffer array, then synchronize threads
if(global_i>=0 && global_i<=N && global_j>=0 && global_j<=N){
tmp_arr[local_i][local_j] = old[global_i*(N+1) + global_j];
// Maintain the Dirichlet Type Boundary Conditions.
if(!global_i || !global_j || global_i==N || global_j==N) cur[global_i*(N+1)+global_j] = tmp_arr[local_i][local_j];
}
__syncthreads();
// Compute the updated value and store it into *cur
if(local_i && local_i<cell_size-1 && local_j && local_j<cell_size-1 && global_i && global_i<N && global_j && global_j<N){
double nn_diff = 0.;
for(int k=0;k<8;++k) nn_diff += tmp_arr[local_i+dX[k]][local_j+dY[k]];
nn_diff -= 8.*tmp_arr[local_i][local_j];
cur[global_i*(N+1) + global_j] = tmp_arr[local_i][local_j] + Diff*delta_t*nn_diff/3./pow(delta_x, 2.);
}
return;
}
__global__ void iterationWithOneBlock(int N,int N_step, int nx_thread, double *cur, double *tmp, double delta_x, double delta_t){
// Run multiple steps of iterations with one block of threads
int t_id = threadIdx.x, b_size = blockDim.x, t_width = (N-2+nx_thread)/nx_thread;
assert(b_size == nx_thread*nx_thread);
// Define neighbor vectors:
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
int global_i = (t_id/nx_thread)*t_width, globel_j = (t_id%nx_thread)*t_width;
for(int step=0;step<N_step;++step){
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N){
double nn_sum = 0., coeff = Diff*delta_t/3./pow(delta_x, 2.);
for(int k=0;k<8;++k) nn_sum += cur[(i+dX[k])*(N+1) + j+dY[k]];
tmp[i*(N+1) + j] = (1.-8.*coeff)*cur[i*(N+1) + j] + coeff*nn_sum;
}
}
__syncthreads();
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N) cur[i*(N+1) + j] = tmp[i*(N+1) + j];
}
__syncthreads();
}
return;
}
__global__ void cudaGetError(int N, double *ana, double *cur, double *e_sum){
// Parallelly compute the error
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < (N+1)*(N+1)) (*e_sum) += (ana[index] - cur[index])*(ana[index] - cur[index]);
return;
}
class DiffEqnSolver{
int n_grid, array_size, in_cell, cell_size, n_cell;
int t_width, nx_thread;
double d_x, **val, **ana, *cur, *old, *d_ana, *err_sum;
public:
DiffEqnSolver(int N):n_grid(N){
d_x = L/n_grid;
array_size = (n_grid+1)*(n_grid+1);
val = new double* [n_grid + 1];
val[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) val[i] = val[i-1] + n_grid + 1;
ana = new double* [n_grid + 1];
ana[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) ana[i] = ana[i-1] + n_grid + 1;
cudaMalloc((void **)&cur, array_size*sizeof(double));
cudaMalloc((void **)&old, array_size*sizeof(double));
cudaMalloc((void **)&d_ana, array_size*sizeof(double));
cudaMalloc((void **)&err_sum, sizeof(double));
// Setting the boundary conditions
for(int i=0;i<=n_grid;++i){
val[0][i] = left(i*d_x);
val[n_grid][i] = right(i*d_x);
val[i][0] = bottom(i*d_x);
val[i][n_grid] = top(i*d_x);
}
// Get the analytical solution
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j) ana[i][j] = analytical(i*d_x, j*d_x);
}
void init(double init_val){
for(int i=1;i<n_grid;++i) for(int j=1;j<n_grid;++j) val[i][j] = init_val;
}
// Compute errors (L2 norm)
double getError(){
double sum = 0.;
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j)
sum += pow(val[i][j] - ana[i][j],2.);
return sqrt(sum);
}
double getErrorUsingCuda(){
double init_sum = 0.;
cudaMemcpy(d_ana, ana[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(cur, val[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(err_sum, &init_sum, sizeof(double), cudaMemcpyHostToDevice);
int b_sz = min(MAX_BLOCK_WIDTH * MAX_BLOCK_WIDTH, array_size);
int n_blk = (array_size + b_sz - 1)/b_sz;
cudaGetError<<<n_blk, b_sz>>>(n_grid, d_ana, cur, err_sum);
cudaMemcpy(&init_sum, err_sum, sizeof(double), cudaMemcpyDeviceToHost);
return sqrt(init_sum);
}
// Get grid size and block size
void setUpGrid(int c_size){
cell_size = c_size;
assert(cell_size > 2 && cell_size <= MAX_BLOCK_WIDTH);
in_cell = cell_size - 2;
n_cell = (n_grid + in_cell - 2)/in_cell;
}
// One step of iteration with multiple blocks
void oneStep(double d_t){
cudaMemcpy(old, val[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
oneIteration<<<n_cell*n_cell, cell_size*cell_size>>>(n_grid, cell_size, cur, old, d_x, d_t);
cudaMemcpy(val[0], cur, array_size*sizeof(double), cudaMemcpyDeviceToHost);
}
// Run multiple iterations with multiple blocks
double runIterations(int N_step, double d_t){
for(int t=0;t<N_step;++t) oneStep(d_t);
return getError();
}
// Get block size if we use only one block of threads
void setUpBlock(int nx_t){
nx_thread = nx_t;
assert(nx_thread > 0 && nx_thread <= MAX_BLOCK_WIDTH);
t_width = (n_grid-2+nx_thread)/nx_thread;
}
// Run multiple iterations with only one block of threads
double runWithOneBlock(int N_step, double d_t){
cudaMemcpy(cur, val[0], array_size*sizeof(double), cudaMemcpyHostToDevice);
iterationWithOneBlock<<<1, nx_thread*nx_thread>>>(n_grid, N_step, nx_thread, cur, old, d_x, d_t);
cudaMemcpy(val[0], cur, array_size*sizeof(double), cudaMemcpyDeviceToHost);
return getError();
}
void fileOutPut(string filename){
FILE *fp = fopen(filename.c_str(), "w");
if (fp == NULL) {
fprintf(stderr, "Can't open output file %s!\n", filename.c_str());
exit(1);
}
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j){
fprintf(fp, "%lf %lf %lf\n", i*d_x, j*d_x, val[i][j]);
}
fclose(fp);
}
~DiffEqnSolver(){
delete [] val[0];
delete [] val;
delete [] ana[0];
delete [] ana;
cudaFree(cur);
cudaFree(old);
cudaFree(d_ana);
cudaFree(err_sum);
}
};
int main(int argc, char *argv[]){
int block_width = 16;
if(argc > 1) block_width = stoi(argv[1]);
int nL = (int)L;
DiffEqnSolver solver(nL);
solver.init(1.);
int n_batch = 21, n_step = 1000;
double dt = 0.5;
cout<<setprecision(3);
cout<<"Start running iterations:"<<endl;
clock_t start_time = clock(), end_time;
solver.setUpGrid(block_width);
for(int i=1;i<=n_batch;++i){
if(false){
string filename = "data"+to_string(i/4);
solver.fileOutPut(filename);
}
cout<<"Iteration: "<<i<<"\t error:"<<solver.runIterations(n_step, dt)<<endl;
}
//solver.setUpBlock(block_width);
//for(int i=1;i<=n_batch;++i) cout<<"Iteration: "<<i<<"\t error:"<<solver.runWithOneBlock(n_step, dt)<<endl;
end_time = clock();
cout<<"End running iterations!"<<endl<<endl;
cout<<"Time spent during iterations: "<<double(end_time-start_time)/CLOCKS_PER_SEC<<"s\n\n\n";
cout<<"================================================================================"<<endl;
return 0;
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
const double pi = 3.14159265358979323846264;
const double L = 550;
const double Diff = 1.;
const int MAX_BLOCK_WIDTH = 32;
// In this method, we use squre cells of threads, but we need to specify the size of the square.
/*
| coordinate system:
-|---------------y
| x = i * d_x
| y = i * d_x
|
x
*/
inline double left(double y) { return 0; }
inline double right(double y) { return 0; }
inline double bottom(double x) { return 0; }
inline double top(double x){ return sinh(pi)*sin(x*pi/L); }
inline double analytical(double x,double y){
return sinh(y*pi/L)*sin(x*pi/L);
}
__global__ void oneIteration(int N, int cell_size, double *cur, double *old, double delta_x,double delta_t){
// Run one step of iteration with multiple blocks of threads
int b_size = blockDim.x, b_id = blockIdx.x, t_id = threadIdx.x, in_cell = cell_size - 2;
int n_cell = (N + in_cell -2)/in_cell;
assert(N > 1);
assert(cell_size <= MAX_BLOCK_WIDTH);
assert(b_size == cell_size*cell_size); // Here we only use square cells
__shared__ double tmp_arr[MAX_BLOCK_WIDTH][MAX_BLOCK_WIDTH]; // Define a buffer in the shared memory of one block of threads
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
// Compute indices in the cell and in the original matrix
int local_i = t_id/cell_size, local_j = t_id%cell_size;
int global_i = (b_id/n_cell)*in_cell + local_i, global_j = (b_id%n_cell)*in_cell + local_j;
// Copy the old data into the buffer array, then synchronize threads
if(global_i>=0 && global_i<=N && global_j>=0 && global_j<=N){
tmp_arr[local_i][local_j] = old[global_i*(N+1) + global_j];
// Maintain the Dirichlet Type Boundary Conditions.
if(!global_i || !global_j || global_i==N || global_j==N) cur[global_i*(N+1)+global_j] = tmp_arr[local_i][local_j];
}
__syncthreads();
// Compute the updated value and store it into *cur
if(local_i && local_i<cell_size-1 && local_j && local_j<cell_size-1 && global_i && global_i<N && global_j && global_j<N){
double nn_diff = 0.;
for(int k=0;k<8;++k) nn_diff += tmp_arr[local_i+dX[k]][local_j+dY[k]];
nn_diff -= 8.*tmp_arr[local_i][local_j];
cur[global_i*(N+1) + global_j] = tmp_arr[local_i][local_j] + Diff*delta_t*nn_diff/3./pow(delta_x, 2.);
}
return;
}
__global__ void iterationWithOneBlock(int N,int N_step, int nx_thread, double *cur, double *tmp, double delta_x, double delta_t){
// Run multiple steps of iterations with one block of threads
int t_id = threadIdx.x, b_size = blockDim.x, t_width = (N-2+nx_thread)/nx_thread;
assert(b_size == nx_thread*nx_thread);
// Define neighbor vectors:
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
int global_i = (t_id/nx_thread)*t_width, globel_j = (t_id%nx_thread)*t_width;
for(int step=0;step<N_step;++step){
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N){
double nn_sum = 0., coeff = Diff*delta_t/3./pow(delta_x, 2.);
for(int k=0;k<8;++k) nn_sum += cur[(i+dX[k])*(N+1) + j+dY[k]];
tmp[i*(N+1) + j] = (1.-8.*coeff)*cur[i*(N+1) + j] + coeff*nn_sum;
}
}
__syncthreads();
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N) cur[i*(N+1) + j] = tmp[i*(N+1) + j];
}
__syncthreads();
}
return;
}
__global__ void cudaGetError(int N, double *ana, double *cur, double *e_sum){
// Parallelly compute the error
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < (N+1)*(N+1)) (*e_sum) += (ana[index] - cur[index])*(ana[index] - cur[index]);
return;
}
class DiffEqnSolver{
int n_grid, array_size, in_cell, cell_size, n_cell;
int t_width, nx_thread;
double d_x, **val, **ana, *cur, *old, *d_ana, *err_sum;
public:
DiffEqnSolver(int N):n_grid(N){
d_x = L/n_grid;
array_size = (n_grid+1)*(n_grid+1);
val = new double* [n_grid + 1];
val[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) val[i] = val[i-1] + n_grid + 1;
ana = new double* [n_grid + 1];
ana[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) ana[i] = ana[i-1] + n_grid + 1;
hipMalloc((void **)&cur, array_size*sizeof(double));
hipMalloc((void **)&old, array_size*sizeof(double));
hipMalloc((void **)&d_ana, array_size*sizeof(double));
hipMalloc((void **)&err_sum, sizeof(double));
// Setting the boundary conditions
for(int i=0;i<=n_grid;++i){
val[0][i] = left(i*d_x);
val[n_grid][i] = right(i*d_x);
val[i][0] = bottom(i*d_x);
val[i][n_grid] = top(i*d_x);
}
// Get the analytical solution
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j) ana[i][j] = analytical(i*d_x, j*d_x);
}
void init(double init_val){
for(int i=1;i<n_grid;++i) for(int j=1;j<n_grid;++j) val[i][j] = init_val;
}
// Compute errors (L2 norm)
double getError(){
double sum = 0.;
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j)
sum += pow(val[i][j] - ana[i][j],2.);
return sqrt(sum);
}
double getErrorUsingCuda(){
double init_sum = 0.;
hipMemcpy(d_ana, ana[0], array_size*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(cur, val[0], array_size*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(err_sum, &init_sum, sizeof(double), hipMemcpyHostToDevice);
int b_sz = min(MAX_BLOCK_WIDTH * MAX_BLOCK_WIDTH, array_size);
int n_blk = (array_size + b_sz - 1)/b_sz;
cudaGetError<<<n_blk, b_sz>>>(n_grid, d_ana, cur, err_sum);
hipMemcpy(&init_sum, err_sum, sizeof(double), hipMemcpyDeviceToHost);
return sqrt(init_sum);
}
// Get grid size and block size
void setUpGrid(int c_size){
cell_size = c_size;
assert(cell_size > 2 && cell_size <= MAX_BLOCK_WIDTH);
in_cell = cell_size - 2;
n_cell = (n_grid + in_cell - 2)/in_cell;
}
// One step of iteration with multiple blocks
void oneStep(double d_t){
hipMemcpy(old, val[0], array_size*sizeof(double), hipMemcpyHostToDevice);
oneIteration<<<n_cell*n_cell, cell_size*cell_size>>>(n_grid, cell_size, cur, old, d_x, d_t);
hipMemcpy(val[0], cur, array_size*sizeof(double), hipMemcpyDeviceToHost);
}
// Run multiple iterations with multiple blocks
double runIterations(int N_step, double d_t){
for(int t=0;t<N_step;++t) oneStep(d_t);
return getError();
}
// Get block size if we use only one block of threads
void setUpBlock(int nx_t){
nx_thread = nx_t;
assert(nx_thread > 0 && nx_thread <= MAX_BLOCK_WIDTH);
t_width = (n_grid-2+nx_thread)/nx_thread;
}
// Run multiple iterations with only one block of threads
double runWithOneBlock(int N_step, double d_t){
hipMemcpy(cur, val[0], array_size*sizeof(double), hipMemcpyHostToDevice);
iterationWithOneBlock<<<1, nx_thread*nx_thread>>>(n_grid, N_step, nx_thread, cur, old, d_x, d_t);
hipMemcpy(val[0], cur, array_size*sizeof(double), hipMemcpyDeviceToHost);
return getError();
}
void fileOutPut(string filename){
FILE *fp = fopen(filename.c_str(), "w");
if (fp == NULL) {
fprintf(stderr, "Can't open output file %s!\n", filename.c_str());
exit(1);
}
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j){
fprintf(fp, "%lf %lf %lf\n", i*d_x, j*d_x, val[i][j]);
}
fclose(fp);
}
~DiffEqnSolver(){
delete [] val[0];
delete [] val;
delete [] ana[0];
delete [] ana;
hipFree(cur);
hipFree(old);
hipFree(d_ana);
hipFree(err_sum);
}
};
int main(int argc, char *argv[]){
int block_width = 16;
if(argc > 1) block_width = stoi(argv[1]);
int nL = (int)L;
DiffEqnSolver solver(nL);
solver.init(1.);
int n_batch = 21, n_step = 1000;
double dt = 0.5;
cout<<setprecision(3);
cout<<"Start running iterations:"<<endl;
clock_t start_time = clock(), end_time;
solver.setUpGrid(block_width);
for(int i=1;i<=n_batch;++i){
if(false){
string filename = "data"+to_string(i/4);
solver.fileOutPut(filename);
}
cout<<"Iteration: "<<i<<"\t error:"<<solver.runIterations(n_step, dt)<<endl;
}
//solver.setUpBlock(block_width);
//for(int i=1;i<=n_batch;++i) cout<<"Iteration: "<<i<<"\t error:"<<solver.runWithOneBlock(n_step, dt)<<endl;
end_time = clock();
cout<<"End running iterations!"<<endl<<endl;
cout<<"Time spent during iterations: "<<double(end_time-start_time)/CLOCKS_PER_SEC<<"s\n\n\n";
cout<<"================================================================================"<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
const double pi = 3.14159265358979323846264;
const double L = 550;
const double Diff = 1.;
const int MAX_BLOCK_WIDTH = 32;
// In this method, we use squre cells of threads, but we need to specify the size of the square.
/*
| coordinate system:
-|---------------y
| x = i * d_x
| y = i * d_x
|
x
*/
inline double left(double y) { return 0; }
inline double right(double y) { return 0; }
inline double bottom(double x) { return 0; }
inline double top(double x){ return sinh(pi)*sin(x*pi/L); }
inline double analytical(double x,double y){
return sinh(y*pi/L)*sin(x*pi/L);
}
__global__ void oneIteration(int N, int cell_size, double *cur, double *old, double delta_x,double delta_t){
// Run one step of iteration with multiple blocks of threads
int b_size = blockDim.x, b_id = blockIdx.x, t_id = threadIdx.x, in_cell = cell_size - 2;
int n_cell = (N + in_cell -2)/in_cell;
assert(N > 1);
assert(cell_size <= MAX_BLOCK_WIDTH);
assert(b_size == cell_size*cell_size); // Here we only use square cells
__shared__ double tmp_arr[MAX_BLOCK_WIDTH][MAX_BLOCK_WIDTH]; // Define a buffer in the shared memory of one block of threads
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
// Compute indices in the cell and in the original matrix
int local_i = t_id/cell_size, local_j = t_id%cell_size;
int global_i = (b_id/n_cell)*in_cell + local_i, global_j = (b_id%n_cell)*in_cell + local_j;
// Copy the old data into the buffer array, then synchronize threads
if(global_i>=0 && global_i<=N && global_j>=0 && global_j<=N){
tmp_arr[local_i][local_j] = old[global_i*(N+1) + global_j];
// Maintain the Dirichlet Type Boundary Conditions.
if(!global_i || !global_j || global_i==N || global_j==N) cur[global_i*(N+1)+global_j] = tmp_arr[local_i][local_j];
}
__syncthreads();
// Compute the updated value and store it into *cur
if(local_i && local_i<cell_size-1 && local_j && local_j<cell_size-1 && global_i && global_i<N && global_j && global_j<N){
double nn_diff = 0.;
for(int k=0;k<8;++k) nn_diff += tmp_arr[local_i+dX[k]][local_j+dY[k]];
nn_diff -= 8.*tmp_arr[local_i][local_j];
cur[global_i*(N+1) + global_j] = tmp_arr[local_i][local_j] + Diff*delta_t*nn_diff/3./pow(delta_x, 2.);
}
return;
}
__global__ void iterationWithOneBlock(int N,int N_step, int nx_thread, double *cur, double *tmp, double delta_x, double delta_t){
// Run multiple steps of iterations with one block of threads
int t_id = threadIdx.x, b_size = blockDim.x, t_width = (N-2+nx_thread)/nx_thread;
assert(b_size == nx_thread*nx_thread);
// Define neighbor vectors:
int dX[8] = {0, 0, 1, -1, 1, -1, 1, -1};
int dY[8] = {1, -1, 0, 0, 1, 1, -1, -1};
int global_i = (t_id/nx_thread)*t_width, globel_j = (t_id%nx_thread)*t_width;
for(int step=0;step<N_step;++step){
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N){
double nn_sum = 0., coeff = Diff*delta_t/3./pow(delta_x, 2.);
for(int k=0;k<8;++k) nn_sum += cur[(i+dX[k])*(N+1) + j+dY[k]];
tmp[i*(N+1) + j] = (1.-8.*coeff)*cur[i*(N+1) + j] + coeff*nn_sum;
}
}
__syncthreads();
for(int i=global_i;i<global_i+t_width;++i) for(int j=globel_j;j<globel_j+t_width;++j){
if(i && i<N && j && j<N) cur[i*(N+1) + j] = tmp[i*(N+1) + j];
}
__syncthreads();
}
return;
}
__global__ void cudaGetError(int N, double *ana, double *cur, double *e_sum){
// Parallelly compute the error
int index = blockIdx.x*blockDim.x + threadIdx.x;
if(index < (N+1)*(N+1)) (*e_sum) += (ana[index] - cur[index])*(ana[index] - cur[index]);
return;
}
class DiffEqnSolver{
int n_grid, array_size, in_cell, cell_size, n_cell;
int t_width, nx_thread;
double d_x, **val, **ana, *cur, *old, *d_ana, *err_sum;
public:
DiffEqnSolver(int N):n_grid(N){
d_x = L/n_grid;
array_size = (n_grid+1)*(n_grid+1);
val = new double* [n_grid + 1];
val[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) val[i] = val[i-1] + n_grid + 1;
ana = new double* [n_grid + 1];
ana[0] = new double [array_size];
for(int i=1;i<=n_grid;++i) ana[i] = ana[i-1] + n_grid + 1;
hipMalloc((void **)&cur, array_size*sizeof(double));
hipMalloc((void **)&old, array_size*sizeof(double));
hipMalloc((void **)&d_ana, array_size*sizeof(double));
hipMalloc((void **)&err_sum, sizeof(double));
// Setting the boundary conditions
for(int i=0;i<=n_grid;++i){
val[0][i] = left(i*d_x);
val[n_grid][i] = right(i*d_x);
val[i][0] = bottom(i*d_x);
val[i][n_grid] = top(i*d_x);
}
// Get the analytical solution
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j) ana[i][j] = analytical(i*d_x, j*d_x);
}
void init(double init_val){
for(int i=1;i<n_grid;++i) for(int j=1;j<n_grid;++j) val[i][j] = init_val;
}
// Compute errors (L2 norm)
double getError(){
double sum = 0.;
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j)
sum += pow(val[i][j] - ana[i][j],2.);
return sqrt(sum);
}
double getErrorUsingCuda(){
double init_sum = 0.;
hipMemcpy(d_ana, ana[0], array_size*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(cur, val[0], array_size*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(err_sum, &init_sum, sizeof(double), hipMemcpyHostToDevice);
int b_sz = min(MAX_BLOCK_WIDTH * MAX_BLOCK_WIDTH, array_size);
int n_blk = (array_size + b_sz - 1)/b_sz;
cudaGetError<<<n_blk, b_sz>>>(n_grid, d_ana, cur, err_sum);
hipMemcpy(&init_sum, err_sum, sizeof(double), hipMemcpyDeviceToHost);
return sqrt(init_sum);
}
// Get grid size and block size
void setUpGrid(int c_size){
cell_size = c_size;
assert(cell_size > 2 && cell_size <= MAX_BLOCK_WIDTH);
in_cell = cell_size - 2;
n_cell = (n_grid + in_cell - 2)/in_cell;
}
// One step of iteration with multiple blocks
void oneStep(double d_t){
hipMemcpy(old, val[0], array_size*sizeof(double), hipMemcpyHostToDevice);
oneIteration<<<n_cell*n_cell, cell_size*cell_size>>>(n_grid, cell_size, cur, old, d_x, d_t);
hipMemcpy(val[0], cur, array_size*sizeof(double), hipMemcpyDeviceToHost);
}
// Run multiple iterations with multiple blocks
double runIterations(int N_step, double d_t){
for(int t=0;t<N_step;++t) oneStep(d_t);
return getError();
}
// Get block size if we use only one block of threads
void setUpBlock(int nx_t){
nx_thread = nx_t;
assert(nx_thread > 0 && nx_thread <= MAX_BLOCK_WIDTH);
t_width = (n_grid-2+nx_thread)/nx_thread;
}
// Run multiple iterations with only one block of threads
double runWithOneBlock(int N_step, double d_t){
hipMemcpy(cur, val[0], array_size*sizeof(double), hipMemcpyHostToDevice);
iterationWithOneBlock<<<1, nx_thread*nx_thread>>>(n_grid, N_step, nx_thread, cur, old, d_x, d_t);
hipMemcpy(val[0], cur, array_size*sizeof(double), hipMemcpyDeviceToHost);
return getError();
}
void fileOutPut(string filename){
FILE *fp = fopen(filename.c_str(), "w");
if (fp == NULL) {
fprintf(stderr, "Can't open output file %s!\n", filename.c_str());
exit(1);
}
for(int i=0;i<=n_grid;++i) for(int j=0;j<=n_grid;++j){
fprintf(fp, "%lf %lf %lf\n", i*d_x, j*d_x, val[i][j]);
}
fclose(fp);
}
~DiffEqnSolver(){
delete [] val[0];
delete [] val;
delete [] ana[0];
delete [] ana;
hipFree(cur);
hipFree(old);
hipFree(d_ana);
hipFree(err_sum);
}
};
int main(int argc, char *argv[]){
int block_width = 16;
if(argc > 1) block_width = stoi(argv[1]);
int nL = (int)L;
DiffEqnSolver solver(nL);
solver.init(1.);
int n_batch = 21, n_step = 1000;
double dt = 0.5;
cout<<setprecision(3);
cout<<"Start running iterations:"<<endl;
clock_t start_time = clock(), end_time;
solver.setUpGrid(block_width);
for(int i=1;i<=n_batch;++i){
if(false){
string filename = "data"+to_string(i/4);
solver.fileOutPut(filename);
}
cout<<"Iteration: "<<i<<"\t error:"<<solver.runIterations(n_step, dt)<<endl;
}
//solver.setUpBlock(block_width);
//for(int i=1;i<=n_batch;++i) cout<<"Iteration: "<<i<<"\t error:"<<solver.runWithOneBlock(n_step, dt)<<endl;
end_time = clock();
cout<<"End running iterations!"<<endl<<endl;
cout<<"Time spent during iterations: "<<double(end_time-start_time)/CLOCKS_PER_SEC<<"s\n\n\n";
cout<<"================================================================================"<<endl;
return 0;
} | .text
.file "cuda_diff_modi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__oneIterationiiPdS_dd # -- Begin function _Z27__device_stub__oneIterationiiPdS_dd
.p2align 4, 0x90
.type _Z27__device_stub__oneIterationiiPdS_dd,@function
_Z27__device_stub__oneIterationiiPdS_dd: # @_Z27__device_stub__oneIterationiiPdS_dd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12oneIterationiiPdS_dd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z27__device_stub__oneIterationiiPdS_dd, .Lfunc_end0-_Z27__device_stub__oneIterationiiPdS_dd
.cfi_endproc
# -- End function
.globl _Z36__device_stub__iterationWithOneBlockiiiPdS_dd # -- Begin function _Z36__device_stub__iterationWithOneBlockiiiPdS_dd
.p2align 4, 0x90
.type _Z36__device_stub__iterationWithOneBlockiiiPdS_dd,@function
_Z36__device_stub__iterationWithOneBlockiiiPdS_dd: # @_Z36__device_stub__iterationWithOneBlockiiiPdS_dd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21iterationWithOneBlockiiiPdS_dd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z36__device_stub__iterationWithOneBlockiiiPdS_dd, .Lfunc_end1-_Z36__device_stub__iterationWithOneBlockiiiPdS_dd
.cfi_endproc
# -- End function
.globl _Z27__device_stub__cudaGetErroriPdS_S_ # -- Begin function _Z27__device_stub__cudaGetErroriPdS_S_
.p2align 4, 0x90
.type _Z27__device_stub__cudaGetErroriPdS_S_,@function
_Z27__device_stub__cudaGetErroriPdS_S_: # @_Z27__device_stub__cudaGetErroriPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cudaGetErroriPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__cudaGetErroriPdS_S_, .Lfunc_end2-_Z27__device_stub__cudaGetErroriPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI3_1:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_2:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $96, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16, %r14d
cmpl $2, %edi
jl .LBB3_32
# %bb.1:
movq 8(%rsi), %rbx
leaq 16(%rsp), %r12
movq %r12, (%rsp)
testq %rbx, %rbx
je .LBB3_2
# %bb.4:
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB3_13
# %bb.5:
testq %r14, %r14
js .LBB3_6
# %bb.8:
movq %r14, %rdi
incq %rdi
js .LBB3_9
# %bb.11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.12: # %.noexc27
movq %rax, (%rsp)
movq %r14, 16(%rsp)
.LBB3_13:
testq %r14, %r14
je .LBB3_17
# %bb.14:
movq (%rsp), %rdi
cmpq $1, %r14
jne .LBB3_16
# %bb.15:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB3_17
.LBB3_16:
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB3_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r14, 8(%rsp)
movq (%rsp), %rax
movb $0, (%rax,%r14)
movq (%rsp), %rbx
callq __errno_location
movq %rax, %r15
movl (%rax), %ebp
movl $0, (%rax)
leaq 88(%rsp), %rsi
movq %rbx, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %rbx, 88(%rsp)
je .LBB3_18
# %bb.24:
movq %rax, %r14
movslq %r14d, %rax
cmpq %r14, %rax
jne .LBB3_26
# %bb.25:
movl (%r15), %eax
cmpl $34, %eax
je .LBB3_26
# %bb.28:
testl %eax, %eax
jne .LBB3_30
# %bb.29:
movl %ebp, (%r15)
.LBB3_30: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movq (%rsp), %rdi
cmpq %r12, %rdi
je .LBB3_32
# %bb.31: # %.critedge.i.i28
callq _ZdlPv
.LBB3_32:
movq %rsp, %rdi
movl $550, %esi # imm = 0x226
callq _ZN13DiffEqnSolverC2Ei
movl (%rsp), %eax
cmpl $2, %eax
jl .LBB3_37
# %bb.33: # %.preheader.lr.ph.i
movl $1, %ecx
movq 40(%rsp), %rdx
movabsq $4607182418800017408, %rsi # imm = 0x3FF0000000000000
.p2align 4, 0x90
.LBB3_34: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_35 Depth 2
movq (%rdx,%rcx,8), %rdi
movl $1, %r8d
.p2align 4, 0x90
.LBB3_35: # Parent Loop BB3_34 Depth=1
# => This Inner Loop Header: Depth=2
movq %rsi, (%rdi,%r8,8)
incq %r8
cmpq %r8, %rax
jne .LBB3_35
# %bb.36: # %._crit_edge.i
# in Loop: Header=BB3_34 Depth=1
incq %rcx
cmpq %rax, %rcx
jne .LBB3_34
.LBB3_37: # %_ZN13DiffEqnSolver4initEd.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $3, _ZSt4cout+8(%rax)
.Ltmp2:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.38: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_39
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_43
# %bb.42:
movzbl 67(%rbx), %eax
jmp .LBB3_45
.LBB3_43:
.Ltmp4:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp5:
# %bb.44: # %.noexc61
movq (%rbx), %rax
.Ltmp6:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp7:
.LBB3_45: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp8:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp9:
# %bb.46: # %.noexc63
.Ltmp10:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp11:
# %bb.47: # %_ZNSolsEPFRSoS_E.exit
callq clock
movq %rax, %rbx
movl %r14d, 12(%rsp)
leal -2(%r14), %ecx
movl %ecx, 8(%rsp)
movl (%rsp), %eax
addl %r14d, %eax
addl $-4, %eax
cltd
idivl %ecx
movl %eax, 16(%rsp)
movl $1, %ebp
movq %rsp, %r14
.p2align 4, 0x90
.LBB3_48: # =>This Loop Header: Depth=1
# Child Loop BB3_52 Depth 2
# Child Loop BB3_57 Depth 2
# Child Loop BB3_58 Depth 3
.Ltmp12:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp13:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
# in Loop: Header=BB3_48 Depth=1
.Ltmp14:
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
.Ltmp15:
# %bb.50: # in Loop: Header=BB3_48 Depth=1
.Ltmp16:
movq %rax, %r15
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.51: # %.lr.ph.i.preheader
# in Loop: Header=BB3_48 Depth=1
movl $1000, %r12d # imm = 0x3E8
.p2align 4, 0x90
.LBB3_52: # %.lr.ph.i
# Parent Loop BB3_48 Depth=1
# => This Inner Loop Header: Depth=2
.Ltmp18:
movq %r14, %rdi
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
callq _ZN13DiffEqnSolver7oneStepEd
.Ltmp19:
# %bb.53: # %.noexc42
# in Loop: Header=BB3_52 Depth=2
decl %r12d
jne .LBB3_52
# %bb.54: # %._crit_edge.i41
# in Loop: Header=BB3_48 Depth=1
movl (%rsp), %eax
testl %eax, %eax
js .LBB3_55
# %bb.56: # %.preheader.lr.ph.i.i
# in Loop: Header=BB3_48 Depth=1
movq 40(%rsp), %rcx
movq 48(%rsp), %rdx
incq %rax
xorpd %xmm0, %xmm0
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_57: # %.preheader.i.i
# Parent Loop BB3_48 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_58 Depth 3
movq (%rcx,%rsi,8), %rdi
movq (%rdx,%rsi,8), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_58: # Parent Loop BB3_48 Depth=1
# Parent Loop BB3_57 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdi,%r9,8), %xmm1 # xmm1 = mem[0],zero
subsd (%r8,%r9,8), %xmm1
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
incq %r9
cmpq %r9, %rax
jne .LBB3_58
# %bb.59: # %._crit_edge.i.i
# in Loop: Header=BB3_57 Depth=2
incq %rsi
cmpq %rax, %rsi
jne .LBB3_57
# %bb.60: # %_ZN13DiffEqnSolver13runIterationsEid.exit
# in Loop: Header=BB3_48 Depth=1
ucomisd .LCPI3_2(%rip), %xmm0
jb .LBB3_62
.LBB3_61: # in Loop: Header=BB3_48 Depth=1
sqrtsd %xmm0, %xmm0
jmp .LBB3_63
.p2align 4, 0x90
.LBB3_55: # in Loop: Header=BB3_48 Depth=1
xorpd %xmm0, %xmm0
ucomisd .LCPI3_2(%rip), %xmm0
jae .LBB3_61
.LBB3_62: # %call.sqrt
# in Loop: Header=BB3_48 Depth=1
callq sqrt
.LBB3_63: # %_ZN13DiffEqnSolver13runIterationsEid.exit.split
# in Loop: Header=BB3_48 Depth=1
.Ltmp21:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp22:
# %bb.64: # %_ZNSolsEd.exit
# in Loop: Header=BB3_48 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_65
# %bb.67: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
# in Loop: Header=BB3_48 Depth=1
cmpb $0, 56(%r12)
je .LBB3_69
# %bb.68: # in Loop: Header=BB3_48 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_71
.p2align 4, 0x90
.LBB3_69: # in Loop: Header=BB3_48 Depth=1
.Ltmp23:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp24:
# %bb.70: # %.noexc71
# in Loop: Header=BB3_48 Depth=1
movq (%r12), %rax
.Ltmp25:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp26:
.LBB3_71: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i68
# in Loop: Header=BB3_48 Depth=1
.Ltmp27:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp28:
# %bb.72: # %.noexc73
# in Loop: Header=BB3_48 Depth=1
.Ltmp29:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp30:
# %bb.73: # %_ZNSolsEPFRSoS_E.exit45
# in Loop: Header=BB3_48 Depth=1
incl %ebp
cmpl $22, %ebp
jne .LBB3_48
# %bb.74:
callq clock
movq %rax, %r14
.Ltmp32:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.75: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_97
# %bb.76: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i77
cmpb $0, 56(%r15)
je .LBB3_81
# %bb.77:
movzbl 67(%r15), %eax
jmp .LBB3_83
.LBB3_81:
.Ltmp34:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.82: # %.noexc82
movq (%r15), %rax
.Ltmp36:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB3_83: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i79
.Ltmp38:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp39:
# %bb.84: # %.noexc84
.Ltmp40:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.85: # %_ZNSolsEPFRSoS_E.exit47
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_97
# %bb.86: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r12)
je .LBB3_88
# %bb.87:
movzbl 67(%r12), %eax
jmp .LBB3_90
.LBB3_88:
.Ltmp42:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp43:
# %bb.89: # %.noexc93
movq (%r12), %rax
.Ltmp44:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp45:
.LBB3_90: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i90
.Ltmp46:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp47:
# %bb.91: # %.noexc95
.Ltmp48:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp49:
# %bb.92: # %_ZNSolsEPFRSoS_E.exit49
.Ltmp50:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp51:
# %bb.93: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit51
subq %rbx, %r14
cvtsi2sd %r14, %xmm0
divsd .LCPI3_1(%rip), %xmm0
.Ltmp52:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp53:
# %bb.94: # %_ZNSolsEd.exit53
.Ltmp54:
movl $.L.str.5, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp55:
# %bb.95: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit55
.Ltmp56:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $80, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp57:
# %bb.96: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit57
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_97
# %bb.99: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%rbx)
je .LBB3_101
# %bb.100:
movzbl 67(%rbx), %eax
jmp .LBB3_103
.LBB3_101:
.Ltmp58:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp59:
# %bb.102: # %.noexc104
movq (%rbx), %rax
.Ltmp60:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp61:
.LBB3_103: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i101
.Ltmp62:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp63:
# %bb.104: # %.noexc106
.Ltmp64:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp65:
# %bb.105: # %_ZNSolsEPFRSoS_E.exit59
movq %rsp, %rdi
callq _ZN13DiffEqnSolverD2Ev
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_9: # %.noexc11.i
.cfi_def_cfa_offset 144
.Ltmp80:
callq _ZSt17__throw_bad_allocv
.Ltmp81:
# %bb.10: # %.noexc26
.LBB3_65:
.Ltmp69:
callq _ZSt16__throw_bad_castv
.Ltmp70:
# %bb.66: # %.noexc70
.LBB3_97: # %.invoke
.Ltmp66:
callq _ZSt16__throw_bad_castv
.Ltmp67:
# %bb.98: # %.cont
.LBB3_39:
.Ltmp72:
callq _ZSt16__throw_bad_castv
.Ltmp73:
# %bb.40: # %.noexc60
.LBB3_2:
.Ltmp84:
movl $.L.str.8, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp85:
# %bb.3: # %.noexc
.LBB3_18:
.Ltmp77:
movl $.L.str.7, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp78:
# %bb.19:
.LBB3_26: # %.critedge.i.i
.Ltmp75:
movl $.L.str.7, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp76:
# %bb.27:
.LBB3_6: # %.noexc.i
.Ltmp82:
movl $.L.str.9, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp83:
# %bb.7: # %.noexc25
.LBB3_20:
.Ltmp79:
movq %rax, %rbx
cmpl $0, (%r15)
jne .LBB3_22
# %bb.21:
movl %ebp, (%r15)
.LBB3_22: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq (%rsp), %rdi
cmpq %r12, %rdi
je .LBB3_108
# %bb.23: # %.critedge.i.i29
callq _ZdlPv
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB3_106:
.Ltmp74:
jmp .LBB3_107
.LBB3_109:
.Ltmp68:
jmp .LBB3_107
.LBB3_80: # %.loopexit.split-lp.loopexit.split-lp
.Ltmp71:
jmp .LBB3_107
.LBB3_110:
.Ltmp86:
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB3_79: # %.loopexit.split-lp.loopexit
.Ltmp31:
jmp .LBB3_107
.LBB3_78: # %.loopexit
.Ltmp20:
.LBB3_107: # %.loopexit.split-lp
movq %rax, %rbx
movq %rsp, %rdi
callq _ZN13DiffEqnSolverD2Ev
.LBB3_108:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp2-.Ltmp1 # Call between .Ltmp1 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp11-.Ltmp2 # Call between .Ltmp2 and .Ltmp11
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp17-.Ltmp12 # Call between .Ltmp12 and .Ltmp17
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp21 # Call between .Ltmp21 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp65-.Ltmp32 # Call between .Ltmp32 and .Ltmp65
.uleb128 .Ltmp68-.Lfunc_begin0 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp80-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp81-.Ltmp80 # Call between .Ltmp80 and .Ltmp81
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp70-.Ltmp69 # Call between .Ltmp69 and .Ltmp70
.uleb128 .Ltmp71-.Lfunc_begin0 # jumps to .Ltmp71
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin0 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp72-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp73-.Ltmp72 # Call between .Ltmp72 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp84-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp85-.Ltmp84 # Call between .Ltmp84 and .Ltmp85
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp77-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp76-.Ltmp77 # Call between .Ltmp77 and .Ltmp76
.uleb128 .Ltmp79-.Lfunc_begin0 # jumps to .Ltmp79
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp83-.Ltmp82 # Call between .Ltmp82 and .Ltmp83
.uleb128 .Ltmp86-.Lfunc_begin0 # jumps to .Ltmp86
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Lfunc_end3-.Ltmp83 # Call between .Ltmp83 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN13DiffEqnSolverC2Ei
.LCPI4_0:
.quad 0x4081300000000000 # double 550
.LCPI4_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI4_2:
.quad 0x402718f45d72e672 # double 11.548739357257748
.section .text._ZN13DiffEqnSolverC2Ei,"axG",@progbits,_ZN13DiffEqnSolverC2Ei,comdat
.weak _ZN13DiffEqnSolverC2Ei
.p2align 4, 0x90
.type _ZN13DiffEqnSolverC2Ei,@function
_ZN13DiffEqnSolverC2Ei: # @_ZN13DiffEqnSolverC2Ei
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r12d
movq %rdi, %rbx
movl %esi, (%rdi)
cvtsi2sd %esi, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 32(%rdi)
leal 1(%r12), %ebp
movl %ebp, %r14d
imull %r14d, %r14d
movl %r14d, 4(%rdi)
movslq %esi, %r15
cmpl $-1, %r15d
leaq 8(,%r15,8), %rax
movq $-1, %rdi
cmovgeq %rax, %rdi
movq %rdi, (%rsp) # 8-byte Spill
callq _Znam
movq %rax, %r13
movq %rax, 40(%rbx)
shlq $3, %r14
movq %r14, %rdi
callq _Znam
movq %rax, (%r13)
movq %r12, 8(%rsp) # 8-byte Spill
movl %r12d, %r13d
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.lr.ph
movl $1, %eax
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
movq 40(%rbx), %rcx
movq -8(%rcx,%rax,8), %rdx
leaq (%rdx,%r13,8), %rdx
addq $8, %rdx
movq %rdx, (%rcx,%rax,8)
incq %rax
cmpq %rax, %rbp
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq (%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, %r12
movq %rax, 48(%rbx)
movq %r14, %rdi
callq _Znam
movq %rax, (%r12)
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB4_6
# %bb.4: # %.lr.ph43
movl $1, %eax
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movq 48(%rbx), %rcx
movq -8(%rcx,%rax,8), %rdx
leaq (%rdx,%r13,8), %rdx
addq $8, %rdx
movq %rdx, (%rcx,%rax,8)
incq %rax
cmpq %rax, %rbp
jne .LBB4_5
.LBB4_6: # %._crit_edge44
leaq 56(%rbx), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 64(%rbx), %rdi
movslq 4(%rbx), %rsi
shlq $3, %rsi
callq hipMalloc
leaq 72(%rbx), %rdi
movslq 4(%rbx), %rsi
shlq $3, %rsi
callq hipMalloc
leaq 80(%rbx), %rdi
movl $8, %esi
callq hipMalloc
movl (%rbx), %eax
testl %eax, %eax
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
js .LBB4_9
# %bb.7: # %.lr.ph48.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_8: # %.lr.ph48
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movq 40(%rbx), %rcx
movq (%rcx), %rdx
movq $0, (%rdx,%r14,8)
cltq
movq (%rcx,%rax,8), %rax
movq $0, (%rax,%r14,8)
movq (%rcx,%r14,8), %rax
movq $0, (%rax)
mulsd 32(%rbx), %xmm0
mulsd .LCPI4_1(%rip), %xmm0
divsd %xmm1, %xmm0
callq sin
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd .LCPI4_2(%rip), %xmm0
movq 40(%rbx), %rax
movq (%rax,%r14,8), %rcx
movslq (%rbx), %rax
movsd %xmm0, (%rcx,%rax,8)
leaq 1(%r14), %rcx
cmpq %rax, %r14
movq %rcx, %r14
jl .LBB4_8
.LBB4_9: # %.preheader37
cmpl $0, (%rbx)
js .LBB4_15
# %bb.10: # %.preheader.preheader
xorl %r14d, %r14d
movsd .LCPI4_1(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_14: # %._crit_edge52
# in Loop: Header=BB4_11 Depth=1
leaq 1(%r14), %rax
movslq (%rbx), %rcx
cmpq %rcx, %r14
movq %rax, %r14
jge .LBB4_15
.LBB4_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
cmpl $0, (%rbx)
movsd .LCPI4_0(%rip), %xmm3 # xmm3 = mem[0],zero
js .LBB4_14
# %bb.12: # %.lr.ph51
# in Loop: Header=BB4_11 Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movsd 32(%rbx), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
mulsd %xmm1, %xmm0
mulsd 16(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, (%rsp) # 8-byte Spill
mulsd %xmm2, %xmm0
divsd %xmm3, %xmm0
callq sinh
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI4_1(%rip), %xmm0
divsd .LCPI4_0(%rip), %xmm0
callq sin
movsd .LCPI4_0(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI4_1(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movq 48(%rbx), %rax
movq (%rax,%r14,8), %rax
movsd %xmm0, (%rax,%r15,8)
leaq 1(%r15), %rax
movslq (%rbx), %rcx
cmpq %rcx, %r15
movq %rax, %r15
jl .LBB4_13
jmp .LBB4_14
.LBB4_15: # %._crit_edge55
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZN13DiffEqnSolverC2Ei, .Lfunc_end4-_ZN13DiffEqnSolverC2Ei
.cfi_endproc
# -- End function
.section .text._ZN13DiffEqnSolverD2Ev,"axG",@progbits,_ZN13DiffEqnSolverD2Ev,comdat
.weak _ZN13DiffEqnSolverD2Ev # -- Begin function _ZN13DiffEqnSolverD2Ev
.p2align 4, 0x90
.type _ZN13DiffEqnSolverD2Ev,@function
_ZN13DiffEqnSolverD2Ev: # @_ZN13DiffEqnSolverD2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 40(%rdi), %rax
movq (%rax), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
callq _ZdaPv
.LBB5_2:
movq 40(%rbx), %rdi
testq %rdi, %rdi
je .LBB5_4
# %bb.3:
callq _ZdaPv
.LBB5_4:
movq 48(%rbx), %rax
movq (%rax), %rdi
testq %rdi, %rdi
je .LBB5_6
# %bb.5:
callq _ZdaPv
.LBB5_6:
movq 48(%rbx), %rdi
testq %rdi, %rdi
je .LBB5_8
# %bb.7:
callq _ZdaPv
.LBB5_8:
movq 56(%rbx), %rdi
.Ltmp87:
callq hipFree
.Ltmp88:
# %bb.9:
movq 64(%rbx), %rdi
.Ltmp89:
callq hipFree
.Ltmp90:
# %bb.10:
movq 72(%rbx), %rdi
.Ltmp91:
callq hipFree
.Ltmp92:
# %bb.11:
movq 80(%rbx), %rdi
.Ltmp93:
callq hipFree
.Ltmp94:
# %bb.12:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB5_13:
.cfi_def_cfa_offset 16
.Ltmp95:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end5:
.size _ZN13DiffEqnSolverD2Ev, .Lfunc_end5-_ZN13DiffEqnSolverD2Ev
.cfi_endproc
.section .gcc_except_table._ZN13DiffEqnSolverD2Ev,"aG",@progbits,_ZN13DiffEqnSolverD2Ev,comdat
.p2align 2, 0x0
GCC_except_table5:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp87-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp94-.Ltmp87 # Call between .Ltmp87 and .Ltmp94
.uleb128 .Ltmp95-.Lfunc_begin1 # jumps to .Ltmp95
.byte 1 # On action: 1
.Lcst_end1:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end6:
.size __clang_call_terminate, .Lfunc_end6-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZN13DiffEqnSolver7oneStepEd,"axG",@progbits,_ZN13DiffEqnSolver7oneStepEd,comdat
.weak _ZN13DiffEqnSolver7oneStepEd # -- Begin function _ZN13DiffEqnSolver7oneStepEd
.p2align 4, 0x90
.type _ZN13DiffEqnSolver7oneStepEd,@function
_ZN13DiffEqnSolver7oneStepEd: # @_ZN13DiffEqnSolver7oneStepEd
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movsd %xmm0, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
movq 40(%rdi), %rax
movq 64(%rdi), %rdi
movq (%rax), %rsi
movslq 4(%rbx), %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rbx), %edx
movl 16(%rbx), %edi
imull %edi, %edi
imull %edx, %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movl (%rbx), %eax
movl 12(%rbx), %ecx
movq 56(%rbx), %rdx
movq 64(%rbx), %rsi
movsd 32(%rbx), %xmm0 # xmm0 = mem[0],zero
movl %eax, 4(%rsp)
movl %ecx, (%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12oneIterationiiPdS_dd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
movq 40(%rbx), %rax
movq 56(%rbx), %rsi
movq (%rax), %rdi
movslq 4(%rbx), %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _ZN13DiffEqnSolver7oneStepEd, .Lfunc_end7-_ZN13DiffEqnSolver7oneStepEd
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12oneIterationiiPdS_dd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21iterationWithOneBlockiiiPdS_dd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cudaGetErroriPdS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12oneIterationiiPdS_dd,@object # @_Z12oneIterationiiPdS_dd
.section .rodata,"a",@progbits
.globl _Z12oneIterationiiPdS_dd
.p2align 3, 0x0
_Z12oneIterationiiPdS_dd:
.quad _Z27__device_stub__oneIterationiiPdS_dd
.size _Z12oneIterationiiPdS_dd, 8
.type _Z21iterationWithOneBlockiiiPdS_dd,@object # @_Z21iterationWithOneBlockiiiPdS_dd
.globl _Z21iterationWithOneBlockiiiPdS_dd
.p2align 3, 0x0
_Z21iterationWithOneBlockiiiPdS_dd:
.quad _Z36__device_stub__iterationWithOneBlockiiiPdS_dd
.size _Z21iterationWithOneBlockiiiPdS_dd, 8
.type _Z12cudaGetErroriPdS_S_,@object # @_Z12cudaGetErroriPdS_S_
.globl _Z12cudaGetErroriPdS_S_
.p2align 3, 0x0
_Z12cudaGetErroriPdS_S_:
.quad _Z27__device_stub__cudaGetErroriPdS_S_
.size _Z12cudaGetErroriPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Start running iterations:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Iteration: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\t error:"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "End running iterations!"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time spent during iterations: "
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "s\n\n\n"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "================================================================================"
.size .L.str.6, 81
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "stoi"
.size .L.str.7, 5
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "basic_string: construction from null is not valid"
.size .L.str.8, 50
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "basic_string::_M_create"
.size .L.str.9, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12oneIterationiiPdS_dd"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21iterationWithOneBlockiiiPdS_dd"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12cudaGetErroriPdS_S_"
.size .L__unnamed_3, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__oneIterationiiPdS_dd
.addrsig_sym _Z36__device_stub__iterationWithOneBlockiiiPdS_dd
.addrsig_sym _Z27__device_stub__cudaGetErroriPdS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z12oneIterationiiPdS_dd
.addrsig_sym _Z21iterationWithOneBlockiiiPdS_dd
.addrsig_sym _Z12cudaGetErroriPdS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <math.h>
#include <time.h>
static double a = 1.0E-10;
void FillMatrix(double *matrixA, double *matrixB, int size);
void OpenFile(int *N);
void SaveFile(struct tm *start, struct tm *end, double error, double elapsed, int N);
__global__ void Multiply(double* A, double* B, double* C, int N)
{
double result; // Acumula la suma del renglon por la columna
int index; // Indice del vector
int ix; // Indica el renglon
int iy; // Toma valores solo entre 0 a N-1
int k; // Iterador
index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
__global__ void AddMatrix(double* C, int N, double* result)
{
long i;
long j;
for(i = 0; i < N; i++)
for(j = 0; j < N; j++)
*result += C[i + N * j];
}
int main(int argc, char *argv[])
{
//Variables
int N; // Tamaño de la matriz cuadrada.
size_t size; // Tamaño total en memoria.
size_t sizeDouble; // Tamaño en memoria del tipo doble.
double* h_matrixA; // Matriz A en el equipo.
double* h_matrixB; // Matriz B en el equipo.
double* h_matrixC; // Matriz C (resultado) en el equipo.
double* d_matrixA; // Matriz A en la memoria de la GPU.
double* d_matrixB; // Matriz B en la memoria de la GPU.
double* d_matrixC; // Matriz C (resultado) en la memoria de la GPU.
double* h_result; // Sumatoria de los valores de la multiplicacion de matrices en el equipo.
double* d_result; // Sumatoria de los valores de la multiplicacion de matrices en la GPU.
int Tam; // Numero de datos que se manejan
int threads; // Hilos por bloque
int blocks; // Numero de bloques necesario para procesar los datos
double estimation; // Estimacion del calculo
double error; // Error encontrado
double elapsed; // Tiempo que tomo ejecutarse el programa
time_t t; // Variable de tiempo
struct tm *start; // Hora de inicio
struct tm *end; // Hora de termino
clock_t start_clock; // Tiempo de inicio
clock_t stop_clock; // Tiempo de termino
// Inicia la variable de tiempo
t = time(NULL);
// Establece la hora de inicio
start = localtime(&t);
start_clock = clock();
// Asigna la dimension de la matriz
OpenFile(&N);
// Establece el tamaño total de la matriz en memoria
size = N * sizeof(double) * N;
// Establecec el tamaño del tipo de dato double
sizeDouble = sizeof(double);
// Asigna el numero de hilos y calcula el numero de bloques
Tam = N * N;
cudaDeviceGetAttribute(&threads, cudaDevAttrMaxThreadsPerBlock, 0);
blocks = Tam / threads;
if(Tam % threads > 0) //Si sobran datos, aumenta los bloques en 1
blocks++;
//En la memoria del equipo
h_matrixA = (double*)malloc(size);
h_matrixB = (double*)malloc(size);
h_matrixC = (double*)malloc(size);
h_result = (double*)malloc(sizeDouble);
//En la memoria de la GPU
cudaMalloc(&d_matrixA, size);
cudaMalloc(&d_matrixB, size);
cudaMalloc(&d_matrixC, size);
cudaMalloc(&d_result, sizeDouble);
// Llena las matrices h_matrixA y h_matrixB
FillMatrix(h_matrixA, h_matrixB, N);
// Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_matrixA, h_matrixA, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixB, h_matrixB, size, cudaMemcpyHostToDevice);
// Mandar llamar la multiplicacion de matrices.
Multiply<<<blocks, threads >>>(d_matrixA, d_matrixB, d_matrixC, N);
// Inicializa la variable d_result con 0.0 y lo copia a la memoria de la GPU
*h_result = 0.0;
cudaMemcpy(d_result, h_result, sizeDouble, cudaMemcpyHostToDevice);
// Suma los valores de la multiplicacion de matrices
AddMatrix<<<1, 1>>>(d_matrixC, N, d_result);
//Copia el resultado de la suma de los elementos de la matriz en la memoria
cudaMemcpy(h_result, d_result, sizeDouble, cudaMemcpyDeviceToHost);
// Calculo estimado con la formula a^2*N^3.
estimation = pow(N, 3) * pow(a, 2);
// Calcula el % de error.
error = fabs(*h_result - estimation) / estimation * 100.0;
// Libera espacio del equipo
cudaFree(d_matrixA);
cudaFree(d_matrixB);
cudaFree(d_matrixC);
cudaFree(d_result);
// Libera espacio de la tarjeta de video
free(h_matrixA);
free(h_matrixB);
free(h_matrixC);
free(h_result);
// Establece la hora en que termino de calcular
end = localtime(&t);
stop_clock = clock();
// Calcula el tiempo que tomo ejecutar el programa
elapsed = (double)(stop_clock - start_clock) / CLOCKS_PER_SEC;
// Guarda el resultado en un archivo
SaveFile(start, end, error, elapsed, N);
return 0;
}
// Llena las dos matrices con el valor constante
void FillMatrix(
double *matrixA, // Primera matriz
double *matrixB, // Segunda matriz
int N // Dimension de la matriz
)
{
int i; // Indice el renglon
int j; // Indice de la columna
for (i = 0; i < N; i++)
for (j = 0; j < N; j++)
{
matrixA[(i * N) + j] = a;
matrixB[(i * N) + j] = a;
}
}
// Abre un archivo con la dimension de la matriz
void OpenFile(
int *N // Dimension de la matriz
)
{
FILE *file;
file = fopen("parameters.dat", "r");
if (file == NULL)
printf("No se puede abrir el archivo.\n");
else
{
fscanf(file, "%d", N);
fclose(file);
}
}
// Crea un archivo de salida con la hora de inicio, de termino y el tiempo que tomo correr el programa
// Asi como el porcentaje de error
void SaveFile(
struct tm *start, // Hora de inicio
struct tm *end, // Hora de termino
double error, // Porcentaje de error
double elapsed, // Tiempo que paso
int N // Dimension de la matriz
)
{
FILE *file;
char file_name[64];
char output[50];
sprintf(file_name, "cuda-%d-%d-%d-%d-%d.txt", N, end->tm_mday, end->tm_hour, end->tm_min, end->tm_sec);
file = fopen(file_name, "w+");
strftime(output, sizeof(output), "%c", start);
fprintf(file, "Hora de inicio\n%s\n", output);
strftime(output, sizeof(output), "%c", end);
fprintf(file, "Hora de termino\n%s\n", output);
fprintf(file, "Tiempo de ejecucion\n%.15lf\n", elapsed);
fprintf(file, "Error\n%.15le\n", error);
fclose(file);
} | .file "tmpxft_0000e31e_00000000-6_matmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10FillMatrixPdS_i
.type _Z10FillMatrixPdS_i, @function
_Z10FillMatrixPdS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %r9
leaq 0(,%r9,8), %r10
negq %r9
salq $3, %r9
movq %r10, %rcx
movl $0, %r8d
movsd .LC0(%rip), %xmm0
.L5:
leaq (%rcx,%r9), %rax
.L6:
movsd %xmm0, (%rdi,%rax)
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L6
addl $1, %r8d
addq %r10, %rcx
cmpl %r8d, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z10FillMatrixPdS_i, .-_Z10FillMatrixPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "parameters.dat"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "No se puede abrir el archivo.\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.text
.globl _Z8OpenFilePi
.type _Z8OpenFilePi, @function
_Z8OpenFilePi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L12
movq %rax, %rbx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdi
call fclose@PLT
.L8:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.cfi_endproc
.LFE2059:
.size _Z8OpenFilePi, .-_Z8OpenFilePi
.section .rodata.str1.1
.LC5:
.string "cuda-%d-%d-%d-%d-%d.txt"
.LC6:
.string "w+"
.LC7:
.string "%c"
.LC8:
.string "Hora de inicio\n%s\n"
.LC9:
.string "Hora de termino\n%s\n"
.LC10:
.string "Tiempo de ejecucion\n%.15lf\n"
.LC11:
.string "Error\n%.15le\n"
.text
.globl _Z8SaveFileP2tmS0_ddi
.type _Z8SaveFileP2tmS0_ddi, @function
_Z8SaveFileP2tmS0_ddi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %r13
movq %rsi, %rbp
movsd %xmm0, (%rsp)
movsd %xmm1, 8(%rsp)
movl %edx, %r8d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbx
subq $8, %rsp
.cfi_def_cfa_offset 216
movl (%rsi), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl 4(%rsi), %eax
pushq %rax
.cfi_def_cfa_offset 232
movl 8(%rsi), %eax
pushq %rax
.cfi_def_cfa_offset 240
movl 12(%rsi), %r9d
leaq .LC5(%rip), %rcx
movl $64, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $32, %rsp
.cfi_def_cfa_offset 208
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %rbx
leaq 16(%rsp), %r12
movq %r13, %rcx
leaq .LC7(%rip), %r13
movq %r13, %rdx
movl $50, %esi
movq %r12, %rdi
call strftime@PLT
movq %r12, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rcx
movq %r13, %rdx
movl $50, %esi
movq %r12, %rdi
call strftime@PLT
movq %r12, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8SaveFileP2tmS0_ddi, .-_Z8SaveFileP2tmS0_ddi
.globl _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
.type _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i, @function
_Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8MultiplyPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i, .-_Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
.globl _Z8MultiplyPdS_S_i
.type _Z8MultiplyPdS_S_i, @function
_Z8MultiplyPdS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8MultiplyPdS_S_i, .-_Z8MultiplyPdS_S_i
.globl _Z31__device_stub__Z9AddMatrixPdiS_PdiS_
.type _Z31__device_stub__Z9AddMatrixPdiS_PdiS_, @function
_Z31__device_stub__Z9AddMatrixPdiS_PdiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9AddMatrixPdiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z9AddMatrixPdiS_PdiS_, .-_Z31__device_stub__Z9AddMatrixPdiS_PdiS_
.globl _Z9AddMatrixPdiS_
.type _Z9AddMatrixPdiS_, @function
_Z9AddMatrixPdiS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9AddMatrixPdiS_PdiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9AddMatrixPdiS_, .-_Z9AddMatrixPdiS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movq %rax, 56(%rsp)
leaq 56(%rsp), %rdi
call localtime@PLT
movq %rax, 8(%rsp)
call clock@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
call _Z8OpenFilePi
movl 16(%rsp), %eax
movslq %eax, %rbx
imulq %rbx, %rbx
salq $3, %rbx
imull %eax, %eax
movl %eax, %ebp
leaq 20(%rsp), %rdi
movl $0, %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
movl %ebp, %eax
cltd
idivl 20(%rsp)
movl %eax, %ebp
testl %edx, %edx
setg %dl
movzbl %dl, %edx
addl %edx, %ebp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $8, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl 16(%rsp), %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z10FillMatrixPdS_i
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebp, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq $0x000000000, (%r12)
movl $1, %ecx
movl $8, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $2, %ecx
movl $8, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 16(%rsp), %xmm0
movsd .LC13(%rip), %xmm1
call pow@PLT
mulsd .LC14(%rip), %xmm0
movsd (%r12), %xmm1
subsd %xmm0, %xmm1
andpd .LC15(%rip), %xmm1
divsd %xmm0, %xmm1
mulsd .LC16(%rip), %xmm1
movq %xmm1, %rbx
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq 56(%rsp), %rdi
call localtime@PLT
movq %rax, %rbp
call clock@PLT
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movl 16(%rsp), %edx
divsd .LC17(%rip), %xmm1
movq %rbx, %xmm0
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z8SaveFileP2tmS0_ddi
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl 16(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
jmp .L35
.L40:
movq 48(%rsp), %rdx
movl 16(%rsp), %esi
movq 40(%rsp), %rdi
call _Z31__device_stub__Z9AddMatrixPdiS_PdiS_
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z9AddMatrixPdiS_"
.LC19:
.string "_Z8MultiplyPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z9AddMatrixPdiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MultiplyPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -640172613
.long 1037794527
.align 8
.LC13:
.long 0
.long 1074266112
.align 8
.LC14:
.long 210911780
.long 1002937505
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC15:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC16:
.long 0
.long 1079574528
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <math.h>
#include <time.h>
static double a = 1.0E-10;
void FillMatrix(double *matrixA, double *matrixB, int size);
void OpenFile(int *N);
void SaveFile(struct tm *start, struct tm *end, double error, double elapsed, int N);
__global__ void Multiply(double* A, double* B, double* C, int N)
{
double result; // Acumula la suma del renglon por la columna
int index; // Indice del vector
int ix; // Indica el renglon
int iy; // Toma valores solo entre 0 a N-1
int k; // Iterador
index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
__global__ void AddMatrix(double* C, int N, double* result)
{
long i;
long j;
for(i = 0; i < N; i++)
for(j = 0; j < N; j++)
*result += C[i + N * j];
}
int main(int argc, char *argv[])
{
//Variables
int N; // Tamaño de la matriz cuadrada.
size_t size; // Tamaño total en memoria.
size_t sizeDouble; // Tamaño en memoria del tipo doble.
double* h_matrixA; // Matriz A en el equipo.
double* h_matrixB; // Matriz B en el equipo.
double* h_matrixC; // Matriz C (resultado) en el equipo.
double* d_matrixA; // Matriz A en la memoria de la GPU.
double* d_matrixB; // Matriz B en la memoria de la GPU.
double* d_matrixC; // Matriz C (resultado) en la memoria de la GPU.
double* h_result; // Sumatoria de los valores de la multiplicacion de matrices en el equipo.
double* d_result; // Sumatoria de los valores de la multiplicacion de matrices en la GPU.
int Tam; // Numero de datos que se manejan
int threads; // Hilos por bloque
int blocks; // Numero de bloques necesario para procesar los datos
double estimation; // Estimacion del calculo
double error; // Error encontrado
double elapsed; // Tiempo que tomo ejecutarse el programa
time_t t; // Variable de tiempo
struct tm *start; // Hora de inicio
struct tm *end; // Hora de termino
clock_t start_clock; // Tiempo de inicio
clock_t stop_clock; // Tiempo de termino
// Inicia la variable de tiempo
t = time(NULL);
// Establece la hora de inicio
start = localtime(&t);
start_clock = clock();
// Asigna la dimension de la matriz
OpenFile(&N);
// Establece el tamaño total de la matriz en memoria
size = N * sizeof(double) * N;
// Establecec el tamaño del tipo de dato double
sizeDouble = sizeof(double);
// Asigna el numero de hilos y calcula el numero de bloques
Tam = N * N;
cudaDeviceGetAttribute(&threads, cudaDevAttrMaxThreadsPerBlock, 0);
blocks = Tam / threads;
if(Tam % threads > 0) //Si sobran datos, aumenta los bloques en 1
blocks++;
//En la memoria del equipo
h_matrixA = (double*)malloc(size);
h_matrixB = (double*)malloc(size);
h_matrixC = (double*)malloc(size);
h_result = (double*)malloc(sizeDouble);
//En la memoria de la GPU
cudaMalloc(&d_matrixA, size);
cudaMalloc(&d_matrixB, size);
cudaMalloc(&d_matrixC, size);
cudaMalloc(&d_result, sizeDouble);
// Llena las matrices h_matrixA y h_matrixB
FillMatrix(h_matrixA, h_matrixB, N);
// Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_matrixA, h_matrixA, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_matrixB, h_matrixB, size, cudaMemcpyHostToDevice);
// Mandar llamar la multiplicacion de matrices.
Multiply<<<blocks, threads >>>(d_matrixA, d_matrixB, d_matrixC, N);
// Inicializa la variable d_result con 0.0 y lo copia a la memoria de la GPU
*h_result = 0.0;
cudaMemcpy(d_result, h_result, sizeDouble, cudaMemcpyHostToDevice);
// Suma los valores de la multiplicacion de matrices
AddMatrix<<<1, 1>>>(d_matrixC, N, d_result);
//Copia el resultado de la suma de los elementos de la matriz en la memoria
cudaMemcpy(h_result, d_result, sizeDouble, cudaMemcpyDeviceToHost);
// Calculo estimado con la formula a^2*N^3.
estimation = pow(N, 3) * pow(a, 2);
// Calcula el % de error.
error = fabs(*h_result - estimation) / estimation * 100.0;
// Libera espacio del equipo
cudaFree(d_matrixA);
cudaFree(d_matrixB);
cudaFree(d_matrixC);
cudaFree(d_result);
// Libera espacio de la tarjeta de video
free(h_matrixA);
free(h_matrixB);
free(h_matrixC);
free(h_result);
// Establece la hora en que termino de calcular
end = localtime(&t);
stop_clock = clock();
// Calcula el tiempo que tomo ejecutar el programa
elapsed = (double)(stop_clock - start_clock) / CLOCKS_PER_SEC;
// Guarda el resultado en un archivo
SaveFile(start, end, error, elapsed, N);
return 0;
}
// Llena las dos matrices con el valor constante
void FillMatrix(
double *matrixA, // Primera matriz
double *matrixB, // Segunda matriz
int N // Dimension de la matriz
)
{
int i; // Indice el renglon
int j; // Indice de la columna
for (i = 0; i < N; i++)
for (j = 0; j < N; j++)
{
matrixA[(i * N) + j] = a;
matrixB[(i * N) + j] = a;
}
}
// Abre un archivo con la dimension de la matriz
void OpenFile(
int *N // Dimension de la matriz
)
{
FILE *file;
file = fopen("parameters.dat", "r");
if (file == NULL)
printf("No se puede abrir el archivo.\n");
else
{
fscanf(file, "%d", N);
fclose(file);
}
}
// Crea un archivo de salida con la hora de inicio, de termino y el tiempo que tomo correr el programa
// Asi como el porcentaje de error
void SaveFile(
struct tm *start, // Hora de inicio
struct tm *end, // Hora de termino
double error, // Porcentaje de error
double elapsed, // Tiempo que paso
int N // Dimension de la matriz
)
{
FILE *file;
char file_name[64];
char output[50];
sprintf(file_name, "cuda-%d-%d-%d-%d-%d.txt", N, end->tm_mday, end->tm_hour, end->tm_min, end->tm_sec);
file = fopen(file_name, "w+");
strftime(output, sizeof(output), "%c", start);
fprintf(file, "Hora de inicio\n%s\n", output);
strftime(output, sizeof(output), "%c", end);
fprintf(file, "Hora de termino\n%s\n", output);
fprintf(file, "Tiempo de ejecucion\n%.15lf\n", elapsed);
fprintf(file, "Error\n%.15le\n", error);
fclose(file);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
static double a = 1.0E-10;
void FillMatrix(double *matrixA, double *matrixB, int size);
void OpenFile(int *N);
void SaveFile(struct tm *start, struct tm *end, double error, double elapsed, int N);
__global__ void Multiply(double* A, double* B, double* C, int N)
{
double result; // Acumula la suma del renglon por la columna
int index; // Indice del vector
int ix; // Indica el renglon
int iy; // Toma valores solo entre 0 a N-1
int k; // Iterador
index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
__global__ void AddMatrix(double* C, int N, double* result)
{
long i;
long j;
for(i = 0; i < N; i++)
for(j = 0; j < N; j++)
*result += C[i + N * j];
}
int main(int argc, char *argv[])
{
//Variables
int N; // Tamaño de la matriz cuadrada.
size_t size; // Tamaño total en memoria.
size_t sizeDouble; // Tamaño en memoria del tipo doble.
double* h_matrixA; // Matriz A en el equipo.
double* h_matrixB; // Matriz B en el equipo.
double* h_matrixC; // Matriz C (resultado) en el equipo.
double* d_matrixA; // Matriz A en la memoria de la GPU.
double* d_matrixB; // Matriz B en la memoria de la GPU.
double* d_matrixC; // Matriz C (resultado) en la memoria de la GPU.
double* h_result; // Sumatoria de los valores de la multiplicacion de matrices en el equipo.
double* d_result; // Sumatoria de los valores de la multiplicacion de matrices en la GPU.
int Tam; // Numero de datos que se manejan
int threads; // Hilos por bloque
int blocks; // Numero de bloques necesario para procesar los datos
double estimation; // Estimacion del calculo
double error; // Error encontrado
double elapsed; // Tiempo que tomo ejecutarse el programa
time_t t; // Variable de tiempo
struct tm *start; // Hora de inicio
struct tm *end; // Hora de termino
clock_t start_clock; // Tiempo de inicio
clock_t stop_clock; // Tiempo de termino
// Inicia la variable de tiempo
t = time(NULL);
// Establece la hora de inicio
start = localtime(&t);
start_clock = clock();
// Asigna la dimension de la matriz
OpenFile(&N);
// Establece el tamaño total de la matriz en memoria
size = N * sizeof(double) * N;
// Establecec el tamaño del tipo de dato double
sizeDouble = sizeof(double);
// Asigna el numero de hilos y calcula el numero de bloques
Tam = N * N;
hipDeviceGetAttribute(&threads, hipDeviceAttributeMaxThreadsPerBlock, 0);
blocks = Tam / threads;
if(Tam % threads > 0) //Si sobran datos, aumenta los bloques en 1
blocks++;
//En la memoria del equipo
h_matrixA = (double*)malloc(size);
h_matrixB = (double*)malloc(size);
h_matrixC = (double*)malloc(size);
h_result = (double*)malloc(sizeDouble);
//En la memoria de la GPU
hipMalloc(&d_matrixA, size);
hipMalloc(&d_matrixB, size);
hipMalloc(&d_matrixC, size);
hipMalloc(&d_result, sizeDouble);
// Llena las matrices h_matrixA y h_matrixB
FillMatrix(h_matrixA, h_matrixB, N);
// Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_matrixA, h_matrixA, size, hipMemcpyHostToDevice);
hipMemcpy(d_matrixB, h_matrixB, size, hipMemcpyHostToDevice);
// Mandar llamar la multiplicacion de matrices.
Multiply<<<blocks, threads >>>(d_matrixA, d_matrixB, d_matrixC, N);
// Inicializa la variable d_result con 0.0 y lo copia a la memoria de la GPU
*h_result = 0.0;
hipMemcpy(d_result, h_result, sizeDouble, hipMemcpyHostToDevice);
// Suma los valores de la multiplicacion de matrices
AddMatrix<<<1, 1>>>(d_matrixC, N, d_result);
//Copia el resultado de la suma de los elementos de la matriz en la memoria
hipMemcpy(h_result, d_result, sizeDouble, hipMemcpyDeviceToHost);
// Calculo estimado con la formula a^2*N^3.
estimation = pow(N, 3) * pow(a, 2);
// Calcula el % de error.
error = fabs(*h_result - estimation) / estimation * 100.0;
// Libera espacio del equipo
hipFree(d_matrixA);
hipFree(d_matrixB);
hipFree(d_matrixC);
hipFree(d_result);
// Libera espacio de la tarjeta de video
free(h_matrixA);
free(h_matrixB);
free(h_matrixC);
free(h_result);
// Establece la hora en que termino de calcular
end = localtime(&t);
stop_clock = clock();
// Calcula el tiempo que tomo ejecutar el programa
elapsed = (double)(stop_clock - start_clock) / CLOCKS_PER_SEC;
// Guarda el resultado en un archivo
SaveFile(start, end, error, elapsed, N);
return 0;
}
// Llena las dos matrices con el valor constante
void FillMatrix(
double *matrixA, // Primera matriz
double *matrixB, // Segunda matriz
int N // Dimension de la matriz
)
{
int i; // Indice el renglon
int j; // Indice de la columna
for (i = 0; i < N; i++)
for (j = 0; j < N; j++)
{
matrixA[(i * N) + j] = a;
matrixB[(i * N) + j] = a;
}
}
// Abre un archivo con la dimension de la matriz
void OpenFile(
int *N // Dimension de la matriz
)
{
FILE *file;
file = fopen("parameters.dat", "r");
if (file == NULL)
printf("No se puede abrir el archivo.\n");
else
{
fscanf(file, "%d", N);
fclose(file);
}
}
// Crea un archivo de salida con la hora de inicio, de termino y el tiempo que tomo correr el programa
// Asi como el porcentaje de error
void SaveFile(
struct tm *start, // Hora de inicio
struct tm *end, // Hora de termino
double error, // Porcentaje de error
double elapsed, // Tiempo que paso
int N // Dimension de la matriz
)
{
FILE *file;
char file_name[64];
char output[50];
sprintf(file_name, "cuda-%d-%d-%d-%d-%d.txt", N, end->tm_mday, end->tm_hour, end->tm_min, end->tm_sec);
file = fopen(file_name, "w+");
strftime(output, sizeof(output), "%c", start);
fprintf(file, "Hora de inicio\n%s\n", output);
strftime(output, sizeof(output), "%c", end);
fprintf(file, "Hora de termino\n%s\n", output);
fprintf(file, "Tiempo de ejecucion\n%.15lf\n", elapsed);
fprintf(file, "Error\n%.15le\n", error);
fclose(file);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
static double a = 1.0E-10;
void FillMatrix(double *matrixA, double *matrixB, int size);
void OpenFile(int *N);
void SaveFile(struct tm *start, struct tm *end, double error, double elapsed, int N);
__global__ void Multiply(double* A, double* B, double* C, int N)
{
double result; // Acumula la suma del renglon por la columna
int index; // Indice del vector
int ix; // Indica el renglon
int iy; // Toma valores solo entre 0 a N-1
int k; // Iterador
index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
__global__ void AddMatrix(double* C, int N, double* result)
{
long i;
long j;
for(i = 0; i < N; i++)
for(j = 0; j < N; j++)
*result += C[i + N * j];
}
int main(int argc, char *argv[])
{
//Variables
int N; // Tamaño de la matriz cuadrada.
size_t size; // Tamaño total en memoria.
size_t sizeDouble; // Tamaño en memoria del tipo doble.
double* h_matrixA; // Matriz A en el equipo.
double* h_matrixB; // Matriz B en el equipo.
double* h_matrixC; // Matriz C (resultado) en el equipo.
double* d_matrixA; // Matriz A en la memoria de la GPU.
double* d_matrixB; // Matriz B en la memoria de la GPU.
double* d_matrixC; // Matriz C (resultado) en la memoria de la GPU.
double* h_result; // Sumatoria de los valores de la multiplicacion de matrices en el equipo.
double* d_result; // Sumatoria de los valores de la multiplicacion de matrices en la GPU.
int Tam; // Numero de datos que se manejan
int threads; // Hilos por bloque
int blocks; // Numero de bloques necesario para procesar los datos
double estimation; // Estimacion del calculo
double error; // Error encontrado
double elapsed; // Tiempo que tomo ejecutarse el programa
time_t t; // Variable de tiempo
struct tm *start; // Hora de inicio
struct tm *end; // Hora de termino
clock_t start_clock; // Tiempo de inicio
clock_t stop_clock; // Tiempo de termino
// Inicia la variable de tiempo
t = time(NULL);
// Establece la hora de inicio
start = localtime(&t);
start_clock = clock();
// Asigna la dimension de la matriz
OpenFile(&N);
// Establece el tamaño total de la matriz en memoria
size = N * sizeof(double) * N;
// Establecec el tamaño del tipo de dato double
sizeDouble = sizeof(double);
// Asigna el numero de hilos y calcula el numero de bloques
Tam = N * N;
hipDeviceGetAttribute(&threads, hipDeviceAttributeMaxThreadsPerBlock, 0);
blocks = Tam / threads;
if(Tam % threads > 0) //Si sobran datos, aumenta los bloques en 1
blocks++;
//En la memoria del equipo
h_matrixA = (double*)malloc(size);
h_matrixB = (double*)malloc(size);
h_matrixC = (double*)malloc(size);
h_result = (double*)malloc(sizeDouble);
//En la memoria de la GPU
hipMalloc(&d_matrixA, size);
hipMalloc(&d_matrixB, size);
hipMalloc(&d_matrixC, size);
hipMalloc(&d_result, sizeDouble);
// Llena las matrices h_matrixA y h_matrixB
FillMatrix(h_matrixA, h_matrixB, N);
// Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_matrixA, h_matrixA, size, hipMemcpyHostToDevice);
hipMemcpy(d_matrixB, h_matrixB, size, hipMemcpyHostToDevice);
// Mandar llamar la multiplicacion de matrices.
Multiply<<<blocks, threads >>>(d_matrixA, d_matrixB, d_matrixC, N);
// Inicializa la variable d_result con 0.0 y lo copia a la memoria de la GPU
*h_result = 0.0;
hipMemcpy(d_result, h_result, sizeDouble, hipMemcpyHostToDevice);
// Suma los valores de la multiplicacion de matrices
AddMatrix<<<1, 1>>>(d_matrixC, N, d_result);
//Copia el resultado de la suma de los elementos de la matriz en la memoria
hipMemcpy(h_result, d_result, sizeDouble, hipMemcpyDeviceToHost);
// Calculo estimado con la formula a^2*N^3.
estimation = pow(N, 3) * pow(a, 2);
// Calcula el % de error.
error = fabs(*h_result - estimation) / estimation * 100.0;
// Libera espacio del equipo
hipFree(d_matrixA);
hipFree(d_matrixB);
hipFree(d_matrixC);
hipFree(d_result);
// Libera espacio de la tarjeta de video
free(h_matrixA);
free(h_matrixB);
free(h_matrixC);
free(h_result);
// Establece la hora en que termino de calcular
end = localtime(&t);
stop_clock = clock();
// Calcula el tiempo que tomo ejecutar el programa
elapsed = (double)(stop_clock - start_clock) / CLOCKS_PER_SEC;
// Guarda el resultado en un archivo
SaveFile(start, end, error, elapsed, N);
return 0;
}
// Llena las dos matrices con el valor constante
void FillMatrix(
double *matrixA, // Primera matriz
double *matrixB, // Segunda matriz
int N // Dimension de la matriz
)
{
int i; // Indice el renglon
int j; // Indice de la columna
for (i = 0; i < N; i++)
for (j = 0; j < N; j++)
{
matrixA[(i * N) + j] = a;
matrixB[(i * N) + j] = a;
}
}
// Abre un archivo con la dimension de la matriz
void OpenFile(
int *N // Dimension de la matriz
)
{
FILE *file;
file = fopen("parameters.dat", "r");
if (file == NULL)
printf("No se puede abrir el archivo.\n");
else
{
fscanf(file, "%d", N);
fclose(file);
}
}
// Crea un archivo de salida con la hora de inicio, de termino y el tiempo que tomo correr el programa
// Asi como el porcentaje de error
void SaveFile(
struct tm *start, // Hora de inicio
struct tm *end, // Hora de termino
double error, // Porcentaje de error
double elapsed, // Tiempo que paso
int N // Dimension de la matriz
)
{
FILE *file;
char file_name[64];
char output[50];
sprintf(file_name, "cuda-%d-%d-%d-%d-%d.txt", N, end->tm_mday, end->tm_hour, end->tm_min, end->tm_sec);
file = fopen(file_name, "w+");
strftime(output, sizeof(output), "%c", start);
fprintf(file, "Hora de inicio\n%s\n", output);
strftime(output, sizeof(output), "%c", end);
fprintf(file, "Hora de termino\n%s\n", output);
fprintf(file, "Tiempo de ejecucion\n%.15lf\n", elapsed);
fprintf(file, "Error\n%.15le\n", error);
fclose(file);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MultiplyPdS_S_i
.globl _Z8MultiplyPdS_S_i
.p2align 8
.type _Z8MultiplyPdS_S_i,@function
_Z8MultiplyPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v0, v3
v_mul_lo_u32 v2, v7, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v2
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[2:3]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[8:9], 3, v[5:6]
v_add_nc_u32_e32 v5, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b64 v[10:11], v[3:4], off
global_load_b64 v[8:9], v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[10:11], v[8:9], v[1:2]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v7, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MultiplyPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MultiplyPdS_S_i, .Lfunc_end0-_Z8MultiplyPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9AddMatrixPdiS_
.globl _Z9AddMatrixPdiS_
.p2align 8
.type _Z9AddMatrixPdiS_,@function
_Z9AddMatrixPdiS_:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_5
s_load_b64 s[4:5], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_ashr_i32 s3, s2, 31
s_mov_b64 s[8:9], 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[6:7], s[4:5], 0x0
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
s_lshl_b64 s[6:7], s[2:3], 3
.p2align 6
.LBB1_2:
s_mov_b64 s[10:11], s[0:1]
s_mov_b64 s[12:13], s[2:3]
.LBB1_3:
global_load_b64 v[3:4], v2, s[10:11]
s_add_u32 s12, s12, -1
s_addc_u32 s13, s13, -1
s_add_u32 s10, s10, s6
s_addc_u32 s11, s11, s7
s_cmp_lg_u64 s[12:13], 0
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[3:4], v[0:1]
global_store_b64 v2, v[0:1], s[4:5]
s_cbranch_scc1 .LBB1_3
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmp_lg_u64 s[8:9], s[2:3]
s_cbranch_scc1 .LBB1_2
.LBB1_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9AddMatrixPdiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 14
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9AddMatrixPdiS_, .Lfunc_end1-_Z9AddMatrixPdiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MultiplyPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MultiplyPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9AddMatrixPdiS_
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z9AddMatrixPdiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
static double a = 1.0E-10;
void FillMatrix(double *matrixA, double *matrixB, int size);
void OpenFile(int *N);
void SaveFile(struct tm *start, struct tm *end, double error, double elapsed, int N);
__global__ void Multiply(double* A, double* B, double* C, int N)
{
double result; // Acumula la suma del renglon por la columna
int index; // Indice del vector
int ix; // Indica el renglon
int iy; // Toma valores solo entre 0 a N-1
int k; // Iterador
index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
__global__ void AddMatrix(double* C, int N, double* result)
{
long i;
long j;
for(i = 0; i < N; i++)
for(j = 0; j < N; j++)
*result += C[i + N * j];
}
int main(int argc, char *argv[])
{
//Variables
int N; // Tamaño de la matriz cuadrada.
size_t size; // Tamaño total en memoria.
size_t sizeDouble; // Tamaño en memoria del tipo doble.
double* h_matrixA; // Matriz A en el equipo.
double* h_matrixB; // Matriz B en el equipo.
double* h_matrixC; // Matriz C (resultado) en el equipo.
double* d_matrixA; // Matriz A en la memoria de la GPU.
double* d_matrixB; // Matriz B en la memoria de la GPU.
double* d_matrixC; // Matriz C (resultado) en la memoria de la GPU.
double* h_result; // Sumatoria de los valores de la multiplicacion de matrices en el equipo.
double* d_result; // Sumatoria de los valores de la multiplicacion de matrices en la GPU.
int Tam; // Numero de datos que se manejan
int threads; // Hilos por bloque
int blocks; // Numero de bloques necesario para procesar los datos
double estimation; // Estimacion del calculo
double error; // Error encontrado
double elapsed; // Tiempo que tomo ejecutarse el programa
time_t t; // Variable de tiempo
struct tm *start; // Hora de inicio
struct tm *end; // Hora de termino
clock_t start_clock; // Tiempo de inicio
clock_t stop_clock; // Tiempo de termino
// Inicia la variable de tiempo
t = time(NULL);
// Establece la hora de inicio
start = localtime(&t);
start_clock = clock();
// Asigna la dimension de la matriz
OpenFile(&N);
// Establece el tamaño total de la matriz en memoria
size = N * sizeof(double) * N;
// Establecec el tamaño del tipo de dato double
sizeDouble = sizeof(double);
// Asigna el numero de hilos y calcula el numero de bloques
Tam = N * N;
hipDeviceGetAttribute(&threads, hipDeviceAttributeMaxThreadsPerBlock, 0);
blocks = Tam / threads;
if(Tam % threads > 0) //Si sobran datos, aumenta los bloques en 1
blocks++;
//En la memoria del equipo
h_matrixA = (double*)malloc(size);
h_matrixB = (double*)malloc(size);
h_matrixC = (double*)malloc(size);
h_result = (double*)malloc(sizeDouble);
//En la memoria de la GPU
hipMalloc(&d_matrixA, size);
hipMalloc(&d_matrixB, size);
hipMalloc(&d_matrixC, size);
hipMalloc(&d_result, sizeDouble);
// Llena las matrices h_matrixA y h_matrixB
FillMatrix(h_matrixA, h_matrixB, N);
// Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_matrixA, h_matrixA, size, hipMemcpyHostToDevice);
hipMemcpy(d_matrixB, h_matrixB, size, hipMemcpyHostToDevice);
// Mandar llamar la multiplicacion de matrices.
Multiply<<<blocks, threads >>>(d_matrixA, d_matrixB, d_matrixC, N);
// Inicializa la variable d_result con 0.0 y lo copia a la memoria de la GPU
*h_result = 0.0;
hipMemcpy(d_result, h_result, sizeDouble, hipMemcpyHostToDevice);
// Suma los valores de la multiplicacion de matrices
AddMatrix<<<1, 1>>>(d_matrixC, N, d_result);
//Copia el resultado de la suma de los elementos de la matriz en la memoria
hipMemcpy(h_result, d_result, sizeDouble, hipMemcpyDeviceToHost);
// Calculo estimado con la formula a^2*N^3.
estimation = pow(N, 3) * pow(a, 2);
// Calcula el % de error.
error = fabs(*h_result - estimation) / estimation * 100.0;
// Libera espacio del equipo
hipFree(d_matrixA);
hipFree(d_matrixB);
hipFree(d_matrixC);
hipFree(d_result);
// Libera espacio de la tarjeta de video
free(h_matrixA);
free(h_matrixB);
free(h_matrixC);
free(h_result);
// Establece la hora en que termino de calcular
end = localtime(&t);
stop_clock = clock();
// Calcula el tiempo que tomo ejecutar el programa
elapsed = (double)(stop_clock - start_clock) / CLOCKS_PER_SEC;
// Guarda el resultado en un archivo
SaveFile(start, end, error, elapsed, N);
return 0;
}
// Llena las dos matrices con el valor constante
void FillMatrix(
double *matrixA, // Primera matriz
double *matrixB, // Segunda matriz
int N // Dimension de la matriz
)
{
int i; // Indice el renglon
int j; // Indice de la columna
for (i = 0; i < N; i++)
for (j = 0; j < N; j++)
{
matrixA[(i * N) + j] = a;
matrixB[(i * N) + j] = a;
}
}
// Abre un archivo con la dimension de la matriz
void OpenFile(
int *N // Dimension de la matriz
)
{
FILE *file;
file = fopen("parameters.dat", "r");
if (file == NULL)
printf("No se puede abrir el archivo.\n");
else
{
fscanf(file, "%d", N);
fclose(file);
}
}
// Crea un archivo de salida con la hora de inicio, de termino y el tiempo que tomo correr el programa
// Asi como el porcentaje de error
void SaveFile(
struct tm *start, // Hora de inicio
struct tm *end, // Hora de termino
double error, // Porcentaje de error
double elapsed, // Tiempo que paso
int N // Dimension de la matriz
)
{
FILE *file;
char file_name[64];
char output[50];
sprintf(file_name, "cuda-%d-%d-%d-%d-%d.txt", N, end->tm_mday, end->tm_hour, end->tm_min, end->tm_sec);
file = fopen(file_name, "w+");
strftime(output, sizeof(output), "%c", start);
fprintf(file, "Hora de inicio\n%s\n", output);
strftime(output, sizeof(output), "%c", end);
fprintf(file, "Hora de termino\n%s\n", output);
fprintf(file, "Tiempo de ejecucion\n%.15lf\n", elapsed);
fprintf(file, "Error\n%.15le\n", error);
fclose(file);
} | .text
.file "matmult.hip"
.globl _Z23__device_stub__MultiplyPdS_S_i # -- Begin function _Z23__device_stub__MultiplyPdS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__MultiplyPdS_S_i,@function
_Z23__device_stub__MultiplyPdS_S_i: # @_Z23__device_stub__MultiplyPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8MultiplyPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__MultiplyPdS_S_i, .Lfunc_end0-_Z23__device_stub__MultiplyPdS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__AddMatrixPdiS_ # -- Begin function _Z24__device_stub__AddMatrixPdiS_
.p2align 4, 0x90
.type _Z24__device_stub__AddMatrixPdiS_,@function
_Z24__device_stub__AddMatrixPdiS_: # @_Z24__device_stub__AddMatrixPdiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9AddMatrixPdiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__AddMatrixPdiS_, .Lfunc_end1-_Z24__device_stub__AddMatrixPdiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4008000000000000 # double 3
.LCPI2_1:
.quad 0x3bc79ca10c924224 # double 1.0000000000000001E-20
.LCPI2_3:
.quad 0x4059000000000000 # double 100
.LCPI2_4:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movq %rax, 120(%rsp)
leaq 120(%rsp), %rdi
callq localtime
movq %rax, 168(%rsp) # 8-byte Spill
callq clock
movq %rax, 160(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.2:
movq %rax, %rbx
movq %rsp, %rdx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rdi
callq fclose
jmp .LBB2_3
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_3: # %_Z8OpenFilePi.exit
movslq (%rsp), %rbx
movq %rbx, %rbp
imulq %rbx, %rbp
shlq $3, %rbp
imull %ebx, %ebx
leaq 4(%rsp), %rdi
xorl %r14d, %r14d
movl $56, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movl %ebx, %eax
xorl %edx, %edx
idivl 4(%rsp)
movl %eax, %ebx
cmpl $1, %edx
sbbl $-1, %ebx
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movl $8, %edi
callq malloc
movq %rax, %r13
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movl (%rsp), %eax
testl %eax, %eax
jle .LBB2_8
# %bb.4: # %.preheader.lr.ph.i
movabsq $4457293557087583675, %rcx # imm = 0x3DDB7CDFD9D7BDBB
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movl %r14d, %edi
leaq (%r12,%rdi,8), %rsi
leaq (%r15,%rdi,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %rcx, (%rdi,%r8,8)
movq %rcx, (%rsi,%r8,8)
incq %r8
cmpq %r8, %rax
jne .LBB2_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB2_5 Depth=1
incq %rdx
addl %eax, %r14d
cmpq %rax, %rdx
jne .LBB2_5
.LBB2_8: # %_Z10FillMatrixPdS_i.exit
movabsq $4294967296, %r14 # imm = 0x100000000
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edx
movl %ebx, %edi
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 56(%rsp)
movl %esi, 116(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 116(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8MultiplyPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq $0, (%r13)
movq 8(%rsp), %rdi
movl $8, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
incq %r14
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 16(%rsp), %rax
movl (%rsp), %ecx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movl %ecx, 40(%rsp)
movq %rdx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9AddMatrixPdiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq 8(%rsp), %rsi
movl $8, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
cvtsi2sdl (%rsp), %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
mulsd .LCPI2_1(%rip), %xmm0
movsd (%r13), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
andpd .LCPI2_2(%rip), %xmm1
divsd %xmm0, %xmm1
mulsd .LCPI2_3(%rip), %xmm1
movapd %xmm1, 176(%rsp) # 16-byte Spill
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
leaq 120(%rsp), %rdi
callq localtime
movq %rax, %rbx
callq clock
subq 160(%rsp), %rax # 8-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
divsd .LCPI2_4(%rip), %xmm1
movl (%rsp), %edx
movq 168(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movaps 176(%rsp), %xmm0 # 16-byte Reload
callq _Z8SaveFileP2tmS0_ddi
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z8OpenFilePi # -- Begin function _Z8OpenFilePi
.p2align 4, 0x90
.type _Z8OpenFilePi,@function
_Z8OpenFilePi: # @_Z8OpenFilePi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB3_1
# %bb.2:
movq %rax, %r14
movl $.L.str.3, %esi
movq %rax, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB3_1:
.cfi_def_cfa_offset 32
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z8OpenFilePi, .Lfunc_end3-_Z8OpenFilePi
.cfi_endproc
# -- End function
.globl _Z10FillMatrixPdS_i # -- Begin function _Z10FillMatrixPdS_i
.p2align 4, 0x90
.type _Z10FillMatrixPdS_i,@function
_Z10FillMatrixPdS_i: # @_Z10FillMatrixPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
xorl %ecx, %ecx
movabsq $4457293557087583675, %r8 # imm = 0x3DDB7CDFD9D7BDBB
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %ecx, %r11d
leaq (%rsi,%r11,8), %r10
leaq (%rdi,%r11,8), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r8, (%r11,%rbx,8)
movq %r8, (%r10,%rbx,8)
incq %rbx
cmpq %rbx, %rax
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r9
addl %edx, %ecx
cmpq %rax, %r9
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_6: # %._crit_edge17
retq
.Lfunc_end4:
.size _Z10FillMatrixPdS_i, .Lfunc_end4-_Z10FillMatrixPdS_i
.cfi_endproc
# -- End function
.globl _Z8SaveFileP2tmS0_ddi # -- Begin function _Z8SaveFileP2tmS0_ddi
.p2align 4, 0x90
.type _Z8SaveFileP2tmS0_ddi,@function
_Z8SaveFileP2tmS0_ddi: # @_Z8SaveFileP2tmS0_ddi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl 12(%rsi), %ecx
movl 8(%rsi), %r8d
movl (%rsi), %eax
movl 4(%rsi), %r9d
movl %eax, (%rsp)
leaq 96(%rsp), %rbx
movl $.L.str.4, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq sprintf
movl $.L.str.5, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
leaq 32(%rsp), %r12
movl $50, %esi
movl $.L.str.6, %edx
movq %r12, %rdi
movq %r15, %rcx
callq strftime
movl $.L.str.7, %esi
movq %rbx, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $50, %esi
movl $.L.str.6, %edx
movq %r12, %rdi
movq %r14, %rcx
callq strftime
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $.L.str.9, %esi
movq %rbx, %rdi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movl $.L.str.10, %esi
movq %rbx, %rdi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq %rbx, %rdi
callq fclose
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8SaveFileP2tmS0_ddi, .Lfunc_end5-_Z8SaveFileP2tmS0_ddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MultiplyPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9AddMatrixPdiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MultiplyPdS_S_i,@object # @_Z8MultiplyPdS_S_i
.section .rodata,"a",@progbits
.globl _Z8MultiplyPdS_S_i
.p2align 3, 0x0
_Z8MultiplyPdS_S_i:
.quad _Z23__device_stub__MultiplyPdS_S_i
.size _Z8MultiplyPdS_S_i, 8
.type _Z9AddMatrixPdiS_,@object # @_Z9AddMatrixPdiS_
.globl _Z9AddMatrixPdiS_
.p2align 3, 0x0
_Z9AddMatrixPdiS_:
.quad _Z24__device_stub__AddMatrixPdiS_
.size _Z9AddMatrixPdiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "parameters.dat"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cuda-%d-%d-%d-%d-%d.txt"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w+"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%c"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Hora de inicio\n%s\n"
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Hora de termino\n%s\n"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Tiempo de ejecucion\n%.15lf\n"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Error\n%.15le\n"
.size .L.str.10, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MultiplyPdS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9AddMatrixPdiS_"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No se puede abrir el archivo."
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MultiplyPdS_S_i
.addrsig_sym _Z24__device_stub__AddMatrixPdiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MultiplyPdS_S_i
.addrsig_sym _Z9AddMatrixPdiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000e31e_00000000-6_matmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10FillMatrixPdS_i
.type _Z10FillMatrixPdS_i, @function
_Z10FillMatrixPdS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L3
movslq %edx, %r9
leaq 0(,%r9,8), %r10
negq %r9
salq $3, %r9
movq %r10, %rcx
movl $0, %r8d
movsd .LC0(%rip), %xmm0
.L5:
leaq (%rcx,%r9), %rax
.L6:
movsd %xmm0, (%rdi,%rax)
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L6
addl $1, %r8d
addq %r10, %rcx
cmpl %r8d, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z10FillMatrixPdS_i, .-_Z10FillMatrixPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "parameters.dat"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "No se puede abrir el archivo.\n"
.section .rodata.str1.1
.LC4:
.string "%d"
.text
.globl _Z8OpenFilePi
.type _Z8OpenFilePi, @function
_Z8OpenFilePi:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L12
movq %rax, %rbx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq %rbx, %rdi
call fclose@PLT
.L8:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.cfi_endproc
.LFE2059:
.size _Z8OpenFilePi, .-_Z8OpenFilePi
.section .rodata.str1.1
.LC5:
.string "cuda-%d-%d-%d-%d-%d.txt"
.LC6:
.string "w+"
.LC7:
.string "%c"
.LC8:
.string "Hora de inicio\n%s\n"
.LC9:
.string "Hora de termino\n%s\n"
.LC10:
.string "Tiempo de ejecucion\n%.15lf\n"
.LC11:
.string "Error\n%.15le\n"
.text
.globl _Z8SaveFileP2tmS0_ddi
.type _Z8SaveFileP2tmS0_ddi, @function
_Z8SaveFileP2tmS0_ddi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %r13
movq %rsi, %rbp
movsd %xmm0, (%rsp)
movsd %xmm1, 8(%rsp)
movl %edx, %r8d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbx
subq $8, %rsp
.cfi_def_cfa_offset 216
movl (%rsi), %eax
pushq %rax
.cfi_def_cfa_offset 224
movl 4(%rsi), %eax
pushq %rax
.cfi_def_cfa_offset 232
movl 8(%rsi), %eax
pushq %rax
.cfi_def_cfa_offset 240
movl 12(%rsi), %r9d
leaq .LC5(%rip), %rcx
movl $64, %edx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __sprintf_chk@PLT
addq $32, %rsp
.cfi_def_cfa_offset 208
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, %rbx
leaq 16(%rsp), %r12
movq %r13, %rcx
leaq .LC7(%rip), %r13
movq %r13, %rdx
movl $50, %esi
movq %r12, %rdi
call strftime@PLT
movq %r12, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbp, %rcx
movq %r13, %rdx
movl $50, %esi
movq %r12, %rdi
call strftime@PLT
movq %r12, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC11(%rip), %rdx
movl $2, %esi
movq %rbx, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call fclose@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8SaveFileP2tmS0_ddi, .-_Z8SaveFileP2tmS0_ddi
.globl _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
.type _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i, @function
_Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8MultiplyPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i, .-_Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
.globl _Z8MultiplyPdS_S_i
.type _Z8MultiplyPdS_S_i, @function
_Z8MultiplyPdS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8MultiplyPdS_S_i, .-_Z8MultiplyPdS_S_i
.globl _Z31__device_stub__Z9AddMatrixPdiS_PdiS_
.type _Z31__device_stub__Z9AddMatrixPdiS_PdiS_, @function
_Z31__device_stub__Z9AddMatrixPdiS_PdiS_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9AddMatrixPdiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z9AddMatrixPdiS_PdiS_, .-_Z31__device_stub__Z9AddMatrixPdiS_PdiS_
.globl _Z9AddMatrixPdiS_
.type _Z9AddMatrixPdiS_, @function
_Z9AddMatrixPdiS_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9AddMatrixPdiS_PdiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z9AddMatrixPdiS_, .-_Z9AddMatrixPdiS_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movq %rax, 56(%rsp)
leaq 56(%rsp), %rdi
call localtime@PLT
movq %rax, 8(%rsp)
call clock@PLT
movq %rax, %r15
leaq 16(%rsp), %rdi
call _Z8OpenFilePi
movl 16(%rsp), %eax
movslq %eax, %rbx
imulq %rbx, %rbx
salq $3, %rbx
imull %eax, %eax
movl %eax, %ebp
leaq 20(%rsp), %rdi
movl $0, %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
movl %ebp, %eax
cltd
idivl 20(%rsp)
movl %eax, %ebp
testl %edx, %edx
setg %dl
movzbl %dl, %edx
addl %edx, %ebp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $8, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl 16(%rsp), %edx
movq %r13, %rsi
movq %r14, %rdi
call _Z10FillMatrixPdS_i
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 20(%rsp), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ebp, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq $0x000000000, (%r12)
movl $1, %ecx
movl $8, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movl $2, %ecx
movl $8, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 16(%rsp), %xmm0
movsd .LC13(%rip), %xmm1
call pow@PLT
mulsd .LC14(%rip), %xmm0
movsd (%r12), %xmm1
subsd %xmm0, %xmm1
andpd .LC15(%rip), %xmm1
divsd %xmm0, %xmm1
mulsd .LC16(%rip), %xmm1
movq %xmm1, %rbx
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq 56(%rsp), %rdi
call localtime@PLT
movq %rax, %rbp
call clock@PLT
subq %r15, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movl 16(%rsp), %edx
divsd .LC17(%rip), %xmm1
movq %rbx, %xmm0
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z8SaveFileP2tmS0_ddi
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl 16(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z8MultiplyPdS_S_iPdS_S_i
jmp .L35
.L40:
movq 48(%rsp), %rdx
movl 16(%rsp), %esi
movq 40(%rsp), %rdi
call _Z31__device_stub__Z9AddMatrixPdiS_PdiS_
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z9AddMatrixPdiS_"
.LC19:
.string "_Z8MultiplyPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z9AddMatrixPdiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MultiplyPdS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -640172613
.long 1037794527
.align 8
.LC13:
.long 0
.long 1074266112
.align 8
.LC14:
.long 210911780
.long 1002937505
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC15:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC16:
.long 0
.long 1079574528
.align 8
.LC17:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmult.hip"
.globl _Z23__device_stub__MultiplyPdS_S_i # -- Begin function _Z23__device_stub__MultiplyPdS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__MultiplyPdS_S_i,@function
_Z23__device_stub__MultiplyPdS_S_i: # @_Z23__device_stub__MultiplyPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8MultiplyPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__MultiplyPdS_S_i, .Lfunc_end0-_Z23__device_stub__MultiplyPdS_S_i
.cfi_endproc
# -- End function
.globl _Z24__device_stub__AddMatrixPdiS_ # -- Begin function _Z24__device_stub__AddMatrixPdiS_
.p2align 4, 0x90
.type _Z24__device_stub__AddMatrixPdiS_,@function
_Z24__device_stub__AddMatrixPdiS_: # @_Z24__device_stub__AddMatrixPdiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9AddMatrixPdiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__AddMatrixPdiS_, .Lfunc_end1-_Z24__device_stub__AddMatrixPdiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4008000000000000 # double 3
.LCPI2_1:
.quad 0x3bc79ca10c924224 # double 1.0000000000000001E-20
.LCPI2_3:
.quad 0x4059000000000000 # double 100
.LCPI2_4:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq time
movq %rax, 120(%rsp)
leaq 120(%rsp), %rdi
callq localtime
movq %rax, 168(%rsp) # 8-byte Spill
callq clock
movq %rax, 160(%rsp) # 8-byte Spill
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB2_1
# %bb.2:
movq %rax, %rbx
movq %rsp, %rdx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rdi
callq fclose
jmp .LBB2_3
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB2_3: # %_Z8OpenFilePi.exit
movslq (%rsp), %rbx
movq %rbx, %rbp
imulq %rbx, %rbp
shlq $3, %rbp
imull %ebx, %ebx
leaq 4(%rsp), %rdi
xorl %r14d, %r14d
movl $56, %esi
xorl %edx, %edx
callq hipDeviceGetAttribute
movl %ebx, %eax
xorl %edx, %edx
idivl 4(%rsp)
movl %eax, %ebx
cmpl $1, %edx
sbbl $-1, %ebx
movq %rbp, %rdi
callq malloc
movq %rax, %r15
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movl $8, %edi
callq malloc
movq %rax, %r13
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movl (%rsp), %eax
testl %eax, %eax
jle .LBB2_8
# %bb.4: # %.preheader.lr.ph.i
movabsq $4457293557087583675, %rcx # imm = 0x3DDB7CDFD9D7BDBB
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
movl %r14d, %edi
leaq (%r12,%rdi,8), %rsi
leaq (%r15,%rdi,8), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %rcx, (%rdi,%r8,8)
movq %rcx, (%rsi,%r8,8)
incq %r8
cmpq %r8, %rax
jne .LBB2_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB2_5 Depth=1
incq %rdx
addl %eax, %r14d
cmpq %rax, %rdx
jne .LBB2_5
.LBB2_8: # %_Z10FillMatrixPdS_i.exit
movabsq $4294967296, %r14 # imm = 0x100000000
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edx
movl %ebx, %edi
orq %r14, %rdi
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl (%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 56(%rsp)
movl %esi, 116(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 116(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8MultiplyPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq $0, (%r13)
movq 8(%rsp), %rdi
movl $8, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
incq %r14
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 16(%rsp), %rax
movl (%rsp), %ecx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movl %ecx, 40(%rsp)
movq %rdx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9AddMatrixPdiS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq 8(%rsp), %rsi
movl $8, %edx
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
cvtsi2sdl (%rsp), %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
mulsd .LCPI2_1(%rip), %xmm0
movsd (%r13), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
andpd .LCPI2_2(%rip), %xmm1
divsd %xmm0, %xmm1
mulsd .LCPI2_3(%rip), %xmm1
movapd %xmm1, 176(%rsp) # 16-byte Spill
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
leaq 120(%rsp), %rdi
callq localtime
movq %rax, %rbx
callq clock
subq 160(%rsp), %rax # 8-byte Folded Reload
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
divsd .LCPI2_4(%rip), %xmm1
movl (%rsp), %edx
movq 168(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movaps 176(%rsp), %xmm0 # 16-byte Reload
callq _Z8SaveFileP2tmS0_ddi
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z8OpenFilePi # -- Begin function _Z8OpenFilePi
.p2align 4, 0x90
.type _Z8OpenFilePi,@function
_Z8OpenFilePi: # @_Z8OpenFilePi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
testq %rax, %rax
je .LBB3_1
# %bb.2:
movq %rax, %r14
movl $.L.str.3, %esi
movq %rax, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB3_1:
.cfi_def_cfa_offset 32
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z8OpenFilePi, .Lfunc_end3-_Z8OpenFilePi
.cfi_endproc
# -- End function
.globl _Z10FillMatrixPdS_i # -- Begin function _Z10FillMatrixPdS_i
.p2align 4, 0x90
.type _Z10FillMatrixPdS_i,@function
_Z10FillMatrixPdS_i: # @_Z10FillMatrixPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
xorl %ecx, %ecx
movabsq $4457293557087583675, %r8 # imm = 0x3DDB7CDFD9D7BDBB
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %ecx, %r11d
leaq (%rsi,%r11,8), %r10
leaq (%rdi,%r11,8), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r8, (%r11,%rbx,8)
movq %r8, (%r10,%rbx,8)
incq %rbx
cmpq %rbx, %rax
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r9
addl %edx, %ecx
cmpq %rax, %r9
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_6: # %._crit_edge17
retq
.Lfunc_end4:
.size _Z10FillMatrixPdS_i, .Lfunc_end4-_Z10FillMatrixPdS_i
.cfi_endproc
# -- End function
.globl _Z8SaveFileP2tmS0_ddi # -- Begin function _Z8SaveFileP2tmS0_ddi
.p2align 4, 0x90
.type _Z8SaveFileP2tmS0_ddi,@function
_Z8SaveFileP2tmS0_ddi: # @_Z8SaveFileP2tmS0_ddi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, %r15
movl 12(%rsi), %ecx
movl 8(%rsi), %r8d
movl (%rsi), %eax
movl 4(%rsi), %r9d
movl %eax, (%rsp)
leaq 96(%rsp), %rbx
movl $.L.str.4, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq sprintf
movl $.L.str.5, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
leaq 32(%rsp), %r12
movl $50, %esi
movl $.L.str.6, %edx
movq %r12, %rdi
movq %r15, %rcx
callq strftime
movl $.L.str.7, %esi
movq %rbx, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $50, %esi
movl $.L.str.6, %edx
movq %r12, %rdi
movq %r14, %rcx
callq strftime
movl $.L.str.8, %esi
movq %rbx, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq fprintf
movl $.L.str.9, %esi
movq %rbx, %rdi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movl $.L.str.10, %esi
movq %rbx, %rdi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq %rbx, %rdi
callq fclose
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8SaveFileP2tmS0_ddi, .Lfunc_end5-_Z8SaveFileP2tmS0_ddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MultiplyPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9AddMatrixPdiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MultiplyPdS_S_i,@object # @_Z8MultiplyPdS_S_i
.section .rodata,"a",@progbits
.globl _Z8MultiplyPdS_S_i
.p2align 3, 0x0
_Z8MultiplyPdS_S_i:
.quad _Z23__device_stub__MultiplyPdS_S_i
.size _Z8MultiplyPdS_S_i, 8
.type _Z9AddMatrixPdiS_,@object # @_Z9AddMatrixPdiS_
.globl _Z9AddMatrixPdiS_
.p2align 3, 0x0
_Z9AddMatrixPdiS_:
.quad _Z24__device_stub__AddMatrixPdiS_
.size _Z9AddMatrixPdiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "parameters.dat"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cuda-%d-%d-%d-%d-%d.txt"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "w+"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%c"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Hora de inicio\n%s\n"
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Hora de termino\n%s\n"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Tiempo de ejecucion\n%.15lf\n"
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Error\n%.15le\n"
.size .L.str.10, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MultiplyPdS_S_i"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9AddMatrixPdiS_"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "No se puede abrir el archivo."
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MultiplyPdS_S_i
.addrsig_sym _Z24__device_stub__AddMatrixPdiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MultiplyPdS_S_i
.addrsig_sym _Z9AddMatrixPdiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define size 5
__global__ void addvec(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int a[size] = {1, 2, 3, 4, 5};
const int b[size] = {10, 20, 30, 40, 50};
int c[size] = {0}; int *da, *db, *dc;
cudaMalloc((void**)& dc, size*sizeof(int));
cudaMalloc((void**)& da, size*sizeof(int));
cudaMalloc((void**)& db, size*sizeof(int));
cudaMemcpy(da, a, size*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(db, b, size*sizeof(int), cudaMemcpyHostToDevice);
addvec<<<1, size>>>(dc, da, db);
cudaMemcpy(c, dc, size*sizeof(int), cudaMemcpyDeviceToHost);
printf("{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n", c[0], c[1], c[2], c[3], c[4]);
cudaThreadSynchronize();
cudaFree(dc); cudaFree(da); cudaFree(db);
return 0;
} | code for sm_80
Function : _Z6addvecPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define size 5
__global__ void addvec(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int a[size] = {1, 2, 3, 4, 5};
const int b[size] = {10, 20, 30, 40, 50};
int c[size] = {0}; int *da, *db, *dc;
cudaMalloc((void**)& dc, size*sizeof(int));
cudaMalloc((void**)& da, size*sizeof(int));
cudaMalloc((void**)& db, size*sizeof(int));
cudaMemcpy(da, a, size*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(db, b, size*sizeof(int), cudaMemcpyHostToDevice);
addvec<<<1, size>>>(dc, da, db);
cudaMemcpy(c, dc, size*sizeof(int), cudaMemcpyDeviceToHost);
printf("{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n", c[0], c[1], c[2], c[3], c[4]);
cudaThreadSynchronize();
cudaFree(dc); cudaFree(da); cudaFree(db);
return 0;
} | .file "tmpxft_00162137_00000000-6_addVec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
.type _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_, @function
_Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addvecPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_, .-_Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
.globl _Z6addvecPiPKiS1_
.type _Z6addvecPiPKiS1_, @function
_Z6addvecPiPKiS1_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addvecPiPKiS1_, .-_Z6addvecPiPKiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movl $0, 128(%rsp)
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
movl 136(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 140(%rsp), %r9d
movl 136(%rsp), %r8d
movl 132(%rsp), %ecx
movl 128(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
call cudaThreadSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6addvecPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addvecPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define size 5
__global__ void addvec(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int a[size] = {1, 2, 3, 4, 5};
const int b[size] = {10, 20, 30, 40, 50};
int c[size] = {0}; int *da, *db, *dc;
cudaMalloc((void**)& dc, size*sizeof(int));
cudaMalloc((void**)& da, size*sizeof(int));
cudaMalloc((void**)& db, size*sizeof(int));
cudaMemcpy(da, a, size*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(db, b, size*sizeof(int), cudaMemcpyHostToDevice);
addvec<<<1, size>>>(dc, da, db);
cudaMemcpy(c, dc, size*sizeof(int), cudaMemcpyDeviceToHost);
printf("{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n", c[0], c[1], c[2], c[3], c[4]);
cudaThreadSynchronize();
cudaFree(dc); cudaFree(da); cudaFree(db);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define size 5
__global__ void addvec(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int a[size] = {1, 2, 3, 4, 5};
const int b[size] = {10, 20, 30, 40, 50};
int c[size] = {0}; int *da, *db, *dc;
hipMalloc((void**)& dc, size*sizeof(int));
hipMalloc((void**)& da, size*sizeof(int));
hipMalloc((void**)& db, size*sizeof(int));
hipMemcpy(da, a, size*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(db, b, size*sizeof(int), hipMemcpyHostToDevice);
addvec<<<1, size>>>(dc, da, db);
hipMemcpy(c, dc, size*sizeof(int), hipMemcpyDeviceToHost);
printf("{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n", c[0], c[1], c[2], c[3], c[4]);
hipDeviceSynchronize();
hipFree(dc); hipFree(da); hipFree(db);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define size 5
__global__ void addvec(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int a[size] = {1, 2, 3, 4, 5};
const int b[size] = {10, 20, 30, 40, 50};
int c[size] = {0}; int *da, *db, *dc;
hipMalloc((void**)& dc, size*sizeof(int));
hipMalloc((void**)& da, size*sizeof(int));
hipMalloc((void**)& db, size*sizeof(int));
hipMemcpy(da, a, size*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(db, b, size*sizeof(int), hipMemcpyHostToDevice);
addvec<<<1, size>>>(dc, da, db);
hipMemcpy(c, dc, size*sizeof(int), hipMemcpyDeviceToHost);
printf("{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n", c[0], c[1], c[2], c[3], c[4]);
hipDeviceSynchronize();
hipFree(dc); hipFree(da); hipFree(db);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addvecPiPKiS1_
.globl _Z6addvecPiPKiS1_
.p2align 8
.type _Z6addvecPiPKiS1_,@function
_Z6addvecPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addvecPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addvecPiPKiS1_, .Lfunc_end0-_Z6addvecPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addvecPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6addvecPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define size 5
__global__ void addvec(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int a[size] = {1, 2, 3, 4, 5};
const int b[size] = {10, 20, 30, 40, 50};
int c[size] = {0}; int *da, *db, *dc;
hipMalloc((void**)& dc, size*sizeof(int));
hipMalloc((void**)& da, size*sizeof(int));
hipMalloc((void**)& db, size*sizeof(int));
hipMemcpy(da, a, size*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(db, b, size*sizeof(int), hipMemcpyHostToDevice);
addvec<<<1, size>>>(dc, da, db);
hipMemcpy(c, dc, size*sizeof(int), hipMemcpyDeviceToHost);
printf("{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n", c[0], c[1], c[2], c[3], c[4]);
hipDeviceSynchronize();
hipFree(dc); hipFree(da); hipFree(db);
return 0;
} | .text
.file "addVec.hip"
.globl _Z21__device_stub__addvecPiPKiS1_ # -- Begin function _Z21__device_stub__addvecPiPKiS1_
.p2align 4, 0x90
.type _Z21__device_stub__addvecPiPKiS1_,@function
_Z21__device_stub__addvecPiPKiS1_: # @_Z21__device_stub__addvecPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addvecPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__addvecPiPKiS1_, .Lfunc_end0-_Z21__device_stub__addvecPiPKiS1_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 192(%rsp)
movl $5, 208(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 160(%rsp)
movl $50, 176(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movl $0, 48(%rsp)
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6addvecPiPKiS1_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl 36(%rsp), %edx
movl 40(%rsp), %ecx
movl 44(%rsp), %r8d
movl 48(%rsp), %r9d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addvecPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addvecPiPKiS1_,@object # @_Z6addvecPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z6addvecPiPKiS1_
.p2align 3, 0x0
_Z6addvecPiPKiS1_:
.quad _Z21__device_stub__addvecPiPKiS1_
.size _Z6addvecPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n"
.size .L.str, 63
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addvecPiPKiS1_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addvecPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addvecPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6addvecPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addvecPiPKiS1_
.globl _Z6addvecPiPKiS1_
.p2align 8
.type _Z6addvecPiPKiS1_,@function
_Z6addvecPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addvecPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addvecPiPKiS1_, .Lfunc_end0-_Z6addvecPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addvecPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6addvecPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00162137_00000000-6_addVec.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
.type _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_, @function
_Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addvecPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_, .-_Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
.globl _Z6addvecPiPKiS1_
.type _Z6addvecPiPKiS1_, @function
_Z6addvecPiPKiS1_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addvecPiPKiS1_, .-_Z6addvecPiPKiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $2, 52(%rsp)
movl $3, 56(%rsp)
movl $4, 60(%rsp)
movl $5, 64(%rsp)
movl $10, 80(%rsp)
movl $20, 84(%rsp)
movl $30, 88(%rsp)
movl $40, 92(%rsp)
movl $50, 96(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movl $0, 128(%rsp)
leaq 16(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
movq %rsp, %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $20, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $20, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 112(%rsp), %rdi
movl $2, %ecx
movl $20, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
subq $8, %rsp
.cfi_def_cfa_offset 168
movl 136(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 176
movl 140(%rsp), %r9d
movl 136(%rsp), %r8d
movl 132(%rsp), %ecx
movl 128(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
call cudaThreadSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 16(%rsp), %rdi
call _Z31__device_stub__Z6addvecPiPKiS1_PiPKiS1_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6addvecPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addvecPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addVec.hip"
.globl _Z21__device_stub__addvecPiPKiS1_ # -- Begin function _Z21__device_stub__addvecPiPKiS1_
.p2align 4, 0x90
.type _Z21__device_stub__addvecPiPKiS1_,@function
_Z21__device_stub__addvecPiPKiS1_: # @_Z21__device_stub__addvecPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addvecPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__addvecPiPKiS1_, .Lfunc_end0-_Z21__device_stub__addvecPiPKiS1_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI1_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 192(%rsp)
movl $5, 208(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 160(%rsp)
movl $50, 176(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movl $0, 48(%rsp)
leaq 8(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $20, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $20, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $20, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6addvecPiPKiS1_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $20, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl 36(%rsp), %edx
movl 40(%rsp), %ecx
movl 44(%rsp), %r8d
movl 48(%rsp), %r9d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addvecPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addvecPiPKiS1_,@object # @_Z6addvecPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z6addvecPiPKiS1_
.p2align 3, 0x0
_Z6addvecPiPKiS1_:
.quad _Z21__device_stub__addvecPiPKiS1_
.size _Z6addvecPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "{1, 2, 3, 4, 5} + {10, 20, 30, 40, 50} = {%d, %d, %d, %d, %d}\n"
.size .L.str, 63
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addvecPiPKiS1_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addvecPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addvecPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_forwardElimination( float * fullMatrix, float * B, unsigned int nComp ) {
unsigned int t = threadIdx.x;
unsigned int baseIndex = t*nComp*nComp;
unsigned int i,j,k;
for ( i = 0; i < nComp - 1; i++ )
for ( j = i + 1; j < nComp; j++ ) {
double div = fullMatrix[baseIndex+ j*nComp+i ] / fullMatrix[baseIndex+ i*nComp+ i ];
for ( k = 0; k < nComp; k++ )
fullMatrix[ baseIndex+j*nComp+k ] -= div * fullMatrix[baseIndex+ i *nComp+ k ];
B[ baseIndex+j ] -= div * B[ baseIndex+i ];
}
__syncthreads();
} | code for sm_80
Function : _Z25kernel_forwardEliminationPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc80003f05270 */
/*0030*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fc80007ffe0ff */
/*0040*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004702670 */
/*0050*/ @P0 BRA 0x9d0 ; /* 0x0000097000000947 */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IADD3 R4, R2, -c[0x0][0x170], RZ ; /* 0x80005c0002047a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD R6, R3, c[0x0][0x170], RZ ; /* 0x00005c0003067a24 */
/* 0x001fe400078e02ff */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a24 */
/* 0x000fc600078e02ff */
/*00d0*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f06070 */
/*00f0*/ @P0 BRA 0x9a0 ; /* 0x000008a000000947 */
/* 0x001fea0003800000 */
/*0100*/ IMAD R8, R3.reuse, c[0x0][0x170], R6.reuse ; /* 0x00005c0003087a24 */
/* 0x140fe400078e0206 */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.IADD R10, R3, 0x1, R6 ; /* 0x00000001030a7824 */
/* 0x000fe200078e0206 */
/*0130*/ IADD3 R9, R8.reuse, 0x3, RZ ; /* 0x0000000308097810 */
/* 0x040fe20007ffe0ff */
/*0140*/ IMAD.IADD R12, R8.reuse, 0x1, R3 ; /* 0x00000001080c7824 */
/* 0x040fe200078e0203 */
/*0150*/ IADD3 R22, R8, 0x1, RZ ; /* 0x0000000108167810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e000d */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0180*/ IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e000d */
/*0190*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD R24, R7, c[0x0][0x170], R6 ; /* 0x00005c0007187a24 */
/* 0x000fe400078e0206 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.IADD R14, R24, 0x1, R3 ; /* 0x00000001180e7824 */
/* 0x000fc800078e0203 */
/*01d0*/ IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e000f */
/*01e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ BSSY B0, 0x2b0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0200*/ MUFU.RCP R17, R16 ; /* 0x0000001000117308 */
/* 0x005e300000001000 */
/*0210*/ FCHK P0, R15, R16 ; /* 0x000000100f007302 */
/* 0x008e620000000000 */
/*0220*/ FFMA R18, -R16, R17, 1 ; /* 0x3f80000010127423 */
/* 0x001fc80000000111 */
/*0230*/ FFMA R18, R17, R18, R17 ; /* 0x0000001211127223 */
/* 0x000fc80000000011 */
/*0240*/ FFMA R17, R15, R18, RZ ; /* 0x000000120f117223 */
/* 0x000fc800000000ff */
/*0250*/ FFMA R19, -R16, R17, R15 ; /* 0x0000001110137223 */
/* 0x000fc8000000010f */
/*0260*/ FFMA R17, R18, R19, R17 ; /* 0x0000001312117223 */
/* 0x000fe20000000011 */
/*0270*/ @!P0 BRA 0x2a0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0280*/ MOV R18, 0x2a0 ; /* 0x000002a000127802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x9f0 ; /* 0x0000075000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*02c0*/ F2F.F64.F32 R14, R17 ; /* 0x00000011000e7310 */
/* 0x0000620000201800 */
/*02d0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*02e0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fd400078e00ff */
/*02f0*/ @!P0 BRA 0x650 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R25, R24.reuse, 0x3, RZ ; /* 0x0000000318197810 */
/* 0x041fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R26, R24, 0x1, RZ ; /* 0x00000001181a7810 */
/* 0x000fe20007ffe0ff */
/*0330*/ IMAD.MOV.U32 R23, RZ, RZ, R9 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0009 */
/*0340*/ IMAD.IADD R17, R8, 0x1, R27.reuse ; /* 0x0000000108117824 */
/* 0x100fe400078e021b */
/*0350*/ IMAD.MOV.U32 R28, RZ, RZ, 0x4 ; /* 0x00000004ff1c7424 */
/* 0x001fe400078e00ff */
/*0360*/ IMAD.IADD R21, R24, 0x1, R27 ; /* 0x0000000118157824 */
/* 0x000fe400078e021b */
/*0370*/ IMAD.WIDE.U32 R16, R17, R28, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e001c */
/*0380*/ IMAD.WIDE.U32 R20, R21, R28, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe200078e001c */
/*0390*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x001ee2000c1e1900 */
/*03b0*/ F2F.F64.F32 R18, R29 ; /* 0x0000001d00127310 */
/* 0x004ff00000201800 */
/*03c0*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x008e240000201800 */
/*03d0*/ DFMA R18, -R14, R18, R16 ; /* 0x000000120e12722b */
/* 0x0030440000000110 */
/*03e0*/ IMAD.IADD R17, R22, 0x1, R27 ; /* 0x0000000116117824 */
/* 0x001fc800078e021b */
/*03f0*/ F2F.F32.F64 R29, R18 ; /* 0x00000012001d7310 */
/* 0x0020620000301000 */
/*0400*/ IMAD.WIDE.U32 R16, R17, R28, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e001c */
/*0410*/ IMAD.IADD R19, R26, 0x1, R27 ; /* 0x000000011a137824 */
/* 0x001fc800078e021b */
/*0420*/ IMAD.WIDE.U32 R18, R19, R28, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fe200078e001c */
/*0430*/ STG.E [R20.64], R29 ; /* 0x0000001d14007986 */
/* 0x0021e8000c101904 */
/*0440*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x0010a8000c1e1900 */
/*0450*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x001ee2000c1e1900 */
/*0460*/ F2F.F64.F32 R20, R29 ; /* 0x0000001d00147310 */
/* 0x004ff00000201800 */
/*0470*/ F2F.F64.F32 R16, R17 ; /* 0x0000001100107310 */
/* 0x008e240000201800 */
/*0480*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x0010440000000110 */
/*0490*/ IADD3 R21, R23, -0x1, RZ ; /* 0xffffffff17157810 */
/* 0x001fc80007ffe0ff */
/*04a0*/ F2F.F32.F64 R29, R16 ; /* 0x00000010001d7310 */
/* 0x0020620000301000 */
/*04b0*/ IMAD.WIDE.U32 R20, R21, R28, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe200078e001c */
/*04c0*/ IADD3 R16, R25, -0x1, RZ ; /* 0xffffffff19107810 */
/* 0x001fca0007ffe0ff */
/*04d0*/ IMAD.WIDE.U32 R16, R16, R28, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fe200078e001c */
/*04e0*/ STG.E [R18.64], R29 ; /* 0x0000001d12007986 */
/* 0x0021e8000c101904 */
/*04f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000228000c1e1900 */
/*0500*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002ea2000c1e1900 */
/*0510*/ F2F.F64.F32 R18, R20 ; /* 0x0000001400127310 */
/* 0x001ff00000201800 */
/*0520*/ F2F.F64.F32 R20, R21 ; /* 0x0000001500147310 */
/* 0x004e240000201800 */
/*0530*/ DFMA R20, -R14, R18, R20 ; /* 0x000000120e14722b */
/* 0x0010440000000114 */
/*0540*/ IMAD.WIDE.U32 R18, R23, R28, c[0x0][0x160] ; /* 0x0000580017127625 */
/* 0x001fc800078e001c */
/*0550*/ F2F.F32.F64 R29, R20 ; /* 0x00000014001d7310 */
/* 0x002e240000301000 */
/*0560*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x0011e8000c101904 */
/*0570*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE.U32 R28, R25, R28, c[0x0][0x160] ; /* 0x00005800191c7625 */
/* 0x001fca00078e001c */
/*0590*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x002ee2000c1e1900 */
/*05a0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fca0007ffe0ff */
/*05b0*/ IMAD.IADD R16, R4, 0x1, R27 ; /* 0x0000000104107824 */
/* 0x000fca00078e021b */
/*05c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*05d0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ F2F.F64.F32 R20, R18 ; /* 0x0000001200147310 */
/* 0x004ff00000201800 */
/*0600*/ F2F.F64.F32 R18, R19 ; /* 0x0000001300127310 */
/* 0x008e240000201800 */
/*0610*/ DFMA R18, -R14, R20, R18 ; /* 0x000000140e12722b */
/* 0x001e0c0000000112 */
/*0620*/ F2F.F32.F64 R21, R18 ; /* 0x0000001200157310 */
/* 0x001e240000301000 */
/*0630*/ STG.E [R28.64], R21 ; /* 0x000000151c007986 */
/* 0x0011e2000c101904 */
/*0640*/ @P0 BRA 0x340 ; /* 0xfffffcf000000947 */
/* 0x000fea000383ffff */
/*0650*/ @!P1 BRA 0x8d0 ; /* 0x0000027000009947 */
/* 0x001fea0003800000 */
/*0660*/ IADD3 R18, R24, R27, RZ ; /* 0x0000001b18127210 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD.IADD R28, R8, 0x1, R27 ; /* 0x00000001081c7824 */
/* 0x000fe400078e021b */
/*0680*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE.U32 R28, R28, R23, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e0017 */
/*06a0*/ IMAD.WIDE.U32 R18, R18, R23, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fe200078e0017 */
/*06b0*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ee2000c1e1900 */
/*06d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*06e0*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x004ff00000201800 */
/*06f0*/ F2F.F64.F32 R16, R25 ; /* 0x0000001900107310 */
/* 0x008e240000201800 */
/*0700*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x003e140000000110 */
/*0710*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x001e240000301000 */
/*0720*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0011e2000c101904 */
/*0730*/ @!P0 BRA 0x8d0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R17, R27, 0x1, RZ ; /* 0x000000011b117810 */
/* 0x001fca0007ffe0ff */
/*0750*/ IMAD.IADD R28, R8, 0x1, R17.reuse ; /* 0x00000001081c7824 */
/* 0x100fe400078e0211 */
/*0760*/ IMAD.IADD R18, R24, 0x1, R17 ; /* 0x0000000118127824 */
/* 0x000fe400078e0211 */
/*0770*/ IMAD.WIDE.U32 R28, R28, R23, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e0017 */
/*0780*/ IMAD.WIDE.U32 R18, R18, R23, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fe400078e0017 */
/*0790*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000ee2000c1e1900 */
/*07b0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f05270 */
/*07c0*/ @P0 IADD3 R27, R27, 0x2, RZ ; /* 0x000000021b1b0810 */
/* 0x000fca0007ffe0ff */
/*07d0*/ @P0 IMAD.IADD R24, R24, 0x1, R27 ; /* 0x0000000118180824 */
/* 0x000fc800078e021b */
/*07e0*/ @P0 IMAD.WIDE.U32 R24, R24, R23, c[0x0][0x160] ; /* 0x0000580018180625 */
/* 0x000fe200078e0017 */
/*07f0*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x004ff00000201800 */
/*0800*/ F2F.F64.F32 R16, R26 ; /* 0x0000001a00107310 */
/* 0x008e240000201800 */
/*0810*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x0010440000000110 */
/*0820*/ @P0 IMAD.IADD R20, R8, 0x1, R27 ; /* 0x0000000108140824 */
/* 0x001fc800078e021b */
/*0830*/ @P0 IMAD.WIDE.U32 R20, R20, R23, c[0x0][0x160] ; /* 0x0000580014140625 */
/* 0x000fc800078e0017 */
/*0840*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x002e240000301000 */
/*0850*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0011e8000c101904 */
/*0860*/ @P0 LDG.E R20, [R20.64] ; /* 0x0000000414140981 */
/* 0x000ea8000c1e1900 */
/*0870*/ @P0 LDG.E R23, [R24.64] ; /* 0x0000000418170981 */
/* 0x000ee2000c1e1900 */
/*0880*/ @P0 F2F.F64.F32 R28, R20 ; /* 0x00000014001c0310 */
/* 0x004ff00000201800 */
/*0890*/ @P0 F2F.F64.F32 R26, R23 ; /* 0x00000017001a0310 */
/* 0x008e640000201800 */
/*08a0*/ @P0 DFMA R26, -R14, R28, R26 ; /* 0x0000001c0e1a022b */
/* 0x002e54000000011a */
/*08b0*/ @P0 F2F.F32.F64 R27, R26 ; /* 0x0000001a001b0310 */
/* 0x002e640000301000 */
/*08c0*/ @P0 STG.E [R24.64], R27 ; /* 0x0000001b18000986 */
/* 0x0021e4000c101904 */
/*08d0*/ IMAD.IADD R18, R7, 0x1, R6 ; /* 0x0000000107127824 */
/* 0x001fe200078e0206 */
/*08e0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0900*/ IMAD.WIDE.U32 R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fca00078e0013 */
/*0910*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f06070 */
/*0940*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x004ff00000201800 */
/*0950*/ F2F.F64.F32 R16, R23 ; /* 0x0000001700107310 */
/* 0x008e240000201800 */
/*0960*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x003e140000000110 */
/*0970*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x001e240000301000 */
/*0980*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0011e2000c101904 */
/*0990*/ @!P0 BRA 0x190 ; /* 0xfffff7f000008947 */
/* 0x000fea000383ffff */
/*09a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f06070 */
/*09b0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fd800078e0005 */
/*09c0*/ @!P0 BRA 0xd0 ; /* 0xfffff70000008947 */
/* 0x000fea000383ffff */
/*09d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09f0*/ SHF.R.U32.HI R14, RZ, 0x17, R16.reuse ; /* 0x00000017ff0e7819 */
/* 0x100fe20000011610 */
/*0a00*/ BSSY B1, 0x1050 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0a10*/ SHF.R.U32.HI R19, RZ, 0x17, R15 ; /* 0x00000017ff137819 */
/* 0x000fe2000001160f */
/*0a20*/ IMAD.MOV.U32 R26, RZ, RZ, R16 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0010 */
/*0a30*/ LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0e0e7812 */
/* 0x000fc400078ec0ff */
/*0a40*/ LOP3.LUT R19, R19, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff13137812 */
/* 0x000fe400078ec0ff */
/*0a50*/ IADD3 R23, R14, -0x1, RZ ; /* 0xffffffff0e177810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R21, R19, -0x1, RZ ; /* 0xffffffff13157810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ ISETP.GT.U32.AND P0, PT, R23, 0xfd, PT ; /* 0x000000fd1700780c */
/* 0x000fc80003f04070 */
/*0a80*/ ISETP.GT.U32.OR P0, PT, R21, 0xfd, P0 ; /* 0x000000fd1500780c */
/* 0x000fda0000704470 */
/*0a90*/ @!P0 IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff118224 */
/* 0x000fe200078e00ff */
/*0aa0*/ @!P0 BRA 0xc30 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ FSETP.GTU.FTZ.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fe20003f1c200 */
/*0ac0*/ IMAD.MOV.U32 R20, RZ, RZ, R15 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000f */
/*0ad0*/ FSETP.GTU.FTZ.AND P1, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fc80003f3c200 */
/*0ae0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0af0*/ @P0 BRA 0x1030 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT P0, RZ, R26, 0x7fffffff, R15, 0xc8, !PT ; /* 0x7fffffff1aff7812 */
/* 0x000fda000780c80f */
/*0b10*/ @!P0 BRA 0x1010 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ FSETP.NEU.FTZ.AND P2, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */
/* 0x000fe40003f5d200 */
/*0b30*/ FSETP.NEU.FTZ.AND P1, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f3d200 */
/*0b40*/ FSETP.NEU.FTZ.AND P0, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */
/* 0x000fd60003f1d200 */
/*0b50*/ @!P1 BRA !P2, 0x1010 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0b60*/ LOP3.LUT P2, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000784c0ff */
/*0b70*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b80*/ @P1 BRA 0xff0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT P1, RZ, R26, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1aff7812 */
/* 0x000fc8000782c0ff */
/*0ba0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0bb0*/ @P0 BRA 0xfc0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.GE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f06270 */
/*0bd0*/ ISETP.GE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fd60003f26270 */
/*0be0*/ @P0 MOV R17, RZ ; /* 0x000000ff00110202 */
/* 0x000fe20000000f00 */
/*0bf0*/ @!P0 IMAD.MOV.U32 R17, RZ, RZ, -0x40 ; /* 0xffffffc0ff118424 */
/* 0x000fe400078e00ff */
/*0c00*/ @!P0 FFMA R15, R20, 1.84467440737095516160e+19, RZ ; /* 0x5f800000140f8823 */
/* 0x000fe400000000ff */
/*0c10*/ @!P1 FFMA R26, R16, 1.84467440737095516160e+19, RZ ; /* 0x5f800000101a9823 */
/* 0x000fe200000000ff */
/*0c20*/ @!P1 IADD3 R17, R17, 0x40, RZ ; /* 0x0000004011119810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ LEA R21, R14, 0xc0800000, 0x17 ; /* 0xc08000000e157811 */
/* 0x000fe200078eb8ff */
/*0c40*/ BSSY B2, 0xfb0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0c50*/ IADD3 R16, R19, -0x7f, RZ ; /* 0xffffff8113107810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ IMAD.IADD R26, R26, 0x1, -R21 ; /* 0x000000011a1a7824 */
/* 0x000fe400078e0a15 */
/*0c70*/ IMAD R21, R16.reuse, -0x800000, R15 ; /* 0xff80000010157824 */
/* 0x040fe200078e020f */
/*0c80*/ IADD3 R16, R16, 0x7f, -R14 ; /* 0x0000007f10107810 */
/* 0x000fe20007ffe80e */
/*0c90*/ MUFU.RCP R20, R26 ; /* 0x0000001a00147308 */
/* 0x000e220000001000 */
/*0ca0*/ FADD.FTZ R23, -R26, -RZ ; /* 0x800000ff1a177221 */
/* 0x000fc60000010100 */
/*0cb0*/ IMAD.IADD R16, R16, 0x1, R17 ; /* 0x0000000110107824 */
/* 0x000fe400078e0211 */
/*0cc0*/ FFMA R19, R20, R23, 1 ; /* 0x3f80000014137423 */
/* 0x001fc80000000017 */
/*0cd0*/ FFMA R15, R20, R19, R20 ; /* 0x00000013140f7223 */
/* 0x000fc80000000014 */
/*0ce0*/ FFMA R20, R21, R15, RZ ; /* 0x0000000f15147223 */
/* 0x000fc800000000ff */
/*0cf0*/ FFMA R19, R23, R20, R21 ; /* 0x0000001417137223 */
/* 0x000fc80000000015 */
/*0d00*/ FFMA R20, R15, R19, R20 ; /* 0x000000130f147223 */
/* 0x000fc80000000014 */
/*0d10*/ FFMA R21, R23, R20, R21 ; /* 0x0000001417157223 */
/* 0x000fc80000000015 */
/*0d20*/ FFMA R19, R15, R21, R20 ; /* 0x000000150f137223 */
/* 0x000fca0000000014 */
/*0d30*/ SHF.R.U32.HI R14, RZ, 0x17, R19 ; /* 0x00000017ff0e7819 */
/* 0x000fc80000011613 */
/*0d40*/ LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0e0e7812 */
/* 0x000fca00078ec0ff */
/*0d50*/ IMAD.IADD R23, R14, 0x1, R16 ; /* 0x000000010e177824 */
/* 0x000fca00078e0210 */
/*0d60*/ IADD3 R14, R23, -0x1, RZ ; /* 0xffffffff170e7810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.GE.U32.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f06070 */
/*0d80*/ @!P0 BRA 0xf90 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d90*/ ISETP.GT.AND P0, PT, R23, 0xfe, PT ; /* 0x000000fe1700780c */
/* 0x000fda0003f04270 */
/*0da0*/ @P0 BRA 0xf60 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.GE.AND P0, PT, R23, 0x1, PT ; /* 0x000000011700780c */
/* 0x000fda0003f06270 */
/*0dc0*/ @P0 BRA 0xfa0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0dd0*/ ISETP.GE.AND P0, PT, R23, -0x18, PT ; /* 0xffffffe81700780c */
/* 0x000fe40003f06270 */
/*0de0*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fd600078ec0ff */
/*0df0*/ @!P0 BRA 0xfa0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e00*/ FFMA.RZ R14, R15, R21.reuse, R20.reuse ; /* 0x000000150f0e7223 */
/* 0x180fe2000000c014 */
/*0e10*/ IADD3 R17, R23.reuse, 0x20, RZ ; /* 0x0000002017117810 */
/* 0x040fe40007ffe0ff */
/*0e20*/ ISETP.NE.AND P2, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f45270 */
/*0e30*/ LOP3.LUT R16, R14, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0e107812 */
/* 0x000fe200078ec0ff */
/*0e40*/ FFMA.RP R14, R15, R21.reuse, R20.reuse ; /* 0x000000150f0e7223 */
/* 0x180fe20000008014 */
/*0e50*/ ISETP.NE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f25270 */
/*0e60*/ FFMA.RM R15, R15, R21, R20 ; /* 0x000000150f0f7223 */
/* 0x000fe20000004014 */
/*0e70*/ LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000010107812 */
/* 0x000fe200078efcff */
/*0e80*/ IMAD.MOV R20, RZ, RZ, -R23 ; /* 0x000000ffff147224 */
/* 0x000fc600078e0a17 */
/*0e90*/ SHF.L.U32 R17, R16, R17, RZ ; /* 0x0000001110117219 */
/* 0x000fe400000006ff */
/*0ea0*/ FSETP.NEU.FTZ.AND P0, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x000fe40003f1d000 */
/*0eb0*/ SEL R15, R20, RZ, P2 ; /* 0x000000ff140f7207 */
/* 0x000fe40001000000 */
/*0ec0*/ ISETP.NE.AND P1, PT, R17, RZ, P1 ; /* 0x000000ff1100720c */
/* 0x000fe40000f25270 */
/*0ed0*/ SHF.R.U32.HI R15, RZ, R15, R16 ; /* 0x0000000fff0f7219 */
/* 0x000fe40000011610 */
/*0ee0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0ef0*/ SHF.R.U32.HI R17, RZ, 0x1, R15 ; /* 0x00000001ff117819 */
/* 0x000fe4000001160f */
/*0f00*/ SEL R14, RZ, 0x1, !P0 ; /* 0x00000001ff0e7807 */
/* 0x000fc80004000000 */
/*0f10*/ LOP3.LUT R14, R14, 0x1, R17, 0xf8, !PT ; /* 0x000000010e0e7812 */
/* 0x000fc800078ef811 */
/*0f20*/ LOP3.LUT R14, R14, R15, RZ, 0xc0, !PT ; /* 0x0000000f0e0e7212 */
/* 0x000fca00078ec0ff */
/*0f30*/ IMAD.IADD R14, R17, 0x1, R14 ; /* 0x00000001110e7824 */
/* 0x000fca00078e020e */
/*0f40*/ LOP3.LUT R19, R14, R19, RZ, 0xfc, !PT ; /* 0x000000130e137212 */
/* 0x000fe200078efcff */
/*0f50*/ BRA 0xfa0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f60*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fc800078ec0ff */
/*0f70*/ LOP3.LUT R19, R19, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000013137812 */
/* 0x000fe200078efcff */
/*0f80*/ BRA 0xfa0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f90*/ IMAD R19, R16, 0x800000, R19 ; /* 0x0080000010137824 */
/* 0x000fe400078e0213 */
/*0fa0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0x1040 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0fc0*/ LOP3.LUT R15, R26, 0x80000000, R15, 0x48, !PT ; /* 0x800000001a0f7812 */
/* 0x000fc800078e480f */
/*0fd0*/ LOP3.LUT R19, R15, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000f137812 */
/* 0x000fe200078efcff */
/*0fe0*/ BRA 0x1040 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ff0*/ LOP3.LUT R19, R26, 0x80000000, R15, 0x48, !PT ; /* 0x800000001a137812 */
/* 0x000fe200078e480f */
/*1000*/ BRA 0x1040 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1010*/ MUFU.RSQ R19, -QNAN ; /* 0xffc0000000137908 */
/* 0x000e220000001400 */
/*1020*/ BRA 0x1040 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1030*/ FADD.FTZ R19, R20, R16 ; /* 0x0000001014137221 */
/* 0x000fe40000010000 */
/*1040*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1050*/ IMAD.MOV.U32 R17, RZ, RZ, R19 ; /* 0x000000ffff117224 */
/* 0x001fe400078e0013 */
/*1060*/ IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; /* 0x00000000ff137424 */
/* 0x000fc800078e00ff */
/*1070*/ RET.REL.NODEC R18 0x0 ; /* 0xffffef8012007950 */
/* 0x000fea0003c3ffff */
/*1080*/ BRA 0x1080; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_forwardElimination( float * fullMatrix, float * B, unsigned int nComp ) {
unsigned int t = threadIdx.x;
unsigned int baseIndex = t*nComp*nComp;
unsigned int i,j,k;
for ( i = 0; i < nComp - 1; i++ )
for ( j = i + 1; j < nComp; j++ ) {
double div = fullMatrix[baseIndex+ j*nComp+i ] / fullMatrix[baseIndex+ i*nComp+ i ];
for ( k = 0; k < nComp; k++ )
fullMatrix[ baseIndex+j*nComp+k ] -= div * fullMatrix[baseIndex+ i *nComp+ k ];
B[ baseIndex+j ] -= div * B[ baseIndex+i ];
}
__syncthreads();
} | .file "tmpxft_000da495_00000000-6_kernel_forwardElimination.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j
.type _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j, @function
_Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25kernel_forwardEliminationPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j, .-_Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j
.globl _Z25kernel_forwardEliminationPfS_j
.type _Z25kernel_forwardEliminationPfS_j, @function
_Z25kernel_forwardEliminationPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25kernel_forwardEliminationPfS_j, .-_Z25kernel_forwardEliminationPfS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25kernel_forwardEliminationPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25kernel_forwardEliminationPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_forwardElimination( float * fullMatrix, float * B, unsigned int nComp ) {
unsigned int t = threadIdx.x;
unsigned int baseIndex = t*nComp*nComp;
unsigned int i,j,k;
for ( i = 0; i < nComp - 1; i++ )
for ( j = i + 1; j < nComp; j++ ) {
double div = fullMatrix[baseIndex+ j*nComp+i ] / fullMatrix[baseIndex+ i*nComp+ i ];
for ( k = 0; k < nComp; k++ )
fullMatrix[ baseIndex+j*nComp+k ] -= div * fullMatrix[baseIndex+ i *nComp+ k ];
B[ baseIndex+j ] -= div * B[ baseIndex+i ];
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_forwardElimination( float * fullMatrix, float * B, unsigned int nComp ) {
unsigned int t = threadIdx.x;
unsigned int baseIndex = t*nComp*nComp;
unsigned int i,j,k;
for ( i = 0; i < nComp - 1; i++ )
for ( j = i + 1; j < nComp; j++ ) {
double div = fullMatrix[baseIndex+ j*nComp+i ] / fullMatrix[baseIndex+ i*nComp+ i ];
for ( k = 0; k < nComp; k++ )
fullMatrix[ baseIndex+j*nComp+k ] -= div * fullMatrix[baseIndex+ i *nComp+ k ];
B[ baseIndex+j ] -= div * B[ baseIndex+i ];
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_forwardElimination( float * fullMatrix, float * B, unsigned int nComp ) {
unsigned int t = threadIdx.x;
unsigned int baseIndex = t*nComp*nComp;
unsigned int i,j,k;
for ( i = 0; i < nComp - 1; i++ )
for ( j = i + 1; j < nComp; j++ ) {
double div = fullMatrix[baseIndex+ j*nComp+i ] / fullMatrix[baseIndex+ i*nComp+ i ];
for ( k = 0; k < nComp; k++ )
fullMatrix[ baseIndex+j*nComp+k ] -= div * fullMatrix[baseIndex+ i *nComp+ k ];
B[ baseIndex+j ] -= div * B[ baseIndex+i ];
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25kernel_forwardEliminationPfS_j
.globl _Z25kernel_forwardEliminationPfS_j
.p2align 8
.type _Z25kernel_forwardEliminationPfS_j,@function
_Z25kernel_forwardEliminationPfS_j:
s_load_b32 s5, s[0:1], 0x10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB0_8
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v8, v0, s5
s_mul_i32 s4, s5, s5
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v10, v0, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v8, s5
v_add_nc_u32_e32 v11, s5, v9
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v11, s5, v11
v_add_nc_u32_e32 v10, s5, v10
s_cmp_eq_u32 s7, s6
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_mov_b32 s4, s7
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s7, s5
s_cbranch_scc1 .LBB0_2
v_add_nc_u32_e32 v0, s4, v8
v_mov_b32_e32 v12, v11
s_mov_b32 s8, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, s[4:5]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo
.LBB0_5:
v_add_nc_u32_e32 v0, s8, v8
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v0, s5, s[4:5]
v_mov_b32_e32 v7, v1
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v7, null, v6, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v13, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v7, v13, 1.0
v_fmac_f32_e32 v13, v14, v13
v_div_scale_f32 v14, vcc_lo, v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v14, v13
v_fma_f32 v16, -v7, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v16, v13
v_fma_f32 v7, -v7, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v7, v13, v15
v_div_fixup_f32 v0, v7, v6, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[6:7], v0
.p2align 6
.LBB0_6:
v_dual_mov_b32 v14, 0 :: v_dual_add_nc_u32 v13, s9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[15:16], 2, v[13:14]
v_add_nc_u32_e32 v13, s9, v12
s_add_i32 s9, s9, 1
s_cmp_lg_u32 s5, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_u32 v15, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_clause 0x1
global_load_b32 v0, v[15:16], off
global_load_b32 v17, v[13:14], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[15:16], v0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[17:18], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[6:7], v[15:16], v[17:18]
v_cvt_f32_f64_e32 v0, v[15:16]
global_store_b32 v[13:14], v0, off
s_cbranch_scc1 .LBB0_6
v_add_nc_u32_e32 v0, s8, v9
v_add_nc_u32_e32 v12, s5, v12
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_ge_u32 s8, s5
v_lshlrev_b64 v[13:14], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v17, v[13:14], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[15:16], v0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[17:18], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[15:16], v[17:18]
v_cvt_f32_f64_e32 v0, v[6:7]
global_store_b32 v[13:14], v0, off
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_8:
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_forwardEliminationPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25kernel_forwardEliminationPfS_j, .Lfunc_end0-_Z25kernel_forwardEliminationPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_forwardEliminationPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z25kernel_forwardEliminationPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_forwardElimination( float * fullMatrix, float * B, unsigned int nComp ) {
unsigned int t = threadIdx.x;
unsigned int baseIndex = t*nComp*nComp;
unsigned int i,j,k;
for ( i = 0; i < nComp - 1; i++ )
for ( j = i + 1; j < nComp; j++ ) {
double div = fullMatrix[baseIndex+ j*nComp+i ] / fullMatrix[baseIndex+ i*nComp+ i ];
for ( k = 0; k < nComp; k++ )
fullMatrix[ baseIndex+j*nComp+k ] -= div * fullMatrix[baseIndex+ i *nComp+ k ];
B[ baseIndex+j ] -= div * B[ baseIndex+i ];
}
__syncthreads();
} | .text
.file "kernel_forwardElimination.hip"
.globl _Z40__device_stub__kernel_forwardEliminationPfS_j # -- Begin function _Z40__device_stub__kernel_forwardEliminationPfS_j
.p2align 4, 0x90
.type _Z40__device_stub__kernel_forwardEliminationPfS_j,@function
_Z40__device_stub__kernel_forwardEliminationPfS_j: # @_Z40__device_stub__kernel_forwardEliminationPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25kernel_forwardEliminationPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z40__device_stub__kernel_forwardEliminationPfS_j, .Lfunc_end0-_Z40__device_stub__kernel_forwardEliminationPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25kernel_forwardEliminationPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25kernel_forwardEliminationPfS_j,@object # @_Z25kernel_forwardEliminationPfS_j
.section .rodata,"a",@progbits
.globl _Z25kernel_forwardEliminationPfS_j
.p2align 3, 0x0
_Z25kernel_forwardEliminationPfS_j:
.quad _Z40__device_stub__kernel_forwardEliminationPfS_j
.size _Z25kernel_forwardEliminationPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25kernel_forwardEliminationPfS_j"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__kernel_forwardEliminationPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25kernel_forwardEliminationPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25kernel_forwardEliminationPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc80003f05270 */
/*0030*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fc80007ffe0ff */
/*0040*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fda0004702670 */
/*0050*/ @P0 BRA 0x9d0 ; /* 0x0000097000000947 */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0070*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe200078ec0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IADD3 R4, R2, -c[0x0][0x170], RZ ; /* 0x80005c0002047a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD R6, R3, c[0x0][0x170], RZ ; /* 0x00005c0003067a24 */
/* 0x001fe400078e02ff */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a24 */
/* 0x000fc600078e02ff */
/*00d0*/ IADD3 R5, R3, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f06070 */
/*00f0*/ @P0 BRA 0x9a0 ; /* 0x000008a000000947 */
/* 0x001fea0003800000 */
/*0100*/ IMAD R8, R3.reuse, c[0x0][0x170], R6.reuse ; /* 0x00005c0003087a24 */
/* 0x140fe400078e0206 */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.IADD R10, R3, 0x1, R6 ; /* 0x00000001030a7824 */
/* 0x000fe200078e0206 */
/*0130*/ IADD3 R9, R8.reuse, 0x3, RZ ; /* 0x0000000308097810 */
/* 0x040fe20007ffe0ff */
/*0140*/ IMAD.IADD R12, R8.reuse, 0x1, R3 ; /* 0x00000001080c7824 */
/* 0x040fe200078e0203 */
/*0150*/ IADD3 R22, R8, 0x1, RZ ; /* 0x0000000108167810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e000d */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0005 */
/*0180*/ IMAD.WIDE.U32 R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e000d */
/*0190*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD R24, R7, c[0x0][0x170], R6 ; /* 0x00005c0007187a24 */
/* 0x000fe400078e0206 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.IADD R14, R24, 0x1, R3 ; /* 0x00000001180e7824 */
/* 0x000fc800078e0203 */
/*01d0*/ IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e000f */
/*01e0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ BSSY B0, 0x2b0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0200*/ MUFU.RCP R17, R16 ; /* 0x0000001000117308 */
/* 0x005e300000001000 */
/*0210*/ FCHK P0, R15, R16 ; /* 0x000000100f007302 */
/* 0x008e620000000000 */
/*0220*/ FFMA R18, -R16, R17, 1 ; /* 0x3f80000010127423 */
/* 0x001fc80000000111 */
/*0230*/ FFMA R18, R17, R18, R17 ; /* 0x0000001211127223 */
/* 0x000fc80000000011 */
/*0240*/ FFMA R17, R15, R18, RZ ; /* 0x000000120f117223 */
/* 0x000fc800000000ff */
/*0250*/ FFMA R19, -R16, R17, R15 ; /* 0x0000001110137223 */
/* 0x000fc8000000010f */
/*0260*/ FFMA R17, R18, R19, R17 ; /* 0x0000001312117223 */
/* 0x000fe20000000011 */
/*0270*/ @!P0 BRA 0x2a0 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0280*/ MOV R18, 0x2a0 ; /* 0x000002a000127802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x9f0 ; /* 0x0000075000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*02c0*/ F2F.F64.F32 R14, R17 ; /* 0x00000011000e7310 */
/* 0x0000620000201800 */
/*02d0*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f25270 */
/*02e0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fd400078e00ff */
/*02f0*/ @!P0 BRA 0x650 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*0300*/ IADD3 R25, R24.reuse, 0x3, RZ ; /* 0x0000000318197810 */
/* 0x041fe20007ffe0ff */
/*0310*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R26, R24, 0x1, RZ ; /* 0x00000001181a7810 */
/* 0x000fe20007ffe0ff */
/*0330*/ IMAD.MOV.U32 R23, RZ, RZ, R9 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0009 */
/*0340*/ IMAD.IADD R17, R8, 0x1, R27.reuse ; /* 0x0000000108117824 */
/* 0x100fe400078e021b */
/*0350*/ IMAD.MOV.U32 R28, RZ, RZ, 0x4 ; /* 0x00000004ff1c7424 */
/* 0x001fe400078e00ff */
/*0360*/ IMAD.IADD R21, R24, 0x1, R27 ; /* 0x0000000118157824 */
/* 0x000fe400078e021b */
/*0370*/ IMAD.WIDE.U32 R16, R17, R28, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e001c */
/*0380*/ IMAD.WIDE.U32 R20, R21, R28, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe200078e001c */
/*0390*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x0000a8000c1e1900 */
/*03a0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x001ee2000c1e1900 */
/*03b0*/ F2F.F64.F32 R18, R29 ; /* 0x0000001d00127310 */
/* 0x004ff00000201800 */
/*03c0*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x008e240000201800 */
/*03d0*/ DFMA R18, -R14, R18, R16 ; /* 0x000000120e12722b */
/* 0x0030440000000110 */
/*03e0*/ IMAD.IADD R17, R22, 0x1, R27 ; /* 0x0000000116117824 */
/* 0x001fc800078e021b */
/*03f0*/ F2F.F32.F64 R29, R18 ; /* 0x00000012001d7310 */
/* 0x0020620000301000 */
/*0400*/ IMAD.WIDE.U32 R16, R17, R28, c[0x0][0x160] ; /* 0x0000580011107625 */
/* 0x000fc800078e001c */
/*0410*/ IMAD.IADD R19, R26, 0x1, R27 ; /* 0x000000011a137824 */
/* 0x001fc800078e021b */
/*0420*/ IMAD.WIDE.U32 R18, R19, R28, c[0x0][0x160] ; /* 0x0000580013127625 */
/* 0x000fe200078e001c */
/*0430*/ STG.E [R20.64], R29 ; /* 0x0000001d14007986 */
/* 0x0021e8000c101904 */
/*0440*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x0010a8000c1e1900 */
/*0450*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x001ee2000c1e1900 */
/*0460*/ F2F.F64.F32 R20, R29 ; /* 0x0000001d00147310 */
/* 0x004ff00000201800 */
/*0470*/ F2F.F64.F32 R16, R17 ; /* 0x0000001100107310 */
/* 0x008e240000201800 */
/*0480*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x0010440000000110 */
/*0490*/ IADD3 R21, R23, -0x1, RZ ; /* 0xffffffff17157810 */
/* 0x001fc80007ffe0ff */
/*04a0*/ F2F.F32.F64 R29, R16 ; /* 0x00000010001d7310 */
/* 0x0020620000301000 */
/*04b0*/ IMAD.WIDE.U32 R20, R21, R28, c[0x0][0x160] ; /* 0x0000580015147625 */
/* 0x000fe200078e001c */
/*04c0*/ IADD3 R16, R25, -0x1, RZ ; /* 0xffffffff19107810 */
/* 0x001fca0007ffe0ff */
/*04d0*/ IMAD.WIDE.U32 R16, R16, R28, c[0x0][0x160] ; /* 0x0000580010107625 */
/* 0x000fe200078e001c */
/*04e0*/ STG.E [R18.64], R29 ; /* 0x0000001d12007986 */
/* 0x0021e8000c101904 */
/*04f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000228000c1e1900 */
/*0500*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002ea2000c1e1900 */
/*0510*/ F2F.F64.F32 R18, R20 ; /* 0x0000001400127310 */
/* 0x001ff00000201800 */
/*0520*/ F2F.F64.F32 R20, R21 ; /* 0x0000001500147310 */
/* 0x004e240000201800 */
/*0530*/ DFMA R20, -R14, R18, R20 ; /* 0x000000120e14722b */
/* 0x0010440000000114 */
/*0540*/ IMAD.WIDE.U32 R18, R23, R28, c[0x0][0x160] ; /* 0x0000580017127625 */
/* 0x001fc800078e001c */
/*0550*/ F2F.F32.F64 R29, R20 ; /* 0x00000014001d7310 */
/* 0x002e240000301000 */
/*0560*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x0011e8000c101904 */
/*0570*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE.U32 R28, R25, R28, c[0x0][0x160] ; /* 0x00005800191c7625 */
/* 0x001fca00078e001c */
/*0590*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x002ee2000c1e1900 */
/*05a0*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fca0007ffe0ff */
/*05b0*/ IMAD.IADD R16, R4, 0x1, R27 ; /* 0x0000000104107824 */
/* 0x000fca00078e021b */
/*05c0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*05d0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3 R25, R25, 0x4, RZ ; /* 0x0000000419197810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ F2F.F64.F32 R20, R18 ; /* 0x0000001200147310 */
/* 0x004ff00000201800 */
/*0600*/ F2F.F64.F32 R18, R19 ; /* 0x0000001300127310 */
/* 0x008e240000201800 */
/*0610*/ DFMA R18, -R14, R20, R18 ; /* 0x000000140e12722b */
/* 0x001e0c0000000112 */
/*0620*/ F2F.F32.F64 R21, R18 ; /* 0x0000001200157310 */
/* 0x001e240000301000 */
/*0630*/ STG.E [R28.64], R21 ; /* 0x000000151c007986 */
/* 0x0011e2000c101904 */
/*0640*/ @P0 BRA 0x340 ; /* 0xfffffcf000000947 */
/* 0x000fea000383ffff */
/*0650*/ @!P1 BRA 0x8d0 ; /* 0x0000027000009947 */
/* 0x001fea0003800000 */
/*0660*/ IADD3 R18, R24, R27, RZ ; /* 0x0000001b18127210 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD.IADD R28, R8, 0x1, R27 ; /* 0x00000001081c7824 */
/* 0x000fe400078e021b */
/*0680*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE.U32 R28, R28, R23, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e0017 */
/*06a0*/ IMAD.WIDE.U32 R18, R18, R23, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fe200078e0017 */
/*06b0*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ee2000c1e1900 */
/*06d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*06e0*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x004ff00000201800 */
/*06f0*/ F2F.F64.F32 R16, R25 ; /* 0x0000001900107310 */
/* 0x008e240000201800 */
/*0700*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x003e140000000110 */
/*0710*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x001e240000301000 */
/*0720*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0011e2000c101904 */
/*0730*/ @!P0 BRA 0x8d0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R17, R27, 0x1, RZ ; /* 0x000000011b117810 */
/* 0x001fca0007ffe0ff */
/*0750*/ IMAD.IADD R28, R8, 0x1, R17.reuse ; /* 0x00000001081c7824 */
/* 0x100fe400078e0211 */
/*0760*/ IMAD.IADD R18, R24, 0x1, R17 ; /* 0x0000000118127824 */
/* 0x000fe400078e0211 */
/*0770*/ IMAD.WIDE.U32 R28, R28, R23, c[0x0][0x160] ; /* 0x000058001c1c7625 */
/* 0x000fc800078e0017 */
/*0780*/ IMAD.WIDE.U32 R18, R18, R23, c[0x0][0x160] ; /* 0x0000580012127625 */
/* 0x000fe400078e0017 */
/*0790*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea8000c1e1900 */
/*07a0*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000ee2000c1e1900 */
/*07b0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f05270 */
/*07c0*/ @P0 IADD3 R27, R27, 0x2, RZ ; /* 0x000000021b1b0810 */
/* 0x000fca0007ffe0ff */
/*07d0*/ @P0 IMAD.IADD R24, R24, 0x1, R27 ; /* 0x0000000118180824 */
/* 0x000fc800078e021b */
/*07e0*/ @P0 IMAD.WIDE.U32 R24, R24, R23, c[0x0][0x160] ; /* 0x0000580018180625 */
/* 0x000fe200078e0017 */
/*07f0*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x004ff00000201800 */
/*0800*/ F2F.F64.F32 R16, R26 ; /* 0x0000001a00107310 */
/* 0x008e240000201800 */
/*0810*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x0010440000000110 */
/*0820*/ @P0 IMAD.IADD R20, R8, 0x1, R27 ; /* 0x0000000108140824 */
/* 0x001fc800078e021b */
/*0830*/ @P0 IMAD.WIDE.U32 R20, R20, R23, c[0x0][0x160] ; /* 0x0000580014140625 */
/* 0x000fc800078e0017 */
/*0840*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x002e240000301000 */
/*0850*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0011e8000c101904 */
/*0860*/ @P0 LDG.E R20, [R20.64] ; /* 0x0000000414140981 */
/* 0x000ea8000c1e1900 */
/*0870*/ @P0 LDG.E R23, [R24.64] ; /* 0x0000000418170981 */
/* 0x000ee2000c1e1900 */
/*0880*/ @P0 F2F.F64.F32 R28, R20 ; /* 0x00000014001c0310 */
/* 0x004ff00000201800 */
/*0890*/ @P0 F2F.F64.F32 R26, R23 ; /* 0x00000017001a0310 */
/* 0x008e640000201800 */
/*08a0*/ @P0 DFMA R26, -R14, R28, R26 ; /* 0x0000001c0e1a022b */
/* 0x002e54000000011a */
/*08b0*/ @P0 F2F.F32.F64 R27, R26 ; /* 0x0000001a001b0310 */
/* 0x002e640000301000 */
/*08c0*/ @P0 STG.E [R24.64], R27 ; /* 0x0000001b18000986 */
/* 0x0021e4000c101904 */
/*08d0*/ IMAD.IADD R18, R7, 0x1, R6 ; /* 0x0000000107127824 */
/* 0x001fe200078e0206 */
/*08e0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x000fc800078e00ff */
/*0900*/ IMAD.WIDE.U32 R18, R18, R19, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fca00078e0013 */
/*0910*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0930*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f06070 */
/*0940*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x004ff00000201800 */
/*0950*/ F2F.F64.F32 R16, R23 ; /* 0x0000001700107310 */
/* 0x008e240000201800 */
/*0960*/ DFMA R16, -R14, R20, R16 ; /* 0x000000140e10722b */
/* 0x003e140000000110 */
/*0970*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x001e240000301000 */
/*0980*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0011e2000c101904 */
/*0990*/ @!P0 BRA 0x190 ; /* 0xfffff7f000008947 */
/* 0x000fea000383ffff */
/*09a0*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe20003f06070 */
/*09b0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fd800078e0005 */
/*09c0*/ @!P0 BRA 0xd0 ; /* 0xfffff70000008947 */
/* 0x000fea000383ffff */
/*09d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09f0*/ SHF.R.U32.HI R14, RZ, 0x17, R16.reuse ; /* 0x00000017ff0e7819 */
/* 0x100fe20000011610 */
/*0a00*/ BSSY B1, 0x1050 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0a10*/ SHF.R.U32.HI R19, RZ, 0x17, R15 ; /* 0x00000017ff137819 */
/* 0x000fe2000001160f */
/*0a20*/ IMAD.MOV.U32 R26, RZ, RZ, R16 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0010 */
/*0a30*/ LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0e0e7812 */
/* 0x000fc400078ec0ff */
/*0a40*/ LOP3.LUT R19, R19, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff13137812 */
/* 0x000fe400078ec0ff */
/*0a50*/ IADD3 R23, R14, -0x1, RZ ; /* 0xffffffff0e177810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R21, R19, -0x1, RZ ; /* 0xffffffff13157810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ ISETP.GT.U32.AND P0, PT, R23, 0xfd, PT ; /* 0x000000fd1700780c */
/* 0x000fc80003f04070 */
/*0a80*/ ISETP.GT.U32.OR P0, PT, R21, 0xfd, P0 ; /* 0x000000fd1500780c */
/* 0x000fda0000704470 */
/*0a90*/ @!P0 IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff118224 */
/* 0x000fe200078e00ff */
/*0aa0*/ @!P0 BRA 0xc30 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ FSETP.GTU.FTZ.AND P0, PT, |R15|, +INF , PT ; /* 0x7f8000000f00780b */
/* 0x000fe20003f1c200 */
/*0ac0*/ IMAD.MOV.U32 R20, RZ, RZ, R15 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000f */
/*0ad0*/ FSETP.GTU.FTZ.AND P1, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fc80003f3c200 */
/*0ae0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0af0*/ @P0 BRA 0x1030 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0b00*/ LOP3.LUT P0, RZ, R26, 0x7fffffff, R15, 0xc8, !PT ; /* 0x7fffffff1aff7812 */
/* 0x000fda000780c80f */
/*0b10*/ @!P0 BRA 0x1010 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0b20*/ FSETP.NEU.FTZ.AND P2, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */
/* 0x000fe40003f5d200 */
/*0b30*/ FSETP.NEU.FTZ.AND P1, PT, |R16|, +INF , PT ; /* 0x7f8000001000780b */
/* 0x000fe40003f3d200 */
/*0b40*/ FSETP.NEU.FTZ.AND P0, PT, |R20|, +INF , PT ; /* 0x7f8000001400780b */
/* 0x000fd60003f1d200 */
/*0b50*/ @!P1 BRA !P2, 0x1010 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0b60*/ LOP3.LUT P2, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000784c0ff */
/*0b70*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b80*/ @P1 BRA 0xff0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b90*/ LOP3.LUT P1, RZ, R26, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1aff7812 */
/* 0x000fc8000782c0ff */
/*0ba0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0bb0*/ @P0 BRA 0xfc0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.GE.AND P0, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f06270 */
/*0bd0*/ ISETP.GE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fd60003f26270 */
/*0be0*/ @P0 MOV R17, RZ ; /* 0x000000ff00110202 */
/* 0x000fe20000000f00 */
/*0bf0*/ @!P0 IMAD.MOV.U32 R17, RZ, RZ, -0x40 ; /* 0xffffffc0ff118424 */
/* 0x000fe400078e00ff */
/*0c00*/ @!P0 FFMA R15, R20, 1.84467440737095516160e+19, RZ ; /* 0x5f800000140f8823 */
/* 0x000fe400000000ff */
/*0c10*/ @!P1 FFMA R26, R16, 1.84467440737095516160e+19, RZ ; /* 0x5f800000101a9823 */
/* 0x000fe200000000ff */
/*0c20*/ @!P1 IADD3 R17, R17, 0x40, RZ ; /* 0x0000004011119810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ LEA R21, R14, 0xc0800000, 0x17 ; /* 0xc08000000e157811 */
/* 0x000fe200078eb8ff */
/*0c40*/ BSSY B2, 0xfb0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0c50*/ IADD3 R16, R19, -0x7f, RZ ; /* 0xffffff8113107810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ IMAD.IADD R26, R26, 0x1, -R21 ; /* 0x000000011a1a7824 */
/* 0x000fe400078e0a15 */
/*0c70*/ IMAD R21, R16.reuse, -0x800000, R15 ; /* 0xff80000010157824 */
/* 0x040fe200078e020f */
/*0c80*/ IADD3 R16, R16, 0x7f, -R14 ; /* 0x0000007f10107810 */
/* 0x000fe20007ffe80e */
/*0c90*/ MUFU.RCP R20, R26 ; /* 0x0000001a00147308 */
/* 0x000e220000001000 */
/*0ca0*/ FADD.FTZ R23, -R26, -RZ ; /* 0x800000ff1a177221 */
/* 0x000fc60000010100 */
/*0cb0*/ IMAD.IADD R16, R16, 0x1, R17 ; /* 0x0000000110107824 */
/* 0x000fe400078e0211 */
/*0cc0*/ FFMA R19, R20, R23, 1 ; /* 0x3f80000014137423 */
/* 0x001fc80000000017 */
/*0cd0*/ FFMA R15, R20, R19, R20 ; /* 0x00000013140f7223 */
/* 0x000fc80000000014 */
/*0ce0*/ FFMA R20, R21, R15, RZ ; /* 0x0000000f15147223 */
/* 0x000fc800000000ff */
/*0cf0*/ FFMA R19, R23, R20, R21 ; /* 0x0000001417137223 */
/* 0x000fc80000000015 */
/*0d00*/ FFMA R20, R15, R19, R20 ; /* 0x000000130f147223 */
/* 0x000fc80000000014 */
/*0d10*/ FFMA R21, R23, R20, R21 ; /* 0x0000001417157223 */
/* 0x000fc80000000015 */
/*0d20*/ FFMA R19, R15, R21, R20 ; /* 0x000000150f137223 */
/* 0x000fca0000000014 */
/*0d30*/ SHF.R.U32.HI R14, RZ, 0x17, R19 ; /* 0x00000017ff0e7819 */
/* 0x000fc80000011613 */
/*0d40*/ LOP3.LUT R14, R14, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0e0e7812 */
/* 0x000fca00078ec0ff */
/*0d50*/ IMAD.IADD R23, R14, 0x1, R16 ; /* 0x000000010e177824 */
/* 0x000fca00078e0210 */
/*0d60*/ IADD3 R14, R23, -0x1, RZ ; /* 0xffffffff170e7810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.GE.U32.AND P0, PT, R14, 0xfe, PT ; /* 0x000000fe0e00780c */
/* 0x000fda0003f06070 */
/*0d80*/ @!P0 BRA 0xf90 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d90*/ ISETP.GT.AND P0, PT, R23, 0xfe, PT ; /* 0x000000fe1700780c */
/* 0x000fda0003f04270 */
/*0da0*/ @P0 BRA 0xf60 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0db0*/ ISETP.GE.AND P0, PT, R23, 0x1, PT ; /* 0x000000011700780c */
/* 0x000fda0003f06270 */
/*0dc0*/ @P0 BRA 0xfa0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0dd0*/ ISETP.GE.AND P0, PT, R23, -0x18, PT ; /* 0xffffffe81700780c */
/* 0x000fe40003f06270 */
/*0de0*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fd600078ec0ff */
/*0df0*/ @!P0 BRA 0xfa0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0e00*/ FFMA.RZ R14, R15, R21.reuse, R20.reuse ; /* 0x000000150f0e7223 */
/* 0x180fe2000000c014 */
/*0e10*/ IADD3 R17, R23.reuse, 0x20, RZ ; /* 0x0000002017117810 */
/* 0x040fe40007ffe0ff */
/*0e20*/ ISETP.NE.AND P2, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f45270 */
/*0e30*/ LOP3.LUT R16, R14, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0e107812 */
/* 0x000fe200078ec0ff */
/*0e40*/ FFMA.RP R14, R15, R21.reuse, R20.reuse ; /* 0x000000150f0e7223 */
/* 0x180fe20000008014 */
/*0e50*/ ISETP.NE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f25270 */
/*0e60*/ FFMA.RM R15, R15, R21, R20 ; /* 0x000000150f0f7223 */
/* 0x000fe20000004014 */
/*0e70*/ LOP3.LUT R16, R16, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000010107812 */
/* 0x000fe200078efcff */
/*0e80*/ IMAD.MOV R20, RZ, RZ, -R23 ; /* 0x000000ffff147224 */
/* 0x000fc600078e0a17 */
/*0e90*/ SHF.L.U32 R17, R16, R17, RZ ; /* 0x0000001110117219 */
/* 0x000fe400000006ff */
/*0ea0*/ FSETP.NEU.FTZ.AND P0, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x000fe40003f1d000 */
/*0eb0*/ SEL R15, R20, RZ, P2 ; /* 0x000000ff140f7207 */
/* 0x000fe40001000000 */
/*0ec0*/ ISETP.NE.AND P1, PT, R17, RZ, P1 ; /* 0x000000ff1100720c */
/* 0x000fe40000f25270 */
/*0ed0*/ SHF.R.U32.HI R15, RZ, R15, R16 ; /* 0x0000000fff0f7219 */
/* 0x000fe40000011610 */
/*0ee0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0ef0*/ SHF.R.U32.HI R17, RZ, 0x1, R15 ; /* 0x00000001ff117819 */
/* 0x000fe4000001160f */
/*0f00*/ SEL R14, RZ, 0x1, !P0 ; /* 0x00000001ff0e7807 */
/* 0x000fc80004000000 */
/*0f10*/ LOP3.LUT R14, R14, 0x1, R17, 0xf8, !PT ; /* 0x000000010e0e7812 */
/* 0x000fc800078ef811 */
/*0f20*/ LOP3.LUT R14, R14, R15, RZ, 0xc0, !PT ; /* 0x0000000f0e0e7212 */
/* 0x000fca00078ec0ff */
/*0f30*/ IMAD.IADD R14, R17, 0x1, R14 ; /* 0x00000001110e7824 */
/* 0x000fca00078e020e */
/*0f40*/ LOP3.LUT R19, R14, R19, RZ, 0xfc, !PT ; /* 0x000000130e137212 */
/* 0x000fe200078efcff */
/*0f50*/ BRA 0xfa0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0f60*/ LOP3.LUT R19, R19, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000013137812 */
/* 0x000fc800078ec0ff */
/*0f70*/ LOP3.LUT R19, R19, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000013137812 */
/* 0x000fe200078efcff */
/*0f80*/ BRA 0xfa0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f90*/ IMAD R19, R16, 0x800000, R19 ; /* 0x0080000010137824 */
/* 0x000fe400078e0213 */
/*0fa0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0x1040 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0fc0*/ LOP3.LUT R15, R26, 0x80000000, R15, 0x48, !PT ; /* 0x800000001a0f7812 */
/* 0x000fc800078e480f */
/*0fd0*/ LOP3.LUT R19, R15, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000f137812 */
/* 0x000fe200078efcff */
/*0fe0*/ BRA 0x1040 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ff0*/ LOP3.LUT R19, R26, 0x80000000, R15, 0x48, !PT ; /* 0x800000001a137812 */
/* 0x000fe200078e480f */
/*1000*/ BRA 0x1040 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1010*/ MUFU.RSQ R19, -QNAN ; /* 0xffc0000000137908 */
/* 0x000e220000001400 */
/*1020*/ BRA 0x1040 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1030*/ FADD.FTZ R19, R20, R16 ; /* 0x0000001014137221 */
/* 0x000fe40000010000 */
/*1040*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1050*/ IMAD.MOV.U32 R17, RZ, RZ, R19 ; /* 0x000000ffff117224 */
/* 0x001fe400078e0013 */
/*1060*/ IMAD.MOV.U32 R19, RZ, RZ, 0x0 ; /* 0x00000000ff137424 */
/* 0x000fc800078e00ff */
/*1070*/ RET.REL.NODEC R18 0x0 ; /* 0xffffef8012007950 */
/* 0x000fea0003c3ffff */
/*1080*/ BRA 0x1080; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25kernel_forwardEliminationPfS_j
.globl _Z25kernel_forwardEliminationPfS_j
.p2align 8
.type _Z25kernel_forwardEliminationPfS_j,@function
_Z25kernel_forwardEliminationPfS_j:
s_load_b32 s5, s[0:1], 0x10
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB0_8
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v8, v0, s5
s_mul_i32 s4, s5, s5
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v10, v0, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v8, s5
v_add_nc_u32_e32 v11, s5, v9
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v11, s5, v11
v_add_nc_u32_e32 v10, s5, v10
s_cmp_eq_u32 s7, s6
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_mov_b32 s4, s7
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s7, s5
s_cbranch_scc1 .LBB0_2
v_add_nc_u32_e32 v0, s4, v8
v_mov_b32_e32 v12, v11
s_mov_b32 s8, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s5, s[4:5]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo
.LBB0_5:
v_add_nc_u32_e32 v0, s8, v8
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v0, s5, s[4:5]
v_mov_b32_e32 v7, v1
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v7, null, v6, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v13, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v7, v13, 1.0
v_fmac_f32_e32 v13, v14, v13
v_div_scale_f32 v14, vcc_lo, v0, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v14, v13
v_fma_f32 v16, -v7, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v16, v13
v_fma_f32 v7, -v7, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v7, v13, v15
v_div_fixup_f32 v0, v7, v6, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f64_f32_e32 v[6:7], v0
.p2align 6
.LBB0_6:
v_dual_mov_b32 v14, 0 :: v_dual_add_nc_u32 v13, s9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[15:16], 2, v[13:14]
v_add_nc_u32_e32 v13, s9, v12
s_add_i32 s9, s9, 1
s_cmp_lg_u32 s5, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_u32 v15, vcc_lo, s0, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s0, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
s_clause 0x1
global_load_b32 v0, v[15:16], off
global_load_b32 v17, v[13:14], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[15:16], v0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[17:18], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[6:7], v[15:16], v[17:18]
v_cvt_f32_f64_e32 v0, v[15:16]
global_store_b32 v[13:14], v0, off
s_cbranch_scc1 .LBB0_6
v_add_nc_u32_e32 v0, s8, v9
v_add_nc_u32_e32 v12, s5, v12
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_ge_u32 s8, s5
v_lshlrev_b64 v[13:14], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v17, v[13:14], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[15:16], v0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[17:18], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[15:16], v[17:18]
v_cvt_f32_f64_e32 v0, v[6:7]
global_store_b32 v[13:14], v0, off
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_8:
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25kernel_forwardEliminationPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25kernel_forwardEliminationPfS_j, .Lfunc_end0-_Z25kernel_forwardEliminationPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25kernel_forwardEliminationPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z25kernel_forwardEliminationPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000da495_00000000-6_kernel_forwardElimination.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j
.type _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j, @function
_Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25kernel_forwardEliminationPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j, .-_Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j
.globl _Z25kernel_forwardEliminationPfS_j
.type _Z25kernel_forwardEliminationPfS_j, @function
_Z25kernel_forwardEliminationPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25kernel_forwardEliminationPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25kernel_forwardEliminationPfS_j, .-_Z25kernel_forwardEliminationPfS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25kernel_forwardEliminationPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25kernel_forwardEliminationPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_forwardElimination.hip"
.globl _Z40__device_stub__kernel_forwardEliminationPfS_j # -- Begin function _Z40__device_stub__kernel_forwardEliminationPfS_j
.p2align 4, 0x90
.type _Z40__device_stub__kernel_forwardEliminationPfS_j,@function
_Z40__device_stub__kernel_forwardEliminationPfS_j: # @_Z40__device_stub__kernel_forwardEliminationPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25kernel_forwardEliminationPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z40__device_stub__kernel_forwardEliminationPfS_j, .Lfunc_end0-_Z40__device_stub__kernel_forwardEliminationPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25kernel_forwardEliminationPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25kernel_forwardEliminationPfS_j,@object # @_Z25kernel_forwardEliminationPfS_j
.section .rodata,"a",@progbits
.globl _Z25kernel_forwardEliminationPfS_j
.p2align 3, 0x0
_Z25kernel_forwardEliminationPfS_j:
.quad _Z40__device_stub__kernel_forwardEliminationPfS_j
.size _Z25kernel_forwardEliminationPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25kernel_forwardEliminationPfS_j"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__kernel_forwardEliminationPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25kernel_forwardEliminationPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define THREADS_PER_BLOCK 256
#define MULTIPLICATIONS 4096
/**
* Multiply square matrix (n x n) by the vector of size n.
*
*
* @param mat Input matrix.
* @param vec Input vector.
* @param out Output vector.
* @param n Dimension.
*/
__global__ void matrix_vector_multiplication(float *mat, float *vec, float *out, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
float sum = 0;
for (int k = 0; k < MULTIPLICATIONS; k++)
for (int i = 0; i < n; i++)
sum += mat[i * n + tid] * vec[i];
out[tid] = sum;
}
}
int main(int argc, char const *argv[])
{
if (argc != 2) {
fprintf(stderr, "usage: %s <n>\n", argv[0]);
exit(1);
}
int n = atoi(argv[1]);
if (n < 0) {
fprintf(stderr, "Invalid size\n");
exit(1);
}
// Host & device inputs and outputs
float *h_mat, *h_vec, *h_out;
float *d_mat, *d_vec, *d_out;
// Allocate host memory
h_mat = (float*) malloc(sizeof(float) * n * n);
h_vec = (float*) malloc(sizeof(float) * n);
h_out = (float*) malloc(sizeof(float) * n);
// Allocate device memory
cudaMalloc((void**) &d_mat, sizeof(float) * n * n);
cudaMalloc((void**) &d_vec, sizeof(float) * n);
cudaMalloc((void**) &d_out, sizeof(float) * n);
// Initialize host matrix
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
h_mat[i * n + j] = 0.05;
// Initialize host vector
for (int i = 0; i < n; i++)
h_vec[i] = 0.05;
// Transfer data from host to device memory
cudaMemcpy(d_mat, h_mat, sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_vec, h_vec, sizeof(float) * n, cudaMemcpyHostToDevice);
cudaEvent_t start, finish;
float elapsed_milliseconds;
// Use event to calculate time
cudaEventCreate(&start);
cudaEventCreate(&finish);
cudaEventRecord(start, 0);
matrix_vector_multiplication<<<n/THREADS_PER_BLOCK + 1, THREADS_PER_BLOCK>>>(d_mat, d_vec, d_out, n);
cudaEventRecord(finish, 0);
cudaEventSynchronize(finish); // Wait for stop event to complete
cudaEventElapsedTime(&elapsed_milliseconds, start, finish); // Calculate the time difference (millisecond level)
// Transfer data back to host memory
cudaMemcpy(h_out, d_out, sizeof(float) * n, cudaMemcpyDeviceToHost);
printf("%f\n", h_out[0]);
printf("GPU Elapsed time = %.2fs\n", elapsed_milliseconds/1000.0);
// Deallocate device memory
cudaFree(d_mat);
cudaFree(d_vec);
cudaFree(d_vec);
// Deallocate host memory
free(h_mat);
free(h_vec);
free(h_out);
return 0;
} | code for sm_80
Function : _Z28matrix_vector_multiplicationPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 MOV R26, RZ ; /* 0x000000ff001a8202 */
/* 0x000fe20000000f00 */
/*0090*/ @!P0 BRA 0xc80 ; /* 0x00000be000008947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00d0*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fe40000000f00 */
/*00e0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0110*/ IMAD.WIDE R10, R0, R11, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fe200078e020b */
/*0120*/ IADD3 R5, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fcc0007ffe1ff */
/*0130*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fc40000000f00 */
/*0150*/ ISETP.GE.U32.AND P2, PT, R4, 0x1000, PT ; /* 0x000010000400780c */
/* 0x000fe20003f46070 */
/*0160*/ @!P1 BRA 0xb10 ; /* 0x000009a000009947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R13, c[0x0][0x16c] ; /* 0x00005b00000d7a02 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fc40000000f00 */
/*01d0*/ MOV R15, R11 ; /* 0x0000000b000f7202 */
/* 0x000fe20000000f00 */
/*01e0*/ @!P0 BRA 0x980 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GT.AND P3, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f64270 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0210*/ @!P3 BRA 0x6c0 ; /* 0x000004a00000b947 */
/* 0x000fea0003800000 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0230*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0240*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R18, [R12.64+0x4] ; /* 0x000004040c127981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IMAD.WIDE R8, R7, c[0x0][0x178], R14 ; /* 0x00005e0007087a25 */
/* 0x000fc600078e020e */
/*0280*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x000f26000c1e1900 */
/*0290*/ IMAD.WIDE R28, R7.reuse, c[0x0][0x178], R8 ; /* 0x00005e00071c7a25 */
/* 0x040fe200078e0208 */
/*02a0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x000b28000c1e1900 */
/*02c0*/ LDG.E R25, [R12.64+0xc] ; /* 0x00000c040c197981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R14, [R12.64+0x10] ; /* 0x000010040c0e7981 */
/* 0x001f22000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7, c[0x0][0x178], R28 ; /* 0x00005e00071c7a25 */
/* 0x020fca00078e021c */
/*02f0*/ LDG.E R24, [R28.64] ; /* 0x000000041c187981 */
/* 0x000962000c1e1900 */
/*0300*/ IMAD.WIDE R8, R7, c[0x0][0x178], R28 ; /* 0x00005e0007087a25 */
/* 0x002fca00078e021c */
/*0310*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000562000c1e1900 */
/*0320*/ IMAD.WIDE R20, R7, c[0x0][0x178], R8 ; /* 0x00005e0007147a25 */
/* 0x000fca00078e0208 */
/*0330*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000162000c1e1900 */
/*0340*/ FFMA R8, R16, R17, R26 ; /* 0x0000001110087223 */
/* 0x004fc6000000001a */
/*0350*/ LDG.E R26, [R12.64+0x14] ; /* 0x000014040c1a7981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, c[0x0][0x178], R20 ; /* 0x00005e0007107a25 */
/* 0x000fc600078e0214 */
/*0370*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x001ea2000c1e1900 */
/*0380*/ FFMA R8, R18, R19, R8 ; /* 0x0000001312087223 */
/* 0x008fc60000000008 */
/*0390*/ LDG.E R19, [R12.64+0x18] ; /* 0x000018040c137981 */
/* 0x000ee8000c1e1900 */
/*03a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x0000e2000c1e1900 */
/*03b0*/ FFMA R28, R23, R22, R8 ; /* 0x00000016171c7223 */
/* 0x010fc60000000008 */
/*03c0*/ LDG.E R8, [R12.64+0x1c] ; /* 0x00001c040c087981 */
/* 0x000f22000c1e1900 */
/*03d0*/ IMAD.WIDE R16, R7, c[0x0][0x178], R16 ; /* 0x00005e0007107a25 */
/* 0x001fca00078e0210 */
/*03e0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000b22000c1e1900 */
/*03f0*/ IMAD.WIDE R22, R7, c[0x0][0x178], R16 ; /* 0x00005e0007167a25 */
/* 0x000fca00078e0210 */
/*0400*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000122000c1e1900 */
/*0410*/ FFMA R16, R25, R24, R28 ; /* 0x0000001819107223 */
/* 0x020fe4000000001c */
/*0420*/ IMAD.WIDE R24, R7.reuse, c[0x0][0x178], R22 ; /* 0x00005e0007187a25 */
/* 0x040fe200078e0216 */
/*0430*/ LDG.E R28, [R12.64+0x24] ; /* 0x000024040c1c7981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0450*/ FFMA R16, R14, R15, R16 ; /* 0x0000000f0e107223 */
/* 0x000fe40000000010 */
/*0460*/ IMAD.WIDE R14, R7, c[0x0][0x178], R24 ; /* 0x00005e00070e7a25 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R23, [R12.64+0x28] ; /* 0x000028040c177981 */
/* 0x001168000c1e1900 */
/*0480*/ LDG.E R22, [R12.64+0x30] ; /* 0x000030040c167981 */
/* 0x000162000c1e1900 */
/*0490*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x004fc40000000010 */
/*04a0*/ IMAD.WIDE R16, R7, c[0x0][0x178], R14 ; /* 0x00005e0007107a25 */
/* 0x000fe200078e020e */
/*04b0*/ LDG.E R27, [R12.64+0x2c] ; /* 0x00002c040c1b7981 */
/* 0x0000a8000c1e1900 */
/*04c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a2000c1e1900 */
/*04d0*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x008fc6000000001a */
/*04e0*/ LDG.E R15, [R12.64+0x34] ; /* 0x000034040c0f7981 */
/* 0x0010e2000c1e1900 */
/*04f0*/ IMAD.WIDE R18, R7, c[0x0][0x178], R16 ; /* 0x00005e0007127a25 */
/* 0x000fc600078e0210 */
/*0500*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0000e2000c1e1900 */
/*0510*/ FFMA R26, R8, R9, R26 ; /* 0x00000009081a7223 */
/* 0x010fe4000000001a */
/*0520*/ IMAD.WIDE R8, R7, c[0x0][0x178], R18 ; /* 0x00005e0007087a25 */
/* 0x000fe400078e0212 */
/*0530*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0008e4000c1e1900 */
/*0540*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R20, R7.reuse, c[0x0][0x178], R8 ; /* 0x00005e0007147a25 */
/* 0x040fe400078e0208 */
/*0560*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ae8000c1e1900 */
/*0570*/ IMAD.WIDE R24, R7, c[0x0][0x178], R20 ; /* 0x00005e0007187a25 */
/* 0x002fe200078e0214 */
/*0580*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x001ee6000c1e1900 */
/*0590*/ FFMA R29, R28, R29, R26 ; /* 0x0000001d1c1d7223 */
/* 0x020fe2000000001a */
/*05a0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x010f28000c1e1900 */
/*05b0*/ LDG.E R28, [R12.64+0x38] ; /* 0x000038040c1c7981 */
/* 0x000168000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x000122000c1e1900 */
/*05d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ ISETP.GT.AND P3, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f64270 */
/*05f0*/ IADD3 R9, P4, R12, 0x40, RZ ; /* 0x000000400c097810 */
/* 0x000fe40007f9e0ff */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0610*/ MOV R12, R9 ; /* 0x00000009000c7202 */
/* 0x001fe20000000f00 */
/*0620*/ FFMA R14, R23, R14, R29 ; /* 0x0000000e170e7223 */
/* 0x004fc8000000001d */
/*0630*/ FFMA R27, R27, R16, R14 ; /* 0x000000101b1b7223 */
/* 0x008fe2000000000e */
/*0640*/ IADD3.X R16, RZ, R13, RZ, P4, !PT ; /* 0x0000000dff107210 */
/* 0x000fc600027fe4ff */
/*0650*/ FFMA R18, R22, R18, R27 ; /* 0x0000001216127223 */
/* 0x000fc8000000001b */
/*0660*/ FFMA R8, R15, R8, R18 ; /* 0x000000080f087223 */
/* 0x000fe20000000012 */
/*0670*/ MOV R13, R16 ; /* 0x00000010000d7202 */
/* 0x000fe20000000f00 */
/*0680*/ IMAD.WIDE R14, R7, c[0x0][0x178], R24 ; /* 0x00005e00070e7a25 */
/* 0x000fc800078e0218 */
/*0690*/ FFMA R8, R28, R17, R8 ; /* 0x000000111c087223 */
/* 0x020fc80000000008 */
/*06a0*/ FFMA R26, R26, R19, R8 ; /* 0x000000131a1a7223 */
/* 0x010fe20000000008 */
/*06b0*/ @P3 BRA 0x230 ; /* 0xfffffb7000003947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P3, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f64270 */
/*06d0*/ @!P3 BRA 0x960 ; /* 0x000002800000b947 */
/* 0x000fea0003800000 */
/*06e0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*06f0*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x0000a8000c1e1900 */
/*0700*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ee2000c1e1900 */
/*0720*/ IMAD.WIDE R20, R7, c[0x0][0x178], R14 ; /* 0x00005e0007147a25 */
/* 0x000fc600078e020e */
/*0730*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*0740*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x0002e2000c1e1900 */
/*0750*/ IMAD.WIDE R16, R7, c[0x0][0x178], R20 ; /* 0x00005e0007107a25 */
/* 0x000fc600078e0214 */
/*0760*/ LDG.E R28, [R12.64+0xc] ; /* 0x00000c040c1c7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R18, R7.reuse, c[0x0][0x178], R16 ; /* 0x00005e0007127a25 */
/* 0x040fe400078e0210 */
/*0780*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000128000c1e1900 */
/*0790*/ IMAD.WIDE R8, R7.reuse, c[0x0][0x178], R18 ; /* 0x00005e0007087a25 */
/* 0x040fe200078e0212 */
/*07a0*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x00036a000c1e1900 */
/*07b0*/ IMAD.WIDE R14, R7, c[0x0][0x178], R8 ; /* 0x00005e00070e7a25 */
/* 0x001fc400078e0208 */
/*07c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000168000c1e1900 */
/*07d0*/ IMAD.WIDE R20, R7.reuse, c[0x0][0x178], R14 ; /* 0x00005e0007147a25 */
/* 0x042fe400078e020e */
/*07e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*07f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R18, R7, c[0x0][0x178], R20 ; /* 0x00005e0007127a25 */
/* 0x000fc600078e0214 */
/*0810*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000f62000c1e1900 */
/*0820*/ FFMA R27, R27, R23, R26 ; /* 0x000000171b1b7223 */
/* 0x004fc6000000001a */
/*0830*/ LDG.E R23, [R12.64+0x14] ; /* 0x000014040c177981 */
/* 0x0000a8000c1e1900 */
/*0840*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x0000a2000c1e1900 */
/*0850*/ FFMA R22, R22, R25, R27 ; /* 0x0000001916167223 */
/* 0x008fc6000000001b */
/*0860*/ LDG.E R27, [R12.64+0x18] ; /* 0x000018040c1b7981 */
/* 0x0000e8000c1e1900 */
/*0870*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ee2000c1e1900 */
/*0880*/ FFMA R17, R24, R17, R22 ; /* 0x0000001118117223 */
/* 0x010fc80000000016 */
/*0890*/ FFMA R17, R28, R29, R17 ; /* 0x0000001d1c117223 */
/* 0x020fe20000000011 */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08b0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ FFMA R8, R8, R9, R17 ; /* 0x0000000908087223 */
/* 0x000fe20000000011 */
/*08d0*/ IADD3 R9, P3, R12, 0x20, RZ ; /* 0x000000200c097810 */
/* 0x000fe40007f7e0ff */
/*08e0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ MOV R12, R9 ; /* 0x00000009000c7202 */
/* 0x001fe20000000f00 */
/*0900*/ FFMA R8, R23, R14, R8 ; /* 0x0000000e17087223 */
/* 0x004fc40000000008 */
/*0910*/ IMAD.WIDE R14, R7, c[0x0][0x178], R18 ; /* 0x00005e00070e7a25 */
/* 0x000fc800078e0212 */
/*0920*/ FFMA R8, R27, R16, R8 ; /* 0x000000101b087223 */
/* 0x008fe20000000008 */
/*0930*/ IADD3.X R16, RZ, R13, RZ, P3, !PT ; /* 0x0000000dff107210 */
/* 0x000fc60001ffe4ff */
/*0940*/ FFMA R26, R26, R25, R8 ; /* 0x000000191a1a7223 */
/* 0x000fe20000000008 */
/*0950*/ MOV R13, R16 ; /* 0x00000010000d7202 */
/* 0x000fe40000000f00 */
/*0960*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0970*/ @!P0 BRA 0xb10 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0990*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R20, [R12.64+0x4] ; /* 0x000004040c147981 */
/* 0x000ee8000c1e1900 */
/*09b0*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x000f22000c1e1900 */
/*09c0*/ IMAD.WIDE R8, R7, c[0x0][0x178], R14 ; /* 0x00005e0007087a25 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea6000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x178], R8 ; /* 0x00005e0007107a25 */
/* 0x040fe200078e0208 */
/*09f0*/ LDG.E R25, [R12.64+0xc] ; /* 0x00000c040c197981 */
/* 0x000168000c1e1900 */
/*0a00*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0a10*/ IMAD.WIDE R18, R7, c[0x0][0x178], R16 ; /* 0x00005e0007127a25 */
/* 0x000fc600078e0210 */
/*0a20*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a60*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ FFMA R21, R21, R14, R26 ; /* 0x0000000e15157223 */
/* 0x004fc8000000001a */
/*0a80*/ FFMA R20, R20, R8, R21 ; /* 0x0000000814147223 */
/* 0x008fe20000000015 */
/*0a90*/ IADD3 R21, P3, R12, 0x10, RZ ; /* 0x000000100c157810 */
/* 0x000fc60007f7e0ff */
/*0aa0*/ FFMA R20, R23, R22, R20 ; /* 0x0000001617147223 */
/* 0x010fe20000000014 */
/*0ab0*/ IADD3.X R8, RZ, R13, RZ, P3, !PT ; /* 0x0000000dff087210 */
/* 0x000fe20001ffe4ff */
/*0ac0*/ IMAD.WIDE R14, R7, c[0x0][0x178], R18 ; /* 0x00005e00070e7a25 */
/* 0x000fe200078e0212 */
/*0ad0*/ MOV R12, R21 ; /* 0x00000015000c7202 */
/* 0x001fe40000000f00 */
/*0ae0*/ MOV R13, R8 ; /* 0x00000008000d7202 */
/* 0x000fe20000000f00 */
/*0af0*/ FFMA R26, R25, R24, R20 ; /* 0x00000018191a7223 */
/* 0x020fe20000000014 */
/*0b00*/ @P0 BRA 0x980 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b10*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0b20*/ @!P0 BRA 0xc70 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0b30*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0b40*/ IMAD R12, R3, c[0x0][0x178], R0 ; /* 0x00005e00030c7a24 */
/* 0x000fd200078e0200 */
/*0b50*/ IMAD.WIDE R8, R12, R13, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e020d */
/*0b60*/ IMAD.WIDE R6, R3, R13, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fe400078e020d */
/*0b70*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0ba0*/ FFMA R26, R3, R8, R26 ; /* 0x00000008031a7223 */
/* 0x004fd8000000001a */
/*0bb0*/ @!P0 BRA 0xc70 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*0bd0*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040406037981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ IADD3 R8, R12, c[0x0][0x178], RZ ; /* 0x00005e000c087a10 */
/* 0x000fd60007ffe0ff */
/*0bf0*/ @P0 IADD3 R12, R8.reuse, c[0x0][0x178], RZ ; /* 0x00005e00080c0a10 */
/* 0x040fe20007ffe0ff */
/*0c00*/ IMAD.WIDE R8, R8, R13.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe200078e020d */
/*0c10*/ @P0 LDG.E R15, [R6.64+0x8] ; /* 0x00000804060f0981 */
/* 0x000ee6000c1e1900 */
/*0c20*/ @P0 IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c0625 */
/* 0x000fe400078e020d */
/*0c30*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ @P0 LDG.E R12, [R12.64] ; /* 0x000000040c0c0981 */
/* 0x000ee2000c1e1900 */
/*0c50*/ FFMA R26, R3, R8, R26 ; /* 0x00000008031a7223 */
/* 0x004fc8000000001a */
/*0c60*/ @P0 FFMA R26, R15, R12, R26 ; /* 0x0000000c0f1a0223 */
/* 0x008fe4000000001a */
/*0c70*/ @!P2 BRA 0x130 ; /* 0xfffff4b00000a947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c90*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0ca0*/ STG.E [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x000fe2000c101904 */
/*0cb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define THREADS_PER_BLOCK 256
#define MULTIPLICATIONS 4096
/**
* Multiply square matrix (n x n) by the vector of size n.
*
*
* @param mat Input matrix.
* @param vec Input vector.
* @param out Output vector.
* @param n Dimension.
*/
__global__ void matrix_vector_multiplication(float *mat, float *vec, float *out, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
float sum = 0;
for (int k = 0; k < MULTIPLICATIONS; k++)
for (int i = 0; i < n; i++)
sum += mat[i * n + tid] * vec[i];
out[tid] = sum;
}
}
int main(int argc, char const *argv[])
{
if (argc != 2) {
fprintf(stderr, "usage: %s <n>\n", argv[0]);
exit(1);
}
int n = atoi(argv[1]);
if (n < 0) {
fprintf(stderr, "Invalid size\n");
exit(1);
}
// Host & device inputs and outputs
float *h_mat, *h_vec, *h_out;
float *d_mat, *d_vec, *d_out;
// Allocate host memory
h_mat = (float*) malloc(sizeof(float) * n * n);
h_vec = (float*) malloc(sizeof(float) * n);
h_out = (float*) malloc(sizeof(float) * n);
// Allocate device memory
cudaMalloc((void**) &d_mat, sizeof(float) * n * n);
cudaMalloc((void**) &d_vec, sizeof(float) * n);
cudaMalloc((void**) &d_out, sizeof(float) * n);
// Initialize host matrix
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
h_mat[i * n + j] = 0.05;
// Initialize host vector
for (int i = 0; i < n; i++)
h_vec[i] = 0.05;
// Transfer data from host to device memory
cudaMemcpy(d_mat, h_mat, sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_vec, h_vec, sizeof(float) * n, cudaMemcpyHostToDevice);
cudaEvent_t start, finish;
float elapsed_milliseconds;
// Use event to calculate time
cudaEventCreate(&start);
cudaEventCreate(&finish);
cudaEventRecord(start, 0);
matrix_vector_multiplication<<<n/THREADS_PER_BLOCK + 1, THREADS_PER_BLOCK>>>(d_mat, d_vec, d_out, n);
cudaEventRecord(finish, 0);
cudaEventSynchronize(finish); // Wait for stop event to complete
cudaEventElapsedTime(&elapsed_milliseconds, start, finish); // Calculate the time difference (millisecond level)
// Transfer data back to host memory
cudaMemcpy(h_out, d_out, sizeof(float) * n, cudaMemcpyDeviceToHost);
printf("%f\n", h_out[0]);
printf("GPU Elapsed time = %.2fs\n", elapsed_milliseconds/1000.0);
// Deallocate device memory
cudaFree(d_mat);
cudaFree(d_vec);
cudaFree(d_vec);
// Deallocate host memory
free(h_mat);
free(h_vec);
free(h_out);
return 0;
} | .file "tmpxft_00019fe3_00000000-6_cuda_mat_vec_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
.type _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i, @function
_Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28matrix_vector_multiplicationPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i, .-_Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
.globl _Z28matrix_vector_multiplicationPfS_S_i
.type _Z28matrix_vector_multiplicationPfS_S_i, @function
_Z28matrix_vector_multiplicationPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28matrix_vector_multiplicationPfS_S_i, .-_Z28matrix_vector_multiplicationPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: %s <n>\n"
.LC1:
.string "Invalid size\n"
.LC3:
.string "%f\n"
.LC5:
.string "GPU Elapsed time = %.2fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L24
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r12d
testl %eax, %eax
js .L25
movslq %eax, %rbx
movq %rbx, %r15
imulq %rbx, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %ebp, %ebp
jle .L14
leal -1(%rbp), %esi
leaq 4(,%rsi,4), %rdi
movq 8(%rsp), %rax
leaq (%rax,%rdi), %rdx
movl $0, %ecx
notq %rsi
salq $2, %rsi
movss .LC2(%rip), %xmm0
.L15:
leaq (%rsi,%rdx), %rax
.L16:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
addl $1, %ecx
addq %rbx, %rdx
cmpl %r12d, %ecx
jne .L15
movq %r13, %rax
leaq 0(%r13,%rdi), %rdx
movss .LC2(%rip), %xmm0
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
.L14:
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L19:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
jmp .L19
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z28matrix_vector_multiplicationPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z28matrix_vector_multiplicationPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1028443341
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define THREADS_PER_BLOCK 256
#define MULTIPLICATIONS 4096
/**
* Multiply square matrix (n x n) by the vector of size n.
*
*
* @param mat Input matrix.
* @param vec Input vector.
* @param out Output vector.
* @param n Dimension.
*/
__global__ void matrix_vector_multiplication(float *mat, float *vec, float *out, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
float sum = 0;
for (int k = 0; k < MULTIPLICATIONS; k++)
for (int i = 0; i < n; i++)
sum += mat[i * n + tid] * vec[i];
out[tid] = sum;
}
}
int main(int argc, char const *argv[])
{
if (argc != 2) {
fprintf(stderr, "usage: %s <n>\n", argv[0]);
exit(1);
}
int n = atoi(argv[1]);
if (n < 0) {
fprintf(stderr, "Invalid size\n");
exit(1);
}
// Host & device inputs and outputs
float *h_mat, *h_vec, *h_out;
float *d_mat, *d_vec, *d_out;
// Allocate host memory
h_mat = (float*) malloc(sizeof(float) * n * n);
h_vec = (float*) malloc(sizeof(float) * n);
h_out = (float*) malloc(sizeof(float) * n);
// Allocate device memory
cudaMalloc((void**) &d_mat, sizeof(float) * n * n);
cudaMalloc((void**) &d_vec, sizeof(float) * n);
cudaMalloc((void**) &d_out, sizeof(float) * n);
// Initialize host matrix
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
h_mat[i * n + j] = 0.05;
// Initialize host vector
for (int i = 0; i < n; i++)
h_vec[i] = 0.05;
// Transfer data from host to device memory
cudaMemcpy(d_mat, h_mat, sizeof(float) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_vec, h_vec, sizeof(float) * n, cudaMemcpyHostToDevice);
cudaEvent_t start, finish;
float elapsed_milliseconds;
// Use event to calculate time
cudaEventCreate(&start);
cudaEventCreate(&finish);
cudaEventRecord(start, 0);
matrix_vector_multiplication<<<n/THREADS_PER_BLOCK + 1, THREADS_PER_BLOCK>>>(d_mat, d_vec, d_out, n);
cudaEventRecord(finish, 0);
cudaEventSynchronize(finish); // Wait for stop event to complete
cudaEventElapsedTime(&elapsed_milliseconds, start, finish); // Calculate the time difference (millisecond level)
// Transfer data back to host memory
cudaMemcpy(h_out, d_out, sizeof(float) * n, cudaMemcpyDeviceToHost);
printf("%f\n", h_out[0]);
printf("GPU Elapsed time = %.2fs\n", elapsed_milliseconds/1000.0);
// Deallocate device memory
cudaFree(d_mat);
cudaFree(d_vec);
cudaFree(d_vec);
// Deallocate host memory
free(h_mat);
free(h_vec);
free(h_out);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 256
#define MULTIPLICATIONS 4096
/**
* Multiply square matrix (n x n) by the vector of size n.
*
*
* @param mat Input matrix.
* @param vec Input vector.
* @param out Output vector.
* @param n Dimension.
*/
__global__ void matrix_vector_multiplication(float *mat, float *vec, float *out, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
float sum = 0;
for (int k = 0; k < MULTIPLICATIONS; k++)
for (int i = 0; i < n; i++)
sum += mat[i * n + tid] * vec[i];
out[tid] = sum;
}
}
int main(int argc, char const *argv[])
{
if (argc != 2) {
fprintf(stderr, "usage: %s <n>\n", argv[0]);
exit(1);
}
int n = atoi(argv[1]);
if (n < 0) {
fprintf(stderr, "Invalid size\n");
exit(1);
}
// Host & device inputs and outputs
float *h_mat, *h_vec, *h_out;
float *d_mat, *d_vec, *d_out;
// Allocate host memory
h_mat = (float*) malloc(sizeof(float) * n * n);
h_vec = (float*) malloc(sizeof(float) * n);
h_out = (float*) malloc(sizeof(float) * n);
// Allocate device memory
hipMalloc((void**) &d_mat, sizeof(float) * n * n);
hipMalloc((void**) &d_vec, sizeof(float) * n);
hipMalloc((void**) &d_out, sizeof(float) * n);
// Initialize host matrix
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
h_mat[i * n + j] = 0.05;
// Initialize host vector
for (int i = 0; i < n; i++)
h_vec[i] = 0.05;
// Transfer data from host to device memory
hipMemcpy(d_mat, h_mat, sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(d_vec, h_vec, sizeof(float) * n, hipMemcpyHostToDevice);
hipEvent_t start, finish;
float elapsed_milliseconds;
// Use event to calculate time
hipEventCreate(&start);
hipEventCreate(&finish);
hipEventRecord(start, 0);
matrix_vector_multiplication<<<n/THREADS_PER_BLOCK + 1, THREADS_PER_BLOCK>>>(d_mat, d_vec, d_out, n);
hipEventRecord(finish, 0);
hipEventSynchronize(finish); // Wait for stop event to complete
hipEventElapsedTime(&elapsed_milliseconds, start, finish); // Calculate the time difference (millisecond level)
// Transfer data back to host memory
hipMemcpy(h_out, d_out, sizeof(float) * n, hipMemcpyDeviceToHost);
printf("%f\n", h_out[0]);
printf("GPU Elapsed time = %.2fs\n", elapsed_milliseconds/1000.0);
// Deallocate device memory
hipFree(d_mat);
hipFree(d_vec);
hipFree(d_vec);
// Deallocate host memory
free(h_mat);
free(h_vec);
free(h_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 256
#define MULTIPLICATIONS 4096
/**
* Multiply square matrix (n x n) by the vector of size n.
*
*
* @param mat Input matrix.
* @param vec Input vector.
* @param out Output vector.
* @param n Dimension.
*/
__global__ void matrix_vector_multiplication(float *mat, float *vec, float *out, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
float sum = 0;
for (int k = 0; k < MULTIPLICATIONS; k++)
for (int i = 0; i < n; i++)
sum += mat[i * n + tid] * vec[i];
out[tid] = sum;
}
}
int main(int argc, char const *argv[])
{
if (argc != 2) {
fprintf(stderr, "usage: %s <n>\n", argv[0]);
exit(1);
}
int n = atoi(argv[1]);
if (n < 0) {
fprintf(stderr, "Invalid size\n");
exit(1);
}
// Host & device inputs and outputs
float *h_mat, *h_vec, *h_out;
float *d_mat, *d_vec, *d_out;
// Allocate host memory
h_mat = (float*) malloc(sizeof(float) * n * n);
h_vec = (float*) malloc(sizeof(float) * n);
h_out = (float*) malloc(sizeof(float) * n);
// Allocate device memory
hipMalloc((void**) &d_mat, sizeof(float) * n * n);
hipMalloc((void**) &d_vec, sizeof(float) * n);
hipMalloc((void**) &d_out, sizeof(float) * n);
// Initialize host matrix
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
h_mat[i * n + j] = 0.05;
// Initialize host vector
for (int i = 0; i < n; i++)
h_vec[i] = 0.05;
// Transfer data from host to device memory
hipMemcpy(d_mat, h_mat, sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(d_vec, h_vec, sizeof(float) * n, hipMemcpyHostToDevice);
hipEvent_t start, finish;
float elapsed_milliseconds;
// Use event to calculate time
hipEventCreate(&start);
hipEventCreate(&finish);
hipEventRecord(start, 0);
matrix_vector_multiplication<<<n/THREADS_PER_BLOCK + 1, THREADS_PER_BLOCK>>>(d_mat, d_vec, d_out, n);
hipEventRecord(finish, 0);
hipEventSynchronize(finish); // Wait for stop event to complete
hipEventElapsedTime(&elapsed_milliseconds, start, finish); // Calculate the time difference (millisecond level)
// Transfer data back to host memory
hipMemcpy(h_out, d_out, sizeof(float) * n, hipMemcpyDeviceToHost);
printf("%f\n", h_out[0]);
printf("GPU Elapsed time = %.2fs\n", elapsed_milliseconds/1000.0);
// Deallocate device memory
hipFree(d_mat);
hipFree(d_vec);
hipFree(d_vec);
// Deallocate host memory
free(h_mat);
free(h_vec);
free(h_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28matrix_vector_multiplicationPfS_S_i
.globl _Z28matrix_vector_multiplicationPfS_S_i
.p2align 8
.type _Z28matrix_vector_multiplicationPfS_S_i,@function
_Z28matrix_vector_multiplicationPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_cmp_gt_i32 s8, 0
s_mov_b32 s10, 0
s_cselect_b32 s9, -1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s10, 0x1000
s_cbranch_scc1 .LBB0_5
.LBB0_3:
v_mov_b32_e32 v2, v1
s_and_not1_b32 vcc_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_mov_b64 s[2:3], s[6:7]
s_mov_b32 s11, s8
s_cbranch_vccnz .LBB0_2
.p2align 6
.LBB0_4:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s12, s[2:3], 0x0
s_add_i32 s11, s11, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_cmp_eq_u32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s12, v3
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28matrix_vector_multiplicationPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28matrix_vector_multiplicationPfS_S_i, .Lfunc_end0-_Z28matrix_vector_multiplicationPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28matrix_vector_multiplicationPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28matrix_vector_multiplicationPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define THREADS_PER_BLOCK 256
#define MULTIPLICATIONS 4096
/**
* Multiply square matrix (n x n) by the vector of size n.
*
*
* @param mat Input matrix.
* @param vec Input vector.
* @param out Output vector.
* @param n Dimension.
*/
__global__ void matrix_vector_multiplication(float *mat, float *vec, float *out, int n)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
float sum = 0;
for (int k = 0; k < MULTIPLICATIONS; k++)
for (int i = 0; i < n; i++)
sum += mat[i * n + tid] * vec[i];
out[tid] = sum;
}
}
int main(int argc, char const *argv[])
{
if (argc != 2) {
fprintf(stderr, "usage: %s <n>\n", argv[0]);
exit(1);
}
int n = atoi(argv[1]);
if (n < 0) {
fprintf(stderr, "Invalid size\n");
exit(1);
}
// Host & device inputs and outputs
float *h_mat, *h_vec, *h_out;
float *d_mat, *d_vec, *d_out;
// Allocate host memory
h_mat = (float*) malloc(sizeof(float) * n * n);
h_vec = (float*) malloc(sizeof(float) * n);
h_out = (float*) malloc(sizeof(float) * n);
// Allocate device memory
hipMalloc((void**) &d_mat, sizeof(float) * n * n);
hipMalloc((void**) &d_vec, sizeof(float) * n);
hipMalloc((void**) &d_out, sizeof(float) * n);
// Initialize host matrix
for (int i = 0; i < n; i++)
for (int j = 0; j < n; j++)
h_mat[i * n + j] = 0.05;
// Initialize host vector
for (int i = 0; i < n; i++)
h_vec[i] = 0.05;
// Transfer data from host to device memory
hipMemcpy(d_mat, h_mat, sizeof(float) * n * n, hipMemcpyHostToDevice);
hipMemcpy(d_vec, h_vec, sizeof(float) * n, hipMemcpyHostToDevice);
hipEvent_t start, finish;
float elapsed_milliseconds;
// Use event to calculate time
hipEventCreate(&start);
hipEventCreate(&finish);
hipEventRecord(start, 0);
matrix_vector_multiplication<<<n/THREADS_PER_BLOCK + 1, THREADS_PER_BLOCK>>>(d_mat, d_vec, d_out, n);
hipEventRecord(finish, 0);
hipEventSynchronize(finish); // Wait for stop event to complete
hipEventElapsedTime(&elapsed_milliseconds, start, finish); // Calculate the time difference (millisecond level)
// Transfer data back to host memory
hipMemcpy(h_out, d_out, sizeof(float) * n, hipMemcpyDeviceToHost);
printf("%f\n", h_out[0]);
printf("GPU Elapsed time = %.2fs\n", elapsed_milliseconds/1000.0);
// Deallocate device memory
hipFree(d_mat);
hipFree(d_vec);
hipFree(d_vec);
// Deallocate host memory
free(h_mat);
free(h_vec);
free(h_out);
return 0;
} | .text
.file "cuda_mat_vec_multiplication.hip"
.globl _Z43__device_stub__matrix_vector_multiplicationPfS_S_i # -- Begin function _Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.p2align 4, 0x90
.type _Z43__device_stub__matrix_vector_multiplicationPfS_S_i,@function
_Z43__device_stub__matrix_vector_multiplicationPfS_S_i: # @_Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28matrix_vector_multiplicationPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z43__device_stub__matrix_vector_multiplicationPfS_S_i, .Lfunc_end0-_Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_12
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
testl %r13d, %r13d
js .LBB1_13
# %bb.2:
movl %r13d, %ebp
leaq (,%rbp,4), %r12
imulq %r12, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %r13d, %r13d
je .LBB1_9
# %bb.3: # %.preheader49.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_4: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movl %ecx, %esi
leaq (%rbx,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1028443341, (%rsi,%rdi,4) # imm = 0x3D4CCCCD
incq %rdi
cmpq %rdi, %rax
jne .LBB1_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB1_4 Depth=1
incq %rdx
addl %r13d, %ecx
cmpq %rax, %rdx
jne .LBB1_4
# %bb.7: # %.lr.ph53.preheader
cmpl $2, %r13d
movl $1, %eax
cmovgel %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_8: # %.lr.ph53
# =>This Inner Loop Header: Depth=1
movl $1028443341, (%r14,%rcx,4) # imm = 0x3D4CCCCD
incq %rcx
cmpq %rcx, %rax
jne .LBB1_8
.LBB1_9: # %._crit_edge54
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r13d, %eax
shrl $8, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z28matrix_vector_multiplicationPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 48(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_13:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $13, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28matrix_vector_multiplicationPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28matrix_vector_multiplicationPfS_S_i,@object # @_Z28matrix_vector_multiplicationPfS_S_i
.section .rodata,"a",@progbits
.globl _Z28matrix_vector_multiplicationPfS_S_i
.p2align 3, 0x0
_Z28matrix_vector_multiplicationPfS_S_i:
.quad _Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.size _Z28matrix_vector_multiplicationPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s <n>\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Invalid size\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Elapsed time = %.2fs\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28matrix_vector_multiplicationPfS_S_i"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28matrix_vector_multiplicationPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28matrix_vector_multiplicationPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 MOV R26, RZ ; /* 0x000000ff001a8202 */
/* 0x000fe20000000f00 */
/*0090*/ @!P0 BRA 0xc80 ; /* 0x00000be000008947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00d0*/ MOV R26, RZ ; /* 0x000000ff001a7202 */
/* 0x000fe40000000f00 */
/*00e0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0110*/ IMAD.WIDE R10, R0, R11, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fe200078e020b */
/*0120*/ IADD3 R5, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a10 */
/* 0x000fcc0007ffe1ff */
/*0130*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fc40000000f00 */
/*0150*/ ISETP.GE.U32.AND P2, PT, R4, 0x1000, PT ; /* 0x000010000400780c */
/* 0x000fe20003f46070 */
/*0160*/ @!P1 BRA 0xb10 ; /* 0x000009a000009947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R12, c[0x0][0x168] ; /* 0x00005a00000c7a02 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R13, c[0x0][0x16c] ; /* 0x00005b00000d7a02 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R14, R10 ; /* 0x0000000a000e7202 */
/* 0x000fc40000000f00 */
/*01d0*/ MOV R15, R11 ; /* 0x0000000b000f7202 */
/* 0x000fe20000000f00 */
/*01e0*/ @!P0 BRA 0x980 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.GT.AND P3, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f64270 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0210*/ @!P3 BRA 0x6c0 ; /* 0x000004a00000b947 */
/* 0x000fea0003800000 */
/*0220*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0230*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0240*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R18, [R12.64+0x4] ; /* 0x000004040c127981 */
/* 0x000ee2000c1e1900 */
/*0270*/ IMAD.WIDE R8, R7, c[0x0][0x178], R14 ; /* 0x00005e0007087a25 */
/* 0x000fc600078e020e */
/*0280*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x000f26000c1e1900 */
/*0290*/ IMAD.WIDE R28, R7.reuse, c[0x0][0x178], R8 ; /* 0x00005e00071c7a25 */
/* 0x040fe200078e0208 */
/*02a0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x000b28000c1e1900 */
/*02c0*/ LDG.E R25, [R12.64+0xc] ; /* 0x00000c040c197981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R14, [R12.64+0x10] ; /* 0x000010040c0e7981 */
/* 0x001f22000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7, c[0x0][0x178], R28 ; /* 0x00005e00071c7a25 */
/* 0x020fca00078e021c */
/*02f0*/ LDG.E R24, [R28.64] ; /* 0x000000041c187981 */
/* 0x000962000c1e1900 */
/*0300*/ IMAD.WIDE R8, R7, c[0x0][0x178], R28 ; /* 0x00005e0007087a25 */
/* 0x002fca00078e021c */
/*0310*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000562000c1e1900 */
/*0320*/ IMAD.WIDE R20, R7, c[0x0][0x178], R8 ; /* 0x00005e0007147a25 */
/* 0x000fca00078e0208 */
/*0330*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000162000c1e1900 */
/*0340*/ FFMA R8, R16, R17, R26 ; /* 0x0000001110087223 */
/* 0x004fc6000000001a */
/*0350*/ LDG.E R26, [R12.64+0x14] ; /* 0x000014040c1a7981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, c[0x0][0x178], R20 ; /* 0x00005e0007107a25 */
/* 0x000fc600078e0214 */
/*0370*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x001ea2000c1e1900 */
/*0380*/ FFMA R8, R18, R19, R8 ; /* 0x0000001312087223 */
/* 0x008fc60000000008 */
/*0390*/ LDG.E R19, [R12.64+0x18] ; /* 0x000018040c137981 */
/* 0x000ee8000c1e1900 */
/*03a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x0000e2000c1e1900 */
/*03b0*/ FFMA R28, R23, R22, R8 ; /* 0x00000016171c7223 */
/* 0x010fc60000000008 */
/*03c0*/ LDG.E R8, [R12.64+0x1c] ; /* 0x00001c040c087981 */
/* 0x000f22000c1e1900 */
/*03d0*/ IMAD.WIDE R16, R7, c[0x0][0x178], R16 ; /* 0x00005e0007107a25 */
/* 0x001fca00078e0210 */
/*03e0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000b22000c1e1900 */
/*03f0*/ IMAD.WIDE R22, R7, c[0x0][0x178], R16 ; /* 0x00005e0007167a25 */
/* 0x000fca00078e0210 */
/*0400*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000122000c1e1900 */
/*0410*/ FFMA R16, R25, R24, R28 ; /* 0x0000001819107223 */
/* 0x020fe4000000001c */
/*0420*/ IMAD.WIDE R24, R7.reuse, c[0x0][0x178], R22 ; /* 0x00005e0007187a25 */
/* 0x040fe200078e0216 */
/*0430*/ LDG.E R28, [R12.64+0x24] ; /* 0x000024040c1c7981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0450*/ FFMA R16, R14, R15, R16 ; /* 0x0000000f0e107223 */
/* 0x000fe40000000010 */
/*0460*/ IMAD.WIDE R14, R7, c[0x0][0x178], R24 ; /* 0x00005e00070e7a25 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R23, [R12.64+0x28] ; /* 0x000028040c177981 */
/* 0x001168000c1e1900 */
/*0480*/ LDG.E R22, [R12.64+0x30] ; /* 0x000030040c167981 */
/* 0x000162000c1e1900 */
/*0490*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x004fc40000000010 */
/*04a0*/ IMAD.WIDE R16, R7, c[0x0][0x178], R14 ; /* 0x00005e0007107a25 */
/* 0x000fe200078e020e */
/*04b0*/ LDG.E R27, [R12.64+0x2c] ; /* 0x00002c040c1b7981 */
/* 0x0000a8000c1e1900 */
/*04c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a2000c1e1900 */
/*04d0*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x008fc6000000001a */
/*04e0*/ LDG.E R15, [R12.64+0x34] ; /* 0x000034040c0f7981 */
/* 0x0010e2000c1e1900 */
/*04f0*/ IMAD.WIDE R18, R7, c[0x0][0x178], R16 ; /* 0x00005e0007127a25 */
/* 0x000fc600078e0210 */
/*0500*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0000e2000c1e1900 */
/*0510*/ FFMA R26, R8, R9, R26 ; /* 0x00000009081a7223 */
/* 0x010fe4000000001a */
/*0520*/ IMAD.WIDE R8, R7, c[0x0][0x178], R18 ; /* 0x00005e0007087a25 */
/* 0x000fe400078e0212 */
/*0530*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0008e4000c1e1900 */
/*0540*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R20, R7.reuse, c[0x0][0x178], R8 ; /* 0x00005e0007147a25 */
/* 0x040fe400078e0208 */
/*0560*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ae8000c1e1900 */
/*0570*/ IMAD.WIDE R24, R7, c[0x0][0x178], R20 ; /* 0x00005e0007187a25 */
/* 0x002fe200078e0214 */
/*0580*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x001ee6000c1e1900 */
/*0590*/ FFMA R29, R28, R29, R26 ; /* 0x0000001d1c1d7223 */
/* 0x020fe2000000001a */
/*05a0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x010f28000c1e1900 */
/*05b0*/ LDG.E R28, [R12.64+0x38] ; /* 0x000038040c1c7981 */
/* 0x000168000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x000122000c1e1900 */
/*05d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ ISETP.GT.AND P3, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f64270 */
/*05f0*/ IADD3 R9, P4, R12, 0x40, RZ ; /* 0x000000400c097810 */
/* 0x000fe40007f9e0ff */
/*0600*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0610*/ MOV R12, R9 ; /* 0x00000009000c7202 */
/* 0x001fe20000000f00 */
/*0620*/ FFMA R14, R23, R14, R29 ; /* 0x0000000e170e7223 */
/* 0x004fc8000000001d */
/*0630*/ FFMA R27, R27, R16, R14 ; /* 0x000000101b1b7223 */
/* 0x008fe2000000000e */
/*0640*/ IADD3.X R16, RZ, R13, RZ, P4, !PT ; /* 0x0000000dff107210 */
/* 0x000fc600027fe4ff */
/*0650*/ FFMA R18, R22, R18, R27 ; /* 0x0000001216127223 */
/* 0x000fc8000000001b */
/*0660*/ FFMA R8, R15, R8, R18 ; /* 0x000000080f087223 */
/* 0x000fe20000000012 */
/*0670*/ MOV R13, R16 ; /* 0x00000010000d7202 */
/* 0x000fe20000000f00 */
/*0680*/ IMAD.WIDE R14, R7, c[0x0][0x178], R24 ; /* 0x00005e00070e7a25 */
/* 0x000fc800078e0218 */
/*0690*/ FFMA R8, R28, R17, R8 ; /* 0x000000111c087223 */
/* 0x020fc80000000008 */
/*06a0*/ FFMA R26, R26, R19, R8 ; /* 0x000000131a1a7223 */
/* 0x010fe20000000008 */
/*06b0*/ @P3 BRA 0x230 ; /* 0xfffffb7000003947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P3, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f64270 */
/*06d0*/ @!P3 BRA 0x960 ; /* 0x000002800000b947 */
/* 0x000fea0003800000 */
/*06e0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*06f0*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x0000a8000c1e1900 */
/*0700*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ee2000c1e1900 */
/*0720*/ IMAD.WIDE R20, R7, c[0x0][0x178], R14 ; /* 0x00005e0007147a25 */
/* 0x000fc600078e020e */
/*0730*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f28000c1e1900 */
/*0740*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x0002e2000c1e1900 */
/*0750*/ IMAD.WIDE R16, R7, c[0x0][0x178], R20 ; /* 0x00005e0007107a25 */
/* 0x000fc600078e0214 */
/*0760*/ LDG.E R28, [R12.64+0xc] ; /* 0x00000c040c1c7981 */
/* 0x000f66000c1e1900 */
/*0770*/ IMAD.WIDE R18, R7.reuse, c[0x0][0x178], R16 ; /* 0x00005e0007127a25 */
/* 0x040fe400078e0210 */
/*0780*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000128000c1e1900 */
/*0790*/ IMAD.WIDE R8, R7.reuse, c[0x0][0x178], R18 ; /* 0x00005e0007087a25 */
/* 0x040fe200078e0212 */
/*07a0*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x00036a000c1e1900 */
/*07b0*/ IMAD.WIDE R14, R7, c[0x0][0x178], R8 ; /* 0x00005e00070e7a25 */
/* 0x001fc400078e0208 */
/*07c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000168000c1e1900 */
/*07d0*/ IMAD.WIDE R20, R7.reuse, c[0x0][0x178], R14 ; /* 0x00005e0007147a25 */
/* 0x042fe400078e020e */
/*07e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f68000c1e1900 */
/*07f0*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R18, R7, c[0x0][0x178], R20 ; /* 0x00005e0007127a25 */
/* 0x000fc600078e0214 */
/*0810*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000f62000c1e1900 */
/*0820*/ FFMA R27, R27, R23, R26 ; /* 0x000000171b1b7223 */
/* 0x004fc6000000001a */
/*0830*/ LDG.E R23, [R12.64+0x14] ; /* 0x000014040c177981 */
/* 0x0000a8000c1e1900 */
/*0840*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x0000a2000c1e1900 */
/*0850*/ FFMA R22, R22, R25, R27 ; /* 0x0000001916167223 */
/* 0x008fc6000000001b */
/*0860*/ LDG.E R27, [R12.64+0x18] ; /* 0x000018040c1b7981 */
/* 0x0000e8000c1e1900 */
/*0870*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ee2000c1e1900 */
/*0880*/ FFMA R17, R24, R17, R22 ; /* 0x0000001118117223 */
/* 0x010fc80000000016 */
/*0890*/ FFMA R17, R28, R29, R17 ; /* 0x0000001d1c117223 */
/* 0x020fe20000000011 */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08b0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ FFMA R8, R8, R9, R17 ; /* 0x0000000908087223 */
/* 0x000fe20000000011 */
/*08d0*/ IADD3 R9, P3, R12, 0x20, RZ ; /* 0x000000200c097810 */
/* 0x000fe40007f7e0ff */
/*08e0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ MOV R12, R9 ; /* 0x00000009000c7202 */
/* 0x001fe20000000f00 */
/*0900*/ FFMA R8, R23, R14, R8 ; /* 0x0000000e17087223 */
/* 0x004fc40000000008 */
/*0910*/ IMAD.WIDE R14, R7, c[0x0][0x178], R18 ; /* 0x00005e00070e7a25 */
/* 0x000fc800078e0212 */
/*0920*/ FFMA R8, R27, R16, R8 ; /* 0x000000101b087223 */
/* 0x008fe20000000008 */
/*0930*/ IADD3.X R16, RZ, R13, RZ, P3, !PT ; /* 0x0000000dff107210 */
/* 0x000fc60001ffe4ff */
/*0940*/ FFMA R26, R26, R25, R8 ; /* 0x000000191a1a7223 */
/* 0x000fe20000000008 */
/*0950*/ MOV R13, R16 ; /* 0x00000010000d7202 */
/* 0x000fe40000000f00 */
/*0960*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0970*/ @!P0 BRA 0xb10 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0990*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R20, [R12.64+0x4] ; /* 0x000004040c147981 */
/* 0x000ee8000c1e1900 */
/*09b0*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x000f22000c1e1900 */
/*09c0*/ IMAD.WIDE R8, R7, c[0x0][0x178], R14 ; /* 0x00005e0007087a25 */
/* 0x000fc600078e020e */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea6000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R7.reuse, c[0x0][0x178], R8 ; /* 0x00005e0007107a25 */
/* 0x040fe200078e0208 */
/*09f0*/ LDG.E R25, [R12.64+0xc] ; /* 0x00000c040c197981 */
/* 0x000168000c1e1900 */
/*0a00*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0a10*/ IMAD.WIDE R18, R7, c[0x0][0x178], R16 ; /* 0x00005e0007127a25 */
/* 0x000fc600078e0210 */
/*0a20*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a60*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ FFMA R21, R21, R14, R26 ; /* 0x0000000e15157223 */
/* 0x004fc8000000001a */
/*0a80*/ FFMA R20, R20, R8, R21 ; /* 0x0000000814147223 */
/* 0x008fe20000000015 */
/*0a90*/ IADD3 R21, P3, R12, 0x10, RZ ; /* 0x000000100c157810 */
/* 0x000fc60007f7e0ff */
/*0aa0*/ FFMA R20, R23, R22, R20 ; /* 0x0000001617147223 */
/* 0x010fe20000000014 */
/*0ab0*/ IADD3.X R8, RZ, R13, RZ, P3, !PT ; /* 0x0000000dff087210 */
/* 0x000fe20001ffe4ff */
/*0ac0*/ IMAD.WIDE R14, R7, c[0x0][0x178], R18 ; /* 0x00005e00070e7a25 */
/* 0x000fe200078e0212 */
/*0ad0*/ MOV R12, R21 ; /* 0x00000015000c7202 */
/* 0x001fe40000000f00 */
/*0ae0*/ MOV R13, R8 ; /* 0x00000008000d7202 */
/* 0x000fe20000000f00 */
/*0af0*/ FFMA R26, R25, R24, R20 ; /* 0x00000018191a7223 */
/* 0x020fe20000000014 */
/*0b00*/ @P0 BRA 0x980 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b10*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0b20*/ @!P0 BRA 0xc70 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0b30*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0b40*/ IMAD R12, R3, c[0x0][0x178], R0 ; /* 0x00005e00030c7a24 */
/* 0x000fd200078e0200 */
/*0b50*/ IMAD.WIDE R8, R12, R13, c[0x0][0x160] ; /* 0x000058000c087625 */
/* 0x000fc800078e020d */
/*0b60*/ IMAD.WIDE R6, R3, R13, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fe400078e020d */
/*0b70*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05270 */
/*0ba0*/ FFMA R26, R3, R8, R26 ; /* 0x00000008031a7223 */
/* 0x004fd8000000001a */
/*0bb0*/ @!P0 BRA 0xc70 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05270 */
/*0bd0*/ LDG.E R3, [R6.64+0x4] ; /* 0x0000040406037981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ IADD3 R8, R12, c[0x0][0x178], RZ ; /* 0x00005e000c087a10 */
/* 0x000fd60007ffe0ff */
/*0bf0*/ @P0 IADD3 R12, R8.reuse, c[0x0][0x178], RZ ; /* 0x00005e00080c0a10 */
/* 0x040fe20007ffe0ff */
/*0c00*/ IMAD.WIDE R8, R8, R13.reuse, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x080fe200078e020d */
/*0c10*/ @P0 LDG.E R15, [R6.64+0x8] ; /* 0x00000804060f0981 */
/* 0x000ee6000c1e1900 */
/*0c20*/ @P0 IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c0625 */
/* 0x000fe400078e020d */
/*0c30*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ @P0 LDG.E R12, [R12.64] ; /* 0x000000040c0c0981 */
/* 0x000ee2000c1e1900 */
/*0c50*/ FFMA R26, R3, R8, R26 ; /* 0x00000008031a7223 */
/* 0x004fc8000000001a */
/*0c60*/ @P0 FFMA R26, R15, R12, R26 ; /* 0x0000000c0f1a0223 */
/* 0x008fe4000000001a */
/*0c70*/ @!P2 BRA 0x130 ; /* 0xfffff4b00000a947 */
/* 0x000fea000383ffff */
/*0c80*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0c90*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0ca0*/ STG.E [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x000fe2000c101904 */
/*0cb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28matrix_vector_multiplicationPfS_S_i
.globl _Z28matrix_vector_multiplicationPfS_S_i
.p2align 8
.type _Z28matrix_vector_multiplicationPfS_S_i,@function
_Z28matrix_vector_multiplicationPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_cmp_gt_i32 s8, 0
s_mov_b32 s10, 0
s_cselect_b32 s9, -1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s10, 0x1000
s_cbranch_scc1 .LBB0_5
.LBB0_3:
v_mov_b32_e32 v2, v1
s_and_not1_b32 vcc_lo, exec_lo, s9
s_waitcnt lgkmcnt(0)
s_mov_b64 s[2:3], s[6:7]
s_mov_b32 s11, s8
s_cbranch_vccnz .LBB0_2
.p2align 6
.LBB0_4:
v_ashrrev_i32_e32 v3, 31, v2
s_load_b32 s12, s[2:3], 0x0
s_add_i32 s11, s11, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s8, v2
s_cmp_eq_u32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s12, v3
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28matrix_vector_multiplicationPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28matrix_vector_multiplicationPfS_S_i, .Lfunc_end0-_Z28matrix_vector_multiplicationPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28matrix_vector_multiplicationPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28matrix_vector_multiplicationPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00019fe3_00000000-6_cuda_mat_vec_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
.type _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i, @function
_Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28matrix_vector_multiplicationPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i, .-_Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
.globl _Z28matrix_vector_multiplicationPfS_S_i
.type _Z28matrix_vector_multiplicationPfS_S_i, @function
_Z28matrix_vector_multiplicationPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z28matrix_vector_multiplicationPfS_S_i, .-_Z28matrix_vector_multiplicationPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: %s <n>\n"
.LC1:
.string "Invalid size\n"
.LC3:
.string "%f\n"
.LC5:
.string "GPU Elapsed time = %.2fs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L24
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r12d
testl %eax, %eax
js .L25
movslq %eax, %rbx
movq %rbx, %r15
imulq %rbx, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %ebp, %ebp
jle .L14
leal -1(%rbp), %esi
leaq 4(,%rsi,4), %rdi
movq 8(%rsp), %rax
leaq (%rax,%rdi), %rdx
movl $0, %ecx
notq %rsi
salq $2, %rsi
movss .LC2(%rip), %xmm0
.L15:
leaq (%rsi,%rdx), %rax
.L16:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
addl $1, %ecx
addq %rbx, %rdx
cmpl %r12d, %ecx
jne .L15
movq %r13, %rax
leaq 0(%r13,%rdi), %rdx
movss .LC2(%rip), %xmm0
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
.L14:
movl $1, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leal 255(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $8, %eax
addl $1, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L19:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L25:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L26:
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z53__device_stub__Z28matrix_vector_multiplicationPfS_S_iPfS_S_i
jmp .L19
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z28matrix_vector_multiplicationPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z28matrix_vector_multiplicationPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1028443341
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_mat_vec_multiplication.hip"
.globl _Z43__device_stub__matrix_vector_multiplicationPfS_S_i # -- Begin function _Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.p2align 4, 0x90
.type _Z43__device_stub__matrix_vector_multiplicationPfS_S_i,@function
_Z43__device_stub__matrix_vector_multiplicationPfS_S_i: # @_Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28matrix_vector_multiplicationPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z43__device_stub__matrix_vector_multiplicationPfS_S_i, .Lfunc_end0-_Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_12
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
testl %r13d, %r13d
js .LBB1_13
# %bb.2:
movl %r13d, %ebp
leaq (,%rbp,4), %r12
imulq %r12, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %r13d, %r13d
je .LBB1_9
# %bb.3: # %.preheader49.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_4: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
movl %ecx, %esi
leaq (%rbx,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movl $1028443341, (%rsi,%rdi,4) # imm = 0x3D4CCCCD
incq %rdi
cmpq %rdi, %rax
jne .LBB1_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB1_4 Depth=1
incq %rdx
addl %r13d, %ecx
cmpq %rax, %rdx
jne .LBB1_4
# %bb.7: # %.lr.ph53.preheader
cmpl $2, %r13d
movl $1, %eax
cmovgel %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_8: # %.lr.ph53
# =>This Inner Loop Header: Depth=1
movl $1028443341, (%r14,%rcx,4) # imm = 0x3D4CCCCD
incq %rcx
cmpq %rcx, %rax
jne .LBB1_8
.LBB1_9: # %._crit_edge54
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r13d, %eax
shrl $8, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rdx,%rax), %rdi
incq %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z28matrix_vector_multiplicationPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 48(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movq (%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_13:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $13, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28matrix_vector_multiplicationPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28matrix_vector_multiplicationPfS_S_i,@object # @_Z28matrix_vector_multiplicationPfS_S_i
.section .rodata,"a",@progbits
.globl _Z28matrix_vector_multiplicationPfS_S_i
.p2align 3, 0x0
_Z28matrix_vector_multiplicationPfS_S_i:
.quad _Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.size _Z28matrix_vector_multiplicationPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s <n>\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Invalid size\n"
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Elapsed time = %.2fs\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28matrix_vector_multiplicationPfS_S_i"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__matrix_vector_multiplicationPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28matrix_vector_multiplicationPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C"
{
}
__global__ void elSq(int N, int M, float *Mat)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
if (i < N && j < M)
{
Mat[index] = __fmul_rn(Mat[index], Mat[index]);
}
} | code for sm_80
Function : _Z4elSqiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
{
}
__global__ void elSq(int N, int M, float *Mat)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
if (i < N && j < M)
{
Mat[index] = __fmul_rn(Mat[index], Mat[index]);
}
} | .file "tmpxft_00178d01_00000000-6_elSq.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4elSqiiPfiiPf
.type _Z25__device_stub__Z4elSqiiPfiiPf, @function
_Z25__device_stub__Z4elSqiiPfiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4elSqiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4elSqiiPfiiPf, .-_Z25__device_stub__Z4elSqiiPfiiPf
.globl _Z4elSqiiPf
.type _Z4elSqiiPf, @function
_Z4elSqiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4elSqiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4elSqiiPf, .-_Z4elSqiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4elSqiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4elSqiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
{
}
__global__ void elSq(int N, int M, float *Mat)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
if (i < N && j < M)
{
Mat[index] = __fmul_rn(Mat[index], Mat[index]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void elSq(int N, int M, float *Mat)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
if (i < N && j < M)
{
Mat[index] = __fmul_rn(Mat[index], Mat[index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void elSq(int N, int M, float *Mat)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
if (i < N && j < M)
{
Mat[index] = __fmul_rn(Mat[index], Mat[index]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4elSqiiPf
.globl _Z4elSqiiPf
.p2align 8
.type _Z4elSqiiPf,@function
_Z4elSqiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4elSqiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4elSqiiPf, .Lfunc_end0-_Z4elSqiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4elSqiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4elSqiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
{
}
__global__ void elSq(int N, int M, float *Mat)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
if (i < N && j < M)
{
Mat[index] = __fmul_rn(Mat[index], Mat[index]);
}
} | .text
.file "elSq.hip"
.globl _Z19__device_stub__elSqiiPf # -- Begin function _Z19__device_stub__elSqiiPf
.p2align 4, 0x90
.type _Z19__device_stub__elSqiiPf,@function
_Z19__device_stub__elSqiiPf: # @_Z19__device_stub__elSqiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4elSqiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__elSqiiPf, .Lfunc_end0-_Z19__device_stub__elSqiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4elSqiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4elSqiiPf,@object # @_Z4elSqiiPf
.section .rodata,"a",@progbits
.globl _Z4elSqiiPf
.p2align 3, 0x0
_Z4elSqiiPf:
.quad _Z19__device_stub__elSqiiPf
.size _Z4elSqiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4elSqiiPf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__elSqiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4elSqiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4elSqiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4elSqiiPf
.globl _Z4elSqiiPf
.p2align 8
.type _Z4elSqiiPf,@function
_Z4elSqiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4elSqiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4elSqiiPf, .Lfunc_end0-_Z4elSqiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4elSqiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4elSqiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178d01_00000000-6_elSq.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4elSqiiPfiiPf
.type _Z25__device_stub__Z4elSqiiPfiiPf, @function
_Z25__device_stub__Z4elSqiiPfiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4elSqiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4elSqiiPfiiPf, .-_Z25__device_stub__Z4elSqiiPfiiPf
.globl _Z4elSqiiPf
.type _Z4elSqiiPf, @function
_Z4elSqiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4elSqiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4elSqiiPf, .-_Z4elSqiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4elSqiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4elSqiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "elSq.hip"
.globl _Z19__device_stub__elSqiiPf # -- Begin function _Z19__device_stub__elSqiiPf
.p2align 4, 0x90
.type _Z19__device_stub__elSqiiPf,@function
_Z19__device_stub__elSqiiPf: # @_Z19__device_stub__elSqiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4elSqiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__elSqiiPf, .Lfunc_end0-_Z19__device_stub__elSqiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4elSqiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4elSqiiPf,@object # @_Z4elSqiiPf
.section .rodata,"a",@progbits
.globl _Z4elSqiiPf
.p2align 3, 0x0
_Z4elSqiiPf:
.quad _Z19__device_stub__elSqiiPf
.size _Z4elSqiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4elSqiiPf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__elSqiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4elSqiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernelUpdateParticle(double *positions, double *velocities, double *pBests, double *gBest, int particlesCount, int dimensionsCount, double r1, double r2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= particlesCount * dimensionsCount)
return;
velocities[i] = d_OMEGA * velocities[i] + r1 * (pBests[i] - positions[i])
+ r2 * (gBest[i % dimensionsCount] - positions[i]);
// Update posisi particle
positions[i] += velocities[i];
} | code for sm_80
Function : _Z20kernelUpdateParticlePdS_S_S_iidd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x184] ; /* 0x0000610000057a13 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GE.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f46270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*00d0*/ IMAD.WIDE R8, R4, R15, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fcc00078e020f */
/*00e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0140*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0150*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R0, R5, R3, R6 ; /* 0x0000000305007224 */
/* 0x000fe400078e0206 */
/*01a0*/ IMAD.WIDE R2, R4, R15, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc600078e020f */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f04070 */
/*01c0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000eb6000c1e1b00 */
/*01d0*/ @!P0 IADD3 R0, R0, -R5, RZ ; /* 0x8000000500008210 */
/* 0x000fc40007ffe0ff */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R0, R0, -R5, RZ ; /* 0x8000000500009210 */
/* 0x000fc80007ffe0ff */
/*0210*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0220*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff008a12 */
/* 0x000fe200078e33ff */
/*0230*/ IMAD.WIDE R4, R4, R15, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020f */
/*0240*/ IMAD.WIDE R14, R0, R15, c[0x0][0x178] ; /* 0x00005e00000e7625 */
/* 0x000fe200078e020f */
/*0250*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000eea000c1e1b00 */
/*0260*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1b00 */
/*0270*/ DADD R12, -R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004e0c0000000108 */
/*0280*/ DMUL R12, R12, c[0x0][0x188] ; /* 0x000062000c0c7a28 */
/* 0x001ecc0000000000 */
/*0290*/ DFMA R6, R6, c[0x3][0x0], R12 ; /* 0x00c0000006067a2b */
/* 0x008fc8000000000c */
/*02a0*/ DADD R10, -R10, R14 ; /* 0x000000000a0a7229 */
/* 0x010e0c000000010e */
/*02b0*/ DFMA R6, R10, c[0x0][0x190], R6 ; /* 0x000064000a067a2b */
/* 0x001e0e0000000006 */
/*02c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe8000c101b04 */
/*02d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*02e0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x004e0e0000000008 */
/*02f0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x001fe2000c101b04 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernelUpdateParticle(double *positions, double *velocities, double *pBests, double *gBest, int particlesCount, int dimensionsCount, double r1, double r2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= particlesCount * dimensionsCount)
return;
velocities[i] = d_OMEGA * velocities[i] + r1 * (pBests[i] - positions[i])
+ r2 * (gBest[i % dimensionsCount] - positions[i]);
// Update posisi particle
positions[i] += velocities[i];
} | .file "tmpxft_00143470_00000000-6_kernelUpdateParticle.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd
.type _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd, @function
_Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20kernelUpdateParticlePdS_S_S_iidd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd, .-_Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd
.globl _Z20kernelUpdateParticlePdS_S_S_iidd
.type _Z20kernelUpdateParticlePdS_S_S_iidd, @function
_Z20kernelUpdateParticlePdS_S_S_iidd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20kernelUpdateParticlePdS_S_S_iidd, .-_Z20kernelUpdateParticlePdS_S_S_iidd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20kernelUpdateParticlePdS_S_S_iidd"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "d_OMEGA"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kernelUpdateParticlePdS_S_S_iidd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_OMEGA(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7d_OMEGA
.comm _ZL7d_OMEGA,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernelUpdateParticle(double *positions, double *velocities, double *pBests, double *gBest, int particlesCount, int dimensionsCount, double r1, double r2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= particlesCount * dimensionsCount)
return;
velocities[i] = d_OMEGA * velocities[i] + r1 * (pBests[i] - positions[i])
+ r2 * (gBest[i % dimensionsCount] - positions[i]);
// Update posisi particle
positions[i] += velocities[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelUpdateParticle(double *positions, double *velocities, double *pBests, double *gBest, int particlesCount, int dimensionsCount, double r1, double r2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= particlesCount * dimensionsCount)
return;
velocities[i] = d_OMEGA * velocities[i] + r1 * (pBests[i] - positions[i])
+ r2 * (gBest[i % dimensionsCount] - positions[i]);
// Update posisi particle
positions[i] += velocities[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelUpdateParticle(double *positions, double *velocities, double *pBests, double *gBest, int particlesCount, int dimensionsCount, double r1, double r2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= particlesCount * dimensionsCount)
return;
velocities[i] = d_OMEGA * velocities[i] + r1 * (pBests[i] - positions[i])
+ r2 * (gBest[i % dimensionsCount] - positions[i]);
// Update posisi particle
positions[i] += velocities[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20kernelUpdateParticlePdS_S_S_iidd
.globl _Z20kernelUpdateParticlePdS_S_S_iidd
.p2align 8
.type _Z20kernelUpdateParticlePdS_S_S_iidd,@function
_Z20kernelUpdateParticlePdS_S_S_iidd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s2, s3, 31
s_load_b256 s[4:11], s[0:1], 0x0
s_add_i32 s3, s3, s2
v_ashrrev_i32_e32 v9, 31, v1
s_xor_b32 s2, s3, s2
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v11, v1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v11, v11, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v8, v0
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_mul_lo_u32 v0, s3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v8, v0
global_load_b64 v[0:1], v[4:5], off
global_load_b64 v[4:5], v[6:7], off
v_add_nc_u32_e32 v8, v8, v10
v_mul_hi_u32 v8, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v8, s2
v_sub_nc_u32_e32 v8, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s2, v8
v_cmp_le_u32_e32 vcc_lo, s2, v8
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s2, v8
v_cmp_le_u32_e32 vcc_lo, s2, v8
s_load_b128 s[0:3], s[0:1], 0x28
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, v8, v9
v_sub_nc_u32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_load_b64 v[10:11], v[2:3], off
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(2)
v_add_f64 v[0:1], v[0:1], -v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_OMEGA@rel32@lo+4
s_addc_u32 s1, s1, d_OMEGA@rel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], s[0:1], v[10:11], v[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[8:9], -v[4:5]
v_fma_f64 v[0:1], v[4:5], s[2:3], v[0:1]
global_store_b64 v[2:3], v[0:1], off
global_load_b64 v[2:3], v[6:7], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
global_store_b64 v[6:7], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20kernelUpdateParticlePdS_S_S_iidd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20kernelUpdateParticlePdS_S_S_iidd, .Lfunc_end0-_Z20kernelUpdateParticlePdS_S_S_iidd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_OMEGA
.type d_OMEGA,@object
.data
.globl d_OMEGA
.p2align 3, 0x0
d_OMEGA:
.quad 0x3fe47ae147ae147b
.size d_OMEGA, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_OMEGA
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20kernelUpdateParticlePdS_S_S_iidd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20kernelUpdateParticlePdS_S_S_iidd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelUpdateParticle(double *positions, double *velocities, double *pBests, double *gBest, int particlesCount, int dimensionsCount, double r1, double r2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i >= particlesCount * dimensionsCount)
return;
velocities[i] = d_OMEGA * velocities[i] + r1 * (pBests[i] - positions[i])
+ r2 * (gBest[i % dimensionsCount] - positions[i]);
// Update posisi particle
positions[i] += velocities[i];
} | .text
.file "kernelUpdateParticle.hip"
.globl _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd # -- Begin function _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.p2align 4, 0x90
.type _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd,@function
_Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd: # @_Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20kernelUpdateParticlePdS_S_S_iidd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd, .Lfunc_end0-_Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kernelUpdateParticlePdS_S_S_iidd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_OMEGA, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_OMEGA,@object # @d_OMEGA
.local d_OMEGA
.comm d_OMEGA,8,8
.type _Z20kernelUpdateParticlePdS_S_S_iidd,@object # @_Z20kernelUpdateParticlePdS_S_S_iidd
.section .rodata,"a",@progbits
.globl _Z20kernelUpdateParticlePdS_S_S_iidd
.p2align 3, 0x0
_Z20kernelUpdateParticlePdS_S_S_iidd:
.quad _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.size _Z20kernelUpdateParticlePdS_S_S_iidd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20kernelUpdateParticlePdS_S_S_iidd"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_OMEGA"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_OMEGA
.addrsig_sym _Z20kernelUpdateParticlePdS_S_S_iidd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20kernelUpdateParticlePdS_S_S_iidd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x184] ; /* 0x0000610000057a13 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GE.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f46270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*00d0*/ IMAD.WIDE R8, R4, R15, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fcc00078e020f */
/*00e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0120*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0140*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0150*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0190*/ IMAD R0, R5, R3, R6 ; /* 0x0000000305007224 */
/* 0x000fe400078e0206 */
/*01a0*/ IMAD.WIDE R2, R4, R15, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc600078e020f */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f04070 */
/*01c0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000eb6000c1e1b00 */
/*01d0*/ @!P0 IADD3 R0, R0, -R5, RZ ; /* 0x8000000500008210 */
/* 0x000fc40007ffe0ff */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R0, R0, -R5, RZ ; /* 0x8000000500009210 */
/* 0x000fc80007ffe0ff */
/*0210*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0220*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff008a12 */
/* 0x000fe200078e33ff */
/*0230*/ IMAD.WIDE R4, R4, R15, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020f */
/*0240*/ IMAD.WIDE R14, R0, R15, c[0x0][0x178] ; /* 0x00005e00000e7625 */
/* 0x000fe200078e020f */
/*0250*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000eea000c1e1b00 */
/*0260*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1b00 */
/*0270*/ DADD R12, -R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004e0c0000000108 */
/*0280*/ DMUL R12, R12, c[0x0][0x188] ; /* 0x000062000c0c7a28 */
/* 0x001ecc0000000000 */
/*0290*/ DFMA R6, R6, c[0x3][0x0], R12 ; /* 0x00c0000006067a2b */
/* 0x008fc8000000000c */
/*02a0*/ DADD R10, -R10, R14 ; /* 0x000000000a0a7229 */
/* 0x010e0c000000010e */
/*02b0*/ DFMA R6, R10, c[0x0][0x190], R6 ; /* 0x000064000a067a2b */
/* 0x001e0e0000000006 */
/*02c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe8000c101b04 */
/*02d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*02e0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x004e0e0000000008 */
/*02f0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x001fe2000c101b04 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20kernelUpdateParticlePdS_S_S_iidd
.globl _Z20kernelUpdateParticlePdS_S_S_iidd
.p2align 8
.type _Z20kernelUpdateParticlePdS_S_S_iidd,@function
_Z20kernelUpdateParticlePdS_S_S_iidd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s2, s3, 31
s_load_b256 s[4:11], s[0:1], 0x0
s_add_i32 s3, s3, s2
v_ashrrev_i32_e32 v9, 31, v1
s_xor_b32 s2, s3, s2
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v11, v1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v11, v11, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v8, v0
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_mul_lo_u32 v0, s3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v8, v0
global_load_b64 v[0:1], v[4:5], off
global_load_b64 v[4:5], v[6:7], off
v_add_nc_u32_e32 v8, v8, v10
v_mul_hi_u32 v8, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v8, s2
v_sub_nc_u32_e32 v8, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s2, v8
v_cmp_le_u32_e32 vcc_lo, s2, v8
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s2, v8
v_cmp_le_u32_e32 vcc_lo, s2, v8
s_load_b128 s[0:3], s[0:1], 0x28
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, v8, v9
v_sub_nc_u32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 3, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_load_b64 v[10:11], v[2:3], off
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(2)
v_add_f64 v[0:1], v[0:1], -v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, d_OMEGA@rel32@lo+4
s_addc_u32 s1, s1, d_OMEGA@rel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], s[0:1], v[10:11], v[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[8:9], -v[4:5]
v_fma_f64 v[0:1], v[4:5], s[2:3], v[0:1]
global_store_b64 v[2:3], v[0:1], off
global_load_b64 v[2:3], v[6:7], off
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
global_store_b64 v[6:7], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20kernelUpdateParticlePdS_S_S_iidd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20kernelUpdateParticlePdS_S_S_iidd, .Lfunc_end0-_Z20kernelUpdateParticlePdS_S_S_iidd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_OMEGA
.type d_OMEGA,@object
.data
.globl d_OMEGA
.p2align 3, 0x0
d_OMEGA:
.quad 0x3fe47ae147ae147b
.size d_OMEGA, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_OMEGA
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20kernelUpdateParticlePdS_S_S_iidd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20kernelUpdateParticlePdS_S_S_iidd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00143470_00000000-6_kernelUpdateParticle.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd
.type _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd, @function
_Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z20kernelUpdateParticlePdS_S_S_iidd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd, .-_Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd
.globl _Z20kernelUpdateParticlePdS_S_S_iidd
.type _Z20kernelUpdateParticlePdS_S_S_iidd, @function
_Z20kernelUpdateParticlePdS_S_S_iidd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z20kernelUpdateParticlePdS_S_S_iiddPdS_S_S_iidd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20kernelUpdateParticlePdS_S_S_iidd, .-_Z20kernelUpdateParticlePdS_S_S_iidd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20kernelUpdateParticlePdS_S_S_iidd"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "d_OMEGA"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20kernelUpdateParticlePdS_S_S_iidd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_OMEGA(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7d_OMEGA
.comm _ZL7d_OMEGA,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelUpdateParticle.hip"
.globl _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd # -- Begin function _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.p2align 4, 0x90
.type _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd,@function
_Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd: # @_Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z20kernelUpdateParticlePdS_S_S_iidd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd, .Lfunc_end0-_Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20kernelUpdateParticlePdS_S_S_iidd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_OMEGA, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_OMEGA,@object # @d_OMEGA
.local d_OMEGA
.comm d_OMEGA,8,8
.type _Z20kernelUpdateParticlePdS_S_S_iidd,@object # @_Z20kernelUpdateParticlePdS_S_S_iidd
.section .rodata,"a",@progbits
.globl _Z20kernelUpdateParticlePdS_S_S_iidd
.p2align 3, 0x0
_Z20kernelUpdateParticlePdS_S_S_iidd:
.quad _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.size _Z20kernelUpdateParticlePdS_S_S_iidd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20kernelUpdateParticlePdS_S_S_iidd"
.size .L__unnamed_1, 37
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_OMEGA"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__kernelUpdateParticlePdS_S_S_iidd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_OMEGA
.addrsig_sym _Z20kernelUpdateParticlePdS_S_S_iidd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Compute the padding activation.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @param value the padding value.
* @return nothing.
*/
extern "C"
__global__ void activation(long *x_shape, float *x, long *y_shape, float *y, float value)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
if (threadIdx.x >= x_shape[0] || blockIdx.x >= x_shape[1] || blockIdx.y >= x_shape[2] || blockIdx.z >= x_shape[3]) {
y[y_index] = value;
} else {
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
}
}
/**
* Compute the gradients with respect to the inputs.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @return nothing.
*/
extern "C"
__global__ void inputs_gradients(long *x_shape, float *x, long *y_shape, float *y)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
} | code for sm_80
Function : inputs_gradients
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0040*/ LDG.E R6, [R2.64+0x10] ; /* 0x0000100402067981 */
/* 0x000ea8000c1e1900 */
/*0050*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180402097981 */
/* 0x000ea8000c1e1900 */
/*0060*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000ee2000c1e1900 */
/*0070*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e220000002500 */
/*0080*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fc40000000f00 */
/*0090*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000ee20000002100 */
/*00a0*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc80000000f00 */
/*00b0*/ S2UR UR7, SR_CTAID.Y ; /* 0x00000000000779c3 */
/* 0x000e620000002600 */
/*00c0*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000f28000c1e1900 */
/*00d0*/ LDG.E R7, [R4.64+0x18] ; /* 0x0000180404077981 */
/* 0x000f26000c1e1900 */
/*00e0*/ S2UR UR8, SR_CTAID.Z ; /* 0x00000000000879c3 */
/* 0x000f620000002700 */
/*00f0*/ IMAD R12, R9, R6, RZ ; /* 0x00000006090c7224 */
/* 0x004fe400078e02ff */
/*0100*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD R10, R12, UR6, RZ ; /* 0x000000060c0a7c24 */
/* 0x001fc4000f8e02ff */
/*0120*/ IMAD R3, R8, R11, RZ ; /* 0x0000000b08037224 */
/* 0x008fe400078e02ff */
/*0130*/ IMAD R10, R9, UR7, R10 ; /* 0x00000007090a7c24 */
/* 0x002fe2000f8e020a */
/*0140*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fc600000001ff */
/*0150*/ IMAD R2, R12, R3, R10 ; /* 0x000000030c027224 */
/* 0x000fca00078e020a */
/*0160*/ IADD3 R2, R2, UR8, RZ ; /* 0x0000000802027c10 */
/* 0x020fca000fffe0ff */
/*0170*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0209 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0190*/ IMAD R8, R7, R0, RZ ; /* 0x0000000007087224 */
/* 0x010fc800078e02ff */
/*01a0*/ IMAD R0, R8, UR6, RZ ; /* 0x0000000608007c24 */
/* 0x000fc8000f8e02ff */
/*01b0*/ IMAD R0, R7, UR7, R0 ; /* 0x0000000707007c24 */
/* 0x000fe4000f8e0200 */
/*01c0*/ IMAD R11, R6, R11, RZ ; /* 0x0000000b060b7224 */
/* 0x004fc800078e02ff */
/*01d0*/ IMAD R0, R8, R11, R0 ; /* 0x0000000b08007224 */
/* 0x000fca00078e0200 */
/*01e0*/ IADD3 R4, R0, UR8, RZ ; /* 0x0000000800047c10 */
/* 0x000fca000fffe0ff */
/*01f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fca00078e0209 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x008fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : activation
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0060*/ LDG.E R0, [R6.64+0x18] ; /* 0x0000180406007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R9, [R6.64+0x10] ; /* 0x0000100406097981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ee8000c1e1b00 */
/*0090*/ LDG.E R8, [R6.64+0x8] ; /* 0x0000080406087981 */
/* 0x000f22000c1e1900 */
/*00a0*/ S2UR UR6, SR_CTAID.X ; /* 0x00000000000679c3 */
/* 0x000e260000002500 */
/*00b0*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000eea0000002100 */
/*00c0*/ S2UR UR7, SR_CTAID.Y ; /* 0x00000000000779c3 */
/* 0x000e700000002600 */
/*00d0*/ S2UR UR8, SR_CTAID.Z ; /* 0x00000000000879c3 */
/* 0x000f620000002700 */
/*00e0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*00f0*/ BSSY B0, 0x270 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD R10, R0, R9, RZ ; /* 0x00000009000a7224 */
/* 0x004fc800078e02ff */
/*0110*/ IMAD R9, R10, UR6, RZ ; /* 0x000000060a097c24 */
/* 0x001fe2000f8e02ff */
/*0120*/ ISETP.GT.U32.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x008fc60003f04070 */
/*0130*/ IMAD R0, R0, UR7, R9 ; /* 0x0000000700007c24 */
/* 0x002fe2000f8e0209 */
/*0140*/ ISETP.GT.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f04300 */
/*0150*/ IMAD R9, R8, R11, RZ ; /* 0x0000000b08097224 */
/* 0x010fc800078e02ff */
/*0160*/ IMAD R0, R10, R9, R0 ; /* 0x000000090a007224 */
/* 0x000fca00078e0200 */
/*0170*/ IADD3 R4, R0, UR8, RZ ; /* 0x0000000800047c10 */
/* 0x020fca000fffe0ff */
/*0180*/ IMAD.WIDE R4, R4, R13, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e020d */
/*0190*/ @!P0 BRA 0x260 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ea4000c1e1b00 */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R6, UR6, PT ; /* 0x0000000606007c0c */
/* 0x004fc8000bf04070 */
/*01c0*/ ISETP.GT.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0003f04300 */
/*01d0*/ @!P0 BRA 0x260 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E.64 R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000ea4000c1e1b00 */
/*01f0*/ ISETP.GT.U32.AND P0, PT, R8, UR7, PT ; /* 0x0000000708007c0c */
/* 0x004fc8000bf04070 */
/*0200*/ ISETP.GT.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f04300 */
/*0210*/ @!P0 BRA 0x260 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0220*/ LDG.E.64 R2, [R2.64+0x18] ; /* 0x0000180402027981 */
/* 0x000ea4000c1e1b00 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R2, UR8, PT ; /* 0x0000000802007c0c */
/* 0x004fc8000bf04070 */
/*0240*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0003f04300 */
/*0250*/ @P0 BRA 0x2a0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ MOV R3, c[0x0][0x180] ; /* 0x0000600000037a02 */
/* 0x000fca0000000f00 */
/*0280*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ IMAD R8, R2, R8, RZ ; /* 0x0000000802087224 */
/* 0x000fe400078e02ff */
/*02b0*/ IMAD R7, R6, R11, RZ ; /* 0x0000000b06077224 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD R3, R8, UR6, RZ ; /* 0x0000000608037c24 */
/* 0x000fc8000f8e02ff */
/*02d0*/ IMAD R3, R2, UR7, R3 ; /* 0x0000000702037c24 */
/* 0x000fc8000f8e0203 */
/*02e0*/ IMAD R2, R8, R7, R3 ; /* 0x0000000708027224 */
/* 0x000fca00078e0203 */
/*02f0*/ IADD3 R2, R2, UR8, RZ ; /* 0x0000000802027c10 */
/* 0x000fca000fffe0ff */
/*0300*/ IMAD.WIDE R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e020d */
/*0310*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0320*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Compute the padding activation.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @param value the padding value.
* @return nothing.
*/
extern "C"
__global__ void activation(long *x_shape, float *x, long *y_shape, float *y, float value)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
if (threadIdx.x >= x_shape[0] || blockIdx.x >= x_shape[1] || blockIdx.y >= x_shape[2] || blockIdx.z >= x_shape[3]) {
y[y_index] = value;
} else {
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
}
}
/**
* Compute the gradients with respect to the inputs.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @return nothing.
*/
extern "C"
__global__ void inputs_gradients(long *x_shape, float *x, long *y_shape, float *y)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
} | .file "tmpxft_0010e88e_00000000-6_pad_2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10activationPlPfS_S0_fPlPfS_S0_f
.type _Z38__device_stub__Z10activationPlPfS_S0_fPlPfS_S0_f, @function
_Z38__device_stub__Z10activationPlPfS_S0_fPlPfS_S0_f:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq activation(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z10activationPlPfS_S0_fPlPfS_S0_f, .-_Z38__device_stub__Z10activationPlPfS_S0_fPlPfS_S0_f
.globl activation
.type activation, @function
activation:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10activationPlPfS_S0_fPlPfS_S0_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size activation, .-activation
.globl _Z43__device_stub__Z16inputs_gradientsPlPfS_S0_PlPfS_S0_
.type _Z43__device_stub__Z16inputs_gradientsPlPfS_S0_PlPfS_S0_, @function
_Z43__device_stub__Z16inputs_gradientsPlPfS_S0_PlPfS_S0_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq inputs_gradients(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z43__device_stub__Z16inputs_gradientsPlPfS_S0_PlPfS_S0_, .-_Z43__device_stub__Z16inputs_gradientsPlPfS_S0_PlPfS_S0_
.globl inputs_gradients
.type inputs_gradients, @function
inputs_gradients:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16inputs_gradientsPlPfS_S0_PlPfS_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size inputs_gradients, .-inputs_gradients
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "inputs_gradients"
.LC1:
.string "activation"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq inputs_gradients(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq activation(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Compute the padding activation.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @param value the padding value.
* @return nothing.
*/
extern "C"
__global__ void activation(long *x_shape, float *x, long *y_shape, float *y, float value)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
if (threadIdx.x >= x_shape[0] || blockIdx.x >= x_shape[1] || blockIdx.y >= x_shape[2] || blockIdx.z >= x_shape[3]) {
y[y_index] = value;
} else {
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
}
}
/**
* Compute the gradients with respect to the inputs.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @return nothing.
*/
extern "C"
__global__ void inputs_gradients(long *x_shape, float *x, long *y_shape, float *y)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
} | #include <hip/hip_runtime.h>
/**
* Compute the padding activation.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @param value the padding value.
* @return nothing.
*/
extern "C"
__global__ void activation(long *x_shape, float *x, long *y_shape, float *y, float value)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
if (threadIdx.x >= x_shape[0] || blockIdx.x >= x_shape[1] || blockIdx.y >= x_shape[2] || blockIdx.z >= x_shape[3]) {
y[y_index] = value;
} else {
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
}
}
/**
* Compute the gradients with respect to the inputs.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @return nothing.
*/
extern "C"
__global__ void inputs_gradients(long *x_shape, float *x, long *y_shape, float *y)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/**
* Compute the padding activation.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @param value the padding value.
* @return nothing.
*/
extern "C"
__global__ void activation(long *x_shape, float *x, long *y_shape, float *y, float value)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
if (threadIdx.x >= x_shape[0] || blockIdx.x >= x_shape[1] || blockIdx.y >= x_shape[2] || blockIdx.z >= x_shape[3]) {
y[y_index] = value;
} else {
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
}
}
/**
* Compute the gradients with respect to the inputs.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @return nothing.
*/
extern "C"
__global__ void inputs_gradients(long *x_shape, float *x, long *y_shape, float *y)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected activation
.globl activation
.p2align 8
.type activation,@function
activation:
s_mov_b32 s8, s13
s_clause 0x2
s_load_b64 s[12:13], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b32 s20, s[0:1], 0x20
v_mov_b32_e32 v1, 0
s_mov_b32 s2, s15
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_load_b64 s[16:17], s[12:13], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[10:11], 0x8
s_load_b64 s[10:11], s[10:11], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i64_e32 vcc_lo, s[16:17], v[0:1]
v_mov_b32_e32 v1, s20
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[16:17], s[12:13], 0x8
s_mov_b32 s9, s15
v_mov_b32_e32 v1, s20
s_waitcnt lgkmcnt(0)
v_cmp_le_i64_e64 s3, s[16:17], s[8:9]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[18:19], s[12:13], 0x10
v_mov_b32_e32 v1, s20
s_waitcnt lgkmcnt(0)
v_cmp_le_i64_e64 s3, s[18:19], s[14:15]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[12:13], s[12:13], 0x18
s_mov_b32 s3, 0
v_mov_b32_e32 v1, s20
s_waitcnt lgkmcnt(0)
v_cmp_le_i64_e64 s3, s[12:13], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
v_mul_lo_u32 v1, s16, v0
s_mul_i32 s3, s12, s18
s_load_b64 s[16:17], s[0:1], 0x8
s_mul_i32 s7, s12, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v1, v1, s3
s_mul_i32 s3, s8, s3
s_add_i32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, s3, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s16, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s17, v2, vcc_lo
global_load_b32 v1, v[1:2], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
v_mul_lo_u32 v0, s4, v0
s_mul_i32 s3, s10, s6
s_load_b64 s[0:1], s[0:1], 0x18
s_mul_i32 s4, s10, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, v0, s3
s_mul_i32 s3, s8, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v2, s2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel activation
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size activation, .Lfunc_end0-activation
.section .AMDGPU.csdata,"",@progbits
.text
.protected inputs_gradients
.globl inputs_gradients
.p2align 8
.type inputs_gradients,@function
inputs_gradients:
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b32 s8, s[0:1], 0x8
s_load_b32 s9, s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s8, v0
s_mul_i32 s1, s0, s9
s_mul_i32 s0, s0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v1, v1, s1
s_mul_i32 s1, s13, s1
s_add_i32 s1, s15, s1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v1, s1, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
s_clause 0x2
s_load_b32 s0, s[4:5], 0x8
s_load_b32 s1, s[4:5], 0x10
s_load_b32 s2, s[4:5], 0x18
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s0, v0
s_mul_i32 s0, s2, s1
s_mul_i32 s2, s2, s14
s_mul_i32 s13, s13, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s15, s15, s13
v_mul_lo_u32 v0, v0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s2, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel inputs_gradients
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size inputs_gradients, .Lfunc_end1-inputs_gradients
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: activation
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: activation.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: inputs_gradients
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: inputs_gradients.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/**
* Compute the padding activation.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @param value the padding value.
* @return nothing.
*/
extern "C"
__global__ void activation(long *x_shape, float *x, long *y_shape, float *y, float value)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
if (threadIdx.x >= x_shape[0] || blockIdx.x >= x_shape[1] || blockIdx.y >= x_shape[2] || blockIdx.z >= x_shape[3]) {
y[y_index] = value;
} else {
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
}
}
/**
* Compute the gradients with respect to the inputs.
* @param x_shape the shape of the input buffer.
* @param x the input buffer.
* @param y_shape the shape of the output buffer.
* @param y the output buffer.
* @return nothing.
*/
extern "C"
__global__ void inputs_gradients(long *x_shape, float *x, long *y_shape, float *y)
{
int yfs = y_shape[2] * y_shape[3]; // Y feature size.
int y_index = threadIdx.x * y_shape[1] * yfs + blockIdx.x * yfs + blockIdx.y * y_shape[3] + blockIdx.z;
int xfs = x_shape[2] * x_shape[3]; // X feature size.
int x_index = threadIdx.x * x_shape[1] * xfs + blockIdx.x * xfs + blockIdx.y * x_shape[3] + blockIdx.z;
y[y_index] = x[x_index];
} | .text
.file "pad_2d.hip"
.globl __device_stub__activation # -- Begin function __device_stub__activation
.p2align 4, 0x90
.type __device_stub__activation,@function
__device_stub__activation: # @__device_stub__activation
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $activation, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__activation, .Lfunc_end0-__device_stub__activation
.cfi_endproc
# -- End function
.globl __device_stub__inputs_gradients # -- Begin function __device_stub__inputs_gradients
.p2align 4, 0x90
.type __device_stub__inputs_gradients,@function
__device_stub__inputs_gradients: # @__device_stub__inputs_gradients
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $inputs_gradients, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__inputs_gradients, .Lfunc_end1-__device_stub__inputs_gradients
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $activation, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $inputs_gradients, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type activation,@object # @activation
.section .rodata,"a",@progbits
.globl activation
.p2align 3, 0x0
activation:
.quad __device_stub__activation
.size activation, 8
.type inputs_gradients,@object # @inputs_gradients
.globl inputs_gradients
.p2align 3, 0x0
inputs_gradients:
.quad __device_stub__inputs_gradients
.size inputs_gradients, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "activation"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "inputs_gradients"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__activation
.addrsig_sym __device_stub__inputs_gradients
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym activation
.addrsig_sym inputs_gradients
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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