system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CUDAkernel_multiply( float* sourceA, float* sourceB, float* destination, int size )
{
int index = CUDASTDOFFSET;
float a = sourceA[index];
float b = sourceB[index];
if( index < size )
{
destination[index] = a * b;
}
}
|
.text
.file "CUDAkernel_multiply.hip"
.globl _Z34__device_stub__CUDAkernel_multiplyPfS_S_i # -- Begin function _Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__CUDAkernel_multiplyPfS_S_i,@function
_Z34__device_stub__CUDAkernel_multiplyPfS_S_i: # @_Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19CUDAkernel_multiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__CUDAkernel_multiplyPfS_S_i, .Lfunc_end0-_Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19CUDAkernel_multiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19CUDAkernel_multiplyPfS_S_i,@object # @_Z19CUDAkernel_multiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z19CUDAkernel_multiplyPfS_S_i
.p2align 3, 0x0
_Z19CUDAkernel_multiplyPfS_S_i:
.quad _Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.size _Z19CUDAkernel_multiplyPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19CUDAkernel_multiplyPfS_S_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19CUDAkernel_multiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z19CUDAkernel_multiplyPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0110*/ FMUL R9, R2, R5 ; /* 0x0000000502097220 */
/* 0x004fca0000400000 */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19CUDAkernel_multiplyPfS_S_i
.globl _Z19CUDAkernel_multiplyPfS_S_i
.p2align 8
.type _Z19CUDAkernel_multiplyPfS_S_i,@function
_Z19CUDAkernel_multiplyPfS_S_i:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19CUDAkernel_multiplyPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19CUDAkernel_multiplyPfS_S_i, .Lfunc_end0-_Z19CUDAkernel_multiplyPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19CUDAkernel_multiplyPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19CUDAkernel_multiplyPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00080c3c_00000000-6_CUDAkernel_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19CUDAkernel_multiplyPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19CUDAkernel_multiplyPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19CUDAkernel_multiplyPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19CUDAkernel_multiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z19CUDAkernel_multiplyPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19CUDAkernel_multiplyPfS_S_iPfS_S_i
.globl _Z19CUDAkernel_multiplyPfS_S_i
.type _Z19CUDAkernel_multiplyPfS_S_i, @function
_Z19CUDAkernel_multiplyPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19CUDAkernel_multiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19CUDAkernel_multiplyPfS_S_i, .-_Z19CUDAkernel_multiplyPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19CUDAkernel_multiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19CUDAkernel_multiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "CUDAkernel_multiply.hip"
.globl _Z34__device_stub__CUDAkernel_multiplyPfS_S_i # -- Begin function _Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__CUDAkernel_multiplyPfS_S_i,@function
_Z34__device_stub__CUDAkernel_multiplyPfS_S_i: # @_Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19CUDAkernel_multiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__CUDAkernel_multiplyPfS_S_i, .Lfunc_end0-_Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19CUDAkernel_multiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19CUDAkernel_multiplyPfS_S_i,@object # @_Z19CUDAkernel_multiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z19CUDAkernel_multiplyPfS_S_i
.p2align 3, 0x0
_Z19CUDAkernel_multiplyPfS_S_i:
.quad _Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.size _Z19CUDAkernel_multiplyPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19CUDAkernel_multiplyPfS_S_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__CUDAkernel_multiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19CUDAkernel_multiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
cudaError_t error = call; \
if(error != cudaSuccess){ \
printf("ERROR: %s:%d\n", __FILE__, __LINE__); \
printf("error_num: %d reason:%s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return ( (double)tp.tv_sec + (double)tp.tv_usec * 1e-6 );
}
__global__ void helloFromGPU(void){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
printf("Hello from GPU! %d\n", idx);
}
int main(void){
int nElem = 6;
dim3 block(6);
dim3 grid( (nElem + block.x -1) / block.x );
double iStart, iElapse;
iStart = cpuSecond();
helloFromGPU<<< grid, block >>>();
CHECK(cudaDeviceSynchronize());
iElapse = cpuSecond() - iStart;
printf("Elapsed time: %5.6f sec\n", iElapse);
return 0;
}
|
code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fe400078e0200 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
cudaError_t error = call; \
if(error != cudaSuccess){ \
printf("ERROR: %s:%d\n", __FILE__, __LINE__); \
printf("error_num: %d reason:%s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return ( (double)tp.tv_sec + (double)tp.tv_usec * 1e-6 );
}
__global__ void helloFromGPU(void){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
printf("Hello from GPU! %d\n", idx);
}
int main(void){
int nElem = 6;
dim3 block(6);
dim3 grid( (nElem + block.x -1) / block.x );
double iStart, iElapse;
iStart = cpuSecond();
helloFromGPU<<< grid, block >>>();
CHECK(cudaDeviceSynchronize());
iElapse = cpuSecond() - iStart;
printf("Elapsed time: %5.6f sec\n", iElapse);
return 0;
}
|
.file "tmpxft_00037140_00000000-6_timing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dkambam/procuda/master/ch2/timing/cpu-timer/timing.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "ERROR: %s:%d\n"
.LC3:
.string "error_num: %d reason:%s\n"
.LC4:
.string "Elapsed time: %5.6f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl $6, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L20
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L16
.L20:
movl $35, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
cudaError_t error = call; \
if(error != cudaSuccess){ \
printf("ERROR: %s:%d\n", __FILE__, __LINE__); \
printf("error_num: %d reason:%s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return ( (double)tp.tv_sec + (double)tp.tv_usec * 1e-6 );
}
__global__ void helloFromGPU(void){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
printf("Hello from GPU! %d\n", idx);
}
int main(void){
int nElem = 6;
dim3 block(6);
dim3 grid( (nElem + block.x -1) / block.x );
double iStart, iElapse;
iStart = cpuSecond();
helloFromGPU<<< grid, block >>>();
CHECK(cudaDeviceSynchronize());
iElapse = cpuSecond() - iStart;
printf("Elapsed time: %5.6f sec\n", iElapse);
return 0;
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
hipError_t error = call; \
if(error != hipSuccess){ \
printf("ERROR: %s:%d\n", __FILE__, __LINE__); \
printf("error_num: %d reason:%s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return ( (double)tp.tv_sec + (double)tp.tv_usec * 1e-6 );
}
__global__ void helloFromGPU(void){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
printf("Hello from GPU! %d\n", idx);
}
int main(void){
int nElem = 6;
dim3 block(6);
dim3 grid( (nElem + block.x -1) / block.x );
double iStart, iElapse;
iStart = cpuSecond();
helloFromGPU<<< grid, block >>>();
CHECK(hipDeviceSynchronize());
iElapse = cpuSecond() - iStart;
printf("Elapsed time: %5.6f sec\n", iElapse);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define CHECK(call) \
{ \
hipError_t error = call; \
if(error != hipSuccess){ \
printf("ERROR: %s:%d\n", __FILE__, __LINE__); \
printf("error_num: %d reason:%s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return ( (double)tp.tv_sec + (double)tp.tv_usec * 1e-6 );
}
__global__ void helloFromGPU(void){
int idx = threadIdx.x + blockIdx.x * blockDim.x;
printf("Hello from GPU! %d\n", idx);
}
int main(void){
int nElem = 6;
dim3 block(6);
dim3 grid( (nElem + block.x -1) / block.x );
double iStart, iElapse;
iStart = cpuSecond();
helloFromGPU<<< grid, block >>>();
CHECK(hipDeviceSynchronize());
iElapse = cpuSecond() - iStart;
printf("Elapsed time: %5.6f sec\n", iElapse);
return 0;
}
|
.text
.file "timing.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end1-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rbx
movq 16(%rsp), %r14
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 5(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_4
# %bb.3:
cvtsi2sd %r14, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
cvtsi2sd %rbx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 96
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $35, %edx
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: %s:%d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dkambam/procuda/master/ch2/timing/cpu-timer/timing.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error_num: %d reason:%s\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Elapsed time: %5.6f sec\n"
.size .L.str.3, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00037140_00000000-6_timing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dkambam/procuda/master/ch2/timing/cpu-timer/timing.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "ERROR: %s:%d\n"
.LC3:
.string "error_num: %d reason:%s\n"
.LC4:
.string "Elapsed time: %5.6f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl $6, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L20
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L16
.L20:
movl $35, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "timing.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end1-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $72, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rbx
movq 16(%rsp), %r14
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 5(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_4
# %bb.3:
cvtsi2sd %r14, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
cvtsi2sd %rbx, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 96
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $35, %edx
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: %s:%d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dkambam/procuda/master/ch2/timing/cpu-timer/timing.hip"
.size .L.str.1, 112
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "error_num: %d reason:%s\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Elapsed time: %5.6f sec\n"
.size .L.str.3, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda.h"
#include "stdio.h"
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
void print_CPU_matrix(int array[], int n){
for(int i = 0; i < n; i++) {
if(i % 16 == 0)
printf("%s\n", "");
printf("%d ", array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[10];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < N; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < (N/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
compartida[threadIdx.x * acceso + offset] = 0;
printf("%s\n", "TRABAJO");
result[blockIdx.x] = compartida[0];
}
printf("%s\n", "");
}
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 8;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
cudaMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), cudaMemcpyHostToDevice);
int threads_per_block = 10;
int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miGrid1D_1(block_count,1);
dim3 miBloque1D_1(threads_per_block,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, N);
//###################################################################################
//################################### READ BACK #####################################
cudaMemcpy(arreglo_result, d_arreglo_suma2, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_matrix(arreglo_result, N);
free(arreglo_suma1);
cudaFree (d_arreglo_suma1);
free(arreglo_result);
cudaFree (d_arreglo_suma2);
}
|
code for sm_80
Function : _Z7sumadorPiS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0070*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x001fcc000f8e023f */
/*0080*/ IADD3 R2, R19, UR4, RZ ; /* 0x0000000413027c10 */
/* 0x002fca000fffe0ff */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ LDG.E R4, [R2.64] ; /* 0x0000002402047981 */
/* 0x0000a2000c1e1900 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x34000000 ; /* 0x34000000ff067424 */
/* 0x000fe200078e00ff */
/*00d0*/ R2UR UR43, R1 ; /* 0x00000000012b73c2 */
/* 0x000e6200000e0000 */
/*00e0*/ FFMA R0, RZ, -RZ, RZ ; /* 0x800000ffff007223 */
/* 0x000fe200000000ff */
/*00f0*/ I2F.U32 R18, R19 ; /* 0x0000001300127306 */
/* 0x000fe20000201000 */
/*0100*/ FFMA R6, R6, 8388608, RZ ; /* 0x4b00000006067823 */
/* 0x000fe200000000ff */
/*0110*/ ULDC UR40, c[0x0][0x20] ; /* 0x0000080000287ab9 */
/* 0x000fe20000000800 */
/*0120*/ FMUL R0, R0, 0.5 ; /* 0x3f00000000007820 */
/* 0x000fe20000400000 */
/*0130*/ ULDC UR41, c[0x0][0x24] ; /* 0x0000090000297ab9 */
/* 0x000fe20000000800 */
/*0140*/ FFMA R7, RZ, 1.4426950216293334961, R6 ; /* 0x3fb8aa3bff077823 */
/* 0x000fe20000000006 */
/*0150*/ ULDC.64 UR38, c[0x0][0x168] ; /* 0x00005a0000267ab9 */
/* 0x000fe20000000a00 */
/*0160*/ FFMA R5, RZ, R5, 0.0032181653659790754318 ; /* 0x3b52e7dbff057423 */
/* 0x000fc40000000005 */
/*0170*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x000fe40000000000 */
/*0180*/ FFMA R5, RZ, R5, 0.018033718690276145935 ; /* 0x3c93bb73ff057423 */
/* 0x000fe40000000005 */
/*0190*/ FFMA R3, RZ, 1.4426950216293334961, R6 ; /* 0x3fb8aa3bff037823 */
/* 0x001fe40000000006 */
/*01a0*/ FFMA R5, RZ, R5, 0.12022458761930465698 ; /* 0x3df6384fff057423 */
/* 0x000fe40000000005 */
/*01b0*/ FFMA R3, R0, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b00037823 */
/* 0x000fe40000000003 */
/*01c0*/ FMUL R5, RZ, R5 ; /* 0x00000005ff057220 */
/* 0x000fc40000400000 */
/*01d0*/ FFMA R3, RZ, 1.9251366722983220825e-08, R3 ; /* 0x32a55e34ff037823 */
/* 0x000fe20000000003 */
/*01e0*/ UIADD3 UR40, UP0, UR43, UR40, URZ ; /* 0x000000282b287290 */
/* 0x002fe2000ff1e03f */
/*01f0*/ FMUL R2, R5, 3 ; /* 0x4040000005027820 */
/* 0x000fe40000400000 */
/*0200*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0210*/ UIADD3.X UR41, URZ, UR41, URZ, UP0, !UPT ; /* 0x000000293f297290 */
/* 0x000fe200087fe43f */
/*0220*/ FFMA R2, R0, R2, R3 ; /* 0x0000000200027223 */
/* 0x000fe40000000003 */
/*0230*/ I2F.U32 R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008201000 */
/*0240*/ UMOV UR4, 0x4 ; /* 0x0000000400047882 */
/* 0x000fe20000000000 */
/*0250*/ FFMA R6, RZ, R5, R2 ; /* 0x00000005ff067223 */
/* 0x000fe20000000002 */
/*0260*/ UIMAD.WIDE.U32 UR38, UR5, UR4, UR38 ; /* 0x00000004052672a5 */
/* 0x000fc6000f8e0026 */
/*0270*/ FADD R2, R7, R6 ; /* 0x0000000607027221 */
/* 0x000fc80000000000 */
/*0280*/ R2UR UR42, R2 ; /* 0x00000000022a73c2 */
/* 0x000e6200000e0000 */
/*0290*/ FADD R22, -R0, c[0x0][0x170] ; /* 0x00005c0000167621 */
/* 0x001fe40000000100 */
/*02a0*/ FADD R17, -R7, UR42 ; /* 0x0000002a07117e21 */
/* 0x002fc80008000100 */
/*02b0*/ FADD R17, R6, -R17 ; /* 0x8000001106117221 */
/* 0x000fe20000000000 */
/*02c0*/ STS [R19.X4], R4 ; /* 0x0000000413007388 */
/* 0x0041e80000004800 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ I2F R0, R16 ; /* 0x0000001000007306 */
/* 0x000e620000201400 */
/*02f0*/ BSSY B0, 0x4e0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff027424 */
/* 0x000fe400078e00ff */
/*0310*/ FADD R9, R0, -1 ; /* 0xbf80000000097421 */
/* 0x002fca0000000000 */
/*0320*/ FSETP.NEU.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fda0003f0d000 */
/*0330*/ @!P0 BRA 0x4d0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0340*/ FMUL R2, R9.reuse, UR42 ; /* 0x0000002a09027c20 */
/* 0x040fe20008400000 */
/*0350*/ FSETP.GTU.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe20003f4c200 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff077424 */
/* 0x000fe400078e00ff */
/*0370*/ FRND R3, R2 ; /* 0x0000000200037307 */
/* 0x000e620000201000 */
/*0380*/ FFMA R4, R9, UR42, -R2 ; /* 0x0000002a09047c23 */
/* 0x001fe20008000802 */
/*0390*/ FSETP.GT.AND P0, PT, |R2|, 152, PT ; /* 0x431800000200780b */
/* 0x000fc60003f04200 */
/*03a0*/ FFMA R5, R17, R9, R4 ; /* 0x0000000911057223 */
/* 0x000fc60000000004 */
/*03b0*/ F2I.NTZ R6, R2 ; /* 0x0000000200067305 */
/* 0x000e220000203100 */
/*03c0*/ FADD R4, R2, -R3 ; /* 0x8000000302047221 */
/* 0x002fe20000000000 */
/*03d0*/ FSETP.GT.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fc60003f24000 */
/*03e0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fe20000000000 */
/*03f0*/ SEL R3, RZ, 0x83000000, P1 ; /* 0x83000000ff037807 */
/* 0x000fe40000800000 */
/*0400*/ FSETP.GEU.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fe20003f2e000 */
/*0410*/ FFMA R5, R4, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed04057423 */
/* 0x000fe20000000007 */
/*0420*/ LEA R6, R6, -R3, 0x17 ; /* 0x8000000306067211 */
/* 0x001fe400078eb8ff */
/*0430*/ FSEL R2, RZ, +INF , !P1 ; /* 0x7f800000ff027808 */
/* 0x000fe20004800000 */
/*0440*/ FFMA R5, R4, R5, 0.0096188392490148544312 ; /* 0x3c1d985604057423 */
/* 0x000fc80000000005 */
/*0450*/ FFMA R5, R4, R5, 0.055503588169813156128 ; /* 0x3d6357bb04057423 */
/* 0x000fc80000000005 */
/*0460*/ FFMA R5, R4, R5, 0.24022644758224487305 ; /* 0x3e75fdec04057423 */
/* 0x000fc80000000005 */
/*0470*/ FFMA R7, R4, R5, 0.69314718246459960938 ; /* 0x3f31721804077423 */
/* 0x000fe20000000005 */
/*0480*/ IADD3 R5, R3, 0x7f000000, RZ ; /* 0x7f00000003057810 */
/* 0x000fc60007ffe0ff */
/*0490*/ FFMA R4, R4, R7, 1 ; /* 0x3f80000004047423 */
/* 0x000fc80000000007 */
/*04a0*/ FMUL R5, R5, R4 ; /* 0x0000000405057220 */
/* 0x000fc80000400000 */
/*04b0*/ @!P0 FMUL R2, R6, R5 ; /* 0x0000000506028220 */
/* 0x000fe40000400000 */
/*04c0*/ @P2 FADD R2, R9, 2 ; /* 0x4000000009022421 */
/* 0x000fe40000000000 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0b */
/* 0x000fda0003f0e000 */
/*04f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0500*/ FMUL R3, R0.reuse, UR42 ; /* 0x0000002a00037c20 */
/* 0x040fe20008400000 */
/*0510*/ FSETP.GTU.AND P2, PT, |R0|.reuse, +INF , PT ; /* 0x7f8000000000780b */
/* 0x040fe20003f4c200 */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff077424 */
/* 0x000fe200078e00ff */
/*0530*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0540*/ FRND R6, R3 ; /* 0x0000000300067307 */
/* 0x000e620000201000 */
/*0550*/ FFMA R4, R0, UR42, -R3 ; /* 0x0000002a00047c23 */
/* 0x001fe20008000803 */
/*0560*/ FSETP.GEU.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f2e000 */
/*0570*/ BSSY B0, 0x790 ; /* 0x0000021000007945 */
/* 0x000fe40003800000 */
/*0580*/ FFMA R4, R17, R0, R4 ; /* 0x0000000011047223 */
/* 0x000fe40000000004 */
/*0590*/ FADD R5, R3, -R6 ; /* 0x8000000603057221 */
/* 0x002fe20000000000 */
/*05a0*/ FSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fc60003f04000 */
/*05b0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x000fe20000000000 */
/*05c0*/ SEL R6, RZ, 0x83000000, P0 ; /* 0x83000000ff067807 */
/* 0x000fe40000000000 */
/*05d0*/ FSETP.GT.AND P0, PT, |R3|, 152, PT ; /* 0x431800000300780b */
/* 0x000fe20003f04200 */
/*05e0*/ FFMA R5, R4, R7, 0.0013391353422775864601 ; /* 0x3aaf85ed04057423 */
/* 0x000fe20000000007 */
/*05f0*/ IADD3 R8, R6, 0x7f000000, RZ ; /* 0x7f00000006087810 */
/* 0x000fe20007ffe0ff */
/*0600*/ F2I.NTZ R7, R3 ; /* 0x0000000300077305 */
/* 0x000e240000203100 */
/*0610*/ FFMA R5, R4, R5, 0.0096188392490148544312 ; /* 0x3c1d985604057423 */
/* 0x000fc80000000005 */
/*0620*/ FFMA R5, R4, R5, 0.055503588169813156128 ; /* 0x3d6357bb04057423 */
/* 0x000fc80000000005 */
/*0630*/ FFMA R5, R4, R5, 0.24022644758224487305 ; /* 0x3e75fdec04057423 */
/* 0x000fc80000000005 */
/*0640*/ FFMA R5, R4.reuse, R5, 0.69314718246459960938 ; /* 0x3f31721804057423 */
/* 0x040fe40000000005 */
/*0650*/ IMAD R6, R7, 0x800000, -R6 ; /* 0x0080000007067824 */
/* 0x001fe400078e0a06 */
/*0660*/ FFMA R5, R4, R5, 1 ; /* 0x3f80000004057423 */
/* 0x000fc80000000005 */
/*0670*/ FMUL R5, R5, R8 ; /* 0x0000000805057220 */
/* 0x000fe40000400000 */
/*0680*/ IMAD.U32 R8, RZ, RZ, UR4 ; /* 0x00000004ff087e24 */
/* 0x000fe4000f8e00ff */
/*0690*/ FMUL R5, R5, R6 ; /* 0x0000000605057220 */
/* 0x000fe20000400000 */
/*06a0*/ @P0 FSEL R5, RZ, +INF , !P1 ; /* 0x7f800000ff050808 */
/* 0x000fe20004800000 */
/*06b0*/ @P2 FADD R5, R0, 2 ; /* 0x4000000000052421 */
/* 0x000fc80000000000 */
/*06c0*/ F2I.TRUNC.NTZ R0, R5 ; /* 0x0000000500007305 */
/* 0x000e30000020f100 */
/*06d0*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x001e300000201400 */
/*06e0*/ MUFU.RCP R3, R9 ; /* 0x0000000900037308 */
/* 0x001e300000001000 */
/*06f0*/ FCHK P0, R8, R9 ; /* 0x0000000908007302 */
/* 0x000e620000000000 */
/*0700*/ FFMA R4, -R9, R3, 1 ; /* 0x3f80000009047423 */
/* 0x001fc80000000103 */
/*0710*/ FFMA R4, R3, R4, R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000003 */
/*0720*/ FFMA R3, R4, c[0x0][0x170], RZ ; /* 0x00005c0004037a23 */
/* 0x000fc800000000ff */
/*0730*/ FFMA R6, -R9, R3, c[0x0][0x170] ; /* 0x00005c0009067623 */
/* 0x000fc80000000103 */
/*0740*/ FFMA R3, R4, R6, R3 ; /* 0x0000000604037223 */
/* 0x000fe20000000003 */
/*0750*/ @!P0 BRA 0x780 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0760*/ MOV R4, 0x780 ; /* 0x0000078000047802 */
/* 0x000fe40000000f00 */
/*0770*/ CALL.REL.NOINC 0xb20 ; /* 0x000003a000007944 */
/* 0x000fea0003c00000 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ FSETP.GT.AND P0, PT, R3, R18, PT ; /* 0x000000120300720b */
/* 0x001fe20003f04000 */
/*07a0*/ BSSY B6, 0x9f0 ; /* 0x0000024000067945 */
/* 0x000fd80003800000 */
/*07b0*/ @!P0 BRA 0x9e0 ; /* 0x0000022000008947 */
/* 0x000fea0003800000 */
/*07c0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e22000020f100 */
/*07d0*/ IMAD R9, R0, R19, RZ ; /* 0x0000001300097224 */
/* 0x000fca00078e02ff */
/*07e0*/ IADD3 R0, R2, R9, RZ ; /* 0x0000000902007210 */
/* 0x001fc80007ffe0ff */
/*07f0*/ I2F.U32 R3, R0 ; /* 0x0000000000037306 */
/* 0x000e240000201000 */
/*0800*/ FSETP.GT.AND P0, PT, R22, R3, PT ; /* 0x000000031600720b */
/* 0x001fda0003f04000 */
/*0810*/ @!P0 BRA 0x9e0 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.SHL.U32 R0, R9, 0x4, RZ ; /* 0x0000000409007824 */
/* 0x000fe200078e00ff */
/*0830*/ LDS R3, [R9.X4] ; /* 0x0000000009037984 */
/* 0x000fe20000004800 */
/*0840*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff0a7624 */
/* 0x000fe200078e00ff */
/*0850*/ MOV R11, c[0x4][0x14] ; /* 0x01000500000b7a02 */
/* 0x000fe20000000f00 */
/*0860*/ IMAD R0, R2, 0x4, R0 ; /* 0x0000000402007824 */
/* 0x000fe200078e0200 */
/*0870*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0890*/ MOV R6, UR40 ; /* 0x0000002800067c02 */
/* 0x000fe20008000f00 */
/*08a0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x000fe20000100a00 */
/*08b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*08c0*/ IMAD.U32 R7, RZ, RZ, UR41 ; /* 0x00000029ff077e24 */
/* 0x000fe2000f8e00ff */
/*08d0*/ LDS R8, [R0] ; /* 0x0000000000087984 */
/* 0x000e240000000800 */
/*08e0*/ IMAD.IADD R8, R8, 0x1, R3 ; /* 0x0000000108087824 */
/* 0x001fc400078e0203 */
/*08f0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*0900*/ STS [R9.X4], R8 ; /* 0x0000000809007388 */
/* 0x0003e80000004800 */
/*0910*/ STS [R0], RZ ; /* 0x000000ff00007388 */
/* 0x0003e40000000800 */
/*0920*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe20000000000 */
/*0930*/ MOV R11, 0x9a0 ; /* 0x000009a0000b7802 */
/* 0x000fe40000000f00 */
/*0940*/ MOV R20, 0x920 ; /* 0x0000092000147802 */
/* 0x000fc40000000f00 */
/*0950*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0960*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0970*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0980*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0990*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*09a0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*09b0*/ IMAD.U32 R2, RZ, RZ, UR38 ; /* 0x00000026ff027e24 */
/* 0x000fe2000f8e00ff */
/*09c0*/ MOV R3, UR39 ; /* 0x0000002700037c02 */
/* 0x000fca0008000f00 */
/*09d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0011e4000c101924 */
/*09e0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*09f0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x001fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff087624 */
/* 0x000fe200078e00ff */
/*0a10*/ MOV R4, c[0x4][0x8] ; /* 0x0100020000047a02 */
/* 0x000fe20000000f00 */
/*0a20*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff097624 */
/* 0x000fe200078e00ff */
/*0a30*/ MOV R7, UR41 ; /* 0x0000002900077c02 */
/* 0x000fe20008000f00 */
/*0a40*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0a50*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*0a60*/ IMAD.U32 R6, RZ, RZ, UR40 ; /* 0x00000028ff067e24 */
/* 0x000fe2000f8e00ff */
/*0a70*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003ec0000100a00 */
/*0a80*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe20000000000 */
/*0a90*/ MOV R11, 0xb00 ; /* 0x00000b00000b7802 */
/* 0x000fe40000000f00 */
/*0aa0*/ MOV R20, 0xa80 ; /* 0x00000a8000147802 */
/* 0x000fc40000000f00 */
/*0ab0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0ac0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0ad0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0ae0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0af0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0b00*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ BRA 0x2e0 ; /* 0xfffff7c000007947 */
/* 0x000fea000383ffff */
/*0b20*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0b7624 */
/* 0x000fe200078e00ff */
/*0b30*/ SHF.R.U32.HI R6, RZ, 0x17, R9 ; /* 0x00000017ff067819 */
/* 0x000fe20000011609 */
/*0b40*/ BSSY B1, 0x1190 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0b50*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fe400078e00ff */
/*0b60*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe400078ec0ff */
/*0b70*/ SHF.R.U32.HI R3, RZ, 0x17, R11 ; /* 0x00000017ff037819 */
/* 0x000fe4000001160b */
/*0b80*/ IADD3 R12, R6, -0x1, RZ ; /* 0xffffffff060c7810 */
/* 0x000fc40007ffe0ff */
/*0b90*/ LOP3.LUT R7, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03077812 */
/* 0x000fe400078ec0ff */
/*0ba0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fe40003f04070 */
/*0bb0*/ IADD3 R10, R7, -0x1, RZ ; /* 0xffffffff070a7810 */
/* 0x000fc80007ffe0ff */
/*0bc0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0bd0*/ @!P0 MOV R5, RZ ; /* 0x000000ff00058202 */
/* 0x000fe20000000f00 */
/*0be0*/ @!P0 BRA 0xd70 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe20003f1c200 */
/*0c00*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0c10*/ FSETP.GTU.FTZ.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f3c200 */
/*0c20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0c30*/ @P0 BRA 0x1170 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0c50*/ @!P0 BRA 0x1150 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0c60*/ FSETP.NEU.FTZ.AND P2, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f5d200 */
/*0c70*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0c80*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*0c90*/ @!P1 BRA !P2, 0x1150 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0ca0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*0cb0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0cc0*/ @P1 BRA 0x1130 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0cd0*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0ce0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0cf0*/ @P0 BRA 0x1100 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0d00*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0d10*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0d20*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe200078e00ff */
/*0d30*/ @!P0 MOV R5, 0xffffffc0 ; /* 0xffffffc000058802 */
/* 0x000fe20000000f00 */
/*0d40*/ @!P0 FFMA R8, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b088823 */
/* 0x000fe400000000ff */
/*0d50*/ @!P1 FFMA R9, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003099823 */
/* 0x000fe200000000ff */
/*0d60*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ LEA R10, R6, 0xc0800000, 0x17 ; /* 0xc0800000060a7811 */
/* 0x000fe200078eb8ff */
/*0d80*/ BSSY B2, 0x10f0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0d90*/ IADD3 R7, R7, -0x7f, RZ ; /* 0xffffff8107077810 */
/* 0x000fc60007ffe0ff */
/*0da0*/ IMAD.IADD R10, R9, 0x1, -R10 ; /* 0x00000001090a7824 */
/* 0x000fe400078e0a0a */
/*0db0*/ IMAD R8, R7, -0x800000, R8 ; /* 0xff80000007087824 */
/* 0x000fe400078e0208 */
/*0dc0*/ MUFU.RCP R3, R10 ; /* 0x0000000a00037308 */
/* 0x000e220000001000 */
/*0dd0*/ FADD.FTZ R9, -R10, -RZ ; /* 0x800000ff0a097221 */
/* 0x000fc80000010100 */
/*0de0*/ FFMA R12, R3, R9, 1 ; /* 0x3f800000030c7423 */
/* 0x001fc80000000009 */
/*0df0*/ FFMA R11, R3, R12, R3 ; /* 0x0000000c030b7223 */
/* 0x000fc80000000003 */
/*0e00*/ FFMA R3, R8, R11, RZ ; /* 0x0000000b08037223 */
/* 0x000fc800000000ff */
/*0e10*/ FFMA R12, R9, R3, R8 ; /* 0x00000003090c7223 */
/* 0x000fc80000000008 */
/*0e20*/ FFMA R12, R11, R12, R3 ; /* 0x0000000c0b0c7223 */
/* 0x000fc80000000003 */
/*0e30*/ FFMA R9, R9, R12, R8 ; /* 0x0000000c09097223 */
/* 0x000fe20000000008 */
/*0e40*/ IADD3 R8, R7, 0x7f, -R6 ; /* 0x0000007f07087810 */
/* 0x000fc60007ffe806 */
/*0e50*/ FFMA R3, R11, R9, R12 ; /* 0x000000090b037223 */
/* 0x000fe4000000000c */
/*0e60*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fc600078e0205 */
/*0e70*/ SHF.R.U32.HI R6, RZ, 0x17, R3 ; /* 0x00000017ff067819 */
/* 0x000fc80000011603 */
/*0e80*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fc800078ec0ff */
/*0e90*/ IADD3 R10, R6, R8, RZ ; /* 0x00000008060a7210 */
/* 0x000fc80007ffe0ff */
/*0ea0*/ IADD3 R5, R10, -0x1, RZ ; /* 0xffffffff0a057810 */
/* 0x000fc80007ffe0ff */
/*0eb0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0ec0*/ @!P0 BRA 0x10d0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0ed0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0ee0*/ @P0 BRA 0x10a0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0ef0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0f00*/ @P0 BRA 0x10e0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0f10*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0f20*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0f30*/ @!P0 BRA 0x10e0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0f40*/ FFMA.RZ R5, R11.reuse, R9.reuse, R12.reuse ; /* 0x000000090b057223 */
/* 0x1c0fe2000000c00c */
/*0f50*/ IADD3 R8, R10.reuse, 0x20, RZ ; /* 0x000000200a087810 */
/* 0x040fe20007ffe0ff */
/*0f60*/ FFMA.RM R6, R11, R9.reuse, R12.reuse ; /* 0x000000090b067223 */
/* 0x180fe2000000400c */
/*0f70*/ ISETP.NE.AND P2, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x040fe40003f45270 */
/*0f80*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0f90*/ FFMA.RP R5, R11, R9, R12 ; /* 0x000000090b057223 */
/* 0x000fe2000000800c */
/*0fa0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25270 */
/*0fb0*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a0a */
/*0fc0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0fd0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0fe0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0ff0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*1000*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*1010*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*1020*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*1030*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*1040*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*1050*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*1060*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*1070*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x000fca00078e0205 */
/*1080*/ LOP3.LUT R3, R8, R3, RZ, 0xfc, !PT ; /* 0x0000000308037212 */
/* 0x000fe200078efcff */
/*1090*/ BRA 0x10e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*10a0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*10b0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*10c0*/ BRA 0x10e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*10d0*/ LEA R3, R8, R3, 0x17 ; /* 0x0000000308037211 */
/* 0x000fe400078eb8ff */
/*10e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*10f0*/ BRA 0x1180 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1100*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fc800078e4808 */
/*1110*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*1120*/ BRA 0x1180 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1130*/ LOP3.LUT R3, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009037812 */
/* 0x000fe200078e4808 */
/*1140*/ BRA 0x1180 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1150*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*1160*/ BRA 0x1180 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1170*/ FADD.FTZ R3, R3, c[0x0][0x170] ; /* 0x00005c0003037621 */
/* 0x000fe40000010000 */
/*1180*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1190*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*11a0*/ RET.REL.NODEC R4 0x0 ; /* 0xffffee5004007950 */
/* 0x000fea0003c3ffff */
/*11b0*/ BRA 0x11b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda.h"
#include "stdio.h"
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
void print_CPU_matrix(int array[], int n){
for(int i = 0; i < n; i++) {
if(i % 16 == 0)
printf("%s\n", "");
printf("%d ", array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[10];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < N; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < (N/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
compartida[threadIdx.x * acceso + offset] = 0;
printf("%s\n", "TRABAJO");
result[blockIdx.x] = compartida[0];
}
printf("%s\n", "");
}
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 8;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
cudaMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), cudaMemcpyHostToDevice);
int threads_per_block = 10;
int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miGrid1D_1(block_count,1);
dim3 miBloque1D_1(threads_per_block,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, N);
//###################################################################################
//################################### READ BACK #####################################
cudaMemcpy(arreglo_result, d_arreglo_suma2, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_matrix(arreglo_result, N);
free(arreglo_suma1);
cudaFree (d_arreglo_suma1);
free(arreglo_result);
cudaFree (d_arreglo_suma2);
}
|
.file "tmpxft_000688c6_00000000-6_sum_test_shared_single_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z6printii
.type _Z6printii, @function
_Z6printii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6printii, .-_Z6printii
.globl _Z14init_CPU_arrayPii
.type _Z14init_CPU_arrayPii, @function
_Z14init_CPU_arrayPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L5
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L7:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z14init_CPU_arrayPii, .-_Z14init_CPU_arrayPii
.globl _Z15print_CPU_arrayPii
.type _Z15print_CPU_arrayPii, @function
_Z15print_CPU_arrayPii:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L11:
movl (%rbx), %edi
call _Z6printii
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z15print_CPU_arrayPii, .-_Z15print_CPU_arrayPii
.section .rodata.str1.1
.LC1:
.string ""
.LC2:
.string "%s\n"
.LC3:
.string "%d "
.text
.globl _Z16print_CPU_matrixPii
.type _Z16print_CPU_matrixPii, @function
_Z16print_CPU_matrixPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L23
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
jmp .L20
.L19:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
je .L26
.L20:
testb $15, %bl
jne .L19
movq %r15, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L26:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z16print_CPU_matrixPii, .-_Z16print_CPU_matrixPii
.globl _Z29__device_stub__Z7sumadorPiS_fPiS_f
.type _Z29__device_stub__Z7sumadorPiS_fPiS_f, @function
_Z29__device_stub__Z7sumadorPiS_fPiS_f:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sumadorPiS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z7sumadorPiS_fPiS_f, .-_Z29__device_stub__Z7sumadorPiS_fPiS_f
.globl _Z7sumadorPiS_f
.type _Z7sumadorPiS_f, @function
_Z7sumadorPiS_f:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7sumadorPiS_f, .-_Z7sumadorPiS_f
.section .rodata.str1.1
.LC5:
.string "RESULTADO DE LA SUMA:"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, %edi
call malloc@PLT
movq %rax, arreglo_suma1(%rip)
movl $32, %esi
leaq d_arreglo_suma1(%rip), %rdi
call cudaMalloc@PLT
movl $32, %edi
call malloc@PLT
movq %rax, arreglo_result(%rip)
movl $32, %esi
leaq d_arreglo_suma2(%rip), %rdi
call cudaMalloc@PLT
movl $8, %esi
movq arreglo_suma1(%rip), %rdi
call _Z14init_CPU_arrayPii
movl $1, %ecx
movl $32, %edx
movq arreglo_suma1(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call cudaMemcpy@PLT
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L36:
movl $2, %ecx
movl $32, %edx
movq d_arreglo_suma2(%rip), %rsi
movq arreglo_result(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %esi
movq arreglo_result(%rip), %rdi
call _Z16print_CPU_matrixPii
movq arreglo_suma1(%rip), %rdi
call free@PLT
movq d_arreglo_suma1(%rip), %rdi
call cudaFree@PLT
movq arreglo_result(%rip), %rdi
call free@PLT
movq d_arreglo_suma2(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movss .LC4(%rip), %xmm0
movq d_arreglo_suma2(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
jmp .L36
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7sumadorPiS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sumadorPiS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_arreglo_suma2
.bss
.align 8
.type d_arreglo_suma2, @object
.size d_arreglo_suma2, 8
d_arreglo_suma2:
.zero 8
.globl arreglo_result
.align 8
.type arreglo_result, @object
.size arreglo_result, 8
arreglo_result:
.zero 8
.globl d_arreglo_suma1
.align 8
.type d_arreglo_suma1, @object
.size d_arreglo_suma1, 8
d_arreglo_suma1:
.zero 8
.globl arreglo_suma1
.align 8
.type arreglo_suma1, @object
.size arreglo_suma1, 8
arreglo_suma1:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1090519040
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda.h"
#include "stdio.h"
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
void print_CPU_matrix(int array[], int n){
for(int i = 0; i < n; i++) {
if(i % 16 == 0)
printf("%s\n", "");
printf("%d ", array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[10];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < N; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < (N/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
compartida[threadIdx.x * acceso + offset] = 0;
printf("%s\n", "TRABAJO");
result[blockIdx.x] = compartida[0];
}
printf("%s\n", "");
}
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 8;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
cudaMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
cudaMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), cudaMemcpyHostToDevice);
int threads_per_block = 10;
int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miGrid1D_1(block_count,1);
dim3 miBloque1D_1(threads_per_block,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, N);
//###################################################################################
//################################### READ BACK #####################################
cudaMemcpy(arreglo_result, d_arreglo_suma2, N * sizeof(int), cudaMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_matrix(arreglo_result, N);
free(arreglo_suma1);
cudaFree (d_arreglo_suma1);
free(arreglo_result);
cudaFree (d_arreglo_suma2);
}
|
#include "hip/hip_runtime.h"
#include "stdio.h"
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
void print_CPU_matrix(int array[], int n){
for(int i = 0; i < n; i++) {
if(i % 16 == 0)
printf("%s\n", "");
printf("%d ", array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[10];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < N; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < (N/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
compartida[threadIdx.x * acceso + offset] = 0;
printf("%s\n", "TRABAJO");
result[blockIdx.x] = compartida[0];
}
printf("%s\n", "");
}
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 8;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
hipMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), hipMemcpyHostToDevice);
int threads_per_block = 10;
int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miGrid1D_1(block_count,1);
dim3 miBloque1D_1(threads_per_block,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, N);
//###################################################################################
//################################### READ BACK #####################################
hipMemcpy(arreglo_result, d_arreglo_suma2, N * sizeof(int), hipMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_matrix(arreglo_result, N);
free(arreglo_suma1);
hipFree (d_arreglo_suma1);
free(arreglo_result);
hipFree (d_arreglo_suma2);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include "stdio.h"
void printi(int i){
printf("%d\n", i);
}
void init_CPU_array(int* array, int n){
for(int i = 0; i < n; i++) {
array[i] = 1;
}
}
void print_CPU_array(int array[], int n){
for(int i = 0; i < n; i++) {
printi(array[i]);
}
}
void print_CPU_matrix(int array[], int n){
for(int i = 0; i < n; i++) {
if(i % 16 == 0)
printf("%s\n", "");
printf("%d ", array[i]);
}
}
// realiza la suma de determinantes
__global__ void sumador(int* arreglo, int* result, float N)
{
__shared__ int compartida[10];
int tid = blockIdx.x * blockDim.x + threadIdx.x;
compartida[threadIdx.x] = arreglo[tid];
__syncthreads();
for(int i=1; pow((float)2,(float)i-1) < N; i++)
{
int acceso = pow((float)2,(float)i);
int offset = pow((float)2, (float)i-1);
if(threadIdx.x < (N/acceso) && (threadIdx.x * acceso + offset) < (N - blockIdx.x * blockDim.x))
{
compartida[threadIdx.x * acceso] = compartida[threadIdx.x * acceso] + compartida[threadIdx.x * acceso + offset];
compartida[threadIdx.x * acceso + offset] = 0;
printf("%s\n", "TRABAJO");
result[blockIdx.x] = compartida[0];
}
printf("%s\n", "");
}
}
int* arreglo_suma1;
int* d_arreglo_suma1;
int* arreglo_result;
int* d_arreglo_suma2;
int main(int argc, char** argv){
int N = 8;
//##################################################################################
//############################## INICIALIZACION ####################################
arreglo_suma1 = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma1, N * sizeof(int));
arreglo_result = (int*) malloc(N * sizeof(int));
hipMalloc(&d_arreglo_suma2, N * sizeof(int));
init_CPU_array(arreglo_suma1, N);
hipMemcpy(d_arreglo_suma1, arreglo_suma1, N * sizeof(int), hipMemcpyHostToDevice);
int threads_per_block = 10;
int block_count = ceil((float)N / threads_per_block);
//##################################################################################
//################################ EJECUCIONES #####################################
dim3 miGrid1D_1(block_count,1);
dim3 miBloque1D_1(threads_per_block,1);
sumador<<<miGrid1D_1, miBloque1D_1>>>(d_arreglo_suma1, d_arreglo_suma2, N);
//###################################################################################
//################################### READ BACK #####################################
hipMemcpy(arreglo_result, d_arreglo_suma2, N * sizeof(int), hipMemcpyDeviceToHost);
printf("%s\n", "RESULTADO DE LA SUMA:");
print_CPU_matrix(arreglo_result, N);
free(arreglo_suma1);
hipFree (d_arreglo_suma1);
free(arreglo_result);
hipFree (d_arreglo_suma2);
}
|
.text
.file "sum_test_shared_single_block.hip"
.globl _Z6printii # -- Begin function _Z6printii
.p2align 4, 0x90
.type _Z6printii,@function
_Z6printii: # @_Z6printii
.cfi_startproc
# %bb.0:
movl %edi, %esi
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z6printii, .Lfunc_end0-_Z6printii
.cfi_endproc
# -- End function
.globl _Z14init_CPU_arrayPii # -- Begin function _Z14init_CPU_arrayPii
.p2align 4, 0x90
.type _Z14init_CPU_arrayPii,@function
_Z14init_CPU_arrayPii: # @_Z14init_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z14init_CPU_arrayPii, .Lfunc_end1-_Z14init_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z15print_CPU_arrayPii # -- Begin function _Z15print_CPU_arrayPii
.p2align 4, 0x90
.type _Z15print_CPU_arrayPii,@function
_Z15print_CPU_arrayPii: # @_Z15print_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z15print_CPU_arrayPii, .Lfunc_end2-_Z15print_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z16print_CPU_matrixPii # -- Begin function _Z16print_CPU_matrixPii
.p2align 4, 0x90
.type _Z16print_CPU_matrixPii,@function
_Z16print_CPU_matrixPii: # @_Z16print_CPU_matrixPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testb $15, %r15b
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16print_CPU_matrixPii, .Lfunc_end3-_Z16print_CPU_matrixPii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sumadorPiS_f # -- Begin function _Z22__device_stub__sumadorPiS_f
.p2align 4, 0x90
.type _Z22__device_stub__sumadorPiS_f,@function
_Z22__device_stub__sumadorPiS_f: # @_Z22__device_stub__sumadorPiS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sumadorPiS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z22__device_stub__sumadorPiS_f, .Lfunc_end4-_Z22__device_stub__sumadorPiS_f
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $32, %edi
callq malloc
movq %rax, arreglo_suma1(%rip)
movl $d_arreglo_suma1, %edi
movl $32, %esi
callq hipMalloc
movl $32, %edi
callq malloc
movq %rax, arreglo_result(%rip)
movl $d_arreglo_suma2, %edi
movl $32, %esi
callq hipMalloc
xorl %eax, %eax
movq arreglo_suma1(%rip), %rsi
.p2align 4, 0x90
.LBB5_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rsi,%rax,4)
incq %rax
cmpq $8, %rax
jne .LBB5_1
# %bb.2: # %_Z14init_CPU_arrayPii.exit
movq d_arreglo_suma1(%rip), %rdi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl $1090519040, 12(%rsp) # imm = 0x41000000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sumadorPiS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq arreglo_result(%rip), %rdi
movq d_arreglo_suma2(%rip), %rsi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
callq puts@PLT
movq arreglo_result(%rip), %rbx
xorl %r14d, %r14d
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_5 Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $8, %r14
je .LBB5_8
.LBB5_5: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
testq %r14, %r14
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB5_7
.LBB5_8: # %_Z16print_CPU_matrixPii.exit
movq arreglo_suma1(%rip), %rdi
callq free
movq d_arreglo_suma1(%rip), %rdi
callq hipFree
movq arreglo_result(%rip), %rdi
callq free
movq d_arreglo_suma2(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sumadorPiS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type _Z7sumadorPiS_f,@object # @_Z7sumadorPiS_f
.section .rodata,"a",@progbits
.globl _Z7sumadorPiS_f
.p2align 3, 0x0
_Z7sumadorPiS_f:
.quad _Z22__device_stub__sumadorPiS_f
.size _Z7sumadorPiS_f, 8
.type arreglo_suma1,@object # @arreglo_suma1
.bss
.globl arreglo_suma1
.p2align 3, 0x0
arreglo_suma1:
.quad 0
.size arreglo_suma1, 8
.type d_arreglo_suma1,@object # @d_arreglo_suma1
.globl d_arreglo_suma1
.p2align 3, 0x0
d_arreglo_suma1:
.quad 0
.size d_arreglo_suma1, 8
.type arreglo_result,@object # @arreglo_result
.globl arreglo_result
.p2align 3, 0x0
arreglo_result:
.quad 0
.size arreglo_result, 8
.type d_arreglo_suma2,@object # @d_arreglo_suma2
.globl d_arreglo_suma2
.p2align 3, 0x0
d_arreglo_suma2:
.quad 0
.size d_arreglo_suma2, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "RESULTADO DE LA SUMA:"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sumadorPiS_f"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sumadorPiS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sumadorPiS_f
.addrsig_sym d_arreglo_suma1
.addrsig_sym d_arreglo_suma2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000688c6_00000000-6_sum_test_shared_single_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl _Z6printii
.type _Z6printii, @function
_Z6printii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6printii, .-_Z6printii
.globl _Z14init_CPU_arrayPii
.type _Z14init_CPU_arrayPii, @function
_Z14init_CPU_arrayPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L5
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L7:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z14init_CPU_arrayPii, .-_Z14init_CPU_arrayPii
.globl _Z15print_CPU_arrayPii
.type _Z15print_CPU_arrayPii, @function
_Z15print_CPU_arrayPii:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L14
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L11:
movl (%rbx), %edi
call _Z6printii
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z15print_CPU_arrayPii, .-_Z15print_CPU_arrayPii
.section .rodata.str1.1
.LC1:
.string ""
.LC2:
.string "%s\n"
.LC3:
.string "%d "
.text
.globl _Z16print_CPU_matrixPii
.type _Z16print_CPU_matrixPii, @function
_Z16print_CPU_matrixPii:
.LFB2060:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L23
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
jmp .L20
.L19:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
je .L26
.L20:
testb $15, %bl
jne .L19
movq %r15, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L26:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z16print_CPU_matrixPii, .-_Z16print_CPU_matrixPii
.globl _Z29__device_stub__Z7sumadorPiS_fPiS_f
.type _Z29__device_stub__Z7sumadorPiS_fPiS_f, @function
_Z29__device_stub__Z7sumadorPiS_fPiS_f:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7sumadorPiS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z7sumadorPiS_fPiS_f, .-_Z29__device_stub__Z7sumadorPiS_fPiS_f
.globl _Z7sumadorPiS_f
.type _Z7sumadorPiS_f, @function
_Z7sumadorPiS_f:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z7sumadorPiS_f, .-_Z7sumadorPiS_f
.section .rodata.str1.1
.LC5:
.string "RESULTADO DE LA SUMA:"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, %edi
call malloc@PLT
movq %rax, arreglo_suma1(%rip)
movl $32, %esi
leaq d_arreglo_suma1(%rip), %rdi
call cudaMalloc@PLT
movl $32, %edi
call malloc@PLT
movq %rax, arreglo_result(%rip)
movl $32, %esi
leaq d_arreglo_suma2(%rip), %rdi
call cudaMalloc@PLT
movl $8, %esi
movq arreglo_suma1(%rip), %rdi
call _Z14init_CPU_arrayPii
movl $1, %ecx
movl $32, %edx
movq arreglo_suma1(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call cudaMemcpy@PLT
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L36:
movl $2, %ecx
movl $32, %edx
movq d_arreglo_suma2(%rip), %rsi
movq arreglo_result(%rip), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %esi
movq arreglo_result(%rip), %rdi
call _Z16print_CPU_matrixPii
movq arreglo_suma1(%rip), %rdi
call free@PLT
movq d_arreglo_suma1(%rip), %rdi
call cudaFree@PLT
movq arreglo_result(%rip), %rdi
call free@PLT
movq d_arreglo_suma2(%rip), %rdi
call cudaFree@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movss .LC4(%rip), %xmm0
movq d_arreglo_suma2(%rip), %rsi
movq d_arreglo_suma1(%rip), %rdi
call _Z29__device_stub__Z7sumadorPiS_fPiS_f
jmp .L36
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7sumadorPiS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sumadorPiS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_arreglo_suma2
.bss
.align 8
.type d_arreglo_suma2, @object
.size d_arreglo_suma2, 8
d_arreglo_suma2:
.zero 8
.globl arreglo_result
.align 8
.type arreglo_result, @object
.size arreglo_result, 8
arreglo_result:
.zero 8
.globl d_arreglo_suma1
.align 8
.type d_arreglo_suma1, @object
.size d_arreglo_suma1, 8
d_arreglo_suma1:
.zero 8
.globl arreglo_suma1
.align 8
.type arreglo_suma1, @object
.size arreglo_suma1, 8
arreglo_suma1:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1090519040
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "sum_test_shared_single_block.hip"
.globl _Z6printii # -- Begin function _Z6printii
.p2align 4, 0x90
.type _Z6printii,@function
_Z6printii: # @_Z6printii
.cfi_startproc
# %bb.0:
movl %edi, %esi
movl $.L.str, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z6printii, .Lfunc_end0-_Z6printii
.cfi_endproc
# -- End function
.globl _Z14init_CPU_arrayPii # -- Begin function _Z14init_CPU_arrayPii
.p2align 4, 0x90
.type _Z14init_CPU_arrayPii,@function
_Z14init_CPU_arrayPii: # @_Z14init_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z14init_CPU_arrayPii, .Lfunc_end1-_Z14init_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z15print_CPU_arrayPii # -- Begin function _Z15print_CPU_arrayPii
.p2align 4, 0x90
.type _Z15print_CPU_arrayPii,@function
_Z15print_CPU_arrayPii: # @_Z15print_CPU_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z15print_CPU_arrayPii, .Lfunc_end2-_Z15print_CPU_arrayPii
.cfi_endproc
# -- End function
.globl _Z16print_CPU_matrixPii # -- Begin function _Z16print_CPU_matrixPii
.p2align 4, 0x90
.type _Z16print_CPU_matrixPii,@function
_Z16print_CPU_matrixPii: # @_Z16print_CPU_matrixPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testb $15, %r15b
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z16print_CPU_matrixPii, .Lfunc_end3-_Z16print_CPU_matrixPii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__sumadorPiS_f # -- Begin function _Z22__device_stub__sumadorPiS_f
.p2align 4, 0x90
.type _Z22__device_stub__sumadorPiS_f,@function
_Z22__device_stub__sumadorPiS_f: # @_Z22__device_stub__sumadorPiS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sumadorPiS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z22__device_stub__sumadorPiS_f, .Lfunc_end4-_Z22__device_stub__sumadorPiS_f
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $32, %edi
callq malloc
movq %rax, arreglo_suma1(%rip)
movl $d_arreglo_suma1, %edi
movl $32, %esi
callq hipMalloc
movl $32, %edi
callq malloc
movq %rax, arreglo_result(%rip)
movl $d_arreglo_suma2, %edi
movl $32, %esi
callq hipMalloc
xorl %eax, %eax
movq arreglo_suma1(%rip), %rsi
.p2align 4, 0x90
.LBB5_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rsi,%rax,4)
incq %rax
cmpq $8, %rax
jne .LBB5_1
# %bb.2: # %_Z14init_CPU_arrayPii.exit
movq d_arreglo_suma1(%rip), %rdi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq d_arreglo_suma1(%rip), %rax
movq d_arreglo_suma2(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl $1090519040, 12(%rsp) # imm = 0x41000000
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7sumadorPiS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq arreglo_result(%rip), %rdi
movq d_arreglo_suma2(%rip), %rsi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
callq puts@PLT
movq arreglo_result(%rip), %rbx
xorl %r14d, %r14d
jmp .LBB5_5
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_5 Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $8, %r14
je .LBB5_8
.LBB5_5: # %.lr.ph.i20
# =>This Inner Loop Header: Depth=1
testq %r14, %r14
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB5_7
.LBB5_8: # %_Z16print_CPU_matrixPii.exit
movq arreglo_suma1(%rip), %rdi
callq free
movq d_arreglo_suma1(%rip), %rdi
callq hipFree
movq arreglo_result(%rip), %rdi
callq free
movq d_arreglo_suma2(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sumadorPiS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type _Z7sumadorPiS_f,@object # @_Z7sumadorPiS_f
.section .rodata,"a",@progbits
.globl _Z7sumadorPiS_f
.p2align 3, 0x0
_Z7sumadorPiS_f:
.quad _Z22__device_stub__sumadorPiS_f
.size _Z7sumadorPiS_f, 8
.type arreglo_suma1,@object # @arreglo_suma1
.bss
.globl arreglo_suma1
.p2align 3, 0x0
arreglo_suma1:
.quad 0
.size arreglo_suma1, 8
.type d_arreglo_suma1,@object # @d_arreglo_suma1
.globl d_arreglo_suma1
.p2align 3, 0x0
d_arreglo_suma1:
.quad 0
.size d_arreglo_suma1, 8
.type arreglo_result,@object # @arreglo_result
.globl arreglo_result
.p2align 3, 0x0
arreglo_result:
.quad 0
.size arreglo_result, 8
.type d_arreglo_suma2,@object # @d_arreglo_suma2
.globl d_arreglo_suma2
.p2align 3, 0x0
d_arreglo_suma2:
.quad 0
.size d_arreglo_suma2, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "RESULTADO DE LA SUMA:"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7sumadorPiS_f"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sumadorPiS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sumadorPiS_f
.addrsig_sym d_arreglo_suma1
.addrsig_sym d_arreglo_suma2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "thrust/device_ptr.h"
#include "thrust/sort.h"
__global__ void calculate_hash(uint *hash_values, uint *particle_ids, int length)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i >= length)
return;
hash_values[i] = 1;
particle_ids[i] = i;
}
void hash_particles_gpu(uint *d_hash_values, uint *d_particle_ids, int length)
{
int block_size = 256;
int num_blocks = ceil(length/(float)block_size);
calculate_hash<<<num_blocks, block_size>>>(d_hash_values, d_particle_ids, length);
cudaDeviceSynchronize();
thrust::device_ptr<uint> keys(d_hash_values);
thrust::device_ptr<uint> values(d_particle_ids);
thrust::sort_by_key(keys, keys+length, values);
}
int main(int argc, char *argv[])
{
int length = 15;
int bytes;
#ifdef BROKE
int *m_int;
cudaMallocManaged((void**)&m_int, sizeof(int));
#endif
// Allocate uint hash value array
bytes = length*sizeof(unsigned int);
unsigned int * hash_values;
cudaMalloc((void**)&hash_values, bytes);
// Allocate uint particle ID array
bytes = length*sizeof(unsigned int);
unsigned int *particle_ids;
cudaMalloc((void**)&particle_ids, bytes);
hash_particles_gpu(hash_values, particle_ids, length);
}
|
#include <hip/hip_runtime.h>
#include "thrust/device_ptr.h"
#include "thrust/sort.h"
__global__ void calculate_hash(uint *hash_values, uint *particle_ids, int length)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i >= length)
return;
hash_values[i] = 1;
particle_ids[i] = i;
}
void hash_particles_gpu(uint *d_hash_values, uint *d_particle_ids, int length)
{
int block_size = 256;
int num_blocks = ceil(length/(float)block_size);
calculate_hash<<<num_blocks, block_size>>>(d_hash_values, d_particle_ids, length);
hipDeviceSynchronize();
thrust::device_ptr<uint> keys(d_hash_values);
thrust::device_ptr<uint> values(d_particle_ids);
thrust::sort_by_key(keys, keys+length, values);
}
int main(int argc, char *argv[])
{
int length = 15;
int bytes;
#ifdef BROKE
int *m_int;
hipMallocManaged((void**)&m_int, sizeof(int));
#endif
// Allocate uint hash value array
bytes = length*sizeof(unsigned int);
unsigned int * hash_values;
hipMalloc((void**)&hash_values, bytes);
// Allocate uint particle ID array
bytes = length*sizeof(unsigned int);
unsigned int *particle_ids;
hipMalloc((void**)&particle_ids, bytes);
hash_particles_gpu(hash_values, particle_ids, length);
}
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
extern "C" {
}
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
|
code for sm_80
Function : _Z15Vector_AdditionPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x63, PT ; /* 0x000000630600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
extern "C" {
}
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
|
.file "tmpxft_000e77bf_00000000-6_Vector_Addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.type _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, @function
_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Vector_AdditionPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, .-_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.globl _Z15Vector_AdditionPiS_S_
.type _Z15Vector_AdditionPiS_S_, @function
_Z15Vector_AdditionPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15Vector_AdditionPiS_S_, .-_Z15Vector_AdditionPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15Vector_AdditionPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Vector_AdditionPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
extern "C" {
}
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Vector_AdditionPiS_S_
.globl _Z15Vector_AdditionPiS_S_
.p2align 8
.type _Z15Vector_AdditionPiS_S_,@function
_Z15Vector_AdditionPiS_S_:
s_cmpk_gt_i32 s15, 0x63
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Vector_AdditionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Vector_AdditionPiS_S_, .Lfunc_end0-_Z15Vector_AdditionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Vector_AdditionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15Vector_AdditionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void Vector_Addition(int *a, int *b, int *c)
{
int tid = blockIdx.x;
if (tid < 100)
c[tid] = a[tid] + b[tid];
}
|
.text
.file "Vector_Addition.hip"
.globl _Z30__device_stub__Vector_AdditionPiS_S_ # -- Begin function _Z30__device_stub__Vector_AdditionPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__Vector_AdditionPiS_S_,@function
_Z30__device_stub__Vector_AdditionPiS_S_: # @_Z30__device_stub__Vector_AdditionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Vector_AdditionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Vector_AdditionPiS_S_, .Lfunc_end0-_Z30__device_stub__Vector_AdditionPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Vector_AdditionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Vector_AdditionPiS_S_,@object # @_Z15Vector_AdditionPiS_S_
.section .rodata,"a",@progbits
.globl _Z15Vector_AdditionPiS_S_
.p2align 3, 0x0
_Z15Vector_AdditionPiS_S_:
.quad _Z30__device_stub__Vector_AdditionPiS_S_
.size _Z15Vector_AdditionPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15Vector_AdditionPiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Vector_AdditionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Vector_AdditionPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15Vector_AdditionPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x63, PT ; /* 0x000000630600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Vector_AdditionPiS_S_
.globl _Z15Vector_AdditionPiS_S_
.p2align 8
.type _Z15Vector_AdditionPiS_S_,@function
_Z15Vector_AdditionPiS_S_:
s_cmpk_gt_i32 s15, 0x63
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Vector_AdditionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15Vector_AdditionPiS_S_, .Lfunc_end0-_Z15Vector_AdditionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Vector_AdditionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15Vector_AdditionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000e77bf_00000000-6_Vector_Addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.type _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, @function
_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15Vector_AdditionPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_, .-_Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
.globl _Z15Vector_AdditionPiS_S_
.type _Z15Vector_AdditionPiS_S_, @function
_Z15Vector_AdditionPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15Vector_AdditionPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15Vector_AdditionPiS_S_, .-_Z15Vector_AdditionPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15Vector_AdditionPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15Vector_AdditionPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Vector_Addition.hip"
.globl _Z30__device_stub__Vector_AdditionPiS_S_ # -- Begin function _Z30__device_stub__Vector_AdditionPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__Vector_AdditionPiS_S_,@function
_Z30__device_stub__Vector_AdditionPiS_S_: # @_Z30__device_stub__Vector_AdditionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15Vector_AdditionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__Vector_AdditionPiS_S_, .Lfunc_end0-_Z30__device_stub__Vector_AdditionPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15Vector_AdditionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15Vector_AdditionPiS_S_,@object # @_Z15Vector_AdditionPiS_S_
.section .rodata,"a",@progbits
.globl _Z15Vector_AdditionPiS_S_
.p2align 3, 0x0
_Z15Vector_AdditionPiS_S_:
.quad _Z30__device_stub__Vector_AdditionPiS_S_
.size _Z15Vector_AdditionPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15Vector_AdditionPiS_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__Vector_AdditionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15Vector_AdditionPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
__global__ void zero_kernel(int * in, int length) {
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx < length)
in[idx] = 0;
}
|
code for sm_80
Function : _Z11zero_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
__global__ void zero_kernel(int * in, int length) {
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx < length)
in[idx] = 0;
}
|
.file "tmpxft_0016def9_00000000-6_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11zero_kernelPiiPii
.type _Z32__device_stub__Z11zero_kernelPiiPii, @function
_Z32__device_stub__Z11zero_kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11zero_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11zero_kernelPiiPii, .-_Z32__device_stub__Z11zero_kernelPiiPii
.globl _Z11zero_kernelPii
.type _Z11zero_kernelPii, @function
_Z11zero_kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11zero_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11zero_kernelPii, .-_Z11zero_kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11zero_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11zero_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
__global__ void zero_kernel(int * in, int length) {
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx < length)
in[idx] = 0;
}
|
#include <hip/hip_runtime.h>
__global__ void zero_kernel(int * in, int length) {
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx < length)
in[idx] = 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
__global__ void zero_kernel(int * in, int length) {
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx < length)
in[idx] = 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11zero_kernelPii
.globl _Z11zero_kernelPii
.p2align 8
.type _Z11zero_kernelPii,@function
_Z11zero_kernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11zero_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11zero_kernelPii, .Lfunc_end0-_Z11zero_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11zero_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11zero_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
__global__ void zero_kernel(int * in, int length) {
int idx = threadIdx.x + blockDim.x*blockIdx.x;
if (idx < length)
in[idx] = 0;
}
|
.text
.file "zero.hip"
.globl _Z26__device_stub__zero_kernelPii # -- Begin function _Z26__device_stub__zero_kernelPii
.p2align 4, 0x90
.type _Z26__device_stub__zero_kernelPii,@function
_Z26__device_stub__zero_kernelPii: # @_Z26__device_stub__zero_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11zero_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__zero_kernelPii, .Lfunc_end0-_Z26__device_stub__zero_kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11zero_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11zero_kernelPii,@object # @_Z11zero_kernelPii
.section .rodata,"a",@progbits
.globl _Z11zero_kernelPii
.p2align 3, 0x0
_Z11zero_kernelPii:
.quad _Z26__device_stub__zero_kernelPii
.size _Z11zero_kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11zero_kernelPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__zero_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11zero_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11zero_kernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11zero_kernelPii
.globl _Z11zero_kernelPii
.p2align 8
.type _Z11zero_kernelPii,@function
_Z11zero_kernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11zero_kernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11zero_kernelPii, .Lfunc_end0-_Z11zero_kernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11zero_kernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11zero_kernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0016def9_00000000-6_zero.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11zero_kernelPiiPii
.type _Z32__device_stub__Z11zero_kernelPiiPii, @function
_Z32__device_stub__Z11zero_kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11zero_kernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11zero_kernelPiiPii, .-_Z32__device_stub__Z11zero_kernelPiiPii
.globl _Z11zero_kernelPii
.type _Z11zero_kernelPii, @function
_Z11zero_kernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11zero_kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11zero_kernelPii, .-_Z11zero_kernelPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11zero_kernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11zero_kernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "zero.hip"
.globl _Z26__device_stub__zero_kernelPii # -- Begin function _Z26__device_stub__zero_kernelPii
.p2align 4, 0x90
.type _Z26__device_stub__zero_kernelPii,@function
_Z26__device_stub__zero_kernelPii: # @_Z26__device_stub__zero_kernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11zero_kernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__zero_kernelPii, .Lfunc_end0-_Z26__device_stub__zero_kernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11zero_kernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11zero_kernelPii,@object # @_Z11zero_kernelPii
.section .rodata,"a",@progbits
.globl _Z11zero_kernelPii
.p2align 3, 0x0
_Z11zero_kernelPii:
.quad _Z26__device_stub__zero_kernelPii
.size _Z11zero_kernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11zero_kernelPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__zero_kernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11zero_kernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KtexFillRect(void* surface, double* tb, int width, int height, size_t pitch, float2* Pts, int k, float th)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char *pixel1;
if (x >= width || y >= height) return;
pixel1 = (unsigned char *)( (char*)surface + y*pitch) + 4*x;
if (
((Pts[1].y-Pts[0].y)*(x-Pts[0].x)-( y-Pts[0].y)*(Pts[1].x-Pts[0].x)>=0)
&&
((Pts[2].y-Pts[1].y)*(x-Pts[1].x)-( y-Pts[1].y)*(Pts[2].x-Pts[1].x)>=0)
&&
((Pts[3].y-Pts[2].y)*(x-Pts[2].x)-( y-Pts[2].y)*(Pts[3].x-Pts[2].x)>=0)
&&
((Pts[0].y-Pts[3].y)*(x-Pts[3].x)-( y-Pts[3].y)*(Pts[0].x-Pts[3].x)>=0)
&&
(pixel1[k]>=th)
)
tb[x + width*y] = 1;
}
|
code for sm_80
Function : _Z12KtexFillRectPvPdiimP6float2if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ MOV R9, c[0x0][0x184] ; /* 0x0000610000097a02 */
/* 0x000fe20000000f00 */
/*00d0*/ I2F R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000201400 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ LDG.E.64 R2, [R8.64] ; /* 0x0000000608027981 */
/* 0x000e28000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R8.64+0x8] ; /* 0x0000080608067981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ I2F R11, R5 ; /* 0x00000005000b7306 */
/* 0x000e620000201400 */
/*0120*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fc8000ff1e03f */
/*0130*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0140*/ FADD R10, -R3, R4 ; /* 0x00000004030a7221 */
/* 0x001fe40000000100 */
/*0150*/ FADD R13, R6, -R2 ; /* 0x80000002060d7221 */
/* 0x004fc80000000000 */
/*0160*/ FMUL R12, R10, R13 ; /* 0x0000000d0a0c7220 */
/* 0x000fe40000400000 */
/*0170*/ FADD R10, R7, -R3 ; /* 0x80000003070a7221 */
/* 0x000fe40000000000 */
/*0180*/ FADD R13, -R2, R11 ; /* 0x0000000b020d7221 */
/* 0x002fc80000000100 */
/*0190*/ FFMA R10, R10, R13, -R12 ; /* 0x0000000d0a0a7223 */
/* 0x000fe2000000080c */
/*01a0*/ MOV R12, UR4 ; /* 0x00000004000c7c02 */
/* 0x000fe40008000f00 */
/*01b0*/ MOV R13, UR5 ; /* 0x00000005000d7c02 */
/* 0x000fe40008000f00 */
/*01c0*/ FSETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f06000 */
/*01d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E.64 R8, [R12.64+0x8] ; /* 0x000008060c087981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ FADD R15, -R7.reuse, R4 ; /* 0x00000004070f7221 */
/* 0x040fe40000000100 */
/*0200*/ FADD R10, -R6.reuse, R8 ; /* 0x00000008060a7221 */
/* 0x044fe40000000100 */
/*0210*/ FADD R6, -R6, R11 ; /* 0x0000000b06067221 */
/* 0x000fe40000000100 */
/*0220*/ FADD R7, -R7, R9 ; /* 0x0000000907077221 */
/* 0x000fe40000000100 */
/*0230*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R6, R7, R6, -R10 ; /* 0x0000000607067223 */
/* 0x000fca000000080a */
/*0250*/ FSETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fda0003f06000 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.64 R6, [R12.64+0x10] ; /* 0x000010060c067981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ FADD R15, R4, -R9 ; /* 0x80000009040f7221 */
/* 0x000fe40000000000 */
/*0290*/ FADD R10, -R8, R6 ; /* 0x00000006080a7221 */
/* 0x004fe40000000100 */
/*02a0*/ FADD R8, R11, -R8 ; /* 0x800000080b087221 */
/* 0x000fe40000000000 */
/*02b0*/ FADD R9, -R9, R7 ; /* 0x0000000709097221 */
/* 0x000fe40000000100 */
/*02c0*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fc80000400000 */
/*02d0*/ FFMA R8, R9, R8, -R10 ; /* 0x0000000809087223 */
/* 0x000fca000000080a */
/*02e0*/ FSETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fda0003f06000 */
/*02f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0300*/ FADD R2, R2, -R6.reuse ; /* 0x8000000602027221 */
/* 0x100fe40000000000 */
/*0310*/ FADD R9, R4, -R7.reuse ; /* 0x8000000704097221 */
/* 0x100fe40000000000 */
/*0320*/ FADD R3, R3, -R7 ; /* 0x8000000703037221 */
/* 0x000fe40000000000 */
/*0330*/ FADD R6, R11, -R6 ; /* 0x800000060b067221 */
/* 0x000fe40000000000 */
/*0340*/ FMUL R2, R2, R9 ; /* 0x0000000902027220 */
/* 0x000fc80000400000 */
/*0350*/ FFMA R2, R3, R6, -R2 ; /* 0x0000000603027223 */
/* 0x000fca0000000802 */
/*0360*/ FSETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f06000 */
/*0370*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0380*/ SHF.L.U32 R2, R5, 0x2, RZ ; /* 0x0000000205027819 */
/* 0x000fe400000006ff */
/*0390*/ SHF.R.S32.HI R4, RZ, 0x1f, R0 ; /* 0x0000001fff047819 */
/* 0x000fe40000011400 */
/*03a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2.reuse ; /* 0x0000001fff037819 */
/* 0x100fe40000011402 */
/*03b0*/ MOV R9, c[0x0][0x188] ; /* 0x0000620000097a02 */
/* 0x000fe20000000f00 */
/*03c0*/ IMAD R7, R4, c[0x0][0x178], RZ ; /* 0x00005e0004077a24 */
/* 0x000fe400078e02ff */
/*03d0*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], R2 ; /* 0x00005e0000027a25 */
/* 0x000fe200078e0002 */
/*03e0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x000fc60000011409 */
/*03f0*/ IMAD R7, R0, c[0x0][0x17c], R7 ; /* 0x00005f0000077a24 */
/* 0x000fe200078e0207 */
/*0400*/ IADD3 R2, P0, P1, R2, c[0x0][0x160], R9 ; /* 0x0000580002027a10 */
/* 0x000fc8000791e009 */
/*0410*/ IADD3 R3, R3, R7, RZ ; /* 0x0000000703037210 */
/* 0x000fc80007ffe0ff */
/*0420*/ IADD3.X R3, R3, c[0x0][0x164], R4, P0, P1 ; /* 0x0000590003037a10 */
/* 0x000fca00007e2404 */
/*0430*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1100 */
/*0440*/ I2F.U16 R4, R2 ; /* 0x0000000200047306 */
/* 0x004e240000101000 */
/*0450*/ FSETP.GE.AND P0, PT, R4, c[0x0][0x18c], PT ; /* 0x0000630004007a0b */
/* 0x001fda0003f06000 */
/*0460*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0470*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0480*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x000fe200078e0205 */
/*0490*/ HFMA2.MMA R5, -RZ, RZ, 1.984375, 0 ; /* 0x3ff00000ff057435 */
/* 0x000fe200000001ff */
/*04a0*/ MOV R4, 0x0 ; /* 0x0000000000047802 */
/* 0x000fce0000000f00 */
/*04b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*04c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KtexFillRect(void* surface, double* tb, int width, int height, size_t pitch, float2* Pts, int k, float th)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char *pixel1;
if (x >= width || y >= height) return;
pixel1 = (unsigned char *)( (char*)surface + y*pitch) + 4*x;
if (
((Pts[1].y-Pts[0].y)*(x-Pts[0].x)-( y-Pts[0].y)*(Pts[1].x-Pts[0].x)>=0)
&&
((Pts[2].y-Pts[1].y)*(x-Pts[1].x)-( y-Pts[1].y)*(Pts[2].x-Pts[1].x)>=0)
&&
((Pts[3].y-Pts[2].y)*(x-Pts[2].x)-( y-Pts[2].y)*(Pts[3].x-Pts[2].x)>=0)
&&
((Pts[0].y-Pts[3].y)*(x-Pts[3].x)-( y-Pts[3].y)*(Pts[0].x-Pts[3].x)>=0)
&&
(pixel1[k]>=th)
)
tb[x + width*y] = 1;
}
|
.file "tmpxft_000e054c_00000000-6_KtexFillRect.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if
.type _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if, @function
_Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12KtexFillRectPvPdiimP6float2if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if, .-_Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if
.globl _Z12KtexFillRectPvPdiimP6float2if
.type _Z12KtexFillRectPvPdiimP6float2if, @function
_Z12KtexFillRectPvPdiimP6float2if:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12KtexFillRectPvPdiimP6float2if, .-_Z12KtexFillRectPvPdiimP6float2if
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12KtexFillRectPvPdiimP6float2if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12KtexFillRectPvPdiimP6float2if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MaxThreadsY
.bss
.align 4
.type MaxThreadsY, @object
.size MaxThreadsY, 4
MaxThreadsY:
.zero 4
.globl MaxThreadsX
.align 4
.type MaxThreadsX, @object
.size MaxThreadsX, 4
MaxThreadsX:
.zero 4
.globl MaxThreadsPerBlock
.align 4
.type MaxThreadsPerBlock, @object
.size MaxThreadsPerBlock, 4
MaxThreadsPerBlock:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KtexFillRect(void* surface, double* tb, int width, int height, size_t pitch, float2* Pts, int k, float th)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char *pixel1;
if (x >= width || y >= height) return;
pixel1 = (unsigned char *)( (char*)surface + y*pitch) + 4*x;
if (
((Pts[1].y-Pts[0].y)*(x-Pts[0].x)-( y-Pts[0].y)*(Pts[1].x-Pts[0].x)>=0)
&&
((Pts[2].y-Pts[1].y)*(x-Pts[1].x)-( y-Pts[1].y)*(Pts[2].x-Pts[1].x)>=0)
&&
((Pts[3].y-Pts[2].y)*(x-Pts[2].x)-( y-Pts[2].y)*(Pts[3].x-Pts[2].x)>=0)
&&
((Pts[0].y-Pts[3].y)*(x-Pts[3].x)-( y-Pts[3].y)*(Pts[0].x-Pts[3].x)>=0)
&&
(pixel1[k]>=th)
)
tb[x + width*y] = 1;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KtexFillRect(void* surface, double* tb, int width, int height, size_t pitch, float2* Pts, int k, float th)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char *pixel1;
if (x >= width || y >= height) return;
pixel1 = (unsigned char *)( (char*)surface + y*pitch) + 4*x;
if (
((Pts[1].y-Pts[0].y)*(x-Pts[0].x)-( y-Pts[0].y)*(Pts[1].x-Pts[0].x)>=0)
&&
((Pts[2].y-Pts[1].y)*(x-Pts[1].x)-( y-Pts[1].y)*(Pts[2].x-Pts[1].x)>=0)
&&
((Pts[3].y-Pts[2].y)*(x-Pts[2].x)-( y-Pts[2].y)*(Pts[3].x-Pts[2].x)>=0)
&&
((Pts[0].y-Pts[3].y)*(x-Pts[3].x)-( y-Pts[3].y)*(Pts[0].x-Pts[3].x)>=0)
&&
(pixel1[k]>=th)
)
tb[x + width*y] = 1;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KtexFillRect(void* surface, double* tb, int width, int height, size_t pitch, float2* Pts, int k, float th)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char *pixel1;
if (x >= width || y >= height) return;
pixel1 = (unsigned char *)( (char*)surface + y*pitch) + 4*x;
if (
((Pts[1].y-Pts[0].y)*(x-Pts[0].x)-( y-Pts[0].y)*(Pts[1].x-Pts[0].x)>=0)
&&
((Pts[2].y-Pts[1].y)*(x-Pts[1].x)-( y-Pts[1].y)*(Pts[2].x-Pts[1].x)>=0)
&&
((Pts[3].y-Pts[2].y)*(x-Pts[2].x)-( y-Pts[2].y)*(Pts[3].x-Pts[2].x)>=0)
&&
((Pts[0].y-Pts[3].y)*(x-Pts[3].x)-( y-Pts[3].y)*(Pts[0].x-Pts[3].x)>=0)
&&
(pixel1[k]>=th)
)
tb[x + width*y] = 1;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.globl _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.p2align 8
.type _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif,@function
_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f32_i32_e32 v3, v1
v_cvt_f32_i32_e32 v2, v0
s_waitcnt lgkmcnt(0)
s_load_b128 s[4:7], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_subrev_f32 v4, s5, v3 :: v_dual_subrev_f32 v7, s4, v2
v_sub_f32_e64 v5, s6, s4
v_sub_f32_e64 v6, s7, s5
v_mul_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v6, v7, -v4
v_cmp_le_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[10:11], s[2:3], 0x10
v_dual_subrev_f32 v4, s7, v3 :: v_dual_subrev_f32 v7, s6, v2
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v5, s10, s6
v_sub_f32_e64 v6, s11, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v4, v5
v_fma_f32 v4, v7, v6, -v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[2:3], 0x18
v_dual_subrev_f32 v4, s11, v3 :: v_dual_subrev_f32 v7, s10, v2
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v5, s2, s10
v_sub_f32_e64 v6, s3, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v4, v5
v_fma_f32 v4, v7, v6, -v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_dual_subrev_f32 v3, s3, v3 :: v_dual_subrev_f32 v2, s2, v2
v_sub_f32_e64 v4, s4, s2
v_sub_f32_e64 v5, s5, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v4
v_fma_f32 v2, v5, v2, -v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x28
v_ashrrev_i32_e32 v4, 31, v1
v_lshlrev_b32_e32 v6, 2, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, s[2:3]
v_mul_lo_u32 v5, v1, s5
v_mul_lo_u32 v4, v4, s4
s_ashr_i32 s2, s6, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v6
v_add3_u32 v3, v4, v3, v5
v_ashrrev_i32_e32 v4, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s2, v3, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v2
v_cmp_le_f32_e32 vcc_lo, s7, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x3ff00000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, .Lfunc_end0-_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
// includes, project
#define PI 3.1415926536f
int MaxThreadsPerBlock;
int MaxThreadsX;
int MaxThreadsY;
// Conversion d'un vecteur réel en vecteur complexe
// Conversion d'un vecteur complexe en vecteur réel
// Multiplie point par point un vecteur complex par un vecteur réel
// Applique y = at*x +bt à chaque point d'un vecteur réel
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de bytes
// Alpha n'est pas modifié
// Remplissage de la linearmem (tableau de pixels) associée à la texture avec le tableau de réel
// Alpha autorise l'affichage au dessus d'un certain seuil
// Processus auto-régressif X2 = a*X1 + b*X0 + N0;
// Expansion
// On applique une interpolation bi-linéaire à la source
// Transformation Cartesian To Polar
// On applique une interpolation bi-linéaire à la source
__global__ void KtexFillRect(void* surface, double* tb, int width, int height, size_t pitch, float2* Pts, int k, float th)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char *pixel1;
if (x >= width || y >= height) return;
pixel1 = (unsigned char *)( (char*)surface + y*pitch) + 4*x;
if (
((Pts[1].y-Pts[0].y)*(x-Pts[0].x)-( y-Pts[0].y)*(Pts[1].x-Pts[0].x)>=0)
&&
((Pts[2].y-Pts[1].y)*(x-Pts[1].x)-( y-Pts[1].y)*(Pts[2].x-Pts[1].x)>=0)
&&
((Pts[3].y-Pts[2].y)*(x-Pts[2].x)-( y-Pts[2].y)*(Pts[3].x-Pts[2].x)>=0)
&&
((Pts[0].y-Pts[3].y)*(x-Pts[3].x)-( y-Pts[3].y)*(Pts[0].x-Pts[3].x)>=0)
&&
(pixel1[k]>=th)
)
tb[x + width*y] = 1;
}
|
.text
.file "KtexFillRect.hip"
.globl _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif # -- Begin function _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.p2align 4, 0x90
.type _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif,@function
_Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif: # @_Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, .Lfunc_end0-_Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type MaxThreadsPerBlock,@object # @MaxThreadsPerBlock
.bss
.globl MaxThreadsPerBlock
.p2align 2, 0x0
MaxThreadsPerBlock:
.long 0 # 0x0
.size MaxThreadsPerBlock, 4
.type MaxThreadsX,@object # @MaxThreadsX
.globl MaxThreadsX
.p2align 2, 0x0
MaxThreadsX:
.long 0 # 0x0
.size MaxThreadsX, 4
.type MaxThreadsY,@object # @MaxThreadsY
.globl MaxThreadsY
.p2align 2, 0x0
MaxThreadsY:
.long 0 # 0x0
.size MaxThreadsY, 4
.type _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif,@object # @_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.section .rodata,"a",@progbits
.globl _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.p2align 3, 0x0
_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif:
.quad _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.size _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12KtexFillRectPvPdiimP6float2if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ MOV R9, c[0x0][0x184] ; /* 0x0000610000097a02 */
/* 0x000fe20000000f00 */
/*00d0*/ I2F R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000201400 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ LDG.E.64 R2, [R8.64] ; /* 0x0000000608027981 */
/* 0x000e28000c1e1b00 */
/*0100*/ LDG.E.64 R6, [R8.64+0x8] ; /* 0x0000080608067981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ I2F R11, R5 ; /* 0x00000005000b7306 */
/* 0x000e620000201400 */
/*0120*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fc8000ff1e03f */
/*0130*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0140*/ FADD R10, -R3, R4 ; /* 0x00000004030a7221 */
/* 0x001fe40000000100 */
/*0150*/ FADD R13, R6, -R2 ; /* 0x80000002060d7221 */
/* 0x004fc80000000000 */
/*0160*/ FMUL R12, R10, R13 ; /* 0x0000000d0a0c7220 */
/* 0x000fe40000400000 */
/*0170*/ FADD R10, R7, -R3 ; /* 0x80000003070a7221 */
/* 0x000fe40000000000 */
/*0180*/ FADD R13, -R2, R11 ; /* 0x0000000b020d7221 */
/* 0x002fc80000000100 */
/*0190*/ FFMA R10, R10, R13, -R12 ; /* 0x0000000d0a0a7223 */
/* 0x000fe2000000080c */
/*01a0*/ MOV R12, UR4 ; /* 0x00000004000c7c02 */
/* 0x000fe40008000f00 */
/*01b0*/ MOV R13, UR5 ; /* 0x00000005000d7c02 */
/* 0x000fe40008000f00 */
/*01c0*/ FSETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f06000 */
/*01d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E.64 R8, [R12.64+0x8] ; /* 0x000008060c087981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ FADD R15, -R7.reuse, R4 ; /* 0x00000004070f7221 */
/* 0x040fe40000000100 */
/*0200*/ FADD R10, -R6.reuse, R8 ; /* 0x00000008060a7221 */
/* 0x044fe40000000100 */
/*0210*/ FADD R6, -R6, R11 ; /* 0x0000000b06067221 */
/* 0x000fe40000000100 */
/*0220*/ FADD R7, -R7, R9 ; /* 0x0000000907077221 */
/* 0x000fe40000000100 */
/*0230*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R6, R7, R6, -R10 ; /* 0x0000000607067223 */
/* 0x000fca000000080a */
/*0250*/ FSETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fda0003f06000 */
/*0260*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E.64 R6, [R12.64+0x10] ; /* 0x000010060c067981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ FADD R15, R4, -R9 ; /* 0x80000009040f7221 */
/* 0x000fe40000000000 */
/*0290*/ FADD R10, -R8, R6 ; /* 0x00000006080a7221 */
/* 0x004fe40000000100 */
/*02a0*/ FADD R8, R11, -R8 ; /* 0x800000080b087221 */
/* 0x000fe40000000000 */
/*02b0*/ FADD R9, -R9, R7 ; /* 0x0000000709097221 */
/* 0x000fe40000000100 */
/*02c0*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x000fc80000400000 */
/*02d0*/ FFMA R8, R9, R8, -R10 ; /* 0x0000000809087223 */
/* 0x000fca000000080a */
/*02e0*/ FSETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fda0003f06000 */
/*02f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0300*/ FADD R2, R2, -R6.reuse ; /* 0x8000000602027221 */
/* 0x100fe40000000000 */
/*0310*/ FADD R9, R4, -R7.reuse ; /* 0x8000000704097221 */
/* 0x100fe40000000000 */
/*0320*/ FADD R3, R3, -R7 ; /* 0x8000000703037221 */
/* 0x000fe40000000000 */
/*0330*/ FADD R6, R11, -R6 ; /* 0x800000060b067221 */
/* 0x000fe40000000000 */
/*0340*/ FMUL R2, R2, R9 ; /* 0x0000000902027220 */
/* 0x000fc80000400000 */
/*0350*/ FFMA R2, R3, R6, -R2 ; /* 0x0000000603027223 */
/* 0x000fca0000000802 */
/*0360*/ FSETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f06000 */
/*0370*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0380*/ SHF.L.U32 R2, R5, 0x2, RZ ; /* 0x0000000205027819 */
/* 0x000fe400000006ff */
/*0390*/ SHF.R.S32.HI R4, RZ, 0x1f, R0 ; /* 0x0000001fff047819 */
/* 0x000fe40000011400 */
/*03a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R2.reuse ; /* 0x0000001fff037819 */
/* 0x100fe40000011402 */
/*03b0*/ MOV R9, c[0x0][0x188] ; /* 0x0000620000097a02 */
/* 0x000fe20000000f00 */
/*03c0*/ IMAD R7, R4, c[0x0][0x178], RZ ; /* 0x00005e0004077a24 */
/* 0x000fe400078e02ff */
/*03d0*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], R2 ; /* 0x00005e0000027a25 */
/* 0x000fe200078e0002 */
/*03e0*/ SHF.R.S32.HI R4, RZ, 0x1f, R9 ; /* 0x0000001fff047819 */
/* 0x000fc60000011409 */
/*03f0*/ IMAD R7, R0, c[0x0][0x17c], R7 ; /* 0x00005f0000077a24 */
/* 0x000fe200078e0207 */
/*0400*/ IADD3 R2, P0, P1, R2, c[0x0][0x160], R9 ; /* 0x0000580002027a10 */
/* 0x000fc8000791e009 */
/*0410*/ IADD3 R3, R3, R7, RZ ; /* 0x0000000703037210 */
/* 0x000fc80007ffe0ff */
/*0420*/ IADD3.X R3, R3, c[0x0][0x164], R4, P0, P1 ; /* 0x0000590003037a10 */
/* 0x000fca00007e2404 */
/*0430*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1100 */
/*0440*/ I2F.U16 R4, R2 ; /* 0x0000000200047306 */
/* 0x004e240000101000 */
/*0450*/ FSETP.GE.AND P0, PT, R4, c[0x0][0x18c], PT ; /* 0x0000630004007a0b */
/* 0x001fda0003f06000 */
/*0460*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0470*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0480*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x000fe200078e0205 */
/*0490*/ HFMA2.MMA R5, -RZ, RZ, 1.984375, 0 ; /* 0x3ff00000ff057435 */
/* 0x000fe200000001ff */
/*04a0*/ MOV R4, 0x0 ; /* 0x0000000000047802 */
/* 0x000fce0000000f00 */
/*04b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*04c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.globl _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.p2align 8
.type _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif,@function
_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s9, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x20
v_cvt_f32_i32_e32 v3, v1
v_cvt_f32_i32_e32 v2, v0
s_waitcnt lgkmcnt(0)
s_load_b128 s[4:7], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_subrev_f32 v4, s5, v3 :: v_dual_subrev_f32 v7, s4, v2
v_sub_f32_e64 v5, s6, s4
v_sub_f32_e64 v6, s7, s5
v_mul_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, v6, v7, -v4
v_cmp_le_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[10:11], s[2:3], 0x10
v_dual_subrev_f32 v4, s7, v3 :: v_dual_subrev_f32 v7, s6, v2
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v5, s10, s6
v_sub_f32_e64 v6, s11, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v4, v5
v_fma_f32 v4, v7, v6, -v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[2:3], 0x18
v_dual_subrev_f32 v4, s11, v3 :: v_dual_subrev_f32 v7, s10, v2
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v5, s2, s10
v_sub_f32_e64 v6, s3, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v4, v5
v_fma_f32 v4, v7, v6, -v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_f32_e32 vcc_lo, 0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
v_dual_subrev_f32 v3, s3, v3 :: v_dual_subrev_f32 v2, s2, v2
v_sub_f32_e64 v4, s4, s2
v_sub_f32_e64 v5, s5, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v4
v_fma_f32 v2, v5, v2, -v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_f32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x28
v_ashrrev_i32_e32 v4, 31, v1
v_lshlrev_b32_e32 v6, 2, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s4, s[2:3]
v_mul_lo_u32 v5, v1, s5
v_mul_lo_u32 v4, v4, s4
s_ashr_i32 s2, s6, 31
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v6
v_add3_u32 v3, v4, v3, v5
v_ashrrev_i32_e32 v4, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s2, v3, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v2, v2
v_cmp_le_f32_e32 vcc_lo, s7, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x3ff00000
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, .Lfunc_end0-_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000e054c_00000000-6_KtexFillRect.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if
.type _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if, @function
_Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12KtexFillRectPvPdiimP6float2if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if, .-_Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if
.globl _Z12KtexFillRectPvPdiimP6float2if
.type _Z12KtexFillRectPvPdiimP6float2if, @function
_Z12KtexFillRectPvPdiimP6float2if:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z12KtexFillRectPvPdiimP6float2ifPvPdiimP6float2if
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12KtexFillRectPvPdiimP6float2if, .-_Z12KtexFillRectPvPdiimP6float2if
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12KtexFillRectPvPdiimP6float2if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12KtexFillRectPvPdiimP6float2if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl MaxThreadsY
.bss
.align 4
.type MaxThreadsY, @object
.size MaxThreadsY, 4
MaxThreadsY:
.zero 4
.globl MaxThreadsX
.align 4
.type MaxThreadsX, @object
.size MaxThreadsX, 4
MaxThreadsX:
.zero 4
.globl MaxThreadsPerBlock
.align 4
.type MaxThreadsPerBlock, @object
.size MaxThreadsPerBlock, 4
MaxThreadsPerBlock:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "KtexFillRect.hip"
.globl _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif # -- Begin function _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.p2align 4, 0x90
.type _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif,@function
_Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif: # @_Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, .Lfunc_end0-_Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type MaxThreadsPerBlock,@object # @MaxThreadsPerBlock
.bss
.globl MaxThreadsPerBlock
.p2align 2, 0x0
MaxThreadsPerBlock:
.long 0 # 0x0
.size MaxThreadsPerBlock, 4
.type MaxThreadsX,@object # @MaxThreadsX
.globl MaxThreadsX
.p2align 2, 0x0
MaxThreadsX:
.long 0 # 0x0
.size MaxThreadsX, 4
.type MaxThreadsY,@object # @MaxThreadsY
.globl MaxThreadsY
.p2align 2, 0x0
MaxThreadsY:
.long 0 # 0x0
.size MaxThreadsY, 4
.type _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif,@object # @_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.section .rodata,"a",@progbits
.globl _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.p2align 3, 0x0
_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif:
.quad _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.size _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12KtexFillRectPvPdiimP15HIP_vector_typeIfLj2EEif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 64
#define MAX_ERR 1e-6
__global__ void vector_add(float *out, float *a, float *b, int power) {
//int stride = 1;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
//out[tid] = a[tid] + b[tid];
float golden = 1.61803398875;
float golden_to_power = pow(golden,power);
float golden_minus_one_to_power = pow((1 - golden),power);
out[tid] = golden_to_power - golden_minus_one_to_power;
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate host memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Allocate device memory
cudaMalloc((void**)&d_a, sizeof(float) * N);
cudaMalloc((void**)&d_b, sizeof(float) * N);
cudaMalloc((void**)&d_out, sizeof(float) * N);
// Executing kernel
int power = 100;
vector_add<<<1,1>>>(d_out, d_a, d_b, power);
// Transfer data back to host memory
cudaMemcpy(out, d_out, sizeof(float) * N, cudaMemcpyDeviceToHost);
float result = out[0]/2.23606797749979;
printf("out[0] = %lF\n", result);
//printf("PASSED\n");
// Deallocate device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
}
|
code for sm_80
Function : _Z10vector_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64 R2, c[0x0][0x178] ; /* 0x00005e0000027b12 */
/* 0x000e220000201c00 */
/*0020*/ UMOV UR5, 0xa0000000 ; /* 0xa000000000057882 */
/* 0x000fe40000000000 */
/*0030*/ UMOV UR6, 0x3ff9e377 ; /* 0x3ff9e37700067882 */
/* 0x000fe20000000000 */
/*0040*/ LOP3.LUT R0, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003007812 */
/* 0x001fe200078ec0ff */
/*0050*/ IMAD.MOV.U32 R26, RZ, RZ, R2 ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e0002 */
/*0060*/ IMAD.MOV.U32 R27, RZ, RZ, R3 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0003 */
/*0070*/ LEA.HI R5, R0, 0xfffffc0c, RZ, 0xc ; /* 0xfffffc0c00057811 */
/* 0x000fc800078f60ff */
/*0080*/ SHF.L.U32 R0, R2.reuse, R5.reuse, RZ ; /* 0x0000000502007219 */
/* 0x0c0fe400000006ff */
/*0090*/ SHF.L.U64.HI R5, R2, R5, R3 ; /* 0x0000000502057219 */
/* 0x000fe40000010203 */
/*00a0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*00b0*/ MOV R0, 0xe0 ; /* 0x000000e000007802 */
/* 0x000fe40000000f00 */
/*00c0*/ ISETP.NE.AND.EX P0, PT, R5, -0x80000000, PT, P0 ; /* 0x800000000500780c */
/* 0x000fd00003f05300 */
/*00d0*/ CALL.REL.NOINC 0x490 ; /* 0x000003b000007944 */
/* 0x000fea0003c00000 */
/*00e0*/ DADD R4, R2, c[0x2][0x0] ; /* 0x0080000002047629 */
/* 0x000e140000000000 */
/*00f0*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x001fe200078ec0ff */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000f */
/*0110*/ ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fe20003f25270 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fd800078e000e */
/*0130*/ @P1 BRA 0x1f0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0140*/ DSETP.GTU.AND P1, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e1c0003f2c200 */
/*0150*/ @P1 BRA 0x1e0 ; /* 0x0000008000001947 */
/* 0x001fea0003800000 */
/*0160*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0170*/ LOP3.LUT R0, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03007812 */
/* 0x000fc800078ec0ff */
/*0180*/ ISETP.EQ.AND P1, PT, R0, 0x7ff00000, !P1 ; /* 0x7ff000000000780c */
/* 0x000fda0004f22270 */
/*0190*/ @!P1 BRA 0x1f0 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f26270 */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*01c0*/ SEL R5, RZ, 0x7ff00000, !P1 ; /* 0x7ff00000ff057807 */
/* 0x000fe20004800000 */
/*01d0*/ BRA 0x1f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*01e0*/ DADD R4, R2, c[0x2][0x0] ; /* 0x0080000002047629 */
/* 0x0000480000000000 */
/*01f0*/ IMAD.MOV.U32 R26, RZ, RZ, R2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0002 */
/*0200*/ MOV R0, 0x250 ; /* 0x0000025000007802 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R27, RZ, RZ, R3 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0003 */
/*0220*/ UMOV UR5, 0x40000000 ; /* 0x4000000000057882 */
/* 0x000fe40000000000 */
/*0230*/ UMOV UR6, 0x3fe3c6ef ; /* 0x3fe3c6ef00067882 */
/* 0x000fe40000000000 */
/*0240*/ CALL.REL.NOINC 0x490 ; /* 0x0000024000007944 */
/* 0x003fea0003c00000 */
/*0250*/ FRND.F64.TRUNC R6, R2 ; /* 0x0000000200067313 */
/* 0x000e22000030d800 */
/*0260*/ DADD R8, R2, c[0x2][0x8] ; /* 0x0080020002087629 */
/* 0x000e620000000000 */
/*0270*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0280*/ LOP3.LUT R8, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009087812 */
/* 0x002fc800078ec0ff */
/*0290*/ ISETP.NE.AND P2, PT, R8, 0x7ff00000, PT ; /* 0x7ff000000800780c */
/* 0x000fe20003f45270 */
/*02a0*/ DSETP.NEU.AND P1, PT, R6, R2, PT ; /* 0x000000020600722a */
/* 0x0010640003f2d000 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x001fe400078e000f */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fc600078e000e */
/*02d0*/ @!P0 LOP3.LUT R9, R7, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000007098812 */
/* 0x000fca00078e3cff */
/*02e0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff078224 */
/* 0x000fe400078e0009 */
/*02f0*/ @P1 IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff061424 */
/* 0x002fe400078e00ff */
/*0300*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, -0x80000 ; /* 0xfff80000ff071424 */
/* 0x000fe200078e00ff */
/*0310*/ @P2 BRA 0x3d0 ; /* 0x000000b000002947 */
/* 0x000fea0003800000 */
/*0320*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e1c0003f0c200 */
/*0330*/ @P0 BRA 0x3c0 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0350*/ LOP3.LUT R0, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03007812 */
/* 0x000fc800078ec0ff */
/*0360*/ ISETP.EQ.AND P0, PT, R0, 0x7ff00000, !P0 ; /* 0x7ff000000000780c */
/* 0x000fda0004702270 */
/*0370*/ @!P0 BRA 0x3d0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0380*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe20000011403 */
/*0390*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*03a0*/ LOP3.LUT R7, R2, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000002077812 */
/* 0x000fe200078ec0ff */
/*03b0*/ BRA 0x3d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*03c0*/ DADD R6, R2, c[0x2][0x8] ; /* 0x0080020002067629 */
/* 0x0000520000000000 */
/*03d0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x001e220000002500 */
/*03e0*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x002fe20000301000 */
/*03f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*0400*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0410*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e2a0000002100 */
/*0420*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x000e640000301000 */
/*0430*/ FADD R0, -R6, R5 ; /* 0x0000000506007221 */
/* 0x002fc40000000100 */
/*0440*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc600078e0203 */
/*0450*/ FSEL R9, R0, RZ, P0 ; /* 0x000000ff00097208 */
/* 0x000fe20000000000 */
/*0460*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e020b */
/*0470*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ USHF.R.U32.HI UR4, URZ, 0x14, UR6 ; /* 0x000000143f047899 */
/* 0x000fe20008011606 */
/*04a0*/ IMAD.U32 R6, RZ, RZ, UR5 ; /* 0x00000005ff067e24 */
/* 0x000fe4000f8e00ff */
/*04b0*/ IMAD.U32 R7, RZ, RZ, UR6 ; /* 0x00000006ff077e24 */
/* 0x000fe4000f8e00ff */
/*04c0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*04d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*04e0*/ IMAD.U32 R12, RZ, RZ, UR5 ; /* 0x00000005ff0c7e24 */
/* 0x000fe4000f8e00ff */
/*04f0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fc400078e00ff */
/*0500*/ IMAD.MOV.U32 R18, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff127424 */
/* 0x000fe400078e00ff */
/*0510*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff137424 */
/* 0x000fcc00078e00ff */
/*0520*/ @!P1 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006069828 */
/* 0x000e140000000000 */
/*0530*/ @!P1 IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff089224 */
/* 0x001fe400078e0007 */
/*0540*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c9224 */
/* 0x000fc600078e0006 */
/*0550*/ LOP3.LUT R8, R8, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff08087812 */
/* 0x000fc800078ec0ff */
/*0560*/ LOP3.LUT R13, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff00000080d7812 */
/* 0x000fc800078efcff */
/*0570*/ ISETP.GE.U32.AND P2, PT, R13, 0x3ff6a09f, PT ; /* 0x3ff6a09f0d00780c */
/* 0x000fda0003f46070 */
/*0580*/ @P2 IADD3 R9, R13, -0x100000, RZ ; /* 0xfff000000d092810 */
/* 0x000fca0007ffe0ff */
/*0590*/ @P2 IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d2224 */
/* 0x000fcc00078e0009 */
/*05a0*/ DADD R10, R12, 1 ; /* 0x3ff000000c0a7429 */
/* 0x000e080000000000 */
/*05b0*/ DADD R12, R12, -1 ; /* 0xbff000000c0c7429 */
/* 0x000fe40000000000 */
/*05c0*/ MUFU.RCP64H R17, R11 ; /* 0x0000000b00117308 */
/* 0x001e240000001800 */
/*05d0*/ DFMA R8, -R10, R16, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000110 */
/*05e0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*05f0*/ DFMA R16, R16, R8, R16 ; /* 0x000000081010722b */
/* 0x001e0c0000000010 */
/*0600*/ DMUL R8, R16, R12 ; /* 0x0000000c10087228 */
/* 0x001e0c0000000000 */
/*0610*/ DFMA R8, R16, R12, R8 ; /* 0x0000000c1008722b */
/* 0x001e0c0000000008 */
/*0620*/ DMUL R14, R8, R8 ; /* 0x00000008080e7228 */
/* 0x001e080000000000 */
/*0630*/ DADD R10, R12, -R8 ; /* 0x000000000c0a7229 */
/* 0x000e480000000808 */
/*0640*/ DFMA R18, R14, R18, c[0x2][0x10] ; /* 0x008004000e12762b */
/* 0x001e080000000012 */
/*0650*/ DADD R20, R10, R10 ; /* 0x000000000a147229 */
/* 0x002e48000000000a */
/*0660*/ DFMA R18, R14, R18, c[0x2][0x18] ; /* 0x008006000e12762b */
/* 0x001e080000000012 */
/*0670*/ DFMA R20, R12, -R8, R20 ; /* 0x800000080c14722b */
/* 0x002fc80000000014 */
/*0680*/ DFMA R18, R14, R18, c[0x2][0x20] ; /* 0x008008000e12762b */
/* 0x001e080000000012 */
/*0690*/ DMUL R12, R8, R8 ; /* 0x00000008080c7228 */
/* 0x000fc80000000000 */
/*06a0*/ DFMA R18, R14, R18, c[0x2][0x28] ; /* 0x00800a000e12762b */
/* 0x001e080000000012 */
/*06b0*/ DMUL R16, R16, R20 ; /* 0x0000001410107228 */
/* 0x000fc80000000000 */
/*06c0*/ DFMA R18, R14, R18, c[0x2][0x30] ; /* 0x00800c000e12762b */
/* 0x001e0c0000000012 */
/*06d0*/ DFMA R18, R14, R18, c[0x2][0x38] ; /* 0x00800e000e12762b */
/* 0x001e220000000012 */
/*06e0*/ IADD3 R25, R17, 0x100000, RZ ; /* 0x0010000011197810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R24, RZ, RZ, R16 ; /* 0x000000ffff187224 */
/* 0x000fc800078e0010 */
/*0700*/ DFMA R10, R14, R18, c[0x2][0x40] ; /* 0x008010000e0a762b */
/* 0x001e0c0000000012 */
/*0710*/ DADD R22, -R10, c[0x2][0x40] ; /* 0x008010000a167629 */
/* 0x001e0c0000000100 */
/*0720*/ DFMA R22, R14, R18, R22 ; /* 0x000000120e16722b */
/* 0x001e080000000016 */
/*0730*/ DMUL R14, R8, R12 ; /* 0x0000000c080e7228 */
/* 0x000e480000000000 */
/*0740*/ DADD R22, RZ, R22 ; /* 0x00000000ff167229 */
/* 0x001e080000000016 */
/*0750*/ DFMA R18, R8, R8, -R12 ; /* 0x000000080812722b */
/* 0x000fc8000000080c */
/*0760*/ DFMA R20, R8, R12, -R14 ; /* 0x0000000c0814722b */
/* 0x002e48000000080e */
/*0770*/ DADD R22, R22, c[0x2][0x48] ; /* 0x0080120016167629 */
/* 0x001e080000000000 */
/*0780*/ DFMA R20, R16, R12, R20 ; /* 0x0000000c1014722b */
/* 0x002fc80000000014 */
/*0790*/ DFMA R18, R8, R24, R18 ; /* 0x000000180812722b */
/* 0x000e480000000012 */
/*07a0*/ DADD R12, R10, R22 ; /* 0x000000000a0c7229 */
/* 0x001e080000000016 */
/*07b0*/ DFMA R20, R8, R18, R20 ; /* 0x000000120814722b */
/* 0x002fc80000000014 */
/*07c0*/ DADD R18, R10, -R12 ; /* 0x000000000a127229 */
/* 0x001e08000000080c */
/*07d0*/ DMUL R10, R12, R14 ; /* 0x0000000e0c0a7228 */
/* 0x000e480000000000 */
/*07e0*/ DADD R22, R22, R18 ; /* 0x0000000016167229 */
/* 0x001fc80000000012 */
/*07f0*/ DFMA R18, R12, R14, -R10 ; /* 0x0000000e0c12722b */
/* 0x002e0c000000080a */
/*0800*/ DFMA R18, R12, R20, R18 ; /* 0x000000140c12722b */
/* 0x001e0c0000000012 */
/*0810*/ DFMA R22, R22, R14, R18 ; /* 0x0000000e1616722b */
/* 0x0010640000000012 */
/*0820*/ IMAD.U32 R18, RZ, RZ, UR4 ; /* 0x00000004ff127e24 */
/* 0x001fe2000f8e00ff */
/*0830*/ @!P1 LEA.HI R18, R7, 0xffffffca, RZ, 0xc ; /* 0xffffffca07129811 */
/* 0x000fe200078f60ff */
/*0840*/ IMAD.MOV.U32 R7, RZ, RZ, 0x43300000 ; /* 0x43300000ff077424 */
/* 0x000fe400078e00ff */
/*0850*/ DADD R14, R10, R22 ; /* 0x000000000a0e7229 */
/* 0x002e220000000016 */
/*0860*/ IADD3 R6, R18.reuse, -0x3ff, RZ ; /* 0xfffffc0112067810 */
/* 0x040fe20007ffe0ff */
/*0870*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fe200078e00ff */
/*0880*/ @P2 IADD3 R6, R18, -0x3fe, RZ ; /* 0xfffffc0212062810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x000fc400078e00ff */
/*08a0*/ DADD R12, R8, R14 ; /* 0x00000000080c7229 */
/* 0x001e22000000000e */
/*08b0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000006067812 */
/* 0x000fc600078e3cff */
/*08c0*/ DADD R10, R10, -R14 ; /* 0x000000000a0a7229 */
/* 0x000e48000000080e */
/*08d0*/ DADD R8, R8, -R12 ; /* 0x0000000008087229 */
/* 0x001e08000000080c */
/*08e0*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x002fc8000000000a */
/*08f0*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0c0000000008 */
/*0900*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e0c0000000008 */
/*0910*/ DADD R16, R16, R8 ; /* 0x0000000010107229 */
/* 0x001e080000000008 */
/*0920*/ DADD R8, R6, c[0x2][0x50] ; /* 0x0080140006087629 */
/* 0x000fc80000000000 */
/*0930*/ DADD R10, R12, R16 ; /* 0x000000000c0a7229 */
/* 0x001e0c0000000010 */
/*0940*/ DFMA R6, R8, c[0x2][0x58], R10 ; /* 0x0080160008067a2b */
/* 0x001e08000000000a */
/*0950*/ DADD R12, R12, -R10 ; /* 0x000000000c0c7229 */
/* 0x000e48000000080a */
/*0960*/ DFMA R14, -R8, c[0x2][0x58], R6 ; /* 0x00801600080e7a2b */
/* 0x001e080000000106 */
/*0970*/ DADD R12, R16, R12 ; /* 0x00000000100c7229 */
/* 0x002fc8000000000c */
/*0980*/ DADD R14, -R10, R14 ; /* 0x000000000a0e7229 */
/* 0x001064000000010e */
/*0990*/ IMAD.SHL.U32 R10, R27, 0x2, RZ ; /* 0x000000021b0a7824 */
/* 0x001fc800078e00ff */
/*09a0*/ DADD R12, R12, -R14 ; /* 0x000000000c0c7229 */
/* 0x002062000000080e */
/*09b0*/ ISETP.GT.U32.AND P1, PT, R10, -0x2000001, PT ; /* 0xfdffffff0a00780c */
/* 0x000fe20003f24070 */
/*09c0*/ IMAD.MOV.U32 R14, RZ, RZ, R26 ; /* 0x000000ffff0e7224 */
/* 0x001fe200078e001a */
/*09d0*/ LOP3.LUT R15, R27, 0xff0fffff, RZ, 0xc0, !PT ; /* 0xff0fffff1b0f7812 */
/* 0x000fc600078ec0ff */
/*09e0*/ DFMA R12, R8, c[0x2][0x60], R12 ; /* 0x00801800080c7a2b */
/* 0x002e22000000000c */
/*09f0*/ SEL R15, R15, R27, P1 ; /* 0x0000001b0f0f7207 */
/* 0x000fca0000800000 */
/*0a00*/ DADD R8, R6, R12 ; /* 0x0000000006087229 */
/* 0x001e0c000000000c */
/*0a10*/ DADD R10, R6, -R8 ; /* 0x00000000060a7229 */
/* 0x001e080000000808 */
/*0a20*/ DMUL R6, R8, R14 ; /* 0x0000000e08067228 */
/* 0x000e480000000000 */
/*0a30*/ DADD R10, R12, R10 ; /* 0x000000000c0a7229 */
/* 0x0011e4000000000a */
/*0a40*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*0a50*/ DFMA R8, R8, R14, -R6 ; /* 0x0000000e0808722b */
/* 0x002e220000000806 */
/*0a60*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fca00078e00ff */
/*0a70*/ DFMA R8, R10, R14, R8 ; /* 0x0000000e0a08722b */
/* 0x001e0c0000000008 */
/*0a80*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x001e0c0000000008 */
/*0a90*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*0aa0*/ FSETP.GEU.AND P1, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f2e200 */
/*0ab0*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*0ac0*/ DFMA R16, R14, c[0x2][0x68], R10 ; /* 0x00801a000e107a2b */
/* 0x001e0c000000000a */
/*0ad0*/ DFMA R14, R14, c[0x2][0x70], R16 ; /* 0x00801c000e0e7a2b */
/* 0x001e0c0000000010 */
/*0ae0*/ DFMA R16, R14, R18, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000012 */
/*0af0*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0b00*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*0b10*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*0b20*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*0b30*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*0b40*/ DFMA R16, R14, R16, c[0x2][0xa8] ; /* 0x00802a000e10762b */
/* 0x001e0c0000000010 */
/*0b50*/ DFMA R16, R14, R16, c[0x2][0xb0] ; /* 0x00802c000e10762b */
/* 0x001e0c0000000010 */
/*0b60*/ DFMA R16, R14, R16, c[0x2][0xb8] ; /* 0x00802e000e10762b */
/* 0x001e0c0000000010 */
/*0b70*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0b80*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*0b90*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*0ba0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*0bb0*/ @!P1 BRA 0xca0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0bc0*/ FSETP.GEU.AND P2, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f4e200 */
/*0bd0*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*0be0*/ DSETP.GEU.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f2e000 */
/*0bf0*/ FSEL R14, R14, RZ, P1 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000800000 */
/*0c00*/ FSEL R15, R15, RZ, P1 ; /* 0x000000ff0f0f7208 */
/* 0x000fe20000800000 */
/*0c10*/ @P2 BRA 0xca0 ; /* 0x0000008000002947 */
/* 0x000fea0003800000 */
/*0c20*/ LEA.HI R13, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0d7211 */
/* 0x000fe200078f08ff */
/*0c30*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0010 */
/*0c40*/ SHF.R.S32.HI R13, RZ, 0x1, R13 ; /* 0x00000001ff0d7819 */
/* 0x000fca000001140d */
/*0c50*/ IMAD.IADD R12, R12, 0x1, -R13 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0a0d */
/*0c60*/ IMAD R15, R13, 0x100000, R17 ; /* 0x001000000d0f7824 */
/* 0x000fc600078e0211 */
/*0c70*/ LEA R13, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c0d7811 */
/* 0x000fe200078ea0ff */
/*0c80*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fcc00078e00ff */
/*0c90*/ DMUL R14, R14, R12 ; /* 0x0000000c0e0e7228 */
/* 0x0000540000000000 */
/*0ca0*/ LOP3.LUT R12, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f0c7812 */
/* 0x003fe200078ec0ff */
/*0cb0*/ DADD R6, R6, -R10 ; /* 0x0000000006067229 */
/* 0x000e06000000080a */
/*0cc0*/ ISETP.NE.AND P1, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fc60003f25270 */
/*0cd0*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x001e220000000006 */
/*0ce0*/ ISETP.EQ.AND P1, PT, R14, RZ, !P1 ; /* 0x000000ff0e00720c */
/* 0x000fda0004f22270 */
/*0cf0*/ @!P1 DFMA R14, R6, R14, R14 ; /* 0x0000000e060e922b */
/* 0x001064000000000e */
/*0d00*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0000 */
/*0d10*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0d20*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff2d006007950 */
/* 0x002fea0003c3ffff */
/*0d30*/ BRA 0xd30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 64
#define MAX_ERR 1e-6
__global__ void vector_add(float *out, float *a, float *b, int power) {
//int stride = 1;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
//out[tid] = a[tid] + b[tid];
float golden = 1.61803398875;
float golden_to_power = pow(golden,power);
float golden_minus_one_to_power = pow((1 - golden),power);
out[tid] = golden_to_power - golden_minus_one_to_power;
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate host memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Allocate device memory
cudaMalloc((void**)&d_a, sizeof(float) * N);
cudaMalloc((void**)&d_b, sizeof(float) * N);
cudaMalloc((void**)&d_out, sizeof(float) * N);
// Executing kernel
int power = 100;
vector_add<<<1,1>>>(d_out, d_a, d_b, power);
// Transfer data back to host memory
cudaMemcpy(out, d_out, sizeof(float) * N, cudaMemcpyDeviceToHost);
float result = out[0]/2.23606797749979;
printf("out[0] = %lF\n", result);
//printf("PASSED\n");
// Deallocate device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
}
|
.file "tmpxft_00049b51_00000000-6_vector_add_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "out[0] = %lF\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
divsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $100, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1684540248
.long 1073865591
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define N 64
#define MAX_ERR 1e-6
__global__ void vector_add(float *out, float *a, float *b, int power) {
//int stride = 1;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
//out[tid] = a[tid] + b[tid];
float golden = 1.61803398875;
float golden_to_power = pow(golden,power);
float golden_minus_one_to_power = pow((1 - golden),power);
out[tid] = golden_to_power - golden_minus_one_to_power;
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate host memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Allocate device memory
cudaMalloc((void**)&d_a, sizeof(float) * N);
cudaMalloc((void**)&d_b, sizeof(float) * N);
cudaMalloc((void**)&d_out, sizeof(float) * N);
// Executing kernel
int power = 100;
vector_add<<<1,1>>>(d_out, d_a, d_b, power);
// Transfer data back to host memory
cudaMemcpy(out, d_out, sizeof(float) * N, cudaMemcpyDeviceToHost);
float result = out[0]/2.23606797749979;
printf("out[0] = %lF\n", result);
//printf("PASSED\n");
// Deallocate device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
}
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 64
#define MAX_ERR 1e-6
__global__ void vector_add(float *out, float *a, float *b, int power) {
//int stride = 1;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
//out[tid] = a[tid] + b[tid];
float golden = 1.61803398875;
float golden_to_power = pow(golden,power);
float golden_minus_one_to_power = pow((1 - golden),power);
out[tid] = golden_to_power - golden_minus_one_to_power;
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate host memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Allocate device memory
hipMalloc((void**)&d_a, sizeof(float) * N);
hipMalloc((void**)&d_b, sizeof(float) * N);
hipMalloc((void**)&d_out, sizeof(float) * N);
// Executing kernel
int power = 100;
vector_add<<<1,1>>>(d_out, d_a, d_b, power);
// Transfer data back to host memory
hipMemcpy(out, d_out, sizeof(float) * N, hipMemcpyDeviceToHost);
float result = out[0]/2.23606797749979;
printf("out[0] = %lF\n", result);
//printf("PASSED\n");
// Deallocate device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 64
#define MAX_ERR 1e-6
__global__ void vector_add(float *out, float *a, float *b, int power) {
//int stride = 1;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
//out[tid] = a[tid] + b[tid];
float golden = 1.61803398875;
float golden_to_power = pow(golden,power);
float golden_minus_one_to_power = pow((1 - golden),power);
out[tid] = golden_to_power - golden_minus_one_to_power;
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate host memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Allocate device memory
hipMalloc((void**)&d_a, sizeof(float) * N);
hipMalloc((void**)&d_b, sizeof(float) * N);
hipMalloc((void**)&d_out, sizeof(float) * N);
// Executing kernel
int power = 100;
vector_add<<<1,1>>>(d_out, d_a, d_b, power);
// Transfer data back to host memory
hipMemcpy(out, d_out, sizeof(float) * N, hipMemcpyDeviceToHost);
float result = out[0]/2.23606797749979;
printf("out[0] = %lF\n", result);
//printf("PASSED\n");
// Deallocate device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10vector_addPfS_S_i
.globl _Z10vector_addPfS_S_i
.p2align 8
.type _Z10vector_addPfS_S_i,@function
_Z10vector_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_mov_b32 s5, 0x3e76c4e1
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_cmp_eq_u32 s3, 0
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0x3fcf1bbd, 1.0, s2
v_cndmask_b32_e64 v2, 0x3f1e377a, 1.0, s2
v_frexp_mant_f32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_frexp_mant_f32_e32 v4, v2
v_frexp_exp_i32_f32_e32 v1, v1
v_frexp_exp_i32_f32_e32 v2, v2
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v4
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
v_cndmask_b32_e64 v6, 0, 1, s2
v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_subrev_co_ci_u32_e64 v2, vcc_lo, 0, v2, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ldexp_f32 v3, v3, v5
v_ldexp_f32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f32_i32_e32 v1, v1
v_cvt_f32_i32_e32 v2, v2
s_and_b32 s2, s3, 0xffff0000
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v5, 1.0, v3 :: v_dual_add_f32 v6, 1.0, v4
v_dual_add_f32 v9, -1.0, v3 :: v_dual_add_f32 v10, -1.0, v4
v_rcp_f32_e32 v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v11, v9, v7 :: v_dual_mul_f32 v12, v10, v8
v_add_f32_e32 v13, -1.0, v5
v_dual_add_f32 v15, -1.0, v6 :: v_dual_mul_f32 v14, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v16, v6, v12 :: v_dual_sub_f32 v3, v3, v13
v_sub_f32_e32 v4, v4, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v5, v11, v5, -v14
v_fma_f32 v6, v12, v6, -v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v5, v11, v3 :: v_dual_fmac_f32 v6, v12, v4
v_dual_add_f32 v3, v14, v5 :: v_dual_add_f32 v4, v16, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v13, v9, v3 :: v_dual_sub_f32 v14, v3, v14
v_sub_f32_e32 v16, v4, v16
v_sub_f32_e32 v15, v10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_sub_f32 v9, v9, v13 :: v_dual_sub_f32 v6, v16, v6
v_sub_f32_e32 v5, v14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v9, v3
v_add_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v13, v3
v_mul_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v11, v3
v_dual_sub_f32 v10, v10, v15 :: v_dual_mul_f32 v9, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v10, v4
v_add_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v15, v4
v_mul_f32_e32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v12, v4
v_dual_sub_f32 v8, v6, v12 :: v_dual_sub_f32 v7, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v4, v4, v8 :: v_dual_sub_f32 v3, v3, v7
v_fma_f32 v8, v5, v5, -v9
v_dual_add_f32 v12, v4, v4 :: v_dual_mul_f32 v7, v6, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, v3, v3
v_fma_f32 v11, v6, v6, -v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v8, v5, v10 :: v_dual_fmac_f32 v11, v6, v12
v_add_f32_e32 v12, v7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v10, v9, v8 :: v_dual_sub_f32 v7, v12, v7
v_dual_fmaak_f32 v13, s5, v10, 0x3e91f4c4 :: v_dual_fmaak_f32 v14, s5, v12, 0x3e91f4c4
v_sub_f32_e32 v9, v10, v9
s_and_b32 s5, s3, 0xffff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v11, v7
v_dual_fmaak_f32 v13, v10, v13, 0x3ecccdef :: v_dual_fmaak_f32 v14, v12, v14, 0x3ecccdef
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v8, v9
s_bitcmp0_b32 s3, 0
v_dual_mul_f32 v15, v10, v13 :: v_dual_mul_f32 v16, v12, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, v10, v13, -v15
v_fma_f32 v11, v12, v14, -v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v8, v13
v_dual_fmac_f32 v11, v7, v14 :: v_dual_mul_f32 v14, v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v13, v5, v10 :: v_dual_add_f32 v18, v16, v11
v_add_f32_e32 v17, v15, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v20, v12, v6, -v14
v_fma_f32 v19, v10, v5, -v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v22, 0x3f2aaaaa, v18 :: v_dual_add_f32 v21, 0x3f2aaaaa, v17
v_dual_fmac_f32 v20, v12, v4 :: v_dual_sub_f32 v15, v17, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v19, v10, v3
v_sub_f32_e32 v16, v18, v16
v_add_f32_e32 v10, 0xbf2aaaaa, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v20, v7, v6 :: v_dual_sub_f32 v9, v9, v15
v_add_f32_e32 v15, 0xbf2aaaaa, v22
v_dual_sub_f32 v11, v11, v16 :: v_dual_sub_f32 v10, v17, v10
v_ldexp_f32 v6, v6, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v9, 0x31739010, v9 :: v_dual_sub_f32 v12, v18, v15
v_ldexp_f32 v4, v4, 1
v_ldexp_f32 v3, v3, 1
v_add_f32_e32 v7, v9, v10
v_dual_fmac_f32 v19, v8, v5 :: v_dual_add_f32 v10, v14, v20
v_ldexp_f32 v5, v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v9, v13, v19 :: v_dual_sub_f32 v14, v10, v14
v_add_f32_e32 v11, 0x31739010, v11
v_dual_sub_f32 v13, v9, v13 :: v_dual_sub_f32 v14, v20, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v11, v12
v_add_f32_e32 v11, v22, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v15, v22, v11
v_add_f32_e32 v8, v8, v15
v_mul_f32_e32 v16, v10, v11
v_add_f32_e32 v12, v21, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, v10, v11, -v16
v_sub_f32_e32 v17, v21, v12
v_mul_f32_e32 v18, v9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v15, v10, v8
v_add_f32_e32 v7, v7, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v17, v9, v12, -v18
v_dual_sub_f32 v8, v19, v13 :: v_dual_fmac_f32 v15, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v9, v7
v_fmac_f32_e32 v17, v8, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v9, v16, v15 :: v_dual_mul_f32 v8, 0x3f317218, v2
v_add_f32_e32 v10, v18, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v6, v9
v_dual_mul_f32 v7, 0x3f317218, v1 :: v_dual_add_f32 v14, v5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v12, v6 :: v_dual_sub_f32 v5, v14, v5
v_dual_sub_f32 v6, v9, v6 :: v_dual_sub_f32 v5, v10, v5
v_dual_sub_f32 v13, v9, v16 :: v_dual_sub_f32 v16, v10, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v1, 0x3f317218, -v7
v_sub_f32_e32 v13, v15, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_f32_e32 v15, v17, v16
v_fma_f32 v16, v2, 0x3f317218, -v8
v_fmac_f32_e32 v11, 0xb102e308, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v4, v4, v13 :: v_dual_add_f32 v3, v3, v15
v_fmac_f32_e32 v16, 0xb102e308, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v1, v4, v6
v_add_f32_e32 v4, v8, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v4, v8
v_add_f32_e32 v2, v3, v5
v_dual_add_f32 v3, v7, v11 :: v_dual_sub_f32 v8, v16, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v14, v2
v_add_f32_e32 v10, v3, v6
v_sub_f32_e32 v13, v6, v14
v_sub_f32_e32 v7, v3, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v14, v10, v3
v_sub_f32_e32 v2, v2, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v12, v1 :: v_dual_sub_f32 v6, v6, v14
v_dual_add_f32 v9, v4, v5 :: v_dual_sub_f32 v12, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v1, v1, v12
v_sub_f32_e32 v7, v11, v7
v_dual_sub_f32 v11, v9, v4 :: v_dual_add_f32 v12, v8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v15, v9, v11
v_sub_f32_e32 v4, v4, v15
v_sub_f32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v11, v7, v2 :: v_dual_add_f32 v4, v5, v4
v_dual_add_f32 v4, v12, v4 :: v_dual_sub_f32 v13, v10, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_add_f32 v14, v9, v4 :: v_dual_sub_f32 v3, v3, v13
v_cvt_f32_i32_e32 v13, s2
v_sub_f32_e32 v5, v11, v7
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v6, v3 :: v_dual_sub_f32 v6, v12, v8
v_sub_f32_e32 v12, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v1, v1, v6 :: v_dual_sub_f32 v6, v8, v12
v_sub_f32_e32 v8, v14, v9
v_dual_sub_f32 v2, v2, v5 :: v_dual_add_f32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v8
v_add_f32_e32 v1, v1, v4
v_add_f32_e32 v3, v11, v3
v_sub_f32_e32 v11, v11, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v4, v14, v1
v_add_f32_e32 v5, v10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v7, v7, v11 :: v_dual_sub_f32 v8, v4, v14
v_sub_f32_e32 v9, v5, v10
v_cvt_f32_i32_e32 v10, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v2, v2, v7 :: v_dual_sub_f32 v1, v1, v8
v_dual_sub_f32 v3, v3, v9 :: v_dual_add_f32 v6, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v2, v2, v3 :: v_dual_sub_f32 v3, v13, v6
v_mul_f32_e32 v9, v6, v4
v_add_f32_e32 v7, v5, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v3, v3, v10
v_cmp_class_f32_e64 vcc_lo, v9, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v5, v7, v5
v_mul_f32_e32 v10, v3, v4
v_mul_f32_e32 v8, v6, v7
v_mul_f32_e32 v3, v3, v7
v_fma_f32 v4, v6, v4, -v9
v_sub_f32_e32 v2, v2, v5
v_fmac_f32_e32 v10, v6, v1
v_fma_f32 v1, v6, v7, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v4, v4, v10
v_fmac_f32_e32 v3, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v1, v3
v_dual_add_f32 v1, v9, v4 :: v_dual_add_f32 v2, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v1, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v8, 0x204
v_dual_sub_f32 v9, v1, v9 :: v_dual_cndmask_b32 v6, v2, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v5
v_sub_f32_e32 v8, v2, v8
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_sub_f32_e32 v2, v4, v9
v_cndmask_b32_e64 v7, 0, 0x37000000, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v6
v_cndmask_b32_e64 v10, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v12, v6, v10
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v6|
v_mul_f32_e32 v14, 0x3fb8aa3b, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v7, v2
v_fma_f32 v17, v12, 0x3fb8aa3b, -v14
v_rndne_f32_e32 v18, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v17, 0x32a5705f, v12 :: v_dual_sub_f32 v14, v14, v18
v_dual_add_f32 v14, v14, v17 :: v_dual_sub_f32 v3, v3, v8
v_cvt_i32_f32_e32 v8, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v0, v14
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v10, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v0, v0, v8
v_sub_f32_e32 v11, v5, v7
v_cndmask_b32_e64 v5, 0xbf1e377a, 1.0, s2
v_mul_f32_e32 v13, 0x3fb8aa3b, v11
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v15, v11, 0x3fb8aa3b, -v13
v_rndne_f32_e32 v16, v13
v_fmac_f32_e32 v15, 0x32a5705f, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v13, v13, v16
v_cvt_i32_f32_e32 v4, v16
v_add_f32_e32 v13, v13, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v13, v13
s_waitcnt_depctr 0xfff
v_ldexp_f32 v4, v13, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0x7f800000, v4, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
v_fma_f32 v2, v4, v2, v4
v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v3, v0, v3, v0
v_cndmask_b32_e32 v4, v2, v4, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_bfi_b32 v4, 0x7fffffff, v4, v5
v_cndmask_b32_e32 v3, v3, v0, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e64 v2, |v3|, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10vector_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10vector_addPfS_S_i, .Lfunc_end0-_Z10vector_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10vector_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10vector_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 64
#define MAX_ERR 1e-6
__global__ void vector_add(float *out, float *a, float *b, int power) {
//int stride = 1;
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// 0 * 256 + 1 = 1 | BLOCK0 |
// 0 * 256 + 2 = 2
// 1 * 256 + 1 = 257 | BLOCK1 |
// 1 * 256 + 2 = 258
//out[tid] = a[tid] + b[tid];
float golden = 1.61803398875;
float golden_to_power = pow(golden,power);
float golden_minus_one_to_power = pow((1 - golden),power);
out[tid] = golden_to_power - golden_minus_one_to_power;
}
int main(){
float *a, *b, *out;
float *d_a, *d_b, *d_out;
// Allocate host memory
a = (float*)malloc(sizeof(float) * N);
b = (float*)malloc(sizeof(float) * N);
out = (float*)malloc(sizeof(float) * N);
// Allocate device memory
hipMalloc((void**)&d_a, sizeof(float) * N);
hipMalloc((void**)&d_b, sizeof(float) * N);
hipMalloc((void**)&d_out, sizeof(float) * N);
// Executing kernel
int power = 100;
vector_add<<<1,1>>>(d_out, d_a, d_b, power);
// Transfer data back to host memory
hipMemcpy(out, d_out, sizeof(float) * N, hipMemcpyDeviceToHost);
float result = out[0]/2.23606797749979;
printf("out[0] = %lF\n", result);
//printf("PASSED\n");
// Deallocate device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_out);
// Deallocate host memory
free(a);
free(b);
free(out);
}
|
.text
.file "vector_add_block.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4001e3779b97f4a8 # double 2.2360679774997898
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 24(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out[0] = %lF\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00049b51_00000000-6_vector_add_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.type _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, @function
_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i, .-_Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
.globl _Z10vector_addPfS_S_i
.type _Z10vector_addPfS_S_i, @function
_Z10vector_addPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPfS_S_i, .-_Z10vector_addPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "out[0] = %lF\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
divsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl $100, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z35__device_stub__Z10vector_addPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10vector_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1684540248
.long 1073865591
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vector_add_block.hip"
.globl _Z25__device_stub__vector_addPfS_S_i # -- Begin function _Z25__device_stub__vector_addPfS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPfS_S_i,@function
_Z25__device_stub__vector_addPfS_S_i: # @_Z25__device_stub__vector_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPfS_S_i, .Lfunc_end0-_Z25__device_stub__vector_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4001e3779b97f4a8 # double 2.2360679774997898
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 24(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10vector_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPfS_S_i,@object # @_Z10vector_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z10vector_addPfS_S_i
.p2align 3, 0x0
_Z10vector_addPfS_S_i:
.quad _Z25__device_stub__vector_addPfS_S_i
.size _Z10vector_addPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out[0] = %lF\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPfS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/
#include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024
void showResult(int m, int k, int *out);
// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
__shared__ int dist[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row;
int col;
int px;
int py;
for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
{
for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
{
row = by*TILE_WIDTH+py;
col = bx*TILE_WIDTH+px;
dist[py][px] = 0;
__syncthreads();
for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
{
for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
{
rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
}
for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
{
colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
}
__syncthreads();
for(int j=0; j<TILE_DEPTH; j++)
{
dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
}
__syncthreads();
}
D[row*m+col] = dist[py][px];
}
}
}
extern __shared__ int SMem[];
//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
int i = blockIdx.x;
int tid = threadIdx.x;
int s = blockDim.x/2;
int resultValue = INIT_MAX;
int resultIndex = INIT_MAX;
int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j+num == i)
{
SMem[j] = INIT_MAX;
}
else
{
SMem[j] = D[i*m+num+j];
}
//index
SMem[indexBase+j] = j+num;
__syncthreads();
}
if(tid < count)
{
if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
{
SMem[ out[i*k+tid]-num ] = INIT_MAX;
}
__syncthreads();
}
__syncthreads();
// for(s=indexBase/2; s>0; s>>=1)
for(s=indexBase/2; s>32; s>>=1)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j < s)
{
if(SMem[j] == SMem[j+s])
{
if(SMem[indexBase+j] > SMem[indexBase+j+s])
{
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
else if(SMem[j] > SMem[j+s])
{
SMem[j] = SMem[j+s];
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
__syncthreads();
}
}
/*
if(indexBase >= 1024)
{
if(tid < 512)
{
if(SMem[tid] == SMem[tid+512])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
{
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
else if(SMem[tid] > SMem[tid+512])
{
SMem[tid] = SMem[tid+512];
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
__syncthreads();
}
if(indexBase >= 512)
{
if(tid < 256)
{
if(SMem[tid] == SMem[tid+256])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
{
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
else if(SMem[tid] > SMem[tid+256])
{
SMem[tid] = SMem[tid+256];
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
__syncthreads();
}
if(indexBase >= 256)
{
if(tid < 128)
{
if(SMem[tid] == SMem[tid+128])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
{
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
else if(SMem[tid] > SMem[tid+128])
{
SMem[tid] = SMem[tid+128];
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
__syncthreads();
}
if(indexBase >= 128)
{
if(tid < 64)
{
if(SMem[tid] == SMem[tid+64])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
{
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
else if(SMem[tid] > SMem[tid+64])
{
SMem[tid] = SMem[tid+64];
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
__syncthreads();
}
*/
if(tid < 32)
{
/*
#pragma unroll 5
for(s=32; s>0; s>>=1)
{
if(SMem[tid] == SMem[tid+s])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
{
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
else if(SMem[tid] > SMem[tid+s])
{
SMem[tid] = SMem[tid+s];
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
*/
if(SMem[tid] == SMem[tid+32])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
{
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
}
else if(SMem[tid] > SMem[tid+32])
{
SMem[tid] = SMem[tid+32];
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
if(SMem[tid] == SMem[tid+16])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
{
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
}
else if(SMem[tid] > SMem[tid+16])
{
SMem[tid] = SMem[tid+16];
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
if(SMem[tid] == SMem[tid+8])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
{
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
}
else if(SMem[tid] > SMem[tid+8])
{
SMem[tid] = SMem[tid+8];
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
if(SMem[tid] == SMem[tid+4])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
{
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
}
else if(SMem[tid] > SMem[tid+4])
{
SMem[tid] = SMem[tid+4];
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
if(SMem[tid] == SMem[tid+2])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
{
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
}
else if(SMem[tid] > SMem[tid+2])
{
SMem[tid] = SMem[tid+2];
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
if(SMem[tid] == SMem[tid+1])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
{
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
else if(SMem[tid] > SMem[tid+1])
{
SMem[tid] = SMem[tid+1];
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
__syncthreads();
if(resultValue == SMem[0])
{
if(resultIndex > SMem[indexBase])
{
resultIndex = SMem[indexBase];
}
}
else if (resultValue > SMem[0])
{
resultValue = SMem[0];
resultIndex = SMem[indexBase];
}
__syncthreads();
}
return resultIndex;
}
// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
int i;
int count;
i = blockIdx.x;
__syncthreads();
for(count=0; count<k; count++)
{
out[i*k+count] = findMin(m, k, count, D, out);
__syncthreads();
}
}
void showResult(int m, int k, int *out)
{
int i,j;
for(i=0; i<m; i++)
{
for(j=0; j<k; j++)
{
printf("%d ", out[i*k+j]);
if(j == k-1)
{
printf("\n");
}
}
}
}
int main(int argc, char *argv[])
{
int m,n,k;
int i;
int *V, *out; //host copies
int *d_V, *d_out; //device copies
int *D;
FILE *fp;
if(argc != 2)
{
printf("Usage: knn <inputfile>\n");
exit(1);
}
if((fp = fopen(argv[1], "r")) == NULL)
{
printf("Error open input file!\n");
exit(1);
}
while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
{
V = (int *) malloc(m*n*sizeof(int));
out = (int *) malloc(m*k*sizeof(int));
for(i=0; i<m*n; i++)
{
fscanf(fp, "%d", &V[i]);
}
// compute the execution time
cudaEvent_t start, stop;
// create event
cudaEventCreate(&start);
cudaEventCreate(&stop);
// record event
cudaEventRecord(start);
// allocate space for devices copies
cudaMalloc((void **)&d_V, m*n*sizeof(int));
cudaMalloc((void **)&d_out, m*k*sizeof(int));
cudaMalloc((void **)&D, m*m*sizeof(int));
// copy host values to devices copies
cudaMemcpy(d_V, V, m*n*sizeof(int), cudaMemcpyHostToDevice);
int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
int gridDimY = (int)(ceil((float)m/TILE_WIDTH));
dim3 grid(gridDimX, gridDimY);
dim3 block(TILE_WIDTH, TILE_WIDTH);
// launch knn() kernel on GPU
computeDist<<<grid, block>>>(m, n, d_V, D);
cudaDeviceSynchronize();
int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);
// copy result back to host
cudaMemcpy(out, d_out, m*k*sizeof(int), cudaMemcpyDeviceToHost);
// cleanup
cudaFree(d_V);
cudaFree(d_out);
cudaFree(D);
// record event and synchronize
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float time;
// get event elapsed time
cudaEventElapsedTime(&time, start, stop);
showResult(m, k, out);
if(m == 1024) {
printf("SMALL:");
} else if(m == 4096) {
printf("MIDDLE:");
} else if(m == 16384) {
printf("LARGE:");
}
printf("%f\n", time);
free(V);
free(out);
}
fclose(fp);
return 0;
}
|
.file "tmpxft_00125834_00000000-6_knn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7findMiniiiPiS_
.type _Z7findMiniiiPiS_, @function
_Z7findMiniiiPiS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7findMiniiiPiS_, .-_Z7findMiniiiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z10showResultiiPi
.type _Z10showResultiiPi, @function
_Z10showResultiiPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 20(%rsp)
movq %rdx, 24(%rsp)
testl %edi, %edi
jle .L5
movl %esi, %r15d
movl $0, 16(%rsp)
movl $0, 12(%rsp)
movslq %esi, %r14
leaq .LC0(%rip), %r13
jmp .L7
.L8:
addq $1, %rbx
cmpq %r14, %rbx
je .L11
.L9:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, %ebp
jne .L8
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L11:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
addl %r15d, 16(%rsp)
cmpl %eax, 20(%rsp)
je .L5
.L7:
testl %r15d, %r15d
jle .L11
movslq 16(%rsp), %rax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,4), %r12
movl $0, %ebx
leal -1(%r15), %ebp
jmp .L9
.L5:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10showResultiiPi, .-_Z10showResultiiPi
.globl _Z35__device_stub__Z11computeDistiiPiS_iiPiS_
.type _Z35__device_stub__Z11computeDistiiPiS_iiPiS_, @function
_Z35__device_stub__Z11computeDistiiPiS_iiPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11computeDistiiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11computeDistiiPiS_iiPiS_, .-_Z35__device_stub__Z11computeDistiiPiS_iiPiS_
.globl _Z11computeDistiiPiS_
.type _Z11computeDistiiPiS_, @function
_Z11computeDistiiPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11computeDistiiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11computeDistiiPiS_, .-_Z11computeDistiiPiS_
.globl _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
.type _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_, @function
_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3knniiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_, .-_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
.globl _Z3knniiPiS_S_
.type _Z3knniiPiS_S_, @function
_Z3knniiPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3knniiPiS_S_, .-_Z3knniiPiS_S_
.section .rodata.str1.1
.LC2:
.string "Usage: knn <inputfile>\n"
.LC3:
.string "r"
.LC4:
.string "Error open input file!\n"
.LC5:
.string "%d"
.LC10:
.string "SMALL:"
.LC11:
.string "MIDDLE:"
.LC12:
.string "LARGE:"
.LC13:
.string "%f\n"
.LC14:
.string "%d %d %d"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L47
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
jne .L32
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
cvttss2sil %xmm3, %eax
movl %eax, 56(%rsp)
movl %eax, 60(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L36:
call cudaDeviceSynchronize@PLT
movl 4(%rsp), %eax
movl $256, %edx
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1024, %edx
cmpl %edx, %eax
cmovg %edx, %eax
addl %eax, %eax
cltq
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L37:
movl 4(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %r14, %rdx
movl 12(%rsp), %esi
movl 4(%rsp), %edi
call _Z10showResultiiPi
movl 4(%rsp), %eax
cmpl $1024, %eax
je .L50
cmpl $4096, %eax
je .L51
cmpl $16384, %eax
je .L52
.L39:
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
.L32:
leaq 8(%rsp), %rcx
leaq 4(%rsp), %rdx
leaq 12(%rsp), %r8
leaq .LC14(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L53
movl 4(%rsp), %ebx
movl %ebx, %ebp
imull 8(%rsp), %ebp
movslq %ebp, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
imull 12(%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebp, %ebp
jle .L33
movq %r15, %rbp
movl $0, %ebx
leaq .LC5(%rip), %r13
.L34:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 4(%rsp), %eax
imull 8(%rsp), %eax
cmpl %ebx, %eax
jg .L34
.L33:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 4(%rsp), %esi
imull 8(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC8(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L35
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm5
andps %xmm5, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
jmp .L35
.L48:
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl 8(%rsp), %esi
movl 4(%rsp), %edi
call _Z35__device_stub__Z11computeDistiiPiS_iiPiS_
jmp .L36
.L49:
movq 24(%rsp), %r8
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl 12(%rsp), %esi
movl 4(%rsp), %edi
call _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
jmp .L37
.L50:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L51:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L52:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L53:
movq %r12, %rdi
call fclose@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z3knniiPiS_S_"
.LC17:
.string "_Z11computeDistiiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z3knniiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z11computeDistiiPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1023410176
.align 4
.LC7:
.long 1258291200
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC9:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/
#include<stdio.h>
#include<cuda.h>
#include<stdlib.h>
#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024
void showResult(int m, int k, int *out);
// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
__shared__ int dist[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row;
int col;
int px;
int py;
for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
{
for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
{
row = by*TILE_WIDTH+py;
col = bx*TILE_WIDTH+px;
dist[py][px] = 0;
__syncthreads();
for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
{
for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
{
rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
}
for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
{
colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
}
__syncthreads();
for(int j=0; j<TILE_DEPTH; j++)
{
dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
}
__syncthreads();
}
D[row*m+col] = dist[py][px];
}
}
}
extern __shared__ int SMem[];
//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
int i = blockIdx.x;
int tid = threadIdx.x;
int s = blockDim.x/2;
int resultValue = INIT_MAX;
int resultIndex = INIT_MAX;
int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j+num == i)
{
SMem[j] = INIT_MAX;
}
else
{
SMem[j] = D[i*m+num+j];
}
//index
SMem[indexBase+j] = j+num;
__syncthreads();
}
if(tid < count)
{
if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
{
SMem[ out[i*k+tid]-num ] = INIT_MAX;
}
__syncthreads();
}
__syncthreads();
// for(s=indexBase/2; s>0; s>>=1)
for(s=indexBase/2; s>32; s>>=1)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j < s)
{
if(SMem[j] == SMem[j+s])
{
if(SMem[indexBase+j] > SMem[indexBase+j+s])
{
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
else if(SMem[j] > SMem[j+s])
{
SMem[j] = SMem[j+s];
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
__syncthreads();
}
}
/*
if(indexBase >= 1024)
{
if(tid < 512)
{
if(SMem[tid] == SMem[tid+512])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
{
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
else if(SMem[tid] > SMem[tid+512])
{
SMem[tid] = SMem[tid+512];
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
__syncthreads();
}
if(indexBase >= 512)
{
if(tid < 256)
{
if(SMem[tid] == SMem[tid+256])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
{
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
else if(SMem[tid] > SMem[tid+256])
{
SMem[tid] = SMem[tid+256];
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
__syncthreads();
}
if(indexBase >= 256)
{
if(tid < 128)
{
if(SMem[tid] == SMem[tid+128])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
{
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
else if(SMem[tid] > SMem[tid+128])
{
SMem[tid] = SMem[tid+128];
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
__syncthreads();
}
if(indexBase >= 128)
{
if(tid < 64)
{
if(SMem[tid] == SMem[tid+64])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
{
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
else if(SMem[tid] > SMem[tid+64])
{
SMem[tid] = SMem[tid+64];
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
__syncthreads();
}
*/
if(tid < 32)
{
/*
#pragma unroll 5
for(s=32; s>0; s>>=1)
{
if(SMem[tid] == SMem[tid+s])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
{
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
else if(SMem[tid] > SMem[tid+s])
{
SMem[tid] = SMem[tid+s];
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
*/
if(SMem[tid] == SMem[tid+32])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
{
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
}
else if(SMem[tid] > SMem[tid+32])
{
SMem[tid] = SMem[tid+32];
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
if(SMem[tid] == SMem[tid+16])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
{
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
}
else if(SMem[tid] > SMem[tid+16])
{
SMem[tid] = SMem[tid+16];
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
if(SMem[tid] == SMem[tid+8])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
{
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
}
else if(SMem[tid] > SMem[tid+8])
{
SMem[tid] = SMem[tid+8];
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
if(SMem[tid] == SMem[tid+4])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
{
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
}
else if(SMem[tid] > SMem[tid+4])
{
SMem[tid] = SMem[tid+4];
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
if(SMem[tid] == SMem[tid+2])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
{
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
}
else if(SMem[tid] > SMem[tid+2])
{
SMem[tid] = SMem[tid+2];
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
if(SMem[tid] == SMem[tid+1])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
{
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
else if(SMem[tid] > SMem[tid+1])
{
SMem[tid] = SMem[tid+1];
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
__syncthreads();
if(resultValue == SMem[0])
{
if(resultIndex > SMem[indexBase])
{
resultIndex = SMem[indexBase];
}
}
else if (resultValue > SMem[0])
{
resultValue = SMem[0];
resultIndex = SMem[indexBase];
}
__syncthreads();
}
return resultIndex;
}
// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
int i;
int count;
i = blockIdx.x;
__syncthreads();
for(count=0; count<k; count++)
{
out[i*k+count] = findMin(m, k, count, D, out);
__syncthreads();
}
}
void showResult(int m, int k, int *out)
{
int i,j;
for(i=0; i<m; i++)
{
for(j=0; j<k; j++)
{
printf("%d ", out[i*k+j]);
if(j == k-1)
{
printf("\n");
}
}
}
}
int main(int argc, char *argv[])
{
int m,n,k;
int i;
int *V, *out; //host copies
int *d_V, *d_out; //device copies
int *D;
FILE *fp;
if(argc != 2)
{
printf("Usage: knn <inputfile>\n");
exit(1);
}
if((fp = fopen(argv[1], "r")) == NULL)
{
printf("Error open input file!\n");
exit(1);
}
while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
{
V = (int *) malloc(m*n*sizeof(int));
out = (int *) malloc(m*k*sizeof(int));
for(i=0; i<m*n; i++)
{
fscanf(fp, "%d", &V[i]);
}
// compute the execution time
cudaEvent_t start, stop;
// create event
cudaEventCreate(&start);
cudaEventCreate(&stop);
// record event
cudaEventRecord(start);
// allocate space for devices copies
cudaMalloc((void **)&d_V, m*n*sizeof(int));
cudaMalloc((void **)&d_out, m*k*sizeof(int));
cudaMalloc((void **)&D, m*m*sizeof(int));
// copy host values to devices copies
cudaMemcpy(d_V, V, m*n*sizeof(int), cudaMemcpyHostToDevice);
int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
int gridDimY = (int)(ceil((float)m/TILE_WIDTH));
dim3 grid(gridDimX, gridDimY);
dim3 block(TILE_WIDTH, TILE_WIDTH);
// launch knn() kernel on GPU
computeDist<<<grid, block>>>(m, n, d_V, D);
cudaDeviceSynchronize();
int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);
// copy result back to host
cudaMemcpy(out, d_out, m*k*sizeof(int), cudaMemcpyDeviceToHost);
// cleanup
cudaFree(d_V);
cudaFree(d_out);
cudaFree(D);
// record event and synchronize
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float time;
// get event elapsed time
cudaEventElapsedTime(&time, start, stop);
showResult(m, k, out);
if(m == 1024) {
printf("SMALL:");
} else if(m == 4096) {
printf("MIDDLE:");
} else if(m == 16384) {
printf("LARGE:");
}
printf("%f\n", time);
free(V);
free(out);
}
fclose(fp);
return 0;
}
|
/*
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024
void showResult(int m, int k, int *out);
// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
__shared__ int dist[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row;
int col;
int px;
int py;
for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
{
for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
{
row = by*TILE_WIDTH+py;
col = bx*TILE_WIDTH+px;
dist[py][px] = 0;
__syncthreads();
for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
{
for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
{
rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
}
for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
{
colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
}
__syncthreads();
for(int j=0; j<TILE_DEPTH; j++)
{
dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
}
__syncthreads();
}
D[row*m+col] = dist[py][px];
}
}
}
extern __shared__ int SMem[];
//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
int i = blockIdx.x;
int tid = threadIdx.x;
int s = blockDim.x/2;
int resultValue = INIT_MAX;
int resultIndex = INIT_MAX;
int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j+num == i)
{
SMem[j] = INIT_MAX;
}
else
{
SMem[j] = D[i*m+num+j];
}
//index
SMem[indexBase+j] = j+num;
__syncthreads();
}
if(tid < count)
{
if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
{
SMem[ out[i*k+tid]-num ] = INIT_MAX;
}
__syncthreads();
}
__syncthreads();
// for(s=indexBase/2; s>0; s>>=1)
for(s=indexBase/2; s>32; s>>=1)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j < s)
{
if(SMem[j] == SMem[j+s])
{
if(SMem[indexBase+j] > SMem[indexBase+j+s])
{
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
else if(SMem[j] > SMem[j+s])
{
SMem[j] = SMem[j+s];
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
__syncthreads();
}
}
/*
if(indexBase >= 1024)
{
if(tid < 512)
{
if(SMem[tid] == SMem[tid+512])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
{
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
else if(SMem[tid] > SMem[tid+512])
{
SMem[tid] = SMem[tid+512];
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
__syncthreads();
}
if(indexBase >= 512)
{
if(tid < 256)
{
if(SMem[tid] == SMem[tid+256])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
{
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
else if(SMem[tid] > SMem[tid+256])
{
SMem[tid] = SMem[tid+256];
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
__syncthreads();
}
if(indexBase >= 256)
{
if(tid < 128)
{
if(SMem[tid] == SMem[tid+128])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
{
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
else if(SMem[tid] > SMem[tid+128])
{
SMem[tid] = SMem[tid+128];
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
__syncthreads();
}
if(indexBase >= 128)
{
if(tid < 64)
{
if(SMem[tid] == SMem[tid+64])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
{
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
else if(SMem[tid] > SMem[tid+64])
{
SMem[tid] = SMem[tid+64];
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
__syncthreads();
}
*/
if(tid < 32)
{
/*
#pragma unroll 5
for(s=32; s>0; s>>=1)
{
if(SMem[tid] == SMem[tid+s])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
{
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
else if(SMem[tid] > SMem[tid+s])
{
SMem[tid] = SMem[tid+s];
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
*/
if(SMem[tid] == SMem[tid+32])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
{
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
}
else if(SMem[tid] > SMem[tid+32])
{
SMem[tid] = SMem[tid+32];
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
if(SMem[tid] == SMem[tid+16])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
{
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
}
else if(SMem[tid] > SMem[tid+16])
{
SMem[tid] = SMem[tid+16];
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
if(SMem[tid] == SMem[tid+8])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
{
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
}
else if(SMem[tid] > SMem[tid+8])
{
SMem[tid] = SMem[tid+8];
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
if(SMem[tid] == SMem[tid+4])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
{
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
}
else if(SMem[tid] > SMem[tid+4])
{
SMem[tid] = SMem[tid+4];
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
if(SMem[tid] == SMem[tid+2])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
{
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
}
else if(SMem[tid] > SMem[tid+2])
{
SMem[tid] = SMem[tid+2];
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
if(SMem[tid] == SMem[tid+1])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
{
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
else if(SMem[tid] > SMem[tid+1])
{
SMem[tid] = SMem[tid+1];
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
__syncthreads();
if(resultValue == SMem[0])
{
if(resultIndex > SMem[indexBase])
{
resultIndex = SMem[indexBase];
}
}
else if (resultValue > SMem[0])
{
resultValue = SMem[0];
resultIndex = SMem[indexBase];
}
__syncthreads();
}
return resultIndex;
}
// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
int i;
int count;
i = blockIdx.x;
__syncthreads();
for(count=0; count<k; count++)
{
out[i*k+count] = findMin(m, k, count, D, out);
__syncthreads();
}
}
void showResult(int m, int k, int *out)
{
int i,j;
for(i=0; i<m; i++)
{
for(j=0; j<k; j++)
{
printf("%d ", out[i*k+j]);
if(j == k-1)
{
printf("\n");
}
}
}
}
int main(int argc, char *argv[])
{
int m,n,k;
int i;
int *V, *out; //host copies
int *d_V, *d_out; //device copies
int *D;
FILE *fp;
if(argc != 2)
{
printf("Usage: knn <inputfile>\n");
exit(1);
}
if((fp = fopen(argv[1], "r")) == NULL)
{
printf("Error open input file!\n");
exit(1);
}
while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
{
V = (int *) malloc(m*n*sizeof(int));
out = (int *) malloc(m*k*sizeof(int));
for(i=0; i<m*n; i++)
{
fscanf(fp, "%d", &V[i]);
}
// compute the execution time
hipEvent_t start, stop;
// create event
hipEventCreate(&start);
hipEventCreate(&stop);
// record event
hipEventRecord(start);
// allocate space for devices copies
hipMalloc((void **)&d_V, m*n*sizeof(int));
hipMalloc((void **)&d_out, m*k*sizeof(int));
hipMalloc((void **)&D, m*m*sizeof(int));
// copy host values to devices copies
hipMemcpy(d_V, V, m*n*sizeof(int), hipMemcpyHostToDevice);
int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
int gridDimY = (int)(ceil((float)m/TILE_WIDTH));
dim3 grid(gridDimX, gridDimY);
dim3 block(TILE_WIDTH, TILE_WIDTH);
// launch knn() kernel on GPU
computeDist<<<grid, block>>>(m, n, d_V, D);
hipDeviceSynchronize();
int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);
// copy result back to host
hipMemcpy(out, d_out, m*k*sizeof(int), hipMemcpyDeviceToHost);
// cleanup
hipFree(d_V);
hipFree(d_out);
hipFree(D);
// record event and synchronize
hipEventRecord(stop);
hipEventSynchronize(stop);
float time;
// get event elapsed time
hipEventElapsedTime(&time, start, stop);
showResult(m, k, out);
if(m == 1024) {
printf("SMALL:");
} else if(m == 4096) {
printf("MIDDLE:");
} else if(m == 16384) {
printf("LARGE:");
}
printf("%f\n", time);
free(V);
free(out);
}
fclose(fp);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024
void showResult(int m, int k, int *out);
// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
__shared__ int dist[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row;
int col;
int px;
int py;
for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
{
for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
{
row = by*TILE_WIDTH+py;
col = bx*TILE_WIDTH+px;
dist[py][px] = 0;
__syncthreads();
for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
{
for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
{
rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
}
for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
{
colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
}
__syncthreads();
for(int j=0; j<TILE_DEPTH; j++)
{
dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
}
__syncthreads();
}
D[row*m+col] = dist[py][px];
}
}
}
extern __shared__ int SMem[];
//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
int i = blockIdx.x;
int tid = threadIdx.x;
int s = blockDim.x/2;
int resultValue = INIT_MAX;
int resultIndex = INIT_MAX;
int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j+num == i)
{
SMem[j] = INIT_MAX;
}
else
{
SMem[j] = D[i*m+num+j];
}
//index
SMem[indexBase+j] = j+num;
__syncthreads();
}
if(tid < count)
{
if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
{
SMem[ out[i*k+tid]-num ] = INIT_MAX;
}
__syncthreads();
}
__syncthreads();
// for(s=indexBase/2; s>0; s>>=1)
for(s=indexBase/2; s>32; s>>=1)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j < s)
{
if(SMem[j] == SMem[j+s])
{
if(SMem[indexBase+j] > SMem[indexBase+j+s])
{
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
else if(SMem[j] > SMem[j+s])
{
SMem[j] = SMem[j+s];
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
__syncthreads();
}
}
/*
if(indexBase >= 1024)
{
if(tid < 512)
{
if(SMem[tid] == SMem[tid+512])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
{
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
else if(SMem[tid] > SMem[tid+512])
{
SMem[tid] = SMem[tid+512];
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
__syncthreads();
}
if(indexBase >= 512)
{
if(tid < 256)
{
if(SMem[tid] == SMem[tid+256])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
{
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
else if(SMem[tid] > SMem[tid+256])
{
SMem[tid] = SMem[tid+256];
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
__syncthreads();
}
if(indexBase >= 256)
{
if(tid < 128)
{
if(SMem[tid] == SMem[tid+128])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
{
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
else if(SMem[tid] > SMem[tid+128])
{
SMem[tid] = SMem[tid+128];
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
__syncthreads();
}
if(indexBase >= 128)
{
if(tid < 64)
{
if(SMem[tid] == SMem[tid+64])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
{
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
else if(SMem[tid] > SMem[tid+64])
{
SMem[tid] = SMem[tid+64];
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
__syncthreads();
}
*/
if(tid < 32)
{
/*
#pragma unroll 5
for(s=32; s>0; s>>=1)
{
if(SMem[tid] == SMem[tid+s])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
{
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
else if(SMem[tid] > SMem[tid+s])
{
SMem[tid] = SMem[tid+s];
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
*/
if(SMem[tid] == SMem[tid+32])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
{
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
}
else if(SMem[tid] > SMem[tid+32])
{
SMem[tid] = SMem[tid+32];
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
if(SMem[tid] == SMem[tid+16])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
{
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
}
else if(SMem[tid] > SMem[tid+16])
{
SMem[tid] = SMem[tid+16];
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
if(SMem[tid] == SMem[tid+8])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
{
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
}
else if(SMem[tid] > SMem[tid+8])
{
SMem[tid] = SMem[tid+8];
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
if(SMem[tid] == SMem[tid+4])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
{
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
}
else if(SMem[tid] > SMem[tid+4])
{
SMem[tid] = SMem[tid+4];
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
if(SMem[tid] == SMem[tid+2])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
{
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
}
else if(SMem[tid] > SMem[tid+2])
{
SMem[tid] = SMem[tid+2];
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
if(SMem[tid] == SMem[tid+1])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
{
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
else if(SMem[tid] > SMem[tid+1])
{
SMem[tid] = SMem[tid+1];
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
__syncthreads();
if(resultValue == SMem[0])
{
if(resultIndex > SMem[indexBase])
{
resultIndex = SMem[indexBase];
}
}
else if (resultValue > SMem[0])
{
resultValue = SMem[0];
resultIndex = SMem[indexBase];
}
__syncthreads();
}
return resultIndex;
}
// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
int i;
int count;
i = blockIdx.x;
__syncthreads();
for(count=0; count<k; count++)
{
out[i*k+count] = findMin(m, k, count, D, out);
__syncthreads();
}
}
void showResult(int m, int k, int *out)
{
int i,j;
for(i=0; i<m; i++)
{
for(j=0; j<k; j++)
{
printf("%d ", out[i*k+j]);
if(j == k-1)
{
printf("\n");
}
}
}
}
int main(int argc, char *argv[])
{
int m,n,k;
int i;
int *V, *out; //host copies
int *d_V, *d_out; //device copies
int *D;
FILE *fp;
if(argc != 2)
{
printf("Usage: knn <inputfile>\n");
exit(1);
}
if((fp = fopen(argv[1], "r")) == NULL)
{
printf("Error open input file!\n");
exit(1);
}
while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
{
V = (int *) malloc(m*n*sizeof(int));
out = (int *) malloc(m*k*sizeof(int));
for(i=0; i<m*n; i++)
{
fscanf(fp, "%d", &V[i]);
}
// compute the execution time
hipEvent_t start, stop;
// create event
hipEventCreate(&start);
hipEventCreate(&stop);
// record event
hipEventRecord(start);
// allocate space for devices copies
hipMalloc((void **)&d_V, m*n*sizeof(int));
hipMalloc((void **)&d_out, m*k*sizeof(int));
hipMalloc((void **)&D, m*m*sizeof(int));
// copy host values to devices copies
hipMemcpy(d_V, V, m*n*sizeof(int), hipMemcpyHostToDevice);
int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
int gridDimY = (int)(ceil((float)m/TILE_WIDTH));
dim3 grid(gridDimX, gridDimY);
dim3 block(TILE_WIDTH, TILE_WIDTH);
// launch knn() kernel on GPU
computeDist<<<grid, block>>>(m, n, d_V, D);
hipDeviceSynchronize();
int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);
// copy result back to host
hipMemcpy(out, d_out, m*k*sizeof(int), hipMemcpyDeviceToHost);
// cleanup
hipFree(d_V);
hipFree(d_out);
hipFree(D);
// record event and synchronize
hipEventRecord(stop);
hipEventSynchronize(stop);
float time;
// get event elapsed time
hipEventElapsedTime(&time, start, stop);
showResult(m, k, out);
if(m == 1024) {
printf("SMALL:");
} else if(m == 4096) {
printf("MIDDLE:");
} else if(m == 16384) {
printf("LARGE:");
}
printf("%f\n", time);
free(V);
free(out);
}
fclose(fp);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11computeDistiiPiS_
.globl _Z11computeDistiiPiS_
.p2align 8
.type _Z11computeDistiiPiS_,@function
_Z11computeDistiiPiS_:
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 32, v1
s_cbranch_execz .LBB0_15
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
s_lshl_b32 s3, s15, 5
v_dual_mov_b32 v19, v1 :: v_dual_and_b32 v0, 0x3ff, v0
v_add_nc_u32_e32 v4, s3, v1
s_lshl_b32 s12, s14, 5
v_lshl_add_u32 v13, v1, 9, 0x4000
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v6, s12, v0
v_dual_mov_b32 v14, 0 :: v_dual_lshlrev_b32 v15, 2, v0
s_add_u32 s10, s0, 24
s_addc_u32 s11, s1, 0
v_cmp_gt_u32_e64 s0, 32, v0
s_mov_b32 s13, 0
v_add_nc_u32_e32 v16, v13, v15
v_lshl_add_u32 v17, v1, 7, v15
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v2, s5
s_lshr_b32 s14, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mul_i32 s15, s5, s14
s_lshl_b32 s16, s14, 9
v_mul_f32_e32 v2, 0x3c000000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f32_e32 v2, v2
v_cvt_i32_f32_e32 v18, v2
v_mad_u64_u32 v[2:3], null, s5, v4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s1, 0, v18
v_mad_u64_u32 v[4:5], null, s5, v6, v[1:2]
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s18
v_add_nc_u32_e32 v19, s14, v19
v_add_nc_u32_e32 v2, s15, v2
v_add_nc_u32_e32 v16, s16, v16
v_add_nc_u32_e32 v13, s16, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_u32_e32 vcc_lo, 31, v19
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_15
.LBB0_3:
s_and_saveexec_b32 s18, s0
s_cbranch_execz .LBB0_2
s_load_b32 s2, s[10:11], 0xc
v_ashrrev_i32_e32 v3, 31, v2
v_dual_mov_b32 v20, v15 :: v_dual_add_nc_u32 v7, s3, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v21, v17 :: v_dual_mov_b32 v22, v4
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_lo_u32 v24, v7, s4
v_mov_b32_e32 v23, v0
s_mov_b32 s22, 0
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s2, 0xffff
s_mul_i32 s20, s5, s19
s_lshl_b32 s21, s19, 2
s_branch .LBB0_6
.LBB0_5:
v_add3_u32 v7, v23, s12, v24
ds_load_b32 v3, v25
v_add_nc_u32_e32 v23, s19, v23
v_add_nc_u32_e32 v22, s20, v22
v_add_nc_u32_e32 v21, s21, v21
v_ashrrev_i32_e32 v8, 31, v7
v_add_nc_u32_e32 v20, s21, v20
v_cmp_lt_u32_e32 vcc_lo, 31, v23
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_or_b32 s22, vcc_lo, s22
v_add_co_u32 v7, s2, s8, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, s9, v8, s2
s_waitcnt lgkmcnt(0)
global_store_b32 v[7:8], v3, off
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execz .LBB0_2
.LBB0_6:
v_lshlrev_b32_e32 v3, 2, v23
s_and_not1_b32 vcc_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v3, v19, 7, v3
v_add_nc_u32_e32 v25, 0x8000, v3
ds_store_b32 v3, v14 offset:32768
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_5
s_clause 0x1
s_load_b32 s2, s[10:11], 0xc
s_load_b32 s25, s[10:11], 0xc
v_mov_b32_e32 v7, v22
v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
s_mov_b32 s23, s13
s_mov_b32 s29, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s24, s2, 0xffff
s_lshr_b32 s25, s25, 16
s_lshl_b32 s26, s24, 2
s_lshl_b32 s27, s25, 2
s_lshl_b32 s28, s25, 7
.LBB0_8:
v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v12, v10
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v8, v0
s_mov_b32 s30, 0
.LBB0_9:
global_load_b32 v26, v[11:12], off
v_add_nc_u32_e32 v8, s24, v8
v_add_co_u32 v11, vcc_lo, v11, s26
v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 0x7f, v8
s_or_b32 s30, s2, s30
s_waitcnt vmcnt(0)
ds_store_b32 v3, v26
v_add_nc_u32_e32 v3, s26, v3
s_and_not1_b32 exec_lo, exec_lo, s30
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s30
v_ashrrev_i32_e32 v8, 31, v7
v_mov_b32_e32 v3, v21
s_mov_b32 s30, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_mov_b32_e32 v8, v1
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
.LBB0_11:
global_load_b32 v26, v[11:12], off
v_add_nc_u32_e32 v8, s25, v8
v_add_co_u32 v11, vcc_lo, v11, s27
v_add_co_ci_u32_e32 v12, vcc_lo, s23, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 0x7f, v8
s_or_b32 s30, s2, s30
s_waitcnt vmcnt(0)
ds_store_b32 v3, v26
v_add_nc_u32_e32 v3, s28, v3
s_and_not1_b32 exec_lo, exec_lo, s30
s_cbranch_execnz .LBB0_11
s_or_b32 exec_lo, exec_lo, s30
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v25
v_mov_b32_e32 v8, v20
s_mov_b32 s2, 0
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, s2, v13
s_add_i32 s2, s2, 4
ds_load_b32 v12, v8
ds_load_b32 v11, v11
s_cmpk_eq_i32 s2, 0x200
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v26, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v26, v26, v[3:4]
v_dual_mov_b32 v3, v11 :: v_dual_add_nc_u32 v8, 0x80, v8
s_cbranch_scc0 .LBB0_13
s_add_i32 s29, s29, 1
v_add_co_u32 v9, s2, v9, 0x200
v_cmp_eq_u32_e32 vcc_lo, s29, v18
v_add_co_ci_u32_e64 v10, s2, 0, v10, s2
v_add_nc_u32_e32 v7, 0x80, v7
ds_store_b32 v25, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_8
s_branch .LBB0_5
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11computeDistiiPiS_
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11computeDistiiPiS_, .Lfunc_end0-_Z11computeDistiiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3knniiPiS_S_
.globl _Z3knniiPiS_S_
.p2align 8
.type _Z3knniiPiS_S_,@function
_Z3knniiPiS_S_:
s_load_b32 s10, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB1_83
s_clause 0x1
s_load_b32 s11, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
s_mul_i32 s12, s15, s10
v_dual_mov_b32 v20, 0x989680 :: v_dual_lshlrev_b32 v3, 2, v0
v_add_nc_u32_e32 v1, s12, v0
v_cmp_gt_u32_e64 s2, 32, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mov_b32 v21, 0 :: v_dual_add_nc_u32 v4, 0, v3
s_mov_b32 s13, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 0x80, v4
v_add_nc_u32_e32 v6, 64, v4
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_nc_u32_e32 v7, 32, v4
v_add_nc_u32_e32 v8, 16, v4
v_add_nc_u32_e32 v9, 8, v4
v_add_nc_u32_e32 v17, 4, v4
s_waitcnt lgkmcnt(0)
s_min_i32 s14, s11, 0x400
s_cmp_gt_i32 s11, 0
v_add_lshl_u32 v10, s14, v0, 2
s_cselect_b32 s16, -1, 0
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
s_cmpk_gt_i32 s11, 0x41
v_add_nc_u32_e32 v11, 0, v10
v_add_co_u32 v1, vcc_lo, s6, v1
s_cselect_b32 s1, -1, 0
s_lshl_b32 s0, s14, 2
v_cmp_gt_i32_e64 s3, s11, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v12, 0x80, v11
v_add_nc_u32_e32 v13, 64, v11
v_add_nc_u32_e32 v14, 32, v11
v_add_nc_u32_e32 v15, 16, v11
v_add_nc_u32_e32 v16, 8, v11
v_add_nc_u32_e32 v18, 4, v11
v_add_nc_u32_e32 v19, s0, v3
s_mul_i32 s17, s15, s11
s_add_i32 s18, s0, 0
s_sub_i32 s15, 0, s15
s_branch .LBB1_3
.LBB1_2:
s_add_i32 s20, s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s6, s20
s_addc_u32 s21, s7, s21
s_add_i32 s13, s13, 1
global_store_b32 v21, v24, s[20:21]
s_cmp_lg_u32 s13, s10
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_83
.LBB1_3:
v_mov_b32_e32 v24, 0x989680
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB1_2
s_load_b32 s19, s[8:9], 0xc
v_cmp_gt_u32_e64 s0, s13, v0
v_dual_mov_b32 v22, 0x989680 :: v_dual_mov_b32 v23, 0x989680
s_mov_b32 s20, 0
s_mov_b32 s22, s17
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s19, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s21, s19, 2
s_and_saveexec_b32 s23, s3
s_cbranch_execz .LBB1_9
.LBB1_5:
v_mov_b32_e32 v24, v0
s_add_i32 s24, s15, s20
s_mov_b32 s25, 0
s_mov_b32 s26, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_7
.p2align 6
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s27
v_add_nc_u32_e32 v26, s20, v24
v_add_nc_u32_e32 v24, s19, v24
v_add_nc_u32_e32 v27, s25, v3
v_add_nc_u32_e32 v28, s25, v10
s_add_i32 s25, s25, s21
s_waitcnt vmcnt(0)
ds_store_b32 v27, v25
ds_store_b32 v28, v26
v_cmp_le_i32_e32 vcc_lo, s14, v24
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_or_b32 s26, vcc_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB1_9
.LBB1_7:
v_add_nc_u32_e32 v25, s24, v24
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v25
v_mov_b32_e32 v25, 0x989680
s_and_saveexec_b32 s27, vcc_lo
s_cbranch_execz .LBB1_6
v_add_nc_u32_e32 v25, s22, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v26, 31, v25
v_lshlrev_b64 v[25:26], 2, v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v25, vcc_lo, s4, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo
global_load_b32 v25, v[25:26], off
s_branch .LBB1_6
.LBB1_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s23
s_and_saveexec_b32 s23, s0
s_cbranch_execz .LBB1_13
global_load_b32 v24, v[1:2], off
s_waitcnt vmcnt(0)
v_subrev_nc_u32_e32 v24, s20, v24
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s14, v24
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_12
v_lshl_add_u32 v24, v24, 2, 0
ds_store_b32 v24, v20
.LBB1_12:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_mov_b32 s23, s14
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_68
.LBB1_14:
s_and_saveexec_b32 s23, s2
s_cbranch_execz .LBB1_63
ds_load_b32 v26, v4
ds_load_b32 v25, v5
s_mov_b32 s24, 0
s_mov_b32 s25, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v26, v25
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB1_19
s_mov_b32 s26, exec_lo
v_cmpx_gt_i32_e64 v26, v25
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB1_18
ds_store_b32 v4, v25
ds_load_b32 v24, v12
s_mov_b32 s24, exec_lo
.LBB1_18:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s24, exec_lo
.LBB1_19:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB1_21
ds_load_b32 v25, v11
s_waitcnt lgkmcnt(1)
ds_load_b32 v24, v12
s_and_not1_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v25, v24
s_and_b32 s26, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s24, s24, s26
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB1_23
s_waitcnt lgkmcnt(0)
ds_store_b32 v11, v24
.LBB1_23:
s_or_b32 exec_lo, exec_lo, s25
ds_load_b32 v26, v4
ds_load_b32 v25, v6
s_mov_b32 s24, 0
s_mov_b32 s25, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v26, v25
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB1_27
s_mov_b32 s26, exec_lo
v_cmpx_gt_i32_e64 v26, v25
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB1_26
ds_store_b32 v4, v25
ds_load_b32 v24, v13
s_mov_b32 s24, exec_lo
.LBB1_26:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s24, exec_lo
.LBB1_27:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB1_29
ds_load_b32 v25, v11
s_waitcnt lgkmcnt(1)
ds_load_b32 v24, v13
s_and_not1_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v25, v24
s_and_b32 s26, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s24, s24, s26
.LBB1_29:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB1_31
s_waitcnt lgkmcnt(0)
ds_store_b32 v11, v24
.LBB1_31:
s_or_b32 exec_lo, exec_lo, s25
ds_load_b32 v26, v4
ds_load_b32 v25, v7
s_mov_b32 s24, 0
s_mov_b32 s25, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v26, v25
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB1_35
s_mov_b32 s26, exec_lo
v_cmpx_gt_i32_e64 v26, v25
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB1_34
ds_store_b32 v4, v25
ds_load_b32 v24, v14
s_mov_b32 s24, exec_lo
.LBB1_34:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s24, exec_lo
.LBB1_35:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB1_37
ds_load_b32 v25, v11
s_waitcnt lgkmcnt(1)
ds_load_b32 v24, v14
s_and_not1_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v25, v24
s_and_b32 s26, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s24, s24, s26
.LBB1_37:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB1_39
s_waitcnt lgkmcnt(0)
ds_store_b32 v11, v24
.LBB1_39:
s_or_b32 exec_lo, exec_lo, s25
ds_load_b32 v26, v4
ds_load_b32 v25, v8
s_mov_b32 s24, 0
s_mov_b32 s25, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v26, v25
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB1_43
s_mov_b32 s26, exec_lo
v_cmpx_gt_i32_e64 v26, v25
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB1_42
ds_store_b32 v4, v25
ds_load_b32 v24, v15
s_mov_b32 s24, exec_lo
.LBB1_42:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s24, exec_lo
.LBB1_43:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB1_45
ds_load_b32 v25, v11
s_waitcnt lgkmcnt(1)
ds_load_b32 v24, v15
s_and_not1_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v25, v24
s_and_b32 s26, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s24, s24, s26
.LBB1_45:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB1_47
s_waitcnt lgkmcnt(0)
ds_store_b32 v11, v24
.LBB1_47:
s_or_b32 exec_lo, exec_lo, s25
ds_load_b32 v26, v4
ds_load_b32 v25, v9
s_mov_b32 s24, 0
s_mov_b32 s25, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v26, v25
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB1_51
s_mov_b32 s26, exec_lo
v_cmpx_gt_i32_e64 v26, v25
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB1_50
ds_store_b32 v4, v25
ds_load_b32 v24, v16
s_mov_b32 s24, exec_lo
.LBB1_50:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s24, exec_lo
.LBB1_51:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB1_53
ds_load_b32 v25, v11
s_waitcnt lgkmcnt(1)
ds_load_b32 v24, v16
s_and_not1_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v25, v24
s_and_b32 s26, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s24, s24, s26
.LBB1_53:
s_or_b32 exec_lo, exec_lo, s25
s_and_saveexec_b32 s25, s24
s_cbranch_execz .LBB1_55
s_waitcnt lgkmcnt(0)
ds_store_b32 v11, v24
.LBB1_55:
s_or_b32 exec_lo, exec_lo, s25
ds_load_b32 v26, v4
ds_load_b32 v25, v17
s_mov_b32 s24, 0
s_mov_b32 s25, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v26, v25
s_xor_b32 s25, exec_lo, s25
s_cbranch_execz .LBB1_59
s_mov_b32 s26, exec_lo
v_cmpx_gt_i32_e64 v26, v25
s_xor_b32 s26, exec_lo, s26
s_cbranch_execz .LBB1_58
ds_store_b32 v4, v25
ds_load_b32 v24, v18
s_mov_b32 s24, exec_lo
.LBB1_58:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s24, s24, exec_lo
.LBB1_59:
s_and_not1_saveexec_b32 s25, s25
s_cbranch_execz .LBB1_61
ds_load_b32 v25, v11
s_waitcnt lgkmcnt(1)
ds_load_b32 v24, v18
s_and_not1_b32 s24, s24, exec_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v25, v24
s_and_b32 s26, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s24, s24, s26
.LBB1_61:
s_or_b32 exec_lo, exec_lo, s25
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s24
s_cbranch_execz .LBB1_63
s_waitcnt lgkmcnt(0)
ds_store_b32 v11, v24
.LBB1_63:
s_or_b32 exec_lo, exec_lo, s23
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v24, 0
s_barrier
buffer_gl0_inv
ds_load_b32 v26, v24
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v23, v26
s_cbranch_vccz .LBB1_79
v_cmp_le_i32_e32 vcc_lo, v23, v26
v_dual_mov_b32 v24, v22 :: v_dual_mov_b32 v25, v23
s_cbranch_vccnz .LBB1_66
v_dual_mov_b32 v24, s18 :: v_dual_mov_b32 v25, v26
ds_load_b32 v24, v24
.LBB1_66:
s_cbranch_execz .LBB1_80
s_branch .LBB1_81
.LBB1_67:
s_or_b32 exec_lo, exec_lo, s25
s_cmpk_lt_u32 s23, 0x84
s_mov_b32 s23, s24
s_cbranch_scc1 .LBB1_14
.LBB1_68:
s_lshr_b32 s24, s23, 1
s_and_saveexec_b32 s25, s3
s_cbranch_execz .LBB1_67
s_lshl_b32 s26, s24, 2
s_mov_b32 s27, 0
v_add_nc_u32_e32 v24, s26, v19
v_dual_mov_b32 v26, v0 :: v_dual_add_nc_u32 v25, s26, v3
s_mov_b32 s26, 0
s_branch .LBB1_71
.LBB1_70:
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v26, s19, v26
s_add_i32 s26, s26, s21
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_le_i32_e32 vcc_lo, s14, v26
s_or_b32 s27, vcc_lo, s27
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB1_67
.LBB1_71:
s_mov_b32 s28, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s24, v26
s_cbranch_execz .LBB1_70
v_add_nc_u32_e32 v27, s26, v3
v_add_nc_u32_e32 v28, s26, v25
s_mov_b32 s29, exec_lo
ds_load_b32 v29, v27
ds_load_b32 v28, v28
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 v29, v28
s_xor_b32 s29, exec_lo, s29
s_cbranch_execz .LBB1_76
s_mov_b32 s30, exec_lo
v_cmpx_gt_i32_e64 v29, v28
s_cbranch_execz .LBB1_75
v_add_nc_u32_e32 v29, s26, v24
ds_store_b32 v27, v28
v_add_nc_u32_e32 v28, s26, v19
ds_load_b32 v27, v29
s_waitcnt lgkmcnt(0)
ds_store_b32 v28, v27
.LBB1_75:
s_or_b32 exec_lo, exec_lo, s30
.LBB1_76:
s_and_not1_saveexec_b32 s29, s29
s_cbranch_execz .LBB1_70
v_add_nc_u32_e32 v27, s26, v19
v_add_nc_u32_e32 v28, s26, v24
ds_load_b32 v29, v27
ds_load_b32 v28, v28
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v29, v28
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_70
ds_store_b32 v27, v28
s_branch .LBB1_70
.LBB1_79:
.LBB1_80:
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v24, s18 :: v_dual_mov_b32 v25, v23
ds_load_b32 v24, v24
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v24, v22, v24
.LBB1_81:
s_addk_i32 s20, 0x400
s_addk_i32 s22, 0x400
s_cmp_lt_i32 s20, s11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
v_dual_mov_b32 v22, v24 :: v_dual_mov_b32 v23, v25
s_and_saveexec_b32 s23, s3
s_cbranch_execnz .LBB1_5
s_branch .LBB1_9
.LBB1_83:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3knniiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 31
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3knniiPiS_S_, .Lfunc_end1-_Z3knniiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11computeDistiiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z11computeDistiiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3knniiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 33
.sgpr_spill_count: 0
.symbol: _Z3knniiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
* INPUT:
* m: total num of points
* n: n dimensions
* k: num of nearest points
* V: point coordinates
* OUTPUT:
* out: k nearest neighbors
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<stdlib.h>
#define INIT_MAX 10000000
#define TILE_WIDTH 32
#define TILE_DEPTH 128
#define MAX_BLOCK_SIZE 256
#define MAX_PTRNUM_IN_SMEM 1024
void showResult(int m, int k, int *out);
// compute the square of distance of the ith point and jth point
__global__ void computeDist(int m, int n, int *V, int *D)
{
__shared__ int rowVector[TILE_WIDTH][TILE_DEPTH];
__shared__ int colVector[TILE_DEPTH][TILE_WIDTH];
__shared__ int dist[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row;
int col;
int px;
int py;
for(py=ty; py<TILE_WIDTH; py+=blockDim.y)
{
for(px=tx; px<TILE_WIDTH; px+=blockDim.x)
{
row = by*TILE_WIDTH+py;
col = bx*TILE_WIDTH+px;
dist[py][px] = 0;
__syncthreads();
for(int i=0; i<(int)(ceil((float)n/TILE_DEPTH)); i++)
{
for(int j=tx; j<TILE_DEPTH; j+=blockDim.x)
{
rowVector[py][j] = V[row*n+i*TILE_DEPTH+j];
}
for(int j=ty; j<TILE_DEPTH; j+=blockDim.y)
{
colVector[j][px] = V[col*n+i*TILE_DEPTH+j];
}
__syncthreads();
for(int j=0; j<TILE_DEPTH; j++)
{
dist[py][px] += (rowVector[py][j]-colVector[j][px])*(rowVector[py][j]-colVector[j][px]);
}
__syncthreads();
}
D[row*m+col] = dist[py][px];
}
}
}
extern __shared__ int SMem[];
//find the min value and index in the count^th loop
__device__ int findMin(int m, int k, int count, int *D, int *out)
{
int i = blockIdx.x;
int tid = threadIdx.x;
int s = blockDim.x/2;
int resultValue = INIT_MAX;
int resultIndex = INIT_MAX;
int indexBase = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
for(int num=0; num<m; num+=MAX_PTRNUM_IN_SMEM)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j+num == i)
{
SMem[j] = INIT_MAX;
}
else
{
SMem[j] = D[i*m+num+j];
}
//index
SMem[indexBase+j] = j+num;
__syncthreads();
}
if(tid < count)
{
if(out[i*k+tid]-num>=0 && out[i*k+tid]-num<indexBase)
{
SMem[ out[i*k+tid]-num ] = INIT_MAX;
}
__syncthreads();
}
__syncthreads();
// for(s=indexBase/2; s>0; s>>=1)
for(s=indexBase/2; s>32; s>>=1)
{
for(int j=tid; j<indexBase; j+=blockDim.x)
{
if(j < s)
{
if(SMem[j] == SMem[j+s])
{
if(SMem[indexBase+j] > SMem[indexBase+j+s])
{
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
else if(SMem[j] > SMem[j+s])
{
SMem[j] = SMem[j+s];
SMem[indexBase+j] = SMem[indexBase+j+s];
}
}
__syncthreads();
}
}
/*
if(indexBase >= 1024)
{
if(tid < 512)
{
if(SMem[tid] == SMem[tid+512])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+512])
{
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
else if(SMem[tid] > SMem[tid+512])
{
SMem[tid] = SMem[tid+512];
SMem[indexBase+tid] = SMem[indexBase+tid+512];
}
}
__syncthreads();
}
if(indexBase >= 512)
{
if(tid < 256)
{
if(SMem[tid] == SMem[tid+256])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+256])
{
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
else if(SMem[tid] > SMem[tid+256])
{
SMem[tid] = SMem[tid+256];
SMem[indexBase+tid] = SMem[indexBase+tid+256];
}
}
__syncthreads();
}
if(indexBase >= 256)
{
if(tid < 128)
{
if(SMem[tid] == SMem[tid+128])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+128])
{
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
else if(SMem[tid] > SMem[tid+128])
{
SMem[tid] = SMem[tid+128];
SMem[indexBase+tid] = SMem[indexBase+tid+128];
}
}
__syncthreads();
}
if(indexBase >= 128)
{
if(tid < 64)
{
if(SMem[tid] == SMem[tid+64])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+64])
{
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
else if(SMem[tid] > SMem[tid+64])
{
SMem[tid] = SMem[tid+64];
SMem[indexBase+tid] = SMem[indexBase+tid+64];
}
}
__syncthreads();
}
*/
if(tid < 32)
{
/*
#pragma unroll 5
for(s=32; s>0; s>>=1)
{
if(SMem[tid] == SMem[tid+s])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+s])
{
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
else if(SMem[tid] > SMem[tid+s])
{
SMem[tid] = SMem[tid+s];
SMem[indexBase+tid] = SMem[indexBase+tid+s];
}
}
*/
if(SMem[tid] == SMem[tid+32])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+32])
{
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
}
else if(SMem[tid] > SMem[tid+32])
{
SMem[tid] = SMem[tid+32];
SMem[indexBase+tid] = SMem[indexBase+tid+32];
}
if(SMem[tid] == SMem[tid+16])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+16])
{
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
}
else if(SMem[tid] > SMem[tid+16])
{
SMem[tid] = SMem[tid+16];
SMem[indexBase+tid] = SMem[indexBase+tid+16];
}
if(SMem[tid] == SMem[tid+8])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+8])
{
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
}
else if(SMem[tid] > SMem[tid+8])
{
SMem[tid] = SMem[tid+8];
SMem[indexBase+tid] = SMem[indexBase+tid+8];
}
if(SMem[tid] == SMem[tid+4])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+4])
{
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
}
else if(SMem[tid] > SMem[tid+4])
{
SMem[tid] = SMem[tid+4];
SMem[indexBase+tid] = SMem[indexBase+tid+4];
}
if(SMem[tid] == SMem[tid+2])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+2])
{
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
}
else if(SMem[tid] > SMem[tid+2])
{
SMem[tid] = SMem[tid+2];
SMem[indexBase+tid] = SMem[indexBase+tid+2];
}
if(SMem[tid] == SMem[tid+1])
{
if(SMem[indexBase+tid] > SMem[indexBase+tid+1])
{
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
else if(SMem[tid] > SMem[tid+1])
{
SMem[tid] = SMem[tid+1];
SMem[indexBase+tid] = SMem[indexBase+tid+1];
}
}
__syncthreads();
if(resultValue == SMem[0])
{
if(resultIndex > SMem[indexBase])
{
resultIndex = SMem[indexBase];
}
}
else if (resultValue > SMem[0])
{
resultValue = SMem[0];
resultIndex = SMem[indexBase];
}
__syncthreads();
}
return resultIndex;
}
// compute the k nearest neighbors
__global__ void knn(int m, int k, int *V, int *D, int *out)
{
int i;
int count;
i = blockIdx.x;
__syncthreads();
for(count=0; count<k; count++)
{
out[i*k+count] = findMin(m, k, count, D, out);
__syncthreads();
}
}
void showResult(int m, int k, int *out)
{
int i,j;
for(i=0; i<m; i++)
{
for(j=0; j<k; j++)
{
printf("%d ", out[i*k+j]);
if(j == k-1)
{
printf("\n");
}
}
}
}
int main(int argc, char *argv[])
{
int m,n,k;
int i;
int *V, *out; //host copies
int *d_V, *d_out; //device copies
int *D;
FILE *fp;
if(argc != 2)
{
printf("Usage: knn <inputfile>\n");
exit(1);
}
if((fp = fopen(argv[1], "r")) == NULL)
{
printf("Error open input file!\n");
exit(1);
}
while(fscanf(fp, "%d %d %d", &m, &n, &k) != EOF)
{
V = (int *) malloc(m*n*sizeof(int));
out = (int *) malloc(m*k*sizeof(int));
for(i=0; i<m*n; i++)
{
fscanf(fp, "%d", &V[i]);
}
// compute the execution time
hipEvent_t start, stop;
// create event
hipEventCreate(&start);
hipEventCreate(&stop);
// record event
hipEventRecord(start);
// allocate space for devices copies
hipMalloc((void **)&d_V, m*n*sizeof(int));
hipMalloc((void **)&d_out, m*k*sizeof(int));
hipMalloc((void **)&D, m*m*sizeof(int));
// copy host values to devices copies
hipMemcpy(d_V, V, m*n*sizeof(int), hipMemcpyHostToDevice);
int gridDimX = (int)(ceil((float)m/TILE_WIDTH));
int gridDimY = (int)(ceil((float)m/TILE_WIDTH));
dim3 grid(gridDimX, gridDimY);
dim3 block(TILE_WIDTH, TILE_WIDTH);
// launch knn() kernel on GPU
computeDist<<<grid, block>>>(m, n, d_V, D);
hipDeviceSynchronize();
int threadNum = (m<MAX_BLOCK_SIZE)? m: MAX_BLOCK_SIZE;
int ptrNumInSMEM = (m<MAX_PTRNUM_IN_SMEM)? m: MAX_PTRNUM_IN_SMEM;
knn<<<m, threadNum, 2*ptrNumInSMEM*sizeof(int)>>>(m, k, d_V, D, d_out);
// copy result back to host
hipMemcpy(out, d_out, m*k*sizeof(int), hipMemcpyDeviceToHost);
// cleanup
hipFree(d_V);
hipFree(d_out);
hipFree(D);
// record event and synchronize
hipEventRecord(stop);
hipEventSynchronize(stop);
float time;
// get event elapsed time
hipEventElapsedTime(&time, start, stop);
showResult(m, k, out);
if(m == 1024) {
printf("SMALL:");
} else if(m == 4096) {
printf("MIDDLE:");
} else if(m == 16384) {
printf("LARGE:");
}
printf("%f\n", time);
free(V);
free(out);
}
fclose(fp);
return 0;
}
|
.text
.file "knn.hip"
.globl _Z26__device_stub__computeDistiiPiS_ # -- Begin function _Z26__device_stub__computeDistiiPiS_
.p2align 4, 0x90
.type _Z26__device_stub__computeDistiiPiS_,@function
_Z26__device_stub__computeDistiiPiS_: # @_Z26__device_stub__computeDistiiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11computeDistiiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__computeDistiiPiS_, .Lfunc_end0-_Z26__device_stub__computeDistiiPiS_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__knniiPiS_S_ # -- Begin function _Z18__device_stub__knniiPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__knniiPiS_S_,@function
_Z18__device_stub__knniiPiS_S_: # @_Z18__device_stub__knniiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3knniiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__knniiPiS_S_, .Lfunc_end1-_Z18__device_stub__knniiPiS_S_
.cfi_endproc
# -- End function
.globl _Z10showResultiiPi # -- Begin function _Z10showResultiiPi
.p2align 4, 0x90
.type _Z10showResultiiPi,@function
_Z10showResultiiPi: # @_Z10showResultiiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, (%rsp) # 8-byte Spill
# kill: def $esi killed $esi def $rsi
testl %edi, %edi
jle .LBB2_8
# %bb.1: # %.preheader.lr.ph
leal -1(%rsi), %r15d
movl %edi, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl %esi, %r13d
xorl %ebp, %ebp
xorl %ebx, %ebx
movq %rsi, 16(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rbx
movq 16(%rsp), %rsi # 8-byte Reload
addl %esi, %ebp
cmpq 8(%rsp), %rbx # 8-byte Folded Reload
je .LBB2_8
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %esi, %esi
jle .LBB2_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r14d, %r14d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
incq %r14
cmpq %r14, %r13
je .LBB2_7
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpq %r14, %r15
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB2_6
.LBB2_8: # %._crit_edge15
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10showResultiiPi, .Lfunc_end2-_Z10showResultiiPi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB3_1
# %bb.3:
movq 8(%rsi), %rdi
movl $.L.str.3, %esi
callq fopen
testq %rax, %rax
je .LBB3_30
# %bb.4: # %.preheader
movq %rax, %r15
movq %rsp, %rdx
leaq 4(%rsp), %rcx
leaq 8(%rsp), %r8
movl $.L.str.5, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB3_29
# %bb.5: # %.lr.ph46
movabsq $4294967296, %rax # imm = 0x100000000
incq %rax
movq %rax, 200(%rsp) # 8-byte Spill
movq %r15, 136(%rsp) # 8-byte Spill
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_26: # in Loop: Header=BB3_6 Depth=1
movl $.L.str.9, %edi
.LBB3_27: # %.sink.split
# in Loop: Header=BB3_6 Depth=1
xorl %eax, %eax
callq printf
.LBB3_28: # in Loop: Header=BB3_6 Depth=1
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movl $.L.str.5, %esi
movq %r15, %rdi
movq %rsp, %rdx
leaq 4(%rsp), %rcx
leaq 8(%rsp), %r8
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB3_29
.LBB3_6: # =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
# Child Loop BB3_15 Depth 2
# Child Loop BB3_17 Depth 3
movslq (%rsp), %rbx
movslq 4(%rsp), %rdi
imulq %rbx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r12
movslq 8(%rsp), %rdi
imulq %rbx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl 4(%rsp), %eax
imull (%rsp), %eax
testl %eax, %eax
jle .LBB3_9
# %bb.7: # %.lr.ph.preheader
# in Loop: Header=BB3_6 Depth=1
movq %r12, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_8: # %.lr.ph
# Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.6, %esi
movq %r15, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbx
movslq (%rsp), %rax
movslq 4(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %rbx
jl .LBB3_8
.LBB3_9: # %._crit_edge
# in Loop: Header=BB3_6 Depth=1
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq (%rsp), %rax
movslq 4(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movl (%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movslq (%rsp), %rax
movslq 4(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl (%rsp), %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
imulq 200(%rsp), %rdi # 8-byte Folded Reload
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_6 Depth=1
movl (%rsp), %eax
movl 4(%rsp), %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movl %eax, 56(%rsp)
movl %ecx, 12(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z11computeDistiiPiS_, %edi
leaq 160(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11: # in Loop: Header=BB3_6 Depth=1
movq %r12, 144(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movl (%rsp), %edi
cmpl $256, %edi # imm = 0x100
movl $256, %edx # imm = 0x100
cmovll %edi, %edx
cmpl $1024, %edi # imm = 0x400
movl $1024, %eax # imm = 0x400
cmovll %edi, %eax
addl %eax, %eax
movslq %eax, %r8
shlq $2, %r8
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_6 Depth=1
movl (%rsp), %eax
movl 8(%rsp), %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
movl %eax, 12(%rsp)
movl %ecx, 132(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 132(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z3knniiPiS_S_, %edi
leaq 160(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_6 Depth=1
movq 48(%rsp), %rsi
movslq (%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 24(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 152(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movl (%rsp), %eax
movq %rax, 208(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB3_21
# %bb.14: # %.preheader.lr.ph.i
# in Loop: Header=BB3_6 Depth=1
movl 8(%rsp), %ebp
leal -1(%rbp), %r15d
xorl %r13d, %r13d
xorl %r12d, %r12d
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_20: # %._crit_edge.i
# in Loop: Header=BB3_15 Depth=2
incq %r12
addl %ebp, %r13d
cmpq 208(%rsp), %r12 # 8-byte Folded Reload
je .LBB3_21
.LBB3_15: # %.preheader.i
# Parent Loop BB3_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_17 Depth 3
testl %ebp, %ebp
jle .LBB3_20
# %bb.16: # %.lr.ph.i
# in Loop: Header=BB3_15 Depth=2
movl %r13d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
jmp .LBB3_17
.p2align 4, 0x90
.LBB3_19: # in Loop: Header=BB3_17 Depth=3
incq %r14
cmpq %r14, %rbp
je .LBB3_20
.LBB3_17: # Parent Loop BB3_6 Depth=1
# Parent Loop BB3_15 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpq %r14, %r15
jne .LBB3_19
# %bb.18: # in Loop: Header=BB3_17 Depth=3
movl $10, %edi
callq putchar@PLT
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_21: # %_Z10showResultiiPi.exit
# in Loop: Header=BB3_6 Depth=1
movl (%rsp), %eax
cmpl $1024, %eax # imm = 0x400
je .LBB3_22
# %bb.23: # %_Z10showResultiiPi.exit
# in Loop: Header=BB3_6 Depth=1
cmpl $16384, %eax # imm = 0x4000
movq 136(%rsp), %r15 # 8-byte Reload
movq 144(%rsp), %rbx # 8-byte Reload
je .LBB3_26
# %bb.24: # %_Z10showResultiiPi.exit
# in Loop: Header=BB3_6 Depth=1
cmpl $4096, %eax # imm = 0x1000
jne .LBB3_28
# %bb.25: # in Loop: Header=BB3_6 Depth=1
movl $.L.str.8, %edi
jmp .LBB3_27
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_6 Depth=1
movl $.L.str.7, %edi
movq 136(%rsp), %r15 # 8-byte Reload
movq 144(%rsp), %rbx # 8-byte Reload
jmp .LBB3_27
.LBB3_29: # %._crit_edge47
movq %r15, %rdi
callq fclose
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 272
movl $.Lstr.1, %edi
jmp .LBB3_2
.LBB3_30:
movl $.Lstr, %edi
.LBB3_2:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11computeDistiiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3knniiPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11computeDistiiPiS_,@object # @_Z11computeDistiiPiS_
.section .rodata,"a",@progbits
.globl _Z11computeDistiiPiS_
.p2align 3, 0x0
_Z11computeDistiiPiS_:
.quad _Z26__device_stub__computeDistiiPiS_
.size _Z11computeDistiiPiS_, 8
.type _Z3knniiPiS_S_,@object # @_Z3knniiPiS_S_
.globl _Z3knniiPiS_S_
.p2align 3, 0x0
_Z3knniiPiS_S_:
.quad _Z18__device_stub__knniiPiS_S_
.size _Z3knniiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d %d"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "SMALL:"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "MIDDLE:"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "LARGE:"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f\n"
.size .L.str.10, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11computeDistiiPiS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3knniiPiS_S_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error open input file!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: knn <inputfile>"
.size .Lstr.1, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__computeDistiiPiS_
.addrsig_sym _Z18__device_stub__knniiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11computeDistiiPiS_
.addrsig_sym _Z3knniiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00125834_00000000-6_knn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7findMiniiiPiS_
.type _Z7findMiniiiPiS_, @function
_Z7findMiniiiPiS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7findMiniiiPiS_, .-_Z7findMiniiiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl _Z10showResultiiPi
.type _Z10showResultiiPi, @function
_Z10showResultiiPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 20(%rsp)
movq %rdx, 24(%rsp)
testl %edi, %edi
jle .L5
movl %esi, %r15d
movl $0, 16(%rsp)
movl $0, 12(%rsp)
movslq %esi, %r14
leaq .LC0(%rip), %r13
jmp .L7
.L8:
addq $1, %rbx
cmpq %r14, %rbx
je .L11
.L9:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %ebx, %ebp
jne .L8
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L8
.L11:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
addl %r15d, 16(%rsp)
cmpl %eax, 20(%rsp)
je .L5
.L7:
testl %r15d, %r15d
jle .L11
movslq 16(%rsp), %rax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,4), %r12
movl $0, %ebx
leal -1(%r15), %ebp
jmp .L9
.L5:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10showResultiiPi, .-_Z10showResultiiPi
.globl _Z35__device_stub__Z11computeDistiiPiS_iiPiS_
.type _Z35__device_stub__Z11computeDistiiPiS_iiPiS_, @function
_Z35__device_stub__Z11computeDistiiPiS_iiPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11computeDistiiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11computeDistiiPiS_iiPiS_, .-_Z35__device_stub__Z11computeDistiiPiS_iiPiS_
.globl _Z11computeDistiiPiS_
.type _Z11computeDistiiPiS_, @function
_Z11computeDistiiPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11computeDistiiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11computeDistiiPiS_, .-_Z11computeDistiiPiS_
.globl _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
.type _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_, @function
_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3knniiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_, .-_Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
.globl _Z3knniiPiS_S_
.type _Z3knniiPiS_S_, @function
_Z3knniiPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3knniiPiS_S_, .-_Z3knniiPiS_S_
.section .rodata.str1.1
.LC2:
.string "Usage: knn <inputfile>\n"
.LC3:
.string "r"
.LC4:
.string "Error open input file!\n"
.LC5:
.string "%d"
.LC10:
.string "SMALL:"
.LC11:
.string "MIDDLE:"
.LC12:
.string "LARGE:"
.LC13:
.string "%f\n"
.LC14:
.string "%d %d %d"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L47
movq 8(%rsi), %rdi
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
testq %rax, %rax
jne .L32
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
cvttss2sil %xmm3, %eax
movl %eax, 56(%rsp)
movl %eax, 60(%rsp)
movl $32, 68(%rsp)
movl $32, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L36:
call cudaDeviceSynchronize@PLT
movl 4(%rsp), %eax
movl $256, %edx
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1024, %edx
cmpl %edx, %eax
cmovg %edx, %eax
addl %eax, %eax
cltq
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L37:
movl 4(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %r14, %rdx
movl 12(%rsp), %esi
movl 4(%rsp), %edi
call _Z10showResultiiPi
movl 4(%rsp), %eax
cmpl $1024, %eax
je .L50
cmpl $4096, %eax
je .L51
cmpl $16384, %eax
je .L52
.L39:
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
.L32:
leaq 8(%rsp), %rcx
leaq 4(%rsp), %rdx
leaq 12(%rsp), %r8
leaq .LC14(%rip), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L53
movl 4(%rsp), %ebx
movl %ebx, %ebp
imull 8(%rsp), %ebp
movslq %ebp, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r15
imull 12(%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebp, %ebp
jle .L33
movq %r15, %rbp
movl $0, %ebx
leaq .LC5(%rip), %r13
.L34:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 4(%rsp), %eax
imull 8(%rsp), %eax
cmpl %ebx, %eax
jg .L34
.L33:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 4(%rsp), %esi
imull 8(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %esi
imull %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %edx
imull 8(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC6(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC8(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC7(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L35
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm5
andps %xmm5, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
jmp .L35
.L48:
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl 8(%rsp), %esi
movl 4(%rsp), %edi
call _Z35__device_stub__Z11computeDistiiPiS_iiPiS_
jmp .L36
.L49:
movq 24(%rsp), %r8
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movl 12(%rsp), %esi
movl 4(%rsp), %edi
call _Z28__device_stub__Z3knniiPiS_S_iiPiS_S_
jmp .L37
.L50:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L51:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L52:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L39
.L53:
movq %r12, %rdi
call fclose@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z3knniiPiS_S_"
.LC17:
.string "_Z11computeDistiiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z3knniiPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z11computeDistiiPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1023410176
.align 4
.LC7:
.long 1258291200
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC9:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "knn.hip"
.globl _Z26__device_stub__computeDistiiPiS_ # -- Begin function _Z26__device_stub__computeDistiiPiS_
.p2align 4, 0x90
.type _Z26__device_stub__computeDistiiPiS_,@function
_Z26__device_stub__computeDistiiPiS_: # @_Z26__device_stub__computeDistiiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11computeDistiiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__computeDistiiPiS_, .Lfunc_end0-_Z26__device_stub__computeDistiiPiS_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__knniiPiS_S_ # -- Begin function _Z18__device_stub__knniiPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__knniiPiS_S_,@function
_Z18__device_stub__knniiPiS_S_: # @_Z18__device_stub__knniiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3knniiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z18__device_stub__knniiPiS_S_, .Lfunc_end1-_Z18__device_stub__knniiPiS_S_
.cfi_endproc
# -- End function
.globl _Z10showResultiiPi # -- Begin function _Z10showResultiiPi
.p2align 4, 0x90
.type _Z10showResultiiPi,@function
_Z10showResultiiPi: # @_Z10showResultiiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, (%rsp) # 8-byte Spill
# kill: def $esi killed $esi def $rsi
testl %edi, %edi
jle .LBB2_8
# %bb.1: # %.preheader.lr.ph
leal -1(%rsi), %r15d
movl %edi, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl %esi, %r13d
xorl %ebp, %ebp
xorl %ebx, %ebx
movq %rsi, 16(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rbx
movq 16(%rsp), %rsi # 8-byte Reload
addl %esi, %ebp
cmpq 8(%rsp), %rbx # 8-byte Folded Reload
je .LBB2_8
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %esi, %esi
jle .LBB2_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r14d, %r14d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
incq %r14
cmpq %r14, %r13
je .LBB2_7
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpq %r14, %r15
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB2_6
.LBB2_8: # %._crit_edge15
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10showResultiiPi, .Lfunc_end2-_Z10showResultiiPi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB3_1
# %bb.3:
movq 8(%rsi), %rdi
movl $.L.str.3, %esi
callq fopen
testq %rax, %rax
je .LBB3_30
# %bb.4: # %.preheader
movq %rax, %r15
movq %rsp, %rdx
leaq 4(%rsp), %rcx
leaq 8(%rsp), %r8
movl $.L.str.5, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB3_29
# %bb.5: # %.lr.ph46
movabsq $4294967296, %rax # imm = 0x100000000
incq %rax
movq %rax, 200(%rsp) # 8-byte Spill
movq %r15, 136(%rsp) # 8-byte Spill
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_26: # in Loop: Header=BB3_6 Depth=1
movl $.L.str.9, %edi
.LBB3_27: # %.sink.split
# in Loop: Header=BB3_6 Depth=1
xorl %eax, %eax
callq printf
.LBB3_28: # in Loop: Header=BB3_6 Depth=1
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movl $.L.str.5, %esi
movq %r15, %rdi
movq %rsp, %rdx
leaq 4(%rsp), %rcx
leaq 8(%rsp), %r8
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB3_29
.LBB3_6: # =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
# Child Loop BB3_15 Depth 2
# Child Loop BB3_17 Depth 3
movslq (%rsp), %rbx
movslq 4(%rsp), %rdi
imulq %rbx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r12
movslq 8(%rsp), %rdi
imulq %rbx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl 4(%rsp), %eax
imull (%rsp), %eax
testl %eax, %eax
jle .LBB3_9
# %bb.7: # %.lr.ph.preheader
# in Loop: Header=BB3_6 Depth=1
movq %r12, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_8: # %.lr.ph
# Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.6, %esi
movq %r15, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbx
movslq (%rsp), %rax
movslq 4(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %rbx
jl .LBB3_8
.LBB3_9: # %._crit_edge
# in Loop: Header=BB3_6 Depth=1
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq (%rsp), %rax
movslq 4(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq (%rsp), %rax
movslq 8(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movl (%rsp), %esi
imull %esi, %esi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movslq (%rsp), %rax
movslq 4(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
cvtsi2ssl (%rsp), %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
imulq 200(%rsp), %rdi # 8-byte Folded Reload
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_6 Depth=1
movl (%rsp), %eax
movl 4(%rsp), %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movl %eax, 56(%rsp)
movl %ecx, 12(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z11computeDistiiPiS_, %edi
leaq 160(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11: # in Loop: Header=BB3_6 Depth=1
movq %r12, 144(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movl (%rsp), %edi
cmpl $256, %edi # imm = 0x100
movl $256, %edx # imm = 0x100
cmovll %edi, %edx
cmpl $1024, %edi # imm = 0x400
movl $1024, %eax # imm = 0x400
cmovll %edi, %eax
addl %eax, %eax
movslq %eax, %r8
shlq $2, %r8
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12: # in Loop: Header=BB3_6 Depth=1
movl (%rsp), %eax
movl 8(%rsp), %ecx
movq 16(%rsp), %rdx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
movl %eax, 12(%rsp)
movl %ecx, 132(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 132(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z3knniiPiS_S_, %edi
leaq 160(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13: # in Loop: Header=BB3_6 Depth=1
movq 48(%rsp), %rsi
movslq (%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 24(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 152(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movl (%rsp), %eax
movq %rax, 208(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB3_21
# %bb.14: # %.preheader.lr.ph.i
# in Loop: Header=BB3_6 Depth=1
movl 8(%rsp), %ebp
leal -1(%rbp), %r15d
xorl %r13d, %r13d
xorl %r12d, %r12d
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_20: # %._crit_edge.i
# in Loop: Header=BB3_15 Depth=2
incq %r12
addl %ebp, %r13d
cmpq 208(%rsp), %r12 # 8-byte Folded Reload
je .LBB3_21
.LBB3_15: # %.preheader.i
# Parent Loop BB3_6 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_17 Depth 3
testl %ebp, %ebp
jle .LBB3_20
# %bb.16: # %.lr.ph.i
# in Loop: Header=BB3_15 Depth=2
movl %r13d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r14d, %r14d
jmp .LBB3_17
.p2align 4, 0x90
.LBB3_19: # in Loop: Header=BB3_17 Depth=3
incq %r14
cmpq %r14, %rbp
je .LBB3_20
.LBB3_17: # Parent Loop BB3_6 Depth=1
# Parent Loop BB3_15 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbx,%r14,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpq %r14, %r15
jne .LBB3_19
# %bb.18: # in Loop: Header=BB3_17 Depth=3
movl $10, %edi
callq putchar@PLT
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_21: # %_Z10showResultiiPi.exit
# in Loop: Header=BB3_6 Depth=1
movl (%rsp), %eax
cmpl $1024, %eax # imm = 0x400
je .LBB3_22
# %bb.23: # %_Z10showResultiiPi.exit
# in Loop: Header=BB3_6 Depth=1
cmpl $16384, %eax # imm = 0x4000
movq 136(%rsp), %r15 # 8-byte Reload
movq 144(%rsp), %rbx # 8-byte Reload
je .LBB3_26
# %bb.24: # %_Z10showResultiiPi.exit
# in Loop: Header=BB3_6 Depth=1
cmpl $4096, %eax # imm = 0x1000
jne .LBB3_28
# %bb.25: # in Loop: Header=BB3_6 Depth=1
movl $.L.str.8, %edi
jmp .LBB3_27
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_6 Depth=1
movl $.L.str.7, %edi
movq 136(%rsp), %r15 # 8-byte Reload
movq 144(%rsp), %rbx # 8-byte Reload
jmp .LBB3_27
.LBB3_29: # %._crit_edge47
movq %r15, %rdi
callq fclose
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 272
movl $.Lstr.1, %edi
jmp .LBB3_2
.LBB3_30:
movl $.Lstr, %edi
.LBB3_2:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11computeDistiiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3knniiPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11computeDistiiPiS_,@object # @_Z11computeDistiiPiS_
.section .rodata,"a",@progbits
.globl _Z11computeDistiiPiS_
.p2align 3, 0x0
_Z11computeDistiiPiS_:
.quad _Z26__device_stub__computeDistiiPiS_
.size _Z11computeDistiiPiS_, 8
.type _Z3knniiPiS_S_,@object # @_Z3knniiPiS_S_
.globl _Z3knniiPiS_S_
.p2align 3, 0x0
_Z3knniiPiS_S_:
.quad _Z18__device_stub__knniiPiS_S_
.size _Z3knniiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d %d"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "SMALL:"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "MIDDLE:"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "LARGE:"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%f\n"
.size .L.str.10, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11computeDistiiPiS_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3knniiPiS_S_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error open input file!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Usage: knn <inputfile>"
.size .Lstr.1, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__computeDistiiPiS_
.addrsig_sym _Z18__device_stub__knniiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11computeDistiiPiS_
.addrsig_sym _Z3knniiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//
// Created by xiezheng on 2020/9/8.
//
#include <iostream>
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <sys/time.h>
#include <math.h>
#define ROWS 1024
#define COLS 1024
//extern "C"
//{
//
//}
using namespace std;
__global__ void Plus(float A[], float B[], float C[],int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
C[i] = A[i] + B[i];
}
namespace test_cpu //在cpu计算
{
void add_cpu_demo()
{
float *A,*B,*C;
int n = 1024*1024;
int size = n * sizeof(float);
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
for (int j = 0; j < n; ++j) {
C[j] = A[j] + B[j];
}
float max_error = 0.0;
for (int k = 0; k < n; ++k) {
max_error += fabs(100.0 - C[k]);
}
std::cout << "max_error is " << max_error << std::endl;
delete A;
delete B;
delete C;
}
}
namespace test_gpu
{
void add_gpu_demo()
{
float *A, *B, *C, *Ad,*Bd,*Cd;
int n = 1024*1024;
int size = n* sizeof(int);
A = (float*)malloc(n* sizeof(float));
B = (float*)malloc(n* sizeof(float));
C = (float*)malloc(n* sizeof(float));
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
cudaMalloc((void**)&Ad,size);
cudaMalloc((void**)&Bd,size);
cudaMalloc((void**)&Cd,size);
cudaMemcpy(Ad,A,size,cudaMemcpyHostToDevice);
cudaMemcpy(Bd,B,size,cudaMemcpyHostToDevice);
cudaMemcpy(Cd,C,size,cudaMemcpyHostToDevice);
dim3 dimBlock(512);
dim3 dimGrid(n/512);
Plus<<<dimGrid,dimBlock>>>(Ad,Bd,Cd,n);
cudaMemcpy(C,Cd,size,cudaMemcpyHostToDevice);
// 校验误差
float max_error = 0.0;
for(int i=0;i<n;i++)
{
max_error += fabs(100.0 - C[i]);
}
cout << "max error is " << max_error << endl;
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Cd);
delete A;
delete B;
delete C;
}
}
int main()
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
std::cout<<"devices count = "<<deviceCount<<std::endl;
for (int i = 0; i < deviceCount; ++i) {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp,i);
std::cout << "使用GPU device " << i << ": " << devProp.name << std::endl;
std::cout << "设备全局内存总量： " << devProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl;
std::cout << "SM的数量：" << devProp.multiProcessorCount << std::endl;
std::cout << "每个线程块的共享内存大小：" << devProp.sharedMemPerBlock / 1024.0 << " KB" << std::endl;
std::cout << "每个线程块的最大线程数：" << devProp.maxThreadsPerBlock << std::endl;
std::cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << devProp.regsPerBlock << std::endl;
std::cout << "每个EM的最大线程数：" << devProp.maxThreadsPerMultiProcessor << std::endl;
std::cout << "每个EM的最大线程束数：" << devProp.maxThreadsPerMultiProcessor / 32 << std::endl;
std::cout << "设备上多处理器的数量： " << devProp.multiProcessorCount << std::endl;
std::cout << "======================================================" << std::endl;
}
struct timeval start,end;
gettimeofday(&start,NULL);
// test_cpu::add_cpu_demo();
test_gpu::add_gpu_demo();
gettimeofday( &end, NULL );
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
std::cout << "total time is " << timeuse/1000 << "ms" <<std::endl;
return 0;
}
|
code for sm_80
Function : _Z4PlusPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//
// Created by xiezheng on 2020/9/8.
//
#include <iostream>
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <sys/time.h>
#include <math.h>
#define ROWS 1024
#define COLS 1024
//extern "C"
//{
//
//}
using namespace std;
__global__ void Plus(float A[], float B[], float C[],int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
C[i] = A[i] + B[i];
}
namespace test_cpu //在cpu计算
{
void add_cpu_demo()
{
float *A,*B,*C;
int n = 1024*1024;
int size = n * sizeof(float);
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
for (int j = 0; j < n; ++j) {
C[j] = A[j] + B[j];
}
float max_error = 0.0;
for (int k = 0; k < n; ++k) {
max_error += fabs(100.0 - C[k]);
}
std::cout << "max_error is " << max_error << std::endl;
delete A;
delete B;
delete C;
}
}
namespace test_gpu
{
void add_gpu_demo()
{
float *A, *B, *C, *Ad,*Bd,*Cd;
int n = 1024*1024;
int size = n* sizeof(int);
A = (float*)malloc(n* sizeof(float));
B = (float*)malloc(n* sizeof(float));
C = (float*)malloc(n* sizeof(float));
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
cudaMalloc((void**)&Ad,size);
cudaMalloc((void**)&Bd,size);
cudaMalloc((void**)&Cd,size);
cudaMemcpy(Ad,A,size,cudaMemcpyHostToDevice);
cudaMemcpy(Bd,B,size,cudaMemcpyHostToDevice);
cudaMemcpy(Cd,C,size,cudaMemcpyHostToDevice);
dim3 dimBlock(512);
dim3 dimGrid(n/512);
Plus<<<dimGrid,dimBlock>>>(Ad,Bd,Cd,n);
cudaMemcpy(C,Cd,size,cudaMemcpyHostToDevice);
// 校验误差
float max_error = 0.0;
for(int i=0;i<n;i++)
{
max_error += fabs(100.0 - C[i]);
}
cout << "max error is " << max_error << endl;
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Cd);
delete A;
delete B;
delete C;
}
}
int main()
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
std::cout<<"devices count = "<<deviceCount<<std::endl;
for (int i = 0; i < deviceCount; ++i) {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp,i);
std::cout << "使用GPU device " << i << ": " << devProp.name << std::endl;
std::cout << "设备全局内存总量： " << devProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl;
std::cout << "SM的数量：" << devProp.multiProcessorCount << std::endl;
std::cout << "每个线程块的共享内存大小：" << devProp.sharedMemPerBlock / 1024.0 << " KB" << std::endl;
std::cout << "每个线程块的最大线程数：" << devProp.maxThreadsPerBlock << std::endl;
std::cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << devProp.regsPerBlock << std::endl;
std::cout << "每个EM的最大线程数：" << devProp.maxThreadsPerMultiProcessor << std::endl;
std::cout << "每个EM的最大线程束数：" << devProp.maxThreadsPerMultiProcessor / 32 << std::endl;
std::cout << "设备上多处理器的数量： " << devProp.multiProcessorCount << std::endl;
std::cout << "======================================================" << std::endl;
}
struct timeval start,end;
gettimeofday(&start,NULL);
// test_cpu::add_cpu_demo();
test_gpu::add_gpu_demo();
gettimeofday( &end, NULL );
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
std::cout << "total time is " << timeuse/1000 << "ms" <<std::endl;
return 0;
}
|
.file "tmpxft_0009dc19_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max_error is "
.text
.globl _ZN8test_cpu12add_cpu_demoEv
.type _ZN8test_cpu12add_cpu_demoEv, @function
_ZN8test_cpu12add_cpu_demoEv:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L4:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L4
movl $0, %eax
.L5:
movss 0(%rbp,%rax), %xmm0
addss (%rbx,%rax), %xmm0
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L5
movq %r12, %rax
leaq 4194304(%r12), %rdx
movl $0x00000000, 12(%rsp)
movsd .LC3(%rip), %xmm3
movq .LC4(%rip), %xmm2
.L6:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
movapd %xmm3, %xmm0
subsd %xmm1, %xmm0
andpd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 12(%rsp)
addq $4, %rax
cmpq %rax, %rdx
jne .L6
movl $13, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L14
cmpb $0, 56(%r14)
je .L8
movzbl 67(%r14), %eax
.L9:
movsbl %al, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L9
.cfi_endproc
.LFE3669:
.size _ZN8test_cpu12add_cpu_demoEv, .-_ZN8test_cpu12add_cpu_demoEv
.globl _Z28__device_stub__Z4PlusPfS_S_iPfS_S_i
.type _Z28__device_stub__Z4PlusPfS_S_iPfS_S_i, @function
_Z28__device_stub__Z4PlusPfS_S_iPfS_S_i:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4PlusPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z28__device_stub__Z4PlusPfS_S_iPfS_S_i, .-_Z28__device_stub__Z4PlusPfS_S_iPfS_S_i
.globl _Z4PlusPfS_S_i
.type _Z4PlusPfS_S_i, @function
_Z4PlusPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4PlusPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z4PlusPfS_S_i, .-_Z4PlusPfS_S_i
.section .rodata.str1.1
.LC6:
.string "max error is "
.text
.globl _ZN8test_gpu12add_gpu_demoEv
.type _ZN8test_gpu12add_gpu_demoEv, @function
_ZN8test_gpu12add_gpu_demoEv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L24:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L24
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $2048, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L25:
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rax
leaq 4194304(%r12), %rdx
movl $0x00000000, 12(%rsp)
movsd .LC3(%rip), %xmm3
movq .LC4(%rip), %xmm2
.L26:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
movapd %xmm3, %xmm0
subsd %xmm1, %xmm0
andpd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtss2sd 12(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 12(%rsp)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
movl $13, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L37
cmpb $0, 56(%r14)
je .L29
movzbl 67(%r14), %eax
.L30:
movsbl %al, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
testq %r12, %r12
je .L23
movl $4, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
.L23:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $1048576, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z28__device_stub__Z4PlusPfS_S_iPfS_S_i
jmp .L25
.L37:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L39
call _ZSt16__throw_bad_castv@PLT
.L39:
call __stack_chk_fail@PLT
.L29:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L30
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _ZN8test_gpu12add_gpu_demoEv, .-_ZN8test_gpu12add_gpu_demoEv
.section .rodata.str1.1
.LC7:
.string "devices count = "
.LC8:
.string "\344\275\277\347\224\250GPU device "
.LC9:
.string ": "
.LC10:
.string "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\232 "
.LC11:
.string "MB"
.LC12:
.string "SM\347\232\204\346\225\260\351\207\217\357\274\232"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC13:
.string "\346\257\217\344\270\252\347\272\277\347\250\213\345\235\227\347\232\204\345\205\261\344\272\253\345\206\205\345\255\230\345\244\247\345\260\217\357\274\232"
.section .rodata.str1.1
.LC15:
.string " KB"
.section .rodata.str1.8
.align 8
.LC16:
.string "\346\257\217\344\270\252\347\272\277\347\250\213\345\235\227\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\357\274\232"
.align 8
.LC17:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\347\247\215\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.section .rodata.str1.1
.LC18:
.string "\346\257\217\344\270\252EM\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\357\274\232"
.section .rodata.str1.8
.align 8
.LC19:
.string "\346\257\217\344\270\252EM\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\235\237\346\225\260\357\274\232"
.align 8
.LC20:
.string "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.align 8
.LC21:
.string "======================================================"
.section .rodata.str1.1
.LC22:
.string "total time is "
.LC23:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 12(%rsp)
jle .L41
movl $0, %r12d
leaq .LC8(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC9(%rip), %r13
jmp .L84
.L98:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L88
call _ZSt16__throw_bad_castv@PLT
.L88:
call __stack_chk_fail@PLT
.L44:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L99:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L89:
call __stack_chk_fail@PLT
.L48:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L49
.L100:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L90
call _ZSt16__throw_bad_castv@PLT
.L90:
call __stack_chk_fail@PLT
.L52:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L53
.L54:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L55
.L101:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L91
call _ZSt16__throw_bad_castv@PLT
.L91:
call __stack_chk_fail@PLT
.L58:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L59
.L102:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L92
call _ZSt16__throw_bad_castv@PLT
.L92:
call __stack_chk_fail@PLT
.L62:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L63
.L103:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L93
call _ZSt16__throw_bad_castv@PLT
.L93:
call __stack_chk_fail@PLT
.L66:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L67
.L104:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L94
call _ZSt16__throw_bad_castv@PLT
.L94:
call __stack_chk_fail@PLT
.L70:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L71
.L105:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L95
call _ZSt16__throw_bad_castv@PLT
.L95:
call __stack_chk_fail@PLT
.L74:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L75
.L106:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L96
call _ZSt16__throw_bad_castv@PLT
.L96:
call __stack_chk_fail@PLT
.L78:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L79
.L107:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L97
call _ZSt16__throw_bad_castv@PLT
.L97:
call __stack_chk_fail@PLT
.L82:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L83:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 12(%rsp)
jle .L41
.L84:
leaq 48(%rsp), %r15
movl %r12d, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $17, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L98
cmpb $0, 56(%r15)
je .L44
movzbl 67(%r15), %esi
.L45:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $28, %edx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 336(%rsp), %rsi
shrq $20, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC11(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L99
cmpb $0, 56(%r15)
je .L48
movzbl 67(%r15), %esi
.L49:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 436(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L100
cmpb $0, 56(%r15)
je .L52
movzbl 67(%r15), %esi
.L53:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $39, %edx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 344(%rsp), %rax
testq %rax, %rax
js .L54
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L55:
mulsd .LC14(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC15(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L101
cmpb $0, 56(%r15)
je .L58
movzbl 67(%r15), %esi
.L59:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $36, %edx
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 368(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L102
cmpb $0, 56(%r15)
je .L62
movzbl 67(%r15), %esi
.L63:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $71, %edx
leaq .LC17(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 352(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L103
cmpb $0, 56(%r15)
je .L66
movzbl 67(%r15), %esi
.L67:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $29, %edx
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 672(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L104
cmpb $0, 56(%r15)
je .L70
movzbl 67(%r15), %esi
.L71:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $32, %edx
leaq .LC19(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 672(%rsp), %eax
leal 31(%rax), %esi
testl %eax, %eax
cmovns %eax, %esi
sarl $5, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L105
cmpb $0, 56(%r15)
je .L74
movzbl 67(%r15), %esi
.L75:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $34, %edx
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 436(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L106
cmpb $0, 56(%r15)
je .L78
movzbl 67(%r15), %esi
.L79:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $54, %edx
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L107
cmpb $0, 56(%rbp)
je .L82
movzbl 67(%rbp), %esi
jmp .L83
.L41:
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
call _ZN8test_gpu12add_gpu_demoEv
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 32(%rsp), %rbx
subq 16(%rsp), %rbx
imull $1000000, %ebx, %ebx
subl 24(%rsp), %ebx
addl 40(%rsp), %ebx
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movslq %ebx, %rsi
imulq $274877907, %rsi, %rsi
sarq $38, %rsi
sarl $31, %ebx
subl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC23(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L108
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L108:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z4PlusPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z4PlusPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1119092736
.align 4
.LC2:
.long 1092616192
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1079574528
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC14:
.long 0
.long 1062207488
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//
// Created by xiezheng on 2020/9/8.
//
#include <iostream>
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <sys/time.h>
#include <math.h>
#define ROWS 1024
#define COLS 1024
//extern "C"
//{
//
//}
using namespace std;
__global__ void Plus(float A[], float B[], float C[],int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
C[i] = A[i] + B[i];
}
namespace test_cpu //在cpu计算
{
void add_cpu_demo()
{
float *A,*B,*C;
int n = 1024*1024;
int size = n * sizeof(float);
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
for (int j = 0; j < n; ++j) {
C[j] = A[j] + B[j];
}
float max_error = 0.0;
for (int k = 0; k < n; ++k) {
max_error += fabs(100.0 - C[k]);
}
std::cout << "max_error is " << max_error << std::endl;
delete A;
delete B;
delete C;
}
}
namespace test_gpu
{
void add_gpu_demo()
{
float *A, *B, *C, *Ad,*Bd,*Cd;
int n = 1024*1024;
int size = n* sizeof(int);
A = (float*)malloc(n* sizeof(float));
B = (float*)malloc(n* sizeof(float));
C = (float*)malloc(n* sizeof(float));
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
cudaMalloc((void**)&Ad,size);
cudaMalloc((void**)&Bd,size);
cudaMalloc((void**)&Cd,size);
cudaMemcpy(Ad,A,size,cudaMemcpyHostToDevice);
cudaMemcpy(Bd,B,size,cudaMemcpyHostToDevice);
cudaMemcpy(Cd,C,size,cudaMemcpyHostToDevice);
dim3 dimBlock(512);
dim3 dimGrid(n/512);
Plus<<<dimGrid,dimBlock>>>(Ad,Bd,Cd,n);
cudaMemcpy(C,Cd,size,cudaMemcpyHostToDevice);
// 校验误差
float max_error = 0.0;
for(int i=0;i<n;i++)
{
max_error += fabs(100.0 - C[i]);
}
cout << "max error is " << max_error << endl;
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Cd);
delete A;
delete B;
delete C;
}
}
int main()
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
std::cout<<"devices count = "<<deviceCount<<std::endl;
for (int i = 0; i < deviceCount; ++i) {
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp,i);
std::cout << "使用GPU device " << i << ": " << devProp.name << std::endl;
std::cout << "设备全局内存总量： " << devProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl;
std::cout << "SM的数量：" << devProp.multiProcessorCount << std::endl;
std::cout << "每个线程块的共享内存大小：" << devProp.sharedMemPerBlock / 1024.0 << " KB" << std::endl;
std::cout << "每个线程块的最大线程数：" << devProp.maxThreadsPerBlock << std::endl;
std::cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << devProp.regsPerBlock << std::endl;
std::cout << "每个EM的最大线程数：" << devProp.maxThreadsPerMultiProcessor << std::endl;
std::cout << "每个EM的最大线程束数：" << devProp.maxThreadsPerMultiProcessor / 32 << std::endl;
std::cout << "设备上多处理器的数量： " << devProp.multiProcessorCount << std::endl;
std::cout << "======================================================" << std::endl;
}
struct timeval start,end;
gettimeofday(&start,NULL);
// test_cpu::add_cpu_demo();
test_gpu::add_gpu_demo();
gettimeofday( &end, NULL );
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
std::cout << "total time is " << timeuse/1000 << "ms" <<std::endl;
return 0;
}
|
//
// Created by xiezheng on 2020/9/8.
//
#include <iostream>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <math.h>
#define ROWS 1024
#define COLS 1024
//extern "C"
//{
//
//}
using namespace std;
__global__ void Plus(float A[], float B[], float C[],int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
C[i] = A[i] + B[i];
}
namespace test_cpu //在cpu计算
{
void add_cpu_demo()
{
float *A,*B,*C;
int n = 1024*1024;
int size = n * sizeof(float);
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
for (int j = 0; j < n; ++j) {
C[j] = A[j] + B[j];
}
float max_error = 0.0;
for (int k = 0; k < n; ++k) {
max_error += fabs(100.0 - C[k]);
}
std::cout << "max_error is " << max_error << std::endl;
delete A;
delete B;
delete C;
}
}
namespace test_gpu
{
void add_gpu_demo()
{
float *A, *B, *C, *Ad,*Bd,*Cd;
int n = 1024*1024;
int size = n* sizeof(int);
A = (float*)malloc(n* sizeof(float));
B = (float*)malloc(n* sizeof(float));
C = (float*)malloc(n* sizeof(float));
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
hipMalloc((void**)&Ad,size);
hipMalloc((void**)&Bd,size);
hipMalloc((void**)&Cd,size);
hipMemcpy(Ad,A,size,hipMemcpyHostToDevice);
hipMemcpy(Bd,B,size,hipMemcpyHostToDevice);
hipMemcpy(Cd,C,size,hipMemcpyHostToDevice);
dim3 dimBlock(512);
dim3 dimGrid(n/512);
Plus<<<dimGrid,dimBlock>>>(Ad,Bd,Cd,n);
hipMemcpy(C,Cd,size,hipMemcpyHostToDevice);
// 校验误差
float max_error = 0.0;
for(int i=0;i<n;i++)
{
max_error += fabs(100.0 - C[i]);
}
cout << "max error is " << max_error << endl;
hipFree(Ad);
hipFree(Bd);
hipFree(Cd);
delete A;
delete B;
delete C;
}
}
int main()
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
std::cout<<"devices count = "<<deviceCount<<std::endl;
for (int i = 0; i < deviceCount; ++i) {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp,i);
std::cout << "使用GPU device " << i << ": " << devProp.name << std::endl;
std::cout << "设备全局内存总量： " << devProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl;
std::cout << "SM的数量：" << devProp.multiProcessorCount << std::endl;
std::cout << "每个线程块的共享内存大小：" << devProp.sharedMemPerBlock / 1024.0 << " KB" << std::endl;
std::cout << "每个线程块的最大线程数：" << devProp.maxThreadsPerBlock << std::endl;
std::cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << devProp.regsPerBlock << std::endl;
std::cout << "每个EM的最大线程数：" << devProp.maxThreadsPerMultiProcessor << std::endl;
std::cout << "每个EM的最大线程束数：" << devProp.maxThreadsPerMultiProcessor / 32 << std::endl;
std::cout << "设备上多处理器的数量： " << devProp.multiProcessorCount << std::endl;
std::cout << "======================================================" << std::endl;
}
struct timeval start,end;
gettimeofday(&start,NULL);
// test_cpu::add_cpu_demo();
test_gpu::add_gpu_demo();
gettimeofday( &end, NULL );
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
std::cout << "total time is " << timeuse/1000 << "ms" <<std::endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
//
// Created by xiezheng on 2020/9/8.
//
#include <iostream>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <math.h>
#define ROWS 1024
#define COLS 1024
//extern "C"
//{
//
//}
using namespace std;
__global__ void Plus(float A[], float B[], float C[],int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
C[i] = A[i] + B[i];
}
namespace test_cpu //在cpu计算
{
void add_cpu_demo()
{
float *A,*B,*C;
int n = 1024*1024;
int size = n * sizeof(float);
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
for (int j = 0; j < n; ++j) {
C[j] = A[j] + B[j];
}
float max_error = 0.0;
for (int k = 0; k < n; ++k) {
max_error += fabs(100.0 - C[k]);
}
std::cout << "max_error is " << max_error << std::endl;
delete A;
delete B;
delete C;
}
}
namespace test_gpu
{
void add_gpu_demo()
{
float *A, *B, *C, *Ad,*Bd,*Cd;
int n = 1024*1024;
int size = n* sizeof(int);
A = (float*)malloc(n* sizeof(float));
B = (float*)malloc(n* sizeof(float));
C = (float*)malloc(n* sizeof(float));
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
hipMalloc((void**)&Ad,size);
hipMalloc((void**)&Bd,size);
hipMalloc((void**)&Cd,size);
hipMemcpy(Ad,A,size,hipMemcpyHostToDevice);
hipMemcpy(Bd,B,size,hipMemcpyHostToDevice);
hipMemcpy(Cd,C,size,hipMemcpyHostToDevice);
dim3 dimBlock(512);
dim3 dimGrid(n/512);
Plus<<<dimGrid,dimBlock>>>(Ad,Bd,Cd,n);
hipMemcpy(C,Cd,size,hipMemcpyHostToDevice);
// 校验误差
float max_error = 0.0;
for(int i=0;i<n;i++)
{
max_error += fabs(100.0 - C[i]);
}
cout << "max error is " << max_error << endl;
hipFree(Ad);
hipFree(Bd);
hipFree(Cd);
delete A;
delete B;
delete C;
}
}
int main()
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
std::cout<<"devices count = "<<deviceCount<<std::endl;
for (int i = 0; i < deviceCount; ++i) {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp,i);
std::cout << "使用GPU device " << i << ": " << devProp.name << std::endl;
std::cout << "设备全局内存总量： " << devProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl;
std::cout << "SM的数量：" << devProp.multiProcessorCount << std::endl;
std::cout << "每个线程块的共享内存大小：" << devProp.sharedMemPerBlock / 1024.0 << " KB" << std::endl;
std::cout << "每个线程块的最大线程数：" << devProp.maxThreadsPerBlock << std::endl;
std::cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << devProp.regsPerBlock << std::endl;
std::cout << "每个EM的最大线程数：" << devProp.maxThreadsPerMultiProcessor << std::endl;
std::cout << "每个EM的最大线程束数：" << devProp.maxThreadsPerMultiProcessor / 32 << std::endl;
std::cout << "设备上多处理器的数量： " << devProp.multiProcessorCount << std::endl;
std::cout << "======================================================" << std::endl;
}
struct timeval start,end;
gettimeofday(&start,NULL);
// test_cpu::add_cpu_demo();
test_gpu::add_gpu_demo();
gettimeofday( &end, NULL );
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
std::cout << "total time is " << timeuse/1000 << "ms" <<std::endl;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4PlusPfS_S_i
.globl _Z4PlusPfS_S_i
.p2align 8
.type _Z4PlusPfS_S_i,@function
_Z4PlusPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4PlusPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4PlusPfS_S_i, .Lfunc_end0-_Z4PlusPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4PlusPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4PlusPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
//
// Created by xiezheng on 2020/9/8.
//
#include <iostream>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#include <math.h>
#define ROWS 1024
#define COLS 1024
//extern "C"
//{
//
//}
using namespace std;
__global__ void Plus(float A[], float B[], float C[],int n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
C[i] = A[i] + B[i];
}
namespace test_cpu //在cpu计算
{
void add_cpu_demo()
{
float *A,*B,*C;
int n = 1024*1024;
int size = n * sizeof(float);
A = (float*)malloc(size);
B = (float*)malloc(size);
C = (float*)malloc(size);
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
for (int j = 0; j < n; ++j) {
C[j] = A[j] + B[j];
}
float max_error = 0.0;
for (int k = 0; k < n; ++k) {
max_error += fabs(100.0 - C[k]);
}
std::cout << "max_error is " << max_error << std::endl;
delete A;
delete B;
delete C;
}
}
namespace test_gpu
{
void add_gpu_demo()
{
float *A, *B, *C, *Ad,*Bd,*Cd;
int n = 1024*1024;
int size = n* sizeof(int);
A = (float*)malloc(n* sizeof(float));
B = (float*)malloc(n* sizeof(float));
C = (float*)malloc(n* sizeof(float));
for (int i = 0; i < n; ++i) {
A[i] = 90.0;
B[i] = 10.0;
}
hipMalloc((void**)&Ad,size);
hipMalloc((void**)&Bd,size);
hipMalloc((void**)&Cd,size);
hipMemcpy(Ad,A,size,hipMemcpyHostToDevice);
hipMemcpy(Bd,B,size,hipMemcpyHostToDevice);
hipMemcpy(Cd,C,size,hipMemcpyHostToDevice);
dim3 dimBlock(512);
dim3 dimGrid(n/512);
Plus<<<dimGrid,dimBlock>>>(Ad,Bd,Cd,n);
hipMemcpy(C,Cd,size,hipMemcpyHostToDevice);
// 校验误差
float max_error = 0.0;
for(int i=0;i<n;i++)
{
max_error += fabs(100.0 - C[i]);
}
cout << "max error is " << max_error << endl;
hipFree(Ad);
hipFree(Bd);
hipFree(Cd);
delete A;
delete B;
delete C;
}
}
int main()
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
std::cout<<"devices count = "<<deviceCount<<std::endl;
for (int i = 0; i < deviceCount; ++i) {
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp,i);
std::cout << "使用GPU device " << i << ": " << devProp.name << std::endl;
std::cout << "设备全局内存总量： " << devProp.totalGlobalMem / 1024 / 1024 << "MB" << std::endl;
std::cout << "SM的数量：" << devProp.multiProcessorCount << std::endl;
std::cout << "每个线程块的共享内存大小：" << devProp.sharedMemPerBlock / 1024.0 << " KB" << std::endl;
std::cout << "每个线程块的最大线程数：" << devProp.maxThreadsPerBlock << std::endl;
std::cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << devProp.regsPerBlock << std::endl;
std::cout << "每个EM的最大线程数：" << devProp.maxThreadsPerMultiProcessor << std::endl;
std::cout << "每个EM的最大线程束数：" << devProp.maxThreadsPerMultiProcessor / 32 << std::endl;
std::cout << "设备上多处理器的数量： " << devProp.multiProcessorCount << std::endl;
std::cout << "======================================================" << std::endl;
}
struct timeval start,end;
gettimeofday(&start,NULL);
// test_cpu::add_cpu_demo();
test_gpu::add_gpu_demo();
gettimeofday( &end, NULL );
int timeuse = 1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
std::cout << "total time is " << timeuse/1000 << "ms" <<std::endl;
return 0;
}
|
.text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__PlusPfS_S_i # -- Begin function _Z19__device_stub__PlusPfS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__PlusPfS_S_i,@function
_Z19__device_stub__PlusPfS_S_i: # @_Z19__device_stub__PlusPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4PlusPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__PlusPfS_S_i, .Lfunc_end0-_Z19__device_stub__PlusPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN8test_cpu12add_cpu_demoEv
.LCPI1_0:
.quad 0x4059000000000000 # double 100
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _ZN8test_cpu12add_cpu_demoEv
.p2align 4, 0x90
.type _ZN8test_cpu12add_cpu_demoEv,@function
_ZN8test_cpu12add_cpu_demoEv: # @_ZN8test_cpu12add_cpu_demoEv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1119092736, (%r15,%rax,4) # imm = 0x42B40000
movl $1092616192, (%r14,%rax,4) # imm = 0x41200000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2: # %.preheader35.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader35
# =>This Inner Loop Header: Depth=1
movss (%r15,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorps %xmm4, %xmm4
xorl %eax, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movapd %xmm0, %xmm3
subsd %xmm2, %xmm3
andpd %xmm1, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm4, %xmm2
addsd %xmm3, %xmm2
xorps %xmm4, %xmm4
cvtsd2ss %xmm2, %xmm4
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
movss %xmm4, 12(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_16
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_9
# %bb.8:
movzbl 67(%r12), %ecx
jmp .LBB1_10
.LBB1_9:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testq %r15, %r15
je .LBB1_12
# %bb.11:
movq %r15, %rdi
callq _ZdlPv
.LBB1_12:
testq %r14, %r14
je .LBB1_14
# %bb.13:
movq %r14, %rdi
callq _ZdlPv
.LBB1_14:
testq %rbx, %rbx
je .LBB1_15
# %bb.17:
movq %rbx, %rdi
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB1_15:
.cfi_def_cfa_offset 64
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _ZN8test_cpu12add_cpu_demoEv, .Lfunc_end1-_ZN8test_cpu12add_cpu_demoEv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN8test_gpu12add_gpu_demoEv
.LCPI2_0:
.quad 0x4059000000000000 # double 100
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _ZN8test_gpu12add_gpu_demoEv
.p2align 4, 0x90
.type _ZN8test_gpu12add_gpu_demoEv,@function
_ZN8test_gpu12add_gpu_demoEv: # @_ZN8test_gpu12add_gpu_demoEv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1119092736, (%r15,%rax,4) # imm = 0x42B40000
movl $1092616192, (%r14,%rax,4) # imm = 0x41200000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1536(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1048576, 36(%rsp) # imm = 0x100000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z4PlusPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $1, %ecx
callq hipMemcpy
xorps %xmm4, %xmm4
xorl %eax, %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI2_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movapd %xmm0, %xmm3
subsd %xmm2, %xmm3
andpd %xmm1, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm4, %xmm2
addsd %xmm3, %xmm2
xorps %xmm4, %xmm4
cvtsd2ss %xmm2, %xmm4
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
movss %xmm4, 32(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_17
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB2_9
# %bb.8:
movzbl 67(%r12), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testq %r15, %r15
je .LBB2_12
# %bb.11:
movq %r15, %rdi
callq _ZdlPv
.LBB2_12:
testq %r14, %r14
je .LBB2_14
# %bb.13:
movq %r14, %rdi
callq _ZdlPv
.LBB2_14:
testq %rbx, %rbx
je .LBB2_16
# %bb.15:
movq %rbx, %rdi
callq _ZdlPv
.LBB2_16:
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _ZN8test_gpu12add_gpu_demoEv, .Lfunc_end2-_ZN8test_gpu12add_gpu_demoEv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1536
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_52
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 4(%rsp)
jle .LBB3_9
# %bb.5: # %.lr.ph
xorl %ebx, %ebx
leaq 24(%rsp), %r14
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_50: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_51: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB3_9
.LBB3_6: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.4, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_52
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r12)
je .LBB3_14
# %bb.8: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_15
.p2align 4, 0x90
.LBB3_14: # in Loop: Header=BB3_6 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit14
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 312(%rsp), %rsi
shrq $20, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_52
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r12)
je .LBB3_18
# %bb.17: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_6 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 412(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_52
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_22
# %bb.21: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_23
.p2align 4, 0x90
.LBB3_22: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
# in Loop: Header=BB3_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 320(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI3_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI3_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.9, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB3_52
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i26
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r12)
je .LBB3_26
# %bb.25: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r12), %eax
jmp .LBB3_27
.p2align 4, 0x90
.LBB3_26: # in Loop: Header=BB3_6 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit29
# in Loop: Header=BB3_6 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $36, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 344(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_52
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i31
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_30
# %bb.29: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_31
.p2align 4, 0x90
.LBB3_30: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit34
# in Loop: Header=BB3_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $71, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_52
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i36
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_34
# %bb.33: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_35
.p2align 4, 0x90
.LBB3_34: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit39
# in Loop: Header=BB3_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 648(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_52
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_38
# %bb.37: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_39
.p2align 4, 0x90
.LBB3_38: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
# in Loop: Header=BB3_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 648(%rsp), %eax
leal 31(%rax), %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $5, %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_52
# %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_42
# %bb.41: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_43
.p2align 4, 0x90
.LBB3_42: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_43: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
# in Loop: Header=BB3_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 412(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_52
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_46
# %bb.45: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB3_47
.p2align 4, 0x90
.LBB3_46: # in Loop: Header=BB3_6 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
# in Loop: Header=BB3_6 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $54, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_52
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
# in Loop: Header=BB3_6 Depth=1
cmpb $0, 56(%r15)
je .LBB3_50
# %bb.49: # in Loop: Header=BB3_6 Depth=1
movzbl 67(%r15), %eax
jmp .LBB3_51
.LBB3_9: # %._crit_edge
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
callq _ZN8test_gpu12add_gpu_demoEv
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 8(%rsp), %eax
subl 24(%rsp), %eax
imull $1000000, %eax, %ebx # imm = 0xF4240
addl 16(%rsp), %ebx
subl 32(%rsp), %ebx
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq %ebx, %rax
imulq $274877907, %rax, %rsi # imm = 0x10624DD3
movq %rsi, %rax
shrq $63, %rax
sarq $38, %rsi
addl %eax, %esi
movl $_ZSt4cout, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.17, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_52
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i6
cmpb $0, 56(%r14)
je .LBB3_12
# %bb.11:
movzbl 67(%r14), %eax
jmp .LBB3_13
.LBB3_12:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit9
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_52:
.cfi_def_cfa_offset 1536
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4PlusPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4PlusPfS_S_i,@object # @_Z4PlusPfS_S_i
.section .rodata,"a",@progbits
.globl _Z4PlusPfS_S_i
.p2align 3, 0x0
_Z4PlusPfS_S_i:
.quad _Z19__device_stub__PlusPfS_S_i
.size _Z4PlusPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max_error is "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "max error is "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "devices count = "
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\344\275\277\347\224\250GPU device "
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ": "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\232 "
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "MB"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "SM\347\232\204\346\225\260\351\207\217\357\274\232"
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\346\257\217\344\270\252\347\272\277\347\250\213\345\235\227\347\232\204\345\205\261\344\272\253\345\206\205\345\255\230\345\244\247\345\260\217\357\274\232"
.size .L.str.8, 40
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " KB"
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\346\257\217\344\270\252\347\272\277\347\250\213\345\235\227\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\357\274\232"
.size .L.str.10, 37
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\347\247\215\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.size .L.str.11, 72
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\346\257\217\344\270\252EM\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\357\274\232"
.size .L.str.12, 30
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\346\257\217\344\270\252EM\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\235\237\346\225\260\357\274\232"
.size .L.str.13, 33
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "======================================================"
.size .L.str.15, 55
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "total time is "
.size .L.str.16, 15
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "ms"
.size .L.str.17, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4PlusPfS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__PlusPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4PlusPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4PlusPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4PlusPfS_S_i
.globl _Z4PlusPfS_S_i
.p2align 8
.type _Z4PlusPfS_S_i,@function
_Z4PlusPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4PlusPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4PlusPfS_S_i, .Lfunc_end0-_Z4PlusPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4PlusPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4PlusPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// wave 1D GPU
// compile: nvcc -arch=sm_70 -O3 wave_1D.cu
// run: ./a.out
#include "stdio.h"
#include "stdlib.h"
#include "math.h"
#include "cuda.h"
#define DAT double
#define GPU_ID 0 // typically 4 (0-3) on machines at stanford
#define BLOCK_X 100
#define GRID_X 1
#define OVERLENGTH 1 //needed for extra staggered grid
#define zeros(A,N) DAT *A##_d,*A##_h; A##_h = (DAT*)malloc((N)*sizeof(DAT)); \
for(i=0; i < (N); i++){ A##_h[i]=(DAT)0.0; } \
cudaMalloc(&A##_d ,(N)*sizeof(DAT)); \
cudaMemcpy( A##_d,A##_h,(N)*sizeof(DAT),cudaMemcpyHostToDevice);
#define free_all(A) free(A##_h); cudaFree(A##_d);
#define gather(A,N) cudaMemcpy( A##_h,A##_d,(N)*sizeof(DAT),cudaMemcpyDeviceToHost);
void save_array(DAT* A, int N, const char A_name[]){
char* fname; FILE* fid; asprintf(&fname, "%s.dat" , A_name);
fid=fopen(fname, "wb"); fwrite(A, sizeof(DAT), N, fid); fclose(fid); free(fname);
}
#define SaveArray(A,N,A_name) gather(A,N); save_array(A##_h, N, A_name);
void clean_cuda(){
cudaError_t ce = cudaGetLastError();
if(ce != cudaSuccess){ printf("ERROR launching GPU C-CUDA program: %s\n", cudaGetErrorString(ce)); cudaDeviceReset();}
}
// --------------------------------------------------------------------- //
// Physics
const DAT Lx = 10.0;
const DAT k = 1.0;
const DAT rho = 1.0;
// Numerics
const int nx = BLOCK_X*GRID_X-OVERLENGTH;
const int nt = 200;
const DAT dx = Lx/((DAT)nx);
const DAT dt = dx/sqrt(k/rho)/2.1;
// Computing physics kernels
__global__ void init(DAT* x, DAT* P, const DAT Lx, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ x[ix] = (DAT)ix*dx + (-Lx+dx)/2.0; }
if (ix<nx){ P[ix] = exp(-(x[ix]*x[ix])); }
}
__global__ void compute_V(DAT* V, DAT* P, const DAT dt, const DAT rho, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix>0 && ix<nx){ V[ix] = V[ix] - dt*(P[ix]-P[ix-1])/dx/rho; }
}
__global__ void compute_P(DAT* V, DAT* P, const DAT dt, const DAT k, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ P[ix] = P[ix] - dt*(V[ix+1]-V[ix])/dx*k; }
}
int main(){
int i, it;
// Set up GPU
int gpu_id=-1;
dim3 grid, block;
block.x = BLOCK_X; grid.x = GRID_X;
gpu_id = GPU_ID; cudaSetDevice(gpu_id); cudaGetDevice(&gpu_id);
cudaDeviceReset(); cudaDeviceSetCacheConfig(cudaFuncCachePreferL1); // set L1 to prefered
printf("Process uses GPU with id %d .\n",gpu_id);
// Initial arrays
zeros(x,nx );
zeros(P,nx );
zeros(V,nx+1);
// Initial conditions
init<<<grid,block>>>(x_d, P_d, Lx, dx, nx); cudaDeviceSynchronize();
// Action
for (it=0;it<nt;it++){
compute_V<<<grid,block>>>(V_d, P_d, dt, rho, dx, nx); cudaDeviceSynchronize();
compute_P<<<grid,block>>>(V_d, P_d, dt, k , dx, nx); cudaDeviceSynchronize();
}//it
SaveArray(P,nx,"P_c");
free_all(x);
free_all(P);
free_all(V);
clean_cuda();
}
|
.file "tmpxft_000f8c27_00000000-6_wave_1D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s.dat"
.LC1:
.string "wb"
.text
.globl _Z10save_arrayPdiPKc
.type _Z10save_arrayPdiPKc, @function
_Z10save_arrayPdiPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebx
movq %rdx, %rcx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
leaq .LC0(%rip), %rdx
movl $2, %esi
call __asprintf_chk@PLT
leaq .LC1(%rip), %rsi
movq (%rsp), %rdi
call fopen@PLT
movq %rax, %rbp
movslq %ebx, %rdx
movq %rax, %rcx
movl $8, %esi
movq %r12, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10save_arrayPdiPKc, .-_Z10save_arrayPdiPKc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "ERROR launching GPU C-CUDA program: %s\n"
.text
.globl _Z10clean_cudav
.type _Z10clean_cudav, @function
_Z10clean_cudav:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L10
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z10clean_cudav, .-_Z10clean_cudav
.globl _Z28__device_stub__Z4initPdS_ddiPdS_ddi
.type _Z28__device_stub__Z4initPdS_ddiPdS_ddi, @function
_Z28__device_stub__Z4initPdS_ddiPdS_ddi:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4initPdS_ddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z4initPdS_ddiPdS_ddi, .-_Z28__device_stub__Z4initPdS_ddiPdS_ddi
.globl _Z4initPdS_ddi
.type _Z4initPdS_ddi, @function
_Z4initPdS_ddi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4initPdS_ddiPdS_ddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4initPdS_ddi, .-_Z4initPdS_ddi
.globl _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
.type _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi, @function
_Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9compute_VPdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi, .-_Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
.globl _Z9compute_VPdS_dddi
.type _Z9compute_VPdS_dddi, @function
_Z9compute_VPdS_dddi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9compute_VPdS_dddi, .-_Z9compute_VPdS_dddi
.globl _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
.type _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi, @function
_Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9compute_PPdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi, .-_Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
.globl _Z9compute_PPdS_dddi
.type _Z9compute_PPdS_dddi, @function
_Z9compute_PPdS_dddi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z9compute_PPdS_dddi, .-_Z9compute_PPdS_dddi
.section .rodata.str1.8
.align 8
.LC3:
.string "Process uses GPU with id %d .\n"
.section .rodata.str1.1
.LC9:
.string "P_c"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $100, 44(%rsp)
movl $0, 4(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
call cudaDeviceReset@PLT
movl $2, %edi
call cudaDeviceSetCacheConfig@PLT
movl 4(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $792, %edi
call malloc@PLT
movq %rax, %rbp
leaq 792(%rax), %rdx
.L36:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $792, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $792, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $792, %edi
call malloc@PLT
movq %rax, %r12
leaq 792(%rax), %rdx
.L37:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L37
leaq 16(%rsp), %rdi
movl $792, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $792, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $800, %edi
call malloc@PLT
movq %rax, %r13
leaq 800(%rax), %rdx
.L38:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L38
leaq 24(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $800, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L39:
call cudaDeviceSynchronize@PLT
movl $200, %ebx
jmp .L42
.L49:
movl $99, %edx
movsd .LC5(%rip), %xmm1
movsd .LC6(%rip), %xmm0
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z4initPdS_ddiPdS_ddi
jmp .L39
.L51:
movl $99, %edx
movsd .LC5(%rip), %xmm2
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
jmp .L40
.L41:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L50
.L42:
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L40:
call cudaDeviceSynchronize@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movl $99, %edx
movsd .LC5(%rip), %xmm2
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
jmp .L41
.L50:
movl $2, %ecx
movl $792, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rdx
movl $99, %esi
movq %r12, %rdi
call _Z10save_arrayPdiPKc
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call _Z10clean_cudav
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z9compute_PPdS_dddi"
.LC11:
.string "_Z9compute_VPdS_dddi"
.LC12:
.string "_Z4initPdS_ddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9compute_PPdS_dddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9compute_VPdS_dddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPdS_ddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 1214738225
.long 1069145036
.align 8
.LC6:
.long 0
.long 1076101120
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC8:
.long -888328975
.long 1068015761
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// wave 1D GPU
// compile: nvcc -arch=sm_70 -O3 wave_1D.cu
// run: ./a.out
#include "stdio.h"
#include "stdlib.h"
#include "math.h"
#include "cuda.h"
#define DAT double
#define GPU_ID 0 // typically 4 (0-3) on machines at stanford
#define BLOCK_X 100
#define GRID_X 1
#define OVERLENGTH 1 //needed for extra staggered grid
#define zeros(A,N) DAT *A##_d,*A##_h; A##_h = (DAT*)malloc((N)*sizeof(DAT)); \
for(i=0; i < (N); i++){ A##_h[i]=(DAT)0.0; } \
cudaMalloc(&A##_d ,(N)*sizeof(DAT)); \
cudaMemcpy( A##_d,A##_h,(N)*sizeof(DAT),cudaMemcpyHostToDevice);
#define free_all(A) free(A##_h); cudaFree(A##_d);
#define gather(A,N) cudaMemcpy( A##_h,A##_d,(N)*sizeof(DAT),cudaMemcpyDeviceToHost);
void save_array(DAT* A, int N, const char A_name[]){
char* fname; FILE* fid; asprintf(&fname, "%s.dat" , A_name);
fid=fopen(fname, "wb"); fwrite(A, sizeof(DAT), N, fid); fclose(fid); free(fname);
}
#define SaveArray(A,N,A_name) gather(A,N); save_array(A##_h, N, A_name);
void clean_cuda(){
cudaError_t ce = cudaGetLastError();
if(ce != cudaSuccess){ printf("ERROR launching GPU C-CUDA program: %s\n", cudaGetErrorString(ce)); cudaDeviceReset();}
}
// --------------------------------------------------------------------- //
// Physics
const DAT Lx = 10.0;
const DAT k = 1.0;
const DAT rho = 1.0;
// Numerics
const int nx = BLOCK_X*GRID_X-OVERLENGTH;
const int nt = 200;
const DAT dx = Lx/((DAT)nx);
const DAT dt = dx/sqrt(k/rho)/2.1;
// Computing physics kernels
__global__ void init(DAT* x, DAT* P, const DAT Lx, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ x[ix] = (DAT)ix*dx + (-Lx+dx)/2.0; }
if (ix<nx){ P[ix] = exp(-(x[ix]*x[ix])); }
}
__global__ void compute_V(DAT* V, DAT* P, const DAT dt, const DAT rho, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix>0 && ix<nx){ V[ix] = V[ix] - dt*(P[ix]-P[ix-1])/dx/rho; }
}
__global__ void compute_P(DAT* V, DAT* P, const DAT dt, const DAT k, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ P[ix] = P[ix] - dt*(V[ix+1]-V[ix])/dx*k; }
}
int main(){
int i, it;
// Set up GPU
int gpu_id=-1;
dim3 grid, block;
block.x = BLOCK_X; grid.x = GRID_X;
gpu_id = GPU_ID; cudaSetDevice(gpu_id); cudaGetDevice(&gpu_id);
cudaDeviceReset(); cudaDeviceSetCacheConfig(cudaFuncCachePreferL1); // set L1 to prefered
printf("Process uses GPU with id %d .\n",gpu_id);
// Initial arrays
zeros(x,nx );
zeros(P,nx );
zeros(V,nx+1);
// Initial conditions
init<<<grid,block>>>(x_d, P_d, Lx, dx, nx); cudaDeviceSynchronize();
// Action
for (it=0;it<nt;it++){
compute_V<<<grid,block>>>(V_d, P_d, dt, rho, dx, nx); cudaDeviceSynchronize();
compute_P<<<grid,block>>>(V_d, P_d, dt, k , dx, nx); cudaDeviceSynchronize();
}//it
SaveArray(P,nx,"P_c");
free_all(x);
free_all(P);
free_all(V);
clean_cuda();
}
|
// wave 1D GPU
// compile: nvcc -arch=sm_70 -O3 wave_1D.cu
// run: ./a.out
#include "stdio.h"
#include "stdlib.h"
#include "math.h"
#include "hip/hip_runtime.h"
#define DAT double
#define GPU_ID 0 // typically 4 (0-3) on machines at stanford
#define BLOCK_X 100
#define GRID_X 1
#define OVERLENGTH 1 //needed for extra staggered grid
#define zeros(A,N) DAT *A##_d,*A##_h; A##_h = (DAT*)malloc((N)*sizeof(DAT)); \
for(i=0; i < (N); i++){ A##_h[i]=(DAT)0.0; } \
hipMalloc(&A##_d ,(N)*sizeof(DAT)); \
hipMemcpy( A##_d,A##_h,(N)*sizeof(DAT),hipMemcpyHostToDevice);
#define free_all(A) free(A##_h); hipFree(A##_d);
#define gather(A,N) hipMemcpy( A##_h,A##_d,(N)*sizeof(DAT),hipMemcpyDeviceToHost);
void save_array(DAT* A, int N, const char A_name[]){
char* fname; FILE* fid; asprintf(&fname, "%s.dat" , A_name);
fid=fopen(fname, "wb"); fwrite(A, sizeof(DAT), N, fid); fclose(fid); free(fname);
}
#define SaveArray(A,N,A_name) gather(A,N); save_array(A##_h, N, A_name);
void clean_cuda(){
hipError_t ce = hipGetLastError();
if(ce != hipSuccess){ printf("ERROR launching GPU C-CUDA program: %s\n", hipGetErrorString(ce)); hipDeviceReset();}
}
// --------------------------------------------------------------------- //
// Physics
const DAT Lx = 10.0;
const DAT k = 1.0;
const DAT rho = 1.0;
// Numerics
const int nx = BLOCK_X*GRID_X-OVERLENGTH;
const int nt = 200;
const DAT dx = Lx/((DAT)nx);
const DAT dt = dx/sqrt(k/rho)/2.1;
// Computing physics kernels
__global__ void init(DAT* x, DAT* P, const DAT Lx, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ x[ix] = (DAT)ix*dx + (-Lx+dx)/2.0; }
if (ix<nx){ P[ix] = exp(-(x[ix]*x[ix])); }
}
__global__ void compute_V(DAT* V, DAT* P, const DAT dt, const DAT rho, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix>0 && ix<nx){ V[ix] = V[ix] - dt*(P[ix]-P[ix-1])/dx/rho; }
}
__global__ void compute_P(DAT* V, DAT* P, const DAT dt, const DAT k, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ P[ix] = P[ix] - dt*(V[ix+1]-V[ix])/dx*k; }
}
int main(){
int i, it;
// Set up GPU
int gpu_id=-1;
dim3 grid, block;
block.x = BLOCK_X; grid.x = GRID_X;
gpu_id = GPU_ID; hipSetDevice(gpu_id); hipGetDevice(&gpu_id);
hipDeviceReset(); hipDeviceSetCacheConfig(hipFuncCachePreferL1); // set L1 to prefered
printf("Process uses GPU with id %d .\n",gpu_id);
// Initial arrays
zeros(x,nx );
zeros(P,nx );
zeros(V,nx+1);
// Initial conditions
init<<<grid,block>>>(x_d, P_d, Lx, dx, nx); hipDeviceSynchronize();
// Action
for (it=0;it<nt;it++){
compute_V<<<grid,block>>>(V_d, P_d, dt, rho, dx, nx); hipDeviceSynchronize();
compute_P<<<grid,block>>>(V_d, P_d, dt, k , dx, nx); hipDeviceSynchronize();
}//it
SaveArray(P,nx,"P_c");
free_all(x);
free_all(P);
free_all(V);
clean_cuda();
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// wave 1D GPU
// compile: nvcc -arch=sm_70 -O3 wave_1D.cu
// run: ./a.out
#include "stdio.h"
#include "stdlib.h"
#include "math.h"
#include "hip/hip_runtime.h"
#define DAT double
#define GPU_ID 0 // typically 4 (0-3) on machines at stanford
#define BLOCK_X 100
#define GRID_X 1
#define OVERLENGTH 1 //needed for extra staggered grid
#define zeros(A,N) DAT *A##_d,*A##_h; A##_h = (DAT*)malloc((N)*sizeof(DAT)); \
for(i=0; i < (N); i++){ A##_h[i]=(DAT)0.0; } \
hipMalloc(&A##_d ,(N)*sizeof(DAT)); \
hipMemcpy( A##_d,A##_h,(N)*sizeof(DAT),hipMemcpyHostToDevice);
#define free_all(A) free(A##_h); hipFree(A##_d);
#define gather(A,N) hipMemcpy( A##_h,A##_d,(N)*sizeof(DAT),hipMemcpyDeviceToHost);
void save_array(DAT* A, int N, const char A_name[]){
char* fname; FILE* fid; asprintf(&fname, "%s.dat" , A_name);
fid=fopen(fname, "wb"); fwrite(A, sizeof(DAT), N, fid); fclose(fid); free(fname);
}
#define SaveArray(A,N,A_name) gather(A,N); save_array(A##_h, N, A_name);
void clean_cuda(){
hipError_t ce = hipGetLastError();
if(ce != hipSuccess){ printf("ERROR launching GPU C-CUDA program: %s\n", hipGetErrorString(ce)); hipDeviceReset();}
}
// --------------------------------------------------------------------- //
// Physics
const DAT Lx = 10.0;
const DAT k = 1.0;
const DAT rho = 1.0;
// Numerics
const int nx = BLOCK_X*GRID_X-OVERLENGTH;
const int nt = 200;
const DAT dx = Lx/((DAT)nx);
const DAT dt = dx/sqrt(k/rho)/2.1;
// Computing physics kernels
__global__ void init(DAT* x, DAT* P, const DAT Lx, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ x[ix] = (DAT)ix*dx + (-Lx+dx)/2.0; }
if (ix<nx){ P[ix] = exp(-(x[ix]*x[ix])); }
}
__global__ void compute_V(DAT* V, DAT* P, const DAT dt, const DAT rho, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix>0 && ix<nx){ V[ix] = V[ix] - dt*(P[ix]-P[ix-1])/dx/rho; }
}
__global__ void compute_P(DAT* V, DAT* P, const DAT dt, const DAT k, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ P[ix] = P[ix] - dt*(V[ix+1]-V[ix])/dx*k; }
}
int main(){
int i, it;
// Set up GPU
int gpu_id=-1;
dim3 grid, block;
block.x = BLOCK_X; grid.x = GRID_X;
gpu_id = GPU_ID; hipSetDevice(gpu_id); hipGetDevice(&gpu_id);
hipDeviceReset(); hipDeviceSetCacheConfig(hipFuncCachePreferL1); // set L1 to prefered
printf("Process uses GPU with id %d .\n",gpu_id);
// Initial arrays
zeros(x,nx );
zeros(P,nx );
zeros(V,nx+1);
// Initial conditions
init<<<grid,block>>>(x_d, P_d, Lx, dx, nx); hipDeviceSynchronize();
// Action
for (it=0;it<nt;it++){
compute_V<<<grid,block>>>(V_d, P_d, dt, rho, dx, nx); hipDeviceSynchronize();
compute_P<<<grid,block>>>(V_d, P_d, dt, k , dx, nx); hipDeviceSynchronize();
}//it
SaveArray(P,nx,"P_c");
free_all(x);
free_all(P);
free_all(V);
clean_cuda();
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4initPdS_ddi
.globl _Z4initPdS_ddi
.p2align 8
.type _Z4initPdS_ddi,@function
_Z4initPdS_ddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[2:3], v1
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
s_waitcnt lgkmcnt(0)
v_add_f64 v[4:5], s[10:11], -s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], s[10:11]
v_fma_f64 v[3:4], v[4:5], 0.5, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[5:6], v[3:4], -v[3:4]
v_mul_f64 v[7:8], v[5:6], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[7:8], v[7:8]
v_fma_f64 v[9:10], v[7:8], s[0:1], v[5:6]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v0, v[7:8]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[9:10], v[7:8], s[0:1], v[9:10]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], v[11:12], 1.0
v_fma_f64 v[7:8], v[9:10], v[11:12], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], v0
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v5, s1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e64 v6, s1, s5, v1, s1
v_cndmask_b32_e32 v8, 0x7ff00000, v8, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v8, 0, v8, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b64 v[5:6], v[3:4], off
global_store_b64 v[0:1], v[7:8], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4initPdS_ddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4initPdS_ddi, .Lfunc_end0-_Z4initPdS_ddi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9compute_VPdS_dddi
.globl _Z9compute_VPdS_dddi
.p2align 8
.type _Z9compute_VPdS_dddi,@function
_Z9compute_VPdS_dddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_lt_i32_e32 vcc_lo, 0, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[2:3], off
global_load_b64 v[2:3], v[2:3], off offset:-8
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[4:5], -v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], s[8:9]
v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[8:9], v[0:1], off
v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
v_div_scale_f64 v[4:5], null, s[10:11], s[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[12:13]
v_div_fixup_f64 v[2:3], v[4:5], s[10:11], v[2:3]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[2:3], v[8:9], -v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9compute_VPdS_dddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9compute_VPdS_dddi, .Lfunc_end1-_Z9compute_VPdS_dddi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9compute_PPdS_dddi
.globl _Z9compute_PPdS_dddi
.p2align 8
.type _Z9compute_PPdS_dddi,@function
_Z9compute_PPdS_dddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b128 v[0:3], v[0:1], off
global_load_b64 v[8:9], v[4:5], off
s_waitcnt vmcnt(1)
v_add_f64 v[0:1], v[2:3], -v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[8:9]
v_div_scale_f64 v[2:3], null, s[0:1], s[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[2:3], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[0:1], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[6:7]
v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[12:13]
v_div_fixup_f64 v[0:1], v[2:3], s[0:1], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], -v[0:1], s[10:11], v[8:9]
global_store_b64 v[4:5], v[0:1], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9compute_PPdS_dddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z9compute_PPdS_dddi, .Lfunc_end2-_Z9compute_PPdS_dddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4initPdS_ddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4initPdS_ddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9compute_VPdS_dddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9compute_VPdS_dddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9compute_PPdS_dddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9compute_PPdS_dddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// wave 1D GPU
// compile: nvcc -arch=sm_70 -O3 wave_1D.cu
// run: ./a.out
#include "stdio.h"
#include "stdlib.h"
#include "math.h"
#include "hip/hip_runtime.h"
#define DAT double
#define GPU_ID 0 // typically 4 (0-3) on machines at stanford
#define BLOCK_X 100
#define GRID_X 1
#define OVERLENGTH 1 //needed for extra staggered grid
#define zeros(A,N) DAT *A##_d,*A##_h; A##_h = (DAT*)malloc((N)*sizeof(DAT)); \
for(i=0; i < (N); i++){ A##_h[i]=(DAT)0.0; } \
hipMalloc(&A##_d ,(N)*sizeof(DAT)); \
hipMemcpy( A##_d,A##_h,(N)*sizeof(DAT),hipMemcpyHostToDevice);
#define free_all(A) free(A##_h); hipFree(A##_d);
#define gather(A,N) hipMemcpy( A##_h,A##_d,(N)*sizeof(DAT),hipMemcpyDeviceToHost);
void save_array(DAT* A, int N, const char A_name[]){
char* fname; FILE* fid; asprintf(&fname, "%s.dat" , A_name);
fid=fopen(fname, "wb"); fwrite(A, sizeof(DAT), N, fid); fclose(fid); free(fname);
}
#define SaveArray(A,N,A_name) gather(A,N); save_array(A##_h, N, A_name);
void clean_cuda(){
hipError_t ce = hipGetLastError();
if(ce != hipSuccess){ printf("ERROR launching GPU C-CUDA program: %s\n", hipGetErrorString(ce)); hipDeviceReset();}
}
// --------------------------------------------------------------------- //
// Physics
const DAT Lx = 10.0;
const DAT k = 1.0;
const DAT rho = 1.0;
// Numerics
const int nx = BLOCK_X*GRID_X-OVERLENGTH;
const int nt = 200;
const DAT dx = Lx/((DAT)nx);
const DAT dt = dx/sqrt(k/rho)/2.1;
// Computing physics kernels
__global__ void init(DAT* x, DAT* P, const DAT Lx, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ x[ix] = (DAT)ix*dx + (-Lx+dx)/2.0; }
if (ix<nx){ P[ix] = exp(-(x[ix]*x[ix])); }
}
__global__ void compute_V(DAT* V, DAT* P, const DAT dt, const DAT rho, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix>0 && ix<nx){ V[ix] = V[ix] - dt*(P[ix]-P[ix-1])/dx/rho; }
}
__global__ void compute_P(DAT* V, DAT* P, const DAT dt, const DAT k, const DAT dx, const int nx){
int ix = blockIdx.x*blockDim.x + threadIdx.x; // thread ID, dimension x
if (ix<nx){ P[ix] = P[ix] - dt*(V[ix+1]-V[ix])/dx*k; }
}
int main(){
int i, it;
// Set up GPU
int gpu_id=-1;
dim3 grid, block;
block.x = BLOCK_X; grid.x = GRID_X;
gpu_id = GPU_ID; hipSetDevice(gpu_id); hipGetDevice(&gpu_id);
hipDeviceReset(); hipDeviceSetCacheConfig(hipFuncCachePreferL1); // set L1 to prefered
printf("Process uses GPU with id %d .\n",gpu_id);
// Initial arrays
zeros(x,nx );
zeros(P,nx );
zeros(V,nx+1);
// Initial conditions
init<<<grid,block>>>(x_d, P_d, Lx, dx, nx); hipDeviceSynchronize();
// Action
for (it=0;it<nt;it++){
compute_V<<<grid,block>>>(V_d, P_d, dt, rho, dx, nx); hipDeviceSynchronize();
compute_P<<<grid,block>>>(V_d, P_d, dt, k , dx, nx); hipDeviceSynchronize();
}//it
SaveArray(P,nx,"P_c");
free_all(x);
free_all(P);
free_all(V);
clean_cuda();
}
|
.text
.file "wave_1D.hip"
.globl _Z10save_arrayPdiPKc # -- Begin function _Z10save_arrayPdiPKc
.p2align 4, 0x90
.type _Z10save_arrayPdiPKc,@function
_Z10save_arrayPdiPKc: # @_Z10save_arrayPdiPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
leaq 8(%rsp), %rdi
movl $.L.str, %esi
xorl %eax, %eax
callq asprintf
movq 8(%rsp), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movslq %ebx, %rdx
movl $8, %esi
movq %r14, %rdi
movq %rax, %rcx
callq fwrite
movq %r15, %rdi
callq fclose
movq 8(%rsp), %rdi
callq free
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10save_arrayPdiPKc, .Lfunc_end0-_Z10save_arrayPdiPKc
.cfi_endproc
# -- End function
.globl _Z10clean_cudav # -- Begin function _Z10clean_cudav
.p2align 4, 0x90
.type _Z10clean_cudav,@function
_Z10clean_cudav: # @_Z10clean_cudav
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
je .LBB1_1
# %bb.2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
popq %rax
.cfi_def_cfa_offset 8
jmp hipDeviceReset # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10clean_cudav, .Lfunc_end1-_Z10clean_cudav
.cfi_endproc
# -- End function
.globl _Z19__device_stub__initPdS_ddi # -- Begin function _Z19__device_stub__initPdS_ddi
.p2align 4, 0x90
.type _Z19__device_stub__initPdS_ddi,@function
_Z19__device_stub__initPdS_ddi: # @_Z19__device_stub__initPdS_ddi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %edx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4initPdS_ddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z19__device_stub__initPdS_ddi, .Lfunc_end2-_Z19__device_stub__initPdS_ddi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__compute_VPdS_dddi # -- Begin function _Z24__device_stub__compute_VPdS_dddi
.p2align 4, 0x90
.type _Z24__device_stub__compute_VPdS_dddi,@function
_Z24__device_stub__compute_VPdS_dddi: # @_Z24__device_stub__compute_VPdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9compute_VPdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__compute_VPdS_dddi, .Lfunc_end3-_Z24__device_stub__compute_VPdS_dddi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__compute_PPdS_dddi # -- Begin function _Z24__device_stub__compute_PPdS_dddi
.p2align 4, 0x90
.type _Z24__device_stub__compute_PPdS_dddi,@function
_Z24__device_stub__compute_PPdS_dddi: # @_Z24__device_stub__compute_PPdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9compute_PPdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z24__device_stub__compute_PPdS_dddi, .Lfunc_end4-_Z24__device_stub__compute_PPdS_dddi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $0, 92(%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 92(%rsp), %rdi
callq hipGetDevice
callq hipDeviceReset
movl $2, %edi
callq hipDeviceSetCacheConfig
movl 92(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $792, %edi # imm = 0x318
callq malloc
movq %rax, %rbx
movl $792, %edx # imm = 0x318
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 120(%rsp), %rdi
movl $792, %esi # imm = 0x318
callq hipMalloc
movq 120(%rsp), %rdi
movl $792, %edx # imm = 0x318
movq %rbx, 192(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $792, %edi # imm = 0x318
callq malloc
movq %rax, %rbx
movl $792, %edx # imm = 0x318
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $792, %esi # imm = 0x318
callq hipMalloc
movq 8(%rsp), %rdi
movl $792, %edx # imm = 0x318
movq %rbx, 184(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movl $800, %edx # imm = 0x320
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 96(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 96(%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %rbx, 176(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 99(%r14), %r13
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 120(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movabsq $4621819117588971520, %rax # imm = 0x4024000000000000
movq %rax, 64(%rsp)
movabsq $4591942965515480881, %rax # imm = 0x3FB9DBCC48676F31
movq %rax, 56(%rsp)
movl $99, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4initPdS_ddi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movl $200, %ebx
leaq 112(%rsp), %r12
leaq 104(%rsp), %r15
leaq 128(%rsp), %rbp
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_3 Depth=1
callq hipDeviceSynchronize
decl %ebx
je .LBB5_8
.LBB5_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
movq 96(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movabsq $4587092768514190577, %rax # imm = 0x3FA8A091CB0D2CF1
movq %rax, 64(%rsp)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 56(%rsp)
movabsq $4591942965515480881, %rax # imm = 0x3FB9DBCC48676F31
movq %rax, 48(%rsp)
movl $99, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r12, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9compute_VPdS_dddi, %edi
movq %rbp, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_5: # in Loop: Header=BB5_3 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_3 Depth=1
movq 96(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movabsq $4587092768514190577, %rax # imm = 0x3FA8A091CB0D2CF1
movq %rax, 64(%rsp)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 56(%rsp)
movabsq $4591942965515480881, %rax # imm = 0x3FB9DBCC48676F31
movq %rax, 48(%rsp)
movl $99, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r12, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9compute_PPdS_dddi, %edi
movq %rbp, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_7
.LBB5_8:
movq 8(%rsp), %rsi
movl $792, %edx # imm = 0x318
movq 184(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 128(%rsp), %rdi
movl $.L.str, %esi
movl $.L.str.4, %edx
xorl %eax, %eax
callq asprintf
movq 128(%rsp), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $8, %esi
movl $99, %edx
movq %r14, %rdi
movq %rax, %rcx
callq fwrite
movq %rbx, %rdi
callq fclose
movq 128(%rsp), %rdi
callq free
movq 192(%rsp), %rdi # 8-byte Reload
callq free
movq 120(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi # 8-byte Reload
callq free
movq 96(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
je .LBB5_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB5_10: # %_Z10clean_cudav.exit
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPdS_ddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9compute_VPdS_dddi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9compute_PPdS_dddi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s.dat"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR launching GPU C-CUDA program: %s\n"
.size .L.str.2, 40
.type _Z4initPdS_ddi,@object # @_Z4initPdS_ddi
.section .rodata,"a",@progbits
.globl _Z4initPdS_ddi
.p2align 3, 0x0
_Z4initPdS_ddi:
.quad _Z19__device_stub__initPdS_ddi
.size _Z4initPdS_ddi, 8
.type _Z9compute_VPdS_dddi,@object # @_Z9compute_VPdS_dddi
.globl _Z9compute_VPdS_dddi
.p2align 3, 0x0
_Z9compute_VPdS_dddi:
.quad _Z24__device_stub__compute_VPdS_dddi
.size _Z9compute_VPdS_dddi, 8
.type _Z9compute_PPdS_dddi,@object # @_Z9compute_PPdS_dddi
.globl _Z9compute_PPdS_dddi
.p2align 3, 0x0
_Z9compute_PPdS_dddi:
.quad _Z24__device_stub__compute_PPdS_dddi
.size _Z9compute_PPdS_dddi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Process uses GPU with id %d .\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P_c"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPdS_ddi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9compute_VPdS_dddi"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9compute_PPdS_dddi"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPdS_ddi
.addrsig_sym _Z24__device_stub__compute_VPdS_dddi
.addrsig_sym _Z24__device_stub__compute_PPdS_dddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPdS_ddi
.addrsig_sym _Z9compute_VPdS_dddi
.addrsig_sym _Z9compute_PPdS_dddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f8c27_00000000-6_wave_1D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s.dat"
.LC1:
.string "wb"
.text
.globl _Z10save_arrayPdiPKc
.type _Z10save_arrayPdiPKc, @function
_Z10save_arrayPdiPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebx
movq %rdx, %rcx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
leaq .LC0(%rip), %rdx
movl $2, %esi
call __asprintf_chk@PLT
leaq .LC1(%rip), %rsi
movq (%rsp), %rdi
call fopen@PLT
movq %rax, %rbp
movslq %ebx, %rdx
movq %rax, %rcx
movl $8, %esi
movq %r12, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z10save_arrayPdiPKc, .-_Z10save_arrayPdiPKc
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "ERROR launching GPU C-CUDA program: %s\n"
.text
.globl _Z10clean_cudav
.type _Z10clean_cudav, @function
_Z10clean_cudav:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L10
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
jmp .L7
.cfi_endproc
.LFE2058:
.size _Z10clean_cudav, .-_Z10clean_cudav
.globl _Z28__device_stub__Z4initPdS_ddiPdS_ddi
.type _Z28__device_stub__Z4initPdS_ddiPdS_ddi, @function
_Z28__device_stub__Z4initPdS_ddiPdS_ddi:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4initPdS_ddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z28__device_stub__Z4initPdS_ddiPdS_ddi, .-_Z28__device_stub__Z4initPdS_ddiPdS_ddi
.globl _Z4initPdS_ddi
.type _Z4initPdS_ddi, @function
_Z4initPdS_ddi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4initPdS_ddiPdS_ddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z4initPdS_ddi, .-_Z4initPdS_ddi
.globl _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
.type _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi, @function
_Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9compute_VPdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi, .-_Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
.globl _Z9compute_VPdS_dddi
.type _Z9compute_VPdS_dddi, @function
_Z9compute_VPdS_dddi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z9compute_VPdS_dddi, .-_Z9compute_VPdS_dddi
.globl _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
.type _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi, @function
_Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9compute_PPdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi, .-_Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
.globl _Z9compute_PPdS_dddi
.type _Z9compute_PPdS_dddi, @function
_Z9compute_PPdS_dddi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z9compute_PPdS_dddi, .-_Z9compute_PPdS_dddi
.section .rodata.str1.8
.align 8
.LC3:
.string "Process uses GPU with id %d .\n"
.section .rodata.str1.1
.LC9:
.string "P_c"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $100, 44(%rsp)
movl $0, 4(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
leaq 4(%rsp), %rdi
call cudaGetDevice@PLT
call cudaDeviceReset@PLT
movl $2, %edi
call cudaDeviceSetCacheConfig@PLT
movl 4(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $792, %edi
call malloc@PLT
movq %rax, %rbp
leaq 792(%rax), %rdx
.L36:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $792, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $792, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $792, %edi
call malloc@PLT
movq %rax, %r12
leaq 792(%rax), %rdx
.L37:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L37
leaq 16(%rsp), %rdi
movl $792, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $792, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $800, %edi
call malloc@PLT
movq %rax, %r13
leaq 800(%rax), %rdx
.L38:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L38
leaq 24(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $800, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L39:
call cudaDeviceSynchronize@PLT
movl $200, %ebx
jmp .L42
.L49:
movl $99, %edx
movsd .LC5(%rip), %xmm1
movsd .LC6(%rip), %xmm0
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z28__device_stub__Z4initPdS_ddiPdS_ddi
jmp .L39
.L51:
movl $99, %edx
movsd .LC5(%rip), %xmm2
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9compute_VPdS_dddiPdS_dddi
jmp .L40
.L41:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L50
.L42:
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L40:
call cudaDeviceSynchronize@PLT
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movl $99, %edx
movsd .LC5(%rip), %xmm2
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9compute_PPdS_dddiPdS_dddi
jmp .L41
.L50:
movl $2, %ecx
movl $792, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC9(%rip), %rdx
movl $99, %esi
movq %r12, %rdi
call _Z10save_arrayPdiPKc
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call _Z10clean_cudav
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z9compute_PPdS_dddi"
.LC11:
.string "_Z9compute_VPdS_dddi"
.LC12:
.string "_Z4initPdS_ddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9compute_PPdS_dddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9compute_VPdS_dddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initPdS_ddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 1214738225
.long 1069145036
.align 8
.LC6:
.long 0
.long 1076101120
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC8:
.long -888328975
.long 1068015761
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "wave_1D.hip"
.globl _Z10save_arrayPdiPKc # -- Begin function _Z10save_arrayPdiPKc
.p2align 4, 0x90
.type _Z10save_arrayPdiPKc,@function
_Z10save_arrayPdiPKc: # @_Z10save_arrayPdiPKc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
leaq 8(%rsp), %rdi
movl $.L.str, %esi
xorl %eax, %eax
callq asprintf
movq 8(%rsp), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r15
movslq %ebx, %rdx
movl $8, %esi
movq %r14, %rdi
movq %rax, %rcx
callq fwrite
movq %r15, %rdi
callq fclose
movq 8(%rsp), %rdi
callq free
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10save_arrayPdiPKc, .Lfunc_end0-_Z10save_arrayPdiPKc
.cfi_endproc
# -- End function
.globl _Z10clean_cudav # -- Begin function _Z10clean_cudav
.p2align 4, 0x90
.type _Z10clean_cudav,@function
_Z10clean_cudav: # @_Z10clean_cudav
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetLastError
testl %eax, %eax
je .LBB1_1
# %bb.2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
popq %rax
.cfi_def_cfa_offset 8
jmp hipDeviceReset # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10clean_cudav, .Lfunc_end1-_Z10clean_cudav
.cfi_endproc
# -- End function
.globl _Z19__device_stub__initPdS_ddi # -- Begin function _Z19__device_stub__initPdS_ddi
.p2align 4, 0x90
.type _Z19__device_stub__initPdS_ddi,@function
_Z19__device_stub__initPdS_ddi: # @_Z19__device_stub__initPdS_ddi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movl %edx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4initPdS_ddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z19__device_stub__initPdS_ddi, .Lfunc_end2-_Z19__device_stub__initPdS_ddi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__compute_VPdS_dddi # -- Begin function _Z24__device_stub__compute_VPdS_dddi
.p2align 4, 0x90
.type _Z24__device_stub__compute_VPdS_dddi,@function
_Z24__device_stub__compute_VPdS_dddi: # @_Z24__device_stub__compute_VPdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9compute_VPdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__compute_VPdS_dddi, .Lfunc_end3-_Z24__device_stub__compute_VPdS_dddi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__compute_PPdS_dddi # -- Begin function _Z24__device_stub__compute_PPdS_dddi
.p2align 4, 0x90
.type _Z24__device_stub__compute_PPdS_dddi,@function
_Z24__device_stub__compute_PPdS_dddi: # @_Z24__device_stub__compute_PPdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9compute_PPdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z24__device_stub__compute_PPdS_dddi, .Lfunc_end4-_Z24__device_stub__compute_PPdS_dddi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $0, 92(%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 92(%rsp), %rdi
callq hipGetDevice
callq hipDeviceReset
movl $2, %edi
callq hipDeviceSetCacheConfig
movl 92(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $792, %edi # imm = 0x318
callq malloc
movq %rax, %rbx
movl $792, %edx # imm = 0x318
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 120(%rsp), %rdi
movl $792, %esi # imm = 0x318
callq hipMalloc
movq 120(%rsp), %rdi
movl $792, %edx # imm = 0x318
movq %rbx, 192(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $792, %edi # imm = 0x318
callq malloc
movq %rax, %rbx
movl $792, %edx # imm = 0x318
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 8(%rsp), %rdi
movl $792, %esi # imm = 0x318
callq hipMalloc
movq 8(%rsp), %rdi
movl $792, %edx # imm = 0x318
movq %rbx, 184(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $800, %edi # imm = 0x320
callq malloc
movq %rax, %rbx
movl $800, %edx # imm = 0x320
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 96(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 96(%rsp), %rdi
movl $800, %edx # imm = 0x320
movq %rbx, 176(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 99(%r14), %r13
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 120(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movabsq $4621819117588971520, %rax # imm = 0x4024000000000000
movq %rax, 64(%rsp)
movabsq $4591942965515480881, %rax # imm = 0x3FB9DBCC48676F31
movq %rax, 56(%rsp)
movl $99, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z4initPdS_ddi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movl $200, %ebx
leaq 112(%rsp), %r12
leaq 104(%rsp), %r15
leaq 128(%rsp), %rbp
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_3 Depth=1
callq hipDeviceSynchronize
decl %ebx
je .LBB5_8
.LBB5_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_5
# %bb.4: # in Loop: Header=BB5_3 Depth=1
movq 96(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movabsq $4587092768514190577, %rax # imm = 0x3FA8A091CB0D2CF1
movq %rax, 64(%rsp)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 56(%rsp)
movabsq $4591942965515480881, %rax # imm = 0x3FB9DBCC48676F31
movq %rax, 48(%rsp)
movl $99, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r12, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9compute_VPdS_dddi, %edi
movq %rbp, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_5: # in Loop: Header=BB5_3 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6: # in Loop: Header=BB5_3 Depth=1
movq 96(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movabsq $4587092768514190577, %rax # imm = 0x3FA8A091CB0D2CF1
movq %rax, 64(%rsp)
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, 56(%rsp)
movabsq $4591942965515480881, %rax # imm = 0x3FB9DBCC48676F31
movq %rax, 48(%rsp)
movl $99, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r12, %rdx
movq %r15, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z9compute_PPdS_dddi, %edi
movq %rbp, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_7
.LBB5_8:
movq 8(%rsp), %rsi
movl $792, %edx # imm = 0x318
movq 184(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 128(%rsp), %rdi
movl $.L.str, %esi
movl $.L.str.4, %edx
xorl %eax, %eax
callq asprintf
movq 128(%rsp), %rdi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
movl $8, %esi
movl $99, %edx
movq %r14, %rdi
movq %rax, %rcx
callq fwrite
movq %rbx, %rdi
callq fclose
movq 128(%rsp), %rdi
callq free
movq 192(%rsp), %rdi # 8-byte Reload
callq free
movq 120(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi # 8-byte Reload
callq free
movq 96(%rsp), %rdi
callq hipFree
callq hipGetLastError
testl %eax, %eax
je .LBB5_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceReset
.LBB5_10: # %_Z10clean_cudav.exit
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initPdS_ddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9compute_VPdS_dddi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9compute_PPdS_dddi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s.dat"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "wb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR launching GPU C-CUDA program: %s\n"
.size .L.str.2, 40
.type _Z4initPdS_ddi,@object # @_Z4initPdS_ddi
.section .rodata,"a",@progbits
.globl _Z4initPdS_ddi
.p2align 3, 0x0
_Z4initPdS_ddi:
.quad _Z19__device_stub__initPdS_ddi
.size _Z4initPdS_ddi, 8
.type _Z9compute_VPdS_dddi,@object # @_Z9compute_VPdS_dddi
.globl _Z9compute_VPdS_dddi
.p2align 3, 0x0
_Z9compute_VPdS_dddi:
.quad _Z24__device_stub__compute_VPdS_dddi
.size _Z9compute_VPdS_dddi, 8
.type _Z9compute_PPdS_dddi,@object # @_Z9compute_PPdS_dddi
.globl _Z9compute_PPdS_dddi
.p2align 3, 0x0
_Z9compute_PPdS_dddi:
.quad _Z24__device_stub__compute_PPdS_dddi
.size _Z9compute_PPdS_dddi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Process uses GPU with id %d .\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "P_c"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initPdS_ddi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9compute_VPdS_dddi"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9compute_PPdS_dddi"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initPdS_ddi
.addrsig_sym _Z24__device_stub__compute_VPdS_dddi
.addrsig_sym _Z24__device_stub__compute_PPdS_dddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initPdS_ddi
.addrsig_sym _Z9compute_VPdS_dddi
.addrsig_sym _Z9compute_PPdS_dddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
#include <iomanip>
#include <math.h>
using namespace std;
typedef double myfloat;
const double pi_const = 3.1415926535897932384626433832795;
void generate_components(float* pi_comp, int n);
float add_components(float* pi_comp, int n);
void print_components(float* pi_comp, int n);
void generate_components(double* pi_comp, int n);
double add_components(double* pi_comp, int n);
void print_components(double* pi_comp, int n);
__global__ void add_components_GPU_2(myfloat* pi_components, myfloat* pi_components_2, int thr_adds)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x) * thr_adds;
for (int i = id_i; i < id_i + thr_adds; i++)
{
*(pi_components_2 + id_i / thr_adds) += *(pi_components + i);
}
}
__global__ void generate_GPU(myfloat* pi_components, int n)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x);
for (int i = id_i; i < n; i += blockDim.x + gridDim.x)
{
*(pi_components + i) = 4 * 1.0 / (2 * i + 1) * ((2 * i) % 4 ? -1.0 : 1.0);
}
}
int main()
{
int n = 1;
//std::cout << "Give n: ";
//std::cin >> n;
n = 600000000;
std::cout << "n: " << n << "\n\n";
myfloat* pi_comp_CPU = (myfloat*)malloc(n * sizeof(myfloat));
cudaError_t cudaStatus;
//Obliczenia CPU
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate_components(pi_comp_CPU, n);
clock_t start_CPU = clock();
myfloat pi_no = add_components(pi_comp_CPU, n);
clock_t stop_CPU = clock();
std::cout << "pi_constant: " << std::setprecision(50) << pi_const << "\n\n";
std::cout << "\n\nCPU\n";
std::cout << "pi CPU: " << std::setprecision(50) << pi_no << "\n";
std::cout << "Czas_CPU: " << 1000 * (stop_CPU - start_CPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - pi_no << "\n\n";
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//GPU
myfloat* pi_components;
myfloat* pi_components_2;
int BLOCK_SIZE = 256;
int GRID_SIZE = 16;
myfloat* pi_sum_h = (myfloat*)malloc(sizeof(myfloat));
cudaStatus = cudaMalloc(&pi_components, (n + BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!\n");
}
cudaStatus = cudaMalloc(&pi_components_2, BLOCK_SIZE * GRID_SIZE * sizeof(myfloat));//(n+1)/2
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!\n");
}
cudaMemcpy(pi_components, pi_comp_CPU, n * sizeof(myfloat), cudaMemcpyHostToDevice);
clock_t start_GPU = clock();
// Obliczenia GPU
//--------------------------------------------------------------
int thr_adds = (n + BLOCK_SIZE * GRID_SIZE - 1) / (BLOCK_SIZE * GRID_SIZE);//ile jeden watek ma wykonac dodawan
add_components_GPU_2 <<<GRID_SIZE, BLOCK_SIZE >>> (pi_components, pi_components_2, thr_adds);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "add_components_GPU_2 launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
cudaMemcpy(pi_comp_CPU, pi_components_2, (BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat), cudaMemcpyDeviceToHost);
*pi_sum_h = add_components(pi_comp_CPU, (BLOCK_SIZE * GRID_SIZE));
//--------------------------------------------------------------
clock_t stop_GPU = clock();
std::cout << "\n\nGPU\n";
std::cout << "pi GPU: " << std::setprecision(50) << *pi_sum_h << "\n";
std::cout << "Czas_GPU: " << 1000 * (stop_GPU - start_GPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - *pi_sum_h << "\n\n";
std::cout << "Speedup: " << (double)(stop_CPU - start_CPU) / (stop_GPU - start_GPU) << "\n\n";
cudaFree(pi_components);
cudaFree(pi_components_2);
free(pi_comp_CPU);
free(pi_sum_h);
return 0;
}
//##################################################################################
void generate_components(myfloat* pi_comp, int n)
{
int sign = 1;
for (int i = 1; i < 2 * n; i += 2)
{
*(pi_comp + i / 2) = 4 * 1.0 / i * sign;
sign = -sign;
}
}
myfloat add_components(myfloat* pi_comp, int n)
{
myfloat pi_no = 0.0;
for (int i = 0; i < n; i++)
{
pi_no += pi_comp[i];
}
return pi_no;
}
void print_components(myfloat* pi_comp, int n)
{
for (int i = 0; i < n; i++)
{
std::cout << "comp " << i << ": " << pi_comp[i] << "\n";
}
}
|
code for sm_80
Function : _Z12generate_GPUPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ LEA R2, R0, 0x1, 0x1 ; /* 0x0000000100027811 */
/* 0x000fe200078e08ff */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0090*/ BSSY B0, 0x1a0 ; /* 0x0000010000007945 */
/* 0x000fe80003800000 */
/*00a0*/ I2F.F64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e300000201c00 */
/*00b0*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e240000001800 */
/*00c0*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*00d0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*00e0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*00f0*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*0100*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0110*/ DMUL R6, R4, 4 ; /* 0x4010000004067828 */
/* 0x001e0c0000000000 */
/*0120*/ DFMA R8, -R2, R6, 4 ; /* 0x401000000208742b */
/* 0x001e0c0000000106 */
/*0130*/ DFMA R4, R4, R8, R6 ; /* 0x000000080404722b */
/* 0x001e140000000006 */
/*0140*/ FFMA R6, RZ, R3, R5 ; /* 0x00000003ff067223 */
/* 0x001fca0000000005 */
/*0150*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0160*/ @P0 BRA 0x190 ; /* 0x0000002000000947 */
/* 0x002fea0003800000 */
/*0170*/ MOV R6, 0x190 ; /* 0x0000019000067802 */
/* 0x000fe40000000f00 */
/*0180*/ CALL.REL.NOINC 0x280 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ LOP3.LUT R3, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100037812 */
/* 0x000fe200078ec0ff */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff027424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.NE.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc80003f05070 */
/*01e0*/ FSEL R3, -R2, 1.875, !P0 ; /* 0x3ff0000002037808 */
/* 0x000fe20004000100 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0200*/ DMUL R4, R4, R2 ; /* 0x0000000204047228 */
/* 0x0000a40000000000 */
/*0210*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fc800078e0207 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff077624 */
/* 0x000fe200078e00ff */
/*0230*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0041e8000c101b04 */
/*0240*/ IADD3 R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe007 */
/*0250*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0260*/ @!P0 BRA 0x70 ; /* 0xfffffe0000008947 */
/* 0x001fea000383ffff */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*02a0*/ LOP3.LUT R4, R3.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03047812 */
/* 0x040fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x40100000 ; /* 0x40100000ff107424 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R7, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003077812 */
/* 0x000fe200078ec0ff */
/*02d0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff117424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0300*/ ISETP.LE.U32.AND P1, PT, R7, 0x40100000, PT ; /* 0x401000000700780c */
/* 0x000fe20003f23070 */
/*0310*/ BSSY B1, 0x720 ; /* 0x0000040000017945 */
/* 0x000fe20003800000 */
/*0320*/ IADD3 R14, R16, -0x1, RZ ; /* 0xffffffff100e7810 */
/* 0x000fc60007ffe0ff */
/*0330*/ @!P0 DMUL R4, R2, 8.98846567431157953865e+307 ; /* 0x7fe0000002048828 */
/* 0x000e0c0000000000 */
/*0340*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x001e280000001800 */
/*0350*/ @!P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005078812 */
/* 0x000fe400078ec0ff */
/*0360*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fe40003f04070 */
/*0370*/ IADD3 R18, R7, -0x1, RZ ; /* 0xffffffff07127810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GT.U32.OR P0, PT, R18, 0x7feffffe, P0 ; /* 0x7feffffe1200780c */
/* 0x000fe20000704470 */
/*0390*/ DFMA R10, R8, -R4, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000804 */
/*03a0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*03b0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x0010640000000008 */
/*03c0*/ SEL R9, R17, 0x63400000, !P1 ; /* 0x6340000011097807 */
/* 0x001fe20004800000 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*03e0*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x002e0c0000000804 */
/*03f0*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*0400*/ DMUL R12, R10, R8 ; /* 0x000000080a0c7228 */
/* 0x001e0c0000000000 */
/*0410*/ DFMA R14, R12, -R4, R8 ; /* 0x800000040c0e722b */
/* 0x001e0c0000000008 */
/*0420*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001062000000000c */
/*0430*/ @P0 BRA 0x600 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT R12, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030c7812 */
/* 0x001fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e00ff */
/*0460*/ IADD3 R7, -R12.reuse, 0x40100000, RZ ; /* 0x401000000c077810 */
/* 0x040fe40007ffe1ff */
/*0470*/ ISETP.LE.U32.AND P0, PT, R12, 0x40100000, PT ; /* 0x401000000c00780c */
/* 0x000fe40003f03070 */
/*0480*/ IMNMX R7, R7, -0x46a00000, !PT ; /* 0xb960000007077817 */
/* 0x000fe40007800200 */
/*0490*/ SEL R12, R17, 0x63400000, !P0 ; /* 0x63400000110c7807 */
/* 0x000fe40004000000 */
/*04a0*/ IMNMX R7, R7, 0x46a00000, PT ; /* 0x46a0000007077817 */
/* 0x000fca0003800200 */
/*04b0*/ IMAD.IADD R16, R7, 0x1, -R12 ; /* 0x0000000107107824 */
/* 0x000fca00078e0a0c */
/*04c0*/ IADD3 R15, R16, 0x7fe00000, RZ ; /* 0x7fe00000100f7810 */
/* 0x000fcc0007ffe0ff */
/*04d0*/ DMUL R12, R10, R14 ; /* 0x0000000e0a0c7228 */
/* 0x002e140000000000 */
/*04e0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*04f0*/ @P0 BRA 0x710 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0500*/ DFMA R4, R10, -R4, R8 ; /* 0x800000040a04722b */
/* 0x000e220000000008 */
/*0510*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0520*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0530*/ LOP3.LUT R7, R5, 0x80000000, R3, 0x48, !PT ; /* 0x8000000005077812 */
/* 0x000fc800078e4803 */
/*0540*/ LOP3.LUT R15, R7, R15, RZ, 0xfc, !PT ; /* 0x0000000f070f7212 */
/* 0x000fce00078efcff */
/*0550*/ @!P0 BRA 0x710 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV R3, RZ, RZ, -R16 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a10 */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0580*/ DFMA R2, R12, -R2, R10 ; /* 0x800000020c02722b */
/* 0x000e08000000000a */
/*0590*/ DMUL.RP R10, R10, R14 ; /* 0x0000000e0a0a7228 */
/* 0x000e640000008000 */
/*05a0*/ IADD3 R2, -R16, -0x43300000, RZ ; /* 0xbcd0000010027810 */
/* 0x001fc80007ffe1ff */
/*05b0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*05c0*/ LOP3.LUT R7, R11, R7, RZ, 0x3c, !PT ; /* 0x000000070b077212 */
/* 0x002fe400078e3cff */
/*05d0*/ FSEL R12, R10, R12, !P0 ; /* 0x0000000c0a0c7208 */
/* 0x000fe40004000000 */
/*05e0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*05f0*/ BRA 0x710 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0600*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0610*/ @P0 BRA 0x6f0 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0620*/ ISETP.NE.AND P0, PT, R16, R7, PT ; /* 0x000000071000720c */
/* 0x000fe20003f05270 */
/*0630*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x001fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0650*/ @!P0 BRA 0x710 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0670*/ LOP3.LUT R2, R3, 0x40100000, RZ, 0x3c, !PT ; /* 0x4010000003027812 */
/* 0x000fe400078e3cff */
/*0680*/ ISETP.EQ.OR P0, PT, R7, RZ, !P0 ; /* 0x000000ff0700720c */
/* 0x000fe40004702670 */
/*0690*/ LOP3.LUT R13, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000020d7812 */
/* 0x000fd600078ec0ff */
/*06a0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*06b0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*06c0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*06d0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*06e0*/ BRA 0x710 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06f0*/ LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030d7812 */
/* 0x001fe200078efcff */
/*0700*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0002 */
/*0710*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0750*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff8a006007950 */
/* 0x000fec0003c3ffff */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20add_components_GPU_2PdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0070*/ IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; /* 0x00000008ff0c7424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000ea20000209400 */
/*00a0*/ BSSY B0, 0x3d0 ; /* 0x0000032000007945 */
/* 0x000fee0003800000 */
/*00b0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x004ea20000001000 */
/*00c0*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x003fc800078e0204 */
/*00d0*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fe200078e02ff */
/*00e0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x004fc80007ffe0ff */
/*00f0*/ IABS R0, R5 ; /* 0x0000000500007213 */
/* 0x000fe20000000000 */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0006 */
/*0140*/ IMAD R9, R4, R7, RZ ; /* 0x0000000704097224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R7, R2, R0 ; /* 0x0000000207007224 */
/* 0x000fe200078e0200 */
/*0190*/ LOP3.LUT R2, R5, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0005027a12 */
/* 0x000fc800078e3cff */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f04070 */
/*01b0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f46270 */
/*01c0*/ @!P0 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x8000000700008210 */
/* 0x080fe40007ffe0ff */
/*01d0*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f26070 */
/*01f0*/ IADD3 R0, R5.reuse, c[0x0][0x170], RZ ; /* 0x00005c0005007a10 */
/* 0x040fe40007ffe0ff */
/*0200*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc40003f05270 */
/*0220*/ IMNMX R2, R0, R7, !PT ; /* 0x0000000700027217 */
/* 0x000fe40007800200 */
/*0230*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fc600078e33ff */
/*0240*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.IADD R4, R2.reuse, 0x1, -R5 ; /* 0x0000000102047824 */
/* 0x040fe400078e0a05 */
/*0260*/ IMAD.IADD R7, R2, 0x1, R7 ; /* 0x0000000102077824 */
/* 0x000fe400078e0207 */
/*0270*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0280*/ LOP3.LUT P2, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe4000784c0ff */
/*0290*/ @!P0 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff038a12 */
/* 0x000fe400078e33ff */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fc60003f26070 */
/*02b0*/ IMAD.WIDE R2, R3, R12, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e020c */
/*02c0*/ @!P2 BRA 0x3c0 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000162000c1e1b00 */
/*02e0*/ IMAD.WIDE R6, R5, R12, c[0x0][0x160] ; /* 0x0000580005067625 */
/* 0x000fc800078e020c */
/*02f0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*0300*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fca0000000f00 */
/*0310*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e000b */
/*0330*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0340*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R10, P2, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007f5e0ff */
/*0360*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0370*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0390*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x026e4e0000000008 */
/*03a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e4000c101b04 */
/*03b0*/ @P0 BRA 0x310 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x002362000c1e1b00 */
/*03f0*/ IMAD.WIDE R6, R5, R12, c[0x0][0x160] ; /* 0x0000580005067625 */
/* 0x000fca00078e020c */
/*0400*/ IADD3 R4, P0, R6, 0x10, RZ ; /* 0x0000001006047810 */
/* 0x000fc80007f1e0ff */
/*0410*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x002fc600007fe4ff */
/*0420*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*0430*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fca00078e0007 */
/*0440*/ LDG.E.64 R6, [R14.64+-0x10] ; /* 0xfffff0040e067981 */
/* 0x004ea4000c1e1b00 */
/*0450*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x024e4e0000000008 */
/*0460*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0023e8000c101b04 */
/*0470*/ LDG.E.64 R8, [R14.64+-0x8] ; /* 0xfffff8040e087981 */
/* 0x000ea4000c1e1b00 */
/*0480*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x004e8e0000000008 */
/*0490*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*04a0*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ee4000c1e1b00 */
/*04b0*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x008ece0000000008 */
/*04c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0085e8000c101b04 */
/*04d0*/ LDG.E.64 R8, [R14.64+0x8] ; /* 0x000008040e087981 */
/* 0x000ee2000c1e1b00 */
/*04e0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R4, P1, R14, 0x20, RZ ; /* 0x000000200e047810 */
/* 0x000fe40007f3e0ff */
/*0500*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fc60003f06270 */
/*0510*/ IMAD.X R7, RZ, RZ, R15, P1 ; /* 0x000000ffff077224 */
/* 0x002fe200008e060f */
/*0520*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x008e4e0000000008 */
/*0530*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0025e4000c101b04 */
/*0540*/ @!P0 BRA 0x420 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
#include <iomanip>
#include <math.h>
using namespace std;
typedef double myfloat;
const double pi_const = 3.1415926535897932384626433832795;
void generate_components(float* pi_comp, int n);
float add_components(float* pi_comp, int n);
void print_components(float* pi_comp, int n);
void generate_components(double* pi_comp, int n);
double add_components(double* pi_comp, int n);
void print_components(double* pi_comp, int n);
__global__ void add_components_GPU_2(myfloat* pi_components, myfloat* pi_components_2, int thr_adds)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x) * thr_adds;
for (int i = id_i; i < id_i + thr_adds; i++)
{
*(pi_components_2 + id_i / thr_adds) += *(pi_components + i);
}
}
__global__ void generate_GPU(myfloat* pi_components, int n)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x);
for (int i = id_i; i < n; i += blockDim.x + gridDim.x)
{
*(pi_components + i) = 4 * 1.0 / (2 * i + 1) * ((2 * i) % 4 ? -1.0 : 1.0);
}
}
int main()
{
int n = 1;
//std::cout << "Give n: ";
//std::cin >> n;
n = 600000000;
std::cout << "n: " << n << "\n\n";
myfloat* pi_comp_CPU = (myfloat*)malloc(n * sizeof(myfloat));
cudaError_t cudaStatus;
//Obliczenia CPU
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate_components(pi_comp_CPU, n);
clock_t start_CPU = clock();
myfloat pi_no = add_components(pi_comp_CPU, n);
clock_t stop_CPU = clock();
std::cout << "pi_constant: " << std::setprecision(50) << pi_const << "\n\n";
std::cout << "\n\nCPU\n";
std::cout << "pi CPU: " << std::setprecision(50) << pi_no << "\n";
std::cout << "Czas_CPU: " << 1000 * (stop_CPU - start_CPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - pi_no << "\n\n";
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//GPU
myfloat* pi_components;
myfloat* pi_components_2;
int BLOCK_SIZE = 256;
int GRID_SIZE = 16;
myfloat* pi_sum_h = (myfloat*)malloc(sizeof(myfloat));
cudaStatus = cudaMalloc(&pi_components, (n + BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!\n");
}
cudaStatus = cudaMalloc(&pi_components_2, BLOCK_SIZE * GRID_SIZE * sizeof(myfloat));//(n+1)/2
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!\n");
}
cudaMemcpy(pi_components, pi_comp_CPU, n * sizeof(myfloat), cudaMemcpyHostToDevice);
clock_t start_GPU = clock();
// Obliczenia GPU
//--------------------------------------------------------------
int thr_adds = (n + BLOCK_SIZE * GRID_SIZE - 1) / (BLOCK_SIZE * GRID_SIZE);//ile jeden watek ma wykonac dodawan
add_components_GPU_2 <<<GRID_SIZE, BLOCK_SIZE >>> (pi_components, pi_components_2, thr_adds);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "add_components_GPU_2 launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
cudaMemcpy(pi_comp_CPU, pi_components_2, (BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat), cudaMemcpyDeviceToHost);
*pi_sum_h = add_components(pi_comp_CPU, (BLOCK_SIZE * GRID_SIZE));
//--------------------------------------------------------------
clock_t stop_GPU = clock();
std::cout << "\n\nGPU\n";
std::cout << "pi GPU: " << std::setprecision(50) << *pi_sum_h << "\n";
std::cout << "Czas_GPU: " << 1000 * (stop_GPU - start_GPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - *pi_sum_h << "\n\n";
std::cout << "Speedup: " << (double)(stop_CPU - start_CPU) / (stop_GPU - start_GPU) << "\n\n";
cudaFree(pi_components);
cudaFree(pi_components_2);
free(pi_comp_CPU);
free(pi_sum_h);
return 0;
}
//##################################################################################
void generate_components(myfloat* pi_comp, int n)
{
int sign = 1;
for (int i = 1; i < 2 * n; i += 2)
{
*(pi_comp + i / 2) = 4 * 1.0 / i * sign;
sign = -sign;
}
}
myfloat add_components(myfloat* pi_comp, int n)
{
myfloat pi_no = 0.0;
for (int i = 0; i < n; i++)
{
pi_no += pi_comp[i];
}
return pi_no;
}
void print_components(myfloat* pi_comp, int n)
{
for (int i = 0; i < n; i++)
{
std::cout << "comp " << i << ": " << pi_comp[i] << "\n";
}
}
|
.file "tmpxft_000372fc_00000000-6_pi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19generate_componentsPdi
.type _Z19generate_componentsPdi, @function
_Z19generate_componentsPdi:
.LFB3950:
.cfi_startproc
endbr64
addl %esi, %esi
cmpl $1, %esi
jle .L3
addl $1, %esi
movl $1, %edx
movl $1, %ecx
movsd .LC0(%rip), %xmm2
.L5:
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
cltq
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
negl %ecx
addl $2, %edx
cmpl %esi, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE3950:
.size _Z19generate_componentsPdi, .-_Z19generate_componentsPdi
.globl _Z14add_componentsPdi
.type _Z14add_componentsPdi, @function
_Z14add_componentsPdi:
.LFB3951:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rdx
pxor %xmm0, %xmm0
.L9:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L9
ret
.L10:
pxor %xmm0, %xmm0
ret
.cfi_endproc
.LFE3951:
.size _Z14add_componentsPdi, .-_Z14add_componentsPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "comp "
.LC3:
.string ": "
.LC4:
.string "\n"
.text
.globl _Z16print_componentsPdi
.type _Z16print_componentsPdi, @function
_Z16print_componentsPdi:
.LFB3952:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L17
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movslq %esi, %r13
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq _ZSt4cout(%rip), %r12
.L14:
movl $5, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r14,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3952:
.size _Z16print_componentsPdi, .-_Z16print_componentsPdi
.globl _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
.type _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i, @function
_Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20add_components_GPU_2PdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i, .-_Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
.globl _Z20add_components_GPU_2PdS_i
.type _Z20add_components_GPU_2PdS_i, @function
_Z20add_components_GPU_2PdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z20add_components_GPU_2PdS_i, .-_Z20add_components_GPU_2PdS_i
.section .rodata.str1.1
.LC5:
.string "n: "
.LC6:
.string "\n\n"
.LC7:
.string "pi_constant: "
.LC9:
.string "\n\nCPU\n"
.LC10:
.string "pi CPU: "
.LC11:
.string "Czas_CPU: "
.LC13:
.string " ms"
.LC14:
.string "pi_error: "
.LC15:
.string "cudaMalloc failed!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "add_components_GPU_2 launch failed: %s\n"
.section .rodata.str1.1
.LC17:
.string "\n\nGPU\n"
.LC18:
.string "pi GPU: "
.LC19:
.string "Czas_GPU: "
.LC20:
.string "Speedup: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $600000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movabsq $4800000000, %rdi
call malloc@PLT
movq %rax, %rbx
movl $600000000, %esi
movq %rax, %rdi
call _Z19generate_componentsPdi
call clock@PLT
movq %rax, %r14
movl $600000000, %esi
movq %rbx, %rdi
call _Z14add_componentsPdi
movsd %xmm0, 8(%rsp)
call clock@PLT
movq %rax, %r12
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC10(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r14, %r12
imulq $1000, %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm2
subsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 16(%rsp), %rdi
movabsq $4800032768, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
.L29:
leaq 24(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
.L30:
movl $1, %ecx
movabsq $4800000000, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r14
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
.L32:
movl $2, %ecx
movl $32768, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $4096, %esi
movq %rbx, %rdi
call _Z14add_componentsPdi
movsd %xmm0, 8(%rsp)
call clock@PLT
movq %rax, %rbp
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC18(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC19(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r14, %rbp
imulq $1000, %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm0
subsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %r14
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC20(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
divsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L29
.L36:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L37:
movl $146485, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
jmp .L31
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L32
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.globl _Z33__device_stub__Z12generate_GPUPdiPdi
.type _Z33__device_stub__Z12generate_GPUPdiPdi, @function
_Z33__device_stub__Z12generate_GPUPdiPdi:
.LFB3979:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12generate_GPUPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z33__device_stub__Z12generate_GPUPdiPdi, .-_Z33__device_stub__Z12generate_GPUPdiPdi
.globl _Z12generate_GPUPdi
.type _Z12generate_GPUPdi, @function
_Z12generate_GPUPdi:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12generate_GPUPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z12generate_GPUPdi, .-_Z12generate_GPUPdi
.section .rodata.str1.1
.LC21:
.string "_Z12generate_GPUPdi"
.LC22:
.string "_Z20add_components_GPU_2PdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3982:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z12generate_GPUPdi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z20add_components_GPU_2PdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC8:
.long 1413754136
.long 1074340347
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
#include <iomanip>
#include <math.h>
using namespace std;
typedef double myfloat;
const double pi_const = 3.1415926535897932384626433832795;
void generate_components(float* pi_comp, int n);
float add_components(float* pi_comp, int n);
void print_components(float* pi_comp, int n);
void generate_components(double* pi_comp, int n);
double add_components(double* pi_comp, int n);
void print_components(double* pi_comp, int n);
__global__ void add_components_GPU_2(myfloat* pi_components, myfloat* pi_components_2, int thr_adds)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x) * thr_adds;
for (int i = id_i; i < id_i + thr_adds; i++)
{
*(pi_components_2 + id_i / thr_adds) += *(pi_components + i);
}
}
__global__ void generate_GPU(myfloat* pi_components, int n)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x);
for (int i = id_i; i < n; i += blockDim.x + gridDim.x)
{
*(pi_components + i) = 4 * 1.0 / (2 * i + 1) * ((2 * i) % 4 ? -1.0 : 1.0);
}
}
int main()
{
int n = 1;
//std::cout << "Give n: ";
//std::cin >> n;
n = 600000000;
std::cout << "n: " << n << "\n\n";
myfloat* pi_comp_CPU = (myfloat*)malloc(n * sizeof(myfloat));
cudaError_t cudaStatus;
//Obliczenia CPU
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate_components(pi_comp_CPU, n);
clock_t start_CPU = clock();
myfloat pi_no = add_components(pi_comp_CPU, n);
clock_t stop_CPU = clock();
std::cout << "pi_constant: " << std::setprecision(50) << pi_const << "\n\n";
std::cout << "\n\nCPU\n";
std::cout << "pi CPU: " << std::setprecision(50) << pi_no << "\n";
std::cout << "Czas_CPU: " << 1000 * (stop_CPU - start_CPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - pi_no << "\n\n";
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//GPU
myfloat* pi_components;
myfloat* pi_components_2;
int BLOCK_SIZE = 256;
int GRID_SIZE = 16;
myfloat* pi_sum_h = (myfloat*)malloc(sizeof(myfloat));
cudaStatus = cudaMalloc(&pi_components, (n + BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!\n");
}
cudaStatus = cudaMalloc(&pi_components_2, BLOCK_SIZE * GRID_SIZE * sizeof(myfloat));//(n+1)/2
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!\n");
}
cudaMemcpy(pi_components, pi_comp_CPU, n * sizeof(myfloat), cudaMemcpyHostToDevice);
clock_t start_GPU = clock();
// Obliczenia GPU
//--------------------------------------------------------------
int thr_adds = (n + BLOCK_SIZE * GRID_SIZE - 1) / (BLOCK_SIZE * GRID_SIZE);//ile jeden watek ma wykonac dodawan
add_components_GPU_2 <<<GRID_SIZE, BLOCK_SIZE >>> (pi_components, pi_components_2, thr_adds);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "add_components_GPU_2 launch failed: %s\n", cudaGetErrorString(cudaStatus));
}
cudaMemcpy(pi_comp_CPU, pi_components_2, (BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat), cudaMemcpyDeviceToHost);
*pi_sum_h = add_components(pi_comp_CPU, (BLOCK_SIZE * GRID_SIZE));
//--------------------------------------------------------------
clock_t stop_GPU = clock();
std::cout << "\n\nGPU\n";
std::cout << "pi GPU: " << std::setprecision(50) << *pi_sum_h << "\n";
std::cout << "Czas_GPU: " << 1000 * (stop_GPU - start_GPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - *pi_sum_h << "\n\n";
std::cout << "Speedup: " << (double)(stop_CPU - start_CPU) / (stop_GPU - start_GPU) << "\n\n";
cudaFree(pi_components);
cudaFree(pi_components_2);
free(pi_comp_CPU);
free(pi_sum_h);
return 0;
}
//##################################################################################
void generate_components(myfloat* pi_comp, int n)
{
int sign = 1;
for (int i = 1; i < 2 * n; i += 2)
{
*(pi_comp + i / 2) = 4 * 1.0 / i * sign;
sign = -sign;
}
}
myfloat add_components(myfloat* pi_comp, int n)
{
myfloat pi_no = 0.0;
for (int i = 0; i < n; i++)
{
pi_no += pi_comp[i];
}
return pi_no;
}
void print_components(myfloat* pi_comp, int n)
{
for (int i = 0; i < n; i++)
{
std::cout << "comp " << i << ": " << pi_comp[i] << "\n";
}
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
#include <iomanip>
#include <math.h>
using namespace std;
typedef double myfloat;
const double pi_const = 3.1415926535897932384626433832795;
void generate_components(float* pi_comp, int n);
float add_components(float* pi_comp, int n);
void print_components(float* pi_comp, int n);
void generate_components(double* pi_comp, int n);
double add_components(double* pi_comp, int n);
void print_components(double* pi_comp, int n);
__global__ void add_components_GPU_2(myfloat* pi_components, myfloat* pi_components_2, int thr_adds)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x) * thr_adds;
for (int i = id_i; i < id_i + thr_adds; i++)
{
*(pi_components_2 + id_i / thr_adds) += *(pi_components + i);
}
}
__global__ void generate_GPU(myfloat* pi_components, int n)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x);
for (int i = id_i; i < n; i += blockDim.x + gridDim.x)
{
*(pi_components + i) = 4 * 1.0 / (2 * i + 1) * ((2 * i) % 4 ? -1.0 : 1.0);
}
}
int main()
{
int n = 1;
//std::cout << "Give n: ";
//std::cin >> n;
n = 600000000;
std::cout << "n: " << n << "\n\n";
myfloat* pi_comp_CPU = (myfloat*)malloc(n * sizeof(myfloat));
hipError_t cudaStatus;
//Obliczenia CPU
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate_components(pi_comp_CPU, n);
clock_t start_CPU = clock();
myfloat pi_no = add_components(pi_comp_CPU, n);
clock_t stop_CPU = clock();
std::cout << "pi_constant: " << std::setprecision(50) << pi_const << "\n\n";
std::cout << "\n\nCPU\n";
std::cout << "pi CPU: " << std::setprecision(50) << pi_no << "\n";
std::cout << "Czas_CPU: " << 1000 * (stop_CPU - start_CPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - pi_no << "\n\n";
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//GPU
myfloat* pi_components;
myfloat* pi_components_2;
int BLOCK_SIZE = 256;
int GRID_SIZE = 16;
myfloat* pi_sum_h = (myfloat*)malloc(sizeof(myfloat));
cudaStatus = hipMalloc(&pi_components, (n + BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!\n");
}
cudaStatus = hipMalloc(&pi_components_2, BLOCK_SIZE * GRID_SIZE * sizeof(myfloat));//(n+1)/2
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!\n");
}
hipMemcpy(pi_components, pi_comp_CPU, n * sizeof(myfloat), hipMemcpyHostToDevice);
clock_t start_GPU = clock();
// Obliczenia GPU
//--------------------------------------------------------------
int thr_adds = (n + BLOCK_SIZE * GRID_SIZE - 1) / (BLOCK_SIZE * GRID_SIZE);//ile jeden watek ma wykonac dodawan
add_components_GPU_2 <<<GRID_SIZE, BLOCK_SIZE >>> (pi_components, pi_components_2, thr_adds);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "add_components_GPU_2 launch failed: %s\n", hipGetErrorString(cudaStatus));
}
hipMemcpy(pi_comp_CPU, pi_components_2, (BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat), hipMemcpyDeviceToHost);
*pi_sum_h = add_components(pi_comp_CPU, (BLOCK_SIZE * GRID_SIZE));
//--------------------------------------------------------------
clock_t stop_GPU = clock();
std::cout << "\n\nGPU\n";
std::cout << "pi GPU: " << std::setprecision(50) << *pi_sum_h << "\n";
std::cout << "Czas_GPU: " << 1000 * (stop_GPU - start_GPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - *pi_sum_h << "\n\n";
std::cout << "Speedup: " << (double)(stop_CPU - start_CPU) / (stop_GPU - start_GPU) << "\n\n";
hipFree(pi_components);
hipFree(pi_components_2);
free(pi_comp_CPU);
free(pi_sum_h);
return 0;
}
//##################################################################################
void generate_components(myfloat* pi_comp, int n)
{
int sign = 1;
for (int i = 1; i < 2 * n; i += 2)
{
*(pi_comp + i / 2) = 4 * 1.0 / i * sign;
sign = -sign;
}
}
myfloat add_components(myfloat* pi_comp, int n)
{
myfloat pi_no = 0.0;
for (int i = 0; i < n; i++)
{
pi_no += pi_comp[i];
}
return pi_no;
}
void print_components(myfloat* pi_comp, int n)
{
for (int i = 0; i < n; i++)
{
std::cout << "comp " << i << ": " << pi_comp[i] << "\n";
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
#include <iomanip>
#include <math.h>
using namespace std;
typedef double myfloat;
const double pi_const = 3.1415926535897932384626433832795;
void generate_components(float* pi_comp, int n);
float add_components(float* pi_comp, int n);
void print_components(float* pi_comp, int n);
void generate_components(double* pi_comp, int n);
double add_components(double* pi_comp, int n);
void print_components(double* pi_comp, int n);
__global__ void add_components_GPU_2(myfloat* pi_components, myfloat* pi_components_2, int thr_adds)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x) * thr_adds;
for (int i = id_i; i < id_i + thr_adds; i++)
{
*(pi_components_2 + id_i / thr_adds) += *(pi_components + i);
}
}
__global__ void generate_GPU(myfloat* pi_components, int n)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x);
for (int i = id_i; i < n; i += blockDim.x + gridDim.x)
{
*(pi_components + i) = 4 * 1.0 / (2 * i + 1) * ((2 * i) % 4 ? -1.0 : 1.0);
}
}
int main()
{
int n = 1;
//std::cout << "Give n: ";
//std::cin >> n;
n = 600000000;
std::cout << "n: " << n << "\n\n";
myfloat* pi_comp_CPU = (myfloat*)malloc(n * sizeof(myfloat));
hipError_t cudaStatus;
//Obliczenia CPU
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate_components(pi_comp_CPU, n);
clock_t start_CPU = clock();
myfloat pi_no = add_components(pi_comp_CPU, n);
clock_t stop_CPU = clock();
std::cout << "pi_constant: " << std::setprecision(50) << pi_const << "\n\n";
std::cout << "\n\nCPU\n";
std::cout << "pi CPU: " << std::setprecision(50) << pi_no << "\n";
std::cout << "Czas_CPU: " << 1000 * (stop_CPU - start_CPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - pi_no << "\n\n";
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//GPU
myfloat* pi_components;
myfloat* pi_components_2;
int BLOCK_SIZE = 256;
int GRID_SIZE = 16;
myfloat* pi_sum_h = (myfloat*)malloc(sizeof(myfloat));
cudaStatus = hipMalloc(&pi_components, (n + BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!\n");
}
cudaStatus = hipMalloc(&pi_components_2, BLOCK_SIZE * GRID_SIZE * sizeof(myfloat));//(n+1)/2
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!\n");
}
hipMemcpy(pi_components, pi_comp_CPU, n * sizeof(myfloat), hipMemcpyHostToDevice);
clock_t start_GPU = clock();
// Obliczenia GPU
//--------------------------------------------------------------
int thr_adds = (n + BLOCK_SIZE * GRID_SIZE - 1) / (BLOCK_SIZE * GRID_SIZE);//ile jeden watek ma wykonac dodawan
add_components_GPU_2 <<<GRID_SIZE, BLOCK_SIZE >>> (pi_components, pi_components_2, thr_adds);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "add_components_GPU_2 launch failed: %s\n", hipGetErrorString(cudaStatus));
}
hipMemcpy(pi_comp_CPU, pi_components_2, (BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat), hipMemcpyDeviceToHost);
*pi_sum_h = add_components(pi_comp_CPU, (BLOCK_SIZE * GRID_SIZE));
//--------------------------------------------------------------
clock_t stop_GPU = clock();
std::cout << "\n\nGPU\n";
std::cout << "pi GPU: " << std::setprecision(50) << *pi_sum_h << "\n";
std::cout << "Czas_GPU: " << 1000 * (stop_GPU - start_GPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - *pi_sum_h << "\n\n";
std::cout << "Speedup: " << (double)(stop_CPU - start_CPU) / (stop_GPU - start_GPU) << "\n\n";
hipFree(pi_components);
hipFree(pi_components_2);
free(pi_comp_CPU);
free(pi_sum_h);
return 0;
}
//##################################################################################
void generate_components(myfloat* pi_comp, int n)
{
int sign = 1;
for (int i = 1; i < 2 * n; i += 2)
{
*(pi_comp + i / 2) = 4 * 1.0 / i * sign;
sign = -sign;
}
}
myfloat add_components(myfloat* pi_comp, int n)
{
myfloat pi_no = 0.0;
for (int i = 0; i < n; i++)
{
pi_no += pi_comp[i];
}
return pi_no;
}
void print_components(myfloat* pi_comp, int n)
{
for (int i = 0; i < n; i++)
{
std::cout << "comp " << i << ": " << pi_comp[i] << "\n";
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20add_components_GPU_2PdS_i
.globl _Z20add_components_GPU_2PdS_i
.p2align 8
.type _Z20add_components_GPU_2PdS_i,@function
_Z20add_components_GPU_2PdS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s3, s[0:1], 0x24
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s2, s4
s_xor_b32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v3
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, s3, v2
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v1, v2, v1
v_add_nc_u32_e32 v4, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v2, v1
v_xor_b32_e32 v2, v4, v3
v_xor_b32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v2, v1
v_mul_lo_u32 v4, v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v1
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v5
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v0
v_add_co_u32 v6, vcc_lo, s4, v6
global_load_b64 v[4:5], v[2:3], off
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.LBB0_2:
global_load_b64 v[8:9], v[6:7], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v6, s0, v6, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v1
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[8:9], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20add_components_GPU_2PdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20add_components_GPU_2PdS_i, .Lfunc_end0-_Z20add_components_GPU_2PdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12generate_GPUPdi
.globl _Z12generate_GPUPdi
.p2align 8
.type _Z12generate_GPUPdi,@function
_Z12generate_GPUPdi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_or_b32 v0, v1, 1, 1
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s6, s5, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
v_cvt_f64_i32_e32 v[2:3], v0
v_add_nc_u32_e32 v0, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 4.0
v_div_scale_f64 v[10:11], vcc_lo, 4.0, v[2:3], 4.0
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_mul_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_and_b32_e32 v7, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s0, 0, v7
v_div_fixup_f64 v[3:4], v[4:5], v[2:3], 4.0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s1, s2, v5
v_add_co_ci_u32_e64 v6, s1, s3, v6, s1
s_or_b32 s7, vcc_lo, s7
v_xor_b32_e32 v2, 0x80000000, v4
v_cndmask_b32_e64 v3, v3, v3, s0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v4, v2, v4, s0
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12generate_GPUPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12generate_GPUPdi, .Lfunc_end1-_Z12generate_GPUPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20add_components_GPU_2PdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20add_components_GPU_2PdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12generate_GPUPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12generate_GPUPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
#include <iomanip>
#include <math.h>
using namespace std;
typedef double myfloat;
const double pi_const = 3.1415926535897932384626433832795;
void generate_components(float* pi_comp, int n);
float add_components(float* pi_comp, int n);
void print_components(float* pi_comp, int n);
void generate_components(double* pi_comp, int n);
double add_components(double* pi_comp, int n);
void print_components(double* pi_comp, int n);
__global__ void add_components_GPU_2(myfloat* pi_components, myfloat* pi_components_2, int thr_adds)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x) * thr_adds;
for (int i = id_i; i < id_i + thr_adds; i++)
{
*(pi_components_2 + id_i / thr_adds) += *(pi_components + i);
}
}
__global__ void generate_GPU(myfloat* pi_components, int n)
{
int id_i = (blockIdx.x * blockDim.x + threadIdx.x);
for (int i = id_i; i < n; i += blockDim.x + gridDim.x)
{
*(pi_components + i) = 4 * 1.0 / (2 * i + 1) * ((2 * i) % 4 ? -1.0 : 1.0);
}
}
int main()
{
int n = 1;
//std::cout << "Give n: ";
//std::cin >> n;
n = 600000000;
std::cout << "n: " << n << "\n\n";
myfloat* pi_comp_CPU = (myfloat*)malloc(n * sizeof(myfloat));
hipError_t cudaStatus;
//Obliczenia CPU
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
generate_components(pi_comp_CPU, n);
clock_t start_CPU = clock();
myfloat pi_no = add_components(pi_comp_CPU, n);
clock_t stop_CPU = clock();
std::cout << "pi_constant: " << std::setprecision(50) << pi_const << "\n\n";
std::cout << "\n\nCPU\n";
std::cout << "pi CPU: " << std::setprecision(50) << pi_no << "\n";
std::cout << "Czas_CPU: " << 1000 * (stop_CPU - start_CPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - pi_no << "\n\n";
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//GPU
myfloat* pi_components;
myfloat* pi_components_2;
int BLOCK_SIZE = 256;
int GRID_SIZE = 16;
myfloat* pi_sum_h = (myfloat*)malloc(sizeof(myfloat));
cudaStatus = hipMalloc(&pi_components, (n + BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!\n");
}
cudaStatus = hipMalloc(&pi_components_2, BLOCK_SIZE * GRID_SIZE * sizeof(myfloat));//(n+1)/2
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!\n");
}
hipMemcpy(pi_components, pi_comp_CPU, n * sizeof(myfloat), hipMemcpyHostToDevice);
clock_t start_GPU = clock();
// Obliczenia GPU
//--------------------------------------------------------------
int thr_adds = (n + BLOCK_SIZE * GRID_SIZE - 1) / (BLOCK_SIZE * GRID_SIZE);//ile jeden watek ma wykonac dodawan
add_components_GPU_2 <<<GRID_SIZE, BLOCK_SIZE >>> (pi_components, pi_components_2, thr_adds);
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "add_components_GPU_2 launch failed: %s\n", hipGetErrorString(cudaStatus));
}
hipMemcpy(pi_comp_CPU, pi_components_2, (BLOCK_SIZE * GRID_SIZE) * sizeof(myfloat), hipMemcpyDeviceToHost);
*pi_sum_h = add_components(pi_comp_CPU, (BLOCK_SIZE * GRID_SIZE));
//--------------------------------------------------------------
clock_t stop_GPU = clock();
std::cout << "\n\nGPU\n";
std::cout << "pi GPU: " << std::setprecision(50) << *pi_sum_h << "\n";
std::cout << "Czas_GPU: " << 1000 * (stop_GPU - start_GPU) / ((double)CLOCKS_PER_SEC) << " ms" << std::endl;
std::cout << "pi_error: " << std::setprecision(50) << pi_const - *pi_sum_h << "\n\n";
std::cout << "Speedup: " << (double)(stop_CPU - start_CPU) / (stop_GPU - start_GPU) << "\n\n";
hipFree(pi_components);
hipFree(pi_components_2);
free(pi_comp_CPU);
free(pi_sum_h);
return 0;
}
//##################################################################################
void generate_components(myfloat* pi_comp, int n)
{
int sign = 1;
for (int i = 1; i < 2 * n; i += 2)
{
*(pi_comp + i / 2) = 4 * 1.0 / i * sign;
sign = -sign;
}
}
myfloat add_components(myfloat* pi_comp, int n)
{
myfloat pi_no = 0.0;
for (int i = 0; i < n; i++)
{
pi_no += pi_comp[i];
}
return pi_no;
}
void print_components(myfloat* pi_comp, int n)
{
for (int i = 0; i < n; i++)
{
std::cout << "comp " << i << ": " << pi_comp[i] << "\n";
}
}
|
.text
.file "pi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__add_components_GPU_2PdS_i # -- Begin function _Z35__device_stub__add_components_GPU_2PdS_i
.p2align 4, 0x90
.type _Z35__device_stub__add_components_GPU_2PdS_i,@function
_Z35__device_stub__add_components_GPU_2PdS_i: # @_Z35__device_stub__add_components_GPU_2PdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20add_components_GPU_2PdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__add_components_GPU_2PdS_i, .Lfunc_end0-_Z35__device_stub__add_components_GPU_2PdS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__generate_GPUPdi # -- Begin function _Z27__device_stub__generate_GPUPdi
.p2align 4, 0x90
.type _Z27__device_stub__generate_GPUPdi,@function
_Z27__device_stub__generate_GPUPdi: # @_Z27__device_stub__generate_GPUPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12generate_GPUPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__generate_GPUPdi, .Lfunc_end1-_Z27__device_stub__generate_GPUPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.LCPI2_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4800000000, %r15 # imm = 0x11E1A3000
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $600000000, %esi # imm = 0x23C34600
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movl $1, %eax
movq $-1, %rcx
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 2(%rcx), %rdx
xorps %xmm1, %xmm1
cvtsi2sd %edx, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
movsd %xmm1, 4(%rbx,%rcx,4)
negl %eax
movq %rdx, %rcx
cmpq $1199999998, %rdx # imm = 0x47868BFE
jb .LBB2_1
# %bb.2: # %_Z19generate_componentsPdi.exit
xorl %r14d, %r14d
callq clock
xorpd %xmm0, %xmm0
movq %rax, %r12
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i55
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%r14,8), %xmm0
incq %r14
cmpq $600000000, %r14 # imm = 0x23C34600
jne .LBB2_3
# %bb.4: # %_Z14add_componentsPdi.exit
movsd %xmm0, (%rsp) # 8-byte Spill
callq clock
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r14
imulq $1000, %r14, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_23
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB2_7
# %bb.6:
movzbl 67(%r13), %eax
jmp .LBB2_8
.LBB2_7:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 32768(%r15), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB2_9
.LBB2_10:
leaq 8(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
.LBB2_12:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
leaq -505032688(%r15), %rdi
addq $-505032448, %r15 # imm = 0xE1E5D100
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $146485, 28(%rsp) # imm = 0x23C35
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20add_components_GPU_2PdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_15
.LBB2_16:
movq 8(%rsp), %rsi
movl $32768, %edx # imm = 0x8000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_17: # %.lr.ph.i58
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB2_17
# %bb.18: # %_Z14add_componentsPdi.exit63
movsd %xmm0, (%rsp) # 8-byte Spill
callq clock
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
imulq $1000, %r15, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i65
cmpb $0, 56(%r13)
je .LBB2_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB2_22
.LBB2_21:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit68
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
cvtsi2sd %r15, %xmm1
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_10
.LBB2_11:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_12
.LBB2_15:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.LBB2_23:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19generate_componentsPdi
.LCPI3_0:
.quad 0x4010000000000000 # double 4
.text
.globl _Z19generate_componentsPdi
.p2align 4, 0x90
.type _Z19generate_componentsPdi,@function
_Z19generate_componentsPdi: # @_Z19generate_componentsPdi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
addl %esi, %esi
movl $1, %eax
movl $1, %ecx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
movsd %xmm1, -4(%rdi,%rcx,4)
negl %eax
addq $2, %rcx
cmpq %rsi, %rcx
jb .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z19generate_componentsPdi, .Lfunc_end3-_Z19generate_componentsPdi
.cfi_endproc
# -- End function
.globl _Z14add_componentsPdi # -- Begin function _Z14add_componentsPdi
.p2align 4, 0x90
.type _Z14add_componentsPdi,@function
_Z14add_componentsPdi: # @_Z14add_componentsPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addsd (%rdi,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_4
# %bb.2: # %._crit_edge
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _Z14add_componentsPdi, .Lfunc_end4-_Z14add_componentsPdi
.cfi_endproc
# -- End function
.globl _Z16print_componentsPdi # -- Begin function _Z16print_componentsPdi
.p2align 4, 0x90
.type _Z16print_componentsPdi,@function
_Z16print_componentsPdi: # @_Z16print_componentsPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r12d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.16, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r12
jne .LBB5_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB5_4: # %._crit_edge
retq
.Lfunc_end5:
.size _Z16print_componentsPdi, .Lfunc_end5-_Z16print_componentsPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20add_components_GPU_2PdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12generate_GPUPdi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20add_components_GPU_2PdS_i,@object # @_Z20add_components_GPU_2PdS_i
.section .rodata,"a",@progbits
.globl _Z20add_components_GPU_2PdS_i
.p2align 3, 0x0
_Z20add_components_GPU_2PdS_i:
.quad _Z35__device_stub__add_components_GPU_2PdS_i
.size _Z20add_components_GPU_2PdS_i, 8
.type _Z12generate_GPUPdi,@object # @_Z12generate_GPUPdi
.globl _Z12generate_GPUPdi
.p2align 3, 0x0
_Z12generate_GPUPdi:
.quad _Z27__device_stub__generate_GPUPdi
.size _Z12generate_GPUPdi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "n: "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pi_constant: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nCPU\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pi CPU: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Czas_CPU: "
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " ms"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "pi_error: "
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc failed!\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "add_components_GPU_2 launch failed: %s\n"
.size .L.str.10, 40
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n\nGPU\n"
.size .L.str.11, 7
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "pi GPU: "
.size .L.str.12, 9
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Czas_GPU: "
.size .L.str.13, 11
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Speedup: "
.size .L.str.14, 10
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "comp "
.size .L.str.15, 6
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz ": "
.size .L.str.16, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20add_components_GPU_2PdS_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12generate_GPUPdi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__add_components_GPU_2PdS_i
.addrsig_sym _Z27__device_stub__generate_GPUPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20add_components_GPU_2PdS_i
.addrsig_sym _Z12generate_GPUPdi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z12generate_GPUPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ LEA R2, R0, 0x1, 0x1 ; /* 0x0000000100027811 */
/* 0x000fe200078e08ff */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0090*/ BSSY B0, 0x1a0 ; /* 0x0000010000007945 */
/* 0x000fe80003800000 */
/*00a0*/ I2F.F64 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e300000201c00 */
/*00b0*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x001e240000001800 */
/*00c0*/ DFMA R6, -R2, R4, 1 ; /* 0x3ff000000206742b */
/* 0x001e0c0000000104 */
/*00d0*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*00e0*/ DFMA R6, R4, R6, R4 ; /* 0x000000060406722b */
/* 0x001e0c0000000004 */
/*00f0*/ DFMA R4, -R2, R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000106 */
/*0100*/ DFMA R4, R6, R4, R6 ; /* 0x000000040604722b */
/* 0x001e0c0000000006 */
/*0110*/ DMUL R6, R4, 4 ; /* 0x4010000004067828 */
/* 0x001e0c0000000000 */
/*0120*/ DFMA R8, -R2, R6, 4 ; /* 0x401000000208742b */
/* 0x001e0c0000000106 */
/*0130*/ DFMA R4, R4, R8, R6 ; /* 0x000000080404722b */
/* 0x001e140000000006 */
/*0140*/ FFMA R6, RZ, R3, R5 ; /* 0x00000003ff067223 */
/* 0x001fca0000000005 */
/*0150*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0160*/ @P0 BRA 0x190 ; /* 0x0000002000000947 */
/* 0x002fea0003800000 */
/*0170*/ MOV R6, 0x190 ; /* 0x0000019000067802 */
/* 0x000fe40000000f00 */
/*0180*/ CALL.REL.NOINC 0x280 ; /* 0x000000f000007944 */
/* 0x000fea0003c00000 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ LOP3.LUT R3, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100037812 */
/* 0x000fe200078ec0ff */
/*01b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3ff00000 ; /* 0x3ff00000ff027424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.NE.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc80003f05070 */
/*01e0*/ FSEL R3, -R2, 1.875, !P0 ; /* 0x3ff0000002037808 */
/* 0x000fe20004000100 */
/*01f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0200*/ DMUL R4, R4, R2 ; /* 0x0000000204047228 */
/* 0x0000a40000000000 */
/*0210*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fc800078e0207 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff077624 */
/* 0x000fe200078e00ff */
/*0230*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0041e8000c101b04 */
/*0240*/ IADD3 R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe007 */
/*0250*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0260*/ @!P0 BRA 0x70 ; /* 0xfffffe0000008947 */
/* 0x001fea000383ffff */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*02a0*/ LOP3.LUT R4, R3.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03047812 */
/* 0x040fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x40100000 ; /* 0x40100000ff107424 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R7, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003077812 */
/* 0x000fe200078ec0ff */
/*02d0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff117424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0002 */
/*0300*/ ISETP.LE.U32.AND P1, PT, R7, 0x40100000, PT ; /* 0x401000000700780c */
/* 0x000fe20003f23070 */
/*0310*/ BSSY B1, 0x720 ; /* 0x0000040000017945 */
/* 0x000fe20003800000 */
/*0320*/ IADD3 R14, R16, -0x1, RZ ; /* 0xffffffff100e7810 */
/* 0x000fc60007ffe0ff */
/*0330*/ @!P0 DMUL R4, R2, 8.98846567431157953865e+307 ; /* 0x7fe0000002048828 */
/* 0x000e0c0000000000 */
/*0340*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x001e280000001800 */
/*0350*/ @!P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005078812 */
/* 0x000fe400078ec0ff */
/*0360*/ ISETP.GT.U32.AND P0, PT, R14, 0x7feffffe, PT ; /* 0x7feffffe0e00780c */
/* 0x000fe40003f04070 */
/*0370*/ IADD3 R18, R7, -0x1, RZ ; /* 0xffffffff07127810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GT.U32.OR P0, PT, R18, 0x7feffffe, P0 ; /* 0x7feffffe1200780c */
/* 0x000fe20000704470 */
/*0390*/ DFMA R10, R8, -R4, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000804 */
/*03a0*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*03b0*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x0010640000000008 */
/*03c0*/ SEL R9, R17, 0x63400000, !P1 ; /* 0x6340000011097807 */
/* 0x001fe20004800000 */
/*03d0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc600078e00ff */
/*03e0*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x002e0c0000000804 */
/*03f0*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001e0c000000000a */
/*0400*/ DMUL R12, R10, R8 ; /* 0x000000080a0c7228 */
/* 0x001e0c0000000000 */
/*0410*/ DFMA R14, R12, -R4, R8 ; /* 0x800000040c0e722b */
/* 0x001e0c0000000008 */
/*0420*/ DFMA R10, R10, R14, R12 ; /* 0x0000000e0a0a722b */
/* 0x001062000000000c */
/*0430*/ @P0 BRA 0x600 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT R12, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030c7812 */
/* 0x001fe200078ec0ff */
/*0450*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e00ff */
/*0460*/ IADD3 R7, -R12.reuse, 0x40100000, RZ ; /* 0x401000000c077810 */
/* 0x040fe40007ffe1ff */
/*0470*/ ISETP.LE.U32.AND P0, PT, R12, 0x40100000, PT ; /* 0x401000000c00780c */
/* 0x000fe40003f03070 */
/*0480*/ IMNMX R7, R7, -0x46a00000, !PT ; /* 0xb960000007077817 */
/* 0x000fe40007800200 */
/*0490*/ SEL R12, R17, 0x63400000, !P0 ; /* 0x63400000110c7807 */
/* 0x000fe40004000000 */
/*04a0*/ IMNMX R7, R7, 0x46a00000, PT ; /* 0x46a0000007077817 */
/* 0x000fca0003800200 */
/*04b0*/ IMAD.IADD R16, R7, 0x1, -R12 ; /* 0x0000000107107824 */
/* 0x000fca00078e0a0c */
/*04c0*/ IADD3 R15, R16, 0x7fe00000, RZ ; /* 0x7fe00000100f7810 */
/* 0x000fcc0007ffe0ff */
/*04d0*/ DMUL R12, R10, R14 ; /* 0x0000000e0a0c7228 */
/* 0x002e140000000000 */
/*04e0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*04f0*/ @P0 BRA 0x710 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0500*/ DFMA R4, R10, -R4, R8 ; /* 0x800000040a04722b */
/* 0x000e220000000008 */
/*0510*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0520*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0530*/ LOP3.LUT R7, R5, 0x80000000, R3, 0x48, !PT ; /* 0x8000000005077812 */
/* 0x000fc800078e4803 */
/*0540*/ LOP3.LUT R15, R7, R15, RZ, 0xfc, !PT ; /* 0x0000000f070f7212 */
/* 0x000fce00078efcff */
/*0550*/ @!P0 BRA 0x710 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV R3, RZ, RZ, -R16 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a10 */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0580*/ DFMA R2, R12, -R2, R10 ; /* 0x800000020c02722b */
/* 0x000e08000000000a */
/*0590*/ DMUL.RP R10, R10, R14 ; /* 0x0000000e0a0a7228 */
/* 0x000e640000008000 */
/*05a0*/ IADD3 R2, -R16, -0x43300000, RZ ; /* 0xbcd0000010027810 */
/* 0x001fc80007ffe1ff */
/*05b0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*05c0*/ LOP3.LUT R7, R11, R7, RZ, 0x3c, !PT ; /* 0x000000070b077212 */
/* 0x002fe400078e3cff */
/*05d0*/ FSEL R12, R10, R12, !P0 ; /* 0x0000000c0a0c7208 */
/* 0x000fe40004000000 */
/*05e0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*05f0*/ BRA 0x710 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0600*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0610*/ @P0 BRA 0x6f0 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0620*/ ISETP.NE.AND P0, PT, R16, R7, PT ; /* 0x000000071000720c */
/* 0x000fe20003f05270 */
/*0630*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x001fe400078e00ff */
/*0640*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0650*/ @!P0 BRA 0x710 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0660*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0670*/ LOP3.LUT R2, R3, 0x40100000, RZ, 0x3c, !PT ; /* 0x4010000003027812 */
/* 0x000fe400078e3cff */
/*0680*/ ISETP.EQ.OR P0, PT, R7, RZ, !P0 ; /* 0x000000ff0700720c */
/* 0x000fe40004702670 */
/*0690*/ LOP3.LUT R13, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000020d7812 */
/* 0x000fd600078ec0ff */
/*06a0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*06b0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*06c0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*06d0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*06e0*/ BRA 0x710 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*06f0*/ LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030d7812 */
/* 0x001fe200078efcff */
/*0700*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0002 */
/*0710*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fe400078e00ff */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0740*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0750*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff8a006007950 */
/* 0x000fec0003c3ffff */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20add_components_GPU_2PdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0060*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e620000002100 */
/*0070*/ IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; /* 0x00000008ff0c7424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000ea20000209400 */
/*00a0*/ BSSY B0, 0x3d0 ; /* 0x0000032000007945 */
/* 0x000fee0003800000 */
/*00b0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x004ea20000001000 */
/*00c0*/ IMAD R5, R5, c[0x0][0x0], R4 ; /* 0x0000000005057a24 */
/* 0x003fc800078e0204 */
/*00d0*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fe200078e02ff */
/*00e0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x004fc80007ffe0ff */
/*00f0*/ IABS R0, R5 ; /* 0x0000000500007213 */
/* 0x000fe20000000000 */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0006 */
/*0140*/ IMAD R9, R4, R7, RZ ; /* 0x0000000704097224 */
/* 0x000fc800078e02ff */
/*0150*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R7, R2, R0 ; /* 0x0000000207007224 */
/* 0x000fe200078e0200 */
/*0190*/ LOP3.LUT R2, R5, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0005027a12 */
/* 0x000fc800078e3cff */
/*01a0*/ ISETP.GT.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe40003f04070 */
/*01b0*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fd60003f46270 */
/*01c0*/ @!P0 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x8000000700008210 */
/* 0x080fe40007ffe0ff */
/*01d0*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f26070 */
/*01f0*/ IADD3 R0, R5.reuse, c[0x0][0x170], RZ ; /* 0x00005c0005007a10 */
/* 0x040fe40007ffe0ff */
/*0200*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fc40003f05270 */
/*0220*/ IMNMX R2, R0, R7, !PT ; /* 0x0000000700027217 */
/* 0x000fe40007800200 */
/*0230*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fc600078e33ff */
/*0240*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.IADD R4, R2.reuse, 0x1, -R5 ; /* 0x0000000102047824 */
/* 0x040fe400078e0a05 */
/*0260*/ IMAD.IADD R7, R2, 0x1, R7 ; /* 0x0000000102077824 */
/* 0x000fe400078e0207 */
/*0270*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*0280*/ LOP3.LUT P2, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe4000784c0ff */
/*0290*/ @!P0 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff038a12 */
/* 0x000fe400078e33ff */
/*02a0*/ ISETP.GE.U32.AND P1, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fc60003f26070 */
/*02b0*/ IMAD.WIDE R2, R3, R12, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e020c */
/*02c0*/ @!P2 BRA 0x3c0 ; /* 0x000000f00000a947 */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000162000c1e1b00 */
/*02e0*/ IMAD.WIDE R6, R5, R12, c[0x0][0x160] ; /* 0x0000580005067625 */
/* 0x000fc800078e020c */
/*02f0*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0007 */
/*0300*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fca0000000f00 */
/*0310*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fcc00078e000b */
/*0330*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0340*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R10, P2, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007f5e0ff */
/*0360*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0370*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0390*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x026e4e0000000008 */
/*03a0*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0023e4000c101b04 */
/*03b0*/ @P0 BRA 0x310 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x002362000c1e1b00 */
/*03f0*/ IMAD.WIDE R6, R5, R12, c[0x0][0x160] ; /* 0x0000580005067625 */
/* 0x000fca00078e020c */
/*0400*/ IADD3 R4, P0, R6, 0x10, RZ ; /* 0x0000001006047810 */
/* 0x000fc80007f1e0ff */
/*0410*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x002fc600007fe4ff */
/*0420*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*0430*/ IMAD.MOV.U32 R15, RZ, RZ, R7 ; /* 0x000000ffff0f7224 */
/* 0x000fca00078e0007 */
/*0440*/ LDG.E.64 R6, [R14.64+-0x10] ; /* 0xfffff0040e067981 */
/* 0x004ea4000c1e1b00 */
/*0450*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x024e4e0000000008 */
/*0460*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0023e8000c101b04 */
/*0470*/ LDG.E.64 R8, [R14.64+-0x8] ; /* 0xfffff8040e087981 */
/* 0x000ea4000c1e1b00 */
/*0480*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x004e8e0000000008 */
/*0490*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*04a0*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ee4000c1e1b00 */
/*04b0*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x008ece0000000008 */
/*04c0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0085e8000c101b04 */
/*04d0*/ LDG.E.64 R8, [R14.64+0x8] ; /* 0x000008040e087981 */
/* 0x000ee2000c1e1b00 */
/*04e0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R4, P1, R14, 0x20, RZ ; /* 0x000000200e047810 */
/* 0x000fe40007f3e0ff */
/*0500*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fc60003f06270 */
/*0510*/ IMAD.X R7, RZ, RZ, R15, P1 ; /* 0x000000ffff077224 */
/* 0x002fe200008e060f */
/*0520*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x008e4e0000000008 */
/*0530*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0025e4000c101b04 */
/*0540*/ @!P0 BRA 0x420 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ BRA 0x560; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20add_components_GPU_2PdS_i
.globl _Z20add_components_GPU_2PdS_i
.p2align 8
.type _Z20add_components_GPU_2PdS_i,@function
_Z20add_components_GPU_2PdS_i:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s3, s[0:1], 0x24
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s2, s4
s_xor_b32 s5, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s5
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v2, v3
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, s3, v2
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v1, v2, v1
v_add_nc_u32_e32 v4, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v2, v1
v_xor_b32_e32 v2, v4, v3
v_xor_b32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v2, v1
v_mul_lo_u32 v4, v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v1
v_subrev_nc_u32_e32 v5, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v5
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v3
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v0
v_add_co_u32 v6, vcc_lo, s4, v6
global_load_b64 v[4:5], v[2:3], off
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
.LBB0_2:
global_load_b64 v[8:9], v[6:7], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v6, s0, v6, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v1
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[8:9], v[4:5]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20add_components_GPU_2PdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20add_components_GPU_2PdS_i, .Lfunc_end0-_Z20add_components_GPU_2PdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12generate_GPUPdi
.globl _Z12generate_GPUPdi
.p2align 8
.type _Z12generate_GPUPdi,@function
_Z12generate_GPUPdi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_3
s_load_b32 s6, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_lshl_or_b32 v0, v1, 1, 1
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s6, s5, 1
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
v_cvt_f64_i32_e32 v[2:3], v0
v_add_nc_u32_e32 v0, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 4.0
v_div_scale_f64 v[10:11], vcc_lo, 4.0, v[2:3], 4.0
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_mul_f64 v[8:9], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_and_b32_e32 v7, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s0, 0, v7
v_div_fixup_f64 v[3:4], v[4:5], v[2:3], 4.0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s5, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s1, s2, v5
v_add_co_ci_u32_e64 v6, s1, s3, v6, s1
s_or_b32 s7, vcc_lo, s7
v_xor_b32_e32 v2, 0x80000000, v4
v_cndmask_b32_e64 v3, v3, v3, s0
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v4, v2, v4, s0
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12generate_GPUPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12generate_GPUPdi, .Lfunc_end1-_Z12generate_GPUPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20add_components_GPU_2PdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20add_components_GPU_2PdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12generate_GPUPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12generate_GPUPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000372fc_00000000-6_pi.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19generate_componentsPdi
.type _Z19generate_componentsPdi, @function
_Z19generate_componentsPdi:
.LFB3950:
.cfi_startproc
endbr64
addl %esi, %esi
cmpl $1, %esi
jle .L3
addl $1, %esi
movl $1, %edx
movl $1, %ecx
movsd .LC0(%rip), %xmm2
.L5:
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
cltq
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %ecx, %xmm1
mulsd %xmm1, %xmm0
movsd %xmm0, (%rdi,%rax,8)
negl %ecx
addl $2, %edx
cmpl %esi, %edx
jne .L5
.L3:
ret
.cfi_endproc
.LFE3950:
.size _Z19generate_componentsPdi, .-_Z19generate_componentsPdi
.globl _Z14add_componentsPdi
.type _Z14add_componentsPdi, @function
_Z14add_componentsPdi:
.LFB3951:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L10
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rdx
pxor %xmm0, %xmm0
.L9:
addsd (%rax), %xmm0
addq $8, %rax
cmpq %rdx, %rax
jne .L9
ret
.L10:
pxor %xmm0, %xmm0
ret
.cfi_endproc
.LFE3951:
.size _Z14add_componentsPdi, .-_Z14add_componentsPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "comp "
.LC3:
.string ": "
.LC4:
.string "\n"
.text
.globl _Z16print_componentsPdi
.type _Z16print_componentsPdi, @function
_Z16print_componentsPdi:
.LFB3952:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L17
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r14
movslq %esi, %r13
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq _ZSt4cout(%rip), %r12
.L14:
movl $5, %edx
movq %r15, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r14,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L14
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3952:
.size _Z16print_componentsPdi, .-_Z16print_componentsPdi
.globl _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
.type _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i, @function
_Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i:
.LFB3977:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20add_components_GPU_2PdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i, .-_Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
.globl _Z20add_components_GPU_2PdS_i
.type _Z20add_components_GPU_2PdS_i, @function
_Z20add_components_GPU_2PdS_i:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z20add_components_GPU_2PdS_i, .-_Z20add_components_GPU_2PdS_i
.section .rodata.str1.1
.LC5:
.string "n: "
.LC6:
.string "\n\n"
.LC7:
.string "pi_constant: "
.LC9:
.string "\n\nCPU\n"
.LC10:
.string "pi CPU: "
.LC11:
.string "Czas_CPU: "
.LC13:
.string " ms"
.LC14:
.string "pi_error: "
.LC15:
.string "cudaMalloc failed!\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "add_components_GPU_2 launch failed: %s\n"
.section .rodata.str1.1
.LC17:
.string "\n\nGPU\n"
.LC18:
.string "pi GPU: "
.LC19:
.string "Czas_GPU: "
.LC20:
.string "Speedup: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $600000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC6(%rip), %r13
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movabsq $4800000000, %rdi
call malloc@PLT
movq %rax, %rbx
movl $600000000, %esi
movq %rax, %rdi
call _Z19generate_componentsPdi
call clock@PLT
movq %rax, %r14
movl $600000000, %esi
movq %rbx, %rdi
call _Z14add_componentsPdi
movsd %xmm0, 8(%rsp)
call clock@PLT
movq %rax, %r12
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC10(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r14, %r12
imulq $1000, %r12, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm2
subsd 8(%rsp), %xmm2
movapd %xmm2, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 16(%rsp), %rdi
movabsq $4800032768, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
.L29:
leaq 24(%rsp), %rdi
movl $32768, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
.L30:
movl $1, %ecx
movabsq $4800000000, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r14
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $16, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
.L32:
movl $2, %ecx
movl $32768, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $4096, %esi
movq %rbx, %rdi
call _Z14add_componentsPdi
movsd %xmm0, 8(%rsp)
call clock@PLT
movq %rax, %rbp
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC18(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC19(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %r14, %rbp
imulq $1000, %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC12(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $50, 8(%rdi,%rax)
movsd .LC8(%rip), %xmm0
subsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %r14
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC20(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2sdq %r12, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rbp, %xmm1
divsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L29
.L36:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L37:
movl $146485, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z20add_components_GPU_2PdS_iPdS_i
jmp .L31
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L32
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.globl _Z33__device_stub__Z12generate_GPUPdiPdi
.type _Z33__device_stub__Z12generate_GPUPdiPdi, @function
_Z33__device_stub__Z12generate_GPUPdiPdi:
.LFB3979:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12generate_GPUPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3979:
.size _Z33__device_stub__Z12generate_GPUPdiPdi, .-_Z33__device_stub__Z12generate_GPUPdiPdi
.globl _Z12generate_GPUPdi
.type _Z12generate_GPUPdi, @function
_Z12generate_GPUPdi:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12generate_GPUPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _Z12generate_GPUPdi, .-_Z12generate_GPUPdi
.section .rodata.str1.1
.LC21:
.string "_Z12generate_GPUPdi"
.LC22:
.string "_Z20add_components_GPU_2PdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3982:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z12generate_GPUPdi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z20add_components_GPU_2PdS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3982:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074790400
.align 8
.LC8:
.long 1413754136
.long 1074340347
.align 8
.LC12:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "pi.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__add_components_GPU_2PdS_i # -- Begin function _Z35__device_stub__add_components_GPU_2PdS_i
.p2align 4, 0x90
.type _Z35__device_stub__add_components_GPU_2PdS_i,@function
_Z35__device_stub__add_components_GPU_2PdS_i: # @_Z35__device_stub__add_components_GPU_2PdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20add_components_GPU_2PdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__add_components_GPU_2PdS_i, .Lfunc_end0-_Z35__device_stub__add_components_GPU_2PdS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__generate_GPUPdi # -- Begin function _Z27__device_stub__generate_GPUPdi
.p2align 4, 0x90
.type _Z27__device_stub__generate_GPUPdi,@function
_Z27__device_stub__generate_GPUPdi: # @_Z27__device_stub__generate_GPUPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12generate_GPUPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__generate_GPUPdi, .Lfunc_end1-_Z27__device_stub__generate_GPUPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.LCPI2_1:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4800000000, %r15 # imm = 0x11E1A3000
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $600000000, %esi # imm = 0x23C34600
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movl $1, %eax
movq $-1, %rcx
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 2(%rcx), %rdx
xorps %xmm1, %xmm1
cvtsi2sd %edx, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
movsd %xmm1, 4(%rbx,%rcx,4)
negl %eax
movq %rdx, %rcx
cmpq $1199999998, %rdx # imm = 0x47868BFE
jb .LBB2_1
# %bb.2: # %_Z19generate_componentsPdi.exit
xorl %r14d, %r14d
callq clock
xorpd %xmm0, %xmm0
movq %rax, %r12
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i55
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%r14,8), %xmm0
incq %r14
cmpq $600000000, %r14 # imm = 0x23C34600
jne .LBB2_3
# %bb.4: # %_Z14add_componentsPdi.exit
movsd %xmm0, (%rsp) # 8-byte Spill
callq clock
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r14
imulq $1000, %r14, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_23
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB2_7
# %bb.6:
movzbl 67(%r13), %eax
jmp .LBB2_8
.LBB2_7:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 32768(%r15), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB2_9
.LBB2_10:
leaq 8(%rsp), %rdi
movl $32768, %esi # imm = 0x8000
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
.LBB2_12:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
leaq -505032688(%r15), %rdi
addq $-505032448, %r15 # imm = 0xE1E5D100
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $146485, 28(%rsp) # imm = 0x23C35
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20add_components_GPU_2PdS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_15
.LBB2_16:
movq 8(%rsp), %rsi
movl $32768, %edx # imm = 0x8000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorpd %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_17: # %.lr.ph.i58
# =>This Inner Loop Header: Depth=1
addsd (%rbx,%rax,8), %xmm0
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB2_17
# %bb.18: # %_Z14add_componentsPdi.exit63
movsd %xmm0, (%rsp) # 8-byte Spill
callq clock
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
imulq $1000, %r15, %rax # imm = 0x3E8
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.7, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i65
cmpb $0, 56(%r13)
je .LBB2_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB2_22
.LBB2_21:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit68
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $50, _ZSt4cout+8(%rax)
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
cvtsi2sd %r15, %xmm1
divsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_10
.LBB2_11:
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB2_12
.LBB2_15:
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.LBB2_23:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19generate_componentsPdi
.LCPI3_0:
.quad 0x4010000000000000 # double 4
.text
.globl _Z19generate_componentsPdi
.p2align 4, 0x90
.type _Z19generate_componentsPdi,@function
_Z19generate_componentsPdi: # @_Z19generate_componentsPdi
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
addl %esi, %esi
movl $1, %eax
movl $1, %ecx
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
mulsd %xmm2, %xmm1
movsd %xmm1, -4(%rdi,%rcx,4)
negl %eax
addq $2, %rcx
cmpq %rsi, %rcx
jb .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z19generate_componentsPdi, .Lfunc_end3-_Z19generate_componentsPdi
.cfi_endproc
# -- End function
.globl _Z14add_componentsPdi # -- Begin function _Z14add_componentsPdi
.p2align 4, 0x90
.type _Z14add_componentsPdi,@function
_Z14add_componentsPdi: # @_Z14add_componentsPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB4_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addsd (%rdi,%rcx,8), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB4_4
# %bb.2: # %._crit_edge
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _Z14add_componentsPdi, .Lfunc_end4-_Z14add_componentsPdi
.cfi_endproc
# -- End function
.globl _Z16print_componentsPdi # -- Begin function _Z16print_componentsPdi
.p2align 4, 0x90
.type _Z16print_componentsPdi,@function
_Z16print_componentsPdi: # @_Z16print_componentsPdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB5_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r12d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.16, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r12
jne .LBB5_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB5_4: # %._crit_edge
retq
.Lfunc_end5:
.size _Z16print_componentsPdi, .Lfunc_end5-_Z16print_componentsPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20add_components_GPU_2PdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12generate_GPUPdi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20add_components_GPU_2PdS_i,@object # @_Z20add_components_GPU_2PdS_i
.section .rodata,"a",@progbits
.globl _Z20add_components_GPU_2PdS_i
.p2align 3, 0x0
_Z20add_components_GPU_2PdS_i:
.quad _Z35__device_stub__add_components_GPU_2PdS_i
.size _Z20add_components_GPU_2PdS_i, 8
.type _Z12generate_GPUPdi,@object # @_Z12generate_GPUPdi
.globl _Z12generate_GPUPdi
.p2align 3, 0x0
_Z12generate_GPUPdi:
.quad _Z27__device_stub__generate_GPUPdi
.size _Z12generate_GPUPdi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "n: "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pi_constant: "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n\nCPU\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pi CPU: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Czas_CPU: "
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " ms"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "pi_error: "
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc failed!\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "add_components_GPU_2 launch failed: %s\n"
.size .L.str.10, 40
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\n\nGPU\n"
.size .L.str.11, 7
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "pi GPU: "
.size .L.str.12, 9
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Czas_GPU: "
.size .L.str.13, 11
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Speedup: "
.size .L.str.14, 10
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "comp "
.size .L.str.15, 6
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz ": "
.size .L.str.16, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20add_components_GPU_2PdS_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12generate_GPUPdi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__add_components_GPU_2PdS_i
.addrsig_sym _Z27__device_stub__generate_GPUPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20add_components_GPU_2PdS_i
.addrsig_sym _Z12generate_GPUPdi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
rkrish11 Rahul Krishna
*/
#include "cuda.h"
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define SEED 35791246
__global__ void init_stuff(curandState *state, int count) {
// This sets a random number seed for all the threads
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<count)
curand_init(1337, idx, 0, &state[idx]);
}
__global__ void cudaMonte(double* pi, int count, curandState* state) {
// Perfome MC simulation on the threads
int id=blockIdx.x*blockDim.x+threadIdx.x;
double x,y,z;
if (id<count) {
x = (double)curand_uniform(&state[id]);
y = (double)curand_uniform(&state[id]);
z = x*x+y*y;
if (z<=1) pi[id]=1;
else pi[id]=0;
}
__syncthreads();
// Find the total number of points that lie inside the quadrant of the cirle
for (int i=1; i<count;i++) {
pi[0]+=pi[i];
}
}
int main(int argc, char** argv) {
int niter=0;
double pi;
double* d_pi;
curandState *d_state;
printf("Enter the number of iterations used to estimate pi: ");
scanf("%d",&niter);
double* h_pi = new double[niter];
if (cudaMalloc(&d_pi, sizeof(int)*niter) != cudaSuccess) {
printf("Error in memory allocation.\n");
return 0;
}
if (cudaMalloc(&d_state, sizeof(curandState)*niter) != cudaSuccess) {
printf("Error in memory allocation for random state.\n");
return 0;
}
if (cudaMemcpy (d_pi, h_pi, sizeof(int)*niter, cudaMemcpyHostToDevice) != cudaSuccess) {
printf("Error in copy from host to device.\n");
cudaFree(d_pi);
return 0;
}
// Number of threads = 1024, number of blocks = (int) (niter/threads)+1
init_stuff<<<(int) niter/1024+1, 1024>>>(d_state, niter);
cudaMonte<<<(int) niter/1024+1, 1024>>>(d_pi, niter, d_state);
if (cudaMemcpy (h_pi, d_pi, sizeof(int)*niter, cudaMemcpyDeviceToHost) != cudaSuccess) {
printf("Error in copy from device to host.\n");
delete[] h_pi;
cudaFree(d_pi);
return 0;
}
// Final Estimate of pi
pi= (double) h_pi[0]/niter*4;
printf("# of trials= %d , estimate of pi is %g \n",niter,pi);
}
|
.file "tmpxft_000fdaff_00000000-6_monteCarlo.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3886:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
.type _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi, @function
_Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi:
.LFB3908:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_stuffP17curandStateXORWOWi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3908:
.size _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi, .-_Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
.globl _Z10init_stuffP17curandStateXORWOWi
.type _Z10init_stuffP17curandStateXORWOWi, @function
_Z10init_stuffP17curandStateXORWOWi:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _Z10init_stuffP17curandStateXORWOWi, .-_Z10init_stuffP17curandStateXORWOWi
.globl _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
.type _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW, @function
_Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW:
.LFB3910:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cudaMontePdiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3910:
.size _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW, .-_Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
.globl _Z9cudaMontePdiP17curandStateXORWOW
.type _Z9cudaMontePdiP17curandStateXORWOW, @function
_Z9cudaMontePdiP17curandStateXORWOW:
.LFB3911:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3911:
.size _Z9cudaMontePdiP17curandStateXORWOW, .-_Z9cudaMontePdiP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter the number of iterations used to estimate pi: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d"
.LC2:
.string "Error in memory allocation.\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Error in memory allocation for random state.\n"
.align 8
.LC4:
.string "Error in copy from host to device.\n"
.align 8
.LC5:
.string "Error in copy from device to host.\n"
.align 8
.LC7:
.string "# of trials= %d , estimate of pi is %g \n"
.text
.globl main
.type main, @function
main:
.LFB3883:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 12(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L20
salq $3, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq 12(%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movslq 12(%rsp), %rsi
imulq $48, %rsi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 12(%rsp), %eax
movl $1024, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L27:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 12(%rsp), %eax
movl $1024, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L28:
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movl 12(%rsp), %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movsd (%rbx), %xmm0
divsd %xmm1, %xmm0
mulsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L24
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L33:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L35:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L24
.L36:
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
jmp .L27
.L37:
movq 24(%rsp), %rdx
movl 12(%rsp), %esi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
jmp .L28
.L38:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L24
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3883:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z9cudaMontePdiP17curandStateXORWOW"
.align 8
.LC9:
.string "_Z10init_stuffP17curandStateXORWOWi"
.section .rodata.str1.1
.LC10:
.string "precalc_xorwow_matrix"
.LC11:
.string "precalc_xorwow_offset_matrix"
.LC12:
.string "mrg32k3aM1"
.LC13:
.string "mrg32k3aM2"
.LC14:
.string "mrg32k3aM1SubSeq"
.LC15:
.string "mrg32k3aM2SubSeq"
.LC16:
.string "mrg32k3aM1Seq"
.LC17:
.string "mrg32k3aM2Seq"
.LC18:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3913:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaMontePdiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_stuffP17curandStateXORWOWi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3913:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
rkrish11 Rahul Krishna
*/
#include "cuda.h"
#include <curand.h>
#include <curand_kernel.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define SEED 35791246
__global__ void init_stuff(curandState *state, int count) {
// This sets a random number seed for all the threads
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<count)
curand_init(1337, idx, 0, &state[idx]);
}
__global__ void cudaMonte(double* pi, int count, curandState* state) {
// Perfome MC simulation on the threads
int id=blockIdx.x*blockDim.x+threadIdx.x;
double x,y,z;
if (id<count) {
x = (double)curand_uniform(&state[id]);
y = (double)curand_uniform(&state[id]);
z = x*x+y*y;
if (z<=1) pi[id]=1;
else pi[id]=0;
}
__syncthreads();
// Find the total number of points that lie inside the quadrant of the cirle
for (int i=1; i<count;i++) {
pi[0]+=pi[i];
}
}
int main(int argc, char** argv) {
int niter=0;
double pi;
double* d_pi;
curandState *d_state;
printf("Enter the number of iterations used to estimate pi: ");
scanf("%d",&niter);
double* h_pi = new double[niter];
if (cudaMalloc(&d_pi, sizeof(int)*niter) != cudaSuccess) {
printf("Error in memory allocation.\n");
return 0;
}
if (cudaMalloc(&d_state, sizeof(curandState)*niter) != cudaSuccess) {
printf("Error in memory allocation for random state.\n");
return 0;
}
if (cudaMemcpy (d_pi, h_pi, sizeof(int)*niter, cudaMemcpyHostToDevice) != cudaSuccess) {
printf("Error in copy from host to device.\n");
cudaFree(d_pi);
return 0;
}
// Number of threads = 1024, number of blocks = (int) (niter/threads)+1
init_stuff<<<(int) niter/1024+1, 1024>>>(d_state, niter);
cudaMonte<<<(int) niter/1024+1, 1024>>>(d_pi, niter, d_state);
if (cudaMemcpy (h_pi, d_pi, sizeof(int)*niter, cudaMemcpyDeviceToHost) != cudaSuccess) {
printf("Error in copy from device to host.\n");
delete[] h_pi;
cudaFree(d_pi);
return 0;
}
// Final Estimate of pi
pi= (double) h_pi[0]/niter*4;
printf("# of trials= %d , estimate of pi is %g \n",niter,pi);
}
|
/*
rkrish11 Rahul Krishna
*/
#include "hip/hip_runtime.h"
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define SEED 35791246
__global__ void init_stuff(hiprandState *state, int count) {
// This sets a random number seed for all the threads
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<count)
hiprand_init(1337, idx, 0, &state[idx]);
}
__global__ void cudaMonte(double* pi, int count, hiprandState* state) {
// Perfome MC simulation on the threads
int id=blockIdx.x*blockDim.x+threadIdx.x;
double x,y,z;
if (id<count) {
x = (double)hiprand_uniform(&state[id]);
y = (double)hiprand_uniform(&state[id]);
z = x*x+y*y;
if (z<=1) pi[id]=1;
else pi[id]=0;
}
__syncthreads();
// Find the total number of points that lie inside the quadrant of the cirle
for (int i=1; i<count;i++) {
pi[0]+=pi[i];
}
}
int main(int argc, char** argv) {
int niter=0;
double pi;
double* d_pi;
hiprandState *d_state;
printf("Enter the number of iterations used to estimate pi: ");
scanf("%d",&niter);
double* h_pi = new double[niter];
if (hipMalloc(&d_pi, sizeof(int)*niter) != hipSuccess) {
printf("Error in memory allocation.\n");
return 0;
}
if (hipMalloc(&d_state, sizeof(hiprandState)*niter) != hipSuccess) {
printf("Error in memory allocation for random state.\n");
return 0;
}
if (hipMemcpy (d_pi, h_pi, sizeof(int)*niter, hipMemcpyHostToDevice) != hipSuccess) {
printf("Error in copy from host to device.\n");
hipFree(d_pi);
return 0;
}
// Number of threads = 1024, number of blocks = (int) (niter/threads)+1
init_stuff<<<(int) niter/1024+1, 1024>>>(d_state, niter);
cudaMonte<<<(int) niter/1024+1, 1024>>>(d_pi, niter, d_state);
if (hipMemcpy (h_pi, d_pi, sizeof(int)*niter, hipMemcpyDeviceToHost) != hipSuccess) {
printf("Error in copy from device to host.\n");
delete[] h_pi;
hipFree(d_pi);
return 0;
}
// Final Estimate of pi
pi= (double) h_pi[0]/niter*4;
printf("# of trials= %d , estimate of pi is %g \n",niter,pi);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
rkrish11 Rahul Krishna
*/
#include "hip/hip_runtime.h"
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#define SEED 35791246
__global__ void init_stuff(hiprandState *state, int count) {
// This sets a random number seed for all the threads
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<count)
hiprand_init(1337, idx, 0, &state[idx]);
}
__global__ void cudaMonte(double* pi, int count, hiprandState* state) {
// Perfome MC simulation on the threads
int id=blockIdx.x*blockDim.x+threadIdx.x;
double x,y,z;
if (id<count) {
x = (double)hiprand_uniform(&state[id]);
y = (double)hiprand_uniform(&state[id]);
z = x*x+y*y;
if (z<=1) pi[id]=1;
else pi[id]=0;
}
__syncthreads();
// Find the total number of points that lie inside the quadrant of the cirle
for (int i=1; i<count;i++) {
pi[0]+=pi[i];
}
}
int main(int argc, char** argv) {
int niter=0;
double pi;
double* d_pi;
hiprandState *d_state;
printf("Enter the number of iterations used to estimate pi: ");
scanf("%d",&niter);
double* h_pi = new double[niter];
if (hipMalloc(&d_pi, sizeof(int)*niter) != hipSuccess) {
printf("Error in memory allocation.\n");
return 0;
}
if (hipMalloc(&d_state, sizeof(hiprandState)*niter) != hipSuccess) {
printf("Error in memory allocation for random state.\n");
return 0;
}
if (hipMemcpy (d_pi, h_pi, sizeof(int)*niter, hipMemcpyHostToDevice) != hipSuccess) {
printf("Error in copy from host to device.\n");
hipFree(d_pi);
return 0;
}
// Number of threads = 1024, number of blocks = (int) (niter/threads)+1
init_stuff<<<(int) niter/1024+1, 1024>>>(d_state, niter);
cudaMonte<<<(int) niter/1024+1, 1024>>>(d_pi, niter, d_state);
if (hipMemcpy (h_pi, d_pi, sizeof(int)*niter, hipMemcpyDeviceToHost) != hipSuccess) {
printf("Error in copy from device to host.\n");
delete[] h_pi;
hipFree(d_pi);
return 0;
}
// Final Estimate of pi
pi= (double) h_pi[0]/niter*4;
printf("# of trials= %d , estimate of pi is %g \n",niter,pi);
}
|
.text
.file "monteCarlo.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__init_stuffP12hiprandStatei # -- Begin function _Z25__device_stub__init_stuffP12hiprandStatei
.p2align 4, 0x90
.type _Z25__device_stub__init_stuffP12hiprandStatei,@function
_Z25__device_stub__init_stuffP12hiprandStatei: # @_Z25__device_stub__init_stuffP12hiprandStatei
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10init_stuffP12hiprandStatei, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__init_stuffP12hiprandStatei, .Lfunc_end0-_Z25__device_stub__init_stuffP12hiprandStatei
.cfi_endproc
# -- End function
.globl _Z24__device_stub__cudaMontePdiP12hiprandState # -- Begin function _Z24__device_stub__cudaMontePdiP12hiprandState
.p2align 4, 0x90
.type _Z24__device_stub__cudaMontePdiP12hiprandState,@function
_Z24__device_stub__cudaMontePdiP12hiprandState: # @_Z24__device_stub__cudaMontePdiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9cudaMontePdiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__cudaMontePdiP12hiprandState, .Lfunc_end1-_Z24__device_stub__cudaMontePdiP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
leaq (,%r14,8), %rax
testq %r14, %r14
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %rbx
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
jmp .LBB2_14
.LBB2_2:
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB2_14
.LBB2_4:
movq 8(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_7
# %bb.5:
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB2_6
.LBB2_7:
movabsq $4294967296, %r14 # imm = 0x100000000
movl 4(%rsp), %eax
leal 1023(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
orq %r14, %rdi
leaq 1024(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 16(%rsp), %rdi
movl 4(%rsp), %esi
callq _Z25__device_stub__init_stuffP12hiprandStatei
.LBB2_9:
movl 4(%rsp), %eax
leal 1023(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
orq %r14, %rdi
addq $1024, %r14 # imm = 0x400
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 8(%rsp), %rdi
movl 4(%rsp), %esi
movq 16(%rsp), %rdx
callq _Z24__device_stub__cudaMontePdiP12hiprandState
.LBB2_11:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdaPv
.LBB2_6:
movq 8(%rsp), %rdi
callq hipFree
.LBB2_14:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 48
movl 4(%rsp), %esi
cvtsi2sd %esi, %xmm1
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
jmp .LBB2_14
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_stuffP12hiprandStatei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaMontePdiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10init_stuffP12hiprandStatei,@object # @_Z10init_stuffP12hiprandStatei
.section .rodata,"a",@progbits
.globl _Z10init_stuffP12hiprandStatei
.p2align 3, 0x0
_Z10init_stuffP12hiprandStatei:
.quad _Z25__device_stub__init_stuffP12hiprandStatei
.size _Z10init_stuffP12hiprandStatei, 8
.type _Z9cudaMontePdiP12hiprandState,@object # @_Z9cudaMontePdiP12hiprandState
.globl _Z9cudaMontePdiP12hiprandState
.p2align 3, 0x0
_Z9cudaMontePdiP12hiprandState:
.quad _Z24__device_stub__cudaMontePdiP12hiprandState
.size _Z9cudaMontePdiP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the number of iterations used to estimate pi: "
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "# of trials= %d , estimate of pi is %g \n"
.size .L.str.6, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10init_stuffP12hiprandStatei"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9cudaMontePdiP12hiprandState"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error in copy from device to host."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error in copy from host to device."
.size .Lstr.1, 35
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error in memory allocation for random state."
.size .Lstr.2, 45
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error in memory allocation."
.size .Lstr.3, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__init_stuffP12hiprandStatei
.addrsig_sym _Z24__device_stub__cudaMontePdiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10init_stuffP12hiprandStatei
.addrsig_sym _Z9cudaMontePdiP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000fdaff_00000000-6_monteCarlo.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3886:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
.type _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi, @function
_Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi:
.LFB3908:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_stuffP17curandStateXORWOWi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3908:
.size _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi, .-_Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
.globl _Z10init_stuffP17curandStateXORWOWi
.type _Z10init_stuffP17curandStateXORWOWi, @function
_Z10init_stuffP17curandStateXORWOWi:
.LFB3909:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3909:
.size _Z10init_stuffP17curandStateXORWOWi, .-_Z10init_stuffP17curandStateXORWOWi
.globl _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
.type _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW, @function
_Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW:
.LFB3910:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9cudaMontePdiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3910:
.size _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW, .-_Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
.globl _Z9cudaMontePdiP17curandStateXORWOW
.type _Z9cudaMontePdiP17curandStateXORWOW, @function
_Z9cudaMontePdiP17curandStateXORWOW:
.LFB3911:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3911:
.size _Z9cudaMontePdiP17curandStateXORWOW, .-_Z9cudaMontePdiP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Enter the number of iterations used to estimate pi: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d"
.LC2:
.string "Error in memory allocation.\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Error in memory allocation for random state.\n"
.align 8
.LC4:
.string "Error in copy from host to device.\n"
.align 8
.LC5:
.string "Error in copy from device to host.\n"
.align 8
.LC7:
.string "# of trials= %d , estimate of pi is %g \n"
.text
.globl main
.type main, @function
main:
.LFB3883:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 12(%rsp), %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L20
salq $3, %rdi
call _Znam@PLT
movq %rax, %rbx
movslq 12(%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movslq 12(%rsp), %rsi
imulq $48, %rsi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L35
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 12(%rsp), %eax
movl $1024, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L27:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 12(%rsp), %eax
movl $1024, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L28:
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
movl 12(%rsp), %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movsd (%rbx), %xmm0
divsd %xmm1, %xmm0
mulsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L24
.L20:
movq 56(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L33:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L24:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L35:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L24
.L36:
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z49__device_stub__Z10init_stuffP17curandStateXORWOWiP17curandStateXORWOWi
jmp .L27
.L37:
movq 24(%rsp), %rdx
movl 12(%rsp), %esi
movq 16(%rsp), %rdi
call _Z49__device_stub__Z9cudaMontePdiP17curandStateXORWOWPdiP17curandStateXORWOW
jmp .L28
.L38:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L24
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3883:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z9cudaMontePdiP17curandStateXORWOW"
.align 8
.LC9:
.string "_Z10init_stuffP17curandStateXORWOWi"
.section .rodata.str1.1
.LC10:
.string "precalc_xorwow_matrix"
.LC11:
.string "precalc_xorwow_offset_matrix"
.LC12:
.string "mrg32k3aM1"
.LC13:
.string "mrg32k3aM2"
.LC14:
.string "mrg32k3aM1SubSeq"
.LC15:
.string "mrg32k3aM2SubSeq"
.LC16:
.string "mrg32k3aM1Seq"
.LC17:
.string "mrg32k3aM2Seq"
.LC18:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3913:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9cudaMontePdiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_stuffP17curandStateXORWOWi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3913:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "monteCarlo.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__init_stuffP12hiprandStatei # -- Begin function _Z25__device_stub__init_stuffP12hiprandStatei
.p2align 4, 0x90
.type _Z25__device_stub__init_stuffP12hiprandStatei,@function
_Z25__device_stub__init_stuffP12hiprandStatei: # @_Z25__device_stub__init_stuffP12hiprandStatei
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10init_stuffP12hiprandStatei, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__init_stuffP12hiprandStatei, .Lfunc_end0-_Z25__device_stub__init_stuffP12hiprandStatei
.cfi_endproc
# -- End function
.globl _Z24__device_stub__cudaMontePdiP12hiprandState # -- Begin function _Z24__device_stub__cudaMontePdiP12hiprandState
.p2align 4, 0x90
.type _Z24__device_stub__cudaMontePdiP12hiprandState,@function
_Z24__device_stub__cudaMontePdiP12hiprandState: # @_Z24__device_stub__cudaMontePdiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9cudaMontePdiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__cudaMontePdiP12hiprandState, .Lfunc_end1-_Z24__device_stub__cudaMontePdiP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
leaq (,%r14,8), %rax
testq %r14, %r14
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %rbx
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
jmp .LBB2_14
.LBB2_2:
movslq 4(%rsp), %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $.Lstr.2, %edi
callq puts@PLT
jmp .LBB2_14
.LBB2_4:
movq 8(%rsp), %rdi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_7
# %bb.5:
movl $.Lstr.1, %edi
callq puts@PLT
jmp .LBB2_6
.LBB2_7:
movabsq $4294967296, %r14 # imm = 0x100000000
movl 4(%rsp), %eax
leal 1023(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
orq %r14, %rdi
leaq 1024(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 16(%rsp), %rdi
movl 4(%rsp), %esi
callq _Z25__device_stub__init_stuffP12hiprandStatei
.LBB2_9:
movl 4(%rsp), %eax
leal 1023(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
orq %r14, %rdi
addq $1024, %r14 # imm = 0x400
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 8(%rsp), %rdi
movl 4(%rsp), %esi
movq 16(%rsp), %rdx
callq _Z24__device_stub__cudaMontePdiP12hiprandState
.LBB2_11:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq _ZdaPv
.LBB2_6:
movq 8(%rsp), %rdi
callq hipFree
.LBB2_14:
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 48
movl 4(%rsp), %esi
cvtsi2sd %esi, %xmm1
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
jmp .LBB2_14
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_stuffP12hiprandStatei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9cudaMontePdiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10init_stuffP12hiprandStatei,@object # @_Z10init_stuffP12hiprandStatei
.section .rodata,"a",@progbits
.globl _Z10init_stuffP12hiprandStatei
.p2align 3, 0x0
_Z10init_stuffP12hiprandStatei:
.quad _Z25__device_stub__init_stuffP12hiprandStatei
.size _Z10init_stuffP12hiprandStatei, 8
.type _Z9cudaMontePdiP12hiprandState,@object # @_Z9cudaMontePdiP12hiprandState
.globl _Z9cudaMontePdiP12hiprandState
.p2align 3, 0x0
_Z9cudaMontePdiP12hiprandState:
.quad _Z24__device_stub__cudaMontePdiP12hiprandState
.size _Z9cudaMontePdiP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the number of iterations used to estimate pi: "
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "# of trials= %d , estimate of pi is %g \n"
.size .L.str.6, 41
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10init_stuffP12hiprandStatei"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9cudaMontePdiP12hiprandState"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error in copy from device to host."
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Error in copy from host to device."
.size .Lstr.1, 35
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error in memory allocation for random state."
.size .Lstr.2, 45
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error in memory allocation."
.size .Lstr.3, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__init_stuffP12hiprandStatei
.addrsig_sym _Z24__device_stub__cudaMontePdiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10init_stuffP12hiprandStatei
.addrsig_sym _Z9cudaMontePdiP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
__global__ void helloFromGPU(void){
if(threadIdx.x == 5){
printf("Hello World from GPU! thread: %d \n", threadIdx.x);
}
}
int main(void){
// Hello from CPU
printf("Hello World from CPU! \n");
// helloFromGPU<<<1, 10>>>();
helloFromGPU<<<1, 10>>>();
// cudaDeviceReset();
cudaDeviceSynchronize();
return 0;
}
|
code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f3e0ff */
/*0040*/ ISETP.NE.AND P0, PT, R0, 0x5, PT ; /* 0x000000050000780c */
/* 0x001fda0003f05270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R8, RZ, RZ, 0x5 ; /* 0x00000005ff087424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*00d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0130*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0140*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
__global__ void helloFromGPU(void){
if(threadIdx.x == 5){
printf("Hello World from GPU! thread: %d \n", threadIdx.x);
}
}
int main(void){
// Hello from CPU
printf("Hello World from CPU! \n");
// helloFromGPU<<<1, 10>>>();
helloFromGPU<<<1, 10>>>();
// cudaDeviceReset();
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_00157721_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU! \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
__global__ void helloFromGPU(void){
if(threadIdx.x == 5){
printf("Hello World from GPU! thread: %d \n", threadIdx.x);
}
}
int main(void){
// Hello from CPU
printf("Hello World from CPU! \n");
// helloFromGPU<<<1, 10>>>();
helloFromGPU<<<1, 10>>>();
// cudaDeviceReset();
cudaDeviceSynchronize();
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloFromGPU(void){
if(threadIdx.x == 5){
printf("Hello World from GPU! thread: %d \n", threadIdx.x);
}
}
int main(void){
// Hello from CPU
printf("Hello World from CPU! \n");
// helloFromGPU<<<1, 10>>>();
helloFromGPU<<<1, 10>>>();
// cudaDeviceReset();
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloFromGPU(void){
if(threadIdx.x == 5){
printf("Hello World from GPU! thread: %d \n", threadIdx.x);
}
}
int main(void){
// Hello from CPU
printf("Hello World from CPU! \n");
// helloFromGPU<<<1, 10>>>();
helloFromGPU<<<1, 10>>>();
// cudaDeviceReset();
hipDeviceSynchronize();
return 0;
}
|
.text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU! "
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00157721_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU! \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "hello.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU! "
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// http://cuda-programming.blogspot.com/2013/01/what-is-constant-memory-in-cuda.html
//STL
#include <iostream>
__constant__ float d_angle[ 360 ]; //constant memory LUT candidate
__global__ void test_kernel( float* d_array );
int main( int argc, char** argv )
{
unsigned size = 3200;
float* d_array;
float h_angle[ 360 ];
//allocate device memory
cudaMalloc( ( void** ) &d_array, size * sizeof( float ) );
//initialize allocated memory
cudaMemset( d_array, 0, sizeof( float ) * size );
//initialize angle array on host
for( unsigned loop=0; loop < 360; loop++ )
h_angle[ loop ] = acos( -1.0f ) * loop/ 180.0f;
//copy host angle data to constant memory
cudaMemcpyToSymbol( d_angle, h_angle, 360 * sizeof( float ) );
test_kernel<<< size / 64, 64>>>( d_array );
//constant variable view
float DtH_angle[ 360 ]; cudaMemcpyFromSymbol( DtH_angle, d_angle, 360 * sizeof( float ) );
for ( unsigned i = 0; i < 360; i++ )
{
printf( "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n",
i,
h_angle[ i ],
DtH_angle[ i ]
);
}
//free device memory
cudaFree( d_array );
cudaFree( d_angle );
return 0;
}
__global__ void test_kernel(float* d_array)
{
//calculate each thread global index
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
#pragma unroll 10
for( unsigned loop=0; loop < 360; loop++ )
d_array[ index ] = d_array[ index ] + d_angle[ loop ];
return;
}
|
code for sm_80
Function : _Z11test_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000162000c1e1900 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0090*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd00008000000 */
/*00a0*/ ULDC.64 UR6, c[0x3][UR4] ; /* 0x00c0000004067abb */
/* 0x000fe20008000a00 */
/*00b0*/ IADD3 R0, R0, 0xa, RZ ; /* 0x0000000a00007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x020fc60008000000 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, 0x168, PT ; /* 0x000001680000780c */
/* 0x000fe20003f05270 */
/*00e0*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*00f0*/ ULDC.64 UR6, c[0x3][UR4+0x8] ; /* 0x00c0020004067abb */
/* 0x000fc60008000a00 */
/*0100*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*0110*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*0120*/ ULDC.64 UR6, c[0x3][UR4+0x10] ; /* 0x00c0040004067abb */
/* 0x000fc60008000a00 */
/*0130*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*0140*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*0150*/ ULDC.64 UR6, c[0x3][UR4+0x18] ; /* 0x00c0060004067abb */
/* 0x000fc60008000a00 */
/*0160*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*0170*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*0180*/ ULDC.64 UR6, c[0x3][UR4+0x20] ; /* 0x00c0080004067abb */
/* 0x000fe40008000a00 */
/*0190*/ UIADD3 UR4, UR4, 0x28, URZ ; /* 0x0000002804047890 */
/* 0x000fe2000fffe03f */
/*01a0*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*01b0*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*01c0*/ @P0 BRA 0xa0 ; /* 0xfffffed000000947 */
/* 0x000fec000383ffff */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// http://cuda-programming.blogspot.com/2013/01/what-is-constant-memory-in-cuda.html
//STL
#include <iostream>
__constant__ float d_angle[ 360 ]; //constant memory LUT candidate
__global__ void test_kernel( float* d_array );
int main( int argc, char** argv )
{
unsigned size = 3200;
float* d_array;
float h_angle[ 360 ];
//allocate device memory
cudaMalloc( ( void** ) &d_array, size * sizeof( float ) );
//initialize allocated memory
cudaMemset( d_array, 0, sizeof( float ) * size );
//initialize angle array on host
for( unsigned loop=0; loop < 360; loop++ )
h_angle[ loop ] = acos( -1.0f ) * loop/ 180.0f;
//copy host angle data to constant memory
cudaMemcpyToSymbol( d_angle, h_angle, 360 * sizeof( float ) );
test_kernel<<< size / 64, 64>>>( d_array );
//constant variable view
float DtH_angle[ 360 ]; cudaMemcpyFromSymbol( DtH_angle, d_angle, 360 * sizeof( float ) );
for ( unsigned i = 0; i < 360; i++ )
{
printf( "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n",
i,
h_angle[ i ],
DtH_angle[ i ]
);
}
//free device memory
cudaFree( d_array );
cudaFree( d_angle );
return 0;
}
__global__ void test_kernel(float* d_array)
{
//calculate each thread global index
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
#pragma unroll 10
for( unsigned loop=0; loop < 360; loop++ )
d_array[ index ] = d_array[ index ] + d_angle[ loop ];
return;
}
|
.file "tmpxft_0002d027_00000000-6_cons.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11test_kernelPfPf
.type _Z31__device_stub__Z11test_kernelPfPf, @function
_Z31__device_stub__Z11test_kernelPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11test_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z11test_kernelPfPf, .-_Z31__device_stub__Z11test_kernelPfPf
.globl _Z11test_kernelPf
.type _Z11test_kernelPf, @function
_Z11test_kernelPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11test_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11test_kernelPf, .-_Z11test_kernelPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $2936, %rsp
.cfi_def_cfa_offset 2960
movq %fs:40, %rax
movq %rax, 2920(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $12800, %esi
call cudaMalloc@PLT
movl $12800, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $0, %eax
movss .LC0(%rip), %xmm2
movss .LC1(%rip), %xmm1
.L14:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
mulss %xmm2, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $360, %rax
jne .L14
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $1440, %edx
leaq _ZL7d_angle(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $50, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
leaq 1472(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $1440, %edx
leaq _ZL7d_angle(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 1472(%rsp,%rbx,4), %xmm1
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $360, %rbx
jne .L16
movq (%rsp), %rdi
call cudaFree@PLT
leaq _ZL7d_angle(%rip), %rdi
call cudaFree@PLT
movq 2920(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $2936, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq (%rsp), %rdi
call _Z31__device_stub__Z11test_kernelPfPf
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z11test_kernelPf"
.LC4:
.string "d_angle"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11test_kernelPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $1440, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_angle(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7d_angle
.comm _ZL7d_angle,1440,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1078530011
.align 4
.LC1:
.long 1127481344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// http://cuda-programming.blogspot.com/2013/01/what-is-constant-memory-in-cuda.html
//STL
#include <iostream>
__constant__ float d_angle[ 360 ]; //constant memory LUT candidate
__global__ void test_kernel( float* d_array );
int main( int argc, char** argv )
{
unsigned size = 3200;
float* d_array;
float h_angle[ 360 ];
//allocate device memory
cudaMalloc( ( void** ) &d_array, size * sizeof( float ) );
//initialize allocated memory
cudaMemset( d_array, 0, sizeof( float ) * size );
//initialize angle array on host
for( unsigned loop=0; loop < 360; loop++ )
h_angle[ loop ] = acos( -1.0f ) * loop/ 180.0f;
//copy host angle data to constant memory
cudaMemcpyToSymbol( d_angle, h_angle, 360 * sizeof( float ) );
test_kernel<<< size / 64, 64>>>( d_array );
//constant variable view
float DtH_angle[ 360 ]; cudaMemcpyFromSymbol( DtH_angle, d_angle, 360 * sizeof( float ) );
for ( unsigned i = 0; i < 360; i++ )
{
printf( "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n",
i,
h_angle[ i ],
DtH_angle[ i ]
);
}
//free device memory
cudaFree( d_array );
cudaFree( d_angle );
return 0;
}
__global__ void test_kernel(float* d_array)
{
//calculate each thread global index
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
#pragma unroll 10
for( unsigned loop=0; loop < 360; loop++ )
d_array[ index ] = d_array[ index ] + d_angle[ loop ];
return;
}
|
// http://cuda-programming.blogspot.com/2013/01/what-is-constant-memory-in-cuda.html
//STL
#include <hip/hip_runtime.h>
#include <iostream>
__constant__ float d_angle[ 360 ]; //constant memory LUT candidate
__global__ void test_kernel( float* d_array );
int main( int argc, char** argv )
{
unsigned size = 3200;
float* d_array;
float h_angle[ 360 ];
//allocate device memory
hipMalloc( ( void** ) &d_array, size * sizeof( float ) );
//initialize allocated memory
hipMemset( d_array, 0, sizeof( float ) * size );
//initialize angle array on host
for( unsigned loop=0; loop < 360; loop++ )
h_angle[ loop ] = acos( -1.0f ) * loop/ 180.0f;
//copy host angle data to constant memory
hipMemcpyToSymbol( HIP_SYMBOL(d_angle), h_angle, 360 * sizeof( float ) );
test_kernel<<< size / 64, 64>>>( d_array );
//constant variable view
float DtH_angle[ 360 ]; hipMemcpyFromSymbol( DtH_angle, HIP_SYMBOL(d_angle), 360 * sizeof( float ) );
for ( unsigned i = 0; i < 360; i++ )
{
printf( "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n",
i,
h_angle[ i ],
DtH_angle[ i ]
);
}
//free device memory
hipFree( d_array );
hipFree( d_angle );
return 0;
}
__global__ void test_kernel(float* d_array)
{
//calculate each thread global index
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
#pragma unroll 10
for( unsigned loop=0; loop < 360; loop++ )
d_array[ index ] = d_array[ index ] + d_angle[ loop ];
return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// http://cuda-programming.blogspot.com/2013/01/what-is-constant-memory-in-cuda.html
//STL
#include <hip/hip_runtime.h>
#include <iostream>
__constant__ float d_angle[ 360 ]; //constant memory LUT candidate
__global__ void test_kernel( float* d_array );
int main( int argc, char** argv )
{
unsigned size = 3200;
float* d_array;
float h_angle[ 360 ];
//allocate device memory
hipMalloc( ( void** ) &d_array, size * sizeof( float ) );
//initialize allocated memory
hipMemset( d_array, 0, sizeof( float ) * size );
//initialize angle array on host
for( unsigned loop=0; loop < 360; loop++ )
h_angle[ loop ] = acos( -1.0f ) * loop/ 180.0f;
//copy host angle data to constant memory
hipMemcpyToSymbol( HIP_SYMBOL(d_angle), h_angle, 360 * sizeof( float ) );
test_kernel<<< size / 64, 64>>>( d_array );
//constant variable view
float DtH_angle[ 360 ]; hipMemcpyFromSymbol( DtH_angle, HIP_SYMBOL(d_angle), 360 * sizeof( float ) );
for ( unsigned i = 0; i < 360; i++ )
{
printf( "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n",
i,
h_angle[ i ],
DtH_angle[ i ]
);
}
//free device memory
hipFree( d_array );
hipFree( d_angle );
return 0;
}
__global__ void test_kernel(float* d_array)
{
//calculate each thread global index
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
#pragma unroll 10
for( unsigned loop=0; loop < 360; loop++ )
d_array[ index ] = d_array[ index ] + d_angle[ loop ];
return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11test_kernelPf
.globl _Z11test_kernelPf
.p2align 8
.type _Z11test_kernelPf,@function
_Z11test_kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b64 s[0:1], 36
global_load_b32 v2, v[0:1], off
.LBB0_1:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_angle@rel32@lo+4
s_addc_u32 s3, s3, d_angle@rel32@hi+12
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_angle@rel32@lo-32
s_addc_u32 s5, s5, d_angle@rel32@hi-24
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-28
s_addc_u32 s7, s7, d_angle@rel32@hi-20
s_load_b32 s8, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-24
s_addc_u32 s7, s7, d_angle@rel32@hi-16
s_load_b32 s9, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-20
s_addc_u32 s7, s7, d_angle@rel32@hi-12
s_load_b32 s10, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-16
s_addc_u32 s7, s7, d_angle@rel32@hi-8
s_load_b32 s11, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-12
s_addc_u32 s7, s7, d_angle@rel32@hi-4
s_load_b32 s12, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-8
s_addc_u32 s7, s7, d_angle@rel32@hi
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, s8, v2
s_load_b32 s13, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_clause 0x1
s_load_b32 s6, s[4:5], 0x0
s_load_b32 s7, s[2:3], 0x0
v_add_f32_e32 v2, s9, v2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_angle@rel32@lo-4
s_addc_u32 s3, s3, d_angle@rel32@hi+4
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_angle@rel32@lo
s_addc_u32 s5, s5, d_angle@rel32@hi+8
v_add_f32_e32 v2, s10, v2
s_load_b32 s8, s[2:3], 0x0
s_add_u32 s2, s0, s4
s_addc_u32 s3, s1, s5
s_add_u32 s0, s0, 40
v_add_f32_e32 v2, s11, v2
s_load_b32 s2, s[2:3], 0x0
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x5c4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, s12, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, s13, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, s6, v2
v_add_f32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, s2, v2
v_add_f32_e32 v2, s7, v2
global_store_b32 v[0:1], v2, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11test_kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11test_kernelPf, .Lfunc_end0-_Z11test_kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_angle
.type d_angle,@object
.section .bss,"aw",@nobits
.globl d_angle
.p2align 4, 0x0
d_angle:
.zero 1440
.size d_angle, 1440
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_angle
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11test_kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11test_kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// http://cuda-programming.blogspot.com/2013/01/what-is-constant-memory-in-cuda.html
//STL
#include <hip/hip_runtime.h>
#include <iostream>
__constant__ float d_angle[ 360 ]; //constant memory LUT candidate
__global__ void test_kernel( float* d_array );
int main( int argc, char** argv )
{
unsigned size = 3200;
float* d_array;
float h_angle[ 360 ];
//allocate device memory
hipMalloc( ( void** ) &d_array, size * sizeof( float ) );
//initialize allocated memory
hipMemset( d_array, 0, sizeof( float ) * size );
//initialize angle array on host
for( unsigned loop=0; loop < 360; loop++ )
h_angle[ loop ] = acos( -1.0f ) * loop/ 180.0f;
//copy host angle data to constant memory
hipMemcpyToSymbol( HIP_SYMBOL(d_angle), h_angle, 360 * sizeof( float ) );
test_kernel<<< size / 64, 64>>>( d_array );
//constant variable view
float DtH_angle[ 360 ]; hipMemcpyFromSymbol( DtH_angle, HIP_SYMBOL(d_angle), 360 * sizeof( float ) );
for ( unsigned i = 0; i < 360; i++ )
{
printf( "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n",
i,
h_angle[ i ],
DtH_angle[ i ]
);
}
//free device memory
hipFree( d_array );
hipFree( d_angle );
return 0;
}
__global__ void test_kernel(float* d_array)
{
//calculate each thread global index
unsigned index = blockIdx.x * blockDim.x + threadIdx.x;
#pragma unroll 10
for( unsigned loop=0; loop < 360; loop++ )
d_array[ index ] = d_array[ index ] + d_angle[ loop ];
return;
}
|
.text
.file "cons.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI0_1:
.quad 0x4066800000000000 # double 180
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2944, %rsp # imm = 0xB80
.cfi_def_cfa_offset 2960
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $12800, %esi # imm = 0x3200
callq hipMalloc
movq 8(%rsp), %rdi
xorl %ebx, %ebx
movl $12800, %edx # imm = 0x3200
xorl %esi, %esi
callq hipMemset
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
xorps %xmm2, %xmm2
cvtsi2sd %rax, %xmm2
mulsd %xmm0, %xmm2
divsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 1504(%rsp,%rbx,4)
incq %rbx
cmpq $360, %rbx # imm = 0x168
jne .LBB0_1
# %bb.2:
leaq 1504(%rsp), %rsi
movl $d_angle, %edi
movl $1440, %edx # imm = 0x5A0
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967346, %rdi # imm = 0x100000032
leaq 14(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11test_kernelPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
xorl %ebx, %ebx
leaq 64(%rsp), %rdi
movl $d_angle, %esi
movl $1440, %edx # imm = 0x5A0
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss 1504(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 64(%rsp,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
incq %rbx
cmpq $360, %rbx # imm = 0x168
jne .LBB0_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movl $d_angle, %edi
callq hipFree
xorl %eax, %eax
addq $2944, %rsp # imm = 0xB80
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z26__device_stub__test_kernelPf # -- Begin function _Z26__device_stub__test_kernelPf
.p2align 4, 0x90
.type _Z26__device_stub__test_kernelPf,@function
_Z26__device_stub__test_kernelPf: # @_Z26__device_stub__test_kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11test_kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__test_kernelPf, .Lfunc_end1-_Z26__device_stub__test_kernelPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11test_kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_angle, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $1440, %r9d # imm = 0x5A0
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_angle,@object # @d_angle
.local d_angle
.comm d_angle,1440,16
.type _Z11test_kernelPf,@object # @_Z11test_kernelPf
.section .rodata,"a",@progbits
.globl _Z11test_kernelPf
.p2align 3, 0x0
_Z11test_kernelPf:
.quad _Z26__device_stub__test_kernelPf
.size _Z11test_kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ind=%02i]: h_angle: [ %.2f ]
.size .L.str, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11test_kernelPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_angle"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__test_kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_angle
.addrsig_sym _Z11test_kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11test_kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000162000c1e1900 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0090*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd00008000000 */
/*00a0*/ ULDC.64 UR6, c[0x3][UR4] ; /* 0x00c0000004067abb */
/* 0x000fe20008000a00 */
/*00b0*/ IADD3 R0, R0, 0xa, RZ ; /* 0x0000000a00007810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x020fc60008000000 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, 0x168, PT ; /* 0x000001680000780c */
/* 0x000fe20003f05270 */
/*00e0*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*00f0*/ ULDC.64 UR6, c[0x3][UR4+0x8] ; /* 0x00c0020004067abb */
/* 0x000fc60008000a00 */
/*0100*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*0110*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*0120*/ ULDC.64 UR6, c[0x3][UR4+0x10] ; /* 0x00c0040004067abb */
/* 0x000fc60008000a00 */
/*0130*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*0140*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*0150*/ ULDC.64 UR6, c[0x3][UR4+0x18] ; /* 0x00c0060004067abb */
/* 0x000fc60008000a00 */
/*0160*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*0170*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*0180*/ ULDC.64 UR6, c[0x3][UR4+0x20] ; /* 0x00c0080004067abb */
/* 0x000fe40008000a00 */
/*0190*/ UIADD3 UR4, UR4, 0x28, URZ ; /* 0x0000002804047890 */
/* 0x000fe2000fffe03f */
/*01a0*/ FADD R5, R5, UR6 ; /* 0x0000000605057e21 */
/* 0x000fc80008000000 */
/*01b0*/ FADD R5, R5, UR7 ; /* 0x0000000705057e21 */
/* 0x000fe20008000000 */
/*01c0*/ @P0 BRA 0xa0 ; /* 0xfffffed000000947 */
/* 0x000fec000383ffff */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101908 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11test_kernelPf
.globl _Z11test_kernelPf
.p2align 8
.type _Z11test_kernelPf,@function
_Z11test_kernelPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b64 s[0:1], 36
global_load_b32 v2, v[0:1], off
.LBB0_1:
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_angle@rel32@lo+4
s_addc_u32 s3, s3, d_angle@rel32@hi+12
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_angle@rel32@lo-32
s_addc_u32 s5, s5, d_angle@rel32@hi-24
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-28
s_addc_u32 s7, s7, d_angle@rel32@hi-20
s_load_b32 s8, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-24
s_addc_u32 s7, s7, d_angle@rel32@hi-16
s_load_b32 s9, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-20
s_addc_u32 s7, s7, d_angle@rel32@hi-12
s_load_b32 s10, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-16
s_addc_u32 s7, s7, d_angle@rel32@hi-8
s_load_b32 s11, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-12
s_addc_u32 s7, s7, d_angle@rel32@hi-4
s_load_b32 s12, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_angle@rel32@lo-8
s_addc_u32 s7, s7, d_angle@rel32@hi
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, s8, v2
s_load_b32 s13, s[4:5], 0x0
s_add_u32 s4, s0, s6
s_addc_u32 s5, s1, s7
s_clause 0x1
s_load_b32 s6, s[4:5], 0x0
s_load_b32 s7, s[2:3], 0x0
v_add_f32_e32 v2, s9, v2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, d_angle@rel32@lo-4
s_addc_u32 s3, s3, d_angle@rel32@hi+4
s_add_u32 s2, s0, s2
s_addc_u32 s3, s1, s3
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_angle@rel32@lo
s_addc_u32 s5, s5, d_angle@rel32@hi+8
v_add_f32_e32 v2, s10, v2
s_load_b32 s8, s[2:3], 0x0
s_add_u32 s2, s0, s4
s_addc_u32 s3, s1, s5
s_add_u32 s0, s0, 40
v_add_f32_e32 v2, s11, v2
s_load_b32 s2, s[2:3], 0x0
s_addc_u32 s1, s1, 0
s_cmpk_eq_i32 s0, 0x5c4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, s12, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, s13, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, s6, v2
v_add_f32_e32 v2, s8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, s2, v2
v_add_f32_e32 v2, s7, v2
global_store_b32 v[0:1], v2, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11test_kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11test_kernelPf, .Lfunc_end0-_Z11test_kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_angle
.type d_angle,@object
.section .bss,"aw",@nobits
.globl d_angle
.p2align 4, 0x0
d_angle:
.zero 1440
.size d_angle, 1440
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_angle
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11test_kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11test_kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0002d027_00000000-6_cons.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11test_kernelPfPf
.type _Z31__device_stub__Z11test_kernelPfPf, @function
_Z31__device_stub__Z11test_kernelPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11test_kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z11test_kernelPfPf, .-_Z31__device_stub__Z11test_kernelPfPf
.globl _Z11test_kernelPf
.type _Z11test_kernelPf, @function
_Z11test_kernelPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11test_kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z11test_kernelPf, .-_Z11test_kernelPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "[ind=%02i]: h_angle: [ %.2f ]; DtH_angle: [ %.2f ] \n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $2936, %rsp
.cfi_def_cfa_offset 2960
movq %fs:40, %rax
movq %rax, 2920(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $12800, %esi
call cudaMalloc@PLT
movl $12800, %edx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movl $0, %eax
movss .LC0(%rip), %xmm2
movss .LC1(%rip), %xmm1
.L14:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
mulss %xmm2, %xmm0
divss %xmm1, %xmm0
movss %xmm0, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $360, %rax
jne .L14
leaq 32(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $1440, %edx
leaq _ZL7d_angle(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $64, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $50, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
leaq 1472(%rsp), %rdi
movl $2, %r8d
movl $0, %ecx
movl $1440, %edx
leaq _ZL7d_angle(%rip), %rsi
call cudaMemcpyFromSymbol@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L16:
pxor %xmm0, %xmm0
cvtss2sd 32(%rsp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 1472(%rsp,%rbx,4), %xmm1
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $360, %rbx
jne .L16
movq (%rsp), %rdi
call cudaFree@PLT
leaq _ZL7d_angle(%rip), %rdi
call cudaFree@PLT
movq 2920(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $2936, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq (%rsp), %rdi
call _Z31__device_stub__Z11test_kernelPfPf
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z11test_kernelPf"
.LC4:
.string "d_angle"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11test_kernelPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $1440, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7d_angle(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7d_angle
.comm _ZL7d_angle,1440,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1078530011
.align 4
.LC1:
.long 1127481344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cons.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x400921fb54442d18 # double 3.1415926535897931
.LCPI0_1:
.quad 0x4066800000000000 # double 180
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2944, %rsp # imm = 0xB80
.cfi_def_cfa_offset 2960
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $12800, %esi # imm = 0x3200
callq hipMalloc
movq 8(%rsp), %rdi
xorl %ebx, %ebx
movl $12800, %edx # imm = 0x3200
xorl %esi, %esi
callq hipMemset
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
xorps %xmm2, %xmm2
cvtsi2sd %rax, %xmm2
mulsd %xmm0, %xmm2
divsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, 1504(%rsp,%rbx,4)
incq %rbx
cmpq $360, %rbx # imm = 0x168
jne .LBB0_1
# %bb.2:
leaq 1504(%rsp), %rsi
movl $d_angle, %edi
movl $1440, %edx # imm = 0x5A0
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967346, %rdi # imm = 0x100000032
leaq 14(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11test_kernelPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
xorl %ebx, %ebx
leaq 64(%rsp), %rdi
movl $d_angle, %esi
movl $1440, %edx # imm = 0x5A0
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss 1504(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 64(%rsp,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
incq %rbx
cmpq $360, %rbx # imm = 0x168
jne .LBB0_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movl $d_angle, %edi
callq hipFree
xorl %eax, %eax
addq $2944, %rsp # imm = 0xB80
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z26__device_stub__test_kernelPf # -- Begin function _Z26__device_stub__test_kernelPf
.p2align 4, 0x90
.type _Z26__device_stub__test_kernelPf,@function
_Z26__device_stub__test_kernelPf: # @_Z26__device_stub__test_kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11test_kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__test_kernelPf, .Lfunc_end1-_Z26__device_stub__test_kernelPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11test_kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_angle, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $1440, %r9d # imm = 0x5A0
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_angle,@object # @d_angle
.local d_angle
.comm d_angle,1440,16
.type _Z11test_kernelPf,@object # @_Z11test_kernelPf
.section .rodata,"a",@progbits
.globl _Z11test_kernelPf
.p2align 3, 0x0
_Z11test_kernelPf:
.quad _Z26__device_stub__test_kernelPf
.size _Z11test_kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ind=%02i]: h_angle: [ %.2f ]
.size .L.str, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11test_kernelPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_angle"
.size .L__unnamed_2, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__test_kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_angle
.addrsig_sym _Z11test_kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void totalWithThreadSyncAndSharedMemInterleaved(float *input, float *output, int len) {
//@@ Compute reduction for a segment of the input vector
__shared__ float sdata[BLOCK_SIZE];
int tid = threadIdx.x, i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < len)
sdata[tid] = input[i];
else
sdata[tid] = 0.0;
for(unsigned int j = 1; j < blockDim.x; j *= 2)
{
if (tid % (2 * j) == 0)
sdata[tid] += sdata[tid+j];
__syncthreads();
}
if(tid == 0)
{
output[blockIdx.x] = sdata[0];
}
}
|
code for sm_80
Function : _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26270 */
/*0060*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*0070*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fcc00078e0203 */
/*0080*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000402029981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe40000000f00 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ @P1 STS [R7.X4], RZ ; /* 0x000000ff07001388 */
/* 0x0001e20000004800 */
/*00c0*/ ISETP.GE.U32.AND P2, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fc60003f46070 */
/*00d0*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0041f40000004800 */
/*00e0*/ @!P2 BRA 0x2d0 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x000fd200078e00ff */
/*0110*/ IMAD.SHL.U32 R10, R5, 0x2, RZ ; /* 0x00000002050a7824 */
/* 0x000fc800078e00ff */
/*0120*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e620000209000 */
/*0130*/ IADD3 R9, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fca0003f45070 */
/*0150*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*0160*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x003fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fca00078e00ff */
/*01c0*/ IADD3 R8, -R3, RZ, RZ ; /* 0x000000ff03087210 */
/* 0x000fca0007ffe1ff */
/*01d0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fca00078e0a0a */
/*0200*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fe40007ffe1ff */
/*0220*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0230*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0240*/ @!P1 IMAD R2, R5, 0x4, R0 ; /* 0x0000000405029824 */
/* 0x000fe200078e0200 */
/*0250*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0260*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0270*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0280*/ @!P1 FADD R3, R3, R2 ; /* 0x0000000203039221 */
/* 0x001fca0000000000 */
/*0290*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02c0*/ @!P1 BRA 0x110 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e0003 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void totalWithThreadSyncAndSharedMemInterleaved(float *input, float *output, int len) {
//@@ Compute reduction for a segment of the input vector
__shared__ float sdata[BLOCK_SIZE];
int tid = threadIdx.x, i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < len)
sdata[tid] = input[i];
else
sdata[tid] = 0.0;
for(unsigned int j = 1; j < blockDim.x; j *= 2)
{
if (tid % (2 * j) == 0)
sdata[tid] += sdata[tid+j];
__syncthreads();
}
if(tid == 0)
{
output[blockIdx.x] = sdata[0];
}
}
|
.file "tmpxft_00147511_00000000-6_totalWithThreadSyncAndSharedMemInterleaved.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i
.type _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i, @function
_Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i, .-_Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i
.globl _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.type _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, @function
_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, .-_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void totalWithThreadSyncAndSharedMemInterleaved(float *input, float *output, int len) {
//@@ Compute reduction for a segment of the input vector
__shared__ float sdata[BLOCK_SIZE];
int tid = threadIdx.x, i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < len)
sdata[tid] = input[i];
else
sdata[tid] = 0.0;
for(unsigned int j = 1; j < blockDim.x; j *= 2)
{
if (tid % (2 * j) == 0)
sdata[tid] += sdata[tid+j];
__syncthreads();
}
if(tid == 0)
{
output[blockIdx.x] = sdata[0];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void totalWithThreadSyncAndSharedMemInterleaved(float *input, float *output, int len) {
//@@ Compute reduction for a segment of the input vector
__shared__ float sdata[BLOCK_SIZE];
int tid = threadIdx.x, i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < len)
sdata[tid] = input[i];
else
sdata[tid] = 0.0;
for(unsigned int j = 1; j < blockDim.x; j *= 2)
{
if (tid % (2 * j) == 0)
sdata[tid] += sdata[tid+j];
__syncthreads();
}
if(tid == 0)
{
output[blockIdx.x] = sdata[0];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void totalWithThreadSyncAndSharedMemInterleaved(float *input, float *output, int len) {
//@@ Compute reduction for a segment of the input vector
__shared__ float sdata[BLOCK_SIZE];
int tid = threadIdx.x, i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < len)
sdata[tid] = input[i];
else
sdata[tid] = 0.0;
for(unsigned int j = 1; j < blockDim.x; j *= 2)
{
if (tid % (2 * j) == 0)
sdata[tid] += sdata[tid+j];
__syncthreads();
}
if(tid == 0)
{
output[blockIdx.x] = sdata[0];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.globl _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.p2align 8
.type _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i,@function
_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, .Lfunc_end0-_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void totalWithThreadSyncAndSharedMemInterleaved(float *input, float *output, int len) {
//@@ Compute reduction for a segment of the input vector
__shared__ float sdata[BLOCK_SIZE];
int tid = threadIdx.x, i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < len)
sdata[tid] = input[i];
else
sdata[tid] = 0.0;
for(unsigned int j = 1; j < blockDim.x; j *= 2)
{
if (tid % (2 * j) == 0)
sdata[tid] += sdata[tid+j];
__syncthreads();
}
if(tid == 0)
{
output[blockIdx.x] = sdata[0];
}
}
|
.text
.file "totalWithThreadSyncAndSharedMemInterleaved.hip"
.globl _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i # -- Begin function _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.p2align 4, 0x90
.type _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i,@function
_Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i: # @_Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i, .Lfunc_end0-_Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i,@object # @_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.section .rodata,"a",@progbits
.globl _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.p2align 3, 0x0
_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i:
.quad _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.size _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26270 */
/*0060*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff039424 */
/* 0x000fc800078e00ff */
/*0070*/ @!P1 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002029625 */
/* 0x000fcc00078e0203 */
/*0080*/ @!P1 LDG.E R2, [R2.64] ; /* 0x0000000402029981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe40000000f00 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ @P1 STS [R7.X4], RZ ; /* 0x000000ff07001388 */
/* 0x0001e20000004800 */
/*00c0*/ ISETP.GE.U32.AND P2, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fc60003f46070 */
/*00d0*/ @!P1 STS [R7.X4], R2 ; /* 0x0000000207009388 */
/* 0x0041f40000004800 */
/*00e0*/ @!P2 BRA 0x2d0 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x000fd200078e00ff */
/*0110*/ IMAD.SHL.U32 R10, R5, 0x2, RZ ; /* 0x00000002050a7824 */
/* 0x000fc800078e00ff */
/*0120*/ I2F.U32.RP R4, R10 ; /* 0x0000000a00047306 */
/* 0x000e620000209000 */
/*0130*/ IADD3 R9, RZ, -R10, RZ ; /* 0x8000000aff097210 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fca0003f45070 */
/*0150*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e640000001000 */
/*0160*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x003fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x002fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*01b0*/ IMAD.HI.U32 R3, R3, R7, RZ ; /* 0x0000000703037227 */
/* 0x000fca00078e00ff */
/*01c0*/ IADD3 R8, -R3, RZ, RZ ; /* 0x000000ff03087210 */
/* 0x000fca0007ffe1ff */
/*01d0*/ IMAD R3, R10, R8, R7 ; /* 0x000000080a037224 */
/* 0x000fca00078e0207 */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IMAD.IADD R3, R3, 0x1, -R10 ; /* 0x0000000103031824 */
/* 0x000fca00078e0a0a */
/*0200*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R3, -R10, R3, RZ ; /* 0x000000030a031210 */
/* 0x000fe40007ffe1ff */
/*0220*/ @!P2 LOP3.LUT R3, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff03a212 */
/* 0x000fc800078e33ff */
/*0230*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0240*/ @!P1 IMAD R2, R5, 0x4, R0 ; /* 0x0000000405029824 */
/* 0x000fe200078e0200 */
/*0250*/ @!P1 LDS R3, [R7.X4] ; /* 0x0000000007039984 */
/* 0x000fe20000004800 */
/*0260*/ MOV R5, R10 ; /* 0x0000000a00057202 */
/* 0x000fc80000000f00 */
/*0270*/ @!P1 LDS R2, [R2] ; /* 0x0000000002029984 */
/* 0x000e240000000800 */
/*0280*/ @!P1 FADD R3, R3, R2 ; /* 0x0000000203039221 */
/* 0x001fca0000000000 */
/*0290*/ @!P1 STS [R7.X4], R3 ; /* 0x0000000307009388 */
/* 0x0001e80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R10, c[0x0][0x0], PT ; /* 0x000000000a007a0c */
/* 0x000fda0003f26070 */
/*02c0*/ @!P1 BRA 0x110 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*02d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e0003 */
/*0310*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.globl _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.p2align 8
.type _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i,@function
_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshlrev_b32_e32 v1, 2, v0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, 1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_ge_u32 s4, s3
s_mov_b32 s5, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshl_b32 s4, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_and_b32_e32 v2, s6, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, .Lfunc_end0-_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00147511_00000000-6_totalWithThreadSyncAndSharedMemInterleaved.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i
.type _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i, @function
_Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i, .-_Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i
.globl _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.type _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, @function
_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z65__device_stub__Z42totalWithThreadSyncAndSharedMemInterleavedPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, .-_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "totalWithThreadSyncAndSharedMemInterleaved.hip"
.globl _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i # -- Begin function _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.p2align 4, 0x90
.type _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i,@function
_Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i: # @_Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i, .Lfunc_end0-_Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i,@object # @_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.section .rodata,"a",@progbits
.globl _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.p2align 3, 0x0
_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i:
.quad _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.size _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z57__device_stub__totalWithThreadSyncAndSharedMemInterleavedPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z42totalWithThreadSyncAndSharedMemInterleavedPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <algorithm>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define BLOCK_SIZE 128
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
struct Tree {
int num_nodes;
Tree *left;
Tree *right;
float total_length;
float branch_length[2];
Tree(int _num_nodes, float _length, Tree *_left, Tree *_right, float length1,
float length2)
: num_nodes(_num_nodes), left(_left), right(_right),
total_length(_length) {
branch_length[0] = length1;
branch_length[1] = length2;
}
};
__global__ void getMin(float *input, int *input_idx, int n, float *output_val,
int *output_idx) {
__shared__ float smem_val[BLOCK_SIZE];
__shared__ int smem_idx[BLOCK_SIZE];
int tx = threadIdx.x;
int bx = blockIdx.x;
int i = tx + bx * BLOCK_SIZE * 8;
float min_val = INFINITY;
int min_idx = i;
if (i < n) {
float a1, a2, a3, a4, a5, a6, a7, a8;
a1 = input[i];
a1 = (a1 != 0.0f) ? a1 : INFINITY;
a2 = (i + BLOCK_SIZE) < n ? input[i + BLOCK_SIZE] : INFINITY;
a2 = (a2 != 0.0f) ? a2 : INFINITY;
a3 = (i + 2 * BLOCK_SIZE) < n ? input[i + 2 * BLOCK_SIZE] : INFINITY;
a3 = (a3 != 0.0f) ? a3 : INFINITY;
a4 = (i + 3 * BLOCK_SIZE) < n ? input[i + 3 * BLOCK_SIZE] : INFINITY;
a4 = (a4 != 0.0f) ? a4 : INFINITY;
a5 = (i + 4 * BLOCK_SIZE) < n ? input[i + 4 * BLOCK_SIZE] : INFINITY;
a5 = (a5 != 0.0f) ? a5 : INFINITY;
a6 = (i + 5 * BLOCK_SIZE) < n ? input[i + 5 * BLOCK_SIZE] : INFINITY;
a6 = (a6 != 0.0f) ? a6 : INFINITY;
a7 = (i + 6 * BLOCK_SIZE) < n ? input[i + 6 * BLOCK_SIZE] : INFINITY;
a7 = (a7 != 0.0f) ? a7 : INFINITY;
a8 = (i + 7 * BLOCK_SIZE) < n ? input[i + 7 * BLOCK_SIZE] : INFINITY;
a8 = (a8 != 0.0f) ? a8 : INFINITY;
min_val = a1;
min_idx = i;
if (a2 < min_val) {
min_val = a2;
min_idx = i + BLOCK_SIZE;
}
if (a3 < min_val) {
min_val = a3;
min_idx = i + 2 * BLOCK_SIZE;
}
if (a4 < min_val) {
min_val = a4;
min_idx = i + 3 * BLOCK_SIZE;
}
if (a5 < min_val) {
min_val = a5;
min_idx = i + 4 * BLOCK_SIZE;
}
if (a6 < min_val) {
min_val = a6;
min_idx = i + 5 * BLOCK_SIZE;
}
if (a7 < min_val) {
min_val = a7;
min_idx = i + 6 * BLOCK_SIZE;
}
if (a8 < min_val) {
min_val = a8;
min_idx = i + 7 * BLOCK_SIZE;
}
}
smem_val[tx] = min_val;
smem_idx[tx] = min_idx;
__syncthreads();
// in-place reduction in shared memory
if (blockDim.x >= 1024 && tx < 512 && smem_val[tx + 512] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 512];
smem_idx[tx] = min_idx = smem_idx[tx + 512];
}
__syncthreads();
if (blockDim.x >= 512 && tx < 256 && smem_val[tx + 256] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 256];
smem_idx[tx] = min_idx = smem_idx[tx + 256];
}
__syncthreads();
if (blockDim.x >= 256 && tx < 128 && smem_val[tx + 128] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 128];
smem_idx[tx] = min_idx = smem_idx[tx + 128];
}
__syncthreads();
if (blockDim.x >= 128 && tx < 64 && smem_val[tx + 64] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 64];
smem_idx[tx] = min_idx = smem_idx[tx + 64];
}
__syncthreads();
// unrolling warp
if (tx < 32) {
volatile float *vsmem_val = smem_val;
volatile int *vsmem_idx = smem_idx;
if (vsmem_val[tx + 32] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 32];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 32];
}
if (vsmem_val[tx + 16] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 16];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 16];
}
if (vsmem_val[tx + 8] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 8];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 8];
}
if (vsmem_val[tx + 4] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 4];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 4];
}
if (vsmem_val[tx + 2] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 2];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 2];
}
if (vsmem_val[tx + 1] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 1];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 1];
}
}
if (tx == 0) {
output_val[bx] = min_val;
output_idx[bx] = (input_idx == nullptr) ? min_idx : input_idx[min_idx];
}
}
/*
void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int total_nodes = num_nodes1 + num_nodes2;
for (int i = 0; i < n; ++i) {
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
mat[n * idx1 + idx1] = 0.0f;
mat[n * idx2 + idx1] = 0.0f;
mat[n * idx1 + idx2] = 0.0f;
mat[n * idx2 + idx2] = 0.0f;
}*/
__global__ void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int tx = threadIdx.x;
int i = tx + blockDim.x * blockIdx.x;
if (i >= n || i == idx1) {
return;
} else if (i == idx2) {
mat[n * idx1 + i] = 0.0f;
mat[n * i + idx1] = 0.0f;
return;
}
int total_nodes = num_nodes1 + num_nodes2;
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
void cleanupTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
delete tree;
return;
}
cleanupTree(tree->left);
cleanupTree(tree->right);
}
void printTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
return;
}
cout << "(";
printTree(tree->left);
cout << ": " << tree->branch_length[0] << ", ";
printTree(tree->right);
cout << ": " << tree->branch_length[1] << ")";
}
int main() {
const int num_seqs = 7;
float h_a[num_seqs][num_seqs]{
{0.0f, 19.0f, 27.0f, 8.0f, 33.0f, 18.0f, 13.0f},
{19.0f, 0.0f, 31.0f, 18.0f, 36.0f, 1.0f, 13.0f},
{27.0f, 31.0f, 0.0f, 26.0f, 41.0f, 32.0f, 29.0f},
{8.0f, 18.0f, 26.0f, 0.0f, 31.0f, 17.0f, 14.0f},
{33.0f, 36.0f, 41.0f, 31.0f, 0.0f, 35.0f, 28.0f},
{18.0f, 1.0f, 32.0f, 17.0f, 35.0f, 0.0f, 12.0f},
{13.0f, 13.0f, 29.0f, 14.0f, 28.0f, 12.0f, 0.0f}};
Tree *nodes[num_seqs];
for (int i = 0; i < num_seqs; ++i) {
nodes[i] = new Tree(1, 0.0f, nullptr, nullptr, 0.0f, 0.0f);
}
int n = num_seqs * num_seqs;
int n_out_level0 = ceil((float)n / (BLOCK_SIZE * 8));
int n_out_level1 = ceil((float)n_out_level0 / (BLOCK_SIZE * 8));
float *h_val = (float *)malloc(sizeof(float) * n_out_level1);
int *h_idx = (int *)malloc(sizeof(int) * n_out_level1);
float *d_a;
float *d_val_level0, *d_val_level1;
int *d_idx_level0, *d_idx_level1;
CHECK(cudaMalloc((void **)&d_a, sizeof(float) * n));
CHECK(cudaMalloc((void **)&d_val_level0, sizeof(float) * n_out_level0));
CHECK(cudaMalloc((void **)&d_idx_level0, sizeof(int) * n_out_level0));
CHECK(cudaMalloc((void **)&d_val_level1, sizeof(float) * n_out_level1));
CHECK(cudaMalloc((void **)&d_idx_level1, sizeof(int) * n_out_level1));
CHECK(cudaMemcpy(d_a, h_a, sizeof(float) * n, cudaMemcpyHostToDevice));
Tree *root;
for (int remain = num_seqs; remain >= 2; --remain) {
// int idx = getMinIdx((float *)a, num_seqs * num_seqs);
getMin<<<n_out_level0, BLOCK_SIZE>>>(d_a, nullptr, n, d_val_level0,
d_idx_level0);
CHECK(cudaDeviceSynchronize());
getMin<<<n_out_level1, BLOCK_SIZE>>>(
d_val_level0, d_idx_level0, n_out_level0, d_val_level1, d_idx_level1);
CHECK(cudaDeviceSynchronize());
CHECK(cudaMemcpy(h_val, d_val_level1, sizeof(float) * n_out_level1,
cudaMemcpyDeviceToHost));
CHECK(cudaMemcpy(h_idx, d_idx_level1, sizeof(int) * n_out_level1,
cudaMemcpyDeviceToHost));
float val = h_val[0];
int idx = h_idx[0];
for (int i = 0; i < n_out_level1; ++i) {
if (h_val[i] < val) {
val = h_val[i];
idx = h_idx[i];
}
}
int idx1 = idx / num_seqs;
int idx2 = idx % num_seqs;
if (idx1 > idx2) {
swap(idx1, idx2);
}
update<<<num_seqs, BLOCK_SIZE>>>(d_a, num_seqs, idx1, idx2,
nodes[idx1]->num_nodes,
nodes[idx2]->num_nodes);
float length = val;
root = new Tree(nodes[idx1]->num_nodes + nodes[idx2]->num_nodes, length / 2,
nodes[idx1], nodes[idx2],
length / 2 - nodes[idx1]->total_length,
length / 2 - nodes[idx2]->total_length);
CHECK(cudaDeviceSynchronize());
nodes[idx1] = root;
}
printTree(root);
// Free device
CHECK(cudaFree(d_a));
CHECK(cudaFree(d_val_level0));
CHECK(cudaFree(d_idx_level0));
CHECK(cudaFree(d_val_level1));
CHECK(cudaFree(d_idx_level1));
// Free host
free(h_val);
free(h_idx);
// Clean up tree
cleanupTree(root);
return 0;
}
|
.file "tmpxft_0014b809_00000000-6_upgma.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3932:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3932:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cleanupTreeP4Tree
.type _Z11cleanupTreeP4Tree, @function
_Z11cleanupTreeP4Tree:
.LFB3926:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
testq %rdi, %rdi
je .L7
.L4:
call _Z11cleanupTreeP4Tree
movq 16(%rbx), %rdi
call _Z11cleanupTreeP4Tree
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
cmpq $0, 16(%rbx)
jne .L4
movl $40, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
jmp .L3
.cfi_endproc
.LFE3926:
.size _Z11cleanupTreeP4Tree, .-_Z11cleanupTreeP4Tree
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "("
.LC1:
.string ": "
.LC2:
.string ", "
.LC3:
.string ")"
.text
.globl _Z9printTreeP4Tree
.type _Z9printTreeP4Tree, @function
_Z9printTreeP4Tree:
.LFB3927:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
cmpq $0, 8(%rdi)
je .L12
.L9:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rbx), %rdi
call _Z9printTreeP4Tree
movl $2, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rbx), %rdi
call _Z9printTreeP4Tree
movl $2, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L8:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
cmpq $0, 16(%rdi)
jne .L9
jmp .L8
.cfi_endproc
.LFE3927:
.size _Z9printTreeP4Tree, .-_Z9printTreeP4Tree
.globl _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
.type _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_, @function
_Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_:
.LFB3954:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6getMinPfPiiS_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3954:
.size _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_, .-_Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
.globl _Z6getMinPfPiiS_S0_
.type _Z6getMinPfPiiS_S0_, @function
_Z6getMinPfPiiS_S0_:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _Z6getMinPfPiiS_S0_, .-_Z6getMinPfPiiS_S0_
.globl _Z30__device_stub__Z6updatePfiiiiiPfiiiii
.type _Z30__device_stub__Z6updatePfiiiiiPfiiiii, @function
_Z30__device_stub__Z6updatePfiiiiiPfiiiii:
.LFB3956:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePfiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3956:
.size _Z30__device_stub__Z6updatePfiiiiiPfiiiii, .-_Z30__device_stub__Z6updatePfiiiiiPfiiiii
.globl _Z6updatePfiiiii
.type _Z6updatePfiiiii, @function
_Z6updatePfiiiii:
.LFB3957:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6updatePfiiiiiPfiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3957:
.size _Z6updatePfiiiii, .-_Z6updatePfiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC23:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hle46/UPGMA/master/gpu/upgma.cu"
.section .rodata.str1.1
.LC24:
.string "Error: %s:%d, "
.LC25:
.string "code: %d, reason: %s\n"
.text
.globl main
.type main, @function
main:
.LFB3928:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $360, %rsp
.cfi_def_cfa_offset 416
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
movl $0x00000000, 144(%rsp)
movss .LC5(%rip), %xmm2
movss %xmm2, 148(%rsp)
movss .LC6(%rip), %xmm3
movss %xmm3, 152(%rsp)
movss .LC7(%rip), %xmm6
movss %xmm6, 156(%rsp)
movss .LC8(%rip), %xmm10
movss %xmm10, 160(%rsp)
movss .LC9(%rip), %xmm1
movss %xmm1, 164(%rsp)
movss .LC10(%rip), %xmm0
movss %xmm0, 168(%rsp)
movss %xmm2, 172(%rsp)
movl $0x00000000, 176(%rsp)
movss .LC11(%rip), %xmm2
movss %xmm2, 180(%rsp)
movss %xmm1, 184(%rsp)
movss .LC12(%rip), %xmm9
movss %xmm9, 188(%rsp)
movss .LC13(%rip), %xmm8
movss %xmm8, 192(%rsp)
movss %xmm0, 196(%rsp)
movss %xmm3, 200(%rsp)
movss %xmm2, 204(%rsp)
movl $0x00000000, 208(%rsp)
movss .LC14(%rip), %xmm3
movss %xmm3, 212(%rsp)
movss .LC15(%rip), %xmm5
movss %xmm5, 216(%rsp)
movss .LC16(%rip), %xmm7
movss %xmm7, 220(%rsp)
movss .LC17(%rip), %xmm4
movss %xmm4, 224(%rsp)
movss %xmm6, 228(%rsp)
movss %xmm1, 232(%rsp)
movss %xmm3, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm2, 244(%rsp)
movss .LC18(%rip), %xmm6
movss %xmm6, 248(%rsp)
movss .LC19(%rip), %xmm3
movss %xmm3, 252(%rsp)
movss %xmm10, 256(%rsp)
movss %xmm9, 260(%rsp)
movss %xmm5, 264(%rsp)
movss %xmm2, 268(%rsp)
movl $0x00000000, 272(%rsp)
movss .LC20(%rip), %xmm5
movss %xmm5, 276(%rsp)
movss .LC21(%rip), %xmm2
movss %xmm2, 280(%rsp)
movss %xmm1, 284(%rsp)
movss %xmm8, 288(%rsp)
movss %xmm7, 292(%rsp)
movss %xmm6, 296(%rsp)
movss %xmm5, 300(%rsp)
movl $0x00000000, 304(%rsp)
movss .LC22(%rip), %xmm1
movss %xmm1, 308(%rsp)
movss %xmm0, 312(%rsp)
movss %xmm0, 316(%rsp)
movss %xmm4, 320(%rsp)
movss %xmm3, 324(%rsp)
movss %xmm2, 328(%rsp)
movss %xmm1, 332(%rsp)
movl $0x00000000, 336(%rsp)
leaq 80(%rsp), %rbx
leaq 136(%rsp), %rbp
.L30:
movl $40, %edi
call _Znwm@PLT
movl $1, (%rax)
movq $0, 8(%rax)
movq $0, 16(%rax)
movl $0x00000000, 24(%rax)
movl $0x00000000, 28(%rax)
movl $0x00000000, 32(%rax)
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L30
movl $4, %edi
call malloc@PLT
movq %rax, %r15
movl $4, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $196, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L57
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L58
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L59
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L60
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $196, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
movl $6, %r13d
jmp .L36
.L56:
movl $259, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl $260, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl $261, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl $262, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl $263, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $265, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
movq 40(%rsp), %r8
movq 24(%rsp), %rcx
movl $49, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
jmp .L37
.L66:
movl $273, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
movq 48(%rsp), %r8
movq 32(%rsp), %rcx
movl $1, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
jmp .L39
.L68:
movl $278, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
movl $280, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
movl $282, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $7, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L44:
movl $40, %edi
call _Znwm@PLT
movq %rax, %r12
movss 12(%rsp), %xmm0
mulss .LC26(%rip), %xmm0
movslq %ebx, %rbx
movq 80(%rsp,%rbx,8), %rax
movaps %xmm0, %xmm1
subss 24(%rax), %xmm1
movslq %ebp, %rdx
movq 80(%rsp,%rdx,8), %rdx
movaps %xmm0, %xmm2
subss 24(%rdx), %xmm2
movl (%rax), %ecx
addl (%rdx), %ecx
movl %ecx, (%r12)
movq %rdx, 8(%r12)
movq %rax, 16(%r12)
movss %xmm0, 24(%r12)
movss %xmm2, 28(%r12)
movss %xmm1, 32(%r12)
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
movslq %ebp, %rbp
movq %r12, 80(%rsp,%rbp,8)
subl $1, %r13d
je .L64
.L36:
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L37:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L66
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L39:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L68
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L69
movl $2, %ecx
movl $4, %edx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L70
movss (%r15), %xmm4
movss %xmm4, 12(%rsp)
movl (%r14), %ebp
movslq %ebp, %rbx
imulq $-1840700269, %rbx, %rbx
shrq $32, %rbx
addl %ebp, %ebx
sarl $2, %ebx
movl %ebp, %eax
sarl $31, %eax
subl %eax, %ebx
leal 0(,%rbx,8), %eax
subl %ebx, %eax
subl %eax, %ebp
cmpl %ebp, %ebx
jg .L43
movl %ebp, %eax
movl %ebx, %ebp
movl %eax, %ebx
jmp .L43
.L62:
movslq %ebx, %rax
movq 80(%rsp,%rax,8), %rdx
movslq %ebp, %rax
movq 80(%rsp,%rax,8), %rax
movl (%rdx), %r9d
movl (%rax), %r8d
movl %ebx, %ecx
movl %ebp, %edx
movl $7, %esi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z6updatePfiiiiiPfiiiii
jmp .L44
.L63:
movl $308, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movq %r12, %rdi
call _Z9printTreeP4Tree
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L71
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L72
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L73
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L74
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L75
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call _Z11cleanupTreeP4Tree
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L76
movl $0, %eax
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movl $315, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
movl $316, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl $317, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
movl $318, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl $319, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3928:
.size main, .-main
.section .rodata.str1.1
.LC27:
.string "_Z6updatePfiiiii"
.LC28:
.string "_Z6getMinPfPiiS_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3959:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z6getMinPfPiiS_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3959:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1100480512
.align 4
.LC6:
.long 1104674816
.align 4
.LC7:
.long 1090519040
.align 4
.LC8:
.long 1107558400
.align 4
.LC9:
.long 1099956224
.align 4
.LC10:
.long 1095761920
.align 4
.LC11:
.long 1106771968
.align 4
.LC12:
.long 1108344832
.align 4
.LC13:
.long 1065353216
.align 4
.LC14:
.long 1104150528
.align 4
.LC15:
.long 1109655552
.align 4
.LC16:
.long 1107296256
.align 4
.LC17:
.long 1105723392
.align 4
.LC18:
.long 1099431936
.align 4
.LC19:
.long 1096810496
.align 4
.LC20:
.long 1108082688
.align 4
.LC21:
.long 1105199104
.align 4
.LC22:
.long 1094713344
.align 4
.LC26:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <algorithm>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define BLOCK_SIZE 128
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
struct Tree {
int num_nodes;
Tree *left;
Tree *right;
float total_length;
float branch_length[2];
Tree(int _num_nodes, float _length, Tree *_left, Tree *_right, float length1,
float length2)
: num_nodes(_num_nodes), left(_left), right(_right),
total_length(_length) {
branch_length[0] = length1;
branch_length[1] = length2;
}
};
__global__ void getMin(float *input, int *input_idx, int n, float *output_val,
int *output_idx) {
__shared__ float smem_val[BLOCK_SIZE];
__shared__ int smem_idx[BLOCK_SIZE];
int tx = threadIdx.x;
int bx = blockIdx.x;
int i = tx + bx * BLOCK_SIZE * 8;
float min_val = INFINITY;
int min_idx = i;
if (i < n) {
float a1, a2, a3, a4, a5, a6, a7, a8;
a1 = input[i];
a1 = (a1 != 0.0f) ? a1 : INFINITY;
a2 = (i + BLOCK_SIZE) < n ? input[i + BLOCK_SIZE] : INFINITY;
a2 = (a2 != 0.0f) ? a2 : INFINITY;
a3 = (i + 2 * BLOCK_SIZE) < n ? input[i + 2 * BLOCK_SIZE] : INFINITY;
a3 = (a3 != 0.0f) ? a3 : INFINITY;
a4 = (i + 3 * BLOCK_SIZE) < n ? input[i + 3 * BLOCK_SIZE] : INFINITY;
a4 = (a4 != 0.0f) ? a4 : INFINITY;
a5 = (i + 4 * BLOCK_SIZE) < n ? input[i + 4 * BLOCK_SIZE] : INFINITY;
a5 = (a5 != 0.0f) ? a5 : INFINITY;
a6 = (i + 5 * BLOCK_SIZE) < n ? input[i + 5 * BLOCK_SIZE] : INFINITY;
a6 = (a6 != 0.0f) ? a6 : INFINITY;
a7 = (i + 6 * BLOCK_SIZE) < n ? input[i + 6 * BLOCK_SIZE] : INFINITY;
a7 = (a7 != 0.0f) ? a7 : INFINITY;
a8 = (i + 7 * BLOCK_SIZE) < n ? input[i + 7 * BLOCK_SIZE] : INFINITY;
a8 = (a8 != 0.0f) ? a8 : INFINITY;
min_val = a1;
min_idx = i;
if (a2 < min_val) {
min_val = a2;
min_idx = i + BLOCK_SIZE;
}
if (a3 < min_val) {
min_val = a3;
min_idx = i + 2 * BLOCK_SIZE;
}
if (a4 < min_val) {
min_val = a4;
min_idx = i + 3 * BLOCK_SIZE;
}
if (a5 < min_val) {
min_val = a5;
min_idx = i + 4 * BLOCK_SIZE;
}
if (a6 < min_val) {
min_val = a6;
min_idx = i + 5 * BLOCK_SIZE;
}
if (a7 < min_val) {
min_val = a7;
min_idx = i + 6 * BLOCK_SIZE;
}
if (a8 < min_val) {
min_val = a8;
min_idx = i + 7 * BLOCK_SIZE;
}
}
smem_val[tx] = min_val;
smem_idx[tx] = min_idx;
__syncthreads();
// in-place reduction in shared memory
if (blockDim.x >= 1024 && tx < 512 && smem_val[tx + 512] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 512];
smem_idx[tx] = min_idx = smem_idx[tx + 512];
}
__syncthreads();
if (blockDim.x >= 512 && tx < 256 && smem_val[tx + 256] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 256];
smem_idx[tx] = min_idx = smem_idx[tx + 256];
}
__syncthreads();
if (blockDim.x >= 256 && tx < 128 && smem_val[tx + 128] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 128];
smem_idx[tx] = min_idx = smem_idx[tx + 128];
}
__syncthreads();
if (blockDim.x >= 128 && tx < 64 && smem_val[tx + 64] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 64];
smem_idx[tx] = min_idx = smem_idx[tx + 64];
}
__syncthreads();
// unrolling warp
if (tx < 32) {
volatile float *vsmem_val = smem_val;
volatile int *vsmem_idx = smem_idx;
if (vsmem_val[tx + 32] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 32];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 32];
}
if (vsmem_val[tx + 16] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 16];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 16];
}
if (vsmem_val[tx + 8] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 8];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 8];
}
if (vsmem_val[tx + 4] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 4];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 4];
}
if (vsmem_val[tx + 2] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 2];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 2];
}
if (vsmem_val[tx + 1] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 1];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 1];
}
}
if (tx == 0) {
output_val[bx] = min_val;
output_idx[bx] = (input_idx == nullptr) ? min_idx : input_idx[min_idx];
}
}
/*
void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int total_nodes = num_nodes1 + num_nodes2;
for (int i = 0; i < n; ++i) {
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
mat[n * idx1 + idx1] = 0.0f;
mat[n * idx2 + idx1] = 0.0f;
mat[n * idx1 + idx2] = 0.0f;
mat[n * idx2 + idx2] = 0.0f;
}*/
__global__ void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int tx = threadIdx.x;
int i = tx + blockDim.x * blockIdx.x;
if (i >= n || i == idx1) {
return;
} else if (i == idx2) {
mat[n * idx1 + i] = 0.0f;
mat[n * i + idx1] = 0.0f;
return;
}
int total_nodes = num_nodes1 + num_nodes2;
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
void cleanupTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
delete tree;
return;
}
cleanupTree(tree->left);
cleanupTree(tree->right);
}
void printTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
return;
}
cout << "(";
printTree(tree->left);
cout << ": " << tree->branch_length[0] << ", ";
printTree(tree->right);
cout << ": " << tree->branch_length[1] << ")";
}
int main() {
const int num_seqs = 7;
float h_a[num_seqs][num_seqs]{
{0.0f, 19.0f, 27.0f, 8.0f, 33.0f, 18.0f, 13.0f},
{19.0f, 0.0f, 31.0f, 18.0f, 36.0f, 1.0f, 13.0f},
{27.0f, 31.0f, 0.0f, 26.0f, 41.0f, 32.0f, 29.0f},
{8.0f, 18.0f, 26.0f, 0.0f, 31.0f, 17.0f, 14.0f},
{33.0f, 36.0f, 41.0f, 31.0f, 0.0f, 35.0f, 28.0f},
{18.0f, 1.0f, 32.0f, 17.0f, 35.0f, 0.0f, 12.0f},
{13.0f, 13.0f, 29.0f, 14.0f, 28.0f, 12.0f, 0.0f}};
Tree *nodes[num_seqs];
for (int i = 0; i < num_seqs; ++i) {
nodes[i] = new Tree(1, 0.0f, nullptr, nullptr, 0.0f, 0.0f);
}
int n = num_seqs * num_seqs;
int n_out_level0 = ceil((float)n / (BLOCK_SIZE * 8));
int n_out_level1 = ceil((float)n_out_level0 / (BLOCK_SIZE * 8));
float *h_val = (float *)malloc(sizeof(float) * n_out_level1);
int *h_idx = (int *)malloc(sizeof(int) * n_out_level1);
float *d_a;
float *d_val_level0, *d_val_level1;
int *d_idx_level0, *d_idx_level1;
CHECK(cudaMalloc((void **)&d_a, sizeof(float) * n));
CHECK(cudaMalloc((void **)&d_val_level0, sizeof(float) * n_out_level0));
CHECK(cudaMalloc((void **)&d_idx_level0, sizeof(int) * n_out_level0));
CHECK(cudaMalloc((void **)&d_val_level1, sizeof(float) * n_out_level1));
CHECK(cudaMalloc((void **)&d_idx_level1, sizeof(int) * n_out_level1));
CHECK(cudaMemcpy(d_a, h_a, sizeof(float) * n, cudaMemcpyHostToDevice));
Tree *root;
for (int remain = num_seqs; remain >= 2; --remain) {
// int idx = getMinIdx((float *)a, num_seqs * num_seqs);
getMin<<<n_out_level0, BLOCK_SIZE>>>(d_a, nullptr, n, d_val_level0,
d_idx_level0);
CHECK(cudaDeviceSynchronize());
getMin<<<n_out_level1, BLOCK_SIZE>>>(
d_val_level0, d_idx_level0, n_out_level0, d_val_level1, d_idx_level1);
CHECK(cudaDeviceSynchronize());
CHECK(cudaMemcpy(h_val, d_val_level1, sizeof(float) * n_out_level1,
cudaMemcpyDeviceToHost));
CHECK(cudaMemcpy(h_idx, d_idx_level1, sizeof(int) * n_out_level1,
cudaMemcpyDeviceToHost));
float val = h_val[0];
int idx = h_idx[0];
for (int i = 0; i < n_out_level1; ++i) {
if (h_val[i] < val) {
val = h_val[i];
idx = h_idx[i];
}
}
int idx1 = idx / num_seqs;
int idx2 = idx % num_seqs;
if (idx1 > idx2) {
swap(idx1, idx2);
}
update<<<num_seqs, BLOCK_SIZE>>>(d_a, num_seqs, idx1, idx2,
nodes[idx1]->num_nodes,
nodes[idx2]->num_nodes);
float length = val;
root = new Tree(nodes[idx1]->num_nodes + nodes[idx2]->num_nodes, length / 2,
nodes[idx1], nodes[idx2],
length / 2 - nodes[idx1]->total_length,
length / 2 - nodes[idx2]->total_length);
CHECK(cudaDeviceSynchronize());
nodes[idx1] = root;
}
printTree(root);
// Free device
CHECK(cudaFree(d_a));
CHECK(cudaFree(d_val_level0));
CHECK(cudaFree(d_idx_level0));
CHECK(cudaFree(d_val_level1));
CHECK(cudaFree(d_idx_level1));
// Free host
free(h_val);
free(h_idx);
// Clean up tree
cleanupTree(root);
return 0;
}
|
#include <iostream>
#include <algorithm>
#include <hip/hip_runtime.h>
using namespace std;
#define BLOCK_SIZE 128
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
struct Tree {
int num_nodes;
Tree *left;
Tree *right;
float total_length;
float branch_length[2];
Tree(int _num_nodes, float _length, Tree *_left, Tree *_right, float length1,
float length2)
: num_nodes(_num_nodes), left(_left), right(_right),
total_length(_length) {
branch_length[0] = length1;
branch_length[1] = length2;
}
};
__global__ void getMin(float *input, int *input_idx, int n, float *output_val,
int *output_idx) {
__shared__ float smem_val[BLOCK_SIZE];
__shared__ int smem_idx[BLOCK_SIZE];
int tx = threadIdx.x;
int bx = blockIdx.x;
int i = tx + bx * BLOCK_SIZE * 8;
float min_val = INFINITY;
int min_idx = i;
if (i < n) {
float a1, a2, a3, a4, a5, a6, a7, a8;
a1 = input[i];
a1 = (a1 != 0.0f) ? a1 : INFINITY;
a2 = (i + BLOCK_SIZE) < n ? input[i + BLOCK_SIZE] : INFINITY;
a2 = (a2 != 0.0f) ? a2 : INFINITY;
a3 = (i + 2 * BLOCK_SIZE) < n ? input[i + 2 * BLOCK_SIZE] : INFINITY;
a3 = (a3 != 0.0f) ? a3 : INFINITY;
a4 = (i + 3 * BLOCK_SIZE) < n ? input[i + 3 * BLOCK_SIZE] : INFINITY;
a4 = (a4 != 0.0f) ? a4 : INFINITY;
a5 = (i + 4 * BLOCK_SIZE) < n ? input[i + 4 * BLOCK_SIZE] : INFINITY;
a5 = (a5 != 0.0f) ? a5 : INFINITY;
a6 = (i + 5 * BLOCK_SIZE) < n ? input[i + 5 * BLOCK_SIZE] : INFINITY;
a6 = (a6 != 0.0f) ? a6 : INFINITY;
a7 = (i + 6 * BLOCK_SIZE) < n ? input[i + 6 * BLOCK_SIZE] : INFINITY;
a7 = (a7 != 0.0f) ? a7 : INFINITY;
a8 = (i + 7 * BLOCK_SIZE) < n ? input[i + 7 * BLOCK_SIZE] : INFINITY;
a8 = (a8 != 0.0f) ? a8 : INFINITY;
min_val = a1;
min_idx = i;
if (a2 < min_val) {
min_val = a2;
min_idx = i + BLOCK_SIZE;
}
if (a3 < min_val) {
min_val = a3;
min_idx = i + 2 * BLOCK_SIZE;
}
if (a4 < min_val) {
min_val = a4;
min_idx = i + 3 * BLOCK_SIZE;
}
if (a5 < min_val) {
min_val = a5;
min_idx = i + 4 * BLOCK_SIZE;
}
if (a6 < min_val) {
min_val = a6;
min_idx = i + 5 * BLOCK_SIZE;
}
if (a7 < min_val) {
min_val = a7;
min_idx = i + 6 * BLOCK_SIZE;
}
if (a8 < min_val) {
min_val = a8;
min_idx = i + 7 * BLOCK_SIZE;
}
}
smem_val[tx] = min_val;
smem_idx[tx] = min_idx;
__syncthreads();
// in-place reduction in shared memory
if (blockDim.x >= 1024 && tx < 512 && smem_val[tx + 512] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 512];
smem_idx[tx] = min_idx = smem_idx[tx + 512];
}
__syncthreads();
if (blockDim.x >= 512 && tx < 256 && smem_val[tx + 256] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 256];
smem_idx[tx] = min_idx = smem_idx[tx + 256];
}
__syncthreads();
if (blockDim.x >= 256 && tx < 128 && smem_val[tx + 128] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 128];
smem_idx[tx] = min_idx = smem_idx[tx + 128];
}
__syncthreads();
if (blockDim.x >= 128 && tx < 64 && smem_val[tx + 64] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 64];
smem_idx[tx] = min_idx = smem_idx[tx + 64];
}
__syncthreads();
// unrolling warp
if (tx < 32) {
volatile float *vsmem_val = smem_val;
volatile int *vsmem_idx = smem_idx;
if (vsmem_val[tx + 32] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 32];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 32];
}
if (vsmem_val[tx + 16] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 16];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 16];
}
if (vsmem_val[tx + 8] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 8];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 8];
}
if (vsmem_val[tx + 4] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 4];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 4];
}
if (vsmem_val[tx + 2] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 2];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 2];
}
if (vsmem_val[tx + 1] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 1];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 1];
}
}
if (tx == 0) {
output_val[bx] = min_val;
output_idx[bx] = (input_idx == nullptr) ? min_idx : input_idx[min_idx];
}
}
/*
void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int total_nodes = num_nodes1 + num_nodes2;
for (int i = 0; i < n; ++i) {
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
mat[n * idx1 + idx1] = 0.0f;
mat[n * idx2 + idx1] = 0.0f;
mat[n * idx1 + idx2] = 0.0f;
mat[n * idx2 + idx2] = 0.0f;
}*/
__global__ void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int tx = threadIdx.x;
int i = tx + blockDim.x * blockIdx.x;
if (i >= n || i == idx1) {
return;
} else if (i == idx2) {
mat[n * idx1 + i] = 0.0f;
mat[n * i + idx1] = 0.0f;
return;
}
int total_nodes = num_nodes1 + num_nodes2;
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
void cleanupTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
delete tree;
return;
}
cleanupTree(tree->left);
cleanupTree(tree->right);
}
void printTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
return;
}
cout << "(";
printTree(tree->left);
cout << ": " << tree->branch_length[0] << ", ";
printTree(tree->right);
cout << ": " << tree->branch_length[1] << ")";
}
int main() {
const int num_seqs = 7;
float h_a[num_seqs][num_seqs]{
{0.0f, 19.0f, 27.0f, 8.0f, 33.0f, 18.0f, 13.0f},
{19.0f, 0.0f, 31.0f, 18.0f, 36.0f, 1.0f, 13.0f},
{27.0f, 31.0f, 0.0f, 26.0f, 41.0f, 32.0f, 29.0f},
{8.0f, 18.0f, 26.0f, 0.0f, 31.0f, 17.0f, 14.0f},
{33.0f, 36.0f, 41.0f, 31.0f, 0.0f, 35.0f, 28.0f},
{18.0f, 1.0f, 32.0f, 17.0f, 35.0f, 0.0f, 12.0f},
{13.0f, 13.0f, 29.0f, 14.0f, 28.0f, 12.0f, 0.0f}};
Tree *nodes[num_seqs];
for (int i = 0; i < num_seqs; ++i) {
nodes[i] = new Tree(1, 0.0f, nullptr, nullptr, 0.0f, 0.0f);
}
int n = num_seqs * num_seqs;
int n_out_level0 = ceil((float)n / (BLOCK_SIZE * 8));
int n_out_level1 = ceil((float)n_out_level0 / (BLOCK_SIZE * 8));
float *h_val = (float *)malloc(sizeof(float) * n_out_level1);
int *h_idx = (int *)malloc(sizeof(int) * n_out_level1);
float *d_a;
float *d_val_level0, *d_val_level1;
int *d_idx_level0, *d_idx_level1;
CHECK(hipMalloc((void **)&d_a, sizeof(float) * n));
CHECK(hipMalloc((void **)&d_val_level0, sizeof(float) * n_out_level0));
CHECK(hipMalloc((void **)&d_idx_level0, sizeof(int) * n_out_level0));
CHECK(hipMalloc((void **)&d_val_level1, sizeof(float) * n_out_level1));
CHECK(hipMalloc((void **)&d_idx_level1, sizeof(int) * n_out_level1));
CHECK(hipMemcpy(d_a, h_a, sizeof(float) * n, hipMemcpyHostToDevice));
Tree *root;
for (int remain = num_seqs; remain >= 2; --remain) {
// int idx = getMinIdx((float *)a, num_seqs * num_seqs);
getMin<<<n_out_level0, BLOCK_SIZE>>>(d_a, nullptr, n, d_val_level0,
d_idx_level0);
CHECK(hipDeviceSynchronize());
getMin<<<n_out_level1, BLOCK_SIZE>>>(
d_val_level0, d_idx_level0, n_out_level0, d_val_level1, d_idx_level1);
CHECK(hipDeviceSynchronize());
CHECK(hipMemcpy(h_val, d_val_level1, sizeof(float) * n_out_level1,
hipMemcpyDeviceToHost));
CHECK(hipMemcpy(h_idx, d_idx_level1, sizeof(int) * n_out_level1,
hipMemcpyDeviceToHost));
float val = h_val[0];
int idx = h_idx[0];
for (int i = 0; i < n_out_level1; ++i) {
if (h_val[i] < val) {
val = h_val[i];
idx = h_idx[i];
}
}
int idx1 = idx / num_seqs;
int idx2 = idx % num_seqs;
if (idx1 > idx2) {
swap(idx1, idx2);
}
update<<<num_seqs, BLOCK_SIZE>>>(d_a, num_seqs, idx1, idx2,
nodes[idx1]->num_nodes,
nodes[idx2]->num_nodes);
float length = val;
root = new Tree(nodes[idx1]->num_nodes + nodes[idx2]->num_nodes, length / 2,
nodes[idx1], nodes[idx2],
length / 2 - nodes[idx1]->total_length,
length / 2 - nodes[idx2]->total_length);
CHECK(hipDeviceSynchronize());
nodes[idx1] = root;
}
printTree(root);
// Free device
CHECK(hipFree(d_a));
CHECK(hipFree(d_val_level0));
CHECK(hipFree(d_idx_level0));
CHECK(hipFree(d_val_level1));
CHECK(hipFree(d_idx_level1));
// Free host
free(h_val);
free(h_idx);
// Clean up tree
cleanupTree(root);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <iostream>
#include <algorithm>
#include <hip/hip_runtime.h>
using namespace std;
#define BLOCK_SIZE 128
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
struct Tree {
int num_nodes;
Tree *left;
Tree *right;
float total_length;
float branch_length[2];
Tree(int _num_nodes, float _length, Tree *_left, Tree *_right, float length1,
float length2)
: num_nodes(_num_nodes), left(_left), right(_right),
total_length(_length) {
branch_length[0] = length1;
branch_length[1] = length2;
}
};
__global__ void getMin(float *input, int *input_idx, int n, float *output_val,
int *output_idx) {
__shared__ float smem_val[BLOCK_SIZE];
__shared__ int smem_idx[BLOCK_SIZE];
int tx = threadIdx.x;
int bx = blockIdx.x;
int i = tx + bx * BLOCK_SIZE * 8;
float min_val = INFINITY;
int min_idx = i;
if (i < n) {
float a1, a2, a3, a4, a5, a6, a7, a8;
a1 = input[i];
a1 = (a1 != 0.0f) ? a1 : INFINITY;
a2 = (i + BLOCK_SIZE) < n ? input[i + BLOCK_SIZE] : INFINITY;
a2 = (a2 != 0.0f) ? a2 : INFINITY;
a3 = (i + 2 * BLOCK_SIZE) < n ? input[i + 2 * BLOCK_SIZE] : INFINITY;
a3 = (a3 != 0.0f) ? a3 : INFINITY;
a4 = (i + 3 * BLOCK_SIZE) < n ? input[i + 3 * BLOCK_SIZE] : INFINITY;
a4 = (a4 != 0.0f) ? a4 : INFINITY;
a5 = (i + 4 * BLOCK_SIZE) < n ? input[i + 4 * BLOCK_SIZE] : INFINITY;
a5 = (a5 != 0.0f) ? a5 : INFINITY;
a6 = (i + 5 * BLOCK_SIZE) < n ? input[i + 5 * BLOCK_SIZE] : INFINITY;
a6 = (a6 != 0.0f) ? a6 : INFINITY;
a7 = (i + 6 * BLOCK_SIZE) < n ? input[i + 6 * BLOCK_SIZE] : INFINITY;
a7 = (a7 != 0.0f) ? a7 : INFINITY;
a8 = (i + 7 * BLOCK_SIZE) < n ? input[i + 7 * BLOCK_SIZE] : INFINITY;
a8 = (a8 != 0.0f) ? a8 : INFINITY;
min_val = a1;
min_idx = i;
if (a2 < min_val) {
min_val = a2;
min_idx = i + BLOCK_SIZE;
}
if (a3 < min_val) {
min_val = a3;
min_idx = i + 2 * BLOCK_SIZE;
}
if (a4 < min_val) {
min_val = a4;
min_idx = i + 3 * BLOCK_SIZE;
}
if (a5 < min_val) {
min_val = a5;
min_idx = i + 4 * BLOCK_SIZE;
}
if (a6 < min_val) {
min_val = a6;
min_idx = i + 5 * BLOCK_SIZE;
}
if (a7 < min_val) {
min_val = a7;
min_idx = i + 6 * BLOCK_SIZE;
}
if (a8 < min_val) {
min_val = a8;
min_idx = i + 7 * BLOCK_SIZE;
}
}
smem_val[tx] = min_val;
smem_idx[tx] = min_idx;
__syncthreads();
// in-place reduction in shared memory
if (blockDim.x >= 1024 && tx < 512 && smem_val[tx + 512] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 512];
smem_idx[tx] = min_idx = smem_idx[tx + 512];
}
__syncthreads();
if (blockDim.x >= 512 && tx < 256 && smem_val[tx + 256] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 256];
smem_idx[tx] = min_idx = smem_idx[tx + 256];
}
__syncthreads();
if (blockDim.x >= 256 && tx < 128 && smem_val[tx + 128] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 128];
smem_idx[tx] = min_idx = smem_idx[tx + 128];
}
__syncthreads();
if (blockDim.x >= 128 && tx < 64 && smem_val[tx + 64] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 64];
smem_idx[tx] = min_idx = smem_idx[tx + 64];
}
__syncthreads();
// unrolling warp
if (tx < 32) {
volatile float *vsmem_val = smem_val;
volatile int *vsmem_idx = smem_idx;
if (vsmem_val[tx + 32] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 32];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 32];
}
if (vsmem_val[tx + 16] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 16];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 16];
}
if (vsmem_val[tx + 8] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 8];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 8];
}
if (vsmem_val[tx + 4] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 4];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 4];
}
if (vsmem_val[tx + 2] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 2];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 2];
}
if (vsmem_val[tx + 1] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 1];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 1];
}
}
if (tx == 0) {
output_val[bx] = min_val;
output_idx[bx] = (input_idx == nullptr) ? min_idx : input_idx[min_idx];
}
}
/*
void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int total_nodes = num_nodes1 + num_nodes2;
for (int i = 0; i < n; ++i) {
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
mat[n * idx1 + idx1] = 0.0f;
mat[n * idx2 + idx1] = 0.0f;
mat[n * idx1 + idx2] = 0.0f;
mat[n * idx2 + idx2] = 0.0f;
}*/
__global__ void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int tx = threadIdx.x;
int i = tx + blockDim.x * blockIdx.x;
if (i >= n || i == idx1) {
return;
} else if (i == idx2) {
mat[n * idx1 + i] = 0.0f;
mat[n * i + idx1] = 0.0f;
return;
}
int total_nodes = num_nodes1 + num_nodes2;
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
void cleanupTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
delete tree;
return;
}
cleanupTree(tree->left);
cleanupTree(tree->right);
}
void printTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
return;
}
cout << "(";
printTree(tree->left);
cout << ": " << tree->branch_length[0] << ", ";
printTree(tree->right);
cout << ": " << tree->branch_length[1] << ")";
}
int main() {
const int num_seqs = 7;
float h_a[num_seqs][num_seqs]{
{0.0f, 19.0f, 27.0f, 8.0f, 33.0f, 18.0f, 13.0f},
{19.0f, 0.0f, 31.0f, 18.0f, 36.0f, 1.0f, 13.0f},
{27.0f, 31.0f, 0.0f, 26.0f, 41.0f, 32.0f, 29.0f},
{8.0f, 18.0f, 26.0f, 0.0f, 31.0f, 17.0f, 14.0f},
{33.0f, 36.0f, 41.0f, 31.0f, 0.0f, 35.0f, 28.0f},
{18.0f, 1.0f, 32.0f, 17.0f, 35.0f, 0.0f, 12.0f},
{13.0f, 13.0f, 29.0f, 14.0f, 28.0f, 12.0f, 0.0f}};
Tree *nodes[num_seqs];
for (int i = 0; i < num_seqs; ++i) {
nodes[i] = new Tree(1, 0.0f, nullptr, nullptr, 0.0f, 0.0f);
}
int n = num_seqs * num_seqs;
int n_out_level0 = ceil((float)n / (BLOCK_SIZE * 8));
int n_out_level1 = ceil((float)n_out_level0 / (BLOCK_SIZE * 8));
float *h_val = (float *)malloc(sizeof(float) * n_out_level1);
int *h_idx = (int *)malloc(sizeof(int) * n_out_level1);
float *d_a;
float *d_val_level0, *d_val_level1;
int *d_idx_level0, *d_idx_level1;
CHECK(hipMalloc((void **)&d_a, sizeof(float) * n));
CHECK(hipMalloc((void **)&d_val_level0, sizeof(float) * n_out_level0));
CHECK(hipMalloc((void **)&d_idx_level0, sizeof(int) * n_out_level0));
CHECK(hipMalloc((void **)&d_val_level1, sizeof(float) * n_out_level1));
CHECK(hipMalloc((void **)&d_idx_level1, sizeof(int) * n_out_level1));
CHECK(hipMemcpy(d_a, h_a, sizeof(float) * n, hipMemcpyHostToDevice));
Tree *root;
for (int remain = num_seqs; remain >= 2; --remain) {
// int idx = getMinIdx((float *)a, num_seqs * num_seqs);
getMin<<<n_out_level0, BLOCK_SIZE>>>(d_a, nullptr, n, d_val_level0,
d_idx_level0);
CHECK(hipDeviceSynchronize());
getMin<<<n_out_level1, BLOCK_SIZE>>>(
d_val_level0, d_idx_level0, n_out_level0, d_val_level1, d_idx_level1);
CHECK(hipDeviceSynchronize());
CHECK(hipMemcpy(h_val, d_val_level1, sizeof(float) * n_out_level1,
hipMemcpyDeviceToHost));
CHECK(hipMemcpy(h_idx, d_idx_level1, sizeof(int) * n_out_level1,
hipMemcpyDeviceToHost));
float val = h_val[0];
int idx = h_idx[0];
for (int i = 0; i < n_out_level1; ++i) {
if (h_val[i] < val) {
val = h_val[i];
idx = h_idx[i];
}
}
int idx1 = idx / num_seqs;
int idx2 = idx % num_seqs;
if (idx1 > idx2) {
swap(idx1, idx2);
}
update<<<num_seqs, BLOCK_SIZE>>>(d_a, num_seqs, idx1, idx2,
nodes[idx1]->num_nodes,
nodes[idx2]->num_nodes);
float length = val;
root = new Tree(nodes[idx1]->num_nodes + nodes[idx2]->num_nodes, length / 2,
nodes[idx1], nodes[idx2],
length / 2 - nodes[idx1]->total_length,
length / 2 - nodes[idx2]->total_length);
CHECK(hipDeviceSynchronize());
nodes[idx1] = root;
}
printTree(root);
// Free device
CHECK(hipFree(d_a));
CHECK(hipFree(d_val_level0));
CHECK(hipFree(d_idx_level0));
CHECK(hipFree(d_val_level1));
CHECK(hipFree(d_idx_level1));
// Free host
free(h_val);
free(h_idx);
// Clean up tree
cleanupTree(root);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6getMinPfPiiS_S0_
.globl _Z6getMinPfPiiS_S0_
.p2align 8
.type _Z6getMinPfPiiS_S0_,@function
_Z6getMinPfPiiS_S0_:
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s4, s15
v_mov_b32_e32 v6, 0x7f800000
v_lshl_or_b32 v1, s4, 10, v0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_16
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v11, 0x7f800000 :: v_dual_mov_b32 v12, 0x7f800000
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v10, v[2:3], off
v_add_nc_u32_e32 v2, 0x80, v1
v_cmpx_gt_i32_e64 s6, v2
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v12, v[3:4], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v3, 0x100, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v3
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v11, v[4:5], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v4, 0x180, v1
v_dual_mov_b32 v13, 0x7f800000 :: v_dual_mov_b32 v14, 0x7f800000
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s6, v4
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v14, v[5:6], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v5, 0x200, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v5
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v13, v[6:7], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v6, 0x280, v1
v_dual_mov_b32 v15, 0x7f800000 :: v_dual_mov_b32 v16, 0x7f800000
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s6, v6
s_cbranch_execz .LBB0_11
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[6:7]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v16, v[7:8], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v7, 0x300, v1
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v7
s_cbranch_execz .LBB0_13
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[7:8]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v15, v[8:9], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v8, 0x380, v1
v_mov_b32_e32 v9, 0x7f800000
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v8
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_15
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 2, v[8:9]
v_add_co_u32 v17, vcc_lo, s2, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v18, vcc_lo
global_load_b32 v9, v[17:18], off
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 0, v12
v_cmp_neq_f32_e64 s2, 0, v11
v_cndmask_b32_e32 v12, 0x7f800000, v12, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v11, 0x7f800000, v11, s2
v_cmp_neq_f32_e64 s2, 0, v14
v_cndmask_b32_e32 v10, 0x7f800000, v10, vcc_lo
v_cmp_lt_f32_e32 vcc_lo, v12, v10
v_dual_cndmask_b32 v1, v1, v2 :: v_dual_cndmask_b32 v2, v10, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v10, 0x7f800000, v14, s2
v_cmp_neq_f32_e64 s2, 0, v13
v_cmp_lt_f32_e32 vcc_lo, v11, v2
v_cndmask_b32_e32 v2, v2, v11, vcc_lo
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v3, 0x7f800000, v13, s2
v_cmp_neq_f32_e64 s2, 0, v16
v_cmp_lt_f32_e32 vcc_lo, v10, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v1, v1, v4
v_cndmask_b32_e64 v4, 0x7f800000, v16, s2
v_cmp_neq_f32_e64 s2, 0, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_lt_f32_e32 vcc_lo, v3, v2
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, 0x7f800000, v15, s2
v_cmp_neq_f32_e64 s2, 0, v9
v_cmp_lt_f32_e32 vcc_lo, v4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_cndmask_b32 v2, v2, v4
v_cndmask_b32_e64 v4, 0x7f800000, v9, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_lt_f32_e32 vcc_lo, v3, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cndmask_b32_e32 v1, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_lt_f32_e32 vcc_lo, v4, v2
v_cndmask_b32_e32 v6, v2, v4, vcc_lo
v_cndmask_b32_e32 v1, v1, v8, vcc_lo
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v2, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 0x200, v0
ds_store_2addr_stride64_b32 v2, v1, v6 offset1:2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b32 s2, s[0:1], 0x34
v_add_nc_u32_e32 v3, 0x200, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s3, 0x3ff, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, vcc_lo, s3
s_and_saveexec_b32 s3, s5
s_cbranch_execz .LBB0_20
v_add_nc_u32_e32 v5, 0x200, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v5
ds_load_b32 v4, v4 offset:512
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v4, v7
s_cbranch_execz .LBB0_19
v_dual_mov_b32 v6, v4 :: v_dual_lshlrev_b32 v1, 2, v5
ds_load_b32 v1, v1
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(1)
ds_store_b32 v2, v1
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_u16_e64 s3, 0x1ff, s2
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s5, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s5
s_cbranch_execz .LBB0_24
v_add_nc_u32_e32 v4, 0x100, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v4
ds_load_b32 v4, v5 offset:512
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v4, v7
s_cbranch_execz .LBB0_23
ds_load_b32 v1, v5
v_mov_b32_e32 v6, v4
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(1)
ds_store_b32 v2, v1
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_lt_u16_e64 s3, 0xff, s2
v_cmp_gt_u32_e32 vcc_lo, 0x80, v0
s_and_b32 s2, 0xffff, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s5, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s5
s_cbranch_execz .LBB0_28
v_add_nc_u32_e32 v4, 0x80, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v4
ds_load_b32 v4, v5 offset:512
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v4, v7
s_cbranch_execz .LBB0_27
ds_store_b32 v3, v4
ds_load_b32 v1, v5
v_mov_b32_e32 v6, v4
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v1
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_28:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_u32_e32 vcc_lo, 64, v0
s_cmpk_gt_u32 s2, 0x7f
s_waitcnt lgkmcnt(0)
s_cselect_b32 s2, -1, 0
s_barrier
s_and_b32 s3, vcc_lo, s2
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_32
v_add_nc_u32_e32 v4, 64, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v4
ds_load_b32 v4, v5 offset:512
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v4, v7
s_cbranch_execz .LBB0_31
ds_load_b32 v1, v5
v_mov_b32_e32 v6, v4
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(1)
ds_store_b32 v2, v1
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_32:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_46
v_or_b32_e32 v7, 32, v0
v_lshl_add_u32 v2, v0, 2, 0x200
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, v7, 2, 0x200
v_cmp_ne_u32_e64 s2, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e64 v2, 0, v2, s2
v_cndmask_b32_e32 v4, 0, v3, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
v_cndmask_b32_e64 v3, 0, s7, s2
s_mov_b32 s2, exec_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_35
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v7
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, 16, v0
s_mov_b64 s[6:7], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v7, 2, 0x200
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_37
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v7
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_37:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, 8, v0
s_mov_b64 s[6:7], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v7, 2, 0x200
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_39
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v7
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, 4, v0
s_mov_b64 s[6:7], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v7, 2, 0x200
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_41
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v7
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_41:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, 2, v0
s_mov_b64 s[6:7], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v7, 2, 0x200
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_43
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v7
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[4:5], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v7, 1, v0
s_mov_b64 s[6:7], src_shared_base
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v4, v7, 2, 0x200
v_cmp_ne_u32_e32 vcc_lo, -1, v4
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
flat_load_b32 v8, v[4:5] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v9, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_f32_e32 v8, v9
s_cbranch_execz .LBB0_45
flat_load_b32 v6, v[4:5] glc dlc
s_waitcnt vmcnt(0)
s_mov_b64 s[6:7], src_shared_base
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v6 dlc
s_waitcnt_vscnt null, 0x0
v_lshlrev_b32_e32 v2, 2, v0
v_lshlrev_b32_e32 v1, 2, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v4, 0, v1, vcc_lo
v_cndmask_b32_e64 v5, 0, s7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v2
flat_load_b32 v1, v[4:5] glc dlc
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cndmask_b32_e64 v3, 0, s7, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b32 v[2:3], v1 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_45:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_50
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x8
s_ashr_i32 s5, s4, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s8, s2
s_addc_u32 s5, s9, s3
s_cmp_eq_u64 s[6:7], 0
global_store_b32 v0, v6, s[4:5]
s_cbranch_scc1 .LBB0_49
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
.LBB0_49:
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_50:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6getMinPfPiiS_S0_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6getMinPfPiiS_S0_, .Lfunc_end0-_Z6getMinPfPiiS_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6updatePfiiiii
.globl _Z6updatePfiiiii
.p2align 8
.type _Z6updatePfiiiii,@function
_Z6updatePfiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s4, v1
v_cmp_ne_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_ne_u32_e64 s7, v1
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB1_3
v_mad_u64_u32 v[2:3], null, s7, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x14
v_mul_lo_u32 v12, v1, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s5, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v6, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v3, s1
v_cvt_f32_i32_e32 v8, s0
s_add_i32 s0, s1, s0
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[4:5], off
v_cvt_f32_i32_e32 v9, s0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, v0, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v2, v8
v_div_scale_f32 v2, null, v9, v9, v3
v_div_scale_f32 v10, vcc_lo, v3, v9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v0, -v2, v8, 1.0
v_fmac_f32_e32 v8, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v8
v_fma_f32 v0, -v2, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v0, v8
v_add_nc_u32_e32 v0, s5, v12
v_fma_f32 v2, -v2, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_div_fmas_f32 v2, v2, v8, v11
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_div_fixup_f32 v2, v2, v9, v3
v_add_nc_u32_e32 v3, s7, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_clause 0x2
global_store_b32 v[4:5], v2, off
global_store_b32 v[6:7], v8, off
global_store_b32 v[0:1], v2, off
.LBB1_3:
s_and_not1_saveexec_b32 s0, s6
s_cbranch_execz .LBB1_5
v_mad_u64_u32 v[2:3], null, s5, s4, v[1:2]
s_mov_b32 s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_mad_u64_u32 v[3:4], null, v1, s4, s[6:7]
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s0
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6updatePfiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6updatePfiiiii, .Lfunc_end1-_Z6updatePfiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6getMinPfPiiS_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6getMinPfPiiS_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6updatePfiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6updatePfiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <iostream>
#include <algorithm>
#include <hip/hip_runtime.h>
using namespace std;
#define BLOCK_SIZE 128
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) { \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
struct Tree {
int num_nodes;
Tree *left;
Tree *right;
float total_length;
float branch_length[2];
Tree(int _num_nodes, float _length, Tree *_left, Tree *_right, float length1,
float length2)
: num_nodes(_num_nodes), left(_left), right(_right),
total_length(_length) {
branch_length[0] = length1;
branch_length[1] = length2;
}
};
__global__ void getMin(float *input, int *input_idx, int n, float *output_val,
int *output_idx) {
__shared__ float smem_val[BLOCK_SIZE];
__shared__ int smem_idx[BLOCK_SIZE];
int tx = threadIdx.x;
int bx = blockIdx.x;
int i = tx + bx * BLOCK_SIZE * 8;
float min_val = INFINITY;
int min_idx = i;
if (i < n) {
float a1, a2, a3, a4, a5, a6, a7, a8;
a1 = input[i];
a1 = (a1 != 0.0f) ? a1 : INFINITY;
a2 = (i + BLOCK_SIZE) < n ? input[i + BLOCK_SIZE] : INFINITY;
a2 = (a2 != 0.0f) ? a2 : INFINITY;
a3 = (i + 2 * BLOCK_SIZE) < n ? input[i + 2 * BLOCK_SIZE] : INFINITY;
a3 = (a3 != 0.0f) ? a3 : INFINITY;
a4 = (i + 3 * BLOCK_SIZE) < n ? input[i + 3 * BLOCK_SIZE] : INFINITY;
a4 = (a4 != 0.0f) ? a4 : INFINITY;
a5 = (i + 4 * BLOCK_SIZE) < n ? input[i + 4 * BLOCK_SIZE] : INFINITY;
a5 = (a5 != 0.0f) ? a5 : INFINITY;
a6 = (i + 5 * BLOCK_SIZE) < n ? input[i + 5 * BLOCK_SIZE] : INFINITY;
a6 = (a6 != 0.0f) ? a6 : INFINITY;
a7 = (i + 6 * BLOCK_SIZE) < n ? input[i + 6 * BLOCK_SIZE] : INFINITY;
a7 = (a7 != 0.0f) ? a7 : INFINITY;
a8 = (i + 7 * BLOCK_SIZE) < n ? input[i + 7 * BLOCK_SIZE] : INFINITY;
a8 = (a8 != 0.0f) ? a8 : INFINITY;
min_val = a1;
min_idx = i;
if (a2 < min_val) {
min_val = a2;
min_idx = i + BLOCK_SIZE;
}
if (a3 < min_val) {
min_val = a3;
min_idx = i + 2 * BLOCK_SIZE;
}
if (a4 < min_val) {
min_val = a4;
min_idx = i + 3 * BLOCK_SIZE;
}
if (a5 < min_val) {
min_val = a5;
min_idx = i + 4 * BLOCK_SIZE;
}
if (a6 < min_val) {
min_val = a6;
min_idx = i + 5 * BLOCK_SIZE;
}
if (a7 < min_val) {
min_val = a7;
min_idx = i + 6 * BLOCK_SIZE;
}
if (a8 < min_val) {
min_val = a8;
min_idx = i + 7 * BLOCK_SIZE;
}
}
smem_val[tx] = min_val;
smem_idx[tx] = min_idx;
__syncthreads();
// in-place reduction in shared memory
if (blockDim.x >= 1024 && tx < 512 && smem_val[tx + 512] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 512];
smem_idx[tx] = min_idx = smem_idx[tx + 512];
}
__syncthreads();
if (blockDim.x >= 512 && tx < 256 && smem_val[tx + 256] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 256];
smem_idx[tx] = min_idx = smem_idx[tx + 256];
}
__syncthreads();
if (blockDim.x >= 256 && tx < 128 && smem_val[tx + 128] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 128];
smem_idx[tx] = min_idx = smem_idx[tx + 128];
}
__syncthreads();
if (blockDim.x >= 128 && tx < 64 && smem_val[tx + 64] < smem_val[tx]) {
smem_val[tx] = min_val = smem_val[tx + 64];
smem_idx[tx] = min_idx = smem_idx[tx + 64];
}
__syncthreads();
// unrolling warp
if (tx < 32) {
volatile float *vsmem_val = smem_val;
volatile int *vsmem_idx = smem_idx;
if (vsmem_val[tx + 32] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 32];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 32];
}
if (vsmem_val[tx + 16] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 16];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 16];
}
if (vsmem_val[tx + 8] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 8];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 8];
}
if (vsmem_val[tx + 4] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 4];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 4];
}
if (vsmem_val[tx + 2] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 2];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 2];
}
if (vsmem_val[tx + 1] < vsmem_val[tx]) {
vsmem_val[tx] = min_val = vsmem_val[tx + 1];
vsmem_idx[tx] = min_idx = vsmem_idx[tx + 1];
}
}
if (tx == 0) {
output_val[bx] = min_val;
output_idx[bx] = (input_idx == nullptr) ? min_idx : input_idx[min_idx];
}
}
/*
void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int total_nodes = num_nodes1 + num_nodes2;
for (int i = 0; i < n; ++i) {
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
mat[n * idx1 + idx1] = 0.0f;
mat[n * idx2 + idx1] = 0.0f;
mat[n * idx1 + idx2] = 0.0f;
mat[n * idx2 + idx2] = 0.0f;
}*/
__global__ void update(float *mat, int n, int idx1, int idx2, int num_nodes1,
int num_nodes2) {
int tx = threadIdx.x;
int i = tx + blockDim.x * blockIdx.x;
if (i >= n || i == idx1) {
return;
} else if (i == idx2) {
mat[n * idx1 + i] = 0.0f;
mat[n * i + idx1] = 0.0f;
return;
}
int total_nodes = num_nodes1 + num_nodes2;
float val =
(mat[n * idx1 + i] * num_nodes1 + mat[n * idx2 + i] * num_nodes2) /
total_nodes;
mat[n * idx1 + i] = val;
mat[n * idx2 + i] = 0.0f;
mat[n * i + idx1] = val;
mat[n * i + idx2] = 0.0f;
}
void cleanupTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
delete tree;
return;
}
cleanupTree(tree->left);
cleanupTree(tree->right);
}
void printTree(Tree *tree) {
// Reach the leaf
if (tree->left == nullptr && tree->right == nullptr) {
return;
}
cout << "(";
printTree(tree->left);
cout << ": " << tree->branch_length[0] << ", ";
printTree(tree->right);
cout << ": " << tree->branch_length[1] << ")";
}
int main() {
const int num_seqs = 7;
float h_a[num_seqs][num_seqs]{
{0.0f, 19.0f, 27.0f, 8.0f, 33.0f, 18.0f, 13.0f},
{19.0f, 0.0f, 31.0f, 18.0f, 36.0f, 1.0f, 13.0f},
{27.0f, 31.0f, 0.0f, 26.0f, 41.0f, 32.0f, 29.0f},
{8.0f, 18.0f, 26.0f, 0.0f, 31.0f, 17.0f, 14.0f},
{33.0f, 36.0f, 41.0f, 31.0f, 0.0f, 35.0f, 28.0f},
{18.0f, 1.0f, 32.0f, 17.0f, 35.0f, 0.0f, 12.0f},
{13.0f, 13.0f, 29.0f, 14.0f, 28.0f, 12.0f, 0.0f}};
Tree *nodes[num_seqs];
for (int i = 0; i < num_seqs; ++i) {
nodes[i] = new Tree(1, 0.0f, nullptr, nullptr, 0.0f, 0.0f);
}
int n = num_seqs * num_seqs;
int n_out_level0 = ceil((float)n / (BLOCK_SIZE * 8));
int n_out_level1 = ceil((float)n_out_level0 / (BLOCK_SIZE * 8));
float *h_val = (float *)malloc(sizeof(float) * n_out_level1);
int *h_idx = (int *)malloc(sizeof(int) * n_out_level1);
float *d_a;
float *d_val_level0, *d_val_level1;
int *d_idx_level0, *d_idx_level1;
CHECK(hipMalloc((void **)&d_a, sizeof(float) * n));
CHECK(hipMalloc((void **)&d_val_level0, sizeof(float) * n_out_level0));
CHECK(hipMalloc((void **)&d_idx_level0, sizeof(int) * n_out_level0));
CHECK(hipMalloc((void **)&d_val_level1, sizeof(float) * n_out_level1));
CHECK(hipMalloc((void **)&d_idx_level1, sizeof(int) * n_out_level1));
CHECK(hipMemcpy(d_a, h_a, sizeof(float) * n, hipMemcpyHostToDevice));
Tree *root;
for (int remain = num_seqs; remain >= 2; --remain) {
// int idx = getMinIdx((float *)a, num_seqs * num_seqs);
getMin<<<n_out_level0, BLOCK_SIZE>>>(d_a, nullptr, n, d_val_level0,
d_idx_level0);
CHECK(hipDeviceSynchronize());
getMin<<<n_out_level1, BLOCK_SIZE>>>(
d_val_level0, d_idx_level0, n_out_level0, d_val_level1, d_idx_level1);
CHECK(hipDeviceSynchronize());
CHECK(hipMemcpy(h_val, d_val_level1, sizeof(float) * n_out_level1,
hipMemcpyDeviceToHost));
CHECK(hipMemcpy(h_idx, d_idx_level1, sizeof(int) * n_out_level1,
hipMemcpyDeviceToHost));
float val = h_val[0];
int idx = h_idx[0];
for (int i = 0; i < n_out_level1; ++i) {
if (h_val[i] < val) {
val = h_val[i];
idx = h_idx[i];
}
}
int idx1 = idx / num_seqs;
int idx2 = idx % num_seqs;
if (idx1 > idx2) {
swap(idx1, idx2);
}
update<<<num_seqs, BLOCK_SIZE>>>(d_a, num_seqs, idx1, idx2,
nodes[idx1]->num_nodes,
nodes[idx2]->num_nodes);
float length = val;
root = new Tree(nodes[idx1]->num_nodes + nodes[idx2]->num_nodes, length / 2,
nodes[idx1], nodes[idx2],
length / 2 - nodes[idx1]->total_length,
length / 2 - nodes[idx2]->total_length);
CHECK(hipDeviceSynchronize());
nodes[idx1] = root;
}
printTree(root);
// Free device
CHECK(hipFree(d_a));
CHECK(hipFree(d_val_level0));
CHECK(hipFree(d_idx_level0));
CHECK(hipFree(d_val_level1));
CHECK(hipFree(d_idx_level1));
// Free host
free(h_val);
free(h_idx);
// Clean up tree
cleanupTree(root);
return 0;
}
|
.text
.file "upgma.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__getMinPfPiiS_S0_ # -- Begin function _Z21__device_stub__getMinPfPiiS_S0_
.p2align 4, 0x90
.type _Z21__device_stub__getMinPfPiiS_S0_,@function
_Z21__device_stub__getMinPfPiiS_S0_: # @_Z21__device_stub__getMinPfPiiS_S0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6getMinPfPiiS_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__getMinPfPiiS_S0_, .Lfunc_end0-_Z21__device_stub__getMinPfPiiS_S0_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__updatePfiiiii # -- Begin function _Z21__device_stub__updatePfiiiii
.p2align 4, 0x90
.type _Z21__device_stub__updatePfiiiii,@function
_Z21__device_stub__updatePfiiiii: # @_Z21__device_stub__updatePfiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z21__device_stub__updatePfiiiii, .Lfunc_end1-_Z21__device_stub__updatePfiiiii
.cfi_endproc
# -- End function
.globl _Z11cleanupTreeP4Tree # -- Begin function _Z11cleanupTreeP4Tree
.p2align 4, 0x90
.type _Z11cleanupTreeP4Tree,@function
_Z11cleanupTreeP4Tree: # @_Z11cleanupTreeP4Tree
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
callq _Z11cleanupTreeP4Tree
movq 16(%rbx), %rbx
.LBB2_1: # %tailrecurse
# =>This Inner Loop Header: Depth=1
movq 8(%rbx), %rdi
testq %rdi, %rdi
jne .LBB2_5
# %bb.2: # in Loop: Header=BB2_1 Depth=1
cmpq $0, 16(%rbx)
jne .LBB2_5
# %bb.3:
testq %rbx, %rbx
je .LBB2_6
# %bb.4:
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_6:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11cleanupTreeP4Tree, .Lfunc_end2-_Z11cleanupTreeP4Tree
.cfi_endproc
# -- End function
.globl _Z9printTreeP4Tree # -- Begin function _Z9printTreeP4Tree
.p2align 4, 0x90
.type _Z9printTreeP4Tree,@function
_Z9printTreeP4Tree: # @_Z9printTreeP4Tree
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
cmpq $0, 8(%rdi)
jne .LBB3_3
# %bb.1:
cmpq $0, 16(%rbx)
je .LBB3_2
.LBB3_3:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rbx), %rdi
callq _Z9printTreeP4Tree
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rbx), %rdi
callq _Z9printTreeP4Tree
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.LBB3_2: # %common.ret
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9printTreeP4Tree, .Lfunc_end3-_Z9printTreeP4Tree
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 528
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 272(%rsp), %rdi
movl $.L__const.main.h_a, %esi
movl $196, %edx
callq memcpy@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $40, %edi
callq _Znwm
movl $1, (%rax)
xorps %xmm0, %xmm0
movups %xmm0, 8(%rax)
movups %xmm0, 20(%rax)
movq %rax, 208(%rsp,%rbx,8)
incq %rbx
cmpq $7, %rbx
jne .LBB4_1
# %bb.2:
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbp
leaq 96(%rsp), %rdi
movl $196, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_3
# %bb.6:
leaq 128(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_7
# %bb.8:
leaq 112(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_9
# %bb.10:
leaq 120(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_11
# %bb.12:
leaq 104(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14:
movq 96(%rsp), %rdi
leaq 272(%rsp), %rsi
movl $196, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_20
# %bb.15: # %.preheader
movl $8, %ebx
movabsq $4294967424, %rax # imm = 0x100000080
leaq -127(%rax), %r15
addq $-121, %rax
movq %rax, 200(%rsp) # 8-byte Spill
movq %r14, 192(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_16: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_18
# %bb.17: # in Loop: Header=BB4_16 Depth=1
movq 96(%rsp), %rax
movq 128(%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 88(%rsp)
movq $0, 48(%rsp)
movl $49, 12(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6getMinPfPiiS_S0_, %edi
leaq 144(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_18: # in Loop: Header=BB4_16 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_19
# %bb.21: # in Loop: Header=BB4_16 Depth=1
movq %r15, %rdi
movl $1, %esi
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22: # in Loop: Header=BB4_16 Depth=1
movq 128(%rsp), %rax
movq 112(%rsp), %rcx
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq %rax, 88(%rsp)
movq %rcx, 48(%rsp)
movl $1, 12(%rsp)
movq %rdx, 40(%rsp)
movq %rsi, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6getMinPfPiiS_S0_, %edi
leaq 144(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23: # in Loop: Header=BB4_16 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_24
# %bb.25: # in Loop: Header=BB4_16 Depth=1
movq 120(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_26
# %bb.27: # in Loop: Header=BB4_16 Depth=1
movq 104(%rsp), %rsi
movl $4, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_28
# %bb.29: # in Loop: Header=BB4_16 Depth=1
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 136(%rsp) # 4-byte Spill
movq %rbp, %r12
movslq (%rbp), %rax
imulq $-1840700269, %rax, %rcx # imm = 0x92492493
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $2, %ecx
addl %edx, %ecx
leal (,%rcx,8), %edx
movl %ecx, %ebp
subl %edx, %ebp
addl %eax, %ebp
cmpl %ebp, %ecx
movl %ebp, %r13d
cmovgl %ecx, %r13d
cmovll %ecx, %ebp
movq 200(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
movslq %ebp, %r14
movslq %r13d, %rbp
testl %eax, %eax
jne .LBB4_31
# %bb.30: # in Loop: Header=BB4_16 Depth=1
movq 96(%rsp), %rax
movq 208(%rsp,%r14,8), %rcx
movl (%rcx), %ecx
movq 208(%rsp,%rbp,8), %rdx
movl (%rdx), %edx
movq %rax, 88(%rsp)
movl $7, 32(%rsp)
movl %r14d, 24(%rsp)
movl %ebp, 16(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 140(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 140(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6updatePfiiiii, %edi
leaq 144(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31: # in Loop: Header=BB4_16 Depth=1
movl $40, %edi
callq _Znwm
movq %rax, %r13
movq 208(%rsp,%r14,8), %rax
movq 208(%rsp,%rbp,8), %rcx
movl (%rcx), %edx
addl (%rax), %edx
movss 136(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
mulss .LCPI4_0(%rip), %xmm2
movaps %xmm2, %xmm0
subss 24(%rax), %xmm0
movaps %xmm2, %xmm1
subss 24(%rcx), %xmm1
movl %edx, (%r13)
movq %rax, 8(%r13)
movq %rcx, 16(%r13)
movss %xmm2, 24(%r13)
movss %xmm0, 28(%r13)
movss %xmm1, 32(%r13)
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_32
# %bb.33: # in Loop: Header=BB4_16 Depth=1
movq %r13, 208(%rsp,%r14,8)
decl %ebx
cmpl $2, %ebx
movq 192(%rsp), %r14 # 8-byte Reload
movq %r12, %rbp
ja .LBB4_16
# %bb.34:
movq %r13, %rdi
callq _Z9printTreeP4Tree
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_35
# %bb.36:
movq 128(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_37
# %bb.38:
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_39
# %bb.40:
movq 120(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_41
# %bb.42:
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_43
# %bb.44:
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r13, %rdi
callq _Z11cleanupTreeP4Tree
xorl %eax, %eax
addq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_32:
.cfi_def_cfa_offset 528
movl %eax, %ebp
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $308, %ecx # imm = 0x134
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %rbx, %rdi
movl %ebp, %edx
jmp .LBB4_5
.LBB4_28:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $283, %ecx # imm = 0x11B
jmp .LBB4_4
.LBB4_26:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $281, %ecx # imm = 0x119
jmp .LBB4_4
.LBB4_24:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $278, %ecx # imm = 0x116
jmp .LBB4_4
.LBB4_19:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $273, %ecx # imm = 0x111
.LBB4_4:
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %r14, %rdi
movl %ebx, %edx
.LBB4_5:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_3:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $259, %ecx # imm = 0x103
jmp .LBB4_4
.LBB4_7:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $260, %ecx # imm = 0x104
jmp .LBB4_4
.LBB4_9:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $261, %ecx # imm = 0x105
jmp .LBB4_4
.LBB4_11:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $262, %ecx # imm = 0x106
jmp .LBB4_4
.LBB4_13:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $263, %ecx # imm = 0x107
jmp .LBB4_4
.LBB4_20:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $265, %ecx # imm = 0x109
jmp .LBB4_4
.LBB4_35:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $315, %ecx # imm = 0x13B
jmp .LBB4_4
.LBB4_37:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $316, %ecx # imm = 0x13C
jmp .LBB4_4
.LBB4_39:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $317, %ecx # imm = 0x13D
jmp .LBB4_4
.LBB4_41:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $318, %ecx # imm = 0x13E
jmp .LBB4_4
.LBB4_43:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $319, %ecx # imm = 0x13F
jmp .LBB4_4
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6getMinPfPiiS_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6getMinPfPiiS_S0_,@object # @_Z6getMinPfPiiS_S0_
.section .rodata,"a",@progbits
.globl _Z6getMinPfPiiS_S0_
.p2align 3, 0x0
_Z6getMinPfPiiS_S0_:
.quad _Z21__device_stub__getMinPfPiiS_S0_
.size _Z6getMinPfPiiS_S0_, 8
.type _Z6updatePfiiiii,@object # @_Z6updatePfiiiii
.globl _Z6updatePfiiiii
.p2align 3, 0x0
_Z6updatePfiiiii:
.quad _Z21__device_stub__updatePfiiiii
.size _Z6updatePfiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "("
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type .L__const.main.h_a,@object # @__const.main.h_a
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.h_a:
.long 0x00000000 # float 0
.long 0x41980000 # float 19
.long 0x41d80000 # float 27
.long 0x41000000 # float 8
.long 0x42040000 # float 33
.long 0x41900000 # float 18
.long 0x41500000 # float 13
.long 0x41980000 # float 19
.long 0x00000000 # float 0
.long 0x41f80000 # float 31
.long 0x41900000 # float 18
.long 0x42100000 # float 36
.long 0x3f800000 # float 1
.long 0x41500000 # float 13
.long 0x41d80000 # float 27
.long 0x41f80000 # float 31
.long 0x00000000 # float 0
.long 0x41d00000 # float 26
.long 0x42240000 # float 41
.long 0x42000000 # float 32
.long 0x41e80000 # float 29
.long 0x41000000 # float 8
.long 0x41900000 # float 18
.long 0x41d00000 # float 26
.long 0x00000000 # float 0
.long 0x41f80000 # float 31
.long 0x41880000 # float 17
.long 0x41600000 # float 14
.long 0x42040000 # float 33
.long 0x42100000 # float 36
.long 0x42240000 # float 41
.long 0x41f80000 # float 31
.long 0x00000000 # float 0
.long 0x420c0000 # float 35
.long 0x41e00000 # float 28
.long 0x41900000 # float 18
.long 0x3f800000 # float 1
.long 0x42000000 # float 32
.long 0x41880000 # float 17
.long 0x420c0000 # float 35
.long 0x00000000 # float 0
.long 0x41400000 # float 12
.long 0x41500000 # float 13
.long 0x41500000 # float 13
.long 0x41e80000 # float 29
.long 0x41600000 # float 14
.long 0x41e00000 # float 28
.long 0x41400000 # float 12
.long 0x00000000 # float 0
.size .L__const.main.h_a, 196
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Error: %s:%d, "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hle46/UPGMA/master/gpu/upgma.hip"
.size .L.str.5, 90
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "code: %d, reason: %s\n"
.size .L.str.6, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6getMinPfPiiS_S0_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6updatePfiiiii"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__getMinPfPiiS_S0_
.addrsig_sym _Z21__device_stub__updatePfiiiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6getMinPfPiiS_S0_
.addrsig_sym _Z6updatePfiiiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0014b809_00000000-6_upgma.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3932:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3932:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cleanupTreeP4Tree
.type _Z11cleanupTreeP4Tree, @function
_Z11cleanupTreeP4Tree:
.LFB3926:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
testq %rdi, %rdi
je .L7
.L4:
call _Z11cleanupTreeP4Tree
movq 16(%rbx), %rdi
call _Z11cleanupTreeP4Tree
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
cmpq $0, 16(%rbx)
jne .L4
movl $40, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
jmp .L3
.cfi_endproc
.LFE3926:
.size _Z11cleanupTreeP4Tree, .-_Z11cleanupTreeP4Tree
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "("
.LC1:
.string ": "
.LC2:
.string ", "
.LC3:
.string ")"
.text
.globl _Z9printTreeP4Tree
.type _Z9printTreeP4Tree, @function
_Z9printTreeP4Tree:
.LFB3927:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
cmpq $0, 8(%rdi)
je .L12
.L9:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rbx), %rdi
call _Z9printTreeP4Tree
movl $2, %edx
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 28(%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rbx), %rdi
call _Z9printTreeP4Tree
movl $2, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 32(%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L8:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
cmpq $0, 16(%rdi)
jne .L9
jmp .L8
.cfi_endproc
.LFE3927:
.size _Z9printTreeP4Tree, .-_Z9printTreeP4Tree
.globl _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
.type _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_, @function
_Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_:
.LFB3954:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6getMinPfPiiS_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3954:
.size _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_, .-_Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
.globl _Z6getMinPfPiiS_S0_
.type _Z6getMinPfPiiS_S0_, @function
_Z6getMinPfPiiS_S0_:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _Z6getMinPfPiiS_S0_, .-_Z6getMinPfPiiS_S0_
.globl _Z30__device_stub__Z6updatePfiiiiiPfiiiii
.type _Z30__device_stub__Z6updatePfiiiiiPfiiiii, @function
_Z30__device_stub__Z6updatePfiiiiiPfiiiii:
.LFB3956:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6updatePfiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3956:
.size _Z30__device_stub__Z6updatePfiiiiiPfiiiii, .-_Z30__device_stub__Z6updatePfiiiiiPfiiiii
.globl _Z6updatePfiiiii
.type _Z6updatePfiiiii, @function
_Z6updatePfiiiii:
.LFB3957:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6updatePfiiiiiPfiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3957:
.size _Z6updatePfiiiii, .-_Z6updatePfiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC23:
.string "/home/ubuntu/Datasets/stackv2/train-structured/hle46/UPGMA/master/gpu/upgma.cu"
.section .rodata.str1.1
.LC24:
.string "Error: %s:%d, "
.LC25:
.string "code: %d, reason: %s\n"
.text
.globl main
.type main, @function
main:
.LFB3928:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $360, %rsp
.cfi_def_cfa_offset 416
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
movl $0x00000000, 144(%rsp)
movss .LC5(%rip), %xmm2
movss %xmm2, 148(%rsp)
movss .LC6(%rip), %xmm3
movss %xmm3, 152(%rsp)
movss .LC7(%rip), %xmm6
movss %xmm6, 156(%rsp)
movss .LC8(%rip), %xmm10
movss %xmm10, 160(%rsp)
movss .LC9(%rip), %xmm1
movss %xmm1, 164(%rsp)
movss .LC10(%rip), %xmm0
movss %xmm0, 168(%rsp)
movss %xmm2, 172(%rsp)
movl $0x00000000, 176(%rsp)
movss .LC11(%rip), %xmm2
movss %xmm2, 180(%rsp)
movss %xmm1, 184(%rsp)
movss .LC12(%rip), %xmm9
movss %xmm9, 188(%rsp)
movss .LC13(%rip), %xmm8
movss %xmm8, 192(%rsp)
movss %xmm0, 196(%rsp)
movss %xmm3, 200(%rsp)
movss %xmm2, 204(%rsp)
movl $0x00000000, 208(%rsp)
movss .LC14(%rip), %xmm3
movss %xmm3, 212(%rsp)
movss .LC15(%rip), %xmm5
movss %xmm5, 216(%rsp)
movss .LC16(%rip), %xmm7
movss %xmm7, 220(%rsp)
movss .LC17(%rip), %xmm4
movss %xmm4, 224(%rsp)
movss %xmm6, 228(%rsp)
movss %xmm1, 232(%rsp)
movss %xmm3, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm2, 244(%rsp)
movss .LC18(%rip), %xmm6
movss %xmm6, 248(%rsp)
movss .LC19(%rip), %xmm3
movss %xmm3, 252(%rsp)
movss %xmm10, 256(%rsp)
movss %xmm9, 260(%rsp)
movss %xmm5, 264(%rsp)
movss %xmm2, 268(%rsp)
movl $0x00000000, 272(%rsp)
movss .LC20(%rip), %xmm5
movss %xmm5, 276(%rsp)
movss .LC21(%rip), %xmm2
movss %xmm2, 280(%rsp)
movss %xmm1, 284(%rsp)
movss %xmm8, 288(%rsp)
movss %xmm7, 292(%rsp)
movss %xmm6, 296(%rsp)
movss %xmm5, 300(%rsp)
movl $0x00000000, 304(%rsp)
movss .LC22(%rip), %xmm1
movss %xmm1, 308(%rsp)
movss %xmm0, 312(%rsp)
movss %xmm0, 316(%rsp)
movss %xmm4, 320(%rsp)
movss %xmm3, 324(%rsp)
movss %xmm2, 328(%rsp)
movss %xmm1, 332(%rsp)
movl $0x00000000, 336(%rsp)
leaq 80(%rsp), %rbx
leaq 136(%rsp), %rbp
.L30:
movl $40, %edi
call _Znwm@PLT
movl $1, (%rax)
movq $0, 8(%rax)
movq $0, 16(%rax)
movl $0x00000000, 24(%rax)
movl $0x00000000, 28(%rax)
movl $0x00000000, 32(%rax)
movq %rax, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L30
movl $4, %edi
call malloc@PLT
movq %rax, %r15
movl $4, %edi
call malloc@PLT
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $196, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L56
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L57
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L58
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L59
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L60
leaq 144(%rsp), %rsi
movl $1, %ecx
movl $196, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
movl $6, %r13d
jmp .L36
.L56:
movl $259, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl $260, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl $261, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl $262, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl $263, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $265, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
movq 40(%rsp), %r8
movq 24(%rsp), %rcx
movl $49, %edx
movl $0, %esi
movq 16(%rsp), %rdi
call _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
jmp .L37
.L66:
movl $273, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
movq 48(%rsp), %r8
movq 32(%rsp), %rcx
movl $1, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z6getMinPfPiiS_S0_PfPiiS_S0_
jmp .L39
.L68:
movl $278, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
movl $280, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L70:
movl $282, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $7, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L44:
movl $40, %edi
call _Znwm@PLT
movq %rax, %r12
movss 12(%rsp), %xmm0
mulss .LC26(%rip), %xmm0
movslq %ebx, %rbx
movq 80(%rsp,%rbx,8), %rax
movaps %xmm0, %xmm1
subss 24(%rax), %xmm1
movslq %ebp, %rdx
movq 80(%rsp,%rdx,8), %rdx
movaps %xmm0, %xmm2
subss 24(%rdx), %xmm2
movl (%rax), %ecx
addl (%rdx), %ecx
movl %ecx, (%r12)
movq %rdx, 8(%r12)
movq %rax, 16(%r12)
movss %xmm0, 24(%r12)
movss %xmm2, 28(%r12)
movss %xmm1, 32(%r12)
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
movslq %ebp, %rbp
movq %r12, 80(%rsp,%rbp,8)
subl $1, %r13d
je .L64
.L36:
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L37:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L66
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L39:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L68
movl $2, %ecx
movl $4, %edx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L69
movl $2, %ecx
movl $4, %edx
movq 48(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L70
movss (%r15), %xmm4
movss %xmm4, 12(%rsp)
movl (%r14), %ebp
movslq %ebp, %rbx
imulq $-1840700269, %rbx, %rbx
shrq $32, %rbx
addl %ebp, %ebx
sarl $2, %ebx
movl %ebp, %eax
sarl $31, %eax
subl %eax, %ebx
leal 0(,%rbx,8), %eax
subl %ebx, %eax
subl %eax, %ebp
cmpl %ebp, %ebx
jg .L43
movl %ebp, %eax
movl %ebx, %ebp
movl %eax, %ebx
jmp .L43
.L62:
movslq %ebx, %rax
movq 80(%rsp,%rax,8), %rdx
movslq %ebp, %rax
movq 80(%rsp,%rax,8), %rax
movl (%rdx), %r9d
movl (%rax), %r8d
movl %ebx, %ecx
movl %ebp, %edx
movl $7, %esi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z6updatePfiiiiiPfiiiii
jmp .L44
.L63:
movl $308, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movq %r12, %rdi
call _Z9printTreeP4Tree
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L71
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L72
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L73
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L74
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L75
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call _Z11cleanupTreeP4Tree
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L76
movl $0, %eax
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movl $315, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L72:
movl $316, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
movl $317, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
movl $318, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl $319, %r8d
leaq .LC23(%rip), %rcx
leaq .LC24(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC25(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3928:
.size main, .-main
.section .rodata.str1.1
.LC27:
.string "_Z6updatePfiiiii"
.LC28:
.string "_Z6getMinPfPiiS_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3959:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z6updatePfiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _Z6getMinPfPiiS_S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3959:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1100480512
.align 4
.LC6:
.long 1104674816
.align 4
.LC7:
.long 1090519040
.align 4
.LC8:
.long 1107558400
.align 4
.LC9:
.long 1099956224
.align 4
.LC10:
.long 1095761920
.align 4
.LC11:
.long 1106771968
.align 4
.LC12:
.long 1108344832
.align 4
.LC13:
.long 1065353216
.align 4
.LC14:
.long 1104150528
.align 4
.LC15:
.long 1109655552
.align 4
.LC16:
.long 1107296256
.align 4
.LC17:
.long 1105723392
.align 4
.LC18:
.long 1099431936
.align 4
.LC19:
.long 1096810496
.align 4
.LC20:
.long 1108082688
.align 4
.LC21:
.long 1105199104
.align 4
.LC22:
.long 1094713344
.align 4
.LC26:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "upgma.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__getMinPfPiiS_S0_ # -- Begin function _Z21__device_stub__getMinPfPiiS_S0_
.p2align 4, 0x90
.type _Z21__device_stub__getMinPfPiiS_S0_,@function
_Z21__device_stub__getMinPfPiiS_S0_: # @_Z21__device_stub__getMinPfPiiS_S0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6getMinPfPiiS_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z21__device_stub__getMinPfPiiS_S0_, .Lfunc_end0-_Z21__device_stub__getMinPfPiiS_S0_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__updatePfiiiii # -- Begin function _Z21__device_stub__updatePfiiiii
.p2align 4, 0x90
.type _Z21__device_stub__updatePfiiiii,@function
_Z21__device_stub__updatePfiiiii: # @_Z21__device_stub__updatePfiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6updatePfiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z21__device_stub__updatePfiiiii, .Lfunc_end1-_Z21__device_stub__updatePfiiiii
.cfi_endproc
# -- End function
.globl _Z11cleanupTreeP4Tree # -- Begin function _Z11cleanupTreeP4Tree
.p2align 4, 0x90
.type _Z11cleanupTreeP4Tree,@function
_Z11cleanupTreeP4Tree: # @_Z11cleanupTreeP4Tree
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
callq _Z11cleanupTreeP4Tree
movq 16(%rbx), %rbx
.LBB2_1: # %tailrecurse
# =>This Inner Loop Header: Depth=1
movq 8(%rbx), %rdi
testq %rdi, %rdi
jne .LBB2_5
# %bb.2: # in Loop: Header=BB2_1 Depth=1
cmpq $0, 16(%rbx)
jne .LBB2_5
# %bb.3:
testq %rbx, %rbx
je .LBB2_6
# %bb.4:
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB2_6:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11cleanupTreeP4Tree, .Lfunc_end2-_Z11cleanupTreeP4Tree
.cfi_endproc
# -- End function
.globl _Z9printTreeP4Tree # -- Begin function _Z9printTreeP4Tree
.p2align 4, 0x90
.type _Z9printTreeP4Tree,@function
_Z9printTreeP4Tree: # @_Z9printTreeP4Tree
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
cmpq $0, 8(%rdi)
jne .LBB3_3
# %bb.1:
cmpq $0, 16(%rbx)
je .LBB3_2
.LBB3_3:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rbx), %rdi
callq _Z9printTreeP4Tree
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 28(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rbx), %rdi
callq _Z9printTreeP4Tree
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.LBB3_2: # %common.ret
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9printTreeP4Tree, .Lfunc_end3-_Z9printTreeP4Tree
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 528
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 272(%rsp), %rdi
movl $.L__const.main.h_a, %esi
movl $196, %edx
callq memcpy@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $40, %edi
callq _Znwm
movl $1, (%rax)
xorps %xmm0, %xmm0
movups %xmm0, 8(%rax)
movups %xmm0, 20(%rax)
movq %rax, 208(%rsp,%rbx,8)
incq %rbx
cmpq $7, %rbx
jne .LBB4_1
# %bb.2:
movl $4, %edi
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %rbp
leaq 96(%rsp), %rdi
movl $196, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_3
# %bb.6:
leaq 128(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_7
# %bb.8:
leaq 112(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_9
# %bb.10:
leaq 120(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_11
# %bb.12:
leaq 104(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.14:
movq 96(%rsp), %rdi
leaq 272(%rsp), %rsi
movl $196, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_20
# %bb.15: # %.preheader
movl $8, %ebx
movabsq $4294967424, %rax # imm = 0x100000080
leaq -127(%rax), %r15
addq $-121, %rax
movq %rax, 200(%rsp) # 8-byte Spill
movq %r14, 192(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_16: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_18
# %bb.17: # in Loop: Header=BB4_16 Depth=1
movq 96(%rsp), %rax
movq 128(%rsp), %rcx
movq 112(%rsp), %rdx
movq %rax, 88(%rsp)
movq $0, 48(%rsp)
movl $49, 12(%rsp)
movq %rcx, 40(%rsp)
movq %rdx, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6getMinPfPiiS_S0_, %edi
leaq 144(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_18: # in Loop: Header=BB4_16 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_19
# %bb.21: # in Loop: Header=BB4_16 Depth=1
movq %r15, %rdi
movl $1, %esi
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22: # in Loop: Header=BB4_16 Depth=1
movq 128(%rsp), %rax
movq 112(%rsp), %rcx
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq %rax, 88(%rsp)
movq %rcx, 48(%rsp)
movl $1, 12(%rsp)
movq %rdx, 40(%rsp)
movq %rsi, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 32(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6getMinPfPiiS_S0_, %edi
leaq 144(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23: # in Loop: Header=BB4_16 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_24
# %bb.25: # in Loop: Header=BB4_16 Depth=1
movq 120(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_26
# %bb.27: # in Loop: Header=BB4_16 Depth=1
movq 104(%rsp), %rsi
movl $4, %edx
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_28
# %bb.29: # in Loop: Header=BB4_16 Depth=1
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 136(%rsp) # 4-byte Spill
movq %rbp, %r12
movslq (%rbp), %rax
imulq $-1840700269, %rax, %rcx # imm = 0x92492493
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $2, %ecx
addl %edx, %ecx
leal (,%rcx,8), %edx
movl %ecx, %ebp
subl %edx, %ebp
addl %eax, %ebp
cmpl %ebp, %ecx
movl %ebp, %r13d
cmovgl %ecx, %r13d
cmovll %ecx, %ebp
movq 200(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967424, %rdx # imm = 0x100000080
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
movslq %ebp, %r14
movslq %r13d, %rbp
testl %eax, %eax
jne .LBB4_31
# %bb.30: # in Loop: Header=BB4_16 Depth=1
movq 96(%rsp), %rax
movq 208(%rsp,%r14,8), %rcx
movl (%rcx), %ecx
movq 208(%rsp,%rbp,8), %rdx
movl (%rdx), %edx
movq %rax, 88(%rsp)
movl $7, 32(%rsp)
movl %r14d, 24(%rsp)
movl %ebp, 16(%rsp)
movl %ecx, 12(%rsp)
movl %edx, 140(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 140(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z6updatePfiiiii, %edi
leaq 144(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31: # in Loop: Header=BB4_16 Depth=1
movl $40, %edi
callq _Znwm
movq %rax, %r13
movq 208(%rsp,%r14,8), %rax
movq 208(%rsp,%rbp,8), %rcx
movl (%rcx), %edx
addl (%rax), %edx
movss 136(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
mulss .LCPI4_0(%rip), %xmm2
movaps %xmm2, %xmm0
subss 24(%rax), %xmm0
movaps %xmm2, %xmm1
subss 24(%rcx), %xmm1
movl %edx, (%r13)
movq %rax, 8(%r13)
movq %rcx, 16(%r13)
movss %xmm2, 24(%r13)
movss %xmm0, 28(%r13)
movss %xmm1, 32(%r13)
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_32
# %bb.33: # in Loop: Header=BB4_16 Depth=1
movq %r13, 208(%rsp,%r14,8)
decl %ebx
cmpl $2, %ebx
movq 192(%rsp), %r14 # 8-byte Reload
movq %r12, %rbp
ja .LBB4_16
# %bb.34:
movq %r13, %rdi
callq _Z9printTreeP4Tree
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_35
# %bb.36:
movq 128(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_37
# %bb.38:
movq 112(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_39
# %bb.40:
movq 120(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_41
# %bb.42:
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_43
# %bb.44:
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r13, %rdi
callq _Z11cleanupTreeP4Tree
xorl %eax, %eax
addq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_32:
.cfi_def_cfa_offset 528
movl %eax, %ebp
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $308, %ecx # imm = 0x134
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %rbx, %rdi
movl %ebp, %edx
jmp .LBB4_5
.LBB4_28:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $283, %ecx # imm = 0x11B
jmp .LBB4_4
.LBB4_26:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $281, %ecx # imm = 0x119
jmp .LBB4_4
.LBB4_24:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $278, %ecx # imm = 0x116
jmp .LBB4_4
.LBB4_19:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $273, %ecx # imm = 0x111
.LBB4_4:
movl %eax, %ebx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %r14
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movq %r14, %rdi
movl %ebx, %edx
.LBB4_5:
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_3:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $259, %ecx # imm = 0x103
jmp .LBB4_4
.LBB4_7:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $260, %ecx # imm = 0x104
jmp .LBB4_4
.LBB4_9:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $261, %ecx # imm = 0x105
jmp .LBB4_4
.LBB4_11:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $262, %ecx # imm = 0x106
jmp .LBB4_4
.LBB4_13:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $263, %ecx # imm = 0x107
jmp .LBB4_4
.LBB4_20:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $265, %ecx # imm = 0x109
jmp .LBB4_4
.LBB4_35:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $315, %ecx # imm = 0x13B
jmp .LBB4_4
.LBB4_37:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $316, %ecx # imm = 0x13C
jmp .LBB4_4
.LBB4_39:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $317, %ecx # imm = 0x13D
jmp .LBB4_4
.LBB4_41:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $318, %ecx # imm = 0x13E
jmp .LBB4_4
.LBB4_43:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $.L.str.5, %edx
movl $319, %ecx # imm = 0x13F
jmp .LBB4_4
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6getMinPfPiiS_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6updatePfiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6getMinPfPiiS_S0_,@object # @_Z6getMinPfPiiS_S0_
.section .rodata,"a",@progbits
.globl _Z6getMinPfPiiS_S0_
.p2align 3, 0x0
_Z6getMinPfPiiS_S0_:
.quad _Z21__device_stub__getMinPfPiiS_S0_
.size _Z6getMinPfPiiS_S0_, 8
.type _Z6updatePfiiiii,@object # @_Z6updatePfiiiii
.globl _Z6updatePfiiiii
.p2align 3, 0x0
_Z6updatePfiiiii:
.quad _Z21__device_stub__updatePfiiiii
.size _Z6updatePfiiiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "("
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type .L__const.main.h_a,@object # @__const.main.h_a
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.h_a:
.long 0x00000000 # float 0
.long 0x41980000 # float 19
.long 0x41d80000 # float 27
.long 0x41000000 # float 8
.long 0x42040000 # float 33
.long 0x41900000 # float 18
.long 0x41500000 # float 13
.long 0x41980000 # float 19
.long 0x00000000 # float 0
.long 0x41f80000 # float 31
.long 0x41900000 # float 18
.long 0x42100000 # float 36
.long 0x3f800000 # float 1
.long 0x41500000 # float 13
.long 0x41d80000 # float 27
.long 0x41f80000 # float 31
.long 0x00000000 # float 0
.long 0x41d00000 # float 26
.long 0x42240000 # float 41
.long 0x42000000 # float 32
.long 0x41e80000 # float 29
.long 0x41000000 # float 8
.long 0x41900000 # float 18
.long 0x41d00000 # float 26
.long 0x00000000 # float 0
.long 0x41f80000 # float 31
.long 0x41880000 # float 17
.long 0x41600000 # float 14
.long 0x42040000 # float 33
.long 0x42100000 # float 36
.long 0x42240000 # float 41
.long 0x41f80000 # float 31
.long 0x00000000 # float 0
.long 0x420c0000 # float 35
.long 0x41e00000 # float 28
.long 0x41900000 # float 18
.long 0x3f800000 # float 1
.long 0x42000000 # float 32
.long 0x41880000 # float 17
.long 0x420c0000 # float 35
.long 0x00000000 # float 0
.long 0x41400000 # float 12
.long 0x41500000 # float 13
.long 0x41500000 # float 13
.long 0x41e80000 # float 29
.long 0x41600000 # float 14
.long 0x41e00000 # float 28
.long 0x41400000 # float 12
.long 0x00000000 # float 0
.size .L__const.main.h_a, 196
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Error: %s:%d, "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/hle46/UPGMA/master/gpu/upgma.hip"
.size .L.str.5, 90
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "code: %d, reason: %s\n"
.size .L.str.6, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6getMinPfPiiS_S0_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6updatePfiiiii"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__getMinPfPiiS_S0_
.addrsig_sym _Z21__device_stub__updatePfiiiii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6getMinPfPiiS_S0_
.addrsig_sym _Z6updatePfiiiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<iostream>
__constant__ float M[10];
int main(){
float h_M[]={1,2,3,4,5,7,8,9,0};
cudaMemcpyToSymbol(M,h_M,10*sizeof(float));
std::cout<< "yo"<<std::endl;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<iostream>
__constant__ float M[10];
int main(){
float h_M[]={1,2,3,4,5,7,8,9,0};
cudaMemcpyToSymbol(M,h_M,10*sizeof(float));
std::cout<< "yo"<<std::endl;
}
|
.file "tmpxft_001894d1_00000000-6_cmemtest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "yo"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x3f800000, (%rsp)
movl $0x40000000, 4(%rsp)
movl $0x40400000, 8(%rsp)
movl $0x40800000, 12(%rsp)
movl $0x40a00000, 16(%rsp)
movl $0x40e00000, 20(%rsp)
movl $0x41000000, 24(%rsp)
movl $0x41100000, 28(%rsp)
movl $0x00000000, 32(%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $40, %edx
leaq _ZL1M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $40, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1M(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1M
.comm _ZL1M,40,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<iostream>
__constant__ float M[10];
int main(){
float h_M[]={1,2,3,4,5,7,8,9,0};
cudaMemcpyToSymbol(M,h_M,10*sizeof(float));
std::cout<< "yo"<<std::endl;
}
|
#include <hip/hip_runtime.h>
#include<iostream>
__constant__ float M[10];
int main(){
float h_M[]={1,2,3,4,5,7,8,9,0};
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,10*sizeof(float));
std::cout<< "yo"<<std::endl;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<iostream>
__constant__ float M[10];
int main(){
float h_M[]={1,2,3,4,5,7,8,9,0};
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,10*sizeof(float));
std::cout<< "yo"<<std::endl;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected M
.type M,@object
.section .bss,"aw",@nobits
.globl M
.p2align 4, 0x0
M:
.zero 40
.size M, 40
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym M
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<iostream>
__constant__ float M[10];
int main(){
float h_M[]={1,2,3,4,5,7,8,9,0};
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,10*sizeof(float));
std::cout<< "yo"<<std::endl;
}
|
.text
.file "cmemtest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI0_1:
.long 0x40a00000 # float 5
.long 0x40e00000 # float 7
.long 0x41000000 # float 8
.long 0x41100000 # float 9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $48, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, (%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [5.0E+0,7.0E+0,8.0E+0,9.0E+0]
movaps %xmm0, 16(%rsp)
movl $0, 32(%rsp)
movq %rsp, %rsi
movl $M, %edi
movl $40, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $M, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $40, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.local M
.comm M,40,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "yo"
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "M"
.size .L__unnamed_1, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected M
.type M,@object
.section .bss,"aw",@nobits
.globl M
.p2align 4, 0x0
M:
.zero 40
.size M, 40
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym M
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001894d1_00000000-6_cmemtest.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "yo"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0x3f800000, (%rsp)
movl $0x40000000, 4(%rsp)
movl $0x40400000, 8(%rsp)
movl $0x40800000, 12(%rsp)
movl $0x40a00000, 16(%rsp)
movl $0x40e00000, 20(%rsp)
movl $0x41000000, 24(%rsp)
movl $0x41100000, 28(%rsp)
movl $0x00000000, 32(%rsp)
movq %rsp, %rsi
movl $1, %r8d
movl $0, %ecx
movl $40, %edx
leaq _ZL1M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $40, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1M(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1M
.comm _ZL1M,40,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cmemtest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI0_1:
.long 0x40a00000 # float 5
.long 0x40e00000 # float 7
.long 0x41000000 # float 8
.long 0x41100000 # float 9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $48, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -16
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, (%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [5.0E+0,7.0E+0,8.0E+0,9.0E+0]
movaps %xmm0, 16(%rsp)
movl $0, 32(%rsp)
movq %rsp, %rsi
movl $M, %edi
movl $40, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $M, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $40, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.local M
.comm M,40,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "yo"
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "M"
.size .L__unnamed_1, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define N 10 // ( N )x( N ) matrix containing data
// The idea with an aligned array is that the GPU will perform better if you pad
// it's data array so that it can fit better in cache. CUDA accomplishes this
// with the cudaMallocPitch() call. pitch (of type size_t) is the number of bytes
// per row in the array on the device. This is equivilent to
// sizeof(arraytype)*(columns + paddingColumns) OR sizeof(arraytype)*numDeviceColumns
//
// This does mean that care must be taken when copying data to and from the device
// because the array is no longer completely linear (it has padding).
// CUDA offers a convenience function called cudaMemcpy2D() which allows you to specify
// the array rows/cols as well as the pitch for the source and the destination
__global__ void kernel(float *A, float *B, int devWidth)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
int o = i+devWidth*j;
B[o] = A[o];
//B[o] = o; // uncomment to print the indexes
}
void print(float *A, int nx, int ny)
{
for (int j = 0; j < ny; j++) {
for (int i = 0; i < nx; i++) {
printf("%4.0f ",A[i+nx*j]);
}
printf("\n");
}
printf("\n");
}
int main(int argc, char * argv[])
{
// Allocate on host
float *h_A, *h_B;
float *d_A, *d_B;
h_A = (float*)malloc(sizeof(float)*N*N);
h_B = (float*)malloc(sizeof(float)*N*N);
size_t h_pitch=sizeof(float)*N;
// Initialize Array h_A
for (int i = 0; i < N*N; i++) h_A[i]=i; //h_A[i]=0; <-- use to print the padded indexes
// Allocate pictched memory for padded arrays d_A and d_B
size_t d_pitch; // actual number of columns in the device array
cudaMallocPitch((void**)&d_A,&d_pitch,sizeof(float)*N,N);
cudaMallocPitch((void**)&d_B,&d_pitch,sizeof(float)*N,N);
int devWidth = d_pitch/sizeof(float);
// Copy memory from unpadded array A to padded array B
cudaMemcpy2D(d_A,d_pitch,h_A,h_pitch,sizeof(float)*N,N,cudaMemcpyHostToDevice);
dim3 threads = dim3(16,16);
dim3 blocks = dim3((N+16-1)/16,(N+16-1)/16);
kernel<<<blocks,threads>>>(d_A,d_B,devWidth);
// Copy memory from padded array B to unpadded array A
cudaMemcpy2D(h_B,h_pitch,d_B,d_pitch,sizeof(float)*N,N,cudaMemcpyDeviceToHost);
// Are they the same?
print(h_A,N,N);
print(h_B,N,N);
// Release Arrays
cudaFree(d_A);
cudaFree(d_B);
free(h_A);
free(h_B);
}
|
code for sm_80
Function : _Z6kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fce00078e0200 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
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