system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mSetFieldBoundary(float *field, float scalar) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
if(x == 0 && y == 0) {
field[Idx] = field[Idx+blockDim.x+1]*scalar;
} else if(x == 0 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x+1]*scalar;
} else if (x == blockDim.x-1 && y == 0) {
field[Idx] = field[Idx+blockDim.x-1]*scalar;
} else if (x == blockDim.x-1 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x-1]*scalar;
} else if (x == 0) {
field[Idx] = field[Idx+1]*scalar;
} else if(x == blockDim.x-1) {
field[Idx] = field[Idx-1]*scalar;
} else if(y == 0) {
field[Idx] = field[Idx+blockDim.x]*scalar;
} else field[Idx] = field[Idx-blockDim.x]*scalar;
} else return;
}
|
.file "tmpxft_0009ff70_00000000-6_mSetFieldBoundary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13checkBoundaryiii
.type _Z13checkBoundaryiii, @function
_Z13checkBoundaryiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13checkBoundaryiii, .-_Z13checkBoundaryiii
.globl _Z38__device_stub__Z17mSetFieldBoundaryPffPff
.type _Z38__device_stub__Z17mSetFieldBoundaryPffPff, @function
_Z38__device_stub__Z17mSetFieldBoundaryPffPff:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17mSetFieldBoundaryPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z17mSetFieldBoundaryPffPff, .-_Z38__device_stub__Z17mSetFieldBoundaryPffPff
.globl _Z17mSetFieldBoundaryPff
.type _Z17mSetFieldBoundaryPff, @function
_Z17mSetFieldBoundaryPff:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17mSetFieldBoundaryPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17mSetFieldBoundaryPff, .-_Z17mSetFieldBoundaryPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17mSetFieldBoundaryPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17mSetFieldBoundaryPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mSetFieldBoundary(float *field, float scalar) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
if(x == 0 && y == 0) {
field[Idx] = field[Idx+blockDim.x+1]*scalar;
} else if(x == 0 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x+1]*scalar;
} else if (x == blockDim.x-1 && y == 0) {
field[Idx] = field[Idx+blockDim.x-1]*scalar;
} else if (x == blockDim.x-1 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x-1]*scalar;
} else if (x == 0) {
field[Idx] = field[Idx+1]*scalar;
} else if(x == blockDim.x-1) {
field[Idx] = field[Idx-1]*scalar;
} else if(y == 0) {
field[Idx] = field[Idx+blockDim.x]*scalar;
} else field[Idx] = field[Idx-blockDim.x]*scalar;
} else return;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mSetFieldBoundary(float *field, float scalar) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
if(x == 0 && y == 0) {
field[Idx] = field[Idx+blockDim.x+1]*scalar;
} else if(x == 0 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x+1]*scalar;
} else if (x == blockDim.x-1 && y == 0) {
field[Idx] = field[Idx+blockDim.x-1]*scalar;
} else if (x == blockDim.x-1 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x-1]*scalar;
} else if (x == 0) {
field[Idx] = field[Idx+1]*scalar;
} else if(x == blockDim.x-1) {
field[Idx] = field[Idx-1]*scalar;
} else if(y == 0) {
field[Idx] = field[Idx+blockDim.x]*scalar;
} else field[Idx] = field[Idx-blockDim.x]*scalar;
} else return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mSetFieldBoundary(float *field, float scalar) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
if(x == 0 && y == 0) {
field[Idx] = field[Idx+blockDim.x+1]*scalar;
} else if(x == 0 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x+1]*scalar;
} else if (x == blockDim.x-1 && y == 0) {
field[Idx] = field[Idx+blockDim.x-1]*scalar;
} else if (x == blockDim.x-1 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x-1]*scalar;
} else if (x == 0) {
field[Idx] = field[Idx+1]*scalar;
} else if(x == blockDim.x-1) {
field[Idx] = field[Idx-1]*scalar;
} else if(y == 0) {
field[Idx] = field[Idx+blockDim.x]*scalar;
} else field[Idx] = field[Idx-blockDim.x]*scalar;
} else return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17mSetFieldBoundaryPff
.globl _Z17mSetFieldBoundaryPff
.p2align 8
.type _Z17mSetFieldBoundaryPff,@function
_Z17mSetFieldBoundaryPff:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s5, -1
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
v_cmp_ne_u32_e64 s2, 0, v0
s_add_i32 s3, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, s3, v0
v_cmp_eq_u32_e64 s3, 0, v0
s_and_b32 s7, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s7
s_cbranch_execz .LBB0_6
s_cmpk_lt_i32 s15, 0x1df
s_cbranch_scc1 .LBB0_3
s_cmpk_eq_i32 s15, 0x1df
s_cselect_b32 s5, -1, 0
s_cbranch_execz .LBB0_4
s_branch .LBB0_5
.LBB0_3:
s_mov_b32 s5, 0
.LBB0_4:
s_cmp_eq_u32 s15, 0
s_cselect_b32 s5, -1, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s5, s5, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_34
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_or_b32_e32 v3, s15, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v3
s_xor_b32 s7, exec_lo, s0
s_cbranch_execz .LBB0_32
s_add_i32 s9, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s9
s_cselect_b32 s0, -1, 0
s_xor_b32 s3, s3, -1
s_or_b32 s0, s3, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_29
v_cmp_ne_u32_e32 vcc_lo, s9, v0
s_cmp_lg_u32 s15, 0
v_cmp_eq_u32_e64 s0, s9, v0
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s10, vcc_lo
s_and_saveexec_b32 s11, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s11
s_cbranch_execz .LBB0_26
s_cmp_lg_u32 s15, s9
s_cselect_b32 s9, -1, 0
s_xor_b32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s9
s_and_saveexec_b32 s9, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s9
s_cbranch_execz .LBB0_23
s_and_saveexec_b32 s9, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s9
s_cbranch_execz .LBB0_20
s_and_saveexec_b32 s9, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_17
s_and_b32 vcc_lo, exec_lo, s10
s_mov_b32 s10, -1
s_cbranch_vccz .LBB0_15
v_subrev_nc_u32_e32 v2, s6, v1
v_mov_b32_e32 v3, 0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s1, v0
global_store_b32 v[2:3], v0, off
.LBB0_15:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_17
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v4
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_and_not1_saveexec_b32 s9, s9
s_cbranch_execz .LBB0_19
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off offset:-4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_20:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_22
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off offset:4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_23:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_25
v_xad_u32 v2, s6, -1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_26:
s_and_not1_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_28
v_add3_u32 v2, s6, -1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_29:
s_and_not1_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_31
v_subrev_nc_u32_e32 v0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 1, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_32:
s_and_not1_saveexec_b32 s0, s7
s_cbranch_execz .LBB0_34
v_add3_u32 v2, s6, 1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_34:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17mSetFieldBoundaryPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17mSetFieldBoundaryPff, .Lfunc_end0-_Z17mSetFieldBoundaryPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17mSetFieldBoundaryPff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17mSetFieldBoundaryPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mSetFieldBoundary(float *field, float scalar) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) {
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int x = threadIdx.x;
int y = blockIdx.x;
if(x == 0 && y == 0) {
field[Idx] = field[Idx+blockDim.x+1]*scalar;
} else if(x == 0 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x+1]*scalar;
} else if (x == blockDim.x-1 && y == 0) {
field[Idx] = field[Idx+blockDim.x-1]*scalar;
} else if (x == blockDim.x-1 && y == blockDim.x-1) {
field[Idx] = field[Idx-blockDim.x-1]*scalar;
} else if (x == 0) {
field[Idx] = field[Idx+1]*scalar;
} else if(x == blockDim.x-1) {
field[Idx] = field[Idx-1]*scalar;
} else if(y == 0) {
field[Idx] = field[Idx+blockDim.x]*scalar;
} else field[Idx] = field[Idx-blockDim.x]*scalar;
} else return;
}
|
.text
.file "mSetFieldBoundary.hip"
.globl _Z32__device_stub__mSetFieldBoundaryPff # -- Begin function _Z32__device_stub__mSetFieldBoundaryPff
.p2align 4, 0x90
.type _Z32__device_stub__mSetFieldBoundaryPff,@function
_Z32__device_stub__mSetFieldBoundaryPff: # @_Z32__device_stub__mSetFieldBoundaryPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17mSetFieldBoundaryPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__mSetFieldBoundaryPff, .Lfunc_end0-_Z32__device_stub__mSetFieldBoundaryPff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17mSetFieldBoundaryPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17mSetFieldBoundaryPff,@object # @_Z17mSetFieldBoundaryPff
.section .rodata,"a",@progbits
.globl _Z17mSetFieldBoundaryPff
.p2align 3, 0x0
_Z17mSetFieldBoundaryPff:
.quad _Z32__device_stub__mSetFieldBoundaryPff
.size _Z17mSetFieldBoundaryPff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17mSetFieldBoundaryPff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__mSetFieldBoundaryPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17mSetFieldBoundaryPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z17mSetFieldBoundaryPff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e6a0000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x001fc8000bf05270 */
/*0060*/ ISETP.NE.AND P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fe40000705270 */
/*0070*/ ISETP.NE.AND P1, PT, R4.reuse, 0x1df, PT ; /* 0x000001df0400780c */
/* 0x042fe40003f25270 */
/*0080*/ ISETP.NE.AND P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705270 */
/*0090*/ @P0 EXIT P1 ; /* 0x000000000000094d */
/* 0x000fea0000800000 */
/*00a0*/ LOP3.LUT P0, RZ, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405ff7212 */
/* 0x000fe2000780fcff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IMAD R0, R4, c[0x0][0x0], R5 ; /* 0x0000000004007a24 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*00f0*/ @!P0 BRA 0x460 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P1, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fe4000bf25270 */
/*0110*/ ISETP.EQ.AND P2, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe40003f42270 */
/*0120*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fd60003f05270 */
/*0130*/ @!P1 BRA P2, 0x3f0 ; /* 0x000002b000009947 */
/* 0x000fea0001000000 */
/*0140*/ ISETP.EQ.AND P4, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe40003f82270 */
/*0150*/ ISETP.NE.AND P3, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf65270 */
/*0160*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f45270 */
/*0170*/ @!P3 BRA P4, 0x390 ; /* 0x000002100000b947 */
/* 0x000fea0002000000 */
/*0180*/ ISETP.EQ.AND P4, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf82270 */
/*0190*/ @!P1 BRA P4, 0x310 ; /* 0x0000017000009947 */
/* 0x000fea0002000000 */
/*01a0*/ @!P0 BRA 0x2d0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*01b0*/ @!P3 BRA 0x290 ; /* 0x000000d00000b947 */
/* 0x000fea0003800000 */
/*01c0*/ @!P2 BRA 0x230 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R4, R0, -c[0x0][0x0], RZ ; /* 0x8000000000047a10 */
/* 0x000fca0007ffe0ff */
/*01e0*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0200*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R4, R0, c[0x0][0x0], RZ ; /* 0x0000000000047a10 */
/* 0x000fca0007ffe0ff */
/*0240*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0250*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0602007981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ FMUL R5, R0, c[0x0][0x168] ; /* 0x00005a0000057a20 */
/* 0x004fca0000400000 */
/*02b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040602007981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FMUL R5, R0, c[0x0][0x168] ; /* 0x00005a0000057a20 */
/* 0x004fca0000400000 */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0320*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fcc000f8e333f */
/*0330*/ IADD3 R4, R0, UR5, RZ ; /* 0x0000000500047c10 */
/* 0x000fca000fffe0ff */
/*0340*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0350*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0370*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R4, R0, R5, RZ ; /* 0x0000000500047210 */
/* 0x000fca0007ffe0ff */
/*03a0*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*03b0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*03d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R5, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff057435 */
/* 0x000fd400000001ff */
/*0400*/ IADD3 R4, R0, -c[0x0][0x0], R5 ; /* 0x8000000000047a10 */
/* 0x000fca0007ffe005 */
/*0410*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0420*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*0440*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ IADD3.X R4, R0, c[0x0][0x0], RZ, PT, !PT ; /* 0x0000000000047a10 */
/* 0x000fca0003ffe4ff */
/*0470*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0007 */
/*0480*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0490*/ FMUL R7, R4, c[0x0][0x168] ; /* 0x00005a0004077a20 */
/* 0x004fca0000400000 */
/*04a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101906 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17mSetFieldBoundaryPff
.globl _Z17mSetFieldBoundaryPff
.p2align 8
.type _Z17mSetFieldBoundaryPff,@function
_Z17mSetFieldBoundaryPff:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s5, -1
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
v_cmp_ne_u32_e64 s2, 0, v0
s_add_i32 s3, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, s3, v0
v_cmp_eq_u32_e64 s3, 0, v0
s_and_b32 s7, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s7
s_cbranch_execz .LBB0_6
s_cmpk_lt_i32 s15, 0x1df
s_cbranch_scc1 .LBB0_3
s_cmpk_eq_i32 s15, 0x1df
s_cselect_b32 s5, -1, 0
s_cbranch_execz .LBB0_4
s_branch .LBB0_5
.LBB0_3:
s_mov_b32 s5, 0
.LBB0_4:
s_cmp_eq_u32 s15, 0
s_cselect_b32 s5, -1, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s5, s5, exec_lo
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_34
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_or_b32_e32 v3, s15, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v3
s_xor_b32 s7, exec_lo, s0
s_cbranch_execz .LBB0_32
s_add_i32 s9, s6, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s15, s9
s_cselect_b32 s0, -1, 0
s_xor_b32 s3, s3, -1
s_or_b32 s0, s3, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_29
v_cmp_ne_u32_e32 vcc_lo, s9, v0
s_cmp_lg_u32 s15, 0
v_cmp_eq_u32_e64 s0, s9, v0
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s10, vcc_lo
s_and_saveexec_b32 s11, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s11
s_cbranch_execz .LBB0_26
s_cmp_lg_u32 s15, s9
s_cselect_b32 s9, -1, 0
s_xor_b32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s9
s_and_saveexec_b32 s9, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s9
s_cbranch_execz .LBB0_23
s_and_saveexec_b32 s9, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s9
s_cbranch_execz .LBB0_20
s_and_saveexec_b32 s9, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s9, exec_lo, s9
s_cbranch_execz .LBB0_17
s_and_b32 vcc_lo, exec_lo, s10
s_mov_b32 s10, -1
s_cbranch_vccz .LBB0_15
v_subrev_nc_u32_e32 v2, s6, v1
v_mov_b32_e32 v3, 0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, s1, v0
global_store_b32 v[2:3], v0, off
.LBB0_15:
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_17
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v4
global_store_b32 v[0:1], v2, off
.LBB0_17:
s_and_not1_saveexec_b32 s9, s9
s_cbranch_execz .LBB0_19
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off offset:-4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_20:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_22
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off offset:4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
global_store_b32 v[0:1], v2, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_23:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_25
v_xad_u32 v2, s6, -1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_26:
s_and_not1_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_28
v_add3_u32 v2, s6, -1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_29:
s_and_not1_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_31
v_subrev_nc_u32_e32 v0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 1, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_32:
s_and_not1_saveexec_b32 s0, s7
s_cbranch_execz .LBB0_34
v_add3_u32 v2, s6, 1, v1
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v3
global_store_b32 v[0:1], v2, off
.LBB0_34:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17mSetFieldBoundaryPff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17mSetFieldBoundaryPff, .Lfunc_end0-_Z17mSetFieldBoundaryPff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17mSetFieldBoundaryPff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17mSetFieldBoundaryPff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0009ff70_00000000-6_mSetFieldBoundary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13checkBoundaryiii
.type _Z13checkBoundaryiii, @function
_Z13checkBoundaryiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13checkBoundaryiii, .-_Z13checkBoundaryiii
.globl _Z38__device_stub__Z17mSetFieldBoundaryPffPff
.type _Z38__device_stub__Z17mSetFieldBoundaryPffPff, @function
_Z38__device_stub__Z17mSetFieldBoundaryPffPff:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17mSetFieldBoundaryPff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z38__device_stub__Z17mSetFieldBoundaryPffPff, .-_Z38__device_stub__Z17mSetFieldBoundaryPffPff
.globl _Z17mSetFieldBoundaryPff
.type _Z17mSetFieldBoundaryPff, @function
_Z17mSetFieldBoundaryPff:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17mSetFieldBoundaryPffPff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17mSetFieldBoundaryPff, .-_Z17mSetFieldBoundaryPff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17mSetFieldBoundaryPff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17mSetFieldBoundaryPff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "mSetFieldBoundary.hip"
.globl _Z32__device_stub__mSetFieldBoundaryPff # -- Begin function _Z32__device_stub__mSetFieldBoundaryPff
.p2align 4, 0x90
.type _Z32__device_stub__mSetFieldBoundaryPff,@function
_Z32__device_stub__mSetFieldBoundaryPff: # @_Z32__device_stub__mSetFieldBoundaryPff
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17mSetFieldBoundaryPff, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__mSetFieldBoundaryPff, .Lfunc_end0-_Z32__device_stub__mSetFieldBoundaryPff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17mSetFieldBoundaryPff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17mSetFieldBoundaryPff,@object # @_Z17mSetFieldBoundaryPff
.section .rodata,"a",@progbits
.globl _Z17mSetFieldBoundaryPff
.p2align 3, 0x0
_Z17mSetFieldBoundaryPff:
.quad _Z32__device_stub__mSetFieldBoundaryPff
.size _Z17mSetFieldBoundaryPff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17mSetFieldBoundaryPff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__mSetFieldBoundaryPff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17mSetFieldBoundaryPff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<cuda.h>
#include<stdio.h>
#include<math.h>
#define TILE_WIDTH 32
/**
* This is a kernel MatrixMul function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel(float* A,
float* B,
float* C,
int m,
int n,
int dim){
__shared__ float Ads[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
// Calculate the number of phase
int phase_num = ceil(dim / (float)TILE_WIDTH);
bool cond0 = Row < m;
bool cond1 = Col < n;
float Cvalue = 0;
// Each thread loads 'Row'th row of A and 'Col'th column of B
for (int ph = 0; ph < phase_num; ++ph) {
if(ph * TILE_WIDTH + tx < dim){
Ads[ty][tx] = (cond0)?A[Row * dim + ph*TILE_WIDTH + tx]:0;
}
else{
Ads[ty][tx] = 0;
}
if(ph * TILE_WIDTH + ty < dim){
Bds[ty][tx] = (cond1)?B[(ph*TILE_WIDTH + ty)*n + Col]:0;
}
else{
Bds[ty][tx] = 0;
}
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Cvalue += Ads[ty][k] * Bds[k][tx];
}
__syncthreads();
}
if(cond0 && cond1){
C[Row * n + Col] = Cvalue;
}
}
/**
* This is a parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
cudaMalloc((void**)&d_A, size_A);
cudaMalloc((void**)&d_B, size_B);
cudaMalloc((void**)&d_C, size_C);
cudaMemcpy(d_A, h_A, size_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size_B, cudaMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
cudaMemcpy(h_C, d_C, size_C, cudaMemcpyDeviceToHost);
// Free device memory for A, B, C
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
/**
* This is a baseline kernel function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel_Baseline(float* A,
float* B,
float* C,
int m,
int n,
int dim){
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
bool cond0 = Row < m;
bool cond1 = Col < n;
if(cond0 && cond1){
float Cvalue = 0;
for(int i = 0;i<dim;i++){
Cvalue += A[Row*dim+i]*B[i*n+Col];
}
C[Row*n+Col] = Cvalue;
}
}
/**
* This is a baseline Parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul_baseline(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
cudaMalloc((void**)&d_A, size_A);
cudaMalloc((void**)&d_B, size_B);
cudaMalloc((void**)&d_C, size_C);
cudaMemcpy(d_A, h_A, size_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size_B, cudaMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel_Baseline<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
cudaMemcpy(h_C, d_C, size_C, cudaMemcpyDeviceToHost);
// Free device memory for A, B, C
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("The baseline Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
|
.file "tmpxft_000abf50_00000000-6_MatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.type _Z15MatrixMulKernelPfS_S_iii, @function
_Z15MatrixMulKernelPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15MatrixMulKernelPfS_S_iii, .-_Z15MatrixMulKernelPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Parallel invoke Matmul function need %.1fs.\n"
.text
.globl _Z14parallelMatMulPfS_S_iii
.type _Z14parallelMatMulPfS_S_iii, @function
_Z14parallelMatMulPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0x00000000, 36(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L13
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L13:
cvttss2siq %xmm4, %rax
movl %eax, 80(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 84(%rsp)
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14parallelMatMulPfS_S_iii, .-_Z14parallelMatMulPfS_S_iii
.globl _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
.type _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii, @function
_Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24MatrixMulKernel_BaselinePfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii, .-_Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
.globl _Z24MatrixMulKernel_BaselinePfS_S_iii
.type _Z24MatrixMulKernel_BaselinePfS_S_iii, @function
_Z24MatrixMulKernel_BaselinePfS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z24MatrixMulKernel_BaselinePfS_S_iii, .-_Z24MatrixMulKernel_BaselinePfS_S_iii
.section .rodata.str1.8
.align 8
.LC7:
.string "The baseline Parallel invoke Matmul function need %.1fs.\n"
.text
.globl _Z23parallelMatMul_baselinePfS_S_iii
.type _Z23parallelMatMul_baselinePfS_S_iii, @function
_Z23parallelMatMul_baselinePfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0x00000000, 36(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L28
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L28:
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L29
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L29:
cvttss2siq %xmm4, %rax
movl %eax, 80(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 84(%rsp)
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L30:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
jmp .L30
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z23parallelMatMul_baselinePfS_S_iii, .-_Z23parallelMatMul_baselinePfS_S_iii
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z24MatrixMulKernel_BaselinePfS_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "_Z15MatrixMulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z24MatrixMulKernel_BaselinePfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1023410176
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<cuda.h>
#include<stdio.h>
#include<math.h>
#define TILE_WIDTH 32
/**
* This is a kernel MatrixMul function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel(float* A,
float* B,
float* C,
int m,
int n,
int dim){
__shared__ float Ads[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
// Calculate the number of phase
int phase_num = ceil(dim / (float)TILE_WIDTH);
bool cond0 = Row < m;
bool cond1 = Col < n;
float Cvalue = 0;
// Each thread loads 'Row'th row of A and 'Col'th column of B
for (int ph = 0; ph < phase_num; ++ph) {
if(ph * TILE_WIDTH + tx < dim){
Ads[ty][tx] = (cond0)?A[Row * dim + ph*TILE_WIDTH + tx]:0;
}
else{
Ads[ty][tx] = 0;
}
if(ph * TILE_WIDTH + ty < dim){
Bds[ty][tx] = (cond1)?B[(ph*TILE_WIDTH + ty)*n + Col]:0;
}
else{
Bds[ty][tx] = 0;
}
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Cvalue += Ads[ty][k] * Bds[k][tx];
}
__syncthreads();
}
if(cond0 && cond1){
C[Row * n + Col] = Cvalue;
}
}
/**
* This is a parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
cudaMalloc((void**)&d_A, size_A);
cudaMalloc((void**)&d_B, size_B);
cudaMalloc((void**)&d_C, size_C);
cudaMemcpy(d_A, h_A, size_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size_B, cudaMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
cudaMemcpy(h_C, d_C, size_C, cudaMemcpyDeviceToHost);
// Free device memory for A, B, C
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
/**
* This is a baseline kernel function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel_Baseline(float* A,
float* B,
float* C,
int m,
int n,
int dim){
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
bool cond0 = Row < m;
bool cond1 = Col < n;
if(cond0 && cond1){
float Cvalue = 0;
for(int i = 0;i<dim;i++){
Cvalue += A[Row*dim+i]*B[i*n+Col];
}
C[Row*n+Col] = Cvalue;
}
}
/**
* This is a baseline Parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul_baseline(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
cudaMalloc((void**)&d_A, size_A);
cudaMalloc((void**)&d_B, size_B);
cudaMalloc((void**)&d_C, size_C);
cudaMemcpy(d_A, h_A, size_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size_B, cudaMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel_Baseline<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
cudaMemcpy(h_C, d_C, size_C, cudaMemcpyDeviceToHost);
// Free device memory for A, B, C
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("The baseline Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
|
#include<hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define TILE_WIDTH 32
/**
* This is a kernel MatrixMul function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel(float* A,
float* B,
float* C,
int m,
int n,
int dim){
__shared__ float Ads[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
// Calculate the number of phase
int phase_num = ceil(dim / (float)TILE_WIDTH);
bool cond0 = Row < m;
bool cond1 = Col < n;
float Cvalue = 0;
// Each thread loads 'Row'th row of A and 'Col'th column of B
for (int ph = 0; ph < phase_num; ++ph) {
if(ph * TILE_WIDTH + tx < dim){
Ads[ty][tx] = (cond0)?A[Row * dim + ph*TILE_WIDTH + tx]:0;
}
else{
Ads[ty][tx] = 0;
}
if(ph * TILE_WIDTH + ty < dim){
Bds[ty][tx] = (cond1)?B[(ph*TILE_WIDTH + ty)*n + Col]:0;
}
else{
Bds[ty][tx] = 0;
}
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Cvalue += Ads[ty][k] * Bds[k][tx];
}
__syncthreads();
}
if(cond0 && cond1){
C[Row * n + Col] = Cvalue;
}
}
/**
* This is a parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
hipMalloc((void**)&d_A, size_A);
hipMalloc((void**)&d_B, size_B);
hipMalloc((void**)&d_C, size_C);
hipMemcpy(d_A, h_A, size_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size_B, hipMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
hipMemcpy(h_C, d_C, size_C, hipMemcpyDeviceToHost);
// Free device memory for A, B, C
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
}
/**
* This is a baseline kernel function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel_Baseline(float* A,
float* B,
float* C,
int m,
int n,
int dim){
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
bool cond0 = Row < m;
bool cond1 = Col < n;
if(cond0 && cond1){
float Cvalue = 0;
for(int i = 0;i<dim;i++){
Cvalue += A[Row*dim+i]*B[i*n+Col];
}
C[Row*n+Col] = Cvalue;
}
}
/**
* This is a baseline Parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul_baseline(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
hipMalloc((void**)&d_A, size_A);
hipMalloc((void**)&d_B, size_B);
hipMalloc((void**)&d_C, size_C);
hipMemcpy(d_A, h_A, size_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size_B, hipMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel_Baseline<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
hipMemcpy(h_C, d_C, size_C, hipMemcpyDeviceToHost);
// Free device memory for A, B, C
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
printf("The baseline Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include<hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define TILE_WIDTH 32
/**
* This is a kernel MatrixMul function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel(float* A,
float* B,
float* C,
int m,
int n,
int dim){
__shared__ float Ads[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
// Calculate the number of phase
int phase_num = ceil(dim / (float)TILE_WIDTH);
bool cond0 = Row < m;
bool cond1 = Col < n;
float Cvalue = 0;
// Each thread loads 'Row'th row of A and 'Col'th column of B
for (int ph = 0; ph < phase_num; ++ph) {
if(ph * TILE_WIDTH + tx < dim){
Ads[ty][tx] = (cond0)?A[Row * dim + ph*TILE_WIDTH + tx]:0;
}
else{
Ads[ty][tx] = 0;
}
if(ph * TILE_WIDTH + ty < dim){
Bds[ty][tx] = (cond1)?B[(ph*TILE_WIDTH + ty)*n + Col]:0;
}
else{
Bds[ty][tx] = 0;
}
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Cvalue += Ads[ty][k] * Bds[k][tx];
}
__syncthreads();
}
if(cond0 && cond1){
C[Row * n + Col] = Cvalue;
}
}
/**
* This is a parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
hipMalloc((void**)&d_A, size_A);
hipMalloc((void**)&d_B, size_B);
hipMalloc((void**)&d_C, size_C);
hipMemcpy(d_A, h_A, size_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size_B, hipMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
hipMemcpy(h_C, d_C, size_C, hipMemcpyDeviceToHost);
// Free device memory for A, B, C
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
}
/**
* This is a baseline kernel function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel_Baseline(float* A,
float* B,
float* C,
int m,
int n,
int dim){
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
bool cond0 = Row < m;
bool cond1 = Col < n;
if(cond0 && cond1){
float Cvalue = 0;
for(int i = 0;i<dim;i++){
Cvalue += A[Row*dim+i]*B[i*n+Col];
}
C[Row*n+Col] = Cvalue;
}
}
/**
* This is a baseline Parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul_baseline(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
hipMalloc((void**)&d_A, size_A);
hipMalloc((void**)&d_B, size_B);
hipMalloc((void**)&d_C, size_C);
hipMemcpy(d_A, h_A, size_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size_B, hipMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel_Baseline<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
hipMemcpy(h_C, d_C, size_C, hipMemcpyDeviceToHost);
// Free device memory for A, B, C
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
printf("The baseline Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPfS_S_iii,@function
_Z15MatrixMulKernelPfS_S_iii:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 5, v5
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v1, s12
v_cmp_le_i32_e64 s2, s6, v4
v_cmp_gt_i32_e64 s4, s6, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x3d000000, v1
v_ceil_f32_e32 v2, v1
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v6, v2
v_lshl_add_u32 v0, s14, 5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, 1, v6
v_cmp_le_i32_e64 s3, s7, v0
v_cmp_gt_i32_e64 s5, s7, v0
s_cbranch_vccnz .LBB0_17
s_load_b128 s[8:11], s[0:1], 0x0
v_dual_mov_b32 v11, 0 :: v_dual_lshlrev_b32 v2, 2, v1
v_lshlrev_b32_e32 v7, 7, v5
s_mov_b32 s6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v8, 0x1000, v2
v_add_nc_u32_e32 v9, v7, v2
v_mad_u64_u32 v[2:3], null, v4, s12, v[1:2]
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB0_2:
s_lshl_b32 s13, s6, 5
s_mov_b32 s14, exec_lo
v_add_nc_u32_e32 v12, s13, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s12, v12
s_xor_b32 s14, exec_lo, s14
s_cbranch_execz .LBB0_4
ds_store_b32 v9, v11
.LBB0_4:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v12, 0
s_and_saveexec_b32 s15, s4
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v12, s13, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s8, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
global_load_b32 v12, v[12:13], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s15
s_waitcnt vmcnt(0)
ds_store_b32 v9, v12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v12, s13, v5
s_mov_b32 s13, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s12, v12
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_10
ds_store_b32 v10, v11
.LBB0_10:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_14
v_mov_b32_e32 v13, 0
s_and_saveexec_b32 s14, s5
s_cbranch_execz .LBB0_13
v_mad_u64_u32 v[13:14], null, v12, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[12:13], 2, v[13:14]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s10, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
global_load_b32 v13, v[12:13], off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v12, v8
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_15:
v_add_nc_u32_e32 v13, s13, v7
s_add_i32 s13, s13, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 0x80, v12
s_cmpk_eq_i32 s13, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v13, v14
s_cbranch_scc0 .LBB0_15
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s6, v6
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_2
s_branch .LBB0_18
.LBB0_17:
v_mov_b32_e32 v3, 0
.LBB0_18:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
s_xor_b32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_iii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z24MatrixMulKernel_BaselinePfS_S_iii
.globl _Z24MatrixMulKernel_BaselinePfS_S_iii
.p2align 8
.type _Z24MatrixMulKernel_BaselinePfS_S_iii,@function
_Z24MatrixMulKernel_BaselinePfS_S_iii:
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v5, s15, 5, v1
v_lshl_add_u32 v0, s14, 5, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v5
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_6
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v5, s2
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v6, 0
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v5, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24MatrixMulKernel_BaselinePfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z24MatrixMulKernel_BaselinePfS_S_iii, .Lfunc_end1-_Z24MatrixMulKernel_BaselinePfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24MatrixMulKernel_BaselinePfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24MatrixMulKernel_BaselinePfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include<hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define TILE_WIDTH 32
/**
* This is a kernel MatrixMul function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel(float* A,
float* B,
float* C,
int m,
int n,
int dim){
__shared__ float Ads[TILE_WIDTH][TILE_WIDTH];
__shared__ float Bds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
// Calculate the number of phase
int phase_num = ceil(dim / (float)TILE_WIDTH);
bool cond0 = Row < m;
bool cond1 = Col < n;
float Cvalue = 0;
// Each thread loads 'Row'th row of A and 'Col'th column of B
for (int ph = 0; ph < phase_num; ++ph) {
if(ph * TILE_WIDTH + tx < dim){
Ads[ty][tx] = (cond0)?A[Row * dim + ph*TILE_WIDTH + tx]:0;
}
else{
Ads[ty][tx] = 0;
}
if(ph * TILE_WIDTH + ty < dim){
Bds[ty][tx] = (cond1)?B[(ph*TILE_WIDTH + ty)*n + Col]:0;
}
else{
Bds[ty][tx] = 0;
}
__syncthreads();
for (int k = 0; k < TILE_WIDTH; ++k) {
Cvalue += Ads[ty][k] * Bds[k][tx];
}
__syncthreads();
}
if(cond0 && cond1){
C[Row * n + Col] = Cvalue;
}
}
/**
* This is a parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
hipMalloc((void**)&d_A, size_A);
hipMalloc((void**)&d_B, size_B);
hipMalloc((void**)&d_C, size_C);
hipMemcpy(d_A, h_A, size_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size_B, hipMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
hipMemcpy(h_C, d_C, size_C, hipMemcpyDeviceToHost);
// Free device memory for A, B, C
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
}
/**
* This is a baseline kernel function of parallel Matmul
*
* @param A Matrix (m,dim)
* @param B Matrix (dim,n)
* @param C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
__global__
void MatrixMulKernel_Baseline(float* A,
float* B,
float* C,
int m,
int n,
int dim){
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
// Identify the row and column of the C element to work on
// Each thread works on an element of C
int Row = by * TILE_WIDTH + ty;
int Col = bx * TILE_WIDTH + tx;
bool cond0 = Row < m;
bool cond1 = Col < n;
if(cond0 && cond1){
float Cvalue = 0;
for(int i = 0;i<dim;i++){
Cvalue += A[Row*dim+i]*B[i*n+Col];
}
C[Row*n+Col] = Cvalue;
}
}
/**
* This is a baseline Parallel Stub function of parallel Matmul
*
* @param h_A Matrix (m,dim)
* @param h_B Matrix (dim,n)
* @param h_C Result Matrix (m,n)
* @param m number of row in h_A
* @param n number of column in h_B
* @param dim number of row in h_B
*/
void parallelMatMul_baseline(float* h_A,
float* h_B,
float* h_C,
int m,
int n,
int dim){
// Using device parallel calculate the result and finally print the time
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
float *d_A, *d_B, *d_C;
size_t size_of_float = sizeof(float);
size_t size_A = m*dim*size_of_float;
size_t size_B = n*dim*size_of_float;
size_t size_C = m*n*size_of_float;
hipMalloc((void**)&d_A, size_A);
hipMalloc((void**)&d_B, size_B);
hipMalloc((void**)&d_C, size_C);
hipMemcpy(d_A, h_A, size_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size_B, hipMemcpyHostToDevice);
// Invoke kernel
dim3 dimGrid(ceil(n/(float)(TILE_WIDTH)),ceil(m/(float)(TILE_WIDTH)),1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH,1);
MatrixMulKernel_Baseline<<<dimGrid, dimBlock>>>(d_A, d_B, d_C, m, n, dim);
hipMemcpy(h_C, d_C, size_C, hipMemcpyDeviceToHost);
// Free device memory for A, B, C
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
printf("The baseline Parallel invoke Matmul function need %.1fs.\n",elapsedTime);
hipEventDestroy(start);
hipEventDestroy(stop);
}
|
.text
.file "MatrixMul.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPfS_S_iii: # @_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14parallelMatMulPfS_S_iii
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z14parallelMatMulPfS_S_iii
.p2align 4, 0x90
.type _Z14parallelMatMulPfS_S_iii,@function
_Z14parallelMatMulPfS_S_iii: # @_Z14parallelMatMulPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %r8d, %r15d
movl %ecx, %r12d
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $0, 12(%rsp)
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r14d, %eax
imull %r12d, %eax
movslq %eax, %rbp
shlq $2, %rbp
movl %r14d, 56(%rsp) # 4-byte Spill
imull %r15d, %r14d
movslq %r14d, %r13
shlq $2, %r13
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %ebx, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r12d, 68(%rsp)
movl %r15d, 64(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14parallelMatMulPfS_S_iii, .Lfunc_end1-_Z14parallelMatMulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii # -- Begin function _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.p2align 4, 0x90
.type _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii,@function
_Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii: # @_Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24MatrixMulKernel_BaselinePfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii, .Lfunc_end2-_Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z23parallelMatMul_baselinePfS_S_iii
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z23parallelMatMul_baselinePfS_S_iii
.p2align 4, 0x90
.type _Z23parallelMatMul_baselinePfS_S_iii,@function
_Z23parallelMatMul_baselinePfS_S_iii: # @_Z23parallelMatMul_baselinePfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %r8d, %r15d
movl %ecx, %r12d
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $0, 12(%rsp)
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r14d, %eax
imull %r12d, %eax
movslq %eax, %rbp
shlq $2, %rbp
movl %r14d, 56(%rsp) # 4-byte Spill
imull %r15d, %r14d
movslq %r14d, %r13
shlq $2, %r13
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %ebx, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r12d, 68(%rsp)
movl %r15d, 64(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z24MatrixMulKernel_BaselinePfS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z23parallelMatMul_baselinePfS_S_iii, .Lfunc_end3-_Z23parallelMatMul_baselinePfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24MatrixMulKernel_BaselinePfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_iii,@object # @_Z15MatrixMulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_iii
.size _Z15MatrixMulKernelPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Parallel invoke Matmul function need %.1fs.\n"
.size .L.str, 45
.type _Z24MatrixMulKernel_BaselinePfS_S_iii,@object # @_Z24MatrixMulKernel_BaselinePfS_S_iii
.section .rodata,"a",@progbits
.globl _Z24MatrixMulKernel_BaselinePfS_S_iii
.p2align 3, 0x0
_Z24MatrixMulKernel_BaselinePfS_S_iii:
.quad _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.size _Z24MatrixMulKernel_BaselinePfS_S_iii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The baseline Parallel invoke Matmul function need %.1fs.\n"
.size .L.str.1, 58
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24MatrixMulKernel_BaselinePfS_S_iii"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_iii
.addrsig_sym _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_iii
.addrsig_sym _Z24MatrixMulKernel_BaselinePfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000abf50_00000000-6_MatrixMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
.globl _Z15MatrixMulKernelPfS_S_iii
.type _Z15MatrixMulKernelPfS_S_iii, @function
_Z15MatrixMulKernelPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15MatrixMulKernelPfS_S_iii, .-_Z15MatrixMulKernelPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Parallel invoke Matmul function need %.1fs.\n"
.text
.globl _Z14parallelMatMulPfS_S_iii
.type _Z14parallelMatMulPfS_S_iii, @function
_Z14parallelMatMulPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0x00000000, 36(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L13
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L13:
cvttss2siq %xmm4, %rax
movl %eax, 80(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 84(%rsp)
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z42__device_stub__Z15MatrixMulKernelPfS_S_iiiPfS_S_iii
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z14parallelMatMulPfS_S_iii, .-_Z14parallelMatMulPfS_S_iii
.globl _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
.type _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii, @function
_Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24MatrixMulKernel_BaselinePfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii, .-_Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
.globl _Z24MatrixMulKernel_BaselinePfS_S_iii
.type _Z24MatrixMulKernel_BaselinePfS_S_iii, @function
_Z24MatrixMulKernel_BaselinePfS_S_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z24MatrixMulKernel_BaselinePfS_S_iii, .-_Z24MatrixMulKernel_BaselinePfS_S_iii
.section .rodata.str1.8
.align 8
.LC7:
.string "The baseline Parallel invoke Matmul function need %.1fs.\n"
.text
.globl _Z23parallelMatMul_baselinePfS_S_iii
.type _Z23parallelMatMul_baselinePfS_S_iii, @function
_Z23parallelMatMul_baselinePfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, %r13d
movl %r8d, %r14d
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0x00000000, 36(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %r12d
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movl %r13d, %ebx
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L28
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L28:
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC1(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC6(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC2(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L29
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC4(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L29:
cvttss2siq %xmm4, %rax
movl %eax, 80(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 84(%rsp)
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L30:
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z51__device_stub__Z24MatrixMulKernel_BaselinePfS_S_iiiPfS_S_iii
jmp .L30
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z23parallelMatMul_baselinePfS_S_iii, .-_Z23parallelMatMul_baselinePfS_S_iii
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z24MatrixMulKernel_BaselinePfS_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "_Z15MatrixMulKernelPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z24MatrixMulKernel_BaselinePfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1023410176
.align 4
.LC2:
.long 1258291200
.align 4
.LC4:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "MatrixMul.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPfS_S_iii: # @_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14parallelMatMulPfS_S_iii
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z14parallelMatMulPfS_S_iii
.p2align 4, 0x90
.type _Z14parallelMatMulPfS_S_iii,@function
_Z14parallelMatMulPfS_S_iii: # @_Z14parallelMatMulPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %r8d, %r15d
movl %ecx, %r12d
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $0, 12(%rsp)
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r14d, %eax
imull %r12d, %eax
movslq %eax, %rbp
shlq $2, %rbp
movl %r14d, 56(%rsp) # 4-byte Spill
imull %r15d, %r14d
movslq %r14d, %r13
shlq $2, %r13
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %ebx, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r12d, 68(%rsp)
movl %r15d, 64(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14parallelMatMulPfS_S_iii, .Lfunc_end1-_Z14parallelMatMulPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii # -- Begin function _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.p2align 4, 0x90
.type _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii,@function
_Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii: # @_Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24MatrixMulKernel_BaselinePfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii, .Lfunc_end2-_Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z23parallelMatMul_baselinePfS_S_iii
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z23parallelMatMul_baselinePfS_S_iii
.p2align 4, 0x90
.type _Z23parallelMatMul_baselinePfS_S_iii,@function
_Z23parallelMatMul_baselinePfS_S_iii: # @_Z23parallelMatMul_baselinePfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %r8d, %r15d
movl %ecx, %r12d
movq %rdx, 80(%rsp) # 8-byte Spill
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $0, 12(%rsp)
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl %r14d, %eax
imull %r12d, %eax
movslq %eax, %rbp
shlq $2, %rbp
movl %r14d, 56(%rsp) # 4-byte Spill
imull %r15d, %r14d
movslq %r14d, %r13
shlq $2, %r13
movl %r15d, %eax
imull %r12d, %eax
movslq %eax, %r14
shlq $2, %r14
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %r12d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %ebx, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r12d, 68(%rsp)
movl %r15d, 64(%rsp)
movl 56(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z24MatrixMulKernel_BaselinePfS_S_iii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z23parallelMatMul_baselinePfS_S_iii, .Lfunc_end3-_Z23parallelMatMul_baselinePfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24MatrixMulKernel_BaselinePfS_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_iii,@object # @_Z15MatrixMulKernelPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_iii
.size _Z15MatrixMulKernelPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Parallel invoke Matmul function need %.1fs.\n"
.size .L.str, 45
.type _Z24MatrixMulKernel_BaselinePfS_S_iii,@object # @_Z24MatrixMulKernel_BaselinePfS_S_iii
.section .rodata,"a",@progbits
.globl _Z24MatrixMulKernel_BaselinePfS_S_iii
.p2align 3, 0x0
_Z24MatrixMulKernel_BaselinePfS_S_iii:
.quad _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.size _Z24MatrixMulKernel_BaselinePfS_S_iii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "The baseline Parallel invoke Matmul function need %.1fs.\n"
.size .L.str.1, 58
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24MatrixMulKernel_BaselinePfS_S_iii"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_iii
.addrsig_sym _Z39__device_stub__MatrixMulKernel_BaselinePfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_iii
.addrsig_sym _Z24MatrixMulKernel_BaselinePfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <iostream>
#include <cuda_runtime.h>
// kernels are C++ functions defined with CUDA
// They will be called with << >>()
// cudaGetDeviceCount (int* count)
// Returns the number of compute-capable devices
// cudaGetDeviceProperties (cudaDeviceProp* prop, int device)
// Returns information about the compute-device.
// Program that gives the information of the GPUs on the boards
int main() {
int devices;
cudaDeviceProp prop;
try {
cudaGetDeviceCount(&devices);
// Get information of all the Nvidia devices on the computer
for(int device = 0; device < devices; device++) {
cudaGetDeviceProperties(&prop, device);
// using std::cout as a display function
// using std::endl as a end of line character
std::cout << "Device Number : " << device << std::endl;
std::cout << "Device name : " << prop.name << std::endl;
std::cout << "Memory Clock Rate (KHz) : " << prop.memoryClockRate << std::endl;
std::cout << "Global Memory size (bits) : " << prop.memoryBusWidth << std::endl;
// get the warp size, i.e. the number of threads in a warp
std::cout << "Warp Size : " << prop.warpSize << std::endl;
std::cout << "Peak Memory Bandwidth (GB/s) : " << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << std::endl;
}
}
catch (const cudaError_t & e) {
std::cerr << e;
}
return 0;
}
/*
Device Number : 0
Device name : GeForce RTX 2060 SUPER
Memory Clock Rate (KHz) : 7001000
Global Memory size (bits) : 256
Warp Size : 32
Peak Memory Bandwidth (GB/s) : 448.064
*/
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <iostream>
#include <cuda_runtime.h>
// kernels are C++ functions defined with CUDA
// They will be called with << >>()
// cudaGetDeviceCount (int* count)
// Returns the number of compute-capable devices
// cudaGetDeviceProperties (cudaDeviceProp* prop, int device)
// Returns information about the compute-device.
// Program that gives the information of the GPUs on the boards
int main() {
int devices;
cudaDeviceProp prop;
try {
cudaGetDeviceCount(&devices);
// Get information of all the Nvidia devices on the computer
for(int device = 0; device < devices; device++) {
cudaGetDeviceProperties(&prop, device);
// using std::cout as a display function
// using std::endl as a end of line character
std::cout << "Device Number : " << device << std::endl;
std::cout << "Device name : " << prop.name << std::endl;
std::cout << "Memory Clock Rate (KHz) : " << prop.memoryClockRate << std::endl;
std::cout << "Global Memory size (bits) : " << prop.memoryBusWidth << std::endl;
// get the warp size, i.e. the number of threads in a warp
std::cout << "Warp Size : " << prop.warpSize << std::endl;
std::cout << "Peak Memory Bandwidth (GB/s) : " << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << std::endl;
}
}
catch (const cudaError_t & e) {
std::cerr << e;
}
return 0;
}
/*
Device Number : 0
Device name : GeForce RTX 2060 SUPER
Memory Clock Rate (KHz) : 7001000
Global Memory size (bits) : 256
Warp Size : 32
Peak Memory Bandwidth (GB/s) : 448.064
*/
|
.file "tmpxft_0011c6c6_00000000-6_tp1-ex1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device Number : "
.align 8
.LC1:
.string "Device name : "
.align 8
.LC2:
.string "Memory Clock Rate (KHz) : "
.align 8
.LC3:
.string "Global Memory size (bits) : "
.align 8
.LC4:
.string "Warp Size : "
.align 8
.LC5:
.string "Peak Memory Bandwidth (GB/s) : "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3669
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
.LEHB0:
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbx
leaq .LC1(%rip), %r13
jmp .L29
.L59:
movl $31, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L41
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L42
.L41:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L36:
endbr64
movq %rax, %rdi
cmpq $1, %rdx
je .L31
movq 1048(%rsp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L43:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L42:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %r14
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L44
cmpb $0, 56(%r14)
je .L11
movzbl 67(%r14), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L45
.L44:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L11:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L45:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 624(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L47
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
.L16:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L48
.L47:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L48:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 628(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L50
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L51
.L50:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L51:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 324(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L54
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L54:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 624(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 628(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC6(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L57
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L57:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L29:
leaq 16(%rsp), %rdi
movl %ebp, %esi
call cudaGetDeviceProperties_v2@PLT
.LEHE0:
jmp .L59
.L32:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L31:
call __cxa_begin_catch@PLT
movl (%rax), %esi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZNSolsEi@PLT
.LEHE2:
call __cxa_end_catch@PLT
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L34:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3669:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3669-.LLSDATTD3669
.LLSDATTD3669:
.byte 0x1
.uleb128 .LLSDACSE3669-.LLSDACSB3669
.LLSDACSB3669:
.uleb128 .LEHB0-.LFB3669
.uleb128 .LEHE0-.LEHB0
.uleb128 .L36-.LFB3669
.uleb128 0x1
.uleb128 .LEHB1-.LFB3669
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.uleb128 .LEHB2-.LFB3669
.uleb128 .LEHE2-.LEHB2
.uleb128 .L37-.LFB3669
.uleb128 0
.uleb128 .LEHB3-.LFB3669
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3669:
.byte 0x1
.byte 0
.align 4
.long DW.ref._ZTI9cudaError-.
.LLSDATT3669:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS9cudaError
.section .rodata._ZTS9cudaError,"aG",@progbits,_ZTS9cudaError,comdat
.align 8
.type _ZTS9cudaError, @object
.size _ZTS9cudaError, 11
_ZTS9cudaError:
.string "9cudaError"
.weak _ZTI9cudaError
.section .data.rel.ro._ZTI9cudaError,"awG",@progbits,_ZTI9cudaError,comdat
.align 8
.type _ZTI9cudaError, @object
.size _ZTI9cudaError, 16
_ZTI9cudaError:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS9cudaError
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.hidden DW.ref._ZTI9cudaError
.weak DW.ref._ZTI9cudaError
.section .data.rel.local.DW.ref._ZTI9cudaError,"awG",@progbits,DW.ref._ZTI9cudaError,comdat
.align 8
.type DW.ref._ZTI9cudaError, @object
.size DW.ref._ZTI9cudaError, 8
DW.ref._ZTI9cudaError:
.quad _ZTI9cudaError
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <iostream>
#include <cuda_runtime.h>
// kernels are C++ functions defined with CUDA
// They will be called with << >>()
// cudaGetDeviceCount (int* count)
// Returns the number of compute-capable devices
// cudaGetDeviceProperties (cudaDeviceProp* prop, int device)
// Returns information about the compute-device.
// Program that gives the information of the GPUs on the boards
int main() {
int devices;
cudaDeviceProp prop;
try {
cudaGetDeviceCount(&devices);
// Get information of all the Nvidia devices on the computer
for(int device = 0; device < devices; device++) {
cudaGetDeviceProperties(&prop, device);
// using std::cout as a display function
// using std::endl as a end of line character
std::cout << "Device Number : " << device << std::endl;
std::cout << "Device name : " << prop.name << std::endl;
std::cout << "Memory Clock Rate (KHz) : " << prop.memoryClockRate << std::endl;
std::cout << "Global Memory size (bits) : " << prop.memoryBusWidth << std::endl;
// get the warp size, i.e. the number of threads in a warp
std::cout << "Warp Size : " << prop.warpSize << std::endl;
std::cout << "Peak Memory Bandwidth (GB/s) : " << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << std::endl;
}
}
catch (const cudaError_t & e) {
std::cerr << e;
}
return 0;
}
/*
Device Number : 0
Device name : GeForce RTX 2060 SUPER
Memory Clock Rate (KHz) : 7001000
Global Memory size (bits) : 256
Warp Size : 32
Peak Memory Bandwidth (GB/s) : 448.064
*/
|
#include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
// kernels are C++ functions defined with CUDA
// They will be called with << >>()
// cudaGetDeviceCount (int* count)
// Returns the number of compute-capable devices
// cudaGetDeviceProperties (cudaDeviceProp* prop, int device)
// Returns information about the compute-device.
// Program that gives the information of the GPUs on the boards
int main() {
int devices;
hipDeviceProp_t prop;
try {
hipGetDeviceCount(&devices);
// Get information of all the Nvidia devices on the computer
for(int device = 0; device < devices; device++) {
hipGetDeviceProperties(&prop, device);
// using std::cout as a display function
// using std::endl as a end of line character
std::cout << "Device Number : " << device << std::endl;
std::cout << "Device name : " << prop.name << std::endl;
std::cout << "Memory Clock Rate (KHz) : " << prop.memoryClockRate << std::endl;
std::cout << "Global Memory size (bits) : " << prop.memoryBusWidth << std::endl;
// get the warp size, i.e. the number of threads in a warp
std::cout << "Warp Size : " << prop.warpSize << std::endl;
std::cout << "Peak Memory Bandwidth (GB/s) : " << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << std::endl;
}
}
catch (const hipError_t & e) {
std::cerr << e;
}
return 0;
}
/*
Device Number : 0
Device name : GeForce RTX 2060 SUPER
Memory Clock Rate (KHz) : 7001000
Global Memory size (bits) : 256
Warp Size : 32
Peak Memory Bandwidth (GB/s) : 448.064
*/
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
// kernels are C++ functions defined with CUDA
// They will be called with << >>()
// cudaGetDeviceCount (int* count)
// Returns the number of compute-capable devices
// cudaGetDeviceProperties (cudaDeviceProp* prop, int device)
// Returns information about the compute-device.
// Program that gives the information of the GPUs on the boards
int main() {
int devices;
hipDeviceProp_t prop;
try {
hipGetDeviceCount(&devices);
// Get information of all the Nvidia devices on the computer
for(int device = 0; device < devices; device++) {
hipGetDeviceProperties(&prop, device);
// using std::cout as a display function
// using std::endl as a end of line character
std::cout << "Device Number : " << device << std::endl;
std::cout << "Device name : " << prop.name << std::endl;
std::cout << "Memory Clock Rate (KHz) : " << prop.memoryClockRate << std::endl;
std::cout << "Global Memory size (bits) : " << prop.memoryBusWidth << std::endl;
// get the warp size, i.e. the number of threads in a warp
std::cout << "Warp Size : " << prop.warpSize << std::endl;
std::cout << "Peak Memory Bandwidth (GB/s) : " << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << std::endl;
}
}
catch (const hipError_t & e) {
std::cerr << e;
}
return 0;
}
/*
Device Number : 0
Device name : GeForce RTX 2060 SUPER
Memory Clock Rate (KHz) : 7001000
Global Memory size (bits) : 256
Warp Size : 32
Peak Memory Bandwidth (GB/s) : 448.064
*/
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <iostream>
#include <hip/hip_runtime.h>
// kernels are C++ functions defined with CUDA
// They will be called with << >>()
// cudaGetDeviceCount (int* count)
// Returns the number of compute-capable devices
// cudaGetDeviceProperties (cudaDeviceProp* prop, int device)
// Returns information about the compute-device.
// Program that gives the information of the GPUs on the boards
int main() {
int devices;
hipDeviceProp_t prop;
try {
hipGetDeviceCount(&devices);
// Get information of all the Nvidia devices on the computer
for(int device = 0; device < devices; device++) {
hipGetDeviceProperties(&prop, device);
// using std::cout as a display function
// using std::endl as a end of line character
std::cout << "Device Number : " << device << std::endl;
std::cout << "Device name : " << prop.name << std::endl;
std::cout << "Memory Clock Rate (KHz) : " << prop.memoryClockRate << std::endl;
std::cout << "Global Memory size (bits) : " << prop.memoryBusWidth << std::endl;
// get the warp size, i.e. the number of threads in a warp
std::cout << "Warp Size : " << prop.warpSize << std::endl;
std::cout << "Peak Memory Bandwidth (GB/s) : " << 2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6 << std::endl;
}
}
catch (const hipError_t & e) {
std::cerr << e;
}
return 0;
}
/*
Device Number : 0
Device name : GeForce RTX 2060 SUPER
Memory Clock Rate (KHz) : 7001000
Global Memory size (bits) : 256
Warp Size : 32
Peak Memory Bandwidth (GB/s) : 448.064
*/
|
.text
.file "tp1-ex1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.Ltmp0:
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
.Ltmp1:
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_67
# %bb.2: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
.Ltmp3:
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
.Ltmp4:
# %bb.4: # in Loop: Header=BB0_3 Depth=1
.Ltmp5:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp6:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_3 Depth=1
.Ltmp7:
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp8:
# %bb.6: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_11
# %bb.10: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_11: # in Loop: Header=BB0_3 Depth=1
.Ltmp9:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp10:
# %bb.12: # %.noexc23
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp11:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp12:
.LBB0_13: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB0_3 Depth=1
.Ltmp13:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp14:
# %bb.14: # %.noexc25
# in Loop: Header=BB0_3 Depth=1
.Ltmp15:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp16:
# %bb.15: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB0_3 Depth=1
.Ltmp17:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit12
# in Loop: Header=BB0_3 Depth=1
movq %r14, %rdi
callq strlen
.Ltmp19:
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit13
# in Loop: Header=BB0_3 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_7
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r15)
je .LBB0_20
# %bb.19: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_3 Depth=1
.Ltmp21:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp22:
# %bb.21: # %.noexc33
# in Loop: Header=BB0_3 Depth=1
movq (%r15), %rax
.Ltmp23:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp24:
.LBB0_22: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i30
# in Loop: Header=BB0_3 Depth=1
.Ltmp25:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp26:
# %bb.23: # %.noexc35
# in Loop: Header=BB0_3 Depth=1
.Ltmp27:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp28:
# %bb.24: # %_ZNSolsEPFRSoS_E.exit14
# in Loop: Header=BB0_3 Depth=1
.Ltmp29:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
# %bb.25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit15
# in Loop: Header=BB0_3 Depth=1
movl 616(%rsp), %esi
.Ltmp31:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp32:
# %bb.26: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_29
# %bb.28: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_31
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_3 Depth=1
.Ltmp33:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp34:
# %bb.30: # %.noexc44
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp35:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp36:
.LBB0_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i41
# in Loop: Header=BB0_3 Depth=1
.Ltmp37:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp38:
# %bb.32: # %.noexc46
# in Loop: Header=BB0_3 Depth=1
.Ltmp39:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp40:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit16
# in Loop: Header=BB0_3 Depth=1
.Ltmp41:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp42:
# %bb.34: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit17
# in Loop: Header=BB0_3 Depth=1
movl 620(%rsp), %esi
.Ltmp43:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp44:
# %bb.35: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i50
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_38
# %bb.37: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_38: # in Loop: Header=BB0_3 Depth=1
.Ltmp45:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp46:
# %bb.39: # %.noexc55
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp47:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp48:
.LBB0_40: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i52
# in Loop: Header=BB0_3 Depth=1
.Ltmp49:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp50:
# %bb.41: # %.noexc57
# in Loop: Header=BB0_3 Depth=1
.Ltmp51:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp52:
# %bb.42: # %_ZNSolsEPFRSoS_E.exit18
# in Loop: Header=BB0_3 Depth=1
.Ltmp53:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp54:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
# in Loop: Header=BB0_3 Depth=1
movl 316(%rsp), %esi
.Ltmp55:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp56:
# %bb.44: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_47
# %bb.46: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_49
.p2align 4, 0x90
.LBB0_47: # in Loop: Header=BB0_3 Depth=1
.Ltmp57:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp58:
# %bb.48: # %.noexc66
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp59:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp60:
.LBB0_49: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i63
# in Loop: Header=BB0_3 Depth=1
.Ltmp61:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp62:
# %bb.50: # %.noexc68
# in Loop: Header=BB0_3 Depth=1
.Ltmp63:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp64:
# %bb.51: # %_ZNSolsEPFRSoS_E.exit20
# in Loop: Header=BB0_3 Depth=1
.Ltmp65:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp66:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit21
# in Loop: Header=BB0_3 Depth=1
cvtsi2sdl 616(%rsp), %xmm1
addsd %xmm1, %xmm1
movl 620(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI0_0(%rip), %xmm0
.Ltmp67:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp68:
# %bb.53: # %_ZNSolsEd.exit
# in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_56
# %bb.55: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_58
.p2align 4, 0x90
.LBB0_56: # in Loop: Header=BB0_3 Depth=1
.Ltmp69:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp70:
# %bb.57: # %.noexc77
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp71:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp72:
.LBB0_58: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i74
# in Loop: Header=BB0_3 Depth=1
.Ltmp73:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp74:
# %bb.59: # %.noexc79
# in Loop: Header=BB0_3 Depth=1
.Ltmp75:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp76:
# %bb.60: # %_ZNSolsEPFRSoS_E.exit22
# in Loop: Header=BB0_3 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jl .LBB0_3
.LBB0_67: # %.loopexit
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_7: # %.invoke
.cfi_def_cfa_offset 1520
.Ltmp78:
callq _ZSt16__throw_bad_castv
.Ltmp79:
# %bb.8: # %.cont
.LBB0_70:
.Ltmp2:
jmp .LBB0_63
.LBB0_62: # %.loopexit.split-lp
.Ltmp80:
jmp .LBB0_63
.LBB0_61: # %.loopexit82
.Ltmp77:
.LBB0_63:
cmpl $1, %edx
jne .LBB0_64
# %bb.65:
movq %rax, %rdi
callq __cxa_begin_catch
movl (%rax), %esi
.Ltmp81:
movl $_ZSt4cerr, %edi
callq _ZNSolsEi
.Ltmp82:
# %bb.66:
callq __cxa_end_catch
jmp .LBB0_67
.LBB0_64:
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB0_68:
.Ltmp83:
movq %rax, %rbx
callq __cxa_end_catch
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 3 # On action: 2
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp76-.Ltmp3 # Call between .Ltmp3 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 3 # On action: 2
.uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp79-.Ltmp78 # Call between .Ltmp78 and .Ltmp79
.uleb128 .Ltmp80-.Lfunc_begin0 # jumps to .Ltmp80
.byte 3 # On action: 2
.uleb128 .Ltmp79-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp81-.Ltmp79 # Call between .Ltmp79 and .Ltmp81
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp81-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp82-.Ltmp81 # Call between .Ltmp81 and .Ltmp82
.uleb128 .Ltmp83-.Lfunc_begin0 # jumps to .Ltmp83
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp82 # Call between .Ltmp82 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 0 # >> Action Record 1 <<
# Cleanup
.byte 0 # No further actions
.byte 1 # >> Action Record 2 <<
# Catch TypeInfo 1
.byte 125 # Continue to action 1
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long _ZTI10hipError_t # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.type _ZTS10hipError_t,@object # @_ZTS10hipError_t
.section .rodata._ZTS10hipError_t,"aG",@progbits,_ZTS10hipError_t,comdat
.weak _ZTS10hipError_t
_ZTS10hipError_t:
.asciz "10hipError_t"
.size _ZTS10hipError_t, 13
.type _ZTI10hipError_t,@object # @_ZTI10hipError_t
.section .rodata._ZTI10hipError_t,"aG",@progbits,_ZTI10hipError_t,comdat
.weak _ZTI10hipError_t
.p2align 3, 0x0
_ZTI10hipError_t:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS10hipError_t
.size _ZTI10hipError_t, 16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Number : "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device name : "
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory Clock Rate (KHz) : "
.size .L.str.2, 32
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Global Memory size (bits) : "
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Warp Size : "
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Peak Memory Bandwidth (GB/s) : "
.size .L.str.5, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv116__enum_type_infoE
.addrsig_sym _ZTS10hipError_t
.addrsig_sym _ZTI10hipError_t
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0011c6c6_00000000-6_tp1-ex1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device Number : "
.align 8
.LC1:
.string "Device name : "
.align 8
.LC2:
.string "Memory Clock Rate (KHz) : "
.align 8
.LC3:
.string "Global Memory size (bits) : "
.align 8
.LC4:
.string "Warp Size : "
.align 8
.LC5:
.string "Peak Memory Bandwidth (GB/s) : "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3669
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
.LEHB0:
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbx
leaq .LC1(%rip), %r13
jmp .L29
.L59:
movl $31, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L41
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L42
.L41:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L36:
endbr64
movq %rax, %rdi
cmpq $1, %rdx
je .L31
movq 1048(%rsp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L43:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L42:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %r14
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L44
cmpb $0, 56(%r14)
je .L11
movzbl 67(%r14), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L45
.L44:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L11:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L45:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 624(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L47
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
.L16:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L48
.L47:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L48:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 628(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L50
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L51
.L50:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L52
call _ZSt16__throw_bad_castv@PLT
.L52:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L51:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 324(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L54
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L55
call _ZSt16__throw_bad_castv@PLT
.L55:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L54:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $31, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 624(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 628(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC6(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
jmp .L57
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L57:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L29:
leaq 16(%rsp), %rdi
movl %ebp, %esi
call cudaGetDeviceProperties_v2@PLT
.LEHE0:
jmp .L59
.L32:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L31:
call __cxa_begin_catch@PLT
movl (%rax), %esi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZNSolsEi@PLT
.LEHE2:
call __cxa_end_catch@PLT
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
je .L34
call __stack_chk_fail@PLT
.L34:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3669:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3669-.LLSDATTD3669
.LLSDATTD3669:
.byte 0x1
.uleb128 .LLSDACSE3669-.LLSDACSB3669
.LLSDACSB3669:
.uleb128 .LEHB0-.LFB3669
.uleb128 .LEHE0-.LEHB0
.uleb128 .L36-.LFB3669
.uleb128 0x1
.uleb128 .LEHB1-.LFB3669
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.uleb128 .LEHB2-.LFB3669
.uleb128 .LEHE2-.LEHB2
.uleb128 .L37-.LFB3669
.uleb128 0
.uleb128 .LEHB3-.LFB3669
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3669:
.byte 0x1
.byte 0
.align 4
.long DW.ref._ZTI9cudaError-.
.LLSDATT3669:
.text
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.weak _ZTS9cudaError
.section .rodata._ZTS9cudaError,"aG",@progbits,_ZTS9cudaError,comdat
.align 8
.type _ZTS9cudaError, @object
.size _ZTS9cudaError, 11
_ZTS9cudaError:
.string "9cudaError"
.weak _ZTI9cudaError
.section .data.rel.ro._ZTI9cudaError,"awG",@progbits,_ZTI9cudaError,comdat
.align 8
.type _ZTI9cudaError, @object
.size _ZTI9cudaError, 16
_ZTI9cudaError:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS9cudaError
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.hidden DW.ref._ZTI9cudaError
.weak DW.ref._ZTI9cudaError
.section .data.rel.local.DW.ref._ZTI9cudaError,"awG",@progbits,DW.ref._ZTI9cudaError,comdat
.align 8
.type DW.ref._ZTI9cudaError, @object
.size DW.ref._ZTI9cudaError, 8
DW.ref._ZTI9cudaError:
.quad _ZTI9cudaError
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "tp1-ex1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.Ltmp0:
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
.Ltmp1:
# %bb.1: # %.preheader
cmpl $0, 4(%rsp)
jle .LBB0_67
# %bb.2: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
.Ltmp3:
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
.Ltmp4:
# %bb.4: # in Loop: Header=BB0_3 Depth=1
.Ltmp5:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp6:
# %bb.5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_3 Depth=1
.Ltmp7:
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.Ltmp8:
# %bb.6: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_11
# %bb.10: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_13
.p2align 4, 0x90
.LBB0_11: # in Loop: Header=BB0_3 Depth=1
.Ltmp9:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp10:
# %bb.12: # %.noexc23
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp11:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp12:
.LBB0_13: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB0_3 Depth=1
.Ltmp13:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp14:
# %bb.14: # %.noexc25
# in Loop: Header=BB0_3 Depth=1
.Ltmp15:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp16:
# %bb.15: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB0_3 Depth=1
.Ltmp17:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp18:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit12
# in Loop: Header=BB0_3 Depth=1
movq %r14, %rdi
callq strlen
.Ltmp19:
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit13
# in Loop: Header=BB0_3 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_7
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i28
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r15)
je .LBB0_20
# %bb.19: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_22
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_3 Depth=1
.Ltmp21:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp22:
# %bb.21: # %.noexc33
# in Loop: Header=BB0_3 Depth=1
movq (%r15), %rax
.Ltmp23:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp24:
.LBB0_22: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i30
# in Loop: Header=BB0_3 Depth=1
.Ltmp25:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp26:
# %bb.23: # %.noexc35
# in Loop: Header=BB0_3 Depth=1
.Ltmp27:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp28:
# %bb.24: # %_ZNSolsEPFRSoS_E.exit14
# in Loop: Header=BB0_3 Depth=1
.Ltmp29:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
# %bb.25: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit15
# in Loop: Header=BB0_3 Depth=1
movl 616(%rsp), %esi
.Ltmp31:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp32:
# %bb.26: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_29
# %bb.28: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_31
.p2align 4, 0x90
.LBB0_29: # in Loop: Header=BB0_3 Depth=1
.Ltmp33:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp34:
# %bb.30: # %.noexc44
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp35:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp36:
.LBB0_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i41
# in Loop: Header=BB0_3 Depth=1
.Ltmp37:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp38:
# %bb.32: # %.noexc46
# in Loop: Header=BB0_3 Depth=1
.Ltmp39:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp40:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit16
# in Loop: Header=BB0_3 Depth=1
.Ltmp41:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp42:
# %bb.34: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit17
# in Loop: Header=BB0_3 Depth=1
movl 620(%rsp), %esi
.Ltmp43:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp44:
# %bb.35: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i50
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_38
# %bb.37: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_40
.p2align 4, 0x90
.LBB0_38: # in Loop: Header=BB0_3 Depth=1
.Ltmp45:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp46:
# %bb.39: # %.noexc55
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp47:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp48:
.LBB0_40: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i52
# in Loop: Header=BB0_3 Depth=1
.Ltmp49:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp50:
# %bb.41: # %.noexc57
# in Loop: Header=BB0_3 Depth=1
.Ltmp51:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp52:
# %bb.42: # %_ZNSolsEPFRSoS_E.exit18
# in Loop: Header=BB0_3 Depth=1
.Ltmp53:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp54:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit19
# in Loop: Header=BB0_3 Depth=1
movl 316(%rsp), %esi
.Ltmp55:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp56:
# %bb.44: # in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_47
# %bb.46: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_49
.p2align 4, 0x90
.LBB0_47: # in Loop: Header=BB0_3 Depth=1
.Ltmp57:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp58:
# %bb.48: # %.noexc66
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp59:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp60:
.LBB0_49: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i63
# in Loop: Header=BB0_3 Depth=1
.Ltmp61:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp62:
# %bb.50: # %.noexc68
# in Loop: Header=BB0_3 Depth=1
.Ltmp63:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp64:
# %bb.51: # %_ZNSolsEPFRSoS_E.exit20
# in Loop: Header=BB0_3 Depth=1
.Ltmp65:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp66:
# %bb.52: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit21
# in Loop: Header=BB0_3 Depth=1
cvtsi2sdl 616(%rsp), %xmm1
addsd %xmm1, %xmm1
movl 620(%rsp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI0_0(%rip), %xmm0
.Ltmp67:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp68:
# %bb.53: # %_ZNSolsEd.exit
# in Loop: Header=BB0_3 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_7
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
# in Loop: Header=BB0_3 Depth=1
cmpb $0, 56(%r12)
je .LBB0_56
# %bb.55: # in Loop: Header=BB0_3 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_58
.p2align 4, 0x90
.LBB0_56: # in Loop: Header=BB0_3 Depth=1
.Ltmp69:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp70:
# %bb.57: # %.noexc77
# in Loop: Header=BB0_3 Depth=1
movq (%r12), %rax
.Ltmp71:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp72:
.LBB0_58: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i74
# in Loop: Header=BB0_3 Depth=1
.Ltmp73:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp74:
# %bb.59: # %.noexc79
# in Loop: Header=BB0_3 Depth=1
.Ltmp75:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp76:
# %bb.60: # %_ZNSolsEPFRSoS_E.exit22
# in Loop: Header=BB0_3 Depth=1
incl %ebx
cmpl 4(%rsp), %ebx
jl .LBB0_3
.LBB0_67: # %.loopexit
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_7: # %.invoke
.cfi_def_cfa_offset 1520
.Ltmp78:
callq _ZSt16__throw_bad_castv
.Ltmp79:
# %bb.8: # %.cont
.LBB0_70:
.Ltmp2:
jmp .LBB0_63
.LBB0_62: # %.loopexit.split-lp
.Ltmp80:
jmp .LBB0_63
.LBB0_61: # %.loopexit82
.Ltmp77:
.LBB0_63:
cmpl $1, %edx
jne .LBB0_64
# %bb.65:
movq %rax, %rdi
callq __cxa_begin_catch
movl (%rax), %esi
.Ltmp81:
movl $_ZSt4cerr, %edi
callq _ZNSolsEi
.Ltmp82:
# %bb.66:
callq __cxa_end_catch
jmp .LBB0_67
.LBB0_64:
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB0_68:
.Ltmp83:
movq %rax, %rbx
callq __cxa_end_catch
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 3 # On action: 2
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp76-.Ltmp3 # Call between .Ltmp3 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 3 # On action: 2
.uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp79-.Ltmp78 # Call between .Ltmp78 and .Ltmp79
.uleb128 .Ltmp80-.Lfunc_begin0 # jumps to .Ltmp80
.byte 3 # On action: 2
.uleb128 .Ltmp79-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp81-.Ltmp79 # Call between .Ltmp79 and .Ltmp81
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp81-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp82-.Ltmp81 # Call between .Ltmp81 and .Ltmp82
.uleb128 .Ltmp83-.Lfunc_begin0 # jumps to .Ltmp83
.byte 0 # On action: cleanup
.uleb128 .Ltmp82-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end0-.Ltmp82 # Call between .Ltmp82 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 0 # >> Action Record 1 <<
# Cleanup
.byte 0 # No further actions
.byte 1 # >> Action Record 2 <<
# Catch TypeInfo 1
.byte 125 # Continue to action 1
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long _ZTI10hipError_t # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.type _ZTS10hipError_t,@object # @_ZTS10hipError_t
.section .rodata._ZTS10hipError_t,"aG",@progbits,_ZTS10hipError_t,comdat
.weak _ZTS10hipError_t
_ZTS10hipError_t:
.asciz "10hipError_t"
.size _ZTS10hipError_t, 13
.type _ZTI10hipError_t,@object # @_ZTI10hipError_t
.section .rodata._ZTI10hipError_t,"aG",@progbits,_ZTI10hipError_t,comdat
.weak _ZTI10hipError_t
.p2align 3, 0x0
_ZTI10hipError_t:
.quad _ZTVN10__cxxabiv116__enum_type_infoE+16
.quad _ZTS10hipError_t
.size _ZTI10hipError_t, 16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device Number : "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device name : "
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Memory Clock Rate (KHz) : "
.size .L.str.2, 32
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Global Memory size (bits) : "
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Warp Size : "
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Peak Memory Bandwidth (GB/s) : "
.size .L.str.5, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZTVN10__cxxabiv116__enum_type_infoE
.addrsig_sym _ZTS10hipError_t
.addrsig_sym _ZTI10hipError_t
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda2(int mbc, int mx, int my, int meqn, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int ix = threadIdx.x + blockIdx.x*blockDim.x;
int iy = threadIdx.y + blockIdx.y*blockDim.y;
if (ix < mx && iy < my)
{
int x_stride = meqn;
int y_stride = (2*mbc + mx)*x_stride;
int I_q = (ix+mbc)*x_stride + (iy+mbc)*y_stride;
int mq;
for(mq = 0; mq < meqn; mq++)
{
int i = I_q+mq;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
}
}
}
|
code for sm_80
Function : _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R6, R0, c[0x0][0x4], R3 ; /* 0x0000010000067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R2, c[0x0][0x0], R5 ; /* 0x0000000002047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fca00078e00ff */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0100*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0120*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f25270 */
/*0130*/ @!P0 BRA 0x6d0 ; /* 0x0000059000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R7, R3, c[0x0][0x160], RZ ; /* 0x0000580003077a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R11, R5.reuse, c[0x0][0x164], RZ ; /* 0x00005900050b7a10 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R14, 0x8 ; /* 0x00000008000e7802 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R6, R0, c[0x0][0x4], R7 ; /* 0x0000010000067a24 */
/* 0x000fe200078e0207 */
/*01a0*/ IADD3 R7, R5, c[0x0][0x160], RZ ; /* 0x0000580005077a10 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R11, R2, c[0x0][0x0], R11 ; /* 0x00000000020b7a24 */
/* 0x000fe200078e020b */
/*01c0*/ LEA R9, R8, c[0x0][0x164], 0x1 ; /* 0x0000590008097a11 */
/* 0x000fe200078e08ff */
/*01d0*/ ULDC.64 UR12, c[0x0][0x188] ; /* 0x00006200000c7ab9 */
/* 0x000fe20000000a00 */
/*01e0*/ IADD3 R29, -R4, c[0x0][0x16c], RZ ; /* 0x00005b00041d7a10 */
/* 0x000fe20007ffe1ff */
/*01f0*/ IMAD R7, R2, c[0x0][0x0], R7 ; /* 0x0000000002077a24 */
/* 0x000fe200078e0207 */
/*0200*/ ULDC.64 UR10, c[0x0][0x180] ; /* 0x00006000000a7ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IMAD R11, R6.reuse, R9.reuse, R11 ; /* 0x00000009060b7224 */
/* 0x0c0fe200078e020b */
/*0220*/ ULDC.64 UR8, c[0x0][0x190] ; /* 0x0000640000087ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD R7, R6, R9, R7 ; /* 0x0000000906077224 */
/* 0x000fe200078e0207 */
/*0240*/ ULDC.64 UR6, c[0x0][0x1a0] ; /* 0x0000680000067ab9 */
/* 0x000fe20000000a00 */
/*0250*/ IMAD R11, R8, 0x3, R11 ; /* 0x00000003080b7824 */
/* 0x000fc400078e020b */
/*0260*/ IMAD R28, R7.reuse, c[0x0][0x16c], RZ ; /* 0x00005b00071c7a24 */
/* 0x040fe200078e02ff */
/*0270*/ IADD3 R26, R7, 0x1, RZ ; /* 0x00000001071a7810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD R11, R11, c[0x0][0x16c], RZ ; /* 0x00005b000b0b7a24 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD.WIDE R14, R11, R14, c[0x0][0x198] ; /* 0x000066000b0e7625 */
/* 0x000fc800078e020e */
/*02a0*/ IMAD R26, R26, c[0x0][0x16c], RZ ; /* 0x00005b001a1a7a24 */
/* 0x000fe400078e02ff */
/*02b0*/ MOV R8, UR12 ; /* 0x0000000c00087c02 */
/* 0x000fe20008000f00 */
/*02c0*/ IMAD.U32 R9, RZ, RZ, UR13 ; /* 0x0000000dff097e24 */
/* 0x000fe2000f8e00ff */
/*02d0*/ MOV R6, UR8 ; /* 0x0000000800067c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R7, RZ, RZ, UR9 ; /* 0x00000009ff077e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R10, UR10 ; /* 0x0000000a000a7c02 */
/* 0x001fe20008000f00 */
/*0300*/ IMAD.WIDE R8, R26, 0x8, R8 ; /* 0x000000081a087825 */
/* 0x000fe200078e0208 */
/*0310*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0320*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1b00 */
/*0330*/ IMAD.WIDE R6, R28, 0x8, R6 ; /* 0x000000081c067825 */
/* 0x000fe400078e0206 */
/*0340*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ee4000c1e1b00 */
/*0350*/ IMAD.U32 R11, RZ, RZ, UR11 ; /* 0x0000000bff0b7e24 */
/* 0x000fc4000f8e00ff */
/*0360*/ IMAD.U32 R13, RZ, RZ, UR7 ; /* 0x00000007ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ LDG.E.64 R24, [R6.64] ; /* 0x0000000406187981 */
/* 0x000ee2000c1e1b00 */
/*0380*/ IMAD.WIDE R10, R28, 0x8, R10 ; /* 0x000000081c0a7825 */
/* 0x000fc800078e020a */
/*0390*/ IMAD.WIDE R12, R28, 0x8, R12 ; /* 0x000000081c0c7825 */
/* 0x000fe200078e020c */
/*03a0*/ LDG.E.64 R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f28000c1e1b00 */
/*03b0*/ LDG.E.64 R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ DADD R22, -R24, R22 ; /* 0x0000000018167229 */
/* 0x008f0c0000000116 */
/*03d0*/ DFMA R20, -R22, c[0x0][0x170], R20 ; /* 0x00005c0016147a2b */
/* 0x010fc80000000114 */
/*03e0*/ DADD R16, -R18, R16 ; /* 0x0000000012107229 */
/* 0x004e0c0000000110 */
/*03f0*/ DFMA R18, -R16, c[0x0][0x178], R20 ; /* 0x00005e0010127a2b */
/* 0x0010640000000114 */
/*0400*/ LDG.E.64 R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x001eaa000c1e1b00 */
/*0410*/ STG.E.64 [R10.64], R18 ; /* 0x000000120a007986 */
/* 0x0021e8000c101b04 */
/*0420*/ LDG.E.64 R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R22, [R8.64+0x8] ; /* 0x0000080408167981 */
/* 0x000ee8000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R14.64+0x8] ; /* 0x000008040e107981 */
/* 0x000f28000c1e1b00 */
/*0450*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008040c127981 */
/* 0x001f22000c1e1b00 */
/*0460*/ DADD R22, -R24, R22 ; /* 0x0000000018167229 */
/* 0x008e8c0000000116 */
/*0470*/ DFMA R20, -R22, c[0x0][0x170], R20 ; /* 0x00005c0016147a2b */
/* 0x004fc80000000114 */
/*0480*/ DADD R16, -R18, R16 ; /* 0x0000000012107229 */
/* 0x010e0c0000000110 */
/*0490*/ DFMA R20, -R16, c[0x0][0x178], R20 ; /* 0x00005e0010147a2b */
/* 0x001e0e0000000114 */
/*04a0*/ STG.E.64 [R10.64+0x8], R20 ; /* 0x000008140a007986 */
/* 0x0011e8000c101b04 */
/*04b0*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000ea8000c1e1b00 */
/*04c0*/ LDG.E.64 R18, [R8.64+0x10] ; /* 0x0000100408127981 */
/* 0x000ea8000c1e1b00 */
/*04d0*/ LDG.E.64 R22, [R12.64+0x10] ; /* 0x000010040c167981 */
/* 0x000ee8000c1e1b00 */
/*04e0*/ LDG.E.64 R20, [R10.64+0x10] ; /* 0x000010040a147981 */
/* 0x001f28000c1e1b00 */
/*04f0*/ LDG.E.64 R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000ee2000c1e1b00 */
/*0500*/ DADD R16, -R16, R18 ; /* 0x0000000010107229 */
/* 0x004f0c0000000112 */
/*0510*/ DFMA R16, -R16, c[0x0][0x170], R20 ; /* 0x00005c0010107a2b */
/* 0x010fc80000000114 */
/*0520*/ DADD R22, -R22, R24 ; /* 0x0000000016167229 */
/* 0x0080640000000118 */
/*0530*/ LDG.E.64 R24, [R10.64+0x18] ; /* 0x000018040a187981 */
/* 0x001ea8000c1e1b00 */
/*0540*/ DFMA R22, -R22, c[0x0][0x178], R16 ; /* 0x00005e0016167a2b */
/* 0x002e0e0000000110 */
/*0550*/ STG.E.64 [R10.64+0x10], R22 ; /* 0x000010160a007986 */
/* 0x0011e8000c101b04 */
/*0560*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000ee8000c1e1b00 */
/*0570*/ LDG.E.64 R18, [R8.64+0x18] ; /* 0x0000180408127981 */
/* 0x000ee8000c1e1b00 */
/*0580*/ LDG.E.64 R20, [R14.64+0x18] ; /* 0x000018040e147981 */
/* 0x000328000c1e1b00 */
/*0590*/ LDG.E.64 R22, [R12.64+0x18] ; /* 0x000018040c167981 */
/* 0x001f22000c1e1b00 */
/*05a0*/ IADD3 R29, R29, -0x4, RZ ; /* 0xfffffffc1d1d7810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.NE.AND P0, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fe20003f05270 */
/*05c0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe4000ff1e03f */
/*05d0*/ UIADD3 UR8, UP1, UR8, 0x20, URZ ; /* 0x0000002008087890 */
/* 0x000fe4000ff3e03f */
/*05e0*/ UIADD3 UR10, UP2, UR10, 0x20, URZ ; /* 0x000000200a0a7890 */
/* 0x000fe4000ff5e03f */
/*05f0*/ UIADD3 UR12, UP3, UR12, 0x20, URZ ; /* 0x000000200c0c7890 */
/* 0x000fe2000ff7e03f */
/*0600*/ IADD3 R14, P2, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x002fe20007f5e0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0620*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fc40008ffe43f */
/*0630*/ UIADD3.X UR11, URZ, UR11, URZ, UP2, !UPT ; /* 0x0000000b3f0b7290 */
/* 0x000fe400097fe43f */
/*0640*/ UIADD3.X UR13, URZ, UR13, URZ, UP3, !UPT ; /* 0x0000000d3f0d7290 */
/* 0x000fe20009ffe43f */
/*0650*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe400017fe4ff */
/*0660*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fe20007ffe0ff */
/*0670*/ DADD R16, -R16, R18 ; /* 0x0000000010107229 */
/* 0x008e8c0000000112 */
/*0680*/ DFMA R16, -R16, c[0x0][0x170], R24 ; /* 0x00005c0010107a2b */
/* 0x004fc80000000118 */
/*0690*/ DADD R20, -R22, R20 ; /* 0x0000000016147229 */
/* 0x010e0c0000000114 */
/*06a0*/ DFMA R16, -R20, c[0x0][0x178], R16 ; /* 0x00005e0014107a2b */
/* 0x001e0e0000000110 */
/*06b0*/ STG.E.64 [R10.64+0x18], R16 ; /* 0x000018100a007986 */
/* 0x0011e2000c101b04 */
/*06c0*/ @P0 BRA 0x2b0 ; /* 0xfffffbe000000947 */
/* 0x000fea000383ffff */
/*06d0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R3, R3, c[0x0][0x160], RZ ; /* 0x0000580003037a10 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff077624 */
/* 0x000fe200078e00ff */
/*0700*/ IADD3 R9, R5.reuse, c[0x0][0x160], RZ ; /* 0x0000580005097a10 */
/* 0x040fe40007ffe0ff */
/*0710*/ IADD3 R5, R5, c[0x0][0x164], RZ ; /* 0x0000590005057a10 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x000fe200078e0203 */
/*0730*/ LEA R3, R7, c[0x0][0x164], 0x1 ; /* 0x0000590007037a11 */
/* 0x000fe200078e08ff */
/*0740*/ IMAD R9, R2.reuse, c[0x0][0x0], R9 ; /* 0x0000000002097a24 */
/* 0x040fe200078e0209 */
/*0750*/ MOV R21, 0x8 ; /* 0x0000000800157802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD R5, R2, c[0x0][0x0], R5 ; /* 0x0000000002057a24 */
/* 0x000fc400078e0205 */
/*0770*/ IMAD R2, R0.reuse, R3.reuse, R9 ; /* 0x0000000300027224 */
/* 0x0c0fe400078e0209 */
/*0780*/ IMAD R0, R0, R3, R5 ; /* 0x0000000300007224 */
/* 0x000fe400078e0205 */
/*0790*/ IMAD R6, R2.reuse, c[0x0][0x16c], R27 ; /* 0x00005b0002067a24 */
/* 0x040fe200078e021b */
/*07a0*/ IADD3 R20, R2, 0x1, RZ ; /* 0x0000000102147810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ IMAD R0, R7, 0x3, R0 ; /* 0x0000000307007824 */
/* 0x000fe400078e0200 */
/*07c0*/ IMAD.WIDE R2, R6, R21, c[0x0][0x1a0] ; /* 0x0000680006027625 */
/* 0x000fc800078e0215 */
/*07d0*/ IMAD R18, R0, c[0x0][0x16c], R27.reuse ; /* 0x00005b0000127a24 */
/* 0x100fe200078e021b */
/*07e0*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe20000000f00 */
/*07f0*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0002 */
/*0800*/ IMAD R20, R20, c[0x0][0x16c], R27 ; /* 0x00005b0014147a24 */
/* 0x000fe400078e021b */
/*0810*/ IMAD.WIDE R2, R6, R21, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x000fc800078e0215 */
/*0820*/ IMAD.WIDE R16, R6, R21, c[0x0][0x190] ; /* 0x0000640006107625 */
/* 0x001fc800078e0215 */
/*0830*/ IMAD.WIDE R18, R18, R21, c[0x0][0x198] ; /* 0x0000660012127625 */
/* 0x000fc800078e0215 */
/*0840*/ IMAD.WIDE R20, R20, R21, c[0x0][0x188] ; /* 0x0000620014147625 */
/* 0x000fc800078e0215 */
/*0850*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0002 */
/*0860*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0000a2000c1e1b00 */
/*0870*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe20000000f00 */
/*0880*/ IMAD.MOV.U32 R22, RZ, RZ, R0 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0000 */
/*0890*/ MOV R23, R5 ; /* 0x0000000500177202 */
/* 0x000fe20000000f00 */
/*08a0*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x0002a8000c1e1b00 */
/*08b0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ee8000c1e1b00 */
/*08c0*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0008e8000c1e1b00 */
/*08d0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000f62000c1e1b00 */
/*08e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc40007ffe0ff */
/*08f0*/ IADD3 R20, P2, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x002fe40007f5e0ff */
/*0900*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0910*/ IADD3 R18, P1, R18, 0x8, RZ ; /* 0x0000000812127810 */
/* 0x010fe20007f3e0ff */
/*0920*/ IMAD.X R21, RZ, RZ, R21, P2 ; /* 0x000000ffff157224 */
/* 0x000fe200010e0615 */
/*0930*/ IADD3 R0, P3, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f7e0ff */
/*0940*/ IADD3 R16, P4, R16, 0x8, RZ ; /* 0x0000000810107810 */
/* 0x001fe40007f9e0ff */
/*0950*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fc40000ffe4ff */
/*0960*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40001ffe4ff */
/*0970*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*0980*/ DADD R12, -R12, R14 ; /* 0x000000000c0c7229 */
/* 0x004f48000000010e */
/*0990*/ DADD R8, -R8, R10 ; /* 0x0000000008087229 */
/* 0x008fc8000000010a */
/*09a0*/ DFMA R6, -R12, c[0x0][0x170], R6 ; /* 0x00005c000c067a2b */
/* 0x020e0c0000000106 */
/*09b0*/ DFMA R6, -R8, c[0x0][0x178], R6 ; /* 0x00005e0008067a2b */
/* 0x0010640000000106 */
/*09c0*/ IADD3 R8, P5, R2, 0x8, RZ ; /* 0x0000000802087810 */
/* 0x001fca0007fbe0ff */
/*09d0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0021e4000c101b04 */
/*09e0*/ IMAD.X R3, RZ, RZ, R3, P5 ; /* 0x000000ffff037224 */
/* 0x001fe200028e0603 */
/*09f0*/ @P0 BRA 0x860 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0a00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a10*/ BRA 0xa10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda2(int mbc, int mx, int my, int meqn, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int ix = threadIdx.x + blockIdx.x*blockDim.x;
int iy = threadIdx.y + blockIdx.y*blockDim.y;
if (ix < mx && iy < my)
{
int x_stride = meqn;
int y_stride = (2*mbc + mx)*x_stride;
int I_q = (ix+mbc)*x_stride + (iy+mbc)*y_stride;
int mq;
for(mq = 0; mq < meqn; mq++)
{
int i = I_q+mq;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
}
}
}
|
.file "tmpxft_000c36ad_00000000-6_cudaclaw5_update_q_cuda2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_
.type _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_, @function
_Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movl %edx, 68(%rsp)
movl %ecx, 64(%rsp)
movsd %xmm0, 56(%rsp)
movsd %xmm1, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_, .-_Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_
.globl _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.type _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, @function
_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, .-_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda2(int mbc, int mx, int my, int meqn, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int ix = threadIdx.x + blockIdx.x*blockDim.x;
int iy = threadIdx.y + blockIdx.y*blockDim.y;
if (ix < mx && iy < my)
{
int x_stride = meqn;
int y_stride = (2*mbc + mx)*x_stride;
int I_q = (ix+mbc)*x_stride + (iy+mbc)*y_stride;
int mq;
for(mq = 0; mq < meqn; mq++)
{
int i = I_q+mq;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
}
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda2(int mbc, int mx, int my, int meqn, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int ix = threadIdx.x + blockIdx.x*blockDim.x;
int iy = threadIdx.y + blockIdx.y*blockDim.y;
if (ix < mx && iy < my)
{
int x_stride = meqn;
int y_stride = (2*mbc + mx)*x_stride;
int I_q = (ix+mbc)*x_stride + (iy+mbc)*y_stride;
int mq;
for(mq = 0; mq < meqn; mq++)
{
int i = I_q+mq;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda2(int mbc, int mx, int my, int meqn, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int ix = threadIdx.x + blockIdx.x*blockDim.x;
int iy = threadIdx.y + blockIdx.y*blockDim.y;
if (ix < mx && iy < my)
{
int x_stride = meqn;
int y_stride = (2*mbc + mx)*x_stride;
int I_q = (ix+mbc)*x_stride + (iy+mbc)*y_stride;
int mq;
for(mq = 0; mq < meqn; mq++)
{
int i = I_q+mq;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.globl _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.p2align 8
.type _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_,@function
_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b64 s[12:13], s[0:1], 0x4
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
v_add_nc_u32_e32 v1, s14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s12, v1
v_cmp_gt_i32_e64 s2, s13, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s3, v0
v_add_nc_u32_e32 v0, s3, v1
s_lshl_b32 s4, s3, 1
v_add_nc_u32_e32 v4, s3, v2
s_add_i32 s13, s4, s12
s_load_b256 s[4:11], s[0:1], 0x10
v_mul_lo_u32 v1, v3, s13
v_mul_lo_u32 v0, v0, s2
s_mul_i32 s13, s13, s2
s_load_b64 s[0:1], s[0:1], 0x40
s_mul_i32 s3, s3, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add3_u32 v5, v4, v1, s14
v_add3_u32 v6, v2, s12, v1
v_mad_u64_u32 v[1:2], null, v3, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, s2, v5, s[2:3]
v_add3_u32 v0, s3, s14, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v6, s2, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[8:9], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[10:11], 3, v[3:4]
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v9, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
v_lshlrev_b64 v[8:9], 3, v[6:7]
v_add_co_u32 v6, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s18, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v9, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
global_load_b64 v[10:11], v[6:7], off
global_load_b64 v[12:13], v[2:3], off
global_load_b64 v[14:15], v[8:9], off
global_load_b64 v[16:17], v[4:5], off
global_load_b64 v[18:19], v[0:1], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(3)
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_waitcnt vmcnt(1)
v_add_f64 v[12:13], v[14:15], -v[16:17]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], s[4:5], v[18:19]
v_fma_f64 v[10:11], -v[12:13], s[6:7], v[10:11]
global_store_b64 v[0:1], v[10:11], off
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, .Lfunc_end0-_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaclaw5_update_q_cuda2(int mbc, int mx, int my, int meqn, double dtdx, double dtdy, double* qold, double* fm, double* fp, double* gm, double* gp)
{
int ix = threadIdx.x + blockIdx.x*blockDim.x;
int iy = threadIdx.y + blockIdx.y*blockDim.y;
if (ix < mx && iy < my)
{
int x_stride = meqn;
int y_stride = (2*mbc + mx)*x_stride;
int I_q = (ix+mbc)*x_stride + (iy+mbc)*y_stride;
int mq;
for(mq = 0; mq < meqn; mq++)
{
int i = I_q+mq;
qold[i] = qold[i] - dtdx * (fm[i+x_stride] - fp[i])
- dtdy * (gm[i+y_stride] - gp[i]);
}
}
}
|
.text
.file "cudaclaw5_update_q_cuda2.hip"
.globl _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_ # -- Begin function _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.p2align 4, 0x90
.type _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_,@function
_Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_: # @_Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 200(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, .Lfunc_end0-_Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_,@object # @_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.p2align 3, 0x0
_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_:
.quad _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.size _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R6, R0, c[0x0][0x4], R3 ; /* 0x0000010000067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R2, c[0x0][0x0], R5 ; /* 0x0000000002047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fca00078e00ff */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0100*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0120*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fd60003f25270 */
/*0130*/ @!P0 BRA 0x6d0 ; /* 0x0000059000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R7, R3, c[0x0][0x160], RZ ; /* 0x0000580003077a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R11, R5.reuse, c[0x0][0x164], RZ ; /* 0x00005900050b7a10 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*0180*/ MOV R14, 0x8 ; /* 0x00000008000e7802 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD R6, R0, c[0x0][0x4], R7 ; /* 0x0000010000067a24 */
/* 0x000fe200078e0207 */
/*01a0*/ IADD3 R7, R5, c[0x0][0x160], RZ ; /* 0x0000580005077a10 */
/* 0x000fe20007ffe0ff */
/*01b0*/ IMAD R11, R2, c[0x0][0x0], R11 ; /* 0x00000000020b7a24 */
/* 0x000fe200078e020b */
/*01c0*/ LEA R9, R8, c[0x0][0x164], 0x1 ; /* 0x0000590008097a11 */
/* 0x000fe200078e08ff */
/*01d0*/ ULDC.64 UR12, c[0x0][0x188] ; /* 0x00006200000c7ab9 */
/* 0x000fe20000000a00 */
/*01e0*/ IADD3 R29, -R4, c[0x0][0x16c], RZ ; /* 0x00005b00041d7a10 */
/* 0x000fe20007ffe1ff */
/*01f0*/ IMAD R7, R2, c[0x0][0x0], R7 ; /* 0x0000000002077a24 */
/* 0x000fe200078e0207 */
/*0200*/ ULDC.64 UR10, c[0x0][0x180] ; /* 0x00006000000a7ab9 */
/* 0x000fe20000000a00 */
/*0210*/ IMAD R11, R6.reuse, R9.reuse, R11 ; /* 0x00000009060b7224 */
/* 0x0c0fe200078e020b */
/*0220*/ ULDC.64 UR8, c[0x0][0x190] ; /* 0x0000640000087ab9 */
/* 0x000fe20000000a00 */
/*0230*/ IMAD R7, R6, R9, R7 ; /* 0x0000000906077224 */
/* 0x000fe200078e0207 */
/*0240*/ ULDC.64 UR6, c[0x0][0x1a0] ; /* 0x0000680000067ab9 */
/* 0x000fe20000000a00 */
/*0250*/ IMAD R11, R8, 0x3, R11 ; /* 0x00000003080b7824 */
/* 0x000fc400078e020b */
/*0260*/ IMAD R28, R7.reuse, c[0x0][0x16c], RZ ; /* 0x00005b00071c7a24 */
/* 0x040fe200078e02ff */
/*0270*/ IADD3 R26, R7, 0x1, RZ ; /* 0x00000001071a7810 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD R11, R11, c[0x0][0x16c], RZ ; /* 0x00005b000b0b7a24 */
/* 0x000fc800078e02ff */
/*0290*/ IMAD.WIDE R14, R11, R14, c[0x0][0x198] ; /* 0x000066000b0e7625 */
/* 0x000fc800078e020e */
/*02a0*/ IMAD R26, R26, c[0x0][0x16c], RZ ; /* 0x00005b001a1a7a24 */
/* 0x000fe400078e02ff */
/*02b0*/ MOV R8, UR12 ; /* 0x0000000c00087c02 */
/* 0x000fe20008000f00 */
/*02c0*/ IMAD.U32 R9, RZ, RZ, UR13 ; /* 0x0000000dff097e24 */
/* 0x000fe2000f8e00ff */
/*02d0*/ MOV R6, UR8 ; /* 0x0000000800067c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R7, RZ, RZ, UR9 ; /* 0x00000009ff077e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R10, UR10 ; /* 0x0000000a000a7c02 */
/* 0x001fe20008000f00 */
/*0300*/ IMAD.WIDE R8, R26, 0x8, R8 ; /* 0x000000081a087825 */
/* 0x000fe200078e0208 */
/*0310*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0320*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1b00 */
/*0330*/ IMAD.WIDE R6, R28, 0x8, R6 ; /* 0x000000081c067825 */
/* 0x000fe400078e0206 */
/*0340*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ee4000c1e1b00 */
/*0350*/ IMAD.U32 R11, RZ, RZ, UR11 ; /* 0x0000000bff0b7e24 */
/* 0x000fc4000f8e00ff */
/*0360*/ IMAD.U32 R13, RZ, RZ, UR7 ; /* 0x00000007ff0d7e24 */
/* 0x000fe2000f8e00ff */
/*0370*/ LDG.E.64 R24, [R6.64] ; /* 0x0000000406187981 */
/* 0x000ee2000c1e1b00 */
/*0380*/ IMAD.WIDE R10, R28, 0x8, R10 ; /* 0x000000081c0a7825 */
/* 0x000fc800078e020a */
/*0390*/ IMAD.WIDE R12, R28, 0x8, R12 ; /* 0x000000081c0c7825 */
/* 0x000fe200078e020c */
/*03a0*/ LDG.E.64 R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f28000c1e1b00 */
/*03b0*/ LDG.E.64 R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ DADD R22, -R24, R22 ; /* 0x0000000018167229 */
/* 0x008f0c0000000116 */
/*03d0*/ DFMA R20, -R22, c[0x0][0x170], R20 ; /* 0x00005c0016147a2b */
/* 0x010fc80000000114 */
/*03e0*/ DADD R16, -R18, R16 ; /* 0x0000000012107229 */
/* 0x004e0c0000000110 */
/*03f0*/ DFMA R18, -R16, c[0x0][0x178], R20 ; /* 0x00005e0010127a2b */
/* 0x0010640000000114 */
/*0400*/ LDG.E.64 R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x001eaa000c1e1b00 */
/*0410*/ STG.E.64 [R10.64], R18 ; /* 0x000000120a007986 */
/* 0x0021e8000c101b04 */
/*0420*/ LDG.E.64 R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000ee8000c1e1b00 */
/*0430*/ LDG.E.64 R22, [R8.64+0x8] ; /* 0x0000080408167981 */
/* 0x000ee8000c1e1b00 */
/*0440*/ LDG.E.64 R16, [R14.64+0x8] ; /* 0x000008040e107981 */
/* 0x000f28000c1e1b00 */
/*0450*/ LDG.E.64 R18, [R12.64+0x8] ; /* 0x000008040c127981 */
/* 0x001f22000c1e1b00 */
/*0460*/ DADD R22, -R24, R22 ; /* 0x0000000018167229 */
/* 0x008e8c0000000116 */
/*0470*/ DFMA R20, -R22, c[0x0][0x170], R20 ; /* 0x00005c0016147a2b */
/* 0x004fc80000000114 */
/*0480*/ DADD R16, -R18, R16 ; /* 0x0000000012107229 */
/* 0x010e0c0000000110 */
/*0490*/ DFMA R20, -R16, c[0x0][0x178], R20 ; /* 0x00005e0010147a2b */
/* 0x001e0e0000000114 */
/*04a0*/ STG.E.64 [R10.64+0x8], R20 ; /* 0x000008140a007986 */
/* 0x0011e8000c101b04 */
/*04b0*/ LDG.E.64 R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000ea8000c1e1b00 */
/*04c0*/ LDG.E.64 R18, [R8.64+0x10] ; /* 0x0000100408127981 */
/* 0x000ea8000c1e1b00 */
/*04d0*/ LDG.E.64 R22, [R12.64+0x10] ; /* 0x000010040c167981 */
/* 0x000ee8000c1e1b00 */
/*04e0*/ LDG.E.64 R20, [R10.64+0x10] ; /* 0x000010040a147981 */
/* 0x001f28000c1e1b00 */
/*04f0*/ LDG.E.64 R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000ee2000c1e1b00 */
/*0500*/ DADD R16, -R16, R18 ; /* 0x0000000010107229 */
/* 0x004f0c0000000112 */
/*0510*/ DFMA R16, -R16, c[0x0][0x170], R20 ; /* 0x00005c0010107a2b */
/* 0x010fc80000000114 */
/*0520*/ DADD R22, -R22, R24 ; /* 0x0000000016167229 */
/* 0x0080640000000118 */
/*0530*/ LDG.E.64 R24, [R10.64+0x18] ; /* 0x000018040a187981 */
/* 0x001ea8000c1e1b00 */
/*0540*/ DFMA R22, -R22, c[0x0][0x178], R16 ; /* 0x00005e0016167a2b */
/* 0x002e0e0000000110 */
/*0550*/ STG.E.64 [R10.64+0x10], R22 ; /* 0x000010160a007986 */
/* 0x0011e8000c101b04 */
/*0560*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000ee8000c1e1b00 */
/*0570*/ LDG.E.64 R18, [R8.64+0x18] ; /* 0x0000180408127981 */
/* 0x000ee8000c1e1b00 */
/*0580*/ LDG.E.64 R20, [R14.64+0x18] ; /* 0x000018040e147981 */
/* 0x000328000c1e1b00 */
/*0590*/ LDG.E.64 R22, [R12.64+0x18] ; /* 0x000018040c167981 */
/* 0x001f22000c1e1b00 */
/*05a0*/ IADD3 R29, R29, -0x4, RZ ; /* 0xfffffffc1d1d7810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ ISETP.NE.AND P0, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fe20003f05270 */
/*05c0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe4000ff1e03f */
/*05d0*/ UIADD3 UR8, UP1, UR8, 0x20, URZ ; /* 0x0000002008087890 */
/* 0x000fe4000ff3e03f */
/*05e0*/ UIADD3 UR10, UP2, UR10, 0x20, URZ ; /* 0x000000200a0a7890 */
/* 0x000fe4000ff5e03f */
/*05f0*/ UIADD3 UR12, UP3, UR12, 0x20, URZ ; /* 0x000000200c0c7890 */
/* 0x000fe2000ff7e03f */
/*0600*/ IADD3 R14, P2, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x002fe20007f5e0ff */
/*0610*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0620*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fc40008ffe43f */
/*0630*/ UIADD3.X UR11, URZ, UR11, URZ, UP2, !UPT ; /* 0x0000000b3f0b7290 */
/* 0x000fe400097fe43f */
/*0640*/ UIADD3.X UR13, URZ, UR13, URZ, UP3, !UPT ; /* 0x0000000d3f0d7290 */
/* 0x000fe20009ffe43f */
/*0650*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe400017fe4ff */
/*0660*/ IADD3 R27, R27, 0x4, RZ ; /* 0x000000041b1b7810 */
/* 0x000fe20007ffe0ff */
/*0670*/ DADD R16, -R16, R18 ; /* 0x0000000010107229 */
/* 0x008e8c0000000112 */
/*0680*/ DFMA R16, -R16, c[0x0][0x170], R24 ; /* 0x00005c0010107a2b */
/* 0x004fc80000000118 */
/*0690*/ DADD R20, -R22, R20 ; /* 0x0000000016147229 */
/* 0x010e0c0000000114 */
/*06a0*/ DFMA R16, -R20, c[0x0][0x178], R16 ; /* 0x00005e0014107a2b */
/* 0x001e0e0000000110 */
/*06b0*/ STG.E.64 [R10.64+0x18], R16 ; /* 0x000018100a007986 */
/* 0x0011e2000c101b04 */
/*06c0*/ @P0 BRA 0x2b0 ; /* 0xfffffbe000000947 */
/* 0x000fea000383ffff */
/*06d0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*06e0*/ IADD3 R3, R3, c[0x0][0x160], RZ ; /* 0x0000580003037a10 */
/* 0x000fe20007ffe0ff */
/*06f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff077624 */
/* 0x000fe200078e00ff */
/*0700*/ IADD3 R9, R5.reuse, c[0x0][0x160], RZ ; /* 0x0000580005097a10 */
/* 0x040fe40007ffe0ff */
/*0710*/ IADD3 R5, R5, c[0x0][0x164], RZ ; /* 0x0000590005057a10 */
/* 0x000fe20007ffe0ff */
/*0720*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x000fe200078e0203 */
/*0730*/ LEA R3, R7, c[0x0][0x164], 0x1 ; /* 0x0000590007037a11 */
/* 0x000fe200078e08ff */
/*0740*/ IMAD R9, R2.reuse, c[0x0][0x0], R9 ; /* 0x0000000002097a24 */
/* 0x040fe200078e0209 */
/*0750*/ MOV R21, 0x8 ; /* 0x0000000800157802 */
/* 0x000fe20000000f00 */
/*0760*/ IMAD R5, R2, c[0x0][0x0], R5 ; /* 0x0000000002057a24 */
/* 0x000fc400078e0205 */
/*0770*/ IMAD R2, R0.reuse, R3.reuse, R9 ; /* 0x0000000300027224 */
/* 0x0c0fe400078e0209 */
/*0780*/ IMAD R0, R0, R3, R5 ; /* 0x0000000300007224 */
/* 0x000fe400078e0205 */
/*0790*/ IMAD R6, R2.reuse, c[0x0][0x16c], R27 ; /* 0x00005b0002067a24 */
/* 0x040fe200078e021b */
/*07a0*/ IADD3 R20, R2, 0x1, RZ ; /* 0x0000000102147810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ IMAD R0, R7, 0x3, R0 ; /* 0x0000000307007824 */
/* 0x000fe400078e0200 */
/*07c0*/ IMAD.WIDE R2, R6, R21, c[0x0][0x1a0] ; /* 0x0000680006027625 */
/* 0x000fc800078e0215 */
/*07d0*/ IMAD R18, R0, c[0x0][0x16c], R27.reuse ; /* 0x00005b0000127a24 */
/* 0x100fe200078e021b */
/*07e0*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe20000000f00 */
/*07f0*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0002 */
/*0800*/ IMAD R20, R20, c[0x0][0x16c], R27 ; /* 0x00005b0014147a24 */
/* 0x000fe400078e021b */
/*0810*/ IMAD.WIDE R2, R6, R21, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x000fc800078e0215 */
/*0820*/ IMAD.WIDE R16, R6, R21, c[0x0][0x190] ; /* 0x0000640006107625 */
/* 0x001fc800078e0215 */
/*0830*/ IMAD.WIDE R18, R18, R21, c[0x0][0x198] ; /* 0x0000660012127625 */
/* 0x000fc800078e0215 */
/*0840*/ IMAD.WIDE R20, R20, R21, c[0x0][0x188] ; /* 0x0000620014147625 */
/* 0x000fc800078e0215 */
/*0850*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0002 */
/*0860*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0000a2000c1e1b00 */
/*0870*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe20000000f00 */
/*0880*/ IMAD.MOV.U32 R22, RZ, RZ, R0 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0000 */
/*0890*/ MOV R23, R5 ; /* 0x0000000500177202 */
/* 0x000fe20000000f00 */
/*08a0*/ LDG.E.64 R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x0002a8000c1e1b00 */
/*08b0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000ee8000c1e1b00 */
/*08c0*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0008e8000c1e1b00 */
/*08d0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000f62000c1e1b00 */
/*08e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc40007ffe0ff */
/*08f0*/ IADD3 R20, P2, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x002fe40007f5e0ff */
/*0900*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0910*/ IADD3 R18, P1, R18, 0x8, RZ ; /* 0x0000000812127810 */
/* 0x010fe20007f3e0ff */
/*0920*/ IMAD.X R21, RZ, RZ, R21, P2 ; /* 0x000000ffff157224 */
/* 0x000fe200010e0615 */
/*0930*/ IADD3 R0, P3, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f7e0ff */
/*0940*/ IADD3 R16, P4, R16, 0x8, RZ ; /* 0x0000000810107810 */
/* 0x001fe40007f9e0ff */
/*0950*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fc40000ffe4ff */
/*0960*/ IADD3.X R5, RZ, R5, RZ, P3, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40001ffe4ff */
/*0970*/ IADD3.X R17, RZ, R17, RZ, P4, !PT ; /* 0x00000011ff117210 */
/* 0x000fe200027fe4ff */
/*0980*/ DADD R12, -R12, R14 ; /* 0x000000000c0c7229 */
/* 0x004f48000000010e */
/*0990*/ DADD R8, -R8, R10 ; /* 0x0000000008087229 */
/* 0x008fc8000000010a */
/*09a0*/ DFMA R6, -R12, c[0x0][0x170], R6 ; /* 0x00005c000c067a2b */
/* 0x020e0c0000000106 */
/*09b0*/ DFMA R6, -R8, c[0x0][0x178], R6 ; /* 0x00005e0008067a2b */
/* 0x0010640000000106 */
/*09c0*/ IADD3 R8, P5, R2, 0x8, RZ ; /* 0x0000000802087810 */
/* 0x001fca0007fbe0ff */
/*09d0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0021e4000c101b04 */
/*09e0*/ IMAD.X R3, RZ, RZ, R3, P5 ; /* 0x000000ffff037224 */
/* 0x001fe200028e0603 */
/*09f0*/ @P0 BRA 0x860 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0a00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a10*/ BRA 0xa10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.globl _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.p2align 8
.type _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_,@function
_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b64 s[12:13], s[0:1], 0x4
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
v_add_nc_u32_e32 v1, s14, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s12, v1
v_cmp_gt_i32_e64 s2, s13, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x0
s_load_b128 s[16:19], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s3, v0
v_add_nc_u32_e32 v0, s3, v1
s_lshl_b32 s4, s3, 1
v_add_nc_u32_e32 v4, s3, v2
s_add_i32 s13, s4, s12
s_load_b256 s[4:11], s[0:1], 0x10
v_mul_lo_u32 v1, v3, s13
v_mul_lo_u32 v0, v0, s2
s_mul_i32 s13, s13, s2
s_load_b64 s[0:1], s[0:1], 0x40
s_mul_i32 s3, s3, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add3_u32 v5, v4, v1, s14
v_add3_u32 v6, v2, s12, v1
v_mad_u64_u32 v[1:2], null, v3, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, s2, v5, s[2:3]
v_add3_u32 v0, s3, s14, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v6, s2, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[8:9], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[10:11], 3, v[3:4]
v_ashrrev_i32_e32 v7, 31, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v9, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
v_lshlrev_b64 v[8:9], 3, v[6:7]
v_add_co_u32 v6, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v7, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s18, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s19, v9, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
global_load_b64 v[10:11], v[6:7], off
global_load_b64 v[12:13], v[2:3], off
global_load_b64 v[14:15], v[8:9], off
global_load_b64 v[16:17], v[4:5], off
global_load_b64 v[18:19], v[0:1], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v8, 8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(3)
v_add_f64 v[10:11], v[10:11], -v[12:13]
s_waitcnt vmcnt(1)
v_add_f64 v[12:13], v[14:15], -v[16:17]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], s[4:5], v[18:19]
v_fma_f64 v[10:11], -v[12:13], s[6:7], v[10:11]
global_store_b64 v[0:1], v[10:11], off
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, .Lfunc_end0-_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000c36ad_00000000-6_cudaclaw5_update_q_cuda2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_
.type _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_, @function
_Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movl %esi, 72(%rsp)
movl %edx, 68(%rsp)
movl %ecx, 64(%rsp)
movsd %xmm0, 56(%rsp)
movsd %xmm1, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 256(%rsp), %rax
movq %rax, 24(%rsp)
movq 264(%rsp), %rax
movq %rax, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_, .-_Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_
.globl _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.type _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, @function
_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_iiiiddPdS_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, .-_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cudaclaw5_update_q_cuda2.hip"
.globl _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_ # -- Begin function _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.p2align 4, 0x90
.type _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_,@function
_Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_: # @_Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 200(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, .Lfunc_end0-_Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_,@object # @_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.p2align 3, 0x0
_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_:
.quad _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.size _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24cudaclaw5_update_q_cuda2iiiiddPdS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void reduce(int* input, int n){
unsigned int tid=threadIdx.x;
unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
unsigned int offset = blockDim.x * blockIdx.x;
__syncthreads();
for(unsigned int s=1; s<blockDim.x; s*=2){
if(tid % (2*s)==0){
input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
}
__syncthreads();
}
}
int main(int argc, char** argv){
struct timeval start, end, t_start, t_end;
int i,n = atoi(argv[1]);
int seed= atoi(argv[2]);
int * array;
int blocks;
int result=0;
int threads=10;
array=(int*)malloc(n * sizeof(int));
srand(seed);
for(i=0;i<n;i++){
array[i]=random();
printf("a[%d]= %d\n",i,array[i]);
}
int *gpu_array;
gettimeofday(&t_start, NULL);
cudaMalloc(&gpu_array, n*sizeof(int));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(gpu_array, array, n*sizeof(int), cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
blocks= (n + threads -1)/threads;
reduce<<<blocks,threads>>>(gpu_array,n);
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
cudaMemcpy(array, gpu_array, n*sizeof(int), cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
for(i=0;i<n;i+=threads){
result = result ^ array[i];
printf("result= %d\n",result);
}
gettimeofday(&t_end, NULL);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(gpu_array);
}
|
code for sm_80
Function : _Z6reducePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc80007ffe0ff */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06070 */
/*0050*/ R2UR UR41, R1 ; /* 0x00000000012973c2 */
/* 0x00005800000e0000 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2UR UR38, SR_CTAID.X ; /* 0x00000000002679c3 */
/* 0x001e220000002500 */
/*0080*/ S2R R18, SR_TID.X ; /* 0x0000000000127919 */
/* 0x000ea20000002100 */
/*0090*/ ULDC UR39, c[0x0][0x0] ; /* 0x0000000000277ab9 */
/* 0x000fe20000000800 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC UR4, c[0x0][0x20] ; /* 0x0000080000047ab9 */
/* 0x000fe40000000800 */
/*00c0*/ UIADD3 UR41, UP0, UR41, UR4, URZ ; /* 0x0000000429297290 */
/* 0x002fe4000ff1e03f */
/*00d0*/ ULDC UR42, c[0x0][0x24] ; /* 0x00000900002a7ab9 */
/* 0x000fe40000000800 */
/*00e0*/ UIADD3.X UR42, URZ, UR42, URZ, UP0, !UPT ; /* 0x0000002a3f2a7290 */
/* 0x000fc400087fe43f */
/*00f0*/ UMOV UR40, 0x1 ; /* 0x0000000100287882 */
/* 0x000fe40000000000 */
/*0100*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe40000000a00 */
/*0110*/ UIMAD UR38, UR38, UR39, URZ ; /* 0x00000027262672a4 */
/* 0x001fc8000f8e023f */
/*0120*/ UIADD3 UR39, UR38, UR39, URZ ; /* 0x0000002726277290 */
/* 0x000fe4000fffe03f */
/*0130*/ IADD3 R2, R18, UR38, RZ ; /* 0x0000002612027c10 */
/* 0x004fca000fffe0ff */
/*0140*/ IMAD.WIDE.U32 R16, R2, R17, c[0x0][0x160] ; /* 0x0000580002107625 */
/* 0x000fc800078e0011 */
/*0150*/ USHF.L.U32 UR43, UR40, 0x1, URZ ; /* 0x00000001282b7899 */
/* 0x000fcc000800063f */
/*0160*/ IMAD R3, RZ, RZ, -UR43 ; /* 0x8000002bff037e24 */
/* 0x000fe2000f8e02ff */
/*0170*/ ISETP.NE.U32.AND P1, PT, RZ, UR43, PT ; /* 0x0000002bff007c0c */
/* 0x000fe4000bf25070 */
/*0180*/ I2F.U32.RP R0, UR43 ; /* 0x0000002b00007d06 */
/* 0x000e300008209000 */
/*0190*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*01a0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*01d0*/ IMAD R3, R3, R5, RZ ; /* 0x0000000503037224 */
/* 0x002fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R5, R5, R3, R4 ; /* 0x0000000305057227 */
/* 0x000fcc00078e0004 */
/*01f0*/ IMAD.HI.U32 R5, R5, R18, RZ ; /* 0x0000001205057227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0210*/ IMAD R3, R5, UR43, R18 ; /* 0x0000002b05037c24 */
/* 0x000fca000f8e0212 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R3, UR43, PT ; /* 0x0000002b03007c0c */
/* 0x000fda000bf06070 */
/*0230*/ @P0 IADD3 R3, R3, -UR43, RZ ; /* 0x8000002b03030c10 */
/* 0x000fc8000fffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R3, UR43, PT ; /* 0x0000002b03007c0c */
/* 0x000fda000bf06070 */
/*0250*/ @P0 IADD3 R3, R3, -UR43, RZ ; /* 0x8000002b03030c10 */
/* 0x000fe4000fffe0ff */
/*0260*/ @!P1 LOP3.LUT R3, RZ, UR43, RZ, 0x33, !PT ; /* 0x0000002bff039c12 */
/* 0x000fc8000f8e33ff */
/*0270*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0280*/ @P0 BRA 0x430 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0290*/ IADD3 R10, R2, UR40, RZ ; /* 0x00000028020a7c10 */
/* 0x000fe2000fffe0ff */
/*02a0*/ LDG.E R3, [R16.64] ; /* 0x0000002410037981 */
/* 0x000ea6000c1e1900 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x168], PT ; /* 0x00005a000a007a0c */
/* 0x000fc80003f06070 */
/*02c0*/ ISETP.GE.U32.OR P0, PT, R10, UR39, P0 ; /* 0x000000270a007c0c */
/* 0x000fda0008706470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b8424 */
/* 0x000fc800078e00ff */
/*02e0*/ @!P0 IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a8625 */
/* 0x000fcc00078e000b */
/*02f0*/ @!P0 LDG.E R10, [R10.64] ; /* 0x000000240a0a8981 */
/* 0x000ea2000c1e1900 */
/*0300*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0310*/ IMAD.U32 R0, RZ, RZ, UR38 ; /* 0x00000026ff007e24 */
/* 0x000fca000f8e00ff */
/*0320*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0001e20000100800 */
/*0330*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0340*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.U32 R6, RZ, RZ, UR41 ; /* 0x00000029ff067e24 */
/* 0x000fe4000f8e00ff */
/*0370*/ IMAD.U32 R7, RZ, RZ, UR42 ; /* 0x0000002aff077e24 */
/* 0x000fe2000f8e00ff */
/*0380*/ @!P0 LOP3.LUT R3, R10, R3, RZ, 0x3c, !PT ; /* 0x000000030a038212 */
/* 0x004fca00078e3cff */
/*0390*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x0001e8000c101924 */
/*03a0*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e40000100a00 */
/*03b0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe40000000000 */
/*03c0*/ MOV R3, 0x430 ; /* 0x0000043000037802 */
/* 0x001fe40000000f00 */
/*03d0*/ MOV R20, 0x3b0 ; /* 0x000003b000147802 */
/* 0x000fe40000000f00 */
/*03e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0400*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0410*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0420*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0430*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe40003800000 */
/*0440*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0450*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0460*/ UISETP.GE.U32.AND UP0, UPT, UR43, UR4, UPT ; /* 0x000000042b00728c */
/* 0x000fca000bf06070 */
/*0470*/ UMOV UR40, UR43 ; /* 0x0000002b00287c82 */
/* 0x000fe20008000000 */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0490*/ @!P0 BRA 0x150 ; /* 0xfffffcb000008947 */
/* 0x000fea000383ffff */
/*04a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04b0*/ BRA 0x4b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void reduce(int* input, int n){
unsigned int tid=threadIdx.x;
unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
unsigned int offset = blockDim.x * blockIdx.x;
__syncthreads();
for(unsigned int s=1; s<blockDim.x; s*=2){
if(tid % (2*s)==0){
input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
}
__syncthreads();
}
}
int main(int argc, char** argv){
struct timeval start, end, t_start, t_end;
int i,n = atoi(argv[1]);
int seed= atoi(argv[2]);
int * array;
int blocks;
int result=0;
int threads=10;
array=(int*)malloc(n * sizeof(int));
srand(seed);
for(i=0;i<n;i++){
array[i]=random();
printf("a[%d]= %d\n",i,array[i]);
}
int *gpu_array;
gettimeofday(&t_start, NULL);
cudaMalloc(&gpu_array, n*sizeof(int));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(gpu_array, array, n*sizeof(int), cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
blocks= (n + threads -1)/threads;
reduce<<<blocks,threads>>>(gpu_array,n);
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
cudaMemcpy(array, gpu_array, n*sizeof(int), cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
for(i=0;i<n;i+=threads){
result = result ^ array[i];
printf("result= %d\n",result);
}
gettimeofday(&t_end, NULL);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(gpu_array);
}
|
.file "tmpxft_0019a067_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6reducePiiPii
.type _Z26__device_stub__Z6reducePiiPii, @function
_Z26__device_stub__Z6reducePiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6reducePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6reducePiiPii, .-_Z26__device_stub__Z6reducePiiPii
.globl _Z6reducePii
.type _Z6reducePii, @function
_Z6reducePii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6reducePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6reducePii, .-_Z6reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a[%d]= %d\n"
.LC1:
.string "cudaMalloc"
.LC2:
.string "Cuda Error: '%s' for %s\n"
.LC3:
.string "cudaMemcpy"
.LC4:
.string "kernel invocation"
.LC5:
.string "memcpy"
.LC6:
.string "result= %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Total time = %ld microsecs Processsing =%ld microsecs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movslq %r15d, %rax
salq $2, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
movl %ebx, %edi
call srand@PLT
testl %r15d, %r15d
jle .L12
leal -1(%r15), %r14d
movl $0, %ebx
leaq .LC0(%rip), %r13
.L13:
call random@PLT
movl %eax, %ecx
movl %eax, 0(%rbp,%rbx,4)
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %r14, %rax
jne .L13
.L12:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 24(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $10, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
leal 9(%r15), %edx
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L18
movl $0, %ebx
movl $0, %r13d
leaq .LC6(%rip), %r14
testl %r15d, %r15d
jle .L20
.L19:
xorl 0(%rbp,%rbx,4), %r13d
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $10, %rbx
cmpl %ebx, %r12d
jg .L19
.L20:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rcx
subq 32(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 56(%rsp), %rcx
subq 40(%rsp), %rcx
movq 80(%rsp), %rdx
subq 64(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 88(%rsp), %rdx
subq 72(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %r12d, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6reducePiiPii
jmp .L16
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6reducePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void reduce(int* input, int n){
unsigned int tid=threadIdx.x;
unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
unsigned int offset = blockDim.x * blockIdx.x;
__syncthreads();
for(unsigned int s=1; s<blockDim.x; s*=2){
if(tid % (2*s)==0){
input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
}
__syncthreads();
}
}
int main(int argc, char** argv){
struct timeval start, end, t_start, t_end;
int i,n = atoi(argv[1]);
int seed= atoi(argv[2]);
int * array;
int blocks;
int result=0;
int threads=10;
array=(int*)malloc(n * sizeof(int));
srand(seed);
for(i=0;i<n;i++){
array[i]=random();
printf("a[%d]= %d\n",i,array[i]);
}
int *gpu_array;
gettimeofday(&t_start, NULL);
cudaMalloc(&gpu_array, n*sizeof(int));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(gpu_array, array, n*sizeof(int), cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
blocks= (n + threads -1)/threads;
reduce<<<blocks,threads>>>(gpu_array,n);
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
cudaMemcpy(array, gpu_array, n*sizeof(int), cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
for(i=0;i<n;i+=threads){
result = result ^ array[i];
printf("result= %d\n",result);
}
gettimeofday(&t_end, NULL);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(gpu_array);
}
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void reduce(int* input, int n){
unsigned int tid=threadIdx.x;
unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
unsigned int offset = blockDim.x * blockIdx.x;
__syncthreads();
for(unsigned int s=1; s<blockDim.x; s*=2){
if(tid % (2*s)==0){
input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
}
__syncthreads();
}
}
int main(int argc, char** argv){
struct timeval start, end, t_start, t_end;
int i,n = atoi(argv[1]);
int seed= atoi(argv[2]);
int * array;
int blocks;
int result=0;
int threads=10;
array=(int*)malloc(n * sizeof(int));
srand(seed);
for(i=0;i<n;i++){
array[i]=random();
printf("a[%d]= %d\n",i,array[i]);
}
int *gpu_array;
gettimeofday(&t_start, NULL);
hipMalloc(&gpu_array, n*sizeof(int));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(gpu_array, array, n*sizeof(int), hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
blocks= (n + threads -1)/threads;
reduce<<<blocks,threads>>>(gpu_array,n);
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
hipMemcpy(array, gpu_array, n*sizeof(int), hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
for(i=0;i<n;i+=threads){
result = result ^ array[i];
printf("result= %d\n",result);
}
gettimeofday(&t_end, NULL);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(gpu_array);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void reduce(int* input, int n){
unsigned int tid=threadIdx.x;
unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
unsigned int offset = blockDim.x * blockIdx.x;
__syncthreads();
for(unsigned int s=1; s<blockDim.x; s*=2){
if(tid % (2*s)==0){
input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
}
__syncthreads();
}
}
int main(int argc, char** argv){
struct timeval start, end, t_start, t_end;
int i,n = atoi(argv[1]);
int seed= atoi(argv[2]);
int * array;
int blocks;
int result=0;
int threads=10;
array=(int*)malloc(n * sizeof(int));
srand(seed);
for(i=0;i<n;i++){
array[i]=random();
printf("a[%d]= %d\n",i,array[i]);
}
int *gpu_array;
gettimeofday(&t_start, NULL);
hipMalloc(&gpu_array, n*sizeof(int));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(gpu_array, array, n*sizeof(int), hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
blocks= (n + threads -1)/threads;
reduce<<<blocks,threads>>>(gpu_array,n);
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
hipMemcpy(array, gpu_array, n*sizeof(int), hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
for(i=0;i<n;i+=threads){
result = result ^ array[i];
printf("result= %d\n",result);
}
gettimeofday(&t_end, NULL);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(gpu_array);
}
|
.text
.file "q2.hip"
.globl _Z21__device_stub__reducePii # -- Begin function _Z21__device_stub__reducePii
.p2align 4, 0x90
.type _Z21__device_stub__reducePii,@function
_Z21__device_stub__reducePii: # @_Z21__device_stub__reducePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6reducePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePii, .Lfunc_end0-_Z21__device_stub__reducePii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %ebx, %r13
leaq (,%r13,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movl %r12d, %edi
callq srand
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
movl %eax, (%r14,%r12,4)
movl $.L.str, %edi
movl %r12d, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.6:
movq (%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
# %bb.8:
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leal 9(%rbx), %eax
cltq
imulq $1717986919, %rax, %rdi # imm = 0x66666667
movq %rdi, %rax
shrq $63, %rax
sarq $34, %rdi
addl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $10, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rax
movq %rax, 80(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6reducePii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.13: # %.preheader
testl %ebx, %ebx
jle .LBB1_16
# %bb.14: # %.lr.ph58.preheader
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_15: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
xorl (%r14,%r15,4), %ebp
movl $.L.str.6, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
addq $10, %r15
cmpl %ebx, %r15d
jl .LBB1_15
.LBB1_16: # %._crit_edge59
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rsi
subq 88(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 96(%rsp), %rsi
addq %rax, %rsi
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
subq 104(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 112(%rsp), %rdx
addq %rax, %rdx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
jmp .LBB1_5
.LBB1_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.3, %edx
jmp .LBB1_5
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.4, %edx
jmp .LBB1_5
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.5, %edx
.LBB1_5:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePii,@object # @_Z6reducePii
.section .rodata,"a",@progbits
.globl _Z6reducePii
.p2align 3, 0x0
_Z6reducePii:
.quad _Z21__device_stub__reducePii
.size _Z6reducePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d]= %d\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda Error: '%s' for %s\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMemcpy"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "kernel invocation"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "memcpy"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "result= %d\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total time = %ld microsecs Processsing =%ld microsecs\n"
.size .L.str.7, 55
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6reducePii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0019a067_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6reducePiiPii
.type _Z26__device_stub__Z6reducePiiPii, @function
_Z26__device_stub__Z6reducePiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6reducePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z6reducePiiPii, .-_Z26__device_stub__Z6reducePiiPii
.globl _Z6reducePii
.type _Z6reducePii, @function
_Z6reducePii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6reducePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6reducePii, .-_Z6reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "a[%d]= %d\n"
.LC1:
.string "cudaMalloc"
.LC2:
.string "Cuda Error: '%s' for %s\n"
.LC3:
.string "cudaMemcpy"
.LC4:
.string "kernel invocation"
.LC5:
.string "memcpy"
.LC6:
.string "result= %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Total time = %ld microsecs Processsing =%ld microsecs\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movslq %r15d, %rax
salq $2, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
movl %ebx, %edi
call srand@PLT
testl %r15d, %r15d
jle .L12
leal -1(%r15), %r14d
movl $0, %ebx
leaq .LC0(%rip), %r13
.L13:
call random@PLT
movl %eax, %ecx
movl %eax, 0(%rbp,%rbx,4)
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $1, %rbx
cmpq %r14, %rax
jne .L13
.L12:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 24(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L28
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $10, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
leal 9(%r15), %edx
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L16:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L18
movl $0, %ebx
movl $0, %r13d
leaq .LC6(%rip), %r14
testl %r15d, %r15d
jle .L20
.L19:
xorl 0(%rbp,%rbx,4), %r13d
movl %r13d, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $10, %rbx
cmpl %ebx, %r12d
jg .L19
.L20:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rcx
subq 32(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 56(%rsp), %rcx
subq 40(%rsp), %rcx
movq 80(%rsp), %rdx
subq 64(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 88(%rsp), %rdx
subq 72(%rsp), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %r12d, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6reducePiiPii
jmp .L16
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6reducePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "q2.hip"
.globl _Z21__device_stub__reducePii # -- Begin function _Z21__device_stub__reducePii
.p2align 4, 0x90
.type _Z21__device_stub__reducePii,@function
_Z21__device_stub__reducePii: # @_Z21__device_stub__reducePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6reducePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__reducePii, .Lfunc_end0-_Z21__device_stub__reducePii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movslq %ebx, %r13
leaq (,%r13,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movl %r12d, %edi
callq srand
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq random
movl %eax, (%r14,%r12,4)
movl $.L.str, %edi
movl %r12d, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %rsp, %rdi
movq %r15, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_4
# %bb.6:
movq (%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_7
# %bb.8:
leaq 104(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leal 9(%rbx), %eax
cltq
imulq $1717986919, %rax, %rdi # imm = 0x66666667
movq %rdi, %rax
shrq $63, %rax
sarq $34, %rdi
addl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $10, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq (%rsp), %rax
movq %rax, 80(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6reducePii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_17
# %bb.13: # %.preheader
testl %ebx, %ebx
jle .LBB1_16
# %bb.14: # %.lr.ph58.preheader
xorl %r15d, %r15d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_15: # %.lr.ph58
# =>This Inner Loop Header: Depth=1
xorl (%r14,%r15,4), %ebp
movl $.L.str.6, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
addq $10, %r15
cmpl %ebx, %r15d
jl .LBB1_15
.LBB1_16: # %._crit_edge59
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rsi
subq 88(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 96(%rsp), %rsi
addq %rax, %rsi
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
subq 104(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 112(%rsp), %rdx
addq %rax, %rdx
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.2, %edx
jmp .LBB1_5
.LBB1_7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.3, %edx
jmp .LBB1_5
.LBB1_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.4, %edx
jmp .LBB1_5
.LBB1_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movl $.L.str.5, %edx
.LBB1_5:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6reducePii,@object # @_Z6reducePii
.section .rodata,"a",@progbits
.globl _Z6reducePii
.p2align 3, 0x0
_Z6reducePii:
.quad _Z21__device_stub__reducePii
.size _Z6reducePii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%d]= %d\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda Error: '%s' for %s\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMalloc"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMemcpy"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "kernel invocation"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "memcpy"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "result= %d\n"
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Total time = %ld microsecs Processsing =%ld microsecs\n"
.size .L.str.7, 55
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6reducePii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__reducePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6reducePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void __dds0(int nrows, int ncols, float *A, float *B, int *Cir, int *Cjc, float *P) {}
|
code for sm_80
Function : _Z6__dds0iiPfS_PiS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void __dds0(int nrows, int ncols, float *A, float *B, int *Cir, int *Cjc, float *P) {}
|
.file "tmpxft_000b9ff0_00000000-6___dds0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_
.type _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_, @function
_Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6__dds0iiPfS_PiS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_, .-_Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_
.globl _Z6__dds0iiPfS_PiS0_S_
.type _Z6__dds0iiPfS_PiS0_S_, @function
_Z6__dds0iiPfS_PiS0_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6__dds0iiPfS_PiS0_S_, .-_Z6__dds0iiPfS_PiS0_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6__dds0iiPfS_PiS0_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6__dds0iiPfS_PiS0_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void __dds0(int nrows, int ncols, float *A, float *B, int *Cir, int *Cjc, float *P) {}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __dds0(int nrows, int ncols, float *A, float *B, int *Cir, int *Cjc, float *P) {}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __dds0(int nrows, int ncols, float *A, float *B, int *Cir, int *Cjc, float *P) {}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6__dds0iiPfS_PiS0_S_
.globl _Z6__dds0iiPfS_PiS0_S_
.p2align 8
.type _Z6__dds0iiPfS_PiS0_S_,@function
_Z6__dds0iiPfS_PiS0_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6__dds0iiPfS_PiS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6__dds0iiPfS_PiS0_S_, .Lfunc_end0-_Z6__dds0iiPfS_PiS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6__dds0iiPfS_PiS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6__dds0iiPfS_PiS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __dds0(int nrows, int ncols, float *A, float *B, int *Cir, int *Cjc, float *P) {}
|
.text
.file "__dds0.hip"
.globl _Z21__device_stub____dds0iiPfS_PiS0_S_ # -- Begin function _Z21__device_stub____dds0iiPfS_PiS0_S_
.p2align 4, 0x90
.type _Z21__device_stub____dds0iiPfS_PiS0_S_,@function
_Z21__device_stub____dds0iiPfS_PiS0_S_: # @_Z21__device_stub____dds0iiPfS_PiS0_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6__dds0iiPfS_PiS0_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub____dds0iiPfS_PiS0_S_, .Lfunc_end0-_Z21__device_stub____dds0iiPfS_PiS0_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6__dds0iiPfS_PiS0_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6__dds0iiPfS_PiS0_S_,@object # @_Z6__dds0iiPfS_PiS0_S_
.section .rodata,"a",@progbits
.globl _Z6__dds0iiPfS_PiS0_S_
.p2align 3, 0x0
_Z6__dds0iiPfS_PiS0_S_:
.quad _Z21__device_stub____dds0iiPfS_PiS0_S_
.size _Z6__dds0iiPfS_PiS0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6__dds0iiPfS_PiS0_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub____dds0iiPfS_PiS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6__dds0iiPfS_PiS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6__dds0iiPfS_PiS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6__dds0iiPfS_PiS0_S_
.globl _Z6__dds0iiPfS_PiS0_S_
.p2align 8
.type _Z6__dds0iiPfS_PiS0_S_,@function
_Z6__dds0iiPfS_PiS0_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6__dds0iiPfS_PiS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6__dds0iiPfS_PiS0_S_, .Lfunc_end0-_Z6__dds0iiPfS_PiS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6__dds0iiPfS_PiS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6__dds0iiPfS_PiS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000b9ff0_00000000-6___dds0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_
.type _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_, @function
_Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6__dds0iiPfS_PiS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_, .-_Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_
.globl _Z6__dds0iiPfS_PiS0_S_
.type _Z6__dds0iiPfS_PiS0_S_, @function
_Z6__dds0iiPfS_PiS0_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z6__dds0iiPfS_PiS0_S_iiPfS_PiS0_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6__dds0iiPfS_PiS0_S_, .-_Z6__dds0iiPfS_PiS0_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6__dds0iiPfS_PiS0_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6__dds0iiPfS_PiS0_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "__dds0.hip"
.globl _Z21__device_stub____dds0iiPfS_PiS0_S_ # -- Begin function _Z21__device_stub____dds0iiPfS_PiS0_S_
.p2align 4, 0x90
.type _Z21__device_stub____dds0iiPfS_PiS0_S_,@function
_Z21__device_stub____dds0iiPfS_PiS0_S_: # @_Z21__device_stub____dds0iiPfS_PiS0_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6__dds0iiPfS_PiS0_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub____dds0iiPfS_PiS0_S_, .Lfunc_end0-_Z21__device_stub____dds0iiPfS_PiS0_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6__dds0iiPfS_PiS0_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6__dds0iiPfS_PiS0_S_,@object # @_Z6__dds0iiPfS_PiS0_S_
.section .rodata,"a",@progbits
.globl _Z6__dds0iiPfS_PiS0_S_
.p2align 3, 0x0
_Z6__dds0iiPfS_PiS0_S_:
.quad _Z21__device_stub____dds0iiPfS_PiS0_S_
.size _Z6__dds0iiPfS_PiS0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6__dds0iiPfS_PiS0_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub____dds0iiPfS_PiS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6__dds0iiPfS_PiS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void MaskInput( float* image, float* mask, float* maskedValues, float* output, int count ) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < count) {
output[id] = image[id] * mask[id] + maskedValues[id] * (1.0f - mask[id]);
}
}
|
code for sm_80
Function : _Z9MaskInputPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*00b0*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0209 */
/*00e0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000f22000c1e1900 */
/*0100*/ FADD R8, -R4, 1 ; /* 0x3f80000004087421 */
/* 0x004fc80000000100 */
/*0110*/ FMUL R10, R8, R7 ; /* 0x00000007080a7220 */
/* 0x008fe40000400000 */
/*0120*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0209 */
/*0130*/ FFMA R11, R4, R3, R10 ; /* 0x00000003040b7223 */
/* 0x010fca000000000a */
/*0140*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void MaskInput( float* image, float* mask, float* maskedValues, float* output, int count ) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < count) {
output[id] = image[id] * mask[id] + maskedValues[id] * (1.0f - mask[id]);
}
}
|
.file "tmpxft_000bb081_00000000-6_MaskInput.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i
.type _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i, @function
_Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9MaskInputPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i, .-_Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i
.globl _Z9MaskInputPfS_S_S_i
.type _Z9MaskInputPfS_S_S_i, @function
_Z9MaskInputPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9MaskInputPfS_S_S_i, .-_Z9MaskInputPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9MaskInputPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MaskInputPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void MaskInput( float* image, float* mask, float* maskedValues, float* output, int count ) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < count) {
output[id] = image[id] * mask[id] + maskedValues[id] * (1.0f - mask[id]);
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MaskInput( float* image, float* mask, float* maskedValues, float* output, int count ) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < count) {
output[id] = image[id] * mask[id] + maskedValues[id] * (1.0f - mask[id]);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MaskInput( float* image, float* mask, float* maskedValues, float* output, int count ) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < count) {
output[id] = image[id] * mask[id] + maskedValues[id] * (1.0f - mask[id]);
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9MaskInputPfS_S_S_i
.globl _Z9MaskInputPfS_S_S_i
.p2align 8
.type _Z9MaskInputPfS_S_S_i,@function
_Z9MaskInputPfS_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(2)
v_sub_f32_e32 v3, 1.0, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v6
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MaskInputPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9MaskInputPfS_S_S_i, .Lfunc_end0-_Z9MaskInputPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MaskInputPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MaskInputPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MaskInput( float* image, float* mask, float* maskedValues, float* output, int count ) {
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if (id < count) {
output[id] = image[id] * mask[id] + maskedValues[id] * (1.0f - mask[id]);
}
}
|
.text
.file "MaskInput.hip"
.globl _Z24__device_stub__MaskInputPfS_S_S_i # -- Begin function _Z24__device_stub__MaskInputPfS_S_S_i
.p2align 4, 0x90
.type _Z24__device_stub__MaskInputPfS_S_S_i,@function
_Z24__device_stub__MaskInputPfS_S_S_i: # @_Z24__device_stub__MaskInputPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9MaskInputPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__MaskInputPfS_S_S_i, .Lfunc_end0-_Z24__device_stub__MaskInputPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MaskInputPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9MaskInputPfS_S_S_i,@object # @_Z9MaskInputPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z9MaskInputPfS_S_S_i
.p2align 3, 0x0
_Z9MaskInputPfS_S_S_i:
.quad _Z24__device_stub__MaskInputPfS_S_S_i
.size _Z9MaskInputPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9MaskInputPfS_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__MaskInputPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9MaskInputPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9MaskInputPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*00b0*/ IMAD.WIDE R6, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x0c0fe400078e0209 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe400078e0209 */
/*00e0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000f22000c1e1900 */
/*0100*/ FADD R8, -R4, 1 ; /* 0x3f80000004087421 */
/* 0x004fc80000000100 */
/*0110*/ FMUL R10, R8, R7 ; /* 0x00000007080a7220 */
/* 0x008fe40000400000 */
/*0120*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc800078e0209 */
/*0130*/ FFMA R11, R4, R3, R10 ; /* 0x00000003040b7223 */
/* 0x010fca000000000a */
/*0140*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9MaskInputPfS_S_S_i
.globl _Z9MaskInputPfS_S_S_i
.p2align 8
.type _Z9MaskInputPfS_S_S_i,@function
_Z9MaskInputPfS_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(2)
v_sub_f32_e32 v3, 1.0, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v3
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v6
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MaskInputPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9MaskInputPfS_S_S_i, .Lfunc_end0-_Z9MaskInputPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MaskInputPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MaskInputPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000bb081_00000000-6_MaskInput.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i
.type _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i, @function
_Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9MaskInputPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i, .-_Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i
.globl _Z9MaskInputPfS_S_S_i
.type _Z9MaskInputPfS_S_S_i, @function
_Z9MaskInputPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9MaskInputPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9MaskInputPfS_S_S_i, .-_Z9MaskInputPfS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9MaskInputPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MaskInputPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "MaskInput.hip"
.globl _Z24__device_stub__MaskInputPfS_S_S_i # -- Begin function _Z24__device_stub__MaskInputPfS_S_S_i
.p2align 4, 0x90
.type _Z24__device_stub__MaskInputPfS_S_S_i,@function
_Z24__device_stub__MaskInputPfS_S_S_i: # @_Z24__device_stub__MaskInputPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9MaskInputPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__MaskInputPfS_S_S_i, .Lfunc_end0-_Z24__device_stub__MaskInputPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MaskInputPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9MaskInputPfS_S_S_i,@object # @_Z9MaskInputPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z9MaskInputPfS_S_S_i
.p2align 3, 0x0
_Z9MaskInputPfS_S_S_i:
.quad _Z24__device_stub__MaskInputPfS_S_S_i
.size _Z9MaskInputPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9MaskInputPfS_S_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__MaskInputPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9MaskInputPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdlib.h>
#include <stdio.h>
#define N 10
__global__ void VecAdd(float* A, float* B, float* C) {
int i = threadIdx.x;
printf("tid: x=%d\n", i);
C[i] = A[i] + B[i];
}
int main() {
float A[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float B[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float *C = (float*)malloc(sizeof(float) * N);
float *dA, *dB, *dC;
cudaMalloc((void**)&dA, N * sizeof(float));
cudaMalloc((void**)&dB, N * sizeof(float));
cudaMalloc((void**)&dC, N * sizeof(float));
cudaMemcpy(dA, A, N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, N * sizeof(float), cudaMemcpyHostToDevice);
// Kernel invocation with N threads
VecAdd<<<1, N>>>(dA, dB, dC);
cudaMemcpy(C, dC, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
for(int i=0; i<N; i++) {
printf("%d: %f\n", i, *(C+i));
}
free(C);
getchar();
return 0;
}
|
code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0013e80000100800 */
/*00b0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fc60000000000 */
/*00c0*/ MOV R3, 0x130 ; /* 0x0000013000037802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0110*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0120*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*0150*/ IMAD.WIDE R6, R2.reuse, R3.reuse, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x0c0fe400078e0203 */
/*0160*/ LDG.E R4, [R4.64] ; /* 0x0000002404047981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000002406077981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0203 */
/*0190*/ FADD R9, R4, R7 ; /* 0x0000000704097221 */
/* 0x004fca0000000000 */
/*01a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101924 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdlib.h>
#include <stdio.h>
#define N 10
__global__ void VecAdd(float* A, float* B, float* C) {
int i = threadIdx.x;
printf("tid: x=%d\n", i);
C[i] = A[i] + B[i];
}
int main() {
float A[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float B[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float *C = (float*)malloc(sizeof(float) * N);
float *dA, *dB, *dC;
cudaMalloc((void**)&dA, N * sizeof(float));
cudaMalloc((void**)&dB, N * sizeof(float));
cudaMalloc((void**)&dC, N * sizeof(float));
cudaMemcpy(dA, A, N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, N * sizeof(float), cudaMemcpyHostToDevice);
// Kernel invocation with N threads
VecAdd<<<1, N>>>(dA, dB, dC);
cudaMemcpy(C, dC, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
for(int i=0; i<N; i++) {
printf("%d: %f\n", i, *(C+i));
}
free(C);
getchar();
return 0;
}
|
.file "tmpxft_000776c8_00000000-6_101.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "%d: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0x00000000, 48(%rsp)
movss .LC1(%rip), %xmm8
movss %xmm8, 52(%rsp)
movss .LC2(%rip), %xmm7
movss %xmm7, 56(%rsp)
movss .LC3(%rip), %xmm6
movss %xmm6, 60(%rsp)
movss .LC4(%rip), %xmm5
movss %xmm5, 64(%rsp)
movss .LC5(%rip), %xmm4
movss %xmm4, 68(%rsp)
movss .LC6(%rip), %xmm3
movss %xmm3, 72(%rsp)
movss .LC7(%rip), %xmm2
movss %xmm2, 76(%rsp)
movss .LC8(%rip), %xmm1
movss %xmm1, 80(%rsp)
movss .LC9(%rip), %xmm0
movss %xmm0, 84(%rsp)
movl $0x00000000, 96(%rsp)
movss %xmm8, 100(%rsp)
movss %xmm7, 104(%rsp)
movss %xmm6, 108(%rsp)
movss %xmm5, 112(%rsp)
movss %xmm4, 116(%rsp)
movss %xmm3, 120(%rsp)
movss %xmm2, 124(%rsp)
movss %xmm1, 128(%rsp)
movss %xmm0, 132(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC10(%rip), %r12
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L13
movq %rbp, %rdi
call free@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1082130432
.align 4
.LC5:
.long 1084227584
.align 4
.LC6:
.long 1086324736
.align 4
.LC7:
.long 1088421888
.align 4
.LC8:
.long 1090519040
.align 4
.LC9:
.long 1091567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdlib.h>
#include <stdio.h>
#define N 10
__global__ void VecAdd(float* A, float* B, float* C) {
int i = threadIdx.x;
printf("tid: x=%d\n", i);
C[i] = A[i] + B[i];
}
int main() {
float A[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float B[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float *C = (float*)malloc(sizeof(float) * N);
float *dA, *dB, *dC;
cudaMalloc((void**)&dA, N * sizeof(float));
cudaMalloc((void**)&dB, N * sizeof(float));
cudaMalloc((void**)&dC, N * sizeof(float));
cudaMemcpy(dA, A, N * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(dB, B, N * sizeof(float), cudaMemcpyHostToDevice);
// Kernel invocation with N threads
VecAdd<<<1, N>>>(dA, dB, dC);
cudaMemcpy(C, dC, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
for(int i=0; i<N; i++) {
printf("%d: %f\n", i, *(C+i));
}
free(C);
getchar();
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define N 10
__global__ void VecAdd(float* A, float* B, float* C) {
int i = threadIdx.x;
printf("tid: x=%d\n", i);
C[i] = A[i] + B[i];
}
int main() {
float A[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float B[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float *C = (float*)malloc(sizeof(float) * N);
float *dA, *dB, *dC;
hipMalloc((void**)&dA, N * sizeof(float));
hipMalloc((void**)&dB, N * sizeof(float));
hipMalloc((void**)&dC, N * sizeof(float));
hipMemcpy(dA, A, N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dB, B, N * sizeof(float), hipMemcpyHostToDevice);
// Kernel invocation with N threads
VecAdd<<<1, N>>>(dA, dB, dC);
hipMemcpy(C, dC, N * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dB);
hipFree(dC);
for(int i=0; i<N; i++) {
printf("%d: %f\n", i, *(C+i));
}
free(C);
getchar();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define N 10
__global__ void VecAdd(float* A, float* B, float* C) {
int i = threadIdx.x;
printf("tid: x=%d\n", i);
C[i] = A[i] + B[i];
}
int main() {
float A[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float B[N] = {0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0};
float *C = (float*)malloc(sizeof(float) * N);
float *dA, *dB, *dC;
hipMalloc((void**)&dA, N * sizeof(float));
hipMalloc((void**)&dB, N * sizeof(float));
hipMalloc((void**)&dC, N * sizeof(float));
hipMemcpy(dA, A, N * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(dB, B, N * sizeof(float), hipMemcpyHostToDevice);
// Kernel invocation with N threads
VecAdd<<<1, N>>>(dA, dB, dC);
hipMemcpy(C, dC, N * sizeof(float), hipMemcpyDeviceToHost);
hipFree(dA);
hipFree(dB);
hipFree(dC);
for(int i=0; i<N; i++) {
printf("%d: %f\n", i, *(C+i));
}
free(C);
getchar();
return 0;
}
|
.text
.file "101.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.LCPI1_1:
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.long 0x40e00000 # float 7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $216, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [0.0E+0,1.0E+0,2.0E+0,3.0E+0]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0]
movaps %xmm1, 192(%rsp)
movabsq $4688247213183205376, %rax # imm = 0x4110000041000000
movq %rax, 208(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm1, 144(%rsp)
movq %rax, 160(%rsp)
movl $40, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_3
# %bb.4:
movq %rbx, %rdi
callq free
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: %f\n"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000776c8_00000000-6_101.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "%d: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0x00000000, 48(%rsp)
movss .LC1(%rip), %xmm8
movss %xmm8, 52(%rsp)
movss .LC2(%rip), %xmm7
movss %xmm7, 56(%rsp)
movss .LC3(%rip), %xmm6
movss %xmm6, 60(%rsp)
movss .LC4(%rip), %xmm5
movss %xmm5, 64(%rsp)
movss .LC5(%rip), %xmm4
movss %xmm4, 68(%rsp)
movss .LC6(%rip), %xmm3
movss %xmm3, 72(%rsp)
movss .LC7(%rip), %xmm2
movss %xmm2, 76(%rsp)
movss .LC8(%rip), %xmm1
movss %xmm1, 80(%rsp)
movss .LC9(%rip), %xmm0
movss %xmm0, 84(%rsp)
movl $0x00000000, 96(%rsp)
movss %xmm8, 100(%rsp)
movss %xmm7, 104(%rsp)
movss %xmm6, 108(%rsp)
movss %xmm5, 112(%rsp)
movss %xmm4, 116(%rsp)
movss %xmm3, 120(%rsp)
movss %xmm2, 124(%rsp)
movss %xmm1, 128(%rsp)
movss %xmm0, 132(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC10(%rip), %r12
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L13
movq %rbp, %rdi
call free@PLT
movq stdin(%rip), %rdi
call getc@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1082130432
.align 4
.LC5:
.long 1084227584
.align 4
.LC6:
.long 1086324736
.align 4
.LC7:
.long 1088421888
.align 4
.LC8:
.long 1090519040
.align 4
.LC9:
.long 1091567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "101.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.LCPI1_1:
.long 0x40800000 # float 4
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.long 0x40e00000 # float 7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $216, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [0.0E+0,1.0E+0,2.0E+0,3.0E+0]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0]
movaps %xmm1, 192(%rsp)
movabsq $4688247213183205376, %rax # imm = 0x4110000041000000
movq %rax, 208(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm1, 144(%rsp)
movq %rax, 160(%rsp)
movl $40, %edi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_3
# %bb.4:
movq %rbx, %rdi
callq free
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d: %f\n"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <sstream>
#include <cmath>
#include <algorithm>
#include <vector>
#include <chrono>
#include <type_traits>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/device_ptr.h>
class GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
public:
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
template <class Resolution = std::chrono::microseconds>
class CPUTimer {
public:
using Clock = std::conditional_t<std::chrono::high_resolution_clock::is_steady,
std::chrono::high_resolution_clock,
std::chrono::steady_clock>;
private:
const Clock::time_point mStart = Clock::now();
public:
CPUTimer() = default;
~CPUTimer() {
const auto end = Clock::now();
std::ostringstream strStream;
// strStream << "Destructor Elapsed: "
// << std::chrono::duration_cast<Resolution>(end - mStart).count()
// << std::endl;
// std::cout << strStream.str() << std::endl;
}
void stop(std::string const& label) {
const auto end = Clock::now();
std::ostringstream strStream;
strStream << "Stop Elapsed " << label << " : "
<< std::chrono::duration_cast<Resolution>(end - mStart).count()
<< std::endl;
std::cout << strStream.str() << std::endl;
}
};
constexpr unsigned NUM_BINS = 256;
void histogramCPU(unsigned int* input, unsigned int* res, unsigned int n)
{
for (unsigned i=0; i<n; ++i) {
res[input[i]]++;
}
}
__global__ void histogramGPUGlobalMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&res[input[i]], 1);
}
}
__global__ void histogramGPUSharedMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Allocate a local histogram for each TB
__shared__ int s_res[NUM_BINS];
// Initalize the shared memory to 0
if (threadIdx.x < NUM_BINS) {
s_res[threadIdx.x] = 0;
}
// Wait for shared memory writes to complete
__syncthreads();
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&s_res[input[i]], 1);
}
// Wait for shared memory writes to complete
__syncthreads();
// Combine the partial results
if (threadIdx.x < NUM_BINS) {
atomicAdd(&res[threadIdx.x], s_res[threadIdx.x]);
}
}
int main()
{
unsigned N = 1 << 16;
std::vector<unsigned> h_input(N);
std::vector<unsigned> h_result(NUM_BINS);
thrust::host_vector<unsigned> h_result_copy(NUM_BINS);
std::srand(42);
std::generate(std::begin(h_input), std::end(h_input), [] { return (unsigned)rand() % NUM_BINS; } );
CPUTimer<> cpu_timer;
histogramCPU(h_input.data(), h_result.data(), h_result.size());
cpu_timer.stop("histogramCPU");
thrust::device_vector<unsigned> d_input(h_input);
thrust::device_vector<unsigned> d_result(h_result_copy);
thrust::device_vector<unsigned> d_result2(h_result_copy);
// Number of threads per threadblock
size_t THREADS = 512;
// Calculate the number of threadblocks
size_t BLOCKS = N / THREADS;
GpuTimer timer;
timer.Start();
CPUTimer<> cpu_timer1;
histogramGPUGlobalMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result.data()),
d_result.size());
timer.Stop();
cpu_timer1.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUGlobalMem: " << timer.Elapsed() << " millisecs\n";
timer.Start();
CPUTimer<> cpu_timer2;
histogramGPUSharedMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result2.data()),
d_result2.size());
timer.Stop();
cpu_timer2.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUSharedMem: " << timer.Elapsed() << " millisecs\n";
auto compare_vals = [](std::string const& label,
auto const& arr1,
auto const& arr2) {
std::cout << "checking values: " << label << std::endl;
size_t mismatches = 0;
for (size_t i = 0; i < arr1.size(); ++i) {
if (arr1[i] != arr2[i]) {
++mismatches;
std::cout << "mismatch for index: " << i << " got:" << arr1[i] << " expected: " << arr2[i] << std::endl;
}
}
std::cout << mismatches << " mismatches for " << label << std::endl;
};
// copy back
h_result_copy = d_result;
compare_vals("h_result vs. d_result", h_result, h_result_copy);
// copy back
h_result_copy = d_result2;
compare_vals("h_result vs. d_result2", h_result, h_result_copy);
}
|
code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21histogramGPUSharedMemPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P1, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x001fe20003f24070 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0204 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fca0000011400 */
/*0080*/ @!P1 STS [R4.X4], RZ ; /* 0x000000ff04009388 */
/* 0x0001e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*00b0*/ @P0 BRA 0x190 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0002 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff067624 */
/* 0x000fe400078e00ff */
/*00e0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x001fc800078010ff */
/*00f0*/ LEA.HI.X R3, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1405 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD R7, R6, c[0x0][0x0], RZ ; /* 0x0000000006077a24 */
/* 0x000fe200078e02ff */
/*0120*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0130*/ IADD3 R0, P0, R7, R0, RZ ; /* 0x0000000007007210 */
/* 0x000fca0007f1e0ff */
/*0140*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe200000e0605 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0160*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f06100 */
/*0170*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0180*/ @!P0 BRA 0xe0 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01c0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e220000004800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*01f0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21histogramGPUGlobalMemPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff067624 */
/* 0x000fe400078e00ff */
/*00b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*00c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1407 */
/*00d0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x001ea2000c1e1900 */
/*00e0*/ IMAD R11, R6, c[0x0][0x0], RZ ; /* 0x00000000060b7a24 */
/* 0x000fe200078e02ff */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0110*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe40003800000 */
/*0120*/ IADD3 R0, P0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400007fe4ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fe20003f06100 */
/*0160*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x004fca00078e0003 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001ee000c10e184 */
/*0180*/ @!P0 BRA 0xb0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <sstream>
#include <cmath>
#include <algorithm>
#include <vector>
#include <chrono>
#include <type_traits>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/device_ptr.h>
class GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
public:
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
template <class Resolution = std::chrono::microseconds>
class CPUTimer {
public:
using Clock = std::conditional_t<std::chrono::high_resolution_clock::is_steady,
std::chrono::high_resolution_clock,
std::chrono::steady_clock>;
private:
const Clock::time_point mStart = Clock::now();
public:
CPUTimer() = default;
~CPUTimer() {
const auto end = Clock::now();
std::ostringstream strStream;
// strStream << "Destructor Elapsed: "
// << std::chrono::duration_cast<Resolution>(end - mStart).count()
// << std::endl;
// std::cout << strStream.str() << std::endl;
}
void stop(std::string const& label) {
const auto end = Clock::now();
std::ostringstream strStream;
strStream << "Stop Elapsed " << label << " : "
<< std::chrono::duration_cast<Resolution>(end - mStart).count()
<< std::endl;
std::cout << strStream.str() << std::endl;
}
};
constexpr unsigned NUM_BINS = 256;
void histogramCPU(unsigned int* input, unsigned int* res, unsigned int n)
{
for (unsigned i=0; i<n; ++i) {
res[input[i]]++;
}
}
__global__ void histogramGPUGlobalMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&res[input[i]], 1);
}
}
__global__ void histogramGPUSharedMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Allocate a local histogram for each TB
__shared__ int s_res[NUM_BINS];
// Initalize the shared memory to 0
if (threadIdx.x < NUM_BINS) {
s_res[threadIdx.x] = 0;
}
// Wait for shared memory writes to complete
__syncthreads();
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&s_res[input[i]], 1);
}
// Wait for shared memory writes to complete
__syncthreads();
// Combine the partial results
if (threadIdx.x < NUM_BINS) {
atomicAdd(&res[threadIdx.x], s_res[threadIdx.x]);
}
}
int main()
{
unsigned N = 1 << 16;
std::vector<unsigned> h_input(N);
std::vector<unsigned> h_result(NUM_BINS);
thrust::host_vector<unsigned> h_result_copy(NUM_BINS);
std::srand(42);
std::generate(std::begin(h_input), std::end(h_input), [] { return (unsigned)rand() % NUM_BINS; } );
CPUTimer<> cpu_timer;
histogramCPU(h_input.data(), h_result.data(), h_result.size());
cpu_timer.stop("histogramCPU");
thrust::device_vector<unsigned> d_input(h_input);
thrust::device_vector<unsigned> d_result(h_result_copy);
thrust::device_vector<unsigned> d_result2(h_result_copy);
// Number of threads per threadblock
size_t THREADS = 512;
// Calculate the number of threadblocks
size_t BLOCKS = N / THREADS;
GpuTimer timer;
timer.Start();
CPUTimer<> cpu_timer1;
histogramGPUGlobalMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result.data()),
d_result.size());
timer.Stop();
cpu_timer1.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUGlobalMem: " << timer.Elapsed() << " millisecs\n";
timer.Start();
CPUTimer<> cpu_timer2;
histogramGPUSharedMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result2.data()),
d_result2.size());
timer.Stop();
cpu_timer2.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUSharedMem: " << timer.Elapsed() << " millisecs\n";
auto compare_vals = [](std::string const& label,
auto const& arr1,
auto const& arr2) {
std::cout << "checking values: " << label << std::endl;
size_t mismatches = 0;
for (size_t i = 0; i < arr1.size(); ++i) {
if (arr1[i] != arr2[i]) {
++mismatches;
std::cout << "mismatch for index: " << i << " got:" << arr1[i] << " expected: " << arr2[i] << std::endl;
}
}
std::cout << mismatches << " mismatches for " << label << std::endl;
};
// copy back
h_result_copy = d_result;
compare_vals("h_result vs. d_result", h_result, h_result_copy);
// copy back
h_result_copy = d_result2;
compare_vals("h_result vs. d_result2", h_result, h_result_copy);
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <sstream>
#include <cmath>
#include <algorithm>
#include <vector>
#include <chrono>
#include <type_traits>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/device_ptr.h>
class GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
public:
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
template <class Resolution = std::chrono::microseconds>
class CPUTimer {
public:
using Clock = std::conditional_t<std::chrono::high_resolution_clock::is_steady,
std::chrono::high_resolution_clock,
std::chrono::steady_clock>;
private:
const Clock::time_point mStart = Clock::now();
public:
CPUTimer() = default;
~CPUTimer() {
const auto end = Clock::now();
std::ostringstream strStream;
// strStream << "Destructor Elapsed: "
// << std::chrono::duration_cast<Resolution>(end - mStart).count()
// << std::endl;
// std::cout << strStream.str() << std::endl;
}
void stop(std::string const& label) {
const auto end = Clock::now();
std::ostringstream strStream;
strStream << "Stop Elapsed " << label << " : "
<< std::chrono::duration_cast<Resolution>(end - mStart).count()
<< std::endl;
std::cout << strStream.str() << std::endl;
}
};
constexpr unsigned NUM_BINS = 256;
void histogramCPU(unsigned int* input, unsigned int* res, unsigned int n)
{
for (unsigned i=0; i<n; ++i) {
res[input[i]]++;
}
}
__global__ void histogramGPUGlobalMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&res[input[i]], 1);
}
}
__global__ void histogramGPUSharedMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Allocate a local histogram for each TB
__shared__ int s_res[NUM_BINS];
// Initalize the shared memory to 0
if (threadIdx.x < NUM_BINS) {
s_res[threadIdx.x] = 0;
}
// Wait for shared memory writes to complete
__syncthreads();
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&s_res[input[i]], 1);
}
// Wait for shared memory writes to complete
__syncthreads();
// Combine the partial results
if (threadIdx.x < NUM_BINS) {
atomicAdd(&res[threadIdx.x], s_res[threadIdx.x]);
}
}
int main()
{
unsigned N = 1 << 16;
std::vector<unsigned> h_input(N);
std::vector<unsigned> h_result(NUM_BINS);
thrust::host_vector<unsigned> h_result_copy(NUM_BINS);
std::srand(42);
std::generate(std::begin(h_input), std::end(h_input), [] { return (unsigned)rand() % NUM_BINS; } );
CPUTimer<> cpu_timer;
histogramCPU(h_input.data(), h_result.data(), h_result.size());
cpu_timer.stop("histogramCPU");
thrust::device_vector<unsigned> d_input(h_input);
thrust::device_vector<unsigned> d_result(h_result_copy);
thrust::device_vector<unsigned> d_result2(h_result_copy);
// Number of threads per threadblock
size_t THREADS = 512;
// Calculate the number of threadblocks
size_t BLOCKS = N / THREADS;
GpuTimer timer;
timer.Start();
CPUTimer<> cpu_timer1;
histogramGPUGlobalMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result.data()),
d_result.size());
timer.Stop();
cpu_timer1.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUGlobalMem: " << timer.Elapsed() << " millisecs\n";
timer.Start();
CPUTimer<> cpu_timer2;
histogramGPUSharedMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result2.data()),
d_result2.size());
timer.Stop();
cpu_timer2.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUSharedMem: " << timer.Elapsed() << " millisecs\n";
auto compare_vals = [](std::string const& label,
auto const& arr1,
auto const& arr2) {
std::cout << "checking values: " << label << std::endl;
size_t mismatches = 0;
for (size_t i = 0; i < arr1.size(); ++i) {
if (arr1[i] != arr2[i]) {
++mismatches;
std::cout << "mismatch for index: " << i << " got:" << arr1[i] << " expected: " << arr2[i] << std::endl;
}
}
std::cout << mismatches << " mismatches for " << label << std::endl;
};
// copy back
h_result_copy = d_result;
compare_vals("h_result vs. d_result", h_result, h_result_copy);
// copy back
h_result_copy = d_result2;
compare_vals("h_result vs. d_result2", h_result, h_result_copy);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <sstream>
#include <cmath>
#include <algorithm>
#include <vector>
#include <chrono>
#include <type_traits>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/device_ptr.h>
class GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
public:
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
template <class Resolution = std::chrono::microseconds>
class CPUTimer {
public:
using Clock = std::conditional_t<std::chrono::high_resolution_clock::is_steady,
std::chrono::high_resolution_clock,
std::chrono::steady_clock>;
private:
const Clock::time_point mStart = Clock::now();
public:
CPUTimer() = default;
~CPUTimer() {
const auto end = Clock::now();
std::ostringstream strStream;
// strStream << "Destructor Elapsed: "
// << std::chrono::duration_cast<Resolution>(end - mStart).count()
// << std::endl;
// std::cout << strStream.str() << std::endl;
}
void stop(std::string const& label) {
const auto end = Clock::now();
std::ostringstream strStream;
strStream << "Stop Elapsed " << label << " : "
<< std::chrono::duration_cast<Resolution>(end - mStart).count()
<< std::endl;
std::cout << strStream.str() << std::endl;
}
};
constexpr unsigned NUM_BINS = 256;
void histogramCPU(unsigned int* input, unsigned int* res, unsigned int n)
{
for (unsigned i=0; i<n; ++i) {
res[input[i]]++;
}
}
__global__ void histogramGPUGlobalMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&res[input[i]], 1);
}
}
__global__ void histogramGPUSharedMem(unsigned *input, unsigned *res, unsigned n)
{
// Calculate global thread ID
int tid = blockIdx.x * blockDim.x + threadIdx.x;
// Allocate a local histogram for each TB
__shared__ int s_res[NUM_BINS];
// Initalize the shared memory to 0
if (threadIdx.x < NUM_BINS) {
s_res[threadIdx.x] = 0;
}
// Wait for shared memory writes to complete
__syncthreads();
for (size_t i = tid; i < n; i += (gridDim.x * blockDim.x)) {
atomicAdd(&s_res[input[i]], 1);
}
// Wait for shared memory writes to complete
__syncthreads();
// Combine the partial results
if (threadIdx.x < NUM_BINS) {
atomicAdd(&res[threadIdx.x], s_res[threadIdx.x]);
}
}
int main()
{
unsigned N = 1 << 16;
std::vector<unsigned> h_input(N);
std::vector<unsigned> h_result(NUM_BINS);
thrust::host_vector<unsigned> h_result_copy(NUM_BINS);
std::srand(42);
std::generate(std::begin(h_input), std::end(h_input), [] { return (unsigned)rand() % NUM_BINS; } );
CPUTimer<> cpu_timer;
histogramCPU(h_input.data(), h_result.data(), h_result.size());
cpu_timer.stop("histogramCPU");
thrust::device_vector<unsigned> d_input(h_input);
thrust::device_vector<unsigned> d_result(h_result_copy);
thrust::device_vector<unsigned> d_result2(h_result_copy);
// Number of threads per threadblock
size_t THREADS = 512;
// Calculate the number of threadblocks
size_t BLOCKS = N / THREADS;
GpuTimer timer;
timer.Start();
CPUTimer<> cpu_timer1;
histogramGPUGlobalMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result.data()),
d_result.size());
timer.Stop();
cpu_timer1.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUGlobalMem: " << timer.Elapsed() << " millisecs\n";
timer.Start();
CPUTimer<> cpu_timer2;
histogramGPUSharedMem<<<BLOCKS, THREADS>>>(thrust::raw_pointer_cast(d_input.data()),
thrust::raw_pointer_cast(d_result2.data()),
d_result2.size());
timer.Stop();
cpu_timer2.stop("histogramGPUGlobalMem");
std::cout << "elapsed for histogramGPUSharedMem: " << timer.Elapsed() << " millisecs\n";
auto compare_vals = [](std::string const& label,
auto const& arr1,
auto const& arr2) {
std::cout << "checking values: " << label << std::endl;
size_t mismatches = 0;
for (size_t i = 0; i < arr1.size(); ++i) {
if (arr1[i] != arr2[i]) {
++mismatches;
std::cout << "mismatch for index: " << i << " got:" << arr1[i] << " expected: " << arr2[i] << std::endl;
}
}
std::cout << mismatches << " mismatches for " << label << std::endl;
};
// copy back
h_result_copy = d_result;
compare_vals("h_result vs. d_result", h_result, h_result_copy);
// copy back
h_result_copy = d_result2;
compare_vals("h_result vs. d_result2", h_result, h_result_copy);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21histogramGPUGlobalMemPjS_j
.globl _Z21histogramGPUGlobalMemPjS_j
.p2align 8
.type _Z21histogramGPUGlobalMemPjS_j,@function
_Z21histogramGPUGlobalMemPjS_j:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v0, 1
s_mov_b32 s7, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s8, s6
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s1, s5
.p2align 6
.LBB0_2:
global_load_b32 v3, v[5:6], off
v_add_co_u32 v5, s0, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_atomic_add_u32 v[7:8], v0, off
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21histogramGPUGlobalMemPjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21histogramGPUGlobalMemPjS_j, .Lfunc_end0-_Z21histogramGPUGlobalMemPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21histogramGPUSharedMemPjS_j
.globl _Z21histogramGPUSharedMemPjS_j
.p2align 8
.type _Z21histogramGPUSharedMemPjS_j,@function
_Z21histogramGPUSharedMemPjS_j:
s_load_b32 s2, s[0:1], 0x24
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, 0xffff, s2
s_mov_b32 s5, 0
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s10, exec_lo
s_barrier
buffer_gl0_inv
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB1_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v5, 1
s_mov_b32 s7, s5
s_mov_b32 s11, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s2, s3
v_add_co_u32 v3, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
s_lshl_b64 s[8:9], s[6:7], 2
.p2align 6
.LBB1_4:
global_load_b32 v6, v[3:4], off
v_add_co_u32 v1, s2, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s7, v2, s2
v_add_co_u32 v3, s3, v3, s8
v_add_co_ci_u32_e64 v4, s3, s9, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u64_e64 s2, s[4:5], v[1:2]
s_or_b32 s11, s2, s11
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v6, 2, v6
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB1_4
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21histogramGPUSharedMemPjS_j
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21histogramGPUSharedMemPjS_j, .Lfunc_end1-_Z21histogramGPUSharedMemPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21histogramGPUGlobalMemPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21histogramGPUGlobalMemPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21histogramGPUSharedMemPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21histogramGPUSharedMemPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21histogramGPUSharedMemPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P1, PT, R4, 0xff, PT ; /* 0x000000ff0400780c */
/* 0x001fe20003f24070 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0204 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fca0000011400 */
/*0080*/ @!P1 STS [R4.X4], RZ ; /* 0x000000ff04009388 */
/* 0x0001e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00a0*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*00b0*/ @P0 BRA 0x190 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0002 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff067624 */
/* 0x000fe400078e00ff */
/*00e0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x001fc800078010ff */
/*00f0*/ LEA.HI.X R3, R0, c[0x0][0x164], R5, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1405 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD R7, R6, c[0x0][0x0], RZ ; /* 0x0000000006077a24 */
/* 0x000fe200078e02ff */
/*0120*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0130*/ IADD3 R0, P0, R7, R0, RZ ; /* 0x0000000007007210 */
/* 0x000fca0007f1e0ff */
/*0140*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe200000e0605 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0160*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f06100 */
/*0170*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0180*/ @!P0 BRA 0xe0 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01c0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e220000004800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0003 */
/*01f0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21histogramGPUGlobalMemPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff067624 */
/* 0x000fe400078e00ff */
/*00b0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*00c0*/ LEA.HI.X R5, R0, c[0x0][0x164], R7, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1407 */
/*00d0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x001ea2000c1e1900 */
/*00e0*/ IMAD R11, R6, c[0x0][0x0], RZ ; /* 0x00000000060b7a24 */
/* 0x000fe200078e02ff */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0110*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe40003800000 */
/*0120*/ IADD3 R0, P0, R11, R0, RZ ; /* 0x000000000b007210 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R7, RZ, R7, RZ, P0, !PT ; /* 0x00000007ff077210 */
/* 0x000fe400007fe4ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fe20003f06100 */
/*0160*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x004fca00078e0003 */
/*0170*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x0001ee000c10e184 */
/*0180*/ @!P0 BRA 0xb0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21histogramGPUGlobalMemPjS_j
.globl _Z21histogramGPUGlobalMemPjS_j
.p2align 8
.type _Z21histogramGPUGlobalMemPjS_j,@function
_Z21histogramGPUGlobalMemPjS_j:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_mov_b32 s5, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v0, 1
s_mov_b32 s7, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s8, s6
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 2
s_mov_b32 s1, s5
.p2align 6
.LBB0_2:
global_load_b32 v3, v[5:6], off
v_add_co_u32 v5, s0, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s9, v6, s0
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s6
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_atomic_add_u32 v[7:8], v0, off
v_cmp_le_u64_e32 vcc_lo, s[4:5], v[1:2]
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21histogramGPUGlobalMemPjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21histogramGPUGlobalMemPjS_j, .Lfunc_end0-_Z21histogramGPUGlobalMemPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21histogramGPUSharedMemPjS_j
.globl _Z21histogramGPUSharedMemPjS_j
.p2align 8
.type _Z21histogramGPUSharedMemPjS_j,@function
_Z21histogramGPUSharedMemPjS_j:
s_load_b32 s2, s[0:1], 0x24
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, 0xffff, s2
s_mov_b32 s5, 0
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s10, exec_lo
s_barrier
buffer_gl0_inv
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[1:2]
s_cbranch_execz .LBB1_5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v5, 1
s_mov_b32 s7, s5
s_mov_b32 s11, s5
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s2, s3
v_add_co_u32 v3, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
s_lshl_b64 s[8:9], s[6:7], 2
.p2align 6
.LBB1_4:
global_load_b32 v6, v[3:4], off
v_add_co_u32 v1, s2, v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s2, s7, v2, s2
v_add_co_u32 v3, s3, v3, s8
v_add_co_ci_u32_e64 v4, s3, s9, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u64_e64 s2, s[4:5], v[1:2]
s_or_b32 s11, s2, s11
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v6, 2, v6
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB1_4
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_7
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21histogramGPUSharedMemPjS_j
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21histogramGPUSharedMemPjS_j, .Lfunc_end1-_Z21histogramGPUSharedMemPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21histogramGPUGlobalMemPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21histogramGPUGlobalMemPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21histogramGPUSharedMemPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21histogramGPUSharedMemPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx: (%d, %d, %d) \n"
"blockIdx: (%d, %d, %d) \n"
"blockDim: (%d, %d, %d) \n"
"gridDim: (%d, %d, %d) \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main(int argc, char **argv){
const int nElem = 12;
dim3 block(4);
dim3 grid( (nElem + block.x - 1)/block.x );
// check the grid and block sizes on the host
printf("Block: (%d, %d, %d) \n"
"Grid: (%d, %d, %d) \n",
block.x, block.y, block.z, grid.x, grid.y, grid.z);
// check the grid and block sizes on the device
checkIndex <<< grid, block >>>();
// done
cudaDeviceReset();
return 0;
}
|
code for sm_80
Function : _Z10checkIndexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R18, c[0x0][0x10] ; /* 0x0000040000127a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.Z ; /* 0x00000000000a7919 */
/* 0x000e220000002300 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0f7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff107624 */
/* 0x000fe200078e00ff */
/*0090*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*00a0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff117624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a20000000a00 */
/*00c0*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff137624 */
/* 0x000fe200078e00ff */
/*00d0*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*00e0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R5, c[0x4][0xc] ; /* 0x0100030000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ S2R R13, SR_CTAID.Z ; /* 0x00000000000d7919 */
/* 0x000ee40000002700 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc400000e06ff */
/*0130*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000ee80000002600 */
/*0140*/ STL.128 [R1+0x20], R16 ; /* 0x0000201001007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100c00 */
/*0160*/ STL.128 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0083e40000100c00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx: (%d, %d, %d) \n"
"blockIdx: (%d, %d, %d) \n"
"blockDim: (%d, %d, %d) \n"
"gridDim: (%d, %d, %d) \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main(int argc, char **argv){
const int nElem = 12;
dim3 block(4);
dim3 grid( (nElem + block.x - 1)/block.x );
// check the grid and block sizes on the host
printf("Block: (%d, %d, %d) \n"
"Grid: (%d, %d, %d) \n",
block.x, block.y, block.z, grid.x, grid.y, grid.z);
// check the grid and block sizes on the device
checkIndex <<< grid, block >>>();
// done
cudaDeviceReset();
return 0;
}
|
.file "tmpxft_00066591_00000000-6_2.2-checkDimension.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Block: (%d, %d, %d) \nGrid: (%d, %d, %d) \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
pushq $1
.cfi_def_cfa_offset 56
pushq $1
.cfi_def_cfa_offset 64
movl $3, %r9d
movl $1, %r8d
movl $1, %ecx
movl $4, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx: (%d, %d, %d) \n"
"blockIdx: (%d, %d, %d) \n"
"blockDim: (%d, %d, %d) \n"
"gridDim: (%d, %d, %d) \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main(int argc, char **argv){
const int nElem = 12;
dim3 block(4);
dim3 grid( (nElem + block.x - 1)/block.x );
// check the grid and block sizes on the host
printf("Block: (%d, %d, %d) \n"
"Grid: (%d, %d, %d) \n",
block.x, block.y, block.z, grid.x, grid.y, grid.z);
// check the grid and block sizes on the device
checkIndex <<< grid, block >>>();
// done
cudaDeviceReset();
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx: (%d, %d, %d) \n"
"blockIdx: (%d, %d, %d) \n"
"blockDim: (%d, %d, %d) \n"
"gridDim: (%d, %d, %d) \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main(int argc, char **argv){
const int nElem = 12;
dim3 block(4);
dim3 grid( (nElem + block.x - 1)/block.x );
// check the grid and block sizes on the host
printf("Block: (%d, %d, %d) \n"
"Grid: (%d, %d, %d) \n",
block.x, block.y, block.z, grid.x, grid.y, grid.z);
// check the grid and block sizes on the device
checkIndex <<< grid, block >>>();
// done
hipDeviceReset();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void checkIndex(void) {
printf("threadIdx: (%d, %d, %d) \n"
"blockIdx: (%d, %d, %d) \n"
"blockDim: (%d, %d, %d) \n"
"gridDim: (%d, %d, %d) \n",
threadIdx.x, threadIdx.y, threadIdx.z,
blockIdx.x, blockIdx.y, blockIdx.z,
blockDim.x, blockDim.y, blockDim.z,
gridDim.x, gridDim.y, gridDim.z);
}
int main(int argc, char **argv){
const int nElem = 12;
dim3 block(4);
dim3 grid( (nElem + block.x - 1)/block.x );
// check the grid and block sizes on the host
printf("Block: (%d, %d, %d) \n"
"Grid: (%d, %d, %d) \n",
block.x, block.y, block.z, grid.x, grid.y, grid.z);
// check the grid and block sizes on the device
checkIndex <<< grid, block >>>();
// done
hipDeviceReset();
return 0;
}
|
.text
.file "2.2-checkDimension.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $64, %rsp
.cfi_adjust_cfa_offset 64
movl $.L.str, %edi
movl $4, %esi
movl $1, %edx
movl $1, %ecx
movl $3, %r8d
movl $1, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Block: (%d, %d, %d) \nGrid: (%d, %d, %d) \n"
.size .L.str, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00066591_00000000-6_2.2-checkDimension.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Block: (%d, %d, %d) \nGrid: (%d, %d, %d) \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
pushq $1
.cfi_def_cfa_offset 56
pushq $1
.cfi_def_cfa_offset 64
movl $3, %r9d
movl $1, %r8d
movl $1, %ecx
movl $4, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 24(%rsp)
movl $1, 28(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "2.2-checkDimension.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $64, %rsp
.cfi_adjust_cfa_offset 64
movl $.L.str, %edi
movl $4, %esi
movl $1, %edx
movl $1, %ecx
movl $3, %r8d
movl $1, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movabsq $4294967299, %rdi # imm = 0x100000003
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Block: (%d, %d, %d) \nGrid: (%d, %d, %d) \n"
.size .L.str, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void dotProduct_CUDA_double(double *sum, int size, double *vector1, double *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
if(idx < size){
sum[idx] = (vector2[idx]) * (vector1[idx]);
}
}
|
code for sm_80
Function : _Z22dotProduct_CUDA_doublePdiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x004e0e0000000000 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void dotProduct_CUDA_double(double *sum, int size, double *vector1, double *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
if(idx < size){
sum[idx] = (vector2[idx]) * (vector1[idx]);
}
}
|
.file "tmpxft_0006cd1b_00000000-6_dotProduct_CUDA_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_
.type _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_, @function
_Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22dotProduct_CUDA_doublePdiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_, .-_Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_
.globl _Z22dotProduct_CUDA_doublePdiS_S_
.type _Z22dotProduct_CUDA_doublePdiS_S_, @function
_Z22dotProduct_CUDA_doublePdiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22dotProduct_CUDA_doublePdiS_S_, .-_Z22dotProduct_CUDA_doublePdiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22dotProduct_CUDA_doublePdiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22dotProduct_CUDA_doublePdiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void dotProduct_CUDA_double(double *sum, int size, double *vector1, double *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
if(idx < size){
sum[idx] = (vector2[idx]) * (vector1[idx]);
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dotProduct_CUDA_double(double *sum, int size, double *vector1, double *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
if(idx < size){
sum[idx] = (vector2[idx]) * (vector1[idx]);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dotProduct_CUDA_double(double *sum, int size, double *vector1, double *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
if(idx < size){
sum[idx] = (vector2[idx]) * (vector1[idx]);
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22dotProduct_CUDA_doublePdiS_S_
.globl _Z22dotProduct_CUDA_doublePdiS_S_
.p2align 8
.type _Z22dotProduct_CUDA_doublePdiS_S_,@function
_Z22dotProduct_CUDA_doublePdiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22dotProduct_CUDA_doublePdiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22dotProduct_CUDA_doublePdiS_S_, .Lfunc_end0-_Z22dotProduct_CUDA_doublePdiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22dotProduct_CUDA_doublePdiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22dotProduct_CUDA_doublePdiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dotProduct_CUDA_double(double *sum, int size, double *vector1, double *vector2){
int idx = blockIdx.x*blockDim.x+threadIdx.x; // Sequential thread index across the blocks
if(idx < size){
sum[idx] = (vector2[idx]) * (vector1[idx]);
}
}
|
.text
.file "dotProduct_CUDA_double.hip"
.globl _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_ # -- Begin function _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.p2align 4, 0x90
.type _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_,@function
_Z37__device_stub__dotProduct_CUDA_doublePdiS_S_: # @_Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22dotProduct_CUDA_doublePdiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_, .Lfunc_end0-_Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22dotProduct_CUDA_doublePdiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22dotProduct_CUDA_doublePdiS_S_,@object # @_Z22dotProduct_CUDA_doublePdiS_S_
.section .rodata,"a",@progbits
.globl _Z22dotProduct_CUDA_doublePdiS_S_
.p2align 3, 0x0
_Z22dotProduct_CUDA_doublePdiS_S_:
.quad _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.size _Z22dotProduct_CUDA_doublePdiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22dotProduct_CUDA_doublePdiS_S_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22dotProduct_CUDA_doublePdiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z22dotProduct_CUDA_doublePdiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x004e0e0000000000 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22dotProduct_CUDA_doublePdiS_S_
.globl _Z22dotProduct_CUDA_doublePdiS_S_
.p2align 8
.type _Z22dotProduct_CUDA_doublePdiS_S_,@function
_Z22dotProduct_CUDA_doublePdiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22dotProduct_CUDA_doublePdiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22dotProduct_CUDA_doublePdiS_S_, .Lfunc_end0-_Z22dotProduct_CUDA_doublePdiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22dotProduct_CUDA_doublePdiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22dotProduct_CUDA_doublePdiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0006cd1b_00000000-6_dotProduct_CUDA_double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_
.type _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_, @function
_Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22dotProduct_CUDA_doublePdiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_, .-_Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_
.globl _Z22dotProduct_CUDA_doublePdiS_S_
.type _Z22dotProduct_CUDA_doublePdiS_S_, @function
_Z22dotProduct_CUDA_doublePdiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22dotProduct_CUDA_doublePdiS_S_PdiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22dotProduct_CUDA_doublePdiS_S_, .-_Z22dotProduct_CUDA_doublePdiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22dotProduct_CUDA_doublePdiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22dotProduct_CUDA_doublePdiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "dotProduct_CUDA_double.hip"
.globl _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_ # -- Begin function _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.p2align 4, 0x90
.type _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_,@function
_Z37__device_stub__dotProduct_CUDA_doublePdiS_S_: # @_Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22dotProduct_CUDA_doublePdiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_, .Lfunc_end0-_Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22dotProduct_CUDA_doublePdiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22dotProduct_CUDA_doublePdiS_S_,@object # @_Z22dotProduct_CUDA_doublePdiS_S_
.section .rodata,"a",@progbits
.globl _Z22dotProduct_CUDA_doublePdiS_S_
.p2align 3, 0x0
_Z22dotProduct_CUDA_doublePdiS_S_:
.quad _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.size _Z22dotProduct_CUDA_doublePdiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22dotProduct_CUDA_doublePdiS_S_"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__dotProduct_CUDA_doublePdiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22dotProduct_CUDA_doublePdiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 1024
__global__ void findMaxInBlock(int *d_arr, int* gpu_return) {
extern __shared__ int s_arr[];
int tid = threadIdx.x;
int index = blockIdx.x * MAX_THREADS_PER_BLOCK + threadIdx.x;
s_arr[tid] = d_arr[index];
__syncthreads();
for (int offset = 1; offset < blockDim.x; offset *=2) {
if (tid % (2*offset) == 0) {
if (s_arr[tid] < s_arr[tid + offset]) {
s_arr[tid] = s_arr[tid + offset];
}
}
__syncthreads();
}
if (tid == 0) {
gpu_return[blockIdx.x] = s_arr[tid];
}
}
void random_ints(int* a, int N) {
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % (10000 + 1 - 0) + 0;
}
int main(void) {
struct timeval cpu_start, cpu_end;
struct timeval gpu_start, gpu_end;
int *arr, *d_arr;
int cpu_result, cpu_return;
int *gpu_result, *gpu_return;
int N;
scanf("%d", &N);
int array_size = N * sizeof(int);
int integer_size = sizeof(int);
int block_number = N / MAX_THREADS_PER_BLOCK;
int thread_number = MAX_THREADS_PER_BLOCK;
gpu_result = (int *)malloc(integer_size * block_number);
arr = (int *)malloc(array_size);
random_ints(arr, N);
cudaMalloc((void **) &d_arr, array_size);
cudaMemcpy(d_arr, arr, array_size, cudaMemcpyHostToDevice);
gettimeofday(&gpu_start, NULL);
findMaxInBlock<<<block_number
,thread_number>>>
(d_arr, gpu_return);
gettimeofday(&gpu_end, NULL);
cudaMemcpy(gpu_result, gpu_return, integer_size * block_number, cudaMemcpyDeviceToHost);
cpu_return = 0;
gettimeofday(&cpu_start, NULL);
for (int i = 0; i < N; i++) {
int num = arr[i];
if (cpu_return < num) {
cpu_return = num;
}
}
gettimeofday(&cpu_end, NULL);
cpu_result = cpu_return;
printf("GPU result: %d GPU run time: %ld\n", gpu_result[1],(gpu_end.tv_usec - gpu_start.tv_usec));
printf("CPU result: %d CPU run time: %ld\n",cpu_result, (cpu_end.tv_usec - cpu_start.tv_usec));
}
|
code for sm_80
Function : _Z14findMaxInBlockPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R0, 0x400, R3 ; /* 0x0000040000047824 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fc80000000f00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06070 */
/*00a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00c0*/ @!P0 BRA 0x340 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IABS R8, R3 ; /* 0x0000000300087213 */
/* 0x001fe20000000000 */
/*00e0*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x000fc400078e00ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fca00078e00ff */
/*0100*/ MOV R11, R6 ; /* 0x00000006000b7202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206067824 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f46270 */
/*0130*/ BSSY B0, 0x310 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*0140*/ IABS R10, R6.reuse ; /* 0x00000006000a7213 */
/* 0x080fe40000000000 */
/*0150*/ IABS R12, R6 ; /* 0x00000006000c7213 */
/* 0x000fe40000000000 */
/*0160*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x001e260000209400 */
/*0170*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0a0c */
/*0180*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fe40007ffe0ff */
/*01a0*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x000fc80000000000 */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*01d0*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*01e0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x000fca00078e02ff */
/*01f0*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0200*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD R5, R5, R12, R7 ; /* 0x0000000c05057224 */
/* 0x000fca00078e0207 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f04070 */
/*0230*/ @!P0 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0a */
/*0240*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IADD3 R5, R5, -R10, RZ ; /* 0x8000000a05059210 */
/* 0x000fca0007ffe0ff */
/*0270*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*0280*/ @!P0 LOP3.LUT R5, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff058212 */
/* 0x000fc800078e33ff */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02a0*/ @P0 BRA 0x300 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD R5, R11, 0x4, R2 ; /* 0x000000040b057824 */
/* 0x000fe200078e0202 */
/*02c0*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fea0000004800 */
/*02d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*02e0*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x001fda0003f06270 */
/*02f0*/ @!P0 STS [R3.X4], R5 ; /* 0x0000000503008388 */
/* 0x0001e40000004800 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f06070 */
/*0330*/ @!P0 BRA 0x100 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*0340*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fda0003f05270 */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0370*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0380*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0390*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 1024
__global__ void findMaxInBlock(int *d_arr, int* gpu_return) {
extern __shared__ int s_arr[];
int tid = threadIdx.x;
int index = blockIdx.x * MAX_THREADS_PER_BLOCK + threadIdx.x;
s_arr[tid] = d_arr[index];
__syncthreads();
for (int offset = 1; offset < blockDim.x; offset *=2) {
if (tid % (2*offset) == 0) {
if (s_arr[tid] < s_arr[tid + offset]) {
s_arr[tid] = s_arr[tid + offset];
}
}
__syncthreads();
}
if (tid == 0) {
gpu_return[blockIdx.x] = s_arr[tid];
}
}
void random_ints(int* a, int N) {
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % (10000 + 1 - 0) + 0;
}
int main(void) {
struct timeval cpu_start, cpu_end;
struct timeval gpu_start, gpu_end;
int *arr, *d_arr;
int cpu_result, cpu_return;
int *gpu_result, *gpu_return;
int N;
scanf("%d", &N);
int array_size = N * sizeof(int);
int integer_size = sizeof(int);
int block_number = N / MAX_THREADS_PER_BLOCK;
int thread_number = MAX_THREADS_PER_BLOCK;
gpu_result = (int *)malloc(integer_size * block_number);
arr = (int *)malloc(array_size);
random_ints(arr, N);
cudaMalloc((void **) &d_arr, array_size);
cudaMemcpy(d_arr, arr, array_size, cudaMemcpyHostToDevice);
gettimeofday(&gpu_start, NULL);
findMaxInBlock<<<block_number
,thread_number>>>
(d_arr, gpu_return);
gettimeofday(&gpu_end, NULL);
cudaMemcpy(gpu_result, gpu_return, integer_size * block_number, cudaMemcpyDeviceToHost);
cpu_return = 0;
gettimeofday(&cpu_start, NULL);
for (int i = 0; i < N; i++) {
int num = arr[i];
if (cpu_return < num) {
cpu_return = num;
}
}
gettimeofday(&cpu_end, NULL);
cpu_result = cpu_return;
printf("GPU result: %d GPU run time: %ld\n", gpu_result[1],(gpu_end.tv_usec - gpu_start.tv_usec));
printf("CPU result: %d CPU run time: %ld\n",cpu_result, (cpu_end.tv_usec - cpu_start.tv_usec));
}
|
.file "tmpxft_000d856c_00000000-6_max.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $-776881895, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $13, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10001, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z36__device_stub__Z14findMaxInBlockPiS_PiS_
.type _Z36__device_stub__Z14findMaxInBlockPiS_PiS_, @function
_Z36__device_stub__Z14findMaxInBlockPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14findMaxInBlockPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z14findMaxInBlockPiS_PiS_, .-_Z36__device_stub__Z14findMaxInBlockPiS_PiS_
.globl _Z14findMaxInBlockPiS_
.type _Z14findMaxInBlockPiS_, @function
_Z14findMaxInBlockPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14findMaxInBlockPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14findMaxInBlockPiS_, .-_Z14findMaxInBlockPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU result: %d GPU run time: %ld\n"
.align 8
.LC2:
.string "CPU result: %d CPU run time: %ld\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 4(%rsp), %r14d
leal 1023(%r14), %ebx
testl %r14d, %r14d
cmovns %r14d, %ebx
sarl $10, %ebx
leal 0(,%rbx,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
leal 0(,%r14,4), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, %esi
movq %rax, %rdi
call _Z11random_intsPii
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %r15, %rdx
movl $0, %esi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 4(%rsp), %edx
testl %edx, %edx
jle .L24
movq %r12, %rax
movslq %edx, %rdx
leaq (%r12,%rdx,4), %rcx
movl $0, %ebx
.L22:
movl (%rax), %edx
cmpl %edx, %ebx
cmovl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L22
.L21:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rcx
subq 56(%rsp), %rcx
movl 4(%rbp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rcx
subq 24(%rsp), %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $0, %esi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14findMaxInBlockPiS_PiS_
jmp .L20
.L24:
movl $0, %ebx
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14findMaxInBlockPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14findMaxInBlockPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 1024
__global__ void findMaxInBlock(int *d_arr, int* gpu_return) {
extern __shared__ int s_arr[];
int tid = threadIdx.x;
int index = blockIdx.x * MAX_THREADS_PER_BLOCK + threadIdx.x;
s_arr[tid] = d_arr[index];
__syncthreads();
for (int offset = 1; offset < blockDim.x; offset *=2) {
if (tid % (2*offset) == 0) {
if (s_arr[tid] < s_arr[tid + offset]) {
s_arr[tid] = s_arr[tid + offset];
}
}
__syncthreads();
}
if (tid == 0) {
gpu_return[blockIdx.x] = s_arr[tid];
}
}
void random_ints(int* a, int N) {
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % (10000 + 1 - 0) + 0;
}
int main(void) {
struct timeval cpu_start, cpu_end;
struct timeval gpu_start, gpu_end;
int *arr, *d_arr;
int cpu_result, cpu_return;
int *gpu_result, *gpu_return;
int N;
scanf("%d", &N);
int array_size = N * sizeof(int);
int integer_size = sizeof(int);
int block_number = N / MAX_THREADS_PER_BLOCK;
int thread_number = MAX_THREADS_PER_BLOCK;
gpu_result = (int *)malloc(integer_size * block_number);
arr = (int *)malloc(array_size);
random_ints(arr, N);
cudaMalloc((void **) &d_arr, array_size);
cudaMemcpy(d_arr, arr, array_size, cudaMemcpyHostToDevice);
gettimeofday(&gpu_start, NULL);
findMaxInBlock<<<block_number
,thread_number>>>
(d_arr, gpu_return);
gettimeofday(&gpu_end, NULL);
cudaMemcpy(gpu_result, gpu_return, integer_size * block_number, cudaMemcpyDeviceToHost);
cpu_return = 0;
gettimeofday(&cpu_start, NULL);
for (int i = 0; i < N; i++) {
int num = arr[i];
if (cpu_return < num) {
cpu_return = num;
}
}
gettimeofday(&cpu_end, NULL);
cpu_result = cpu_return;
printf("GPU result: %d GPU run time: %ld\n", gpu_result[1],(gpu_end.tv_usec - gpu_start.tv_usec));
printf("CPU result: %d CPU run time: %ld\n",cpu_result, (cpu_end.tv_usec - cpu_start.tv_usec));
}
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 1024
__global__ void findMaxInBlock(int *d_arr, int* gpu_return) {
extern __shared__ int s_arr[];
int tid = threadIdx.x;
int index = blockIdx.x * MAX_THREADS_PER_BLOCK + threadIdx.x;
s_arr[tid] = d_arr[index];
__syncthreads();
for (int offset = 1; offset < blockDim.x; offset *=2) {
if (tid % (2*offset) == 0) {
if (s_arr[tid] < s_arr[tid + offset]) {
s_arr[tid] = s_arr[tid + offset];
}
}
__syncthreads();
}
if (tid == 0) {
gpu_return[blockIdx.x] = s_arr[tid];
}
}
void random_ints(int* a, int N) {
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % (10000 + 1 - 0) + 0;
}
int main(void) {
struct timeval cpu_start, cpu_end;
struct timeval gpu_start, gpu_end;
int *arr, *d_arr;
int cpu_result, cpu_return;
int *gpu_result, *gpu_return;
int N;
scanf("%d", &N);
int array_size = N * sizeof(int);
int integer_size = sizeof(int);
int block_number = N / MAX_THREADS_PER_BLOCK;
int thread_number = MAX_THREADS_PER_BLOCK;
gpu_result = (int *)malloc(integer_size * block_number);
arr = (int *)malloc(array_size);
random_ints(arr, N);
hipMalloc((void **) &d_arr, array_size);
hipMemcpy(d_arr, arr, array_size, hipMemcpyHostToDevice);
gettimeofday(&gpu_start, NULL);
findMaxInBlock<<<block_number
,thread_number>>>
(d_arr, gpu_return);
gettimeofday(&gpu_end, NULL);
hipMemcpy(gpu_result, gpu_return, integer_size * block_number, hipMemcpyDeviceToHost);
cpu_return = 0;
gettimeofday(&cpu_start, NULL);
for (int i = 0; i < N; i++) {
int num = arr[i];
if (cpu_return < num) {
cpu_return = num;
}
}
gettimeofday(&cpu_end, NULL);
cpu_result = cpu_return;
printf("GPU result: %d GPU run time: %ld\n", gpu_result[1],(gpu_end.tv_usec - gpu_start.tv_usec));
printf("CPU result: %d CPU run time: %ld\n",cpu_result, (cpu_end.tv_usec - cpu_start.tv_usec));
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 1024
__global__ void findMaxInBlock(int *d_arr, int* gpu_return) {
extern __shared__ int s_arr[];
int tid = threadIdx.x;
int index = blockIdx.x * MAX_THREADS_PER_BLOCK + threadIdx.x;
s_arr[tid] = d_arr[index];
__syncthreads();
for (int offset = 1; offset < blockDim.x; offset *=2) {
if (tid % (2*offset) == 0) {
if (s_arr[tid] < s_arr[tid + offset]) {
s_arr[tid] = s_arr[tid + offset];
}
}
__syncthreads();
}
if (tid == 0) {
gpu_return[blockIdx.x] = s_arr[tid];
}
}
void random_ints(int* a, int N) {
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % (10000 + 1 - 0) + 0;
}
int main(void) {
struct timeval cpu_start, cpu_end;
struct timeval gpu_start, gpu_end;
int *arr, *d_arr;
int cpu_result, cpu_return;
int *gpu_result, *gpu_return;
int N;
scanf("%d", &N);
int array_size = N * sizeof(int);
int integer_size = sizeof(int);
int block_number = N / MAX_THREADS_PER_BLOCK;
int thread_number = MAX_THREADS_PER_BLOCK;
gpu_result = (int *)malloc(integer_size * block_number);
arr = (int *)malloc(array_size);
random_ints(arr, N);
hipMalloc((void **) &d_arr, array_size);
hipMemcpy(d_arr, arr, array_size, hipMemcpyHostToDevice);
gettimeofday(&gpu_start, NULL);
findMaxInBlock<<<block_number
,thread_number>>>
(d_arr, gpu_return);
gettimeofday(&gpu_end, NULL);
hipMemcpy(gpu_result, gpu_return, integer_size * block_number, hipMemcpyDeviceToHost);
cpu_return = 0;
gettimeofday(&cpu_start, NULL);
for (int i = 0; i < N; i++) {
int num = arr[i];
if (cpu_return < num) {
cpu_return = num;
}
}
gettimeofday(&cpu_end, NULL);
cpu_result = cpu_return;
printf("GPU result: %d GPU run time: %ld\n", gpu_result[1],(gpu_end.tv_usec - gpu_start.tv_usec));
printf("CPU result: %d CPU run time: %ld\n",cpu_result, (cpu_end.tv_usec - cpu_start.tv_usec));
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14findMaxInBlockPiS_
.globl _Z14findMaxInBlockPiS_
.p2align 8
.type _Z14findMaxInBlockPiS_,@function
_Z14findMaxInBlockPiS_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x1c
s_mov_b32 s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v1, s2, 10, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_cmp_lt_u16_e64 s4, s3, 2
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_and_b32 vcc_lo, exec_lo, s4
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_6
s_and_b32 s3, 0xffff, s3
s_mov_b32 s4, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_ge_u32 s4, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_mov_b32 s6, s4
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, -1
v_and_b32_e32 v2, s5, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_6:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14findMaxInBlockPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14findMaxInBlockPiS_, .Lfunc_end0-_Z14findMaxInBlockPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14findMaxInBlockPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14findMaxInBlockPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define MAX_THREADS_PER_BLOCK 1024
__global__ void findMaxInBlock(int *d_arr, int* gpu_return) {
extern __shared__ int s_arr[];
int tid = threadIdx.x;
int index = blockIdx.x * MAX_THREADS_PER_BLOCK + threadIdx.x;
s_arr[tid] = d_arr[index];
__syncthreads();
for (int offset = 1; offset < blockDim.x; offset *=2) {
if (tid % (2*offset) == 0) {
if (s_arr[tid] < s_arr[tid + offset]) {
s_arr[tid] = s_arr[tid + offset];
}
}
__syncthreads();
}
if (tid == 0) {
gpu_return[blockIdx.x] = s_arr[tid];
}
}
void random_ints(int* a, int N) {
int i;
for (i = 0; i < N; ++i)
a[i] = rand() % (10000 + 1 - 0) + 0;
}
int main(void) {
struct timeval cpu_start, cpu_end;
struct timeval gpu_start, gpu_end;
int *arr, *d_arr;
int cpu_result, cpu_return;
int *gpu_result, *gpu_return;
int N;
scanf("%d", &N);
int array_size = N * sizeof(int);
int integer_size = sizeof(int);
int block_number = N / MAX_THREADS_PER_BLOCK;
int thread_number = MAX_THREADS_PER_BLOCK;
gpu_result = (int *)malloc(integer_size * block_number);
arr = (int *)malloc(array_size);
random_ints(arr, N);
hipMalloc((void **) &d_arr, array_size);
hipMemcpy(d_arr, arr, array_size, hipMemcpyHostToDevice);
gettimeofday(&gpu_start, NULL);
findMaxInBlock<<<block_number
,thread_number>>>
(d_arr, gpu_return);
gettimeofday(&gpu_end, NULL);
hipMemcpy(gpu_result, gpu_return, integer_size * block_number, hipMemcpyDeviceToHost);
cpu_return = 0;
gettimeofday(&cpu_start, NULL);
for (int i = 0; i < N; i++) {
int num = arr[i];
if (cpu_return < num) {
cpu_return = num;
}
}
gettimeofday(&cpu_end, NULL);
cpu_result = cpu_return;
printf("GPU result: %d GPU run time: %ld\n", gpu_result[1],(gpu_end.tv_usec - gpu_start.tv_usec));
printf("CPU result: %d CPU run time: %ld\n",cpu_result, (cpu_end.tv_usec - cpu_start.tv_usec));
}
|
.text
.file "max.hip"
.globl _Z29__device_stub__findMaxInBlockPiS_ # -- Begin function _Z29__device_stub__findMaxInBlockPiS_
.p2align 4, 0x90
.type _Z29__device_stub__findMaxInBlockPiS_,@function
_Z29__device_stub__findMaxInBlockPiS_: # @_Z29__device_stub__findMaxInBlockPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14findMaxInBlockPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__findMaxInBlockPiS_, .Lfunc_end0-_Z29__device_stub__findMaxInBlockPiS_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-776881895, %rax, %rcx # imm = 0xD1B1B919
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $13, %ecx
addl %edx, %ecx
imull $10001, %ecx, %ecx # imm = 0x2711
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %ebp
leal 1023(%rbp), %r13d
testl %ebp, %ebp
cmovnsl %ebp, %r13d
leal (,%rbp,4), %ebx
sarl $10, %r13d
leal (,%r13,4), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movslq %ebx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-776881895, %rax, %rcx # imm = 0xD1B1B919
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $13, %ecx
addl %edx, %ecx
imull $10001, %ecx, %ecx # imm = 0x2711
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq %rbx, %rbp
jne .LBB2_2
.LBB2_3: # %_Z11random_intsPii.exit
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rax
movq %rax, 24(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14findMaxInBlockPiS_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB2_8
# %bb.6: # %.lr.ph.preheader
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%rcx,4), %r12d
cmpl %r12d, %edx
cmovgl %edx, %r12d
incq %rcx
movl %r12d, %edx
cmpq %rcx, %rax
jne .LBB2_7
.LBB2_8: # %._crit_edge
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rbx), %esi
movq 40(%rsp), %rdx
subq 104(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 56(%rsp), %rdx
subq 24(%rsp), %rdx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14findMaxInBlockPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14findMaxInBlockPiS_,@object # @_Z14findMaxInBlockPiS_
.section .rodata,"a",@progbits
.globl _Z14findMaxInBlockPiS_
.p2align 3, 0x0
_Z14findMaxInBlockPiS_:
.quad _Z29__device_stub__findMaxInBlockPiS_
.size _Z14findMaxInBlockPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU result: %d GPU run time: %ld\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU result: %d CPU run time: %ld\n"
.size .L.str.2, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14findMaxInBlockPiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__findMaxInBlockPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14findMaxInBlockPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z14findMaxInBlockPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R0, 0x400, R3 ; /* 0x0000040000047824 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fc80000000f00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f06070 */
/*00a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00c0*/ @!P0 BRA 0x340 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IABS R8, R3 ; /* 0x0000000300087213 */
/* 0x001fe20000000000 */
/*00e0*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x000fc400078e00ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fca00078e00ff */
/*0100*/ MOV R11, R6 ; /* 0x00000006000b7202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206067824 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f46270 */
/*0130*/ BSSY B0, 0x310 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*0140*/ IABS R10, R6.reuse ; /* 0x00000006000a7213 */
/* 0x080fe40000000000 */
/*0150*/ IABS R12, R6 ; /* 0x00000006000c7213 */
/* 0x000fe40000000000 */
/*0160*/ I2F.RP R7, R10 ; /* 0x0000000a00077306 */
/* 0x001e260000209400 */
/*0170*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fca00078e0a0c */
/*0180*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fe40007ffe0ff */
/*01a0*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x000fc80000000000 */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01c0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*01d0*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*01e0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x000fca00078e02ff */
/*01f0*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0200*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD R5, R5, R12, R7 ; /* 0x0000000c05057224 */
/* 0x000fca00078e0207 */
/*0220*/ ISETP.GT.U32.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f04070 */
/*0230*/ @!P0 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105058824 */
/* 0x000fe200078e0a0a */
/*0240*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IADD3 R5, R5, -R10, RZ ; /* 0x8000000a05059210 */
/* 0x000fca0007ffe0ff */
/*0270*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*0280*/ @!P0 LOP3.LUT R5, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff058212 */
/* 0x000fc800078e33ff */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02a0*/ @P0 BRA 0x300 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD R5, R11, 0x4, R2 ; /* 0x000000040b057824 */
/* 0x000fe200078e0202 */
/*02c0*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fea0000004800 */
/*02d0*/ LDS R5, [R5] ; /* 0x0000000005057984 */
/* 0x000e240000000800 */
/*02e0*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x001fda0003f06270 */
/*02f0*/ @!P0 STS [R3.X4], R5 ; /* 0x0000000503008388 */
/* 0x0001e40000004800 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f06070 */
/*0330*/ @!P0 BRA 0x100 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*0340*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x001fda0003f05270 */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0370*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0380*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0390*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14findMaxInBlockPiS_
.globl _Z14findMaxInBlockPiS_
.p2align 8
.type _Z14findMaxInBlockPiS_,@function
_Z14findMaxInBlockPiS_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x1c
s_mov_b32 s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_or_b32 v1, s2, 10, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_cmp_lt_u16_e64 s4, s3, 2
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_and_b32 vcc_lo, exec_lo, s4
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_6
s_and_b32 s3, 0xffff, s3
s_mov_b32 s4, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_ge_u32 s4, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_mov_b32 s6, s4
s_lshl_b32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s4, -1
v_and_b32_e32 v2, s5, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_6:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
s_mov_b32 s3, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14findMaxInBlockPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14findMaxInBlockPiS_, .Lfunc_end0-_Z14findMaxInBlockPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14findMaxInBlockPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14findMaxInBlockPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d856c_00000000-6_max.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $-776881895, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $13, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10001, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z36__device_stub__Z14findMaxInBlockPiS_PiS_
.type _Z36__device_stub__Z14findMaxInBlockPiS_PiS_, @function
_Z36__device_stub__Z14findMaxInBlockPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14findMaxInBlockPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z14findMaxInBlockPiS_PiS_, .-_Z36__device_stub__Z14findMaxInBlockPiS_PiS_
.globl _Z14findMaxInBlockPiS_
.type _Z14findMaxInBlockPiS_, @function
_Z14findMaxInBlockPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14findMaxInBlockPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14findMaxInBlockPiS_, .-_Z14findMaxInBlockPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU result: %d GPU run time: %ld\n"
.align 8
.LC2:
.string "CPU result: %d CPU run time: %ld\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 4(%rsp), %r14d
leal 1023(%r14), %ebx
testl %r14d, %r14d
cmovns %r14d, %ebx
sarl $10, %ebx
leal 0(,%rbx,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
leal 0(,%r14,4), %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, %esi
movq %rax, %rdi
call _Z11random_intsPii
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L20:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %r15, %rdx
movl $0, %esi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 4(%rsp), %edx
testl %edx, %edx
jle .L24
movq %r12, %rax
movslq %edx, %rdx
leaq (%r12,%rdx,4), %rcx
movl $0, %ebx
.L22:
movl (%rax), %edx
cmpl %edx, %ebx
cmovl %edx, %ebx
addq $4, %rax
cmpq %rcx, %rax
jne .L22
.L21:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rcx
subq 56(%rsp), %rcx
movl 4(%rbp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rcx
subq 24(%rsp), %rcx
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $0, %esi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14findMaxInBlockPiS_PiS_
jmp .L20
.L24:
movl $0, %ebx
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14findMaxInBlockPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14findMaxInBlockPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "max.hip"
.globl _Z29__device_stub__findMaxInBlockPiS_ # -- Begin function _Z29__device_stub__findMaxInBlockPiS_
.p2align 4, 0x90
.type _Z29__device_stub__findMaxInBlockPiS_,@function
_Z29__device_stub__findMaxInBlockPiS_: # @_Z29__device_stub__findMaxInBlockPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14findMaxInBlockPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__findMaxInBlockPiS_, .Lfunc_end0-_Z29__device_stub__findMaxInBlockPiS_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-776881895, %rax, %rcx # imm = 0xD1B1B919
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $13, %ecx
addl %edx, %ecx
imull $10001, %ecx, %ecx # imm = 0x2711
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 4(%rsp), %ebp
leal 1023(%rbp), %r13d
testl %ebp, %ebp
cmovnsl %ebp, %r13d
leal (,%rbp,4), %ebx
sarl $10, %r13d
leal (,%r13,4), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movslq %ebx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-776881895, %rax, %rcx # imm = 0xD1B1B919
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $13, %ecx
addl %edx, %ecx
imull $10001, %ecx, %ecx # imm = 0x2711
subl %ecx, %eax
movl %eax, (%r14,%rbx,4)
incq %rbx
cmpq %rbx, %rbp
jne .LBB2_2
.LBB2_3: # %_Z11random_intsPii.exit
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %r12d, %r12d
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %r13d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rax
movq %rax, 24(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z14findMaxInBlockPiS_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB2_8
# %bb.6: # %.lr.ph.preheader
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_7: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%rcx,4), %r12d
cmpl %r12d, %edx
cmovgl %edx, %r12d
incq %rcx
movl %r12d, %edx
cmpq %rcx, %rax
jne .LBB2_7
.LBB2_8: # %._crit_edge
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 4(%rbx), %esi
movq 40(%rsp), %rdx
subq 104(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 56(%rsp), %rdx
subq 24(%rsp), %rdx
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14findMaxInBlockPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14findMaxInBlockPiS_,@object # @_Z14findMaxInBlockPiS_
.section .rodata,"a",@progbits
.globl _Z14findMaxInBlockPiS_
.p2align 3, 0x0
_Z14findMaxInBlockPiS_:
.quad _Z29__device_stub__findMaxInBlockPiS_
.size _Z14findMaxInBlockPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU result: %d GPU run time: %ld\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU result: %d CPU run time: %ld\n"
.size .L.str.2, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14findMaxInBlockPiS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__findMaxInBlockPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14findMaxInBlockPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <device_launch_parameters.h>
#define N 32 //allocate space for vars; this will end up being the number of blocks to iterate over (we want this to be multiples of 32)
__global__ void Caps(char *c, int *b)
{
int tid = blockIdx.x;
if (tid < N)
{
if (b[tid] == 1)
{
int ascii = (int)c[tid];
ascii -= 32;
c[tid] = (char)ascii;
}
}
}
int main()
{
int a[] = {1, 4, 6, 8, 11, 30};
char String[N];
int *b;
char *c;
//geneate 32 character string
for(int i=0;i<N;i++){
if (i % 5 == 0) { String[i] = 'a'; }
if (i % 5 == 1) { String[i] = 'b'; }
if (i % 5 == 2) { String[i] = 'c'; }
if (i % 5 == 3) { String[i] = 'd'; }
if (i % 5 == 4) { String[i] = 'e'; }
}
int temp[sizeof(String)/sizeof(char)];
for (int i = 0; i < (sizeof(String)/sizeof(char)); i++)
{
temp[i]=0;
}
for (int i = 0; i < (sizeof(a)/sizeof(int)); i++)
{
int val=a[i];
temp[val]=1;
}
cudaMalloc((void**)&c, N * sizeof(char));
cudaMalloc((void**)&b, N * sizeof(int));
cudaMemcpy(b, &temp, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c, &String, N * sizeof(char), cudaMemcpyHostToDevice);
Caps<<<N, 1>>>(c, b);
cudaMemcpy(&String, c, N * sizeof(char), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
printf("%c", String[i]);
}
printf("\n");
cudaFree(b);
cudaFree(c);
return 0;
}
|
code for sm_80
Function : _Z4CapsPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*00d0*/ IADD3 R5, R0, -0x20, RZ ; /* 0xffffffe000057810 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <device_launch_parameters.h>
#define N 32 //allocate space for vars; this will end up being the number of blocks to iterate over (we want this to be multiples of 32)
__global__ void Caps(char *c, int *b)
{
int tid = blockIdx.x;
if (tid < N)
{
if (b[tid] == 1)
{
int ascii = (int)c[tid];
ascii -= 32;
c[tid] = (char)ascii;
}
}
}
int main()
{
int a[] = {1, 4, 6, 8, 11, 30};
char String[N];
int *b;
char *c;
//geneate 32 character string
for(int i=0;i<N;i++){
if (i % 5 == 0) { String[i] = 'a'; }
if (i % 5 == 1) { String[i] = 'b'; }
if (i % 5 == 2) { String[i] = 'c'; }
if (i % 5 == 3) { String[i] = 'd'; }
if (i % 5 == 4) { String[i] = 'e'; }
}
int temp[sizeof(String)/sizeof(char)];
for (int i = 0; i < (sizeof(String)/sizeof(char)); i++)
{
temp[i]=0;
}
for (int i = 0; i < (sizeof(a)/sizeof(int)); i++)
{
int val=a[i];
temp[val]=1;
}
cudaMalloc((void**)&c, N * sizeof(char));
cudaMalloc((void**)&b, N * sizeof(int));
cudaMemcpy(b, &temp, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c, &String, N * sizeof(char), cudaMemcpyHostToDevice);
Caps<<<N, 1>>>(c, b);
cudaMemcpy(&String, c, N * sizeof(char), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
printf("%c", String[i]);
}
printf("\n");
cudaFree(b);
cudaFree(c);
return 0;
}
|
.file "tmpxft_00166af3_00000000-6_Capitalization.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4CapsPcPiPcPi
.type _Z25__device_stub__Z4CapsPcPiPcPi, @function
_Z25__device_stub__Z4CapsPcPiPcPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4CapsPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z4CapsPcPiPcPi, .-_Z25__device_stub__Z4CapsPcPiPcPi
.globl _Z4CapsPcPi
.type _Z4CapsPcPi, @function
_Z4CapsPcPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4CapsPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4CapsPcPi, .-_Z4CapsPcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%c"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $4, 52(%rsp)
movl $6, 56(%rsp)
movl $8, 60(%rsp)
movl $11, 64(%rsp)
movl $30, 68(%rsp)
leaq 208(%rsp), %rbx
movq %rbx, %rcx
movl $0, %edx
jmp .L17
.L12:
cmpl $1, %eax
jne .L14
movb $98, (%rcx)
.L15:
cmpl $4, %eax
jne .L16
movb $101, (%rcx)
jmp .L16
.L14:
cmpl $2, %eax
jne .L13
movb $99, (%rcx)
.L16:
addl $1, %edx
addq $1, %rcx
cmpl $32, %edx
je .L28
.L17:
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
leal (%rax,%rax,4), %esi
movl %edx, %eax
subl %esi, %eax
jne .L12
movb $97, (%rcx)
.L13:
cmpl $3, %eax
jne .L15
movb $100, (%rcx)
jmp .L16
.L28:
leaq 80(%rsp), %rax
leaq 208(%rsp), %rdx
.L18:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
leaq 48(%rsp), %rax
leaq 72(%rsp), %rcx
.L19:
movslq (%rax), %rdx
movl $1, 80(%rsp,%rdx,4)
addq $4, %rax
cmpq %rcx, %rax
jne .L19
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 208(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L20:
leaq 208(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 32(%rbx), %r12
leaq .LC0(%rip), %rbp
.L21:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L21
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z25__device_stub__Z4CapsPcPiPcPi
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4CapsPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4CapsPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <device_launch_parameters.h>
#define N 32 //allocate space for vars; this will end up being the number of blocks to iterate over (we want this to be multiples of 32)
__global__ void Caps(char *c, int *b)
{
int tid = blockIdx.x;
if (tid < N)
{
if (b[tid] == 1)
{
int ascii = (int)c[tid];
ascii -= 32;
c[tid] = (char)ascii;
}
}
}
int main()
{
int a[] = {1, 4, 6, 8, 11, 30};
char String[N];
int *b;
char *c;
//geneate 32 character string
for(int i=0;i<N;i++){
if (i % 5 == 0) { String[i] = 'a'; }
if (i % 5 == 1) { String[i] = 'b'; }
if (i % 5 == 2) { String[i] = 'c'; }
if (i % 5 == 3) { String[i] = 'd'; }
if (i % 5 == 4) { String[i] = 'e'; }
}
int temp[sizeof(String)/sizeof(char)];
for (int i = 0; i < (sizeof(String)/sizeof(char)); i++)
{
temp[i]=0;
}
for (int i = 0; i < (sizeof(a)/sizeof(int)); i++)
{
int val=a[i];
temp[val]=1;
}
cudaMalloc((void**)&c, N * sizeof(char));
cudaMalloc((void**)&b, N * sizeof(int));
cudaMemcpy(b, &temp, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(c, &String, N * sizeof(char), cudaMemcpyHostToDevice);
Caps<<<N, 1>>>(c, b);
cudaMemcpy(&String, c, N * sizeof(char), cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
printf("%c", String[i]);
}
printf("\n");
cudaFree(b);
cudaFree(c);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#define N 32 //allocate space for vars; this will end up being the number of blocks to iterate over (we want this to be multiples of 32)
__global__ void Caps(char *c, int *b)
{
int tid = blockIdx.x;
if (tid < N)
{
if (b[tid] == 1)
{
int ascii = (int)c[tid];
ascii -= 32;
c[tid] = (char)ascii;
}
}
}
int main()
{
int a[] = {1, 4, 6, 8, 11, 30};
char String[N];
int *b;
char *c;
//geneate 32 character string
for(int i=0;i<N;i++){
if (i % 5 == 0) { String[i] = 'a'; }
if (i % 5 == 1) { String[i] = 'b'; }
if (i % 5 == 2) { String[i] = 'c'; }
if (i % 5 == 3) { String[i] = 'd'; }
if (i % 5 == 4) { String[i] = 'e'; }
}
int temp[sizeof(String)/sizeof(char)];
for (int i = 0; i < (sizeof(String)/sizeof(char)); i++)
{
temp[i]=0;
}
for (int i = 0; i < (sizeof(a)/sizeof(int)); i++)
{
int val=a[i];
temp[val]=1;
}
hipMalloc((void**)&c, N * sizeof(char));
hipMalloc((void**)&b, N * sizeof(int));
hipMemcpy(b, &temp, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c, &String, N * sizeof(char), hipMemcpyHostToDevice);
Caps<<<N, 1>>>(c, b);
hipMemcpy(&String, c, N * sizeof(char), hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
printf("%c", String[i]);
}
printf("\n");
hipFree(b);
hipFree(c);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#define N 32 //allocate space for vars; this will end up being the number of blocks to iterate over (we want this to be multiples of 32)
__global__ void Caps(char *c, int *b)
{
int tid = blockIdx.x;
if (tid < N)
{
if (b[tid] == 1)
{
int ascii = (int)c[tid];
ascii -= 32;
c[tid] = (char)ascii;
}
}
}
int main()
{
int a[] = {1, 4, 6, 8, 11, 30};
char String[N];
int *b;
char *c;
//geneate 32 character string
for(int i=0;i<N;i++){
if (i % 5 == 0) { String[i] = 'a'; }
if (i % 5 == 1) { String[i] = 'b'; }
if (i % 5 == 2) { String[i] = 'c'; }
if (i % 5 == 3) { String[i] = 'd'; }
if (i % 5 == 4) { String[i] = 'e'; }
}
int temp[sizeof(String)/sizeof(char)];
for (int i = 0; i < (sizeof(String)/sizeof(char)); i++)
{
temp[i]=0;
}
for (int i = 0; i < (sizeof(a)/sizeof(int)); i++)
{
int val=a[i];
temp[val]=1;
}
hipMalloc((void**)&c, N * sizeof(char));
hipMalloc((void**)&b, N * sizeof(int));
hipMemcpy(b, &temp, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c, &String, N * sizeof(char), hipMemcpyHostToDevice);
Caps<<<N, 1>>>(c, b);
hipMemcpy(&String, c, N * sizeof(char), hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
printf("%c", String[i]);
}
printf("\n");
hipFree(b);
hipFree(c);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4CapsPcPi
.globl _Z4CapsPcPi
.p2align 8
.type _Z4CapsPcPi,@function
_Z4CapsPcPi:
s_cmp_gt_i32 s15, 31
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 0xe0, v1
global_store_b8 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4CapsPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4CapsPcPi, .Lfunc_end0-_Z4CapsPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4CapsPcPi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4CapsPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#define N 32 //allocate space for vars; this will end up being the number of blocks to iterate over (we want this to be multiples of 32)
__global__ void Caps(char *c, int *b)
{
int tid = blockIdx.x;
if (tid < N)
{
if (b[tid] == 1)
{
int ascii = (int)c[tid];
ascii -= 32;
c[tid] = (char)ascii;
}
}
}
int main()
{
int a[] = {1, 4, 6, 8, 11, 30};
char String[N];
int *b;
char *c;
//geneate 32 character string
for(int i=0;i<N;i++){
if (i % 5 == 0) { String[i] = 'a'; }
if (i % 5 == 1) { String[i] = 'b'; }
if (i % 5 == 2) { String[i] = 'c'; }
if (i % 5 == 3) { String[i] = 'd'; }
if (i % 5 == 4) { String[i] = 'e'; }
}
int temp[sizeof(String)/sizeof(char)];
for (int i = 0; i < (sizeof(String)/sizeof(char)); i++)
{
temp[i]=0;
}
for (int i = 0; i < (sizeof(a)/sizeof(int)); i++)
{
int val=a[i];
temp[val]=1;
}
hipMalloc((void**)&c, N * sizeof(char));
hipMalloc((void**)&b, N * sizeof(int));
hipMemcpy(b, &temp, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(c, &String, N * sizeof(char), hipMemcpyHostToDevice);
Caps<<<N, 1>>>(c, b);
hipMemcpy(&String, c, N * sizeof(char), hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++)
{
printf("%c", String[i]);
}
printf("\n");
hipFree(b);
hipFree(c);
return 0;
}
|
.text
.file "Capitalization.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__CapsPcPi # -- Begin function _Z19__device_stub__CapsPcPi
.p2align 4, 0x90
.type _Z19__device_stub__CapsPcPi,@function
_Z19__device_stub__CapsPcPi: # @_Z19__device_stub__CapsPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4CapsPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__CapsPcPi, .Lfunc_end0-_Z19__device_stub__CapsPcPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 4 # 0x4
.long 6 # 0x6
.long 8 # 0x8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,4,6,8]
movaps %xmm0, 128(%rsp)
movabsq $128849018891, %rax # imm = 0x1E0000000B
movq %rax, 144(%rsp)
movb $97, %al
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_1: # %switch.lookup
# =>This Inner Loop Header: Depth=1
movl %ecx, %edi
imulq %rdx, %rdi
shrq $34, %rdi
leal (%rdi,%rdi,4), %edi
movl %eax, %r8d
subb %dil, %r8b
movb %r8b, 96(%rsp,%rsi)
incq %rsi
incb %al
incl %ecx
cmpq $32, %rsi
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movslq 128(%rsp,%rax,4), %rcx
movl $1, 160(%rsp,%rcx,4)
incq %rax
cmpq $6, %rax
jne .LBB1_3
# %bb.4:
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 31(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4CapsPcPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movsbl 96(%rsp,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq $32, %rbx
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4CapsPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4CapsPcPi,@object # @_Z4CapsPcPi
.section .rodata,"a",@progbits
.globl _Z4CapsPcPi
.p2align 3, 0x0
_Z4CapsPcPi:
.quad _Z19__device_stub__CapsPcPi
.size _Z4CapsPcPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4CapsPcPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__CapsPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4CapsPcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4CapsPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R0, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00c0*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*00d0*/ IADD3 R5, R0, -0x20, RZ ; /* 0xffffffe000057810 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4CapsPcPi
.globl _Z4CapsPcPi
.p2align 8
.type _Z4CapsPcPi,@function
_Z4CapsPcPi:
s_cmp_gt_i32 s15, 31
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, 0xe0, v1
global_store_b8 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4CapsPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4CapsPcPi, .Lfunc_end0-_Z4CapsPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4CapsPcPi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4CapsPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00166af3_00000000-6_Capitalization.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4CapsPcPiPcPi
.type _Z25__device_stub__Z4CapsPcPiPcPi, @function
_Z25__device_stub__Z4CapsPcPiPcPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4CapsPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z4CapsPcPiPcPi, .-_Z25__device_stub__Z4CapsPcPiPcPi
.globl _Z4CapsPcPi
.type _Z4CapsPcPi, @function
_Z4CapsPcPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4CapsPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4CapsPcPi, .-_Z4CapsPcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%c"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movl $1, 48(%rsp)
movl $4, 52(%rsp)
movl $6, 56(%rsp)
movl $8, 60(%rsp)
movl $11, 64(%rsp)
movl $30, 68(%rsp)
leaq 208(%rsp), %rbx
movq %rbx, %rcx
movl $0, %edx
jmp .L17
.L12:
cmpl $1, %eax
jne .L14
movb $98, (%rcx)
.L15:
cmpl $4, %eax
jne .L16
movb $101, (%rcx)
jmp .L16
.L14:
cmpl $2, %eax
jne .L13
movb $99, (%rcx)
.L16:
addl $1, %edx
addq $1, %rcx
cmpl $32, %edx
je .L28
.L17:
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
leal (%rax,%rax,4), %esi
movl %edx, %eax
subl %esi, %eax
jne .L12
movb $97, (%rcx)
.L13:
cmpl $3, %eax
jne .L15
movb $100, (%rcx)
jmp .L16
.L28:
leaq 80(%rsp), %rax
leaq 208(%rsp), %rdx
.L18:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
leaq 48(%rsp), %rax
leaq 72(%rsp), %rcx
.L19:
movslq (%rax), %rdx
movl $1, 80(%rsp,%rdx,4)
addq $4, %rax
cmpq %rcx, %rax
jne .L19
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 208(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L20:
leaq 208(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq 32(%rbx), %r12
leaq .LC0(%rip), %rbp
.L21:
movsbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L21
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z25__device_stub__Z4CapsPcPiPcPi
jmp .L20
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4CapsPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4CapsPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Capitalization.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__CapsPcPi # -- Begin function _Z19__device_stub__CapsPcPi
.p2align 4, 0x90
.type _Z19__device_stub__CapsPcPi,@function
_Z19__device_stub__CapsPcPi: # @_Z19__device_stub__CapsPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4CapsPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__CapsPcPi, .Lfunc_end0-_Z19__device_stub__CapsPcPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1 # 0x1
.long 4 # 0x4
.long 6 # 0x6
.long 8 # 0x8
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1,4,6,8]
movaps %xmm0, 128(%rsp)
movabsq $128849018891, %rax # imm = 0x1E0000000B
movq %rax, 144(%rsp)
movb $97, %al
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_1: # %switch.lookup
# =>This Inner Loop Header: Depth=1
movl %ecx, %edi
imulq %rdx, %rdi
shrq $34, %rdi
leal (%rdi,%rdi,4), %edi
movl %eax, %r8d
subb %dil, %r8b
movb %r8b, 96(%rsp,%rsi)
incq %rsi
incb %al
incl %ecx
cmpq $32, %rsi
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movslq 128(%rsp,%rax,4), %rcx
movl $1, 160(%rsp,%rcx,4)
incq %rax
cmpq $6, %rax
jne .LBB1_3
# %bb.4:
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 160(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 96(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 31(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4CapsPcPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movsbl 96(%rsp,%rbx), %edi
callq putchar@PLT
incq %rbx
cmpq $32, %rbx
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4CapsPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4CapsPcPi,@object # @_Z4CapsPcPi
.section .rodata,"a",@progbits
.globl _Z4CapsPcPi
.p2align 3, 0x0
_Z4CapsPcPi:
.quad _Z19__device_stub__CapsPcPi
.size _Z4CapsPcPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4CapsPcPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__CapsPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4CapsPcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#define arraySize 6
#define threadPerBlock 6
/**枚举排序或者秩排序算法
* 对于数组中的每一个元素，通过统计小于其值的数组中其他元素的数量，
* 该统计数量就是该元素在最终结果数组中的位置索引。
*/
// Define kernel function to sort array with rank.
__global__ void rank_sort_kernel(int *device_a, int *device_b)
{
unsigned int count = 0;
unsigned int tid = threadIdx.x;
unsigned int ttid = blockIdx.x * threadPerBlock + tid;
int val = device_a[ttid];
// using shared memory.
__shared__ int cache[threadPerBlock];
for (unsigned int i = tid; i < arraySize; i += threadPerBlock)
{
cache[tid] = device_a[i];
__syncthreads();
for (unsigned j = 0; j < threadPerBlock; ++j)
{
if (val > cache[j])
{
count++;
}
__syncthreads();
}
}
device_b[count] = val;
}
int main(int argc, char **argv)
{
int host_a[arraySize] = {5, 9, 2, 3, 8, 4};
int host_b[arraySize];
int *device_a, *device_b;
cudaMalloc((void**)&device_a, arraySize * sizeof(int));
cudaMalloc((void**)&device_b, arraySize * sizeof(int));
cudaMemcpy(device_a, host_a, arraySize * sizeof(int), cudaMemcpyHostToDevice);
rank_sort_kernel <<< arraySize / threadPerBlock, threadPerBlock >>> (device_a, device_b);
cudaDeviceSynchronize();
cudaMemcpy(host_b, device_b, arraySize * sizeof(int), cudaMemcpyDeviceToHost);
printf("The before sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_a[k]);
}
printf("\n\nThe Enumeration sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_b[k]);
}
cudaFree(device_a);
cudaFree(device_b);
return 0;
}
|
code for sm_80
Function : _Z16rank_sort_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R2, 0x6, R9 ; /* 0x0000000602027824 */
/* 0x001fc800078e0209 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e000b */
/*0070*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000162000c1e1900 */
/*0080*/ ISETP.GT.U32.AND P0, PT, R9, 0x5, PT ; /* 0x000000050900780c */
/* 0x000fe20003f04070 */
/*0090*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fd8000001ff00 */
/*00a0*/ @P0 BRA 0x340 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R9, -0x6, RZ ; /* 0xfffffffa09007810 */
/* 0x001fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3 R0, R0, 0x6, RZ ; /* 0x0000000600007810 */
/* 0x000fca0007ffe0ff */
/*00e0*/ IMAD.WIDE.U32 R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e000b */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0100*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0110*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x001fe40007ffe0ff */
/*0120*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x000e280000000800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ LDS R8, [0x4] ; /* 0x00000400ff087984 */
/* 0x000e680000000800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GT.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f24270 */
/*0190*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*01a0*/ LDS R10, [0x8] ; /* 0x00000800ff0a7984 */
/* 0x000e280000000800 */
/*01b0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GT.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x002fda0003f04270 */
/*01e0*/ @!P0 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0203 */
/*01f0*/ LDS R12, [0xc] ; /* 0x00000c00ff0c7984 */
/* 0x000e680000000800 */
/*0200*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fe20007ffe0ff */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P1, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x001fda0003f24270 */
/*0230*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*0240*/ LDS R14, [0x10] ; /* 0x00001000ff0e7984 */
/* 0x000e280000000800 */
/*0250*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x002fda0003f04270 */
/*0280*/ @!P0 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0203 */
/*0290*/ LDS R2, [0x14] ; /* 0x00001400ff027984 */
/* 0x000e680000000800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GT.AND P1, PT, R7.reuse, R14, PT ; /* 0x0000000e0700720c */
/* 0x041fe40003f24270 */
/*02c0*/ ISETP.GT.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x002fe40003f04270 */
/*02d0*/ IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x000fd20007ffe0ff */
/*02e0*/ @!P1 IMAD.MOV R2, RZ, RZ, R4 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0204 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R0, -0x7, PT ; /* 0xfffffff90000780c */
/* 0x000fc80003f24070 */
/*0300*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*0310*/ @!P0 IMAD.MOV R4, RZ, RZ, R2 ; /* 0x000000ffff048224 */
/* 0x000fd000078e0202 */
/*0320*/ @P1 BRA 0xd0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0340*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x001fc800078010ff */
/*0350*/ LEA.HI.X R3, R4, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f1405 */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe2000c101904 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#define arraySize 6
#define threadPerBlock 6
/**枚举排序或者秩排序算法
* 对于数组中的每一个元素，通过统计小于其值的数组中其他元素的数量，
* 该统计数量就是该元素在最终结果数组中的位置索引。
*/
// Define kernel function to sort array with rank.
__global__ void rank_sort_kernel(int *device_a, int *device_b)
{
unsigned int count = 0;
unsigned int tid = threadIdx.x;
unsigned int ttid = blockIdx.x * threadPerBlock + tid;
int val = device_a[ttid];
// using shared memory.
__shared__ int cache[threadPerBlock];
for (unsigned int i = tid; i < arraySize; i += threadPerBlock)
{
cache[tid] = device_a[i];
__syncthreads();
for (unsigned j = 0; j < threadPerBlock; ++j)
{
if (val > cache[j])
{
count++;
}
__syncthreads();
}
}
device_b[count] = val;
}
int main(int argc, char **argv)
{
int host_a[arraySize] = {5, 9, 2, 3, 8, 4};
int host_b[arraySize];
int *device_a, *device_b;
cudaMalloc((void**)&device_a, arraySize * sizeof(int));
cudaMalloc((void**)&device_b, arraySize * sizeof(int));
cudaMemcpy(device_a, host_a, arraySize * sizeof(int), cudaMemcpyHostToDevice);
rank_sort_kernel <<< arraySize / threadPerBlock, threadPerBlock >>> (device_a, device_b);
cudaDeviceSynchronize();
cudaMemcpy(host_b, device_b, arraySize * sizeof(int), cudaMemcpyDeviceToHost);
printf("The before sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_a[k]);
}
printf("\n\nThe Enumeration sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_b[k]);
}
cudaFree(device_a);
cudaFree(device_b);
return 0;
}
|
.file "tmpxft_000d793b_00000000-6_4_04_rank_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
.type _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_, @function
_Z38__device_stub__Z16rank_sort_kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16rank_sort_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_, .-_Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
.globl _Z16rank_sort_kernelPiS_
.type _Z16rank_sort_kernelPiS_, @function
_Z16rank_sort_kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16rank_sort_kernelPiS_, .-_Z16rank_sort_kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The before sorted Array is: \n"
.LC1:
.string "%d\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n\nThe Enumeration sorted Array is: \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $5, 48(%rsp)
movl $9, 52(%rsp)
movl $2, 56(%rsp)
movl $3, 60(%rsp)
movl $8, 64(%rsp)
movl $4, 68(%rsp)
leaq 8(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $24, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 72(%rsp), %r12
leaq .LC1(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rbx
leaq 104(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z16rank_sort_kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rank_sort_kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#define arraySize 6
#define threadPerBlock 6
/**枚举排序或者秩排序算法
* 对于数组中的每一个元素，通过统计小于其值的数组中其他元素的数量，
* 该统计数量就是该元素在最终结果数组中的位置索引。
*/
// Define kernel function to sort array with rank.
__global__ void rank_sort_kernel(int *device_a, int *device_b)
{
unsigned int count = 0;
unsigned int tid = threadIdx.x;
unsigned int ttid = blockIdx.x * threadPerBlock + tid;
int val = device_a[ttid];
// using shared memory.
__shared__ int cache[threadPerBlock];
for (unsigned int i = tid; i < arraySize; i += threadPerBlock)
{
cache[tid] = device_a[i];
__syncthreads();
for (unsigned j = 0; j < threadPerBlock; ++j)
{
if (val > cache[j])
{
count++;
}
__syncthreads();
}
}
device_b[count] = val;
}
int main(int argc, char **argv)
{
int host_a[arraySize] = {5, 9, 2, 3, 8, 4};
int host_b[arraySize];
int *device_a, *device_b;
cudaMalloc((void**)&device_a, arraySize * sizeof(int));
cudaMalloc((void**)&device_b, arraySize * sizeof(int));
cudaMemcpy(device_a, host_a, arraySize * sizeof(int), cudaMemcpyHostToDevice);
rank_sort_kernel <<< arraySize / threadPerBlock, threadPerBlock >>> (device_a, device_b);
cudaDeviceSynchronize();
cudaMemcpy(host_b, device_b, arraySize * sizeof(int), cudaMemcpyDeviceToHost);
printf("The before sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_a[k]);
}
printf("\n\nThe Enumeration sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_b[k]);
}
cudaFree(device_a);
cudaFree(device_b);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define arraySize 6
#define threadPerBlock 6
/**枚举排序或者秩排序算法
* 对于数组中的每一个元素，通过统计小于其值的数组中其他元素的数量，
* 该统计数量就是该元素在最终结果数组中的位置索引。
*/
// Define kernel function to sort array with rank.
__global__ void rank_sort_kernel(int *device_a, int *device_b)
{
unsigned int count = 0;
unsigned int tid = threadIdx.x;
unsigned int ttid = blockIdx.x * threadPerBlock + tid;
int val = device_a[ttid];
// using shared memory.
__shared__ int cache[threadPerBlock];
for (unsigned int i = tid; i < arraySize; i += threadPerBlock)
{
cache[tid] = device_a[i];
__syncthreads();
for (unsigned j = 0; j < threadPerBlock; ++j)
{
if (val > cache[j])
{
count++;
}
__syncthreads();
}
}
device_b[count] = val;
}
int main(int argc, char **argv)
{
int host_a[arraySize] = {5, 9, 2, 3, 8, 4};
int host_b[arraySize];
int *device_a, *device_b;
hipMalloc((void**)&device_a, arraySize * sizeof(int));
hipMalloc((void**)&device_b, arraySize * sizeof(int));
hipMemcpy(device_a, host_a, arraySize * sizeof(int), hipMemcpyHostToDevice);
rank_sort_kernel <<< arraySize / threadPerBlock, threadPerBlock >>> (device_a, device_b);
hipDeviceSynchronize();
hipMemcpy(host_b, device_b, arraySize * sizeof(int), hipMemcpyDeviceToHost);
printf("The before sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_a[k]);
}
printf("\n\nThe Enumeration sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_b[k]);
}
hipFree(device_a);
hipFree(device_b);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define arraySize 6
#define threadPerBlock 6
/**枚举排序或者秩排序算法
* 对于数组中的每一个元素，通过统计小于其值的数组中其他元素的数量，
* 该统计数量就是该元素在最终结果数组中的位置索引。
*/
// Define kernel function to sort array with rank.
__global__ void rank_sort_kernel(int *device_a, int *device_b)
{
unsigned int count = 0;
unsigned int tid = threadIdx.x;
unsigned int ttid = blockIdx.x * threadPerBlock + tid;
int val = device_a[ttid];
// using shared memory.
__shared__ int cache[threadPerBlock];
for (unsigned int i = tid; i < arraySize; i += threadPerBlock)
{
cache[tid] = device_a[i];
__syncthreads();
for (unsigned j = 0; j < threadPerBlock; ++j)
{
if (val > cache[j])
{
count++;
}
__syncthreads();
}
}
device_b[count] = val;
}
int main(int argc, char **argv)
{
int host_a[arraySize] = {5, 9, 2, 3, 8, 4};
int host_b[arraySize];
int *device_a, *device_b;
hipMalloc((void**)&device_a, arraySize * sizeof(int));
hipMalloc((void**)&device_b, arraySize * sizeof(int));
hipMemcpy(device_a, host_a, arraySize * sizeof(int), hipMemcpyHostToDevice);
rank_sort_kernel <<< arraySize / threadPerBlock, threadPerBlock >>> (device_a, device_b);
hipDeviceSynchronize();
hipMemcpy(host_b, device_b, arraySize * sizeof(int), hipMemcpyDeviceToHost);
printf("The before sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_a[k]);
}
printf("\n\nThe Enumeration sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_b[k]);
}
hipFree(device_a);
hipFree(device_b);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16rank_sort_kernelPiS_
.globl _Z16rank_sort_kernelPiS_
.p2align 8
.type _Z16rank_sort_kernelPiS_,@function
_Z16rank_sort_kernelPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, 6, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_cmpx_gt_u32_e32 6, v0
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
global_load_b32 v2, v0, s[2:3]
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_mov_b32_e32 v0, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 24
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, v3, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc0 .LBB0_2
v_mov_b32_e32 v2, 0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16rank_sort_kernelPiS_
.amdhsa_group_segment_fixed_size 24
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16rank_sort_kernelPiS_, .Lfunc_end0-_Z16rank_sort_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 24
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16rank_sort_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16rank_sort_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#define arraySize 6
#define threadPerBlock 6
/**枚举排序或者秩排序算法
* 对于数组中的每一个元素，通过统计小于其值的数组中其他元素的数量，
* 该统计数量就是该元素在最终结果数组中的位置索引。
*/
// Define kernel function to sort array with rank.
__global__ void rank_sort_kernel(int *device_a, int *device_b)
{
unsigned int count = 0;
unsigned int tid = threadIdx.x;
unsigned int ttid = blockIdx.x * threadPerBlock + tid;
int val = device_a[ttid];
// using shared memory.
__shared__ int cache[threadPerBlock];
for (unsigned int i = tid; i < arraySize; i += threadPerBlock)
{
cache[tid] = device_a[i];
__syncthreads();
for (unsigned j = 0; j < threadPerBlock; ++j)
{
if (val > cache[j])
{
count++;
}
__syncthreads();
}
}
device_b[count] = val;
}
int main(int argc, char **argv)
{
int host_a[arraySize] = {5, 9, 2, 3, 8, 4};
int host_b[arraySize];
int *device_a, *device_b;
hipMalloc((void**)&device_a, arraySize * sizeof(int));
hipMalloc((void**)&device_b, arraySize * sizeof(int));
hipMemcpy(device_a, host_a, arraySize * sizeof(int), hipMemcpyHostToDevice);
rank_sort_kernel <<< arraySize / threadPerBlock, threadPerBlock >>> (device_a, device_b);
hipDeviceSynchronize();
hipMemcpy(host_b, device_b, arraySize * sizeof(int), hipMemcpyDeviceToHost);
printf("The before sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_a[k]);
}
printf("\n\nThe Enumeration sorted Array is: \n");
for (unsigned int k = 0; k < arraySize; ++k)
{
printf("%d\t", host_b[k]);
}
hipFree(device_a);
hipFree(device_b);
return 0;
}
|
.text
.file "4_04_rank_sort.hip"
.globl _Z31__device_stub__rank_sort_kernelPiS_ # -- Begin function _Z31__device_stub__rank_sort_kernelPiS_
.p2align 4, 0x90
.type _Z31__device_stub__rank_sort_kernelPiS_,@function
_Z31__device_stub__rank_sort_kernelPiS_: # @_Z31__device_stub__rank_sort_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16rank_sort_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__rank_sort_kernelPiS_, .Lfunc_end0-_Z31__device_stub__rank_sort_kernelPiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 5 # 0x5
.long 9 # 0x9
.long 2 # 0x2
.long 3 # 0x3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [5,9,2,3]
movaps %xmm0, 112(%rsp)
movabsq $17179869192, %rax # imm = 0x400000008
movq %rax, 128(%rsp)
leaq 8(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 5(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16rank_sort_kernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $24, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB1_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rank_sort_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16rank_sort_kernelPiS_,@object # @_Z16rank_sort_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z16rank_sort_kernelPiS_
.p2align 3, 0x0
_Z16rank_sort_kernelPiS_:
.quad _Z31__device_stub__rank_sort_kernelPiS_
.size _Z16rank_sort_kernelPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16rank_sort_kernelPiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The before sorted Array is: "
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nThe Enumeration sorted Array is: "
.size .Lstr.1, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__rank_sort_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16rank_sort_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z16rank_sort_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R2, 0x6, R9 ; /* 0x0000000602027824 */
/* 0x001fc800078e0209 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e000b */
/*0070*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000162000c1e1900 */
/*0080*/ ISETP.GT.U32.AND P0, PT, R9, 0x5, PT ; /* 0x000000050900780c */
/* 0x000fe20003f04070 */
/*0090*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fd8000001ff00 */
/*00a0*/ @P0 BRA 0x340 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R9, -0x6, RZ ; /* 0xfffffffa09007810 */
/* 0x001fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3 R0, R0, 0x6, RZ ; /* 0x0000000600007810 */
/* 0x000fca0007ffe0ff */
/*00e0*/ IMAD.WIDE.U32 R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e000b */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a2000c1e1900 */
/*0100*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0110*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x001fe40007ffe0ff */
/*0120*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x004fe80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDS R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x000e280000000800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ LDS R8, [0x4] ; /* 0x00000400ff087984 */
/* 0x000e680000000800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GT.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f24270 */
/*0190*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*01a0*/ LDS R10, [0x8] ; /* 0x00000800ff0a7984 */
/* 0x000e280000000800 */
/*01b0*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.GT.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x002fda0003f04270 */
/*01e0*/ @!P0 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0203 */
/*01f0*/ LDS R12, [0xc] ; /* 0x00000c00ff0c7984 */
/* 0x000e680000000800 */
/*0200*/ IADD3 R3, R4, 0x1, RZ ; /* 0x0000000104037810 */
/* 0x000fe20007ffe0ff */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.GT.AND P1, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x001fda0003f24270 */
/*0230*/ @!P1 IMAD.MOV R3, RZ, RZ, R4 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0204 */
/*0240*/ LDS R14, [0x10] ; /* 0x00001000ff0e7984 */
/* 0x000e280000000800 */
/*0250*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fe20007ffe0ff */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x002fda0003f04270 */
/*0280*/ @!P0 IMAD.MOV R4, RZ, RZ, R3 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0203 */
/*0290*/ LDS R2, [0x14] ; /* 0x00001400ff027984 */
/* 0x000e680000000800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GT.AND P1, PT, R7.reuse, R14, PT ; /* 0x0000000e0700720c */
/* 0x041fe40003f24270 */
/*02c0*/ ISETP.GT.AND P0, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x002fe40003f04270 */
/*02d0*/ IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x000fd20007ffe0ff */
/*02e0*/ @!P1 IMAD.MOV R2, RZ, RZ, R4 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0204 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R0, -0x7, PT ; /* 0xfffffff90000780c */
/* 0x000fc80003f24070 */
/*0300*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*0310*/ @!P0 IMAD.MOV R4, RZ, RZ, R2 ; /* 0x000000ffff048224 */
/* 0x000fd000078e0202 */
/*0320*/ @P1 BRA 0xd0 ; /* 0xfffffda000001947 */
/* 0x000fea000383ffff */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0340*/ LEA R2, P0, R4, c[0x0][0x168], 0x2 ; /* 0x00005a0004027a11 */
/* 0x001fc800078010ff */
/*0350*/ LEA.HI.X R3, R4, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0004037a11 */
/* 0x000fca00000f1405 */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe2000c101904 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16rank_sort_kernelPiS_
.globl _Z16rank_sort_kernelPiS_
.p2align 8
.type _Z16rank_sort_kernelPiS_,@function
_Z16rank_sort_kernelPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, 6, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_cmpx_gt_u32_e32 6, v0
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
global_load_b32 v2, v0, s[2:3]
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_mov_b32_e32 v0, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 24
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, v3, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_cbranch_scc0 .LBB0_2
v_mov_b32_e32 v2, 0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16rank_sort_kernelPiS_
.amdhsa_group_segment_fixed_size 24
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16rank_sort_kernelPiS_, .Lfunc_end0-_Z16rank_sort_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 24
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16rank_sort_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16rank_sort_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d793b_00000000-6_4_04_rank_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
.type _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_, @function
_Z38__device_stub__Z16rank_sort_kernelPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16rank_sort_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_, .-_Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
.globl _Z16rank_sort_kernelPiS_
.type _Z16rank_sort_kernelPiS_, @function
_Z16rank_sort_kernelPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16rank_sort_kernelPiS_, .-_Z16rank_sort_kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "The before sorted Array is: \n"
.LC1:
.string "%d\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n\nThe Enumeration sorted Array is: \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $5, 48(%rsp)
movl $9, 52(%rsp)
movl $2, 56(%rsp)
movl $3, 60(%rsp)
movl $8, 64(%rsp)
movl $4, 68(%rsp)
leaq 8(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $24, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 72(%rsp), %r12
leaq .LC1(%rip), %rbp
.L13:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rbx
leaq 104(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z16rank_sort_kernelPiS_PiS_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z16rank_sort_kernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16rank_sort_kernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "4_04_rank_sort.hip"
.globl _Z31__device_stub__rank_sort_kernelPiS_ # -- Begin function _Z31__device_stub__rank_sort_kernelPiS_
.p2align 4, 0x90
.type _Z31__device_stub__rank_sort_kernelPiS_,@function
_Z31__device_stub__rank_sort_kernelPiS_: # @_Z31__device_stub__rank_sort_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16rank_sort_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__rank_sort_kernelPiS_, .Lfunc_end0-_Z31__device_stub__rank_sort_kernelPiS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 5 # 0x5
.long 9 # 0x9
.long 2 # 0x2
.long 3 # 0x3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [5,9,2,3]
movaps %xmm0, 112(%rsp)
movabsq $17179869192, %rax # imm = 0x400000008
movq %rax, 128(%rsp)
leaq 8(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 5(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16rank_sort_kernelPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $24, %edx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB1_3
# %bb.4:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $6, %rbx
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16rank_sort_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16rank_sort_kernelPiS_,@object # @_Z16rank_sort_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z16rank_sort_kernelPiS_
.p2align 3, 0x0
_Z16rank_sort_kernelPiS_:
.quad _Z31__device_stub__rank_sort_kernelPiS_
.size _Z16rank_sort_kernelPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\t"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16rank_sort_kernelPiS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The before sorted Array is: "
.size .Lstr, 29
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nThe Enumeration sorted Array is: "
.size .Lstr.1, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__rank_sort_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16rank_sort_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <math.h>
// function add
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void add(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]+m2[index];
}
// function minus
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void minus(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]-m2[index];
}
// function mul
// 1 block, 1 dimensional block size
__global__ void mul(float* m1, float factor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]*factor;
}
// function div
// 1 block, 1 dimensional block size
__global__ void div(float* m1, float divsor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]/divsor;
}
// function pow
// 1 block, 1 dimensional block size
__global__ void pow(float* m1, float power, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=pow(m1[index],power);
}
// function sqrt
// 1 block, 1 dimensional block size
__global__ void sqrt(float* m1, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=sqrt(m1[index]);
}
// function dot
// m1 of shape H*L, m2 of shape L*M and m3 of shape H*M
// 1 block, 2 dimensional block size
__global__ void dot(float* m1, float* m2, float* m3,
int size_h, int size_l, int size_m){
int h=size_h, l=size_l, m=size_m;
for(int h_index=threadIdx.x;h_index<h;h_index+=blockDim.x){
for(int m_index=threadIdx.y;m_index<m;m_index+=blockDim.y){
float value=0.0;
for(int l_index=0;l_index<l;l_index++){
float x=m1[h_index*l+l_index];
float y=m2[l_index*m+m_index];
value+=x*y;
}
m3[h_index*m+m_index]=value;
}
}
}
|
.file "tmpxft_00127e74_00000000-6_matrixOps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.globl _Z29__device_stub__Z5minusPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5minusPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5minusPfS_S_iPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5minusPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z29__device_stub__Z5minusPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5minusPfS_S_iPfS_S_i
.globl _Z5minusPfS_S_i
.type _Z5minusPfS_S_i, @function
_Z5minusPfS_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5minusPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z5minusPfS_S_i, .-_Z5minusPfS_S_i
.globl _Z26__device_stub__Z3mulPffS_iPffS_i
.type _Z26__device_stub__Z3mulPffS_iPffS_i, @function
_Z26__device_stub__Z3mulPffS_iPffS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z26__device_stub__Z3mulPffS_iPffS_i, .-_Z26__device_stub__Z3mulPffS_iPffS_i
.globl _Z3mulPffS_i
.type _Z3mulPffS_i, @function
_Z3mulPffS_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPffS_iPffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z3mulPffS_i, .-_Z3mulPffS_i
.globl _Z26__device_stub__Z3divPffS_iPffS_i
.type _Z26__device_stub__Z3divPffS_iPffS_i, @function
_Z26__device_stub__Z3divPffS_iPffS_i:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3divPffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z26__device_stub__Z3divPffS_iPffS_i, .-_Z26__device_stub__Z3divPffS_iPffS_i
.globl _Z3divPffS_i
.type _Z3divPffS_i, @function
_Z3divPffS_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3divPffS_iPffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z3divPffS_i, .-_Z3divPffS_i
.globl _Z26__device_stub__Z3powPffS_iPffS_i
.type _Z26__device_stub__Z3powPffS_iPffS_i, @function
_Z26__device_stub__Z3powPffS_iPffS_i:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3powPffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z26__device_stub__Z3powPffS_iPffS_i, .-_Z26__device_stub__Z3powPffS_iPffS_i
.globl _Z3powPffS_i
.type _Z3powPffS_i, @function
_Z3powPffS_i:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3powPffS_iPffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z3powPffS_i, .-_Z3powPffS_i
.globl _Z26__device_stub__Z4sqrtPfS_iPfS_i
.type _Z26__device_stub__Z4sqrtPfS_iPfS_i, @function
_Z26__device_stub__Z4sqrtPfS_iPfS_i:
.LFB2061:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sqrtPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z26__device_stub__Z4sqrtPfS_iPfS_i, .-_Z26__device_stub__Z4sqrtPfS_iPfS_i
.globl _Z4sqrtPfS_i
.type _Z4sqrtPfS_i, @function
_Z4sqrtPfS_i:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4sqrtPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4sqrtPfS_i, .-_Z4sqrtPfS_i
.globl _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii
.type _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii, @function
_Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii:
.LFB2063:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3dotPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii, .-_Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii
.globl _Z3dotPfS_S_iii
.type _Z3dotPfS_S_iii, @function
_Z3dotPfS_S_iii:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z3dotPfS_S_iii, .-_Z3dotPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3dotPfS_S_iii"
.LC1:
.string "_Z4sqrtPfS_i"
.LC2:
.string "_Z3powPffS_i"
.LC3:
.string "_Z3divPffS_i"
.LC4:
.string "_Z3mulPffS_i"
.LC5:
.string "_Z5minusPfS_S_i"
.LC6:
.string "_Z3addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sqrtPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3powPffS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3divPffS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPffS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5minusPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <math.h>
// function add
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void add(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]+m2[index];
}
// function minus
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void minus(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]-m2[index];
}
// function mul
// 1 block, 1 dimensional block size
__global__ void mul(float* m1, float factor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]*factor;
}
// function div
// 1 block, 1 dimensional block size
__global__ void div(float* m1, float divsor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]/divsor;
}
// function pow
// 1 block, 1 dimensional block size
__global__ void pow(float* m1, float power, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=pow(m1[index],power);
}
// function sqrt
// 1 block, 1 dimensional block size
__global__ void sqrt(float* m1, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=sqrt(m1[index]);
}
// function dot
// m1 of shape H*L, m2 of shape L*M and m3 of shape H*M
// 1 block, 2 dimensional block size
__global__ void dot(float* m1, float* m2, float* m3,
int size_h, int size_l, int size_m){
int h=size_h, l=size_l, m=size_m;
for(int h_index=threadIdx.x;h_index<h;h_index+=blockDim.x){
for(int m_index=threadIdx.y;m_index<m;m_index+=blockDim.y){
float value=0.0;
for(int l_index=0;l_index<l;l_index++){
float x=m1[h_index*l+l_index];
float y=m2[l_index*m+m_index];
value+=x*y;
}
m3[h_index*m+m_index]=value;
}
}
}
|
#include <hip/hip_runtime.h>
#include <math.h>
// function add
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void add(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]+m2[index];
}
// function minus
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void minus(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]-m2[index];
}
// function mul
// 1 block, 1 dimensional block size
__global__ void mul(float* m1, float factor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]*factor;
}
// function div
// 1 block, 1 dimensional block size
__global__ void div(float* m1, float divsor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]/divsor;
}
// function pow
// 1 block, 1 dimensional block size
__global__ void pow(float* m1, float power, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=pow(m1[index],power);
}
// function sqrt
// 1 block, 1 dimensional block size
__global__ void sqrt(float* m1, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=sqrt(m1[index]);
}
// function dot
// m1 of shape H*L, m2 of shape L*M and m3 of shape H*M
// 1 block, 2 dimensional block size
__global__ void dot(float* m1, float* m2, float* m3,
int size_h, int size_l, int size_m){
int h=size_h, l=size_l, m=size_m;
for(int h_index=threadIdx.x;h_index<h;h_index+=blockDim.x){
for(int m_index=threadIdx.y;m_index<m;m_index+=blockDim.y){
float value=0.0;
for(int l_index=0;l_index<l;l_index++){
float x=m1[h_index*l+l_index];
float y=m2[l_index*m+m_index];
value+=x*y;
}
m3[h_index*m+m_index]=value;
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <math.h>
// function add
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void add(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]+m2[index];
}
// function minus
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void minus(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]-m2[index];
}
// function mul
// 1 block, 1 dimensional block size
__global__ void mul(float* m1, float factor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]*factor;
}
// function div
// 1 block, 1 dimensional block size
__global__ void div(float* m1, float divsor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]/divsor;
}
// function pow
// 1 block, 1 dimensional block size
__global__ void pow(float* m1, float power, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=pow(m1[index],power);
}
// function sqrt
// 1 block, 1 dimensional block size
__global__ void sqrt(float* m1, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=sqrt(m1[index]);
}
// function dot
// m1 of shape H*L, m2 of shape L*M and m3 of shape H*M
// 1 block, 2 dimensional block size
__global__ void dot(float* m1, float* m2, float* m3,
int size_h, int size_l, int size_m){
int h=size_h, l=size_l, m=size_m;
for(int h_index=threadIdx.x;h_index<h;h_index+=blockDim.x){
for(int m_index=threadIdx.y;m_index<m;m_index+=blockDim.y){
float value=0.0;
for(int l_index=0;l_index<l;l_index++){
float x=m1[h_index*l+l_index];
float y=m2[l_index*m+m_index];
value+=x*y;
}
m3[h_index*m+m_index]=value;
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_i
.globl _Z3addPfS_S_i
.p2align 8
.type _Z3addPfS_S_i,@function
_Z3addPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_u32 v1, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_i, .Lfunc_end0-_Z3addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5minusPfS_S_i
.globl _Z5minusPfS_S_i
.p2align 8
.type _Z5minusPfS_S_i,@function
_Z5minusPfS_S_i:
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB1_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_u32 v1, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5minusPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5minusPfS_S_i, .Lfunc_end1-_Z5minusPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3mulPffS_i
.globl _Z3mulPffS_i
.p2align 8
.type _Z3mulPffS_i,@function
_Z3mulPffS_i:
s_load_b32 s6, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB2_3
s_clause 0x3
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s8, 0xffff
s_mov_b32 s8, 0
.p2align 6
.LBB2_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, s0, s4, v1
v_add_co_ci_u32_e64 v2, s0, s5, v2, s0
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v3, s7, v3 :: v_dual_add_nc_u32 v0, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v0
global_store_b32 v[1:2], v3, off
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPffS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3mulPffS_i, .Lfunc_end2-_Z3mulPffS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3divPffS_i
.globl _Z3divPffS_i
.p2align 8
.type _Z3divPffS_i,@function
_Z3divPffS_i:
s_load_b32 s6, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB3_3
s_clause 0x3
s_load_b32 s8, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s8, 0xffff
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB3_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, s0, s4, v1
v_add_co_ci_u32_e64 v2, s0, s5, v2, s0
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, s7, s7, v3
v_div_scale_f32 v7, vcc_lo, v3, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v5, v6
v_cmp_le_i32_e32 vcc_lo, s6, v0
v_div_fixup_f32 v3, v4, s7, v3
s_or_b32 s8, vcc_lo, s8
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3divPffS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z3divPffS_i, .Lfunc_end3-_Z3divPffS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3powPffS_i
.globl _Z3powPffS_i
.p2align 8
.type _Z3powPffS_i,@function
_Z3powPffS_i:
s_load_b32 s3, s[0:1], 0x18
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB4_3
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x10
s_mov_b32 s9, 0
s_mov_b32 s11, 0x3e76c4e1
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
.LBB4_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s10, v0
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, 1.0, v3
v_cndmask_b32_e64 v4, 1.0, s8, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v4
v_cmp_neq_f32_e64 s12, v4, |v4|
v_cndmask_b32_e32 v3, 1.0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v5, |v3|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v5, v5, v6
v_add_f32_e32 v6, 1.0, v5
v_cmp_lt_f32_e64 s13, |v3|, 1.0
v_cmp_eq_f32_e64 s2, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v6
v_add_f32_e32 v10, -1.0, v6
v_add_f32_e32 v8, -1.0, v5
s_xor_b32 s12, s12, s13
v_sub_f32_e32 v5, v5, v10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v6, v9
v_fma_f32 v6, v9, v6, -v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v9, v5
v_add_f32_e32 v5, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v8, v5 :: v_dual_sub_f32 v11, v5, v11
v_sub_f32_e32 v6, v11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v10
v_sub_f32_e32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v6, v5
v_add_f32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v7, v5
v_add_f32_e32 v6, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v6, v9
v_dual_mul_f32 v8, v6, v6 :: v_dual_sub_f32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v6, v6, -v8
v_add_f32_e32 v9, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v9
v_add_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v10, s11, v9, 0x3e91f4c4
v_sub_f32_e32 v8, v9, v8
v_dual_fmaak_f32 v10, v9, v10, 0x3ecccdef :: v_dual_sub_f32 v7, v7, v8
v_mul_f32_e32 v13, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v9, v10
v_fma_f32 v14, v9, v6, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v9, v10, -v11
v_fmac_f32_e32 v8, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v14, v9, v5
v_ldexp_f32 v5, v5, 1
v_add_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v14, v7, v6
v_ldexp_f32 v6, v6, 1
v_dual_sub_f32 v11, v10, v11 :: v_dual_add_f32 v12, 0x3f2aaaaa, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v8, v11 :: v_dual_add_f32 v11, 0xbf2aaaaa, v12
v_add_f32_e32 v8, 0x31739010, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v10, v11
v_add_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v12, v8
v_dual_add_f32 v9, v13, v14 :: v_dual_sub_f32 v10, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, v9, v7
v_sub_f32_e32 v12, v9, v13
v_add_f32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v9, v7, -v11
v_sub_f32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v10, v9, v8
v_frexp_exp_i32_f32_e32 v8, v3
v_fmac_f32_e32 v10, v12, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_add_f32_e32 v8, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v7, v7
v_add_f32_e32 v9, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v11, v8, v11 :: v_dual_sub_f32 v6, v9, v6
v_sub_f32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v12, 0x3f317218, v7
v_sub_f32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v5, v5, v10
v_fma_f32 v11, v7, 0x3f317218, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v5, v6
v_fmac_f32_e32 v11, 0xb102e308, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v9, v5 :: v_dual_add_f32 v6, v12, v11
v_sub_f32_e32 v9, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v5, v9 :: v_dual_add_f32 v8, v6, v7
v_sub_f32_e32 v10, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v7, v10 :: v_dual_sub_f32 v12, v6, v12
v_sub_f32_e32 v11, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v11, v5
v_sub_f32_e32 v13, v8, v10
v_sub_f32_e32 v6, v6, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v7, v6 :: v_dual_sub_f32 v7, v9, v11
v_sub_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v9, v6
v_sub_f32_e32 v9, v9, v7
v_dual_sub_f32 v7, v11, v9 :: v_dual_add_f32 v10, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v8, v10, v8
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v6
v_add_f32_e32 v6, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v6, v10
v_dual_mul_f32 v8, v4, v6 :: v_dual_sub_f32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v6, v4, v6, -v8
v_cmp_class_f32_e64 vcc_lo, v8, 0x204
v_fmac_f32_e32 v6, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v8, v6
v_cndmask_b32_e32 v7, v5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e64 v9, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
v_sub_f32_e32 v10, v7, v9
v_trunc_f32_e32 v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x3fb8aa3b, v10
v_fma_f32 v12, v10, 0x3fb8aa3b, -v11
v_rndne_f32_e32 v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_sub_f32 v11, v11, v13 :: v_dual_fmac_f32 v12, 0x32a5705f, v10
v_sub_f32_e32 v5, v5, v8
v_cvt_i32_f32_e32 v8, v13
v_sub_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
v_add_f32_e32 v11, v11, v12
v_add_f32_e32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v11, v8
v_mul_f32_e32 v8, 0.5, v4
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v11, v8
v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v7, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e64 s0, v11, v8
v_fma_f32 v5, v6, v5, v6
v_cmp_eq_f32_e64 s1, 0x7f800000, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
v_cndmask_b32_e64 v7, 1.0, v3, s0
v_cndmask_b32_e64 v9, 0, v3, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v5, v5, v6, s1
v_cmp_gt_f32_e64 s1, 0, v4
v_cndmask_b32_e64 v6, |v4|, 0, s12
v_cmp_class_f32_e64 s0, v3, 0x204
v_bfi_b32 v5, 0x7fffffff, v5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s1, s2
v_cndmask_b32_e64 v7, 0x7f800000, 0, s1
v_cmp_eq_f32_e64 s1, |v3|, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, 0x7fc00000, v5, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v3
v_bfi_b32 v7, 0x7fffffff, v7, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, |v3|, s1
v_cndmask_b32_e32 v5, v5, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v4, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_or_b32 vcc_lo, s2, s0
v_cmp_o_f32_e64 s0, v3, v4
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0x7fc00000, v5, s0
v_add_co_u32 v1, s0, s6, v1
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
s_or_b32 s9, vcc_lo, s9
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB4_2
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3powPffS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 14
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z3powPffS_i, .Lfunc_end4-_Z3powPffS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4sqrtPfS_i
.globl _Z4sqrtPfS_i
.p2align 8
.type _Z4sqrtPfS_i,@function
_Z4sqrtPfS_i:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB5_3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s3, 0xffff
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB5_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v7, -v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v6, v4, v3
v_cmp_ge_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_lt_f32_e64 s0, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v4, v6, s0
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 s0, v3, 0x260
v_cmp_le_i32_e32 vcc_lo, s2, v0
v_cndmask_b32_e64 v3, v4, v3, s0
v_add_co_u32 v1, s0, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
s_or_b32 s3, vcc_lo, s3
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB5_2
.LBB5_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sqrtPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z4sqrtPfS_i, .Lfunc_end5-_Z4sqrtPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3dotPfS_S_iii
.globl _Z3dotPfS_S_iii
.p2align 8
.type _Z3dotPfS_S_iii,@function
_Z3dotPfS_S_iii:
s_load_b32 s3, s[0:1], 0x18
v_and_b32_e32 v9, 0x3ff, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v9
s_cbranch_execz .LBB6_10
s_clause 0x3
s_load_b64 s[8:9], s[0:1], 0x1c
s_load_b32 s18, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_bfe_u32 v10, v0, 10, 10
s_mov_b32 s16, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v9, s8
s_cmp_gt_i32 s8, 0
v_cmp_gt_i32_e64 s2, s9, v10
s_cselect_b32 s17, -1, 0
s_add_u32 s12, s0, 40
s_mov_b32 s14, s9
s_addc_u32 s13, s1, 0
s_ashr_i32 s15, s9, 31
s_and_b32 s1, s18, 0xffff
s_lshl_b64 s[14:15], s[14:15], 2
s_mul_i32 s18, s8, s1
s_branch .LBB6_3
.LBB6_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v9, s1, v9
v_add_nc_u32_e32 v0, s18, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s3, v9
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB6_10
.LBB6_3:
s_and_saveexec_b32 s19, s2
s_cbranch_execz .LBB6_2
s_load_b32 s0, s[12:13], 0xc
v_ashrrev_i32_e32 v1, 31, v0
v_mul_lo_u32 v11, v9, s9
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_mov_b32_e32 v1, v10
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s20, s0, 16
s_set_inst_prefetch_distance 0x1
s_branch .LBB6_7
.p2align 6
.LBB6_5:
v_mov_b32_e32 v2, 0
.LBB6_6:
v_add_nc_u32_e32 v5, v1, v11
v_add_nc_u32_e32 v1, s20, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_cmp_le_i32_e32 vcc_lo, s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_or_b32 s21, vcc_lo, s21
v_add_co_u32 v5, s0, s10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s11, v6, s0
global_store_b32 v[5:6], v2, off
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB6_2
.LBB6_7:
s_and_not1_b32 vcc_lo, exec_lo, s17
s_cbranch_vccnz .LBB6_5
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v8, v4
s_mov_b32 s0, s8
v_mov_b32_e32 v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
.LBB6_9:
global_load_b32 v12, v[7:8], off
global_load_b32 v13, v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s14
v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB6_9
s_branch .LBB6_6
.LBB6_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end6:
.size _Z3dotPfS_S_iii, .Lfunc_end6-_Z3dotPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5minusPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z5minusPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPffS_i
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z3mulPffS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3divPffS_i
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z3divPffS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3powPffS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3powPffS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sqrtPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z4sqrtPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <math.h>
// function add
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void add(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]+m2[index];
}
// function minus
// m1, m2 are vectors, matrices or tensors of the same size
// 1 block, 1 dimensional block size
__global__ void minus(float* m1, float* m2, float* m3, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m3[index]=m1[index]-m2[index];
}
// function mul
// 1 block, 1 dimensional block size
__global__ void mul(float* m1, float factor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]*factor;
}
// function div
// 1 block, 1 dimensional block size
__global__ void div(float* m1, float divsor, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=m1[index]/divsor;
}
// function pow
// 1 block, 1 dimensional block size
__global__ void pow(float* m1, float power, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=pow(m1[index],power);
}
// function sqrt
// 1 block, 1 dimensional block size
__global__ void sqrt(float* m1, float* m2, int n){
for(int index=threadIdx.x;index<n;index+=blockDim.x)
m2[index]=sqrt(m1[index]);
}
// function dot
// m1 of shape H*L, m2 of shape L*M and m3 of shape H*M
// 1 block, 2 dimensional block size
__global__ void dot(float* m1, float* m2, float* m3,
int size_h, int size_l, int size_m){
int h=size_h, l=size_l, m=size_m;
for(int h_index=threadIdx.x;h_index<h;h_index+=blockDim.x){
for(int m_index=threadIdx.y;m_index<m;m_index+=blockDim.y){
float value=0.0;
for(int l_index=0;l_index<l;l_index++){
float x=m1[h_index*l+l_index];
float y=m2[l_index*m+m_index];
value+=x*y;
}
m3[h_index*m+m_index]=value;
}
}
}
|
.text
.file "matrixOps.hip"
.globl _Z18__device_stub__addPfS_S_i # -- Begin function _Z18__device_stub__addPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i: # @_Z18__device_stub__addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_i, .Lfunc_end0-_Z18__device_stub__addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__minusPfS_S_i # -- Begin function _Z20__device_stub__minusPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__minusPfS_S_i,@function
_Z20__device_stub__minusPfS_S_i: # @_Z20__device_stub__minusPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5minusPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__minusPfS_S_i, .Lfunc_end1-_Z20__device_stub__minusPfS_S_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mulPffS_i # -- Begin function _Z18__device_stub__mulPffS_i
.p2align 4, 0x90
.type _Z18__device_stub__mulPffS_i,@function
_Z18__device_stub__mulPffS_i: # @_Z18__device_stub__mulPffS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPffS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__mulPffS_i, .Lfunc_end2-_Z18__device_stub__mulPffS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__divPffS_i # -- Begin function _Z18__device_stub__divPffS_i
.p2align 4, 0x90
.type _Z18__device_stub__divPffS_i,@function
_Z18__device_stub__divPffS_i: # @_Z18__device_stub__divPffS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3divPffS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z18__device_stub__divPffS_i, .Lfunc_end3-_Z18__device_stub__divPffS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__powPffS_i # -- Begin function _Z18__device_stub__powPffS_i
.p2align 4, 0x90
.type _Z18__device_stub__powPffS_i,@function
_Z18__device_stub__powPffS_i: # @_Z18__device_stub__powPffS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3powPffS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z18__device_stub__powPffS_i, .Lfunc_end4-_Z18__device_stub__powPffS_i
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sqrtPfS_i # -- Begin function _Z19__device_stub__sqrtPfS_i
.p2align 4, 0x90
.type _Z19__device_stub__sqrtPfS_i,@function
_Z19__device_stub__sqrtPfS_i: # @_Z19__device_stub__sqrtPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sqrtPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z19__device_stub__sqrtPfS_i, .Lfunc_end5-_Z19__device_stub__sqrtPfS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__dotPfS_S_iii # -- Begin function _Z18__device_stub__dotPfS_S_iii
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_iii,@function
_Z18__device_stub__dotPfS_S_iii: # @_Z18__device_stub__dotPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size _Z18__device_stub__dotPfS_S_iii, .Lfunc_end6-_Z18__device_stub__dotPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5minusPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPffS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3divPffS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3powPffS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sqrtPfS_i, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_iii, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_i,@object # @_Z3addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_i
.p2align 3, 0x0
_Z3addPfS_S_i:
.quad _Z18__device_stub__addPfS_S_i
.size _Z3addPfS_S_i, 8
.type _Z5minusPfS_S_i,@object # @_Z5minusPfS_S_i
.globl _Z5minusPfS_S_i
.p2align 3, 0x0
_Z5minusPfS_S_i:
.quad _Z20__device_stub__minusPfS_S_i
.size _Z5minusPfS_S_i, 8
.type _Z3mulPffS_i,@object # @_Z3mulPffS_i
.globl _Z3mulPffS_i
.p2align 3, 0x0
_Z3mulPffS_i:
.quad _Z18__device_stub__mulPffS_i
.size _Z3mulPffS_i, 8
.type _Z3divPffS_i,@object # @_Z3divPffS_i
.globl _Z3divPffS_i
.p2align 3, 0x0
_Z3divPffS_i:
.quad _Z18__device_stub__divPffS_i
.size _Z3divPffS_i, 8
.type _Z3powPffS_i,@object # @_Z3powPffS_i
.globl _Z3powPffS_i
.p2align 3, 0x0
_Z3powPffS_i:
.quad _Z18__device_stub__powPffS_i
.size _Z3powPffS_i, 8
.type _Z4sqrtPfS_i,@object # @_Z4sqrtPfS_i
.globl _Z4sqrtPfS_i
.p2align 3, 0x0
_Z4sqrtPfS_i:
.quad _Z19__device_stub__sqrtPfS_i
.size _Z4sqrtPfS_i, 8
.type _Z3dotPfS_S_iii,@object # @_Z3dotPfS_S_iii
.globl _Z3dotPfS_S_iii
.p2align 3, 0x0
_Z3dotPfS_S_iii:
.quad _Z18__device_stub__dotPfS_S_iii
.size _Z3dotPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPfS_S_i"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5minusPfS_S_i"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3mulPffS_i"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3divPffS_i"
.size .L__unnamed_4, 13
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z3powPffS_i"
.size .L__unnamed_5, 13
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4sqrtPfS_i"
.size .L__unnamed_6, 13
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z3dotPfS_S_iii"
.size .L__unnamed_7, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_i
.addrsig_sym _Z20__device_stub__minusPfS_S_i
.addrsig_sym _Z18__device_stub__mulPffS_i
.addrsig_sym _Z18__device_stub__divPffS_i
.addrsig_sym _Z18__device_stub__powPffS_i
.addrsig_sym _Z19__device_stub__sqrtPfS_i
.addrsig_sym _Z18__device_stub__dotPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_i
.addrsig_sym _Z5minusPfS_S_i
.addrsig_sym _Z3mulPffS_i
.addrsig_sym _Z3divPffS_i
.addrsig_sym _Z3powPffS_i
.addrsig_sym _Z4sqrtPfS_i
.addrsig_sym _Z3dotPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00127e74_00000000-6_matrixOps.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3addPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3addPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3addPfS_S_iPfS_S_i
.globl _Z3addPfS_S_i
.type _Z3addPfS_S_i, @function
_Z3addPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPfS_S_i, .-_Z3addPfS_S_i
.globl _Z29__device_stub__Z5minusPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5minusPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5minusPfS_S_iPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5minusPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z29__device_stub__Z5minusPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5minusPfS_S_iPfS_S_i
.globl _Z5minusPfS_S_i
.type _Z5minusPfS_S_i, @function
_Z5minusPfS_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5minusPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z5minusPfS_S_i, .-_Z5minusPfS_S_i
.globl _Z26__device_stub__Z3mulPffS_iPffS_i
.type _Z26__device_stub__Z3mulPffS_iPffS_i, @function
_Z26__device_stub__Z3mulPffS_iPffS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z26__device_stub__Z3mulPffS_iPffS_i, .-_Z26__device_stub__Z3mulPffS_iPffS_i
.globl _Z3mulPffS_i
.type _Z3mulPffS_i, @function
_Z3mulPffS_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPffS_iPffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z3mulPffS_i, .-_Z3mulPffS_i
.globl _Z26__device_stub__Z3divPffS_iPffS_i
.type _Z26__device_stub__Z3divPffS_iPffS_i, @function
_Z26__device_stub__Z3divPffS_iPffS_i:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3divPffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z26__device_stub__Z3divPffS_iPffS_i, .-_Z26__device_stub__Z3divPffS_iPffS_i
.globl _Z3divPffS_i
.type _Z3divPffS_i, @function
_Z3divPffS_i:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3divPffS_iPffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z3divPffS_i, .-_Z3divPffS_i
.globl _Z26__device_stub__Z3powPffS_iPffS_i
.type _Z26__device_stub__Z3powPffS_iPffS_i, @function
_Z26__device_stub__Z3powPffS_iPffS_i:
.LFB2059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3powPffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z26__device_stub__Z3powPffS_iPffS_i, .-_Z26__device_stub__Z3powPffS_iPffS_i
.globl _Z3powPffS_i
.type _Z3powPffS_i, @function
_Z3powPffS_i:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3powPffS_iPffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z3powPffS_i, .-_Z3powPffS_i
.globl _Z26__device_stub__Z4sqrtPfS_iPfS_i
.type _Z26__device_stub__Z4sqrtPfS_iPfS_i, @function
_Z26__device_stub__Z4sqrtPfS_iPfS_i:
.LFB2061:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sqrtPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z26__device_stub__Z4sqrtPfS_iPfS_i, .-_Z26__device_stub__Z4sqrtPfS_iPfS_i
.globl _Z4sqrtPfS_i
.type _Z4sqrtPfS_i, @function
_Z4sqrtPfS_i:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4sqrtPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z4sqrtPfS_i, .-_Z4sqrtPfS_i
.globl _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii
.type _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii, @function
_Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii:
.LFB2063:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3dotPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii, .-_Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii
.globl _Z3dotPfS_S_iii
.type _Z3dotPfS_S_iii, @function
_Z3dotPfS_S_iii:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3dotPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z3dotPfS_S_iii, .-_Z3dotPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3dotPfS_S_iii"
.LC1:
.string "_Z4sqrtPfS_i"
.LC2:
.string "_Z3powPffS_i"
.LC3:
.string "_Z3divPffS_i"
.LC4:
.string "_Z3mulPffS_i"
.LC5:
.string "_Z5minusPfS_S_i"
.LC6:
.string "_Z3addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2066:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sqrtPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3powPffS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3divPffS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPffS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5minusPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixOps.hip"
.globl _Z18__device_stub__addPfS_S_i # -- Begin function _Z18__device_stub__addPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_i,@function
_Z18__device_stub__addPfS_S_i: # @_Z18__device_stub__addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_i, .Lfunc_end0-_Z18__device_stub__addPfS_S_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__minusPfS_S_i # -- Begin function _Z20__device_stub__minusPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__minusPfS_S_i,@function
_Z20__device_stub__minusPfS_S_i: # @_Z20__device_stub__minusPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5minusPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z20__device_stub__minusPfS_S_i, .Lfunc_end1-_Z20__device_stub__minusPfS_S_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mulPffS_i # -- Begin function _Z18__device_stub__mulPffS_i
.p2align 4, 0x90
.type _Z18__device_stub__mulPffS_i,@function
_Z18__device_stub__mulPffS_i: # @_Z18__device_stub__mulPffS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPffS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__mulPffS_i, .Lfunc_end2-_Z18__device_stub__mulPffS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__divPffS_i # -- Begin function _Z18__device_stub__divPffS_i
.p2align 4, 0x90
.type _Z18__device_stub__divPffS_i,@function
_Z18__device_stub__divPffS_i: # @_Z18__device_stub__divPffS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3divPffS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z18__device_stub__divPffS_i, .Lfunc_end3-_Z18__device_stub__divPffS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__powPffS_i # -- Begin function _Z18__device_stub__powPffS_i
.p2align 4, 0x90
.type _Z18__device_stub__powPffS_i,@function
_Z18__device_stub__powPffS_i: # @_Z18__device_stub__powPffS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3powPffS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z18__device_stub__powPffS_i, .Lfunc_end4-_Z18__device_stub__powPffS_i
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sqrtPfS_i # -- Begin function _Z19__device_stub__sqrtPfS_i
.p2align 4, 0x90
.type _Z19__device_stub__sqrtPfS_i,@function
_Z19__device_stub__sqrtPfS_i: # @_Z19__device_stub__sqrtPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sqrtPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z19__device_stub__sqrtPfS_i, .Lfunc_end5-_Z19__device_stub__sqrtPfS_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__dotPfS_S_iii # -- Begin function _Z18__device_stub__dotPfS_S_iii
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_iii,@function
_Z18__device_stub__dotPfS_S_iii: # @_Z18__device_stub__dotPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size _Z18__device_stub__dotPfS_S_iii, .Lfunc_end6-_Z18__device_stub__dotPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5minusPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPffS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3divPffS_i, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3powPffS_i, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sqrtPfS_i, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_iii, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_i,@object # @_Z3addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_i
.p2align 3, 0x0
_Z3addPfS_S_i:
.quad _Z18__device_stub__addPfS_S_i
.size _Z3addPfS_S_i, 8
.type _Z5minusPfS_S_i,@object # @_Z5minusPfS_S_i
.globl _Z5minusPfS_S_i
.p2align 3, 0x0
_Z5minusPfS_S_i:
.quad _Z20__device_stub__minusPfS_S_i
.size _Z5minusPfS_S_i, 8
.type _Z3mulPffS_i,@object # @_Z3mulPffS_i
.globl _Z3mulPffS_i
.p2align 3, 0x0
_Z3mulPffS_i:
.quad _Z18__device_stub__mulPffS_i
.size _Z3mulPffS_i, 8
.type _Z3divPffS_i,@object # @_Z3divPffS_i
.globl _Z3divPffS_i
.p2align 3, 0x0
_Z3divPffS_i:
.quad _Z18__device_stub__divPffS_i
.size _Z3divPffS_i, 8
.type _Z3powPffS_i,@object # @_Z3powPffS_i
.globl _Z3powPffS_i
.p2align 3, 0x0
_Z3powPffS_i:
.quad _Z18__device_stub__powPffS_i
.size _Z3powPffS_i, 8
.type _Z4sqrtPfS_i,@object # @_Z4sqrtPfS_i
.globl _Z4sqrtPfS_i
.p2align 3, 0x0
_Z4sqrtPfS_i:
.quad _Z19__device_stub__sqrtPfS_i
.size _Z4sqrtPfS_i, 8
.type _Z3dotPfS_S_iii,@object # @_Z3dotPfS_S_iii
.globl _Z3dotPfS_S_iii
.p2align 3, 0x0
_Z3dotPfS_S_iii:
.quad _Z18__device_stub__dotPfS_S_iii
.size _Z3dotPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPfS_S_i"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5minusPfS_S_i"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3mulPffS_i"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z3divPffS_i"
.size .L__unnamed_4, 13
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z3powPffS_i"
.size .L__unnamed_5, 13
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4sqrtPfS_i"
.size .L__unnamed_6, 13
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z3dotPfS_S_iii"
.size .L__unnamed_7, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_i
.addrsig_sym _Z20__device_stub__minusPfS_S_i
.addrsig_sym _Z18__device_stub__mulPffS_i
.addrsig_sym _Z18__device_stub__divPffS_i
.addrsig_sym _Z18__device_stub__powPffS_i
.addrsig_sym _Z19__device_stub__sqrtPfS_i
.addrsig_sym _Z18__device_stub__dotPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_i
.addrsig_sym _Z5minusPfS_S_i
.addrsig_sym _Z3mulPffS_i
.addrsig_sym _Z3divPffS_i
.addrsig_sym _Z3powPffS_i
.addrsig_sym _Z4sqrtPfS_i
.addrsig_sym _Z3dotPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
using namespace std;
template<class T> struct Triplet {
T x,y,z;
Triplet(T i) : x(i), y(i), z(i) {}
};
Triplet<int> a = Triplet<int>(42);
int main () {
cout << "hi " << a.z << endl;
return 0;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
using namespace std;
template<class T> struct Triplet {
T x,y,z;
Triplet(T i) : x(i), y(i), z(i) {}
};
Triplet<int> a = Triplet<int>(42);
int main () {
cout << "hi " << a.z << endl;
return 0;
}
|
.file "tmpxft_00030ca5_00000000-6_error_is_not_a_template.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hi "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8+a(%rip), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_a, @function
_GLOBAL__sub_I_a:
.LFB4326:
.cfi_startproc
endbr64
movl $42, a(%rip)
movl $42, 4+a(%rip)
movl $42, 8+a(%rip)
ret
.cfi_endproc
.LFE4326:
.size _GLOBAL__sub_I_a, .-_GLOBAL__sub_I_a
.section .init_array
.align 8
.quad _GLOBAL__sub_I_a
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl a
.bss
.align 8
.type a, @object
.size a, 12
a:
.zero 12
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
using namespace std;
template<class T> struct Triplet {
T x,y,z;
Triplet(T i) : x(i), y(i), z(i) {}
};
Triplet<int> a = Triplet<int>(42);
int main () {
cout << "hi " << a.z << endl;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
template<class T> struct Triplet {
T x,y,z;
Triplet(T i) : x(i), y(i), z(i) {}
};
Triplet<int> a = Triplet<int>(42);
int main () {
cout << "hi " << a.z << endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
template<class T> struct Triplet {
T x,y,z;
Triplet(T i) : x(i), y(i), z(i) {}
};
Triplet<int> a = Triplet<int>(42);
int main () {
cout << "hi " << a.z << endl;
return 0;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
template<class T> struct Triplet {
T x,y,z;
Triplet(T i) : x(i), y(i), z(i) {}
};
Triplet<int> a = Triplet<int>(42);
int main () {
cout << "hi " << a.z << endl;
return 0;
}
|
.text
.file "error_is_not_a_template.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl a+8(%rip), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type a,@object # @a
.data
.globl a
.p2align 2, 0x0
a:
.long 42 # 0x2a
.long 42 # 0x2a
.long 42 # 0x2a
.size a, 12
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hi "
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00030ca5_00000000-6_error_is_not_a_template.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "hi "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8+a(%rip), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_a, @function
_GLOBAL__sub_I_a:
.LFB4326:
.cfi_startproc
endbr64
movl $42, a(%rip)
movl $42, 4+a(%rip)
movl $42, 8+a(%rip)
ret
.cfi_endproc
.LFE4326:
.size _GLOBAL__sub_I_a, .-_GLOBAL__sub_I_a
.section .init_array
.align 8
.quad _GLOBAL__sub_I_a
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl a
.bss
.align 8
.type a, @object
.size a, 12
a:
.zero 12
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "error_is_not_a_template.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl a+8(%rip), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type a,@object # @a
.data
.globl a
.p2align 2, 0x0
a:
.long 42 # 0x2a
.long 42 # 0x2a
.long 42 # 0x2a
.size a, 12
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hi "
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
using namespace std;
#define N 1024
#define INF 0x03F3F3F
int map[N * N];
int path[N];
__global__ void kernel1(int *nv,int *map,int *cost,int *tmp_cost,bool *visited,int * tmp_path)
{
const int nn = 1024;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//fetch all its neighbour
if(visited[tid])
{
visited[tid] = false;
for(int i = 0; i < *nv; ++i)
{
if(cost[tid] + map[tid * nn + i] < tmp_cost[i])
{
tmp_path[i] = tid;
tmp_cost[i] = cost[tid] + map[tid * N + i];
}
}
}
return;
}
__global__ void kernel2(int *cost,int *tmp_cost,bool *visited,bool *flag,int *tmp_path,int *path)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//some vertex can be updated,means that it is the new one to the queue
if(cost[tid] > tmp_cost[tid])
{
path[tid] = tmp_path[tid];
visited[tid] = true;
cost[tid] = tmp_cost[tid];
*flag = true;
}
tmp_cost[tid] = cost[tid];//if cost[tid] <= tmp_cost[tid]
tmp_path[tid] = path[tid];
return;
}
void print_path(int node,int path[])
{
if(path[node] == -1)
{
printf("%d ",node + 1);
return;
}
else
{
print_path(path[node],path);
printf("%d ",node + 1);
}
return;
}
int main()
{
freopen("input_dijkstra","r",stdin);
int cost[N],tmp_cost[N],path[N],tmp_path[N];
bool visited[N],flag;
int *dev_cost,*dev_tmp_cost,*dev_map,*dev_nv,*dev_path,*dev_tmp_path;
bool *dev_visited,*dev_flag;
int nv,ne;
scanf("%d%d",&nv,&ne);
//initialize
for(int i = 0; i < nv; ++i)
{
cost[i] = INF;
tmp_cost[i] = INF;
visited[i] = false;
for(int j = 0; j < nv; ++j)
map[i * N + j] = map[j * N + i] = INF;
}
//read all the edges
for(int i = 0; i < ne; ++i)
{
int p,q,w;
scanf("%d%d%d",&p,&q,&w);
map[p * N + q] = map[q * N + p] = w;
}
int source;
scanf("%d",&source);
cost[source] = tmp_cost[source] = 0;
visited[source] = true;
flag = true;
path[source] = -1;
tmp_path[source] = -1;
cout<<0<<endl;
cudaMalloc((void**)&dev_cost,N * sizeof(int));
cout<<1<<endl;
cudaMalloc((void**)&dev_tmp_cost,N * sizeof(int));
cudaMalloc((void**)&dev_visited,N * sizeof(bool));
cudaMalloc((void**)&dev_map,N * N * sizeof(int));
cudaMalloc((void**)&dev_flag,sizeof(bool));
cudaMalloc((void**)&dev_nv,sizeof(int));
cudaMalloc((void**)&dev_path,N * sizeof(int));
cudaMalloc((void**)&dev_tmp_path,N * sizeof(int));
cudaMemcpy(dev_cost,cost,N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_tmp_cost,tmp_cost,N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_visited,visited,N * sizeof(bool),cudaMemcpyHostToDevice);
cudaMemcpy(dev_map,map,N * N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_flag,&flag,sizeof(bool),cudaMemcpyHostToDevice);
cudaMemcpy(dev_nv,&nv,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_path,path,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_tmp_path,tmp_path,N*sizeof(int),cudaMemcpyHostToDevice);
while(flag)
{
flag = false;
kernel1<<<1,nv>>>(dev_nv,dev_map,dev_cost,dev_tmp_cost,dev_visited,dev_tmp_path);
cudaMemcpy(dev_flag,&flag,sizeof(bool),cudaMemcpyHostToDevice);
kernel2<<<1,nv>>>(dev_cost,dev_tmp_cost,dev_visited,dev_flag,dev_tmp_path,dev_path);
cudaMemcpy(&flag,dev_flag,sizeof(bool),cudaMemcpyDeviceToHost);
}
cudaMemcpy(cost,dev_cost,N*sizeof(int),cudaMemcpyDeviceToHost);
cudaMemcpy(path,dev_path,N*sizeof(int),cudaMemcpyDeviceToHost);
for(int i = 0; i < nv; ++i)
{
printf("Node %d cost = %2d path: ",i+1,cost[i]);
print_path(i,path);
printf("\n");
}
cout << endl;
return 0;
}
|
code for sm_80
Function : _Z7kernel2PiS_PbS0_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R2, R0.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe200078e0209 */
/*0080*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.GT.AND P0, PT, R15, R6, PT ; /* 0x000000060f00720c */
/* 0x004fe20003f04270 */
/*00b0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fd800078e0209 */
/*00c0*/ @P0 LDG.E R17, [R6.64] ; /* 0x0000000406110981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ @P0 IADD3 R12, P1, R0.reuse, c[0x0][0x170], RZ ; /* 0x00005c00000c0a10 */
/* 0x040fe20007f3e0ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.WIDE R8, R0.reuse, R9, c[0x0][0x188] ; /* 0x0000620000087625 */
/* 0x040fe200078e0209 */
/*0100*/ @P0 LEA.HI.X.SX32 R13, R0, c[0x0][0x174], 0x1, P1 ; /* 0x00005d00000d0a11 */
/* 0x000fe400008f0eff */
/*0110*/ @P0 PRMT R0, R10, 0x7610, R0 ; /* 0x000076100a000816 */
/* 0x000fe40000000000 */
/*0120*/ @P0 STG.E [R8.64], R17 ; /* 0x0000001108000986 */
/* 0x004fe8000c101904 */
/*0130*/ @P0 STG.E.U8 [R12.64], R0 ; /* 0x000000000c000986 */
/* 0x000fe8000c101104 */
/*0140*/ @P0 LDG.E R19, [R4.64] ; /* 0x0000000404130981 */
/* 0x000ea2000c1e1900 */
/*0150*/ @P0 MOV R10, c[0x0][0x178] ; /* 0x00005e00000a0a02 */
/* 0x000fe20000000f00 */
/*0160*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0b0624 */
/* 0x000fc400078e00ff */
/*0170*/ @P0 STG.E [R2.64], R19 ; /* 0x0000001302000986 */
/* 0x004fe8000c101904 */
/*0180*/ @P0 STG.E.U8 [R10.64], R0 ; /* 0x000000000a000986 */
/* 0x000fe8000c101104 */
/*0190*/ @P0 LDG.E R15, [R2.64] ; /* 0x00000004020f0981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x004fe8000c101904 */
/*01b0*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x004fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7kernel1PiS_S_S_PbS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*0060*/ IADD3 R4, P0, R0, c[0x0][0x180], RZ ; /* 0x0000600000047a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R5, R7, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610007057a10 */
/* 0x000fca00007fe4ff */
/*0080*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1100 */
/*0090*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*00c0*/ STG.E.U8 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0001e2000c101104 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*00e0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f06270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ SHF.L.U32 R4, R0, 0xa, RZ ; /* 0x0000000a00047819 */
/* 0x001fe200000006ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fe200000001ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0150*/ MOV R19, c[0x0][0x18c] ; /* 0x0000630000137a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0180*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fe20000000f00 */
/*0190*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff107624 */
/* 0x000fe200078e00ff */
/*01a0*/ LEA R4, P0, R0.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0000047a11 */
/* 0x040fe200078010ff */
/*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0e7624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff117624 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA.HI.X R5, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000057a11 */
/* 0x000fc800000f1407 */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0011 */
/*0210*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee2000c1e1900 */
/*0230*/ IADD3 R10, R10, R11, RZ ; /* 0x0000000b0a0a7210 */
/* 0x004fc80007ffe0ff */
/*0240*/ ISETP.GE.AND P0, PT, R10, R15, PT ; /* 0x0000000f0a00720c */
/* 0x008fda0003f06270 */
/*0250*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a8224 */
/* 0x000fe400078e0010 */
/*0260*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b8224 */
/* 0x000fca00078e0013 */
/*0270*/ @!P0 STG.E [R10.64], R0 ; /* 0x000000000a008986 */
/* 0x0001e8000c101904 */
/*0280*/ @!P0 LDG.E R14, [R8.64] ; /* 0x00000004080e8981 */
/* 0x000ea8000c1e1900 */
/*0290*/ @!P0 LDG.E R15, [R4.64] ; /* 0x00000004040f8981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ @!P0 IADD3 R15, R14, R15, RZ ; /* 0x0000000f0e0f8210 */
/* 0x004fca0007ffe0ff */
/*02b0*/ @!P0 STG.E [R6.64], R15 ; /* 0x0000000f06008986 */
/* 0x0001e8000c101904 */
/*02c0*/ @!P0 LDG.E R12, [R2.64] ; /* 0x00000004020c8981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R14, P2, R6, 0x4, RZ ; /* 0x00000004060e7810 */
/* 0x000fe40007f5e0ff */
/*02f0*/ IADD3 R8, P3, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f7e0ff */
/*0300*/ IADD3 R16, P1, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fe20007f3e0ff */
/*0310*/ IMAD.X R17, RZ, RZ, R7, P2 ; /* 0x000000ffff117224 */
/* 0x000fc400010e0607 */
/*0320*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0330*/ IADD3.X R19, RZ, R19, RZ, P1, !PT ; /* 0x00000013ff137210 */
/* 0x000fe40000ffe4ff */
/*0340*/ ISETP.GE.AND P0, PT, R13, R12, PT ; /* 0x0000000c0d00720c */
/* 0x004fda0003f06270 */
/*0350*/ @!P0 BRA 0x1e0 ; /* 0xfffffe8000008947 */
/* 0x001fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <cstdio>
#include <cstdlib>
#include <cstring>
using namespace std;
#define N 1024
#define INF 0x03F3F3F
int map[N * N];
int path[N];
__global__ void kernel1(int *nv,int *map,int *cost,int *tmp_cost,bool *visited,int * tmp_path)
{
const int nn = 1024;
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//fetch all its neighbour
if(visited[tid])
{
visited[tid] = false;
for(int i = 0; i < *nv; ++i)
{
if(cost[tid] + map[tid * nn + i] < tmp_cost[i])
{
tmp_path[i] = tid;
tmp_cost[i] = cost[tid] + map[tid * N + i];
}
}
}
return;
}
__global__ void kernel2(int *cost,int *tmp_cost,bool *visited,bool *flag,int *tmp_path,int *path)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
//some vertex can be updated,means that it is the new one to the queue
if(cost[tid] > tmp_cost[tid])
{
path[tid] = tmp_path[tid];
visited[tid] = true;
cost[tid] = tmp_cost[tid];
*flag = true;
}
tmp_cost[tid] = cost[tid];//if cost[tid] <= tmp_cost[tid]
tmp_path[tid] = path[tid];
return;
}
void print_path(int node,int path[])
{
if(path[node] == -1)
{
printf("%d ",node + 1);
return;
}
else
{
print_path(path[node],path);
printf("%d ",node + 1);
}
return;
}
int main()
{
freopen("input_dijkstra","r",stdin);
int cost[N],tmp_cost[N],path[N],tmp_path[N];
bool visited[N],flag;
int *dev_cost,*dev_tmp_cost,*dev_map,*dev_nv,*dev_path,*dev_tmp_path;
bool *dev_visited,*dev_flag;
int nv,ne;
scanf("%d%d",&nv,&ne);
//initialize
for(int i = 0; i < nv; ++i)
{
cost[i] = INF;
tmp_cost[i] = INF;
visited[i] = false;
for(int j = 0; j < nv; ++j)
map[i * N + j] = map[j * N + i] = INF;
}
//read all the edges
for(int i = 0; i < ne; ++i)
{
int p,q,w;
scanf("%d%d%d",&p,&q,&w);
map[p * N + q] = map[q * N + p] = w;
}
int source;
scanf("%d",&source);
cost[source] = tmp_cost[source] = 0;
visited[source] = true;
flag = true;
path[source] = -1;
tmp_path[source] = -1;
cout<<0<<endl;
cudaMalloc((void**)&dev_cost,N * sizeof(int));
cout<<1<<endl;
cudaMalloc((void**)&dev_tmp_cost,N * sizeof(int));
cudaMalloc((void**)&dev_visited,N * sizeof(bool));
cudaMalloc((void**)&dev_map,N * N * sizeof(int));
cudaMalloc((void**)&dev_flag,sizeof(bool));
cudaMalloc((void**)&dev_nv,sizeof(int));
cudaMalloc((void**)&dev_path,N * sizeof(int));
cudaMalloc((void**)&dev_tmp_path,N * sizeof(int));
cudaMemcpy(dev_cost,cost,N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_tmp_cost,tmp_cost,N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_visited,visited,N * sizeof(bool),cudaMemcpyHostToDevice);
cudaMemcpy(dev_map,map,N * N * sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_flag,&flag,sizeof(bool),cudaMemcpyHostToDevice);
cudaMemcpy(dev_nv,&nv,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_path,path,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_tmp_path,tmp_path,N*sizeof(int),cudaMemcpyHostToDevice);
while(flag)
{
flag = false;
kernel1<<<1,nv>>>(dev_nv,dev_map,dev_cost,dev_tmp_cost,dev_visited,dev_tmp_path);
cudaMemcpy(dev_flag,&flag,sizeof(bool),cudaMemcpyHostToDevice);
kernel2<<<1,nv>>>(dev_cost,dev_tmp_cost,dev_visited,dev_flag,dev_tmp_path,dev_path);
cudaMemcpy(&flag,dev_flag,sizeof(bool),cudaMemcpyDeviceToHost);
}
cudaMemcpy(cost,dev_cost,N*sizeof(int),cudaMemcpyDeviceToHost);
cudaMemcpy(path,dev_path,N*sizeof(int),cudaMemcpyDeviceToHost);
for(int i = 0; i < nv; ++i)
{
printf("Node %d cost = %2d path: ",i+1,cost[i]);
print_path(i,path);
printf("\n");
}
cout << endl;
return 0;
}
|
.file "tmpxft_000cb8ae_00000000-6_dijkstra.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl _Z10print_pathiPi
.type _Z10print_pathiPi, @function
_Z10print_pathiPi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
movslq %edi, %rax
movl (%rsi,%rax,4), %edi
cmpl $-1, %edi
je .L7
call _Z10print_pathiPi
leal 1(%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leal 1(%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE3669:
.size _Z10print_pathiPi, .-_Z10print_pathiPi
.globl _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
.type _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_, @function
_Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernel1PiS_S_S_PbS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_, .-_Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
.globl _Z7kernel1PiS_S_S_PbS_
.type _Z7kernel1PiS_S_S_PbS_, @function
_Z7kernel1PiS_S_S_PbS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7kernel1PiS_S_S_PbS_, .-_Z7kernel1PiS_S_S_PbS_
.globl _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
.type _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_, @function
_Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernel2PiS_PbS0_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_, .-_Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
.globl _Z7kernel2PiS_PbS0_S_S_
.type _Z7kernel2PiS_PbS0_S_S_, @function
_Z7kernel2PiS_PbS0_S_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7kernel2PiS_PbS0_S_S_, .-_Z7kernel2PiS_PbS0_S_S_
.section .rodata.str1.1
.LC1:
.string "r"
.LC2:
.string "input_dijkstra"
.LC3:
.string "%d%d"
.LC4:
.string "%d%d%d"
.LC5:
.string "%d"
.LC6:
.string "Node %d cost = %2d path: "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -16384(%rsp), %r11
.cfi_def_cfa 11, 16440
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1160, %rsp
.cfi_def_cfa_offset 17600
movq %fs:40, %rax
movq %rax, 17528(%rsp)
xorl %eax, %eax
movq stdin(%rip), %rdx
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call freopen@PLT
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %r8d
testl %r8d, %r8d
jle .L25
leaq map(%rip), %rdi
movslq %r8d, %r8
movq %r8, %rcx
salq $12, %rcx
addq %rdi, %rcx
movq %r8, %r9
negq %r9
salq $12, %r9
movl $0, %esi
.L27:
movl $4144959, 1136(%rsp,%rsi,4)
movl $4144959, 5232(%rsp,%rsi,4)
movb $0, 112(%rsp,%rsi)
leaq (%rcx,%r9), %rax
movq %rdi, %rdx
.L26:
movl $4144959, (%rax)
movl $4144959, (%rdx)
addq $4096, %rax
addq $4, %rdx
cmpq %rcx, %rax
jne .L26
addq $1, %rsi
addq $4096, %rdi
addq $4, %rcx
cmpq %r8, %rsi
jne .L27
.L25:
cmpl $0, 16(%rsp)
jle .L28
movl $0, %ebx
leaq 100(%rsp), %r14
leaq 88(%rsp), %r13
leaq .LC4(%rip), %r12
leaq map(%rip), %rbp
.L29:
leaq 80(%rsp), %rsi
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 88(%rsp), %esi
movl 80(%rsp), %eax
movl 100(%rsp), %ecx
movl %esi, %edx
sall $10, %edx
addl %eax, %edx
movslq %edx, %rdx
movl %ecx, 0(%rbp,%rdx,4)
sall $10, %eax
addl %esi, %eax
cltq
movl %ecx, 0(%rbp,%rax,4)
addl $1, %ebx
cmpl %ebx, 16(%rsp)
jg .L29
.L28:
leaq 20(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 20(%rsp), %rax
movl $0, 5232(%rsp,%rax,4)
movl $0, 1136(%rsp,%rax,4)
movb $1, 112(%rsp,%rax)
movb $1, 11(%rsp)
movl $-1, 9328(%rsp,%rax,4)
movl $-1, 13424(%rsp,%rax,4)
movl $0, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 32(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 1136(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 5232(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq map(%rip), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 11(%rsp), %rsi
movl $1, %ecx
movl $1, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 9328(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 13424(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
cmpb $0, 11(%rsp)
je .L30
leaq 11(%rsp), %rbx
jmp .L33
.L43:
movq 64(%rsp), %r9
movq 72(%rsp), %r8
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z36__device_stub__Z7kernel1PiS_S_S_PbS_PiS_S_S_PbS_
jmp .L31
.L32:
movl $2, %ecx
movl $1, %edx
movq 80(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpb $0, 11(%rsp)
je .L30
.L33:
movb $0, 11(%rsp)
movl 12(%rsp), %eax
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L31:
movl $1, %ecx
movl $1, %edx
movq %rbx, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq 56(%rsp), %r9
movq 64(%rsp), %r8
movq 80(%rsp), %rcx
movq 72(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z7kernel2PiS_PbS0_S_S_PiS_PbS0_S_S_
jmp .L32
.L30:
leaq 1136(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq 9328(%rsp), %rdi
movl $2, %ecx
movl $4096, %edx
movq 56(%rsp), %rsi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L34
leaq 1136(%rsp), %rbp
movl $0, %ebx
leaq .LC6(%rip), %r15
leaq 9328(%rsp), %r14
leaq .LC7(%rip), %r13
.L35:
movl %ebx, %r12d
addl $1, %ebx
movl 0(%rbp), %ecx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rsi
movl %r12d, %edi
call _Z10print_pathiPi
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpl 12(%rsp), %ebx
jl .L35
.L34:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 17528(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $17544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7kernel2PiS_PbS0_S_S_"
.LC9:
.string "_Z7kernel1PiS_S_S_PbS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel2PiS_PbS0_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1PiS_S_S_PbS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl path
.bss
.align 32
.type path, @object
.size path, 4096
path:
.zero 4096
.globl map
.align 32
.type map, @object
.size map, 4194304
map:
.zero 4194304
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
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