system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* correlation.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 1.05
#define GPU_DEVICE 0
/* Problem size */
#define M 2048
#define N 2048
/* Thread block dimensions for kernel 1*/
#define DIM_THREAD_BLOCK_KERNEL_1_X 256
#define DIM_THREAD_BLOCK_KERNEL_1_Y 1
/* Thread block dimensions for kernel 2*/
#define DIM_THREAD_BLOCK_KERNEL_2_X 256
#define DIM_THREAD_BLOCK_KERNEL_2_Y 1
/* Thread block dimensions for kernel 3*/
#define DIM_THREAD_BLOCK_KERNEL_3_X 32
#define DIM_THREAD_BLOCK_KERNEL_3_Y 8
/* Thread block dimensions for kernel 4*/
#define DIM_THREAD_BLOCK_KERNEL_4_X 256
#define DIM_THREAD_BLOCK_KERNEL_4_Y 1
#define sqrt_of_array_cell(x,j) sqrt(x[j])
#define FLOAT_N 3214212.01f
#define EPS 0.005f
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void init_arrays(DATA_TYPE* data)
{
int i, j;
for (i=0; i < (M+1); i++)
{
for (j=0; j< (N+1); j++)
{
data[i*(N+1) + j] = ((DATA_TYPE) i*j)/ (M+1);
}
}
}
void correlation(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat)
{
int i, j, j1, j2;
// Determine mean of column vectors of input data matrix
for (j = 1; j < (M+1); j++)
{
mean[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
// Determine standard deviations of column vectors of data matrix.
for (j = 1; j < (M+1); j++)
{
stddev[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
stddev[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
stddev[j] /= FLOAT_N;
stddev[j] = sqrt_of_array_cell(stddev, j);
stddev[j] = stddev[j] <= EPS ? 1.0 : stddev[j];
}
// Center and reduce the column vectors.
for (i = 1; i < (N+1); i++)
{
for (j = 1; j < (M+1); j++)
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N)*stddev[j]) ;
}
}
// Calculate the m * m correlation matrix.
for (j1 = 1; j1 < M; j1++)
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = j1+1; j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += (data[i*(M+1) + j1] * data[i*(M+1) + j2]);
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
symmat[M*(M+1) + M] = 1.0;
}
void compareResults(DATA_TYPE* symmat, DATA_TYPE* symmat_outputFromGpu)
{
int i,j,fail;
fail = 0;
for (i=1; i < (M+1); i++)
{
for (j=1; j < (N+1); j++)
{
if (percentDiff(symmat[i*(N+1) + j], symmat_outputFromGpu[i*(N+1) + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
printf("i: %d j: %d\n1: %f 2: %f\n", i, j, symmat[i*N + j], symmat_outputFromGpu[i*N + j]);
}
}
}
// print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void mean_kernel(DATA_TYPE *mean, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
mean[j] = 0.0;
int i;
for(i=1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
}
__global__ void std_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
std[j] = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
std[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
std[j] /= (FLOAT_N);
std[j] = sqrt(std[j]);
if(std[j] <= EPS)
{
std[j] = 1.0;
}
}
}
__global__ void reduce_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i >= 1) && (i < (N+1)) && (j >= 1) && (j < (M+1)))
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N) * std[j]);
}
}
__global__ void corr_kernel(DATA_TYPE *symmat, DATA_TYPE *data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
if ((j1 >= 1) && (j1 < M))
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = (j1 + 1); j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += data[i*(M+1) + j1] * data[i*(M+1) + j2];
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
}
void correlationCuda(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat,
DATA_TYPE* symmat_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *data_gpu;
DATA_TYPE *stddev_gpu;
DATA_TYPE *mean_gpu;
DATA_TYPE *symmat_gpu;
hipMalloc((void **)&data_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
hipMalloc((void **)&symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
hipMalloc((void **)&stddev_gpu, sizeof(DATA_TYPE) * (M+1));
hipMalloc((void **)&mean_gpu, sizeof(DATA_TYPE) * (M+1));
hipMemcpy(data_gpu, data, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyHostToDevice);
hipMemcpy(symmat_gpu, symmat, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyHostToDevice);
hipMemcpy(stddev_gpu, stddev, sizeof(DATA_TYPE) * (M+1), hipMemcpyHostToDevice);
hipMemcpy(mean_gpu, mean, sizeof(DATA_TYPE) * (M+1), hipMemcpyHostToDevice);
dim3 block1(DIM_THREAD_BLOCK_KERNEL_1_X, DIM_THREAD_BLOCK_KERNEL_1_Y);
dim3 grid1((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_1_X)), 1);
dim3 block2(DIM_THREAD_BLOCK_KERNEL_2_X, DIM_THREAD_BLOCK_KERNEL_2_Y);
dim3 grid2((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_2_X)), 1);
dim3 block3(DIM_THREAD_BLOCK_KERNEL_3_X, DIM_THREAD_BLOCK_KERNEL_3_Y);
dim3 grid3((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_X)), (size_t)(ceil((float)(N)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_Y)));
dim3 block4(DIM_THREAD_BLOCK_KERNEL_4_X, DIM_THREAD_BLOCK_KERNEL_4_Y);
dim3 grid4((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_4_X)), 1);
t_start = rtclock();
mean_kernel<<< grid1, block1 >>>(mean_gpu,data_gpu);
hipDeviceSynchronize();
std_kernel<<< grid2, block2 >>>(mean_gpu,stddev_gpu,data_gpu);
hipDeviceSynchronize();
reduce_kernel<<< grid3, block3 >>>(mean_gpu,stddev_gpu,data_gpu);
hipDeviceSynchronize();
corr_kernel<<< grid4, block4 >>>(symmat_gpu,data_gpu);
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
DATA_TYPE valueAtSymmatIndexMTimesMPlus1PlusMPoint = 1.0;
hipMemcpy(&(symmat_gpu[(M)*(M+1) + (M)]), &valueAtSymmatIndexMTimesMPlus1PlusMPoint, sizeof(DATA_TYPE), hipMemcpyHostToDevice);
hipMemcpy(symmat_outputFromGpu, symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyDeviceToHost);
hipFree(data_gpu);
hipFree(symmat_gpu);
hipFree(stddev_gpu);
hipFree(mean_gpu);
}
int main()
{
double t_start, t_end;
DATA_TYPE* data;
DATA_TYPE* mean;
DATA_TYPE* stddev;
DATA_TYPE* symmat;
DATA_TYPE* symmat_outputFromGpu;
data = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
mean = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
stddev = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
symmat = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
symmat_outputFromGpu = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
init_arrays(data);
GPU_argv_init();
correlationCuda(data, mean, stddev, symmat, symmat_outputFromGpu);
t_start = rtclock();
correlation(data, mean, stddev, symmat);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(symmat, symmat_outputFromGpu);
free(data);
free(mean);
free(stddev);
free(symmat);
free(symmat_outputFromGpu);
return 0;
} | .text
.file "correlation.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6absValf
.LCPI1_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z6absValf
.p2align 4, 0x90
.type _Z6absValf,@function
_Z6absValf: # @_Z6absValf
.cfi_startproc
# %bb.0:
movaps .LCPI1_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end1:
.size _Z6absValf, .Lfunc_end1-_Z6absValf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11percentDiffdd
.LCPI2_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI2_2:
.quad 0x3e45798ee0000000 # double 9.9999999392252903E-9
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_3:
.long 0x42c80000 # float 100
.text
.globl _Z11percentDiffdd
.p2align 4, 0x90
.type _Z11percentDiffdd,@function
_Z11percentDiffdd: # @_Z11percentDiffdd
.cfi_startproc
# %bb.0:
cvtsd2ss %xmm0, %xmm2
movaps .LCPI2_0(%rip), %xmm3 # xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm3
maxss %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
ucomisd %xmm2, %xmm3
jbe .LBB2_2
# %bb.1:
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movaps .LCPI2_0(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm4
maxss %xmm2, %xmm4
cvtss2sd %xmm4, %xmm4
xorps %xmm2, %xmm2
ucomisd %xmm4, %xmm3
ja .LBB2_3
.LBB2_2:
movaps %xmm0, %xmm2
subsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
movaps .LCPI2_0(%rip), %xmm2 # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movaps %xmm1, %xmm3
xorps %xmm2, %xmm3
maxss %xmm1, %xmm3
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm1
xorps %xmm2, %xmm1
maxss %xmm0, %xmm1
divss %xmm1, %xmm3
xorps %xmm3, %xmm2
maxss %xmm3, %xmm2
mulss .LCPI2_3(%rip), %xmm2
.LBB2_3:
movaps %xmm2, %xmm0
retq
.Lfunc_end2:
.size _Z11percentDiffdd, .Lfunc_end2-_Z11percentDiffdd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11init_arraysPf
.LCPI3_0:
.long 0x45001000 # float 2049
.text
.globl _Z11init_arraysPf
.p2align 4, 0x90
.type _Z11init_arraysPf,@function
_Z11init_arraysPf: # @_Z11init_arraysPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %ecx, %xmm2
mulss %xmm1, %xmm2
divss %xmm0, %xmm2
movss %xmm2, (%rdi,%rcx,4)
incq %rcx
cmpq $2049, %rcx # imm = 0x801
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $8196, %rdi # imm = 0x2004
cmpq $2049, %rax # imm = 0x801
jne .LBB3_1
# %bb.4:
retq
.Lfunc_end3:
.size _Z11init_arraysPf, .Lfunc_end3-_Z11init_arraysPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11correlationPfS_S_S_
.LCPI4_0:
.long 0x4a442e10 # float 3214212
.LCPI4_1:
.long 0x3ba3d70a # float 0.00499999989
.LCPI4_2:
.long 0x3f800000 # float 1
.LCPI4_3:
.long 0x44e01a51 # float 1792.82239
.text
.globl _Z11correlationPfS_S_S_
.p2align 4, 0x90
.type _Z11correlationPfS_S_S_,@function
_Z11correlationPfS_S_S_: # @_Z11correlationPfS_S_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r14
movl $1, %eax
movss .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq %rdi, %rcx
.p2align 4, 0x90
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movl $0, (%r12,%rax,4)
xorps %xmm0, %xmm0
movl $8200, %edx # imm = 0x2008
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rcx,%rdx), %xmm0
movss %xmm0, (%r12,%rax,4)
addq $8196, %rdx # imm = 0x2004
cmpq $16793608, %rdx # imm = 0x1004008
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm2, %xmm0
movss %xmm0, (%r12,%rax,4)
incq %rax
addq $4, %rcx
cmpq $2049, %rax # imm = 0x801
jne .LBB4_1
# %bb.4: # %.preheader93.preheader
movl $1, %r13d
xorps %xmm3, %xmm3
movss .LCPI4_1(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI4_2(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movq %r14, %rbp
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_9: # %call.sqrt
# in Loop: Header=BB4_5 Depth=1
callq sqrtf
movss .LCPI4_2(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI4_1(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
movss .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.LBB4_10: # %.split
# in Loop: Header=BB4_5 Depth=1
movaps %xmm0, %xmm1
cmpnless %xmm4, %xmm1
andps %xmm1, %xmm0
andnps %xmm5, %xmm1
orps %xmm0, %xmm1
movss %xmm1, (%r15,%r13,4)
incq %r13
addq $4, %rbp
cmpq $2049, %r13 # imm = 0x801
je .LBB4_11
.LBB4_5: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
movl $0, (%r15,%r13,4)
movl $8200, %eax # imm = 0x2008
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r12,%r13,4), %xmm0
mulss %xmm0, %xmm0
addss (%r15,%r13,4), %xmm0
movss %xmm0, (%r15,%r13,4)
addq $8196, %rax # imm = 0x2004
cmpq $16793608, %rax # imm = 0x1004008
jne .LBB4_6
# %bb.7: # in Loop: Header=BB4_5 Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm2, %xmm0
ucomiss %xmm3, %xmm0
jb .LBB4_9
# %bb.8: # in Loop: Header=BB4_5 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB4_10
.LBB4_11: # %.preheader91.preheader
leaq 8200(%r14), %rax
movl $1, %ecx
movss .LCPI4_3(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB4_12: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_12 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rax,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss 4(%r12,%rdx,4), %xmm1
movss %xmm1, (%rax,%rdx,4)
movss 4(%r15,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm0, %xmm2
divss %xmm2, %xmm1
movss %xmm1, (%rax,%rdx,4)
incq %rdx
cmpq $2048, %rdx # imm = 0x800
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=1
incq %rcx
addq $8196, %rax # imm = 0x2004
cmpq $2049, %rcx # imm = 0x801
jne .LBB4_12
# %bb.15: # %.preheader.preheader
leaq 8204(%r14), %rax
addq $8200, %r14 # imm = 0x2008
movl $2, %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB4_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_18 Depth 2
# Child Loop BB4_19 Depth 3
movq %rdx, %rsi
shlq $13, %rsi
leaq (%rsi,%rdx,8), %rdi
movl $1065353216, (%rbx,%rdi) # imm = 0x3F800000
leaq (%rsi,%rdx,4), %rsi
leaq (%rbx,%rdx,4), %rdi
incq %rdx
addq %rbx, %rsi
movq %rax, %r8
movq %rcx, %r9
.p2align 4, 0x90
.LBB4_18: # %.lr.ph
# Parent Loop BB4_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_19 Depth 3
movl $0, (%rsi,%r9,4)
xorps %xmm0, %xmm0
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_17 Depth=1
# Parent Loop BB4_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r14,%r10), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r8,%r10), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%rsi,%r9,4)
addq $8196, %r10 # imm = 0x2004
cmpq $16785408, %r10 # imm = 0x1002000
jne .LBB4_19
# %bb.20: # in Loop: Header=BB4_18 Depth=2
movss (%rsi,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r9, %r10
shlq $13, %r10
leaq (%r10,%r9,4), %r10
movss %xmm0, (%rdi,%r10)
incq %r9
addq $4, %r8
cmpq $2049, %r9 # imm = 0x801
jne .LBB4_18
# %bb.16: # %.loopexit
# in Loop: Header=BB4_17 Depth=1
incq %rcx
addq $4, %rax
addq $4, %r14
cmpq $2048, %rdx # imm = 0x800
jne .LBB4_17
# %bb.21:
movl $1065353216, 16793600(%rbx) # imm = 0x3F800000
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z11correlationPfS_S_S_, .Lfunc_end4-_Z11correlationPfS_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14compareResultsPfS_
.LCPI5_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI5_4:
.quad 0x3ff0cccccccccccd # double 1.05
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_2:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI5_3:
.long 0x42c80000 # float 100
.text
.globl _Z14compareResultsPfS_
.p2align 4, 0x90
.type _Z14compareResultsPfS_,@function
_Z14compareResultsPfS_: # @_Z14compareResultsPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 8196(%rsi), %rax
movq %rax, (%rsp) # 8-byte Spill
leaq 8196(%rdi), %rbp
addq $8200, %rbx # imm = 0x2008
addq $8200, %r14 # imm = 0x2008
xorl %r15d, %r15d
movl $1, %r12d
movaps .LCPI5_0(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI5_1(%rip), %xmm5 # xmm5 = mem[0],zero
movsd .LCPI5_4(%rip), %xmm6 # xmm6 = mem[0],zero
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_1 Depth=1
incq %r12
addq $8192, (%rsp) # 8-byte Folded Spill
# imm = 0x2000
addq $8192, %rbp # imm = 0x2000
addq $8196, %rbx # imm = 0x2004
addq $8196, %r14 # imm = 0x2004
cmpq $2049, %r12 # imm = 0x801
je .LBB5_9
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # in Loop: Header=BB5_2 Depth=2
incq %r13
cmpq $2048, %r13 # imm = 0x800
je .LBB5_8
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbx,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm2
xorps %xmm4, %xmm2
maxss %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm5
jbe .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=2
movaps %xmm1, %xmm2
xorps %xmm4, %xmm2
maxss %xmm1, %xmm2
xorps %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
xorps %xmm2, %xmm2
ucomisd %xmm3, %xmm5
ja .LBB5_5
.LBB5_4: # in Loop: Header=BB5_2 Depth=2
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
movaps %xmm2, %xmm1
xorps %xmm4, %xmm1
maxss %xmm2, %xmm1
addss .LCPI5_2(%rip), %xmm0
movaps %xmm0, %xmm2
xorps %xmm4, %xmm2
maxss %xmm0, %xmm2
divss %xmm2, %xmm1
movaps %xmm1, %xmm2
xorps %xmm4, %xmm2
maxss %xmm1, %xmm2
mulss .LCPI5_3(%rip), %xmm2
.LBB5_5: # %_Z11percentDiffdd.exit
# in Loop: Header=BB5_2 Depth=2
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
ucomisd %xmm6, %xmm0
jbe .LBB5_7
# %bb.6: # in Loop: Header=BB5_2 Depth=2
incl %r15d
movss (%rbp,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq (%rsp), %rax # 8-byte Reload
movss (%rax,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
leal 1(%r13), %edx
movl $.L.str.1, %edi
movl %r12d, %esi
movb $2, %al
callq printf
movsd .LCPI5_4(%rip), %xmm6 # xmm6 = mem[0],zero
movsd .LCPI5_1(%rip), %xmm5 # xmm5 = mem[0],zero
movaps .LCPI5_0(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
jmp .LBB5_7
.LBB5_9:
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movl %r15d, %esi
movb $1, %al
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z14compareResultsPfS_, .Lfunc_end5-_Z14compareResultsPfS_
.cfi_endproc
# -- End function
.globl _Z13GPU_argv_initv # -- Begin function _Z13GPU_argv_initv
.p2align 4, 0x90
.type _Z13GPU_argv_initv,@function
_Z13GPU_argv_initv: # @_Z13GPU_argv_initv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.3, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13GPU_argv_initv, .Lfunc_end6-_Z13GPU_argv_initv
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mean_kernelPfS_ # -- Begin function _Z26__device_stub__mean_kernelPfS_
.p2align 4, 0x90
.type _Z26__device_stub__mean_kernelPfS_,@function
_Z26__device_stub__mean_kernelPfS_: # @_Z26__device_stub__mean_kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11mean_kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size _Z26__device_stub__mean_kernelPfS_, .Lfunc_end7-_Z26__device_stub__mean_kernelPfS_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__std_kernelPfS_S_ # -- Begin function _Z25__device_stub__std_kernelPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__std_kernelPfS_S_,@function
_Z25__device_stub__std_kernelPfS_S_: # @_Z25__device_stub__std_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10std_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end8:
.size _Z25__device_stub__std_kernelPfS_S_, .Lfunc_end8-_Z25__device_stub__std_kernelPfS_S_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__reduce_kernelPfS_S_ # -- Begin function _Z28__device_stub__reduce_kernelPfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__reduce_kernelPfS_S_,@function
_Z28__device_stub__reduce_kernelPfS_S_: # @_Z28__device_stub__reduce_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end9:
.size _Z28__device_stub__reduce_kernelPfS_S_, .Lfunc_end9-_Z28__device_stub__reduce_kernelPfS_S_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__corr_kernelPfS_ # -- Begin function _Z26__device_stub__corr_kernelPfS_
.p2align 4, 0x90
.type _Z26__device_stub__corr_kernelPfS_,@function
_Z26__device_stub__corr_kernelPfS_: # @_Z26__device_stub__corr_kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11corr_kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end10:
.size _Z26__device_stub__corr_kernelPfS_, .Lfunc_end10-_Z26__device_stub__corr_kernelPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15correlationCudaPfS_S_S_S_
.LCPI11_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z15correlationCudaPfS_S_S_S_
.p2align 4, 0x90
.type _Z15correlationCudaPfS_S_S_S_,@function
_Z15correlationCudaPfS_S_S_S_: # @_Z15correlationCudaPfS_S_S_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r12
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %r13
leaq 88(%rsp), %rdi
movl $16793604, %esi # imm = 0x1004004
callq hipMalloc
leaq 96(%rsp), %rdi
movl $16793604, %esi # imm = 0x1004004
callq hipMalloc
leaq 112(%rsp), %rdi
movl $8196, %esi # imm = 0x2004
callq hipMalloc
leaq 104(%rsp), %rdi
movl $8196, %esi # imm = 0x2004
callq hipMalloc
movq 88(%rsp), %rdi
movl $16793604, %edx # imm = 0x1004004
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rdi
movl $16793604, %edx # imm = 0x1004004
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 112(%rsp), %rdi
movl $8196, %edx # imm = 0x2004
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
movl $8196, %edx # imm = 0x2004
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 64(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB11_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB11_2: # %_Z7rtclockv.exit
movabsq $4294967304, %r14 # imm = 0x100000008
movq 64(%rsp), %r12
movq 72(%rsp), %r13
leaq 248(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_4
# %bb.3:
movq 104(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11mean_kernelPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB11_4:
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_6
# %bb.5:
movq 104(%rsp), %rax
movq 112(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 24(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10std_kernelPfS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB11_6:
callq hipDeviceSynchronize
movabsq $1099511627840, %rdi # imm = 0x10000000040
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_8
# %bb.7:
movq 104(%rsp), %rax
movq 112(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
movq %rdx, 24(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 24(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13reduce_kernelPfS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB11_8:
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_10
# %bb.9:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11corr_kernelPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB11_10:
callq hipDeviceSynchronize
leaq 64(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB11_12
# %bb.11:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB11_12: # %_Z7rtclockv.exit59
cvtsi2sd %r13, %xmm0
movsd .LCPI11_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsi2sd %r12, %xmm2
addsd %xmm0, %xmm2
cvtsi2sdq 64(%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0
mulsd %xmm1, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movl $1065353216, 64(%rsp) # imm = 0x3F800000
movl $16793600, %edi # imm = 0x1004000
addq 96(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 96(%rsp), %rsi
movl $16793604, %edx # imm = 0x1004004
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _Z15correlationCudaPfS_S_S_S_, .Lfunc_end11-_Z15correlationCudaPfS_S_S_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI12_0:
.long 0x45001000 # float 2049
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI12_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $16793604, %edi # imm = 0x1004004
callq malloc
movq %rax, %rbx
movl $8196, %edi # imm = 0x2004
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movl $8196, %edi # imm = 0x2004
callq malloc
movq %rax, %r15
movl $16793604, %edi # imm = 0x1004004
callq malloc
movq %rax, %r12
movl $16793604, %edi # imm = 0x1004004
callq malloc
movq %rax, %r13
xorl %eax, %eax
movss .LCPI12_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rcx
.p2align 4, 0x90
.LBB12_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB12_2 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB12_2: # Parent Loop BB12_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
mulss %xmm1, %xmm2
divss %xmm0, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $2049, %rdx # imm = 0x801
jne .LBB12_2
# %bb.3: # in Loop: Header=BB12_1 Depth=1
incq %rax
addq $8196, %rcx # imm = 0x2004
cmpq $2049, %rax # imm = 0x801
jne .LBB12_1
# %bb.4: # %_Z11init_arraysPf.exit
leaq 24(%rsp), %rbp
movq %rbp, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.3, %edi
xorl %esi, %esi
movq %rbp, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movq %rbx, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movq %r12, %rcx
movq %r13, %r8
callq _Z15correlationCudaPfS_S_S_S_
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB12_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB12_6: # %_Z7rtclockv.exit
movq 24(%rsp), %rbp
movq 32(%rsp), %r14
movq %rbx, %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movq %r12, %rcx
callq _Z11correlationPfS_S_S_
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB12_8
# %bb.7:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB12_8: # %_Z7rtclockv.exit20
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
movsd .LCPI12_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %rbp, %xmm2
addsd %xmm0, %xmm2
cvtsi2sdq 24(%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
mulsd %xmm1, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.5, %esi
movb $1, %al
callq fprintf
movq %r12, %rdi
movq %r13, %rsi
callq _Z14compareResultsPfS_
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size main, .Lfunc_end12-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mean_kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10std_kernelPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduce_kernelPfS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11corr_kernelPfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "i: %d j: %d\n1: %f 2: %f\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.size .L.str.2, 74
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "setting device %d with name %s\n"
.size .L.str.3, 32
.type _Z11mean_kernelPfS_,@object # @_Z11mean_kernelPfS_
.section .rodata,"a",@progbits
.globl _Z11mean_kernelPfS_
.p2align 3, 0x0
_Z11mean_kernelPfS_:
.quad _Z26__device_stub__mean_kernelPfS_
.size _Z11mean_kernelPfS_, 8
.type _Z10std_kernelPfS_S_,@object # @_Z10std_kernelPfS_S_
.globl _Z10std_kernelPfS_S_
.p2align 3, 0x0
_Z10std_kernelPfS_S_:
.quad _Z25__device_stub__std_kernelPfS_S_
.size _Z10std_kernelPfS_S_, 8
.type _Z13reduce_kernelPfS_S_,@object # @_Z13reduce_kernelPfS_S_
.globl _Z13reduce_kernelPfS_S_
.p2align 3, 0x0
_Z13reduce_kernelPfS_S_:
.quad _Z28__device_stub__reduce_kernelPfS_S_
.size _Z13reduce_kernelPfS_S_, 8
.type _Z11corr_kernelPfS_,@object # @_Z11corr_kernelPfS_
.globl _Z11corr_kernelPfS_
.p2align 3, 0x0
_Z11corr_kernelPfS_:
.quad _Z26__device_stub__corr_kernelPfS_
.size _Z11corr_kernelPfS_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "GPU Runtime: %0.6lfs\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CPU Runtime: %0.6lfs\n"
.size .L.str.5, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11mean_kernelPfS_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10std_kernelPfS_S_"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13reduce_kernelPfS_S_"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11corr_kernelPfS_"
.size .L__unnamed_4, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mean_kernelPfS_
.addrsig_sym _Z25__device_stub__std_kernelPfS_S_
.addrsig_sym _Z28__device_stub__reduce_kernelPfS_S_
.addrsig_sym _Z26__device_stub__corr_kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mean_kernelPfS_
.addrsig_sym _Z10std_kernelPfS_S_
.addrsig_sym _Z13reduce_kernelPfS_S_
.addrsig_sym _Z11corr_kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define TB 128
#define GS(x) (((x) - 1) / TB + 1)
__global__ void add_(float *input, float value, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
input[id] = input[id] + value;
}
} | code for sm_80
Function : _Z4add_Pffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, c[0x0][0x168] ; /* 0x00005a0000057621 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define TB 128
#define GS(x) (((x) - 1) / TB + 1)
__global__ void add_(float *input, float value, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
input[id] = input[id] + value;
}
} | .file "tmpxft_00199551_00000000-6_add_.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4add_PffiPffi
.type _Z25__device_stub__Z4add_PffiPffi, @function
_Z25__device_stub__Z4add_PffiPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4add_Pffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4add_PffiPffi, .-_Z25__device_stub__Z4add_PffiPffi
.globl _Z4add_Pffi
.type _Z4add_Pffi, @function
_Z4add_Pffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4add_PffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4add_Pffi, .-_Z4add_Pffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4add_Pffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add_Pffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define TB 128
#define GS(x) (((x) - 1) / TB + 1)
__global__ void add_(float *input, float value, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
input[id] = input[id] + value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define TB 128
#define GS(x) (((x) - 1) / TB + 1)
__global__ void add_(float *input, float value, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
input[id] = input[id] + value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define TB 128
#define GS(x) (((x) - 1) / TB + 1)
__global__ void add_(float *input, float value, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
input[id] = input[id] + value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add_Pffi
.globl _Z4add_Pffi
.p2align 8
.type _Z4add_Pffi,@function
_Z4add_Pffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add_Pffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4add_Pffi, .Lfunc_end0-_Z4add_Pffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add_Pffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4add_Pffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define TB 128
#define GS(x) (((x) - 1) / TB + 1)
__global__ void add_(float *input, float value, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
input[id] = input[id] + value;
}
} | .text
.file "add_.hip"
.globl _Z19__device_stub__add_Pffi # -- Begin function _Z19__device_stub__add_Pffi
.p2align 4, 0x90
.type _Z19__device_stub__add_Pffi,@function
_Z19__device_stub__add_Pffi: # @_Z19__device_stub__add_Pffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4add_Pffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__add_Pffi, .Lfunc_end0-_Z19__device_stub__add_Pffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add_Pffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4add_Pffi,@object # @_Z4add_Pffi
.section .rodata,"a",@progbits
.globl _Z4add_Pffi
.p2align 3, 0x0
_Z4add_Pffi:
.quad _Z19__device_stub__add_Pffi
.size _Z4add_Pffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4add_Pffi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__add_Pffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4add_Pffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4add_Pffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, c[0x0][0x168] ; /* 0x00005a0000057621 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add_Pffi
.globl _Z4add_Pffi
.p2align 8
.type _Z4add_Pffi,@function
_Z4add_Pffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add_Pffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4add_Pffi, .Lfunc_end0-_Z4add_Pffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add_Pffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4add_Pffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199551_00000000-6_add_.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4add_PffiPffi
.type _Z25__device_stub__Z4add_PffiPffi, @function
_Z25__device_stub__Z4add_PffiPffi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4add_Pffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4add_PffiPffi, .-_Z25__device_stub__Z4add_PffiPffi
.globl _Z4add_Pffi
.type _Z4add_Pffi, @function
_Z4add_Pffi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4add_PffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4add_Pffi, .-_Z4add_Pffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4add_Pffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add_Pffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_.hip"
.globl _Z19__device_stub__add_Pffi # -- Begin function _Z19__device_stub__add_Pffi
.p2align 4, 0x90
.type _Z19__device_stub__add_Pffi,@function
_Z19__device_stub__add_Pffi: # @_Z19__device_stub__add_Pffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4add_Pffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__add_Pffi, .Lfunc_end0-_Z19__device_stub__add_Pffi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add_Pffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4add_Pffi,@object # @_Z4add_Pffi
.section .rodata,"a",@progbits
.globl _Z4add_Pffi
.p2align 3, 0x0
_Z4add_Pffi:
.quad _Z19__device_stub__add_Pffi
.size _Z4add_Pffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4add_Pffi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__add_Pffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4add_Pffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Program to show the COMPUTE CAPABILITY of the current device
*
* Version: Jul 2021
*/
#include <stdio.h>
//#define CURRENT_DEVICE 1
#define EXIT_SUCCESSFULLY 0
#define EXIT_ERROR -1
int main(int argc, char** argv)
{
cudaError_t resultMajor, resultMinor;
int device, computeCapabilityMayor, computeCapabilityMinor;
//cudaSetDevice(CURRENT_DEVICE);
cudaGetDevice(&device);
resultMajor = cudaDeviceGetAttribute(&computeCapabilityMayor, cudaDevAttrComputeCapabilityMajor, device);
resultMinor = cudaDeviceGetAttribute(&computeCapabilityMinor, cudaDevAttrComputeCapabilityMinor, device);
if (resultMajor != cudaSuccess || resultMinor != cudaSuccess)
return EXIT_ERROR;
printf("%d.%d\n",computeCapabilityMayor,computeCapabilityMinor);
return EXIT_SUCCESSFULLY;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Program to show the COMPUTE CAPABILITY of the current device
*
* Version: Jul 2021
*/
#include <stdio.h>
//#define CURRENT_DEVICE 1
#define EXIT_SUCCESSFULLY 0
#define EXIT_ERROR -1
int main(int argc, char** argv)
{
cudaError_t resultMajor, resultMinor;
int device, computeCapabilityMayor, computeCapabilityMinor;
//cudaSetDevice(CURRENT_DEVICE);
cudaGetDevice(&device);
resultMajor = cudaDeviceGetAttribute(&computeCapabilityMayor, cudaDevAttrComputeCapabilityMajor, device);
resultMinor = cudaDeviceGetAttribute(&computeCapabilityMinor, cudaDevAttrComputeCapabilityMinor, device);
if (resultMajor != cudaSuccess || resultMinor != cudaSuccess)
return EXIT_ERROR;
printf("%d.%d\n",computeCapabilityMayor,computeCapabilityMinor);
return EXIT_SUCCESSFULLY;
} | .file "tmpxft_000b2406_00000000-6_compute_capability.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d.%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
movl 12(%rsp), %edx
movl $75, %esi
call cudaDeviceGetAttribute@PLT
movl %eax, %ebx
leaq 20(%rsp), %rdi
movl 12(%rsp), %edx
movl $76, %esi
call cudaDeviceGetAttribute@PLT
orl %eax, %ebx
jne .L6
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L3:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L8
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl $-1, %eax
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Program to show the COMPUTE CAPABILITY of the current device
*
* Version: Jul 2021
*/
#include <stdio.h>
//#define CURRENT_DEVICE 1
#define EXIT_SUCCESSFULLY 0
#define EXIT_ERROR -1
int main(int argc, char** argv)
{
cudaError_t resultMajor, resultMinor;
int device, computeCapabilityMayor, computeCapabilityMinor;
//cudaSetDevice(CURRENT_DEVICE);
cudaGetDevice(&device);
resultMajor = cudaDeviceGetAttribute(&computeCapabilityMayor, cudaDevAttrComputeCapabilityMajor, device);
resultMinor = cudaDeviceGetAttribute(&computeCapabilityMinor, cudaDevAttrComputeCapabilityMinor, device);
if (resultMajor != cudaSuccess || resultMinor != cudaSuccess)
return EXIT_ERROR;
printf("%d.%d\n",computeCapabilityMayor,computeCapabilityMinor);
return EXIT_SUCCESSFULLY;
} | /*
* Program to show the COMPUTE CAPABILITY of the current device
*
* Version: Jul 2021
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
//#define CURRENT_DEVICE 1
#define EXIT_SUCCESSFULLY 0
#define EXIT_ERROR -1
int main(int argc, char** argv)
{
hipError_t resultMajor, resultMinor;
int device, computeCapabilityMayor, computeCapabilityMinor;
//cudaSetDevice(CURRENT_DEVICE);
hipGetDevice(&device);
resultMajor = hipDeviceGetAttribute(&computeCapabilityMayor, hipDeviceAttributeComputeCapabilityMajor, device);
resultMinor = hipDeviceGetAttribute(&computeCapabilityMinor, hipDeviceAttributeComputeCapabilityMinor, device);
if (resultMajor != hipSuccess || resultMinor != hipSuccess)
return EXIT_ERROR;
printf("%d.%d\n",computeCapabilityMayor,computeCapabilityMinor);
return EXIT_SUCCESSFULLY;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Program to show the COMPUTE CAPABILITY of the current device
*
* Version: Jul 2021
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
//#define CURRENT_DEVICE 1
#define EXIT_SUCCESSFULLY 0
#define EXIT_ERROR -1
int main(int argc, char** argv)
{
hipError_t resultMajor, resultMinor;
int device, computeCapabilityMayor, computeCapabilityMinor;
//cudaSetDevice(CURRENT_DEVICE);
hipGetDevice(&device);
resultMajor = hipDeviceGetAttribute(&computeCapabilityMayor, hipDeviceAttributeComputeCapabilityMajor, device);
resultMinor = hipDeviceGetAttribute(&computeCapabilityMinor, hipDeviceAttributeComputeCapabilityMinor, device);
if (resultMajor != hipSuccess || resultMinor != hipSuccess)
return EXIT_ERROR;
printf("%d.%d\n",computeCapabilityMayor,computeCapabilityMinor);
return EXIT_SUCCESSFULLY;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Program to show the COMPUTE CAPABILITY of the current device
*
* Version: Jul 2021
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
//#define CURRENT_DEVICE 1
#define EXIT_SUCCESSFULLY 0
#define EXIT_ERROR -1
int main(int argc, char** argv)
{
hipError_t resultMajor, resultMinor;
int device, computeCapabilityMayor, computeCapabilityMinor;
//cudaSetDevice(CURRENT_DEVICE);
hipGetDevice(&device);
resultMajor = hipDeviceGetAttribute(&computeCapabilityMayor, hipDeviceAttributeComputeCapabilityMajor, device);
resultMinor = hipDeviceGetAttribute(&computeCapabilityMinor, hipDeviceAttributeComputeCapabilityMinor, device);
if (resultMajor != hipSuccess || resultMinor != hipSuccess)
return EXIT_ERROR;
printf("%d.%d\n",computeCapabilityMayor,computeCapabilityMinor);
return EXIT_SUCCESSFULLY;
} | .text
.file "compute_capability.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %edx
leaq 20(%rsp), %rdi
movl $23, %esi
callq hipDeviceGetAttribute
movl %eax, %ebp
movl 12(%rsp), %edx
leaq 16(%rsp), %rdi
movl $61, %esi
callq hipDeviceGetAttribute
movl $-1, %ebx
orl %ebp, %eax
jne .LBB0_2
# %bb.1:
movl 20(%rsp), %esi
movl 16(%rsp), %edx
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.LBB0_2:
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d.%d\n"
.size .L.str, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2406_00000000-6_compute_capability.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d.%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 16(%rsp), %rdi
movl 12(%rsp), %edx
movl $75, %esi
call cudaDeviceGetAttribute@PLT
movl %eax, %ebx
leaq 20(%rsp), %rdi
movl 12(%rsp), %edx
movl $76, %esi
call cudaDeviceGetAttribute@PLT
orl %eax, %ebx
jne .L6
movl 20(%rsp), %ecx
movl 16(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L3:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L8
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl $-1, %eax
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "compute_capability.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %edx
leaq 20(%rsp), %rdi
movl $23, %esi
callq hipDeviceGetAttribute
movl %eax, %ebp
movl 12(%rsp), %edx
leaq 16(%rsp), %rdi
movl $61, %esi
callq hipDeviceGetAttribute
movl $-1, %ebx
orl %ebp, %eax
jne .LBB0_2
# %bb.1:
movl 20(%rsp), %esi
movl 16(%rsp), %edx
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.LBB0_2:
movl %ebx, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d.%d\n"
.size .L.str, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "gMat.cuh"
#include "real.h"
#include <assert.h>
#include <iostream>
void basicMultTest(int w){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
int mem=2*w*w*sizeof(real);
prod(A,B,C,mem);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
void basicMultTestv2(int w, int s){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
prodv2(A, B, C, w, s);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
int main(){
basicMultTest(1);
/* basicMultTest(1);
basicMultTest(2);
basicMultTestv2(16,1);
basicMultTestv2(1,2);
basicMultTestv2(1,3);
basicMultTestv2(2,1);
basicMultTestv2(2,2);
*/
std::cout << "SUCCESS!" << std::endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "gMat.cuh"
#include "real.h"
#include <assert.h>
#include <iostream>
void basicMultTest(int w){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
int mem=2*w*w*sizeof(real);
prod(A,B,C,mem);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
void basicMultTestv2(int w, int s){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
prodv2(A, B, C, w, s);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
int main(){
basicMultTest(1);
/* basicMultTest(1);
basicMultTest(2);
basicMultTestv2(16,1);
basicMultTestv2(1,2);
basicMultTestv2(1,3);
basicMultTestv2(2,1);
basicMultTestv2(2,2);
*/
std::cout << "SUCCESS!" << std::endl;
} | .file "tmpxft_001984e3_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4627:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4627:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4650:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4650:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4967:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L8:
ret
.cfi_endproc
.LFE4967:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .text._ZNSt12_Vector_baseIfSaIfEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIfSaIfEED2Ev
.type _ZNSt12_Vector_baseIfSaIfEED2Ev, @function
_ZNSt12_Vector_baseIfSaIfEED2Ev:
.LFB5137:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L14
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L14:
ret
.cfi_endproc
.LFE5137:
.size _ZNSt12_Vector_baseIfSaIfEED2Ev, .-_ZNSt12_Vector_baseIfSaIfEED2Ev
.weak _ZNSt12_Vector_baseIfSaIfEED1Ev
.set _ZNSt12_Vector_baseIfSaIfEED1Ev,_ZNSt12_Vector_baseIfSaIfEED2Ev
.text
.globl _Z13basicMultTesti
.type _Z13basicMultTesti, @function
_Z13basicMultTesti:
.LFB4619:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4619
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $288, %rsp
.cfi_def_cfa_offset 336
movl %edi, %r13d
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
movq %rax, (%rsp)
leaq 16(%rax), %rax
movq %rax, 16(%rsp)
movabsq $4611686019492741120, %rbx
movq %rbx, 0(%rbp)
movabsq $4647714816524288000, %rcx
movq %rcx, 8(%rbp)
movq %rax, 8(%rsp)
movss .LC0(%rip), %xmm0
movss %xmm0, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movss %xmm0, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm0, 244(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl $24, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 24(%rax), %rax
movq %rax, 48(%rsp)
movdqa 224(%rsp), %xmm1
movups %xmm1, (%rbx)
movq 240(%rsp), %rdx
movq %rdx, 16(%rbx)
movq %rax, 40(%rsp)
movl $0x00000000, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movl $0x00000000, 236(%rsp)
movl $0x00000000, 240(%rsp)
movl $0x00000000, 244(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $24, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
jmp .L61
.L54:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L61:
movq %rax, %r12
movq %rax, 64(%rsp)
leaq 24(%rax), %rax
movq %rax, 80(%rsp)
movdqa 224(%rsp), %xmm2
movups %xmm2, (%r12)
movq 240(%rsp), %rdx
movq %rdx, 16(%r12)
movq %rax, 72(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $16, %edi
.LEHB4:
call _Znwm@PLT
.LEHE4:
jmp .L62
.L53:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L23:
movq %rsp, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L62:
movq %rax, 96(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu 0(%rbp), %xmm3
movups %xmm3, (%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $2, %edx
.LEHB5:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE5:
jmp .L63
.L55:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L26:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L23
.L63:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L27
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L27:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB6:
call _Znwm@PLT
.LEHE6:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%rbx), %xmm4
movups %xmm4, (%rax)
movq 16(%rbx), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB7:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE7:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L28
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L28:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB8:
call _Znwm@PLT
.LEHE8:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%r12), %xmm5
movups %xmm5, (%rax)
movq 16(%r12), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB9:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE9:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L29
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L29:
imull %r13d, %r13d
leal 0(,%r13,8), %ecx
leaq 224(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 128(%rsp), %rdi
.LEHB10:
call _Z4prodRK4gMatS1_RS_i@PLT
leaq 224(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L64
cmpb $0, 56(%r14)
je .L32
movzbl 67(%r14), %esi
.L33:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L65
.L64:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L52:
endbr64
movq %rax, %rbx
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L42
.L66:
call __stack_chk_fail@PLT
.L32:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L33
.L65:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 128(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 176(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 224(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
.LEHE10:
movq 240(%rsp), %rdi
leaq 256(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 256(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L35
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L35:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L36
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L36:
movl $24, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movl $24, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $16, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L38:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L26
.L48:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L40:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L38
.L50:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L42:
leaq 192(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L40
.L51:
endbr64
movq %rax, %rbx
jmp .L42
.L49:
endbr64
movq %rax, %rbx
jmp .L40
.L47:
endbr64
movq %rax, %rbx
jmp .L38
.L44:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4619:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4619:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4619-.LLSDACSB4619
.LLSDACSB4619:
.uleb128 .LEHB0-.LFB4619
.uleb128 .LEHE0-.LEHB0
.uleb128 .L54-.LFB4619
.uleb128 0
.uleb128 .LEHB1-.LFB4619
.uleb128 .LEHE1-.LEHB1
.uleb128 .L53-.LFB4619
.uleb128 0
.uleb128 .LEHB2-.LFB4619
.uleb128 .LEHE2-.LEHB2
.uleb128 .L55-.LFB4619
.uleb128 0
.uleb128 .LEHB3-.LFB4619
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4619
.uleb128 .LEHE4-.LEHB4
.uleb128 .L47-.LFB4619
.uleb128 0
.uleb128 .LEHB5-.LFB4619
.uleb128 .LEHE5-.LEHB5
.uleb128 .L46-.LFB4619
.uleb128 0
.uleb128 .LEHB6-.LFB4619
.uleb128 .LEHE6-.LEHB6
.uleb128 .L49-.LFB4619
.uleb128 0
.uleb128 .LEHB7-.LFB4619
.uleb128 .LEHE7-.LEHB7
.uleb128 .L48-.LFB4619
.uleb128 0
.uleb128 .LEHB8-.LFB4619
.uleb128 .LEHE8-.LEHB8
.uleb128 .L51-.LFB4619
.uleb128 0
.uleb128 .LEHB9-.LFB4619
.uleb128 .LEHE9-.LEHB9
.uleb128 .L50-.LFB4619
.uleb128 0
.uleb128 .LEHB10-.LFB4619
.uleb128 .LEHE10-.LEHB10
.uleb128 .L52-.LFB4619
.uleb128 0
.uleb128 .LEHB11-.LFB4619
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE4619:
.text
.size _Z13basicMultTesti, .-_Z13basicMultTesti
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "SUCCESS!"
.text
.globl main
.type main, @function
main:
.LFB4624:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call _Z13basicMultTesti
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4624:
.size main, .-main
.globl _Z15basicMultTestv2ii
.type _Z15basicMultTestv2ii, @function
_Z15basicMultTestv2ii:
.LFB4623:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4623
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $288, %rsp
.cfi_def_cfa_offset 336
movl %edi, %r13d
movl %esi, %r14d
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB12:
call _Znwm@PLT
.LEHE12:
movq %rax, %rbp
movq %rax, (%rsp)
leaq 16(%rax), %rax
movq %rax, 16(%rsp)
movabsq $4611686019492741120, %rcx
movq %rcx, 0(%rbp)
movabsq $4647714816524288000, %rbx
movq %rbx, 8(%rbp)
movq %rax, 8(%rsp)
movss .LC0(%rip), %xmm0
movss %xmm0, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movss %xmm0, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm0, 244(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl $24, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 24(%rax), %rax
movq %rax, 48(%rsp)
movdqa 224(%rsp), %xmm1
movups %xmm1, (%rbx)
movq 240(%rsp), %rdx
movq %rdx, 16(%rbx)
movq %rax, 40(%rsp)
movl $0x00000000, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movl $0x00000000, 236(%rsp)
movl $0x00000000, 240(%rsp)
movl $0x00000000, 244(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $24, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
jmp .L114
.L107:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L73:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L114:
movq %rax, %r12
movq %rax, 64(%rsp)
leaq 24(%rax), %rax
movq %rax, 80(%rsp)
movdqa 224(%rsp), %xmm2
movups %xmm2, (%r12)
movq 240(%rsp), %rdx
movq %rdx, 16(%r12)
movq %rax, 72(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $16, %edi
.LEHB16:
call _Znwm@PLT
.LEHE16:
jmp .L115
.L106:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L76:
movq %rsp, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L97
call __stack_chk_fail@PLT
.L115:
movq %rax, 96(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu 0(%rbp), %xmm3
movups %xmm3, (%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $2, %edx
.LEHB17:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE17:
jmp .L116
.L108:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L79:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L76
.L116:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L80
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L80:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB18:
call _Znwm@PLT
.LEHE18:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%rbx), %xmm4
movups %xmm4, (%rax)
movq 16(%rbx), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB19:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE19:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L81
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L81:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB20:
call _Znwm@PLT
.LEHE20:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%r12), %xmm5
movups %xmm5, (%rax)
movq 16(%r12), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB21:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE21:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L82
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L82:
leaq 224(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 128(%rsp), %rdi
movl %r14d, %r8d
movl %r13d, %ecx
.LEHB22:
call _Z6prodv2RK4gMatS1_RS_ii@PLT
leaq 224(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L117
cmpb $0, 56(%r14)
je .L85
movzbl 67(%r14), %esi
.L86:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L118
.L117:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L119
call _ZSt16__throw_bad_castv@PLT
.L105:
endbr64
movq %rax, %rbx
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L95
.L119:
call __stack_chk_fail@PLT
.L85:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L86
.L118:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 128(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 176(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 224(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
.LEHE22:
movq 240(%rsp), %rdi
leaq 256(%rsp), %rax
cmpq %rax, %rdi
je .L87
movq 256(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L87:
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L88
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L88:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L89
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L89:
movl $24, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movl $24, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $16, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L120
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L99:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L91:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L79
.L101:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L93:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L91
.L103:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L95:
leaq 192(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L93
.L104:
endbr64
movq %rax, %rbx
jmp .L95
.L102:
endbr64
movq %rax, %rbx
jmp .L93
.L100:
endbr64
movq %rax, %rbx
jmp .L91
.L97:
movq %rbx, %rdi
.LEHB23:
call _Unwind_Resume@PLT
.LEHE23:
.L120:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4623:
.section .gcc_except_table
.LLSDA4623:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4623-.LLSDACSB4623
.LLSDACSB4623:
.uleb128 .LEHB12-.LFB4623
.uleb128 .LEHE12-.LEHB12
.uleb128 .L107-.LFB4623
.uleb128 0
.uleb128 .LEHB13-.LFB4623
.uleb128 .LEHE13-.LEHB13
.uleb128 .L106-.LFB4623
.uleb128 0
.uleb128 .LEHB14-.LFB4623
.uleb128 .LEHE14-.LEHB14
.uleb128 .L108-.LFB4623
.uleb128 0
.uleb128 .LEHB15-.LFB4623
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.uleb128 .LEHB16-.LFB4623
.uleb128 .LEHE16-.LEHB16
.uleb128 .L100-.LFB4623
.uleb128 0
.uleb128 .LEHB17-.LFB4623
.uleb128 .LEHE17-.LEHB17
.uleb128 .L99-.LFB4623
.uleb128 0
.uleb128 .LEHB18-.LFB4623
.uleb128 .LEHE18-.LEHB18
.uleb128 .L102-.LFB4623
.uleb128 0
.uleb128 .LEHB19-.LFB4623
.uleb128 .LEHE19-.LEHB19
.uleb128 .L101-.LFB4623
.uleb128 0
.uleb128 .LEHB20-.LFB4623
.uleb128 .LEHE20-.LEHB20
.uleb128 .L104-.LFB4623
.uleb128 0
.uleb128 .LEHB21-.LFB4623
.uleb128 .LEHE21-.LEHB21
.uleb128 .L103-.LFB4623
.uleb128 0
.uleb128 .LEHB22-.LFB4623
.uleb128 .LEHE22-.LEHB22
.uleb128 .L105-.LFB4623
.uleb128 0
.uleb128 .LEHB23-.LFB4623
.uleb128 .LEHE23-.LEHB23
.uleb128 0
.uleb128 0
.LLSDACSE4623:
.text
.size _Z15basicMultTestv2ii, .-_Z15basicMultTestv2ii
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "gMat.cuh"
#include "real.h"
#include <assert.h>
#include <iostream>
void basicMultTest(int w){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
int mem=2*w*w*sizeof(real);
prod(A,B,C,mem);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
void basicMultTestv2(int w, int s){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
prodv2(A, B, C, w, s);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
int main(){
basicMultTest(1);
/* basicMultTest(1);
basicMultTest(2);
basicMultTestv2(16,1);
basicMultTestv2(1,2);
basicMultTestv2(1,3);
basicMultTestv2(2,1);
basicMultTestv2(2,2);
*/
std::cout << "SUCCESS!" << std::endl;
} | #include <hip/hip_runtime.h>
#include "gMat.cuh"
#include "real.h"
#include <assert.h>
#include <iostream>
void basicMultTest(int w){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
int mem=2*w*w*sizeof(real);
prod(A,B,C,mem);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
void basicMultTestv2(int w, int s){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
prodv2(A, B, C, w, s);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
int main(){
basicMultTest(1);
/* basicMultTest(1);
basicMultTest(2);
basicMultTestv2(16,1);
basicMultTestv2(1,2);
basicMultTestv2(1,3);
basicMultTestv2(2,1);
basicMultTestv2(2,2);
*/
std::cout << "SUCCESS!" << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "gMat.cuh"
#include "real.h"
#include <assert.h>
#include <iostream>
void basicMultTest(int w){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
int mem=2*w*w*sizeof(real);
prod(A,B,C,mem);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
void basicMultTestv2(int w, int s){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
prodv2(A, B, C, w, s);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
int main(){
basicMultTest(1);
/* basicMultTest(1);
basicMultTest(2);
basicMultTestv2(16,1);
basicMultTestv2(1,2);
basicMultTestv2(1,3);
basicMultTestv2(2,1);
basicMultTestv2(2,2);
*/
std::cout << "SUCCESS!" << std::endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "gMat.cuh"
#include "real.h"
#include <assert.h>
#include <iostream>
void basicMultTest(int w){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
int mem=2*w*w*sizeof(real);
prod(A,B,C,mem);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
void basicMultTestv2(int w, int s){
std::vector<real> adat={1,2,3,4};
std::vector<real> bdat={2,0,0,2,0,2};
std::vector<real> cdat={0,0,0,0,0,0};
gMat A{adat,2,2};//A= [1 2; 3 4]
gMat B{bdat,2,3};//B= [2 0 0; 2 0 2]
gMat C{cdat,2,3};
prodv2(A, B, C, w, s);
std::cout << C << std::endl;
assert( C.entry(0,0) == 6 );
assert(C.entry(0,1) == 0 );
assert(C.entry(0,2) == 4 );
assert(C.entry(1,0) == 14 );
assert(C.entry(1,1) == 0 );
assert(C.entry(1,2) == 8 );
A.cleanup();
B.cleanup();
C.cleanup();
}
int main(){
basicMultTest(1);
/* basicMultTest(1);
basicMultTest(2);
basicMultTestv2(16,1);
basicMultTestv2(1,2);
basicMultTestv2(1,3);
basicMultTestv2(2,1);
basicMultTestv2(2,2);
*/
std::cout << "SUCCESS!" << std::endl;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13basicMultTesti
.LCPI0_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.text
.globl _Z13basicMultTesti
.p2align 4, 0x90
.type _Z13basicMultTesti,@function
_Z13basicMultTesti: # @_Z13basicMultTesti
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movups %xmm0, (%rax)
.Ltmp0:
movl $24, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit24
movq %rax, %r14
movups .Lconstinit.2(%rip), %xmm0
movups %xmm0, (%rax)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 16(%r14)
.Ltmp3:
movl $24, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit29
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movq $0, 16(%rax)
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
movl $16, %edi
callq _Znwm
.Ltmp7:
# %bb.3: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rax, 64(%rsp)
movq %rax, 72(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 80(%rsp)
movups (%rbx), %xmm0
movups %xmm0, (%rax)
movq %rcx, 72(%rsp)
.Ltmp9:
leaq 184(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $2, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp10:
# %bb.4:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_6
# %bb.5:
callq _ZdlPv
.LBB0_6: # %_ZNSt6vectorIfSaIfEED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp12:
movl $24, %edi
callq _Znwm
.Ltmp13:
# %bb.7: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i35
movq %rax, 32(%rsp)
movq %rax, 40(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 48(%rsp)
movq 16(%r14), %rdx
movq %rdx, 16(%rax)
movups (%r14), %xmm0
movups %xmm0, (%rax)
movq %rcx, 40(%rsp)
.Ltmp15:
leaq 136(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp16:
# %bb.8:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_10
# %bb.9:
callq _ZdlPv
.LBB0_10: # %_ZNSt6vectorIfSaIfEED2Ev.exit44
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp18:
movl $24, %edi
callq _Znwm
.Ltmp19:
# %bb.11: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i47
movq %rax, (%rsp)
movq %rax, 8(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 16(%rsp)
movq 16(%r15), %rdx
movq %rdx, 16(%rax)
movups (%r15), %xmm0
movups %xmm0, (%rax)
movq %rcx, 8(%rsp)
.Ltmp21:
leaq 88(%rsp), %rdi
movq %rsp, %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp22:
# %bb.12:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
.LBB0_14: # %_ZNSt6vectorIfSaIfEED2Ev.exit56
imull %ebp, %ebp
shll $3, %ebp
.Ltmp24:
leaq 184(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 88(%rsp), %rdx
movl %ebp, %ecx
callq _Z4prodRK4gMatS1_RS_i
.Ltmp25:
# %bb.15:
.Ltmp26:
leaq 88(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZlsRSoR4gMat
.Ltmp27:
# %bb.16:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB0_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB0_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB0_23
.LBB0_21:
.Ltmp28:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.22: # %.noexc102
movq (%r13), %rax
.Ltmp30:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB0_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp32:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.24: # %.noexc104
.Ltmp34:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit
.Ltmp36:
leaq 184(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp37:
# %bb.26:
.Ltmp38:
leaq 136(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp39:
# %bb.27:
.Ltmp40:
leaq 88(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp41:
# %bb.28:
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_30
# %bb.29: # %.critedge.i.i.i
callq _ZdlPv
.LBB0_30: # %_ZN4gMatD2Ev.exit
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_32
# %bb.31: # %.critedge.i.i.i58
callq _ZdlPv
.LBB0_32: # %_ZN4gMatD2Ev.exit60
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_34
# %bb.33: # %.critedge.i.i.i61
callq _ZdlPv
.LBB0_34: # %_ZN4gMatD2Ev.exit63
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 288
.Ltmp42:
callq _ZSt16__throw_bad_castv
.Ltmp43:
# %bb.18: # %.noexc101
.LBB0_40:
.Ltmp23:
movq %rax, %r12
movq (%rsp), %rdi
testq %rdi, %rdi
jne .LBB0_42
jmp .LBB0_43
.LBB0_39:
.Ltmp20:
movq %rax, %r12
jmp .LBB0_43
.LBB0_38:
.Ltmp17:
movq %rax, %r12
movq 32(%rsp), %rdi
testq %rdi, %rdi
jne .LBB0_44
jmp .LBB0_45
.LBB0_37:
.Ltmp14:
movq %rax, %r12
jmp .LBB0_45
.LBB0_36:
.Ltmp11:
movq %rax, %r12
movq 64(%rsp), %rdi
testq %rdi, %rdi
jne .LBB0_46
jmp .LBB0_47
.LBB0_35:
.Ltmp8:
movq %rax, %r12
jmp .LBB0_47
.LBB0_51: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i26
.Ltmp5:
movq %rax, %r12
jmp .LBB0_48
.LBB0_50: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i21
.Ltmp2:
movq %rax, %r12
jmp .LBB0_49
.LBB0_41:
.Ltmp44:
movq %rax, %r12
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_43
.LBB0_42: # %.critedge.i.i.i82
callq _ZdlPv
.LBB0_43: # %_ZNSt6vectorIfSaIfEED2Ev.exit81
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_45
.LBB0_44: # %.critedge.i.i.i85
callq _ZdlPv
.LBB0_45: # %_ZNSt6vectorIfSaIfEED2Ev.exit78
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_47
.LBB0_46: # %.critedge.i.i.i88
callq _ZdlPv
.LBB0_47: # %_ZNSt6vectorIfSaIfEED2Ev.exit75
movq %r15, %rdi
callq _ZdlPv
.LBB0_48: # %_ZNSt6vectorIfSaIfEED2Ev.exit96
movq %r14, %rdi
callq _ZdlPv
.LBB0_49: # %_ZNSt6vectorIfSaIfEED2Ev.exit99
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z13basicMultTesti, .Lfunc_end0-_Z13basicMultTesti
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp43-.Ltmp24 # Call between .Ltmp24 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end0-.Ltmp43 # Call between .Ltmp43 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15basicMultTestv2ii
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.text
.globl _Z15basicMultTestv2ii
.p2align 4, 0x90
.type _Z15basicMultTestv2ii,@function
_Z15basicMultTestv2ii: # @_Z15basicMultTestv2ii
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r12d
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movups %xmm0, (%rax)
.Ltmp45:
movl $24, %edi
callq _Znwm
.Ltmp46:
# %bb.1: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit23
movq %rax, %r14
movups .Lconstinit.2(%rip), %xmm0
movups %xmm0, (%rax)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 16(%r14)
.Ltmp48:
movl $24, %edi
callq _Znwm
.Ltmp49:
# %bb.2: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit28
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movq $0, 16(%rax)
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp51:
movl $16, %edi
callq _Znwm
.Ltmp52:
# %bb.3: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rax, 64(%rsp)
movq %rax, 72(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 80(%rsp)
movups (%rbx), %xmm0
movups %xmm0, (%rax)
movq %rcx, 72(%rsp)
.Ltmp54:
leaq 184(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $2, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp55:
# %bb.4:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIfSaIfEED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp57:
movl $24, %edi
callq _Znwm
.Ltmp58:
# %bb.7: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i34
movq %rax, 32(%rsp)
movq %rax, 40(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 48(%rsp)
movq 16(%r14), %rdx
movq %rdx, 16(%rax)
movups (%r14), %xmm0
movups %xmm0, (%rax)
movq %rcx, 40(%rsp)
.Ltmp60:
leaq 136(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp61:
# %bb.8:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_10
# %bb.9:
callq _ZdlPv
.LBB1_10: # %_ZNSt6vectorIfSaIfEED2Ev.exit43
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp63:
movl $24, %edi
callq _Znwm
.Ltmp64:
# %bb.11: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i46
movq %rax, (%rsp)
movq %rax, 8(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 16(%rsp)
movq 16(%r15), %rdx
movq %rdx, 16(%rax)
movups (%r15), %xmm0
movups %xmm0, (%rax)
movq %rcx, 8(%rsp)
.Ltmp66:
leaq 88(%rsp), %rdi
movq %rsp, %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp67:
# %bb.12:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB1_14
# %bb.13:
callq _ZdlPv
.LBB1_14: # %_ZNSt6vectorIfSaIfEED2Ev.exit55
.Ltmp69:
leaq 184(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 88(%rsp), %rdx
movl %r12d, %ecx
movl %ebp, %r8d
callq _Z6prodv2RK4gMatS1_RS_ii
.Ltmp70:
# %bb.15:
.Ltmp71:
leaq 88(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZlsRSoR4gMat
.Ltmp72:
# %bb.16:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB1_23
.LBB1_21:
.Ltmp73:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp74:
# %bb.22: # %.noexc101
movq (%r13), %rax
.Ltmp75:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp76:
.LBB1_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp77:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp78:
# %bb.24: # %.noexc103
.Ltmp79:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp80:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit
.Ltmp81:
leaq 184(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp82:
# %bb.26:
.Ltmp83:
leaq 136(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp84:
# %bb.27:
.Ltmp85:
leaq 88(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp86:
# %bb.28:
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_30
# %bb.29: # %.critedge.i.i.i
callq _ZdlPv
.LBB1_30: # %_ZN4gMatD2Ev.exit
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_32
# %bb.31: # %.critedge.i.i.i57
callq _ZdlPv
.LBB1_32: # %_ZN4gMatD2Ev.exit59
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_34
# %bb.33: # %.critedge.i.i.i60
callq _ZdlPv
.LBB1_34: # %_ZN4gMatD2Ev.exit62
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 288
.Ltmp87:
callq _ZSt16__throw_bad_castv
.Ltmp88:
# %bb.18: # %.noexc100
.LBB1_40:
.Ltmp68:
movq %rax, %r12
movq (%rsp), %rdi
testq %rdi, %rdi
jne .LBB1_42
jmp .LBB1_43
.LBB1_39:
.Ltmp65:
movq %rax, %r12
jmp .LBB1_43
.LBB1_38:
.Ltmp62:
movq %rax, %r12
movq 32(%rsp), %rdi
testq %rdi, %rdi
jne .LBB1_44
jmp .LBB1_45
.LBB1_37:
.Ltmp59:
movq %rax, %r12
jmp .LBB1_45
.LBB1_36:
.Ltmp56:
movq %rax, %r12
movq 64(%rsp), %rdi
testq %rdi, %rdi
jne .LBB1_46
jmp .LBB1_47
.LBB1_35:
.Ltmp53:
movq %rax, %r12
jmp .LBB1_47
.LBB1_51: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i25
.Ltmp50:
movq %rax, %r12
jmp .LBB1_48
.LBB1_50: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i20
.Ltmp47:
movq %rax, %r12
jmp .LBB1_49
.LBB1_41:
.Ltmp89:
movq %rax, %r12
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_43
.LBB1_42: # %.critedge.i.i.i81
callq _ZdlPv
.LBB1_43: # %_ZNSt6vectorIfSaIfEED2Ev.exit80
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_45
.LBB1_44: # %.critedge.i.i.i84
callq _ZdlPv
.LBB1_45: # %_ZNSt6vectorIfSaIfEED2Ev.exit77
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_47
.LBB1_46: # %.critedge.i.i.i87
callq _ZdlPv
.LBB1_47: # %_ZNSt6vectorIfSaIfEED2Ev.exit74
movq %r15, %rdi
callq _ZdlPv
.LBB1_48: # %_ZNSt6vectorIfSaIfEED2Ev.exit95
movq %r14, %rdi
callq _ZdlPv
.LBB1_49: # %_ZNSt6vectorIfSaIfEED2Ev.exit98
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z15basicMultTestv2ii, .Lfunc_end1-_Z15basicMultTestv2ii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp45-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp45
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin1 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin1 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp52-.Ltmp51 # Call between .Ltmp51 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin1 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin1 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp58-.Ltmp57 # Call between .Ltmp57 and .Ltmp58
.uleb128 .Ltmp59-.Lfunc_begin1 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp61-.Ltmp60 # Call between .Ltmp60 and .Ltmp61
.uleb128 .Ltmp62-.Lfunc_begin1 # jumps to .Ltmp62
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp64-.Ltmp63 # Call between .Ltmp63 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin1 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin1 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp88-.Ltmp69 # Call between .Ltmp69 and .Ltmp88
.uleb128 .Ltmp89-.Lfunc_begin1 # jumps to .Ltmp89
.byte 0 # On action: cleanup
.uleb128 .Ltmp88-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp88 # Call between .Ltmp88 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $1, %edi
callq _Z13basicMultTesti
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type .Lconstinit.2,@object # @constinit.2
.section .rodata,"a",@progbits
.p2align 2, 0x0
.Lconstinit.2:
.long 0x40000000 # float 2
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x40000000 # float 2
.long 0x00000000 # float 0
.long 0x40000000 # float 2
.size .Lconstinit.2, 24
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "SUCCESS!"
.size .L.str, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001984e3_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4627:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4627:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4650:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4650:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4967:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L8:
ret
.cfi_endproc
.LFE4967:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .text._ZNSt12_Vector_baseIfSaIfEED2Ev,"axG",@progbits,_ZNSt12_Vector_baseIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt12_Vector_baseIfSaIfEED2Ev
.type _ZNSt12_Vector_baseIfSaIfEED2Ev, @function
_ZNSt12_Vector_baseIfSaIfEED2Ev:
.LFB5137:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L14
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L14:
ret
.cfi_endproc
.LFE5137:
.size _ZNSt12_Vector_baseIfSaIfEED2Ev, .-_ZNSt12_Vector_baseIfSaIfEED2Ev
.weak _ZNSt12_Vector_baseIfSaIfEED1Ev
.set _ZNSt12_Vector_baseIfSaIfEED1Ev,_ZNSt12_Vector_baseIfSaIfEED2Ev
.text
.globl _Z13basicMultTesti
.type _Z13basicMultTesti, @function
_Z13basicMultTesti:
.LFB4619:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4619
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $288, %rsp
.cfi_def_cfa_offset 336
movl %edi, %r13d
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %rbp
movq %rax, (%rsp)
leaq 16(%rax), %rax
movq %rax, 16(%rsp)
movabsq $4611686019492741120, %rbx
movq %rbx, 0(%rbp)
movabsq $4647714816524288000, %rcx
movq %rcx, 8(%rbp)
movq %rax, 8(%rsp)
movss .LC0(%rip), %xmm0
movss %xmm0, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movss %xmm0, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm0, 244(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl $24, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 24(%rax), %rax
movq %rax, 48(%rsp)
movdqa 224(%rsp), %xmm1
movups %xmm1, (%rbx)
movq 240(%rsp), %rdx
movq %rdx, 16(%rbx)
movq %rax, 40(%rsp)
movl $0x00000000, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movl $0x00000000, 236(%rsp)
movl $0x00000000, 240(%rsp)
movl $0x00000000, 244(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $24, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
jmp .L61
.L54:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L61:
movq %rax, %r12
movq %rax, 64(%rsp)
leaq 24(%rax), %rax
movq %rax, 80(%rsp)
movdqa 224(%rsp), %xmm2
movups %xmm2, (%r12)
movq 240(%rsp), %rdx
movq %rdx, 16(%r12)
movq %rax, 72(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $16, %edi
.LEHB4:
call _Znwm@PLT
.LEHE4:
jmp .L62
.L53:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L23:
movq %rsp, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L62:
movq %rax, 96(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu 0(%rbp), %xmm3
movups %xmm3, (%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $2, %edx
.LEHB5:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE5:
jmp .L63
.L55:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L26:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L23
.L63:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L27
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L27:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB6:
call _Znwm@PLT
.LEHE6:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%rbx), %xmm4
movups %xmm4, (%rax)
movq 16(%rbx), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB7:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE7:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L28
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L28:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB8:
call _Znwm@PLT
.LEHE8:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%r12), %xmm5
movups %xmm5, (%rax)
movq 16(%r12), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB9:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE9:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L29
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L29:
imull %r13d, %r13d
leal 0(,%r13,8), %ecx
leaq 224(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 128(%rsp), %rdi
.LEHB10:
call _Z4prodRK4gMatS1_RS_i@PLT
leaq 224(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L64
cmpb $0, 56(%r14)
je .L32
movzbl 67(%r14), %esi
.L33:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L65
.L64:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L52:
endbr64
movq %rax, %rbx
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L42
.L66:
call __stack_chk_fail@PLT
.L32:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L33
.L65:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 128(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 176(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 224(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
.LEHE10:
movq 240(%rsp), %rdi
leaq 256(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 256(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L35
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L35:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L36
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L36:
movl $24, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movl $24, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $16, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L38:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L26
.L48:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L40:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L38
.L50:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L42:
leaq 192(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L40
.L51:
endbr64
movq %rax, %rbx
jmp .L42
.L49:
endbr64
movq %rax, %rbx
jmp .L40
.L47:
endbr64
movq %rax, %rbx
jmp .L38
.L44:
movq %rbx, %rdi
.LEHB11:
call _Unwind_Resume@PLT
.LEHE11:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4619:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4619:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4619-.LLSDACSB4619
.LLSDACSB4619:
.uleb128 .LEHB0-.LFB4619
.uleb128 .LEHE0-.LEHB0
.uleb128 .L54-.LFB4619
.uleb128 0
.uleb128 .LEHB1-.LFB4619
.uleb128 .LEHE1-.LEHB1
.uleb128 .L53-.LFB4619
.uleb128 0
.uleb128 .LEHB2-.LFB4619
.uleb128 .LEHE2-.LEHB2
.uleb128 .L55-.LFB4619
.uleb128 0
.uleb128 .LEHB3-.LFB4619
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4619
.uleb128 .LEHE4-.LEHB4
.uleb128 .L47-.LFB4619
.uleb128 0
.uleb128 .LEHB5-.LFB4619
.uleb128 .LEHE5-.LEHB5
.uleb128 .L46-.LFB4619
.uleb128 0
.uleb128 .LEHB6-.LFB4619
.uleb128 .LEHE6-.LEHB6
.uleb128 .L49-.LFB4619
.uleb128 0
.uleb128 .LEHB7-.LFB4619
.uleb128 .LEHE7-.LEHB7
.uleb128 .L48-.LFB4619
.uleb128 0
.uleb128 .LEHB8-.LFB4619
.uleb128 .LEHE8-.LEHB8
.uleb128 .L51-.LFB4619
.uleb128 0
.uleb128 .LEHB9-.LFB4619
.uleb128 .LEHE9-.LEHB9
.uleb128 .L50-.LFB4619
.uleb128 0
.uleb128 .LEHB10-.LFB4619
.uleb128 .LEHE10-.LEHB10
.uleb128 .L52-.LFB4619
.uleb128 0
.uleb128 .LEHB11-.LFB4619
.uleb128 .LEHE11-.LEHB11
.uleb128 0
.uleb128 0
.LLSDACSE4619:
.text
.size _Z13basicMultTesti, .-_Z13basicMultTesti
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "SUCCESS!"
.text
.globl main
.type main, @function
main:
.LFB4624:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $1, %edi
call _Z13basicMultTesti
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4624:
.size main, .-main
.globl _Z15basicMultTestv2ii
.type _Z15basicMultTestv2ii, @function
_Z15basicMultTestv2ii:
.LFB4623:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4623
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $288, %rsp
.cfi_def_cfa_offset 336
movl %edi, %r13d
movl %esi, %r14d
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
.LEHB12:
call _Znwm@PLT
.LEHE12:
movq %rax, %rbp
movq %rax, (%rsp)
leaq 16(%rax), %rax
movq %rax, 16(%rsp)
movabsq $4611686019492741120, %rcx
movq %rcx, 0(%rbp)
movabsq $4647714816524288000, %rbx
movq %rbx, 8(%rbp)
movq %rax, 8(%rsp)
movss .LC0(%rip), %xmm0
movss %xmm0, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movss %xmm0, 236(%rsp)
movl $0x00000000, 240(%rsp)
movss %xmm0, 244(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movl $24, %edi
.LEHB13:
call _Znwm@PLT
.LEHE13:
movq %rax, %rbx
movq %rax, 32(%rsp)
leaq 24(%rax), %rax
movq %rax, 48(%rsp)
movdqa 224(%rsp), %xmm1
movups %xmm1, (%rbx)
movq 240(%rsp), %rdx
movq %rdx, 16(%rbx)
movq %rax, 40(%rsp)
movl $0x00000000, 224(%rsp)
movl $0x00000000, 228(%rsp)
movl $0x00000000, 232(%rsp)
movl $0x00000000, 236(%rsp)
movl $0x00000000, 240(%rsp)
movl $0x00000000, 244(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $24, %edi
.LEHB14:
call _Znwm@PLT
.LEHE14:
jmp .L114
.L107:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L73:
movq %rbx, %rdi
.LEHB15:
call _Unwind_Resume@PLT
.LEHE15:
.L114:
movq %rax, %r12
movq %rax, 64(%rsp)
leaq 24(%rax), %rax
movq %rax, 80(%rsp)
movdqa 224(%rsp), %xmm2
movups %xmm2, (%r12)
movq 240(%rsp), %rdx
movq %rdx, 16(%r12)
movq %rax, 72(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $16, %edi
.LEHB16:
call _Znwm@PLT
.LEHE16:
jmp .L115
.L106:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L76:
movq %rsp, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 280(%rsp), %rax
subq %fs:40, %rax
je .L97
call __stack_chk_fail@PLT
.L115:
movq %rax, 96(%rsp)
leaq 16(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu 0(%rbp), %xmm3
movups %xmm3, (%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $0, %r8d
movl $2, %ecx
movl $2, %edx
.LEHB17:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE17:
jmp .L116
.L108:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt12_Vector_baseIfSaIfEED2Ev
.L79:
leaq 32(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L76
.L116:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L80
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L80:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB18:
call _Znwm@PLT
.LEHE18:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%rbx), %xmm4
movups %xmm4, (%rax)
movq 16(%rbx), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB19:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE19:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L81
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L81:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $24, %edi
.LEHB20:
call _Znwm@PLT
.LEHE20:
movq %rax, 96(%rsp)
leaq 24(%rax), %rdx
movq %rdx, 112(%rsp)
movdqu (%r12), %xmm5
movups %xmm5, (%rax)
movq 16(%r12), %rcx
movq %rcx, 16(%rax)
movq %rdx, 104(%rsp)
leaq 96(%rsp), %rsi
leaq 224(%rsp), %rdi
movl $0, %r8d
movl $3, %ecx
movl $2, %edx
.LEHB21:
call _ZN4gMatC1ESt6vectorIfSaIfEEiii@PLT
.LEHE21:
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .L82
movq 112(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L82:
leaq 224(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 128(%rsp), %rdi
movl %r14d, %r8d
movl %r13d, %ecx
.LEHB22:
call _Z6prodv2RK4gMatS1_RS_ii@PLT
leaq 224(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZlsRSoR4gMat@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L117
cmpb $0, 56(%r14)
je .L85
movzbl 67(%r14), %esi
.L86:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
jmp .L118
.L117:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L119
call _ZSt16__throw_bad_castv@PLT
.L105:
endbr64
movq %rax, %rbx
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L95
.L119:
call __stack_chk_fail@PLT
.L85:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L86
.L118:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 128(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 176(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
leaq 224(%rsp), %rdi
call _ZN4gMat7cleanupEv@PLT
.LEHE22:
movq 240(%rsp), %rdi
leaq 256(%rsp), %rax
cmpq %rax, %rdi
je .L87
movq 256(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L87:
movq 192(%rsp), %rdi
leaq 208(%rsp), %rax
cmpq %rax, %rdi
je .L88
movq 208(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L88:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L89
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L89:
movl $24, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movl $24, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $16, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L120
addq $288, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L99:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L91:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L79
.L101:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L93:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L91
.L103:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L95:
leaq 192(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L93
.L104:
endbr64
movq %rax, %rbx
jmp .L95
.L102:
endbr64
movq %rax, %rbx
jmp .L93
.L100:
endbr64
movq %rax, %rbx
jmp .L91
.L97:
movq %rbx, %rdi
.LEHB23:
call _Unwind_Resume@PLT
.LEHE23:
.L120:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4623:
.section .gcc_except_table
.LLSDA4623:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4623-.LLSDACSB4623
.LLSDACSB4623:
.uleb128 .LEHB12-.LFB4623
.uleb128 .LEHE12-.LEHB12
.uleb128 .L107-.LFB4623
.uleb128 0
.uleb128 .LEHB13-.LFB4623
.uleb128 .LEHE13-.LEHB13
.uleb128 .L106-.LFB4623
.uleb128 0
.uleb128 .LEHB14-.LFB4623
.uleb128 .LEHE14-.LEHB14
.uleb128 .L108-.LFB4623
.uleb128 0
.uleb128 .LEHB15-.LFB4623
.uleb128 .LEHE15-.LEHB15
.uleb128 0
.uleb128 0
.uleb128 .LEHB16-.LFB4623
.uleb128 .LEHE16-.LEHB16
.uleb128 .L100-.LFB4623
.uleb128 0
.uleb128 .LEHB17-.LFB4623
.uleb128 .LEHE17-.LEHB17
.uleb128 .L99-.LFB4623
.uleb128 0
.uleb128 .LEHB18-.LFB4623
.uleb128 .LEHE18-.LEHB18
.uleb128 .L102-.LFB4623
.uleb128 0
.uleb128 .LEHB19-.LFB4623
.uleb128 .LEHE19-.LEHB19
.uleb128 .L101-.LFB4623
.uleb128 0
.uleb128 .LEHB20-.LFB4623
.uleb128 .LEHE20-.LEHB20
.uleb128 .L104-.LFB4623
.uleb128 0
.uleb128 .LEHB21-.LFB4623
.uleb128 .LEHE21-.LEHB21
.uleb128 .L103-.LFB4623
.uleb128 0
.uleb128 .LEHB22-.LFB4623
.uleb128 .LEHE22-.LEHB22
.uleb128 .L105-.LFB4623
.uleb128 0
.uleb128 .LEHB23-.LFB4623
.uleb128 .LEHE23-.LEHB23
.uleb128 0
.uleb128 0
.LLSDACSE4623:
.text
.size _Z15basicMultTestv2ii, .-_Z15basicMultTestv2ii
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z13basicMultTesti
.LCPI0_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.text
.globl _Z13basicMultTesti
.p2align 4, 0x90
.type _Z13basicMultTesti,@function
_Z13basicMultTesti: # @_Z13basicMultTesti
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movups %xmm0, (%rax)
.Ltmp0:
movl $24, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit24
movq %rax, %r14
movups .Lconstinit.2(%rip), %xmm0
movups %xmm0, (%rax)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 16(%r14)
.Ltmp3:
movl $24, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit29
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movq $0, 16(%rax)
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp6:
movl $16, %edi
callq _Znwm
.Ltmp7:
# %bb.3: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rax, 64(%rsp)
movq %rax, 72(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 80(%rsp)
movups (%rbx), %xmm0
movups %xmm0, (%rax)
movq %rcx, 72(%rsp)
.Ltmp9:
leaq 184(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $2, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp10:
# %bb.4:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_6
# %bb.5:
callq _ZdlPv
.LBB0_6: # %_ZNSt6vectorIfSaIfEED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp12:
movl $24, %edi
callq _Znwm
.Ltmp13:
# %bb.7: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i35
movq %rax, 32(%rsp)
movq %rax, 40(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 48(%rsp)
movq 16(%r14), %rdx
movq %rdx, 16(%rax)
movups (%r14), %xmm0
movups %xmm0, (%rax)
movq %rcx, 40(%rsp)
.Ltmp15:
leaq 136(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp16:
# %bb.8:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB0_10
# %bb.9:
callq _ZdlPv
.LBB0_10: # %_ZNSt6vectorIfSaIfEED2Ev.exit44
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp18:
movl $24, %edi
callq _Znwm
.Ltmp19:
# %bb.11: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i47
movq %rax, (%rsp)
movq %rax, 8(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 16(%rsp)
movq 16(%r15), %rdx
movq %rdx, 16(%rax)
movups (%r15), %xmm0
movups %xmm0, (%rax)
movq %rcx, 8(%rsp)
.Ltmp21:
leaq 88(%rsp), %rdi
movq %rsp, %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp22:
# %bb.12:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_14
# %bb.13:
callq _ZdlPv
.LBB0_14: # %_ZNSt6vectorIfSaIfEED2Ev.exit56
imull %ebp, %ebp
shll $3, %ebp
.Ltmp24:
leaq 184(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 88(%rsp), %rdx
movl %ebp, %ecx
callq _Z4prodRK4gMatS1_RS_i
.Ltmp25:
# %bb.15:
.Ltmp26:
leaq 88(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZlsRSoR4gMat
.Ltmp27:
# %bb.16:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB0_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB0_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB0_23
.LBB0_21:
.Ltmp28:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp29:
# %bb.22: # %.noexc102
movq (%r13), %rax
.Ltmp30:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp31:
.LBB0_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp32:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp33:
# %bb.24: # %.noexc104
.Ltmp34:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp35:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit
.Ltmp36:
leaq 184(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp37:
# %bb.26:
.Ltmp38:
leaq 136(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp39:
# %bb.27:
.Ltmp40:
leaq 88(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp41:
# %bb.28:
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_30
# %bb.29: # %.critedge.i.i.i
callq _ZdlPv
.LBB0_30: # %_ZN4gMatD2Ev.exit
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_32
# %bb.31: # %.critedge.i.i.i58
callq _ZdlPv
.LBB0_32: # %_ZN4gMatD2Ev.exit60
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_34
# %bb.33: # %.critedge.i.i.i61
callq _ZdlPv
.LBB0_34: # %_ZN4gMatD2Ev.exit63
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 288
.Ltmp42:
callq _ZSt16__throw_bad_castv
.Ltmp43:
# %bb.18: # %.noexc101
.LBB0_40:
.Ltmp23:
movq %rax, %r12
movq (%rsp), %rdi
testq %rdi, %rdi
jne .LBB0_42
jmp .LBB0_43
.LBB0_39:
.Ltmp20:
movq %rax, %r12
jmp .LBB0_43
.LBB0_38:
.Ltmp17:
movq %rax, %r12
movq 32(%rsp), %rdi
testq %rdi, %rdi
jne .LBB0_44
jmp .LBB0_45
.LBB0_37:
.Ltmp14:
movq %rax, %r12
jmp .LBB0_45
.LBB0_36:
.Ltmp11:
movq %rax, %r12
movq 64(%rsp), %rdi
testq %rdi, %rdi
jne .LBB0_46
jmp .LBB0_47
.LBB0_35:
.Ltmp8:
movq %rax, %r12
jmp .LBB0_47
.LBB0_51: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i26
.Ltmp5:
movq %rax, %r12
jmp .LBB0_48
.LBB0_50: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i21
.Ltmp2:
movq %rax, %r12
jmp .LBB0_49
.LBB0_41:
.Ltmp44:
movq %rax, %r12
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_43
.LBB0_42: # %.critedge.i.i.i82
callq _ZdlPv
.LBB0_43: # %_ZNSt6vectorIfSaIfEED2Ev.exit81
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_45
.LBB0_44: # %.critedge.i.i.i85
callq _ZdlPv
.LBB0_45: # %_ZNSt6vectorIfSaIfEED2Ev.exit78
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_47
.LBB0_46: # %.critedge.i.i.i88
callq _ZdlPv
.LBB0_47: # %_ZNSt6vectorIfSaIfEED2Ev.exit75
movq %r15, %rdi
callq _ZdlPv
.LBB0_48: # %_ZNSt6vectorIfSaIfEED2Ev.exit96
movq %r14, %rdi
callq _ZdlPv
.LBB0_49: # %_ZNSt6vectorIfSaIfEED2Ev.exit99
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z13basicMultTesti, .Lfunc_end0-_Z13basicMultTesti
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp43-.Ltmp24 # Call between .Ltmp24 and .Ltmp43
.uleb128 .Ltmp44-.Lfunc_begin0 # jumps to .Ltmp44
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end0-.Ltmp43 # Call between .Ltmp43 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z15basicMultTestv2ii
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.text
.globl _Z15basicMultTestv2ii
.p2align 4, 0x90
.type _Z15basicMultTestv2ii,@function
_Z15basicMultTestv2ii: # @_Z15basicMultTestv2ii
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r12d
movl $16, %edi
callq _Znwm
movq %rax, %rbx
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movups %xmm0, (%rax)
.Ltmp45:
movl $24, %edi
callq _Znwm
.Ltmp46:
# %bb.1: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit23
movq %rax, %r14
movups .Lconstinit.2(%rip), %xmm0
movups %xmm0, (%rax)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 16(%r14)
.Ltmp48:
movl $24, %edi
callq _Znwm
.Ltmp49:
# %bb.2: # %_ZNSt6vectorIfSaIfEEC2ESt16initializer_listIfERKS0_.exit28
movq %rax, %r15
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movq $0, 16(%rax)
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
.Ltmp51:
movl $16, %edi
callq _Znwm
.Ltmp52:
# %bb.3: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %rax, 64(%rsp)
movq %rax, 72(%rsp)
movq %rax, %rcx
addq $16, %rcx
movq %rcx, 80(%rsp)
movups (%rbx), %xmm0
movups %xmm0, (%rax)
movq %rcx, 72(%rsp)
.Ltmp54:
leaq 184(%rsp), %rdi
leaq 64(%rsp), %rsi
movl $2, %edx
movl $2, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp55:
# %bb.4:
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_6
# %bb.5:
callq _ZdlPv
.LBB1_6: # %_ZNSt6vectorIfSaIfEED2Ev.exit
xorps %xmm0, %xmm0
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
.Ltmp57:
movl $24, %edi
callq _Znwm
.Ltmp58:
# %bb.7: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i34
movq %rax, 32(%rsp)
movq %rax, 40(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 48(%rsp)
movq 16(%r14), %rdx
movq %rdx, 16(%rax)
movups (%r14), %xmm0
movups %xmm0, (%rax)
movq %rcx, 40(%rsp)
.Ltmp60:
leaq 136(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp61:
# %bb.8:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_10
# %bb.9:
callq _ZdlPv
.LBB1_10: # %_ZNSt6vectorIfSaIfEED2Ev.exit43
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
.Ltmp63:
movl $24, %edi
callq _Znwm
.Ltmp64:
# %bb.11: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i46
movq %rax, (%rsp)
movq %rax, 8(%rsp)
movq %rax, %rcx
addq $24, %rcx
movq %rcx, 16(%rsp)
movq 16(%r15), %rdx
movq %rdx, 16(%rax)
movups (%r15), %xmm0
movups %xmm0, (%rax)
movq %rcx, 8(%rsp)
.Ltmp66:
leaq 88(%rsp), %rdi
movq %rsp, %rsi
movl $2, %edx
movl $3, %ecx
xorl %r8d, %r8d
callq _ZN4gMatC1ESt6vectorIfSaIfEEiii
.Ltmp67:
# %bb.12:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB1_14
# %bb.13:
callq _ZdlPv
.LBB1_14: # %_ZNSt6vectorIfSaIfEED2Ev.exit55
.Ltmp69:
leaq 184(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 88(%rsp), %rdx
movl %r12d, %ecx
movl %ebp, %r8d
callq _Z6prodv2RK4gMatS1_RS_ii
.Ltmp70:
# %bb.15:
.Ltmp71:
leaq 88(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZlsRSoR4gMat
.Ltmp72:
# %bb.16:
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_17
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB1_23
.LBB1_21:
.Ltmp73:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp74:
# %bb.22: # %.noexc101
movq (%r13), %rax
.Ltmp75:
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp76:
.LBB1_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp77:
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp78:
# %bb.24: # %.noexc103
.Ltmp79:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp80:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit
.Ltmp81:
leaq 184(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp82:
# %bb.26:
.Ltmp83:
leaq 136(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp84:
# %bb.27:
.Ltmp85:
leaq 88(%rsp), %rdi
callq _ZN4gMat7cleanupEv
.Ltmp86:
# %bb.28:
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_30
# %bb.29: # %.critedge.i.i.i
callq _ZdlPv
.LBB1_30: # %_ZN4gMatD2Ev.exit
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_32
# %bb.31: # %.critedge.i.i.i57
callq _ZdlPv
.LBB1_32: # %_ZN4gMatD2Ev.exit59
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_34
# %bb.33: # %.critedge.i.i.i60
callq _ZdlPv
.LBB1_34: # %_ZN4gMatD2Ev.exit62
movq %r15, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %rbx, %rdi
callq _ZdlPv
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_17:
.cfi_def_cfa_offset 288
.Ltmp87:
callq _ZSt16__throw_bad_castv
.Ltmp88:
# %bb.18: # %.noexc100
.LBB1_40:
.Ltmp68:
movq %rax, %r12
movq (%rsp), %rdi
testq %rdi, %rdi
jne .LBB1_42
jmp .LBB1_43
.LBB1_39:
.Ltmp65:
movq %rax, %r12
jmp .LBB1_43
.LBB1_38:
.Ltmp62:
movq %rax, %r12
movq 32(%rsp), %rdi
testq %rdi, %rdi
jne .LBB1_44
jmp .LBB1_45
.LBB1_37:
.Ltmp59:
movq %rax, %r12
jmp .LBB1_45
.LBB1_36:
.Ltmp56:
movq %rax, %r12
movq 64(%rsp), %rdi
testq %rdi, %rdi
jne .LBB1_46
jmp .LBB1_47
.LBB1_35:
.Ltmp53:
movq %rax, %r12
jmp .LBB1_47
.LBB1_51: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i25
.Ltmp50:
movq %rax, %r12
jmp .LBB1_48
.LBB1_50: # %_ZNSt12_Vector_baseIfSaIfEED2Ev.exit.i20
.Ltmp47:
movq %rax, %r12
jmp .LBB1_49
.LBB1_41:
.Ltmp89:
movq %rax, %r12
movq 104(%rsp), %rdi
leaq 120(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_43
.LBB1_42: # %.critedge.i.i.i81
callq _ZdlPv
.LBB1_43: # %_ZNSt6vectorIfSaIfEED2Ev.exit80
movq 152(%rsp), %rdi
leaq 168(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_45
.LBB1_44: # %.critedge.i.i.i84
callq _ZdlPv
.LBB1_45: # %_ZNSt6vectorIfSaIfEED2Ev.exit77
movq 200(%rsp), %rdi
leaq 216(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_47
.LBB1_46: # %.critedge.i.i.i87
callq _ZdlPv
.LBB1_47: # %_ZNSt6vectorIfSaIfEED2Ev.exit74
movq %r15, %rdi
callq _ZdlPv
.LBB1_48: # %_ZNSt6vectorIfSaIfEED2Ev.exit95
movq %r14, %rdi
callq _ZdlPv
.LBB1_49: # %_ZNSt6vectorIfSaIfEED2Ev.exit98
movq %rbx, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z15basicMultTestv2ii, .Lfunc_end1-_Z15basicMultTestv2ii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp45-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp45
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp46-.Ltmp45 # Call between .Ltmp45 and .Ltmp46
.uleb128 .Ltmp47-.Lfunc_begin1 # jumps to .Ltmp47
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49
.uleb128 .Ltmp50-.Lfunc_begin1 # jumps to .Ltmp50
.byte 0 # On action: cleanup
.uleb128 .Ltmp51-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp52-.Ltmp51 # Call between .Ltmp51 and .Ltmp52
.uleb128 .Ltmp53-.Lfunc_begin1 # jumps to .Ltmp53
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin1 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp58-.Ltmp57 # Call between .Ltmp57 and .Ltmp58
.uleb128 .Ltmp59-.Lfunc_begin1 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Ltmp61-.Ltmp60 # Call between .Ltmp60 and .Ltmp61
.uleb128 .Ltmp62-.Lfunc_begin1 # jumps to .Ltmp62
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin1 # >> Call Site 8 <<
.uleb128 .Ltmp64-.Ltmp63 # Call between .Ltmp63 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin1 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin1 # >> Call Site 9 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp68-.Lfunc_begin1 # jumps to .Ltmp68
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin1 # >> Call Site 10 <<
.uleb128 .Ltmp88-.Ltmp69 # Call between .Ltmp69 and .Ltmp88
.uleb128 .Ltmp89-.Lfunc_begin1 # jumps to .Ltmp89
.byte 0 # On action: cleanup
.uleb128 .Ltmp88-.Lfunc_begin1 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp88 # Call between .Ltmp88 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $1, %edi
callq _Z13basicMultTesti
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.type .Lconstinit.2,@object # @constinit.2
.section .rodata,"a",@progbits
.p2align 2, 0x0
.Lconstinit.2:
.long 0x40000000 # float 2
.long 0x00000000 # float 0
.long 0x00000000 # float 0
.long 0x40000000 # float 2
.long 0x00000000 # float 0
.long 0x40000000 # float 2
.size .Lconstinit.2, 24
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "SUCCESS!"
.size .L.str, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void sgemm (float *A, float *B, float *C, int N)
{
// Thread identifiers
const int r = blockIdx.x; // Row ID
const int c = blockIdx.y; // Col ID
// Compute a single element (loop a K)
float acc = 0.0f;
for (int k = 0; k < N; k++) {
acc += A[k * N + r] * B[c * N + k];
}
// Store the result
C[c * N + r] = acc;
} | code for sm_80
Function : _Z5sgemmPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 BRA 0xb30 ; /* 0x00000ab000008947 */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0090*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*00d0*/ @!P0 BRA 0xa30 ; /* 0x0000095000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD R12, R3, c[0x0][0x178], RZ ; /* 0x00005e00030c7a24 */
/* 0x002fe200078e02ff */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0130*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fca0000000f00 */
/*0140*/ IMAD.WIDE R12, R12, R21, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e0215 */
/*0150*/ IMAD.WIDE R20, R0, R21, c[0x0][0x160] ; /* 0x0000580000147625 */
/* 0x001fe400078e0215 */
/*0160*/ @!P0 BRA 0x8c0 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x610 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ IMAD.WIDE R22, R2, 0x4, R20 ; /* 0x0000000402167825 */
/* 0x000fc600078e0214 */
/*01e0*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x000ee6000c1e1900 */
/*01f0*/ IMAD.WIDE R26, R2.reuse, 0x4, R22 ; /* 0x00000004021a7825 */
/* 0x040fe200078e0216 */
/*0200*/ LDG.E R17, [R22.64] ; /* 0x0000000416117981 */
/* 0x0002e8000c1e1900 */
/*0210*/ LDG.E R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x000962000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2, 0x4, R26 ; /* 0x0000000402127825 */
/* 0x000fc600078e021a */
/*0230*/ LDG.E R15, [R12.64+0x8] ; /* 0x000008040c0f7981 */
/* 0x000f66000c1e1900 */
/*0240*/ IMAD.WIDE R28, R2.reuse, 0x4, R18 ; /* 0x00000004021c7825 */
/* 0x040fe200078e0212 */
/*0250*/ LDG.E R7, [R12.64+0x10] ; /* 0x000010040c077981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0270*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000968000c1e1900 */
/*0280*/ LDG.E R21, [R12.64+0x14] ; /* 0x000014040c157981 */
/* 0x001f68000c1e1900 */
/*0290*/ LDG.E R19, [R12.64+0xc] ; /* 0x00000c040c137981 */
/* 0x002f62000c1e1900 */
/*02a0*/ IMAD.WIDE R28, R2, 0x4, R28 ; /* 0x00000004021c7825 */
/* 0x010fc600078e021c */
/*02b0*/ LDG.E R9, [R12.64+0x18] ; /* 0x000018040c097981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000722000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2, 0x4, R28 ; /* 0x0000000402167825 */
/* 0x000fca00078e021c */
/*02e0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000124000c1e1900 */
/*02f0*/ IMAD.WIDE R22, R2, 0x4, R22 ; /* 0x0000000402167825 */
/* 0x001fc800078e0216 */
/*0300*/ FFMA R27, R8, R24, R11 ; /* 0x00000018081b7223 */
/* 0x004fe4000000000b */
/*0310*/ LDG.E R11, [R12.64+0x1c] ; /* 0x00001c040c0b7981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc800078e0216 */
/*0340*/ FFMA R29, R16, R17, R27 ; /* 0x00000011101d7223 */
/* 0x008fe2000000001b */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x000ae2000c1e1900 */
/*0360*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fc600078e0218 */
/*0370*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000ee2000c1e1900 */
/*0380*/ FFMA R24, R15, R14, R29 ; /* 0x0000000e0f187223 */
/* 0x020fe4000000001d */
/*0390*/ IMAD.WIDE R14, R2.reuse, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0210 */
/*03a0*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000368000c1e1900 */
/*03b0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000962000c1e1900 */
/*03c0*/ FFMA R16, R19, R18, R24 ; /* 0x0000001213107223 */
/* 0x002fe40000000018 */
/*03d0*/ IMAD.WIDE R18, R2, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x000fe200078e020e */
/*03e0*/ LDG.E R24, [R12.64+0x24] ; /* 0x000024040c187981 */
/* 0x000f66000c1e1900 */
/*03f0*/ FFMA R16, R7, R10, R16 ; /* 0x0000000a07107223 */
/* 0x000fc40000000010 */
/*0400*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x041fe200078e0212 */
/*0410*/ LDG.E R10, [R12.64+0x28] ; /* 0x000028040c0a7981 */
/* 0x000f66000c1e1900 */
/*0420*/ FFMA R14, R21, R20, R16 ; /* 0x00000014150e7223 */
/* 0x010fe20000000010 */
/*0430*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x000122000c1e1900 */
/*0440*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fc600078e0216 */
/*0450*/ LDG.E R21, [R12.64+0x2c] ; /* 0x00002c040c157981 */
/* 0x000f22000c1e1900 */
/*0460*/ FFMA R9, R9, R26, R14 ; /* 0x0000001a09097223 */
/* 0x000fe4000000000e */
/*0470*/ IMAD.WIDE R14, R2, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0210 */
/*0480*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000328000c1e1900 */
/*0490*/ LDG.E R19, [R12.64+0x30] ; /* 0x000030040c137981 */
/* 0x001f28000c1e1900 */
/*04a0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000128000c1e1900 */
/*04b0*/ LDG.E R18, [R12.64+0x34] ; /* 0x000034040c127981 */
/* 0x000528000c1e1900 */
/*04c0*/ LDG.E R23, [R12.64+0x3c] ; /* 0x00003c040c177981 */
/* 0x002328000c1e1900 */
/*04d0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x001f22000c1e1900 */
/*04e0*/ FFMA R17, R11, R8, R9 ; /* 0x000000080b117223 */
/* 0x004fc40000000009 */
/*04f0*/ IMAD.WIDE R8, R2, 0x4, R14 ; /* 0x0000000402087825 */
/* 0x000fe200078e020e */
/*0500*/ LDG.E R11, [R12.64+0x38] ; /* 0x000038040c0b7981 */
/* 0x0002a8000c1e1900 */
/*0510*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea2000c1e1900 */
/*0520*/ FFMA R27, R27, R28, R17 ; /* 0x0000001c1b1b7223 */
/* 0x008fe20000000011 */
/*0530*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0550*/ FFMA R24, R24, R29, R27 ; /* 0x0000001d18187223 */
/* 0x020fc8000000001b */
/*0560*/ FFMA R10, R10, R25, R24 ; /* 0x000000190a0a7223 */
/* 0x000fc80000000018 */
/*0570*/ FFMA R7, R21, R7, R10 ; /* 0x0000000715077223 */
/* 0x010fc8000000000a */
/*0580*/ FFMA R7, R19, R20, R7 ; /* 0x0000001413077223 */
/* 0x000fe20000000007 */
/*0590*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fc60007f5e0ff */
/*05a0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x000fe20000000007 */
/*05b0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05c0*/ IMAD.WIDE R20, R2, 0x4, R8 ; /* 0x0000000402147825 */
/* 0x000fe200078e0208 */
/*05d0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ FFMA R11, R11, R16, R7 ; /* 0x000000100b0b7223 */
/* 0x004fc80000000007 */
/*05f0*/ FFMA R11, R23, R22, R11 ; /* 0x00000016170b7223 */
/* 0x000fe2000000000b */
/*0600*/ @P1 BRA 0x1b0 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x8a0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0000a2000c1e1900 */
/*0650*/ IMAD.WIDE R28, R2, 0x4, R20 ; /* 0x00000004021c7825 */
/* 0x000fc600078e0214 */
/*0660*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ee6000c1e1900 */
/*0670*/ IMAD.WIDE R14, R2.reuse, 0x4, R28 ; /* 0x00000004020e7825 */
/* 0x040fe200078e021c */
/*0680*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x0002e8000c1e1900 */
/*0690*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000962000c1e1900 */
/*06a0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*06b0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f66000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R2.reuse, 0x4, R16 ; /* 0x0000000402087825 */
/* 0x040fe200078e0210 */
/*06d0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IMAD.WIDE R18, R2, 0x4, R8 ; /* 0x0000000402127825 */
/* 0x000fc600078e0208 */
/*0700*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000368000c1e1900 */
/*0710*/ LDG.E R27, [R12.64+0x10] ; /* 0x000010040c1b7981 */
/* 0x000f62000c1e1900 */
/*0720*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x001fc600078e0212 */
/*0730*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f68000c1e1900 */
/*0740*/ LDG.E R29, [R12.64+0x14] ; /* 0x000014040c1d7981 */
/* 0x002f62000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x010fc600078e0214 */
/*0760*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000128000c1e1900 */
/*0770*/ LDG.E R9, [R12.64+0x18] ; /* 0x000018040c097981 */
/* 0x000f22000c1e1900 */
/*0780*/ FFMA R23, R23, R10, R11 ; /* 0x0000000a17177223 */
/* 0x004fc6000000000b */
/*0790*/ LDG.E R11, [R12.64+0x1c] ; /* 0x00001c040c0b7981 */
/* 0x0002a8000c1e1900 */
/*07a0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ FFMA R7, R22, R7, R23 ; /* 0x0000000716077223 */
/* 0x008fc80000000017 */
/*07c0*/ FFMA R7, R24, R25, R7 ; /* 0x0000001918077223 */
/* 0x020fc80000000007 */
/*07d0*/ FFMA R7, R26, R17, R7 ; /* 0x000000111a077223 */
/* 0x000fc80000000007 */
/*07e0*/ FFMA R7, R27, R8, R7 ; /* 0x000000081b077223 */
/* 0x000fe20000000007 */
/*07f0*/ IADD3 R8, P1, R12, 0x20, RZ ; /* 0x000000200c087810 */
/* 0x000fc60007f3e0ff */
/*0800*/ FFMA R7, R29, R18, R7 ; /* 0x000000121d077223 */
/* 0x000fe20000000007 */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0820*/ IMAD.WIDE R20, R2, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x001fe200078e020e */
/*0830*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc60007ffe0ff */
/*0840*/ FFMA R7, R9, R28, R7 ; /* 0x0000001c09077223 */
/* 0x010fe20000000007 */
/*0850*/ IADD3.X R9, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff097210 */
/* 0x000fe40000ffe4ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*0870*/ MOV R12, R8 ; /* 0x00000008000c7202 */
/* 0x002fe40000000f00 */
/*0880*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe20000000f00 */
/*0890*/ FFMA R11, R11, R10, R7 ; /* 0x0000000a0b0b7223 */
/* 0x004fe40000000007 */
/*08a0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08b0*/ @!P0 BRA 0xa30 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.WIDE R16, R2.reuse, 0x4, R20 ; /* 0x0000000402107825 */
/* 0x040fe200078e0214 */
/*08d0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.WIDE R14, R2, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0210 */
/*0900*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R7, [R12.64+0x4] ; /* 0x000004040c077981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IMAD.WIDE R8, R2, 0x4, R14 ; /* 0x0000000402087825 */
/* 0x000fc600078e020e */
/*0930*/ LDG.E R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000f28000c1e1900 */
/*0940*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000f28000c1e1900 */
/*0950*/ LDG.E R24, [R12.64+0xc] ; /* 0x00000c040c187981 */
/* 0x000168000c1e1900 */
/*0960*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x000f62000c1e1900 */
/*0970*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0980*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0990*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FFMA R10, R10, R20, R11 ; /* 0x000000140a0a7223 */
/* 0x004fc8000000000b */
/*09b0*/ FFMA R7, R7, R18, R10 ; /* 0x0000001207077223 */
/* 0x008fe2000000000a */
/*09c0*/ IADD3 R10, P1, R12, 0x10, RZ ; /* 0x000000100c0a7810 */
/* 0x000fe20007f3e0ff */
/*09d0*/ IMAD.WIDE R20, R2, 0x4, R8 ; /* 0x0000000402147825 */
/* 0x000fc800078e0208 */
/*09e0*/ FFMA R7, R22, R19, R7 ; /* 0x0000001316077223 */
/* 0x010fe20000000007 */
/*09f0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x001fe40000ffe4ff */
/*0a00*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fe20000000f00 */
/*0a10*/ FFMA R11, R24, R23, R7 ; /* 0x00000017180b7223 */
/* 0x020fe20000000007 */
/*0a20*/ @P0 BRA 0x8c0 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0a30*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0a40*/ @!P0 BRA 0xb30 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0a50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0a60*/ IMAD R6, R3, c[0x0][0x178], R4 ; /* 0x00005e0003067a24 */
/* 0x002fe400078e0204 */
/*0a70*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x001fce00078e0200 */
/*0a80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0a90*/ IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fca00078e0209 */
/*0aa0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0ab0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0ac0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ae0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0af0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0b00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0b10*/ FFMA R11, R4, R10, R11 ; /* 0x0000000a040b7223 */
/* 0x004fcc000000000b */
/*0b20*/ @P0 BRA 0xaa0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0b30*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0b40*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x003fc800078e0200 */
/*0b50*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0b60*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0b70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b80*/ BRA 0xb80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void sgemm (float *A, float *B, float *C, int N)
{
// Thread identifiers
const int r = blockIdx.x; // Row ID
const int c = blockIdx.y; // Col ID
// Compute a single element (loop a K)
float acc = 0.0f;
for (int k = 0; k < N; k++) {
acc += A[k * N + r] * B[c * N + k];
}
// Store the result
C[c * N + r] = acc;
} | .file "tmpxft_0009657c_00000000-6_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sgemmPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i
.globl _Z5sgemmPfS_S_i
.type _Z5sgemmPfS_S_i, @function
_Z5sgemmPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sgemmPfS_S_i, .-_Z5sgemmPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5sgemmPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sgemmPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void sgemm (float *A, float *B, float *C, int N)
{
// Thread identifiers
const int r = blockIdx.x; // Row ID
const int c = blockIdx.y; // Col ID
// Compute a single element (loop a K)
float acc = 0.0f;
for (int k = 0; k < N; k++) {
acc += A[k * N + r] * B[c * N + k];
}
// Store the result
C[c * N + r] = acc;
} | #include <hip/hip_runtime.h>
__global__ void sgemm (float *A, float *B, float *C, int N)
{
// Thread identifiers
const int r = blockIdx.x; // Row ID
const int c = blockIdx.y; // Col ID
// Compute a single element (loop a K)
float acc = 0.0f;
for (int k = 0; k < N; k++) {
acc += A[k * N + r] * B[c * N + k];
}
// Store the result
C[c * N + r] = acc;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void sgemm (float *A, float *B, float *C, int N)
{
// Thread identifiers
const int r = blockIdx.x; // Row ID
const int c = blockIdx.y; // Col ID
// Compute a single element (loop a K)
float acc = 0.0f;
for (int k = 0; k < N; k++) {
acc += A[k * N + r] * B[c * N + k];
}
// Store the result
C[c * N + r] = acc;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sgemmPfS_S_i
.globl _Z5sgemmPfS_S_i
.p2align 8
.type _Z5sgemmPfS_S_i,@function
_Z5sgemmPfS_S_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_mul_i32 s2, s15, s4
s_cbranch_scc1 .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[6:7], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[14:15], 2
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
.LBB0_2:
s_load_b32 s3, s[8:9], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e64 v0, s3, s5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_add_i32 s2, s2, s14
v_mov_b32_e32 v1, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sgemmPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sgemmPfS_S_i, .Lfunc_end0-_Z5sgemmPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sgemmPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5sgemmPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void sgemm (float *A, float *B, float *C, int N)
{
// Thread identifiers
const int r = blockIdx.x; // Row ID
const int c = blockIdx.y; // Col ID
// Compute a single element (loop a K)
float acc = 0.0f;
for (int k = 0; k < N; k++) {
acc += A[k * N + r] * B[c * N + k];
}
// Store the result
C[c * N + r] = acc;
} | .text
.file "sgemm.hip"
.globl _Z20__device_stub__sgemmPfS_S_i # -- Begin function _Z20__device_stub__sgemmPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sgemmPfS_S_i,@function
_Z20__device_stub__sgemmPfS_S_i: # @_Z20__device_stub__sgemmPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sgemmPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__sgemmPfS_S_i, .Lfunc_end0-_Z20__device_stub__sgemmPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sgemmPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sgemmPfS_S_i,@object # @_Z5sgemmPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5sgemmPfS_S_i
.p2align 3, 0x0
_Z5sgemmPfS_S_i:
.quad _Z20__device_stub__sgemmPfS_S_i
.size _Z5sgemmPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sgemmPfS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sgemmPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sgemmPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5sgemmPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0070*/ @!P0 BRA 0xb30 ; /* 0x00000ab000008947 */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0090*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*00d0*/ @!P0 BRA 0xa30 ; /* 0x0000095000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*00f0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*0100*/ IMAD R12, R3, c[0x0][0x178], RZ ; /* 0x00005e00030c7a24 */
/* 0x002fe200078e02ff */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0130*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fca0000000f00 */
/*0140*/ IMAD.WIDE R12, R12, R21, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e0215 */
/*0150*/ IMAD.WIDE R20, R0, R21, c[0x0][0x160] ; /* 0x0000580000147625 */
/* 0x001fe400078e0215 */
/*0160*/ @!P0 BRA 0x8c0 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x610 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ IMAD.WIDE R22, R2, 0x4, R20 ; /* 0x0000000402167825 */
/* 0x000fc600078e0214 */
/*01e0*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x000ee6000c1e1900 */
/*01f0*/ IMAD.WIDE R26, R2.reuse, 0x4, R22 ; /* 0x00000004021a7825 */
/* 0x040fe200078e0216 */
/*0200*/ LDG.E R17, [R22.64] ; /* 0x0000000416117981 */
/* 0x0002e8000c1e1900 */
/*0210*/ LDG.E R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x000962000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2, 0x4, R26 ; /* 0x0000000402127825 */
/* 0x000fc600078e021a */
/*0230*/ LDG.E R15, [R12.64+0x8] ; /* 0x000008040c0f7981 */
/* 0x000f66000c1e1900 */
/*0240*/ IMAD.WIDE R28, R2.reuse, 0x4, R18 ; /* 0x00000004021c7825 */
/* 0x040fe200078e0212 */
/*0250*/ LDG.E R7, [R12.64+0x10] ; /* 0x000010040c077981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*0270*/ LDG.E R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000968000c1e1900 */
/*0280*/ LDG.E R21, [R12.64+0x14] ; /* 0x000014040c157981 */
/* 0x001f68000c1e1900 */
/*0290*/ LDG.E R19, [R12.64+0xc] ; /* 0x00000c040c137981 */
/* 0x002f62000c1e1900 */
/*02a0*/ IMAD.WIDE R28, R2, 0x4, R28 ; /* 0x00000004021c7825 */
/* 0x010fc600078e021c */
/*02b0*/ LDG.E R9, [R12.64+0x18] ; /* 0x000018040c097981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000722000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2, 0x4, R28 ; /* 0x0000000402167825 */
/* 0x000fca00078e021c */
/*02e0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000124000c1e1900 */
/*02f0*/ IMAD.WIDE R22, R2, 0x4, R22 ; /* 0x0000000402167825 */
/* 0x001fc800078e0216 */
/*0300*/ FFMA R27, R8, R24, R11 ; /* 0x00000018081b7223 */
/* 0x004fe4000000000b */
/*0310*/ LDG.E R11, [R12.64+0x1c] ; /* 0x00001c040c0b7981 */
/* 0x000ea8000c1e1900 */
/*0320*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000a2000c1e1900 */
/*0330*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc800078e0216 */
/*0340*/ FFMA R29, R16, R17, R27 ; /* 0x00000011101d7223 */
/* 0x008fe2000000001b */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x000ae2000c1e1900 */
/*0360*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fc600078e0218 */
/*0370*/ LDG.E R27, [R12.64+0x20] ; /* 0x000020040c1b7981 */
/* 0x000ee2000c1e1900 */
/*0380*/ FFMA R24, R15, R14, R29 ; /* 0x0000000e0f187223 */
/* 0x020fe4000000001d */
/*0390*/ IMAD.WIDE R14, R2.reuse, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0210 */
/*03a0*/ LDG.E R29, [R16.64] ; /* 0x00000004101d7981 */
/* 0x000368000c1e1900 */
/*03b0*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000962000c1e1900 */
/*03c0*/ FFMA R16, R19, R18, R24 ; /* 0x0000001213107223 */
/* 0x002fe40000000018 */
/*03d0*/ IMAD.WIDE R18, R2, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x000fe200078e020e */
/*03e0*/ LDG.E R24, [R12.64+0x24] ; /* 0x000024040c187981 */
/* 0x000f66000c1e1900 */
/*03f0*/ FFMA R16, R7, R10, R16 ; /* 0x0000000a07107223 */
/* 0x000fc40000000010 */
/*0400*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x041fe200078e0212 */
/*0410*/ LDG.E R10, [R12.64+0x28] ; /* 0x000028040c0a7981 */
/* 0x000f66000c1e1900 */
/*0420*/ FFMA R14, R21, R20, R16 ; /* 0x00000014150e7223 */
/* 0x010fe20000000010 */
/*0430*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x000122000c1e1900 */
/*0440*/ IMAD.WIDE R16, R2, 0x4, R22 ; /* 0x0000000402107825 */
/* 0x000fc600078e0216 */
/*0450*/ LDG.E R21, [R12.64+0x2c] ; /* 0x00002c040c157981 */
/* 0x000f22000c1e1900 */
/*0460*/ FFMA R9, R9, R26, R14 ; /* 0x0000001a09097223 */
/* 0x000fe4000000000e */
/*0470*/ IMAD.WIDE R14, R2, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0210 */
/*0480*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000328000c1e1900 */
/*0490*/ LDG.E R19, [R12.64+0x30] ; /* 0x000030040c137981 */
/* 0x001f28000c1e1900 */
/*04a0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000128000c1e1900 */
/*04b0*/ LDG.E R18, [R12.64+0x34] ; /* 0x000034040c127981 */
/* 0x000528000c1e1900 */
/*04c0*/ LDG.E R23, [R12.64+0x3c] ; /* 0x00003c040c177981 */
/* 0x002328000c1e1900 */
/*04d0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x001f22000c1e1900 */
/*04e0*/ FFMA R17, R11, R8, R9 ; /* 0x000000080b117223 */
/* 0x004fc40000000009 */
/*04f0*/ IMAD.WIDE R8, R2, 0x4, R14 ; /* 0x0000000402087825 */
/* 0x000fe200078e020e */
/*0500*/ LDG.E R11, [R12.64+0x38] ; /* 0x000038040c0b7981 */
/* 0x0002a8000c1e1900 */
/*0510*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea2000c1e1900 */
/*0520*/ FFMA R27, R27, R28, R17 ; /* 0x0000001c1b1b7223 */
/* 0x008fe20000000011 */
/*0530*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0550*/ FFMA R24, R24, R29, R27 ; /* 0x0000001d18187223 */
/* 0x020fc8000000001b */
/*0560*/ FFMA R10, R10, R25, R24 ; /* 0x000000190a0a7223 */
/* 0x000fc80000000018 */
/*0570*/ FFMA R7, R21, R7, R10 ; /* 0x0000000715077223 */
/* 0x010fc8000000000a */
/*0580*/ FFMA R7, R19, R20, R7 ; /* 0x0000001413077223 */
/* 0x000fe20000000007 */
/*0590*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fc60007f5e0ff */
/*05a0*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x000fe20000000007 */
/*05b0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05c0*/ IMAD.WIDE R20, R2, 0x4, R8 ; /* 0x0000000402147825 */
/* 0x000fe200078e0208 */
/*05d0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ FFMA R11, R11, R16, R7 ; /* 0x000000100b0b7223 */
/* 0x004fc80000000007 */
/*05f0*/ FFMA R11, R23, R22, R11 ; /* 0x00000016170b7223 */
/* 0x000fe2000000000b */
/*0600*/ @P1 BRA 0x1b0 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x8a0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x0000a2000c1e1900 */
/*0650*/ IMAD.WIDE R28, R2, 0x4, R20 ; /* 0x00000004021c7825 */
/* 0x000fc600078e0214 */
/*0660*/ LDG.E R22, [R12.64+0x4] ; /* 0x000004040c167981 */
/* 0x000ee6000c1e1900 */
/*0670*/ IMAD.WIDE R14, R2.reuse, 0x4, R28 ; /* 0x00000004020e7825 */
/* 0x040fe200078e021c */
/*0680*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x0002e8000c1e1900 */
/*0690*/ LDG.E R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x000962000c1e1900 */
/*06a0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*06b0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f66000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R2.reuse, 0x4, R16 ; /* 0x0000000402087825 */
/* 0x040fe200078e0210 */
/*06d0*/ LDG.E R26, [R12.64+0xc] ; /* 0x00000c040c1a7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IMAD.WIDE R18, R2, 0x4, R8 ; /* 0x0000000402127825 */
/* 0x000fc600078e0208 */
/*0700*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000368000c1e1900 */
/*0710*/ LDG.E R27, [R12.64+0x10] ; /* 0x000010040c1b7981 */
/* 0x000f62000c1e1900 */
/*0720*/ IMAD.WIDE R20, R2, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x001fc600078e0212 */
/*0730*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f68000c1e1900 */
/*0740*/ LDG.E R29, [R12.64+0x14] ; /* 0x000014040c1d7981 */
/* 0x002f62000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x010fc600078e0214 */
/*0760*/ LDG.E R28, [R20.64] ; /* 0x00000004141c7981 */
/* 0x000128000c1e1900 */
/*0770*/ LDG.E R9, [R12.64+0x18] ; /* 0x000018040c097981 */
/* 0x000f22000c1e1900 */
/*0780*/ FFMA R23, R23, R10, R11 ; /* 0x0000000a17177223 */
/* 0x004fc6000000000b */
/*0790*/ LDG.E R11, [R12.64+0x1c] ; /* 0x00001c040c0b7981 */
/* 0x0002a8000c1e1900 */
/*07a0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ FFMA R7, R22, R7, R23 ; /* 0x0000000716077223 */
/* 0x008fc80000000017 */
/*07c0*/ FFMA R7, R24, R25, R7 ; /* 0x0000001918077223 */
/* 0x020fc80000000007 */
/*07d0*/ FFMA R7, R26, R17, R7 ; /* 0x000000111a077223 */
/* 0x000fc80000000007 */
/*07e0*/ FFMA R7, R27, R8, R7 ; /* 0x000000081b077223 */
/* 0x000fe20000000007 */
/*07f0*/ IADD3 R8, P1, R12, 0x20, RZ ; /* 0x000000200c087810 */
/* 0x000fc60007f3e0ff */
/*0800*/ FFMA R7, R29, R18, R7 ; /* 0x000000121d077223 */
/* 0x000fe20000000007 */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0820*/ IMAD.WIDE R20, R2, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x001fe200078e020e */
/*0830*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fc60007ffe0ff */
/*0840*/ FFMA R7, R9, R28, R7 ; /* 0x0000001c09077223 */
/* 0x010fe20000000007 */
/*0850*/ IADD3.X R9, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff097210 */
/* 0x000fe40000ffe4ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*0870*/ MOV R12, R8 ; /* 0x00000008000c7202 */
/* 0x002fe40000000f00 */
/*0880*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe20000000f00 */
/*0890*/ FFMA R11, R11, R10, R7 ; /* 0x0000000a0b0b7223 */
/* 0x004fe40000000007 */
/*08a0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08b0*/ @!P0 BRA 0xa30 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.WIDE R16, R2.reuse, 0x4, R20 ; /* 0x0000000402107825 */
/* 0x040fe200078e0214 */
/*08d0*/ LDG.E R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea8000c1e1900 */
/*08e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IMAD.WIDE R14, R2, 0x4, R16 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0210 */
/*0900*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0910*/ LDG.E R7, [R12.64+0x4] ; /* 0x000004040c077981 */
/* 0x000ee2000c1e1900 */
/*0920*/ IMAD.WIDE R8, R2, 0x4, R14 ; /* 0x0000000402087825 */
/* 0x000fc600078e020e */
/*0930*/ LDG.E R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000f28000c1e1900 */
/*0940*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000f28000c1e1900 */
/*0950*/ LDG.E R24, [R12.64+0xc] ; /* 0x00000c040c187981 */
/* 0x000168000c1e1900 */
/*0960*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x000f62000c1e1900 */
/*0970*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0980*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0990*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FFMA R10, R10, R20, R11 ; /* 0x000000140a0a7223 */
/* 0x004fc8000000000b */
/*09b0*/ FFMA R7, R7, R18, R10 ; /* 0x0000001207077223 */
/* 0x008fe2000000000a */
/*09c0*/ IADD3 R10, P1, R12, 0x10, RZ ; /* 0x000000100c0a7810 */
/* 0x000fe20007f3e0ff */
/*09d0*/ IMAD.WIDE R20, R2, 0x4, R8 ; /* 0x0000000402147825 */
/* 0x000fc800078e0208 */
/*09e0*/ FFMA R7, R22, R19, R7 ; /* 0x0000001316077223 */
/* 0x010fe20000000007 */
/*09f0*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x001fe40000ffe4ff */
/*0a00*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fe20000000f00 */
/*0a10*/ FFMA R11, R24, R23, R7 ; /* 0x00000017180b7223 */
/* 0x020fe20000000007 */
/*0a20*/ @P0 BRA 0x8c0 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*0a30*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0a40*/ @!P0 BRA 0xb30 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0a50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0a60*/ IMAD R6, R3, c[0x0][0x178], R4 ; /* 0x00005e0003067a24 */
/* 0x002fe400078e0204 */
/*0a70*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x001fce00078e0200 */
/*0a80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0a90*/ IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fca00078e0209 */
/*0aa0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0ab0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0ac0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ad0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ae0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0af0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0b00*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0b10*/ FFMA R11, R4, R10, R11 ; /* 0x0000000a040b7223 */
/* 0x004fcc000000000b */
/*0b20*/ @P0 BRA 0xaa0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0b30*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0b40*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x003fc800078e0200 */
/*0b50*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0b60*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0b70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b80*/ BRA 0xb80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sgemmPfS_S_i
.globl _Z5sgemmPfS_S_i
.p2align 8
.type _Z5sgemmPfS_S_i,@function
_Z5sgemmPfS_S_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_mul_i32 s2, s15, s4
s_cbranch_scc1 .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[6:7], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[14:15], 2
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
.LBB0_2:
s_load_b32 s3, s[8:9], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e64 v0, s3, s5
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_add_i32 s2, s2, s14
v_mov_b32_e32 v1, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sgemmPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sgemmPfS_S_i, .Lfunc_end0-_Z5sgemmPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sgemmPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z5sgemmPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009657c_00000000-6_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sgemmPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i
.globl _Z5sgemmPfS_S_i
.type _Z5sgemmPfS_S_i, @function
_Z5sgemmPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5sgemmPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sgemmPfS_S_i, .-_Z5sgemmPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5sgemmPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sgemmPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgemm.hip"
.globl _Z20__device_stub__sgemmPfS_S_i # -- Begin function _Z20__device_stub__sgemmPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__sgemmPfS_S_i,@function
_Z20__device_stub__sgemmPfS_S_i: # @_Z20__device_stub__sgemmPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sgemmPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__sgemmPfS_S_i, .Lfunc_end0-_Z20__device_stub__sgemmPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sgemmPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sgemmPfS_S_i,@object # @_Z5sgemmPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5sgemmPfS_S_i
.p2align 3, 0x0
_Z5sgemmPfS_S_i:
.quad _Z20__device_stub__sgemmPfS_S_i
.size _Z5sgemmPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sgemmPfS_S_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sgemmPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sgemmPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void backward_avgpool_layer_kernel(int n, int w, int h, int c, float *in_delta, float *out_delta)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if(id >= n) return;
int k = id % c;
id /= c;
int b = id;
int i;
int out_index = (k + c*b);
for(i = 0; i < w*h; ++i){
int in_index = i + h*w*(k + b*c);
in_delta[in_index] += out_delta[out_index] / (w*h);
}
} | code for sm_80
Function : _Z29backward_avgpool_layer_kerneliiiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R8, R8, c[0x0][0xc], R3 ; /* 0x0000030008087a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R5 ; /* 0x0000000008087a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD R7, R7, c[0x0][0x164], RZ ; /* 0x0000590007077a24 */
/* 0x000fca00078e02ff */
/*00a0*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R7.reuse, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x0000620000201400 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD.WIDE R2, R8, R5, c[0x0][0x178] ; /* 0x00005e0008027625 */
/* 0x000fd400078e0205 */
/*0140*/ @!P0 BRA 0x6b0 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R4, R8, R7, RZ ; /* 0x0000000708047224 */
/* 0x003fe200078e02ff */
/*0160*/ IADD3 R9, R7, -R6, RZ ; /* 0x8000000607097210 */
/* 0x000fe20007ffe0ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0180*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*01a0*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*01b0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000e220000001000 */
/*01d0*/ BSSY B0, 0x2c0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*01e0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*01f0*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fe40000000005 */
/*0200*/ FCHK P0, R11, R0 ; /* 0x000000000b007302 */
/* 0x004e240000000000 */
/*0210*/ FFMA R5, R11, R4, RZ ; /* 0x000000040b057223 */
/* 0x000fc800000000ff */
/*0220*/ FFMA R10, -R0, R5, R11 ; /* 0x00000005000a7223 */
/* 0x000fc8000000010b */
/*0230*/ FFMA R10, R4, R10, R5 ; /* 0x0000000a040a7223 */
/* 0x000fe20000000005 */
/*0240*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0260*/ @!P0 BRA 0x2b0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0270*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000b */
/*0280*/ MOV R10, 0x2a0 ; /* 0x000002a0000a7802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000062000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000c */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ MUFU.RCP R15, R0 ; /* 0x00000000000f7308 */
/* 0x000e220000001000 */
/*02e0*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*02f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e8000c101906 */
/*0300*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0310*/ FFMA R10, -R0, R15, 1 ; /* 0x3f800000000a7423 */
/* 0x001fe2000000010f */
/*0320*/ BSSY B0, 0x3e0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0330*/ FFMA R12, R15, R10, R15 ; /* 0x0000000a0f0c7223 */
/* 0x000fe2000000000f */
/*0340*/ FCHK P0, R13, R0 ; /* 0x000000000d007302 */
/* 0x004e260000000000 */
/*0350*/ FFMA R10, R12, R13, RZ ; /* 0x0000000d0c0a7223 */
/* 0x000fc800000000ff */
/*0360*/ FFMA R15, -R0, R10, R13 ; /* 0x0000000a000f7223 */
/* 0x000fc8000000010d */
/*0370*/ FFMA R10, R12, R15, R10 ; /* 0x0000000f0c0a7223 */
/* 0x000fe2000000000a */
/*0380*/ @!P0 BRA 0x3d0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0390*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x002fe200078e000d */
/*03a0*/ MOV R10, 0x3c0 ; /* 0x000003c0000a7802 */
/* 0x000fe40000000f00 */
/*03b0*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000050000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x001fe40000000f00 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*03e0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ MUFU.RCP R15, R0 ; /* 0x00000000000f7308 */
/* 0x000e220000001000 */
/*0400*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*0410*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c101906 */
/*0420*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ FFMA R10, -R0, R15, 1 ; /* 0x3f800000000a7423 */
/* 0x001fe2000000010f */
/*0440*/ BSSY B0, 0x500 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0450*/ FFMA R12, R15, R10, R15 ; /* 0x0000000a0f0c7223 */
/* 0x000fe2000000000f */
/*0460*/ FCHK P0, R13, R0 ; /* 0x000000000d007302 */
/* 0x004e260000000000 */
/*0470*/ FFMA R10, R12, R13, RZ ; /* 0x0000000d0c0a7223 */
/* 0x000fc800000000ff */
/*0480*/ FFMA R15, -R0, R10, R13 ; /* 0x0000000a000f7223 */
/* 0x000fc8000000010d */
/*0490*/ FFMA R10, R12, R15, R10 ; /* 0x0000000f0c0a7223 */
/* 0x000fe2000000000a */
/*04a0*/ @!P0 BRA 0x4f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x002fe200078e000d */
/*04c0*/ MOV R10, 0x4e0 ; /* 0x000004e0000a7802 */
/* 0x000fe40000000f00 */
/*04d0*/ CALL.REL.NOINC 0x8c0 ; /* 0x000003e000007944 */
/* 0x000fea0003c00000 */
/*04e0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000c */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0500*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000806040b7981 */
/* 0x000ea2000c1e1900 */
/*0510*/ MUFU.RCP R15, R0 ; /* 0x00000000000f7308 */
/* 0x000e220000001000 */
/*0520*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*0530*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c101906 */
/*0540*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ FFMA R10, -R0, R15, 1 ; /* 0x3f800000000a7423 */
/* 0x001fe2000000010f */
/*0560*/ BSSY B0, 0x620 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0570*/ FFMA R12, R15, R10, R15 ; /* 0x0000000a0f0c7223 */
/* 0x000fe2000000000f */
/*0580*/ FCHK P0, R13, R0 ; /* 0x000000000d007302 */
/* 0x004e260000000000 */
/*0590*/ FFMA R10, R12, R13, RZ ; /* 0x0000000d0c0a7223 */
/* 0x000fc800000000ff */
/*05a0*/ FFMA R15, -R0, R10, R13 ; /* 0x0000000a000f7223 */
/* 0x000fc8000000010d */
/*05b0*/ FFMA R10, R12, R15, R10 ; /* 0x0000000f0c0a7223 */
/* 0x000fe2000000000a */
/*05c0*/ @!P0 BRA 0x610 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*05d0*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x002fe200078e000d */
/*05e0*/ MOV R10, 0x600 ; /* 0x00000600000a7802 */
/* 0x000fe40000000f00 */
/*05f0*/ CALL.REL.NOINC 0x8c0 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*0600*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x001fe40000000f00 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0620*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c06040b7981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fe20007ffe0ff */
/*0640*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0650*/ IADD3 R12, P1, R4, 0x10, RZ ; /* 0x00000010040c7810 */
/* 0x000fe40007f3e0ff */
/*0660*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*0670*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0605 */
/*0680*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*0690*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0001e6000c101906 */
/*06a0*/ @P0 BRA 0x1b0 ; /* 0xfffffb0000000947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x003fda0003f05270 */
/*06c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD R4, R8, R7, UR4 ; /* 0x0000000408047e24 */
/* 0x000fc8000f8e0207 */
/*06f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*0700*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0710*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe40000000f00 */
/*0720*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x001ea2000c1e1900 */
/*0730*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000e220000001000 */
/*0740*/ BSSY B0, 0x830 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0750*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*0760*/ FFMA R8, R5, R4, R5 ; /* 0x0000000405087223 */
/* 0x000fe40000000005 */
/*0770*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x004e240000000000 */
/*0780*/ FFMA R4, R8, R7, RZ ; /* 0x0000000708047223 */
/* 0x000fc800000000ff */
/*0790*/ FFMA R5, -R0, R4, R7 ; /* 0x0000000400057223 */
/* 0x000fc80000000107 */
/*07a0*/ FFMA R8, R8, R5, R4 ; /* 0x0000000508087223 */
/* 0x000fe40000000004 */
/*07b0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0009 */
/*07c0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*07d0*/ @!P0 BRA 0x820 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*07e0*/ MOV R12, R7 ; /* 0x00000007000c7202 */
/* 0x000fe40000000f00 */
/*07f0*/ MOV R10, 0x810 ; /* 0x00000810000a7802 */
/* 0x000fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0x8c0 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000c */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea2000c1e1900 */
/*0840*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3 R9, P1, R4, 0x4, RZ ; /* 0x0000000404097810 */
/* 0x000fc40007f3e0ff */
/*0860*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0870*/ IMAD.X R10, RZ, RZ, R5, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe400008e0605 */
/*0880*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e6000c101906 */
/*08a0*/ @P0 BRA 0x720 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ SHF.R.U32.HI R13, RZ, 0x17, R0 ; /* 0x00000017ff0d7819 */
/* 0x000fe20000011600 */
/*08d0*/ BSSY B1, 0xf10 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*08e0*/ SHF.R.U32.HI R11, RZ, 0x17, R12 ; /* 0x00000017ff0b7819 */
/* 0x000fe4000001160c */
/*08f0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fe400078ec0ff */
/*0900*/ LOP3.LUT R16, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b107812 */
/* 0x000fe400078ec0ff */
/*0910*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fc40007ffe0ff */
/*0920*/ IADD3 R14, R16, -0x1, RZ ; /* 0xffffffff100e7810 */
/* 0x000fe40007ffe0ff */
/*0930*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fe40003f04070 */
/*0940*/ MOV R15, R0 ; /* 0x00000000000f7202 */
/* 0x000fe40000000f00 */
/*0950*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*0960*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e00ff */
/*0970*/ @!P0 BRA 0xaf0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0980*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f1c200 */
/*0990*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*09a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09b0*/ @P0 BRA 0xef0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*09c0*/ LOP3.LUT P0, RZ, R15, 0x7fffffff, R12, 0xc8, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fda000780c80c */
/*09d0*/ @!P0 BRA 0xed0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*09e0*/ FSETP.NEU.FTZ.AND P2, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f5d200 */
/*09f0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*0a00*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fd60003f1d200 */
/*0a10*/ @!P1 BRA !P2, 0xed0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0a20*/ LOP3.LUT P2, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000784c0ff */
/*0a30*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a40*/ @P1 BRA 0xeb0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0a50*/ LOP3.LUT P1, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000782c0ff */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a70*/ @P0 BRA 0xe80 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a80*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*0a90*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0aa0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e00ff */
/*0ab0*/ @!P0 MOV R11, 0xffffffc0 ; /* 0xffffffc0000b8802 */
/* 0x000fe20000000f00 */
/*0ac0*/ @!P0 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c8823 */
/* 0x000fe400000000ff */
/*0ad0*/ @!P1 FFMA R15, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f800000000f9823 */
/* 0x000fe200000000ff */
/*0ae0*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0af0*/ LEA R14, R13, 0xc0800000, 0x17 ; /* 0xc08000000d0e7811 */
/* 0x000fe200078eb8ff */
/*0b00*/ BSSY B2, 0xe70 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0b10*/ IADD3 R16, R16, -0x7f, RZ ; /* 0xffffff8110107810 */
/* 0x000fc60007ffe0ff */
/*0b20*/ IMAD.IADD R17, R15, 0x1, -R14 ; /* 0x000000010f117824 */
/* 0x000fe400078e0a0e */
/*0b30*/ IMAD R12, R16.reuse, -0x800000, R12 ; /* 0xff800000100c7824 */
/* 0x040fe200078e020c */
/*0b40*/ IADD3 R16, R16, 0x7f, -R13 ; /* 0x0000007f10107810 */
/* 0x000fe20007ffe80d */
/*0b50*/ MUFU.RCP R14, R17 ; /* 0x00000011000e7308 */
/* 0x000e220000001000 */
/*0b60*/ FADD.FTZ R19, -R17, -RZ ; /* 0x800000ff11137221 */
/* 0x000fc60000010100 */
/*0b70*/ IMAD.IADD R16, R16, 0x1, R11 ; /* 0x0000000110107824 */
/* 0x000fe400078e020b */
/*0b80*/ FFMA R15, R14, R19, 1 ; /* 0x3f8000000e0f7423 */
/* 0x001fc80000000013 */
/*0b90*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fc8000000000e */
/*0ba0*/ FFMA R15, R12, R14, RZ ; /* 0x0000000e0c0f7223 */
/* 0x000fc800000000ff */
/*0bb0*/ FFMA R18, R19, R15, R12 ; /* 0x0000000f13127223 */
/* 0x000fc8000000000c */
/*0bc0*/ FFMA R15, R14, R18, R15 ; /* 0x000000120e0f7223 */
/* 0x000fc8000000000f */
/*0bd0*/ FFMA R19, R19, R15, R12 ; /* 0x0000000f13137223 */
/* 0x000fc8000000000c */
/*0be0*/ FFMA R12, R14, R19, R15 ; /* 0x000000130e0c7223 */
/* 0x000fca000000000f */
/*0bf0*/ SHF.R.U32.HI R13, RZ, 0x17, R12 ; /* 0x00000017ff0d7819 */
/* 0x000fc8000001160c */
/*0c00*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fc800078ec0ff */
/*0c10*/ IADD3 R17, R13, R16, RZ ; /* 0x000000100d117210 */
/* 0x000fc80007ffe0ff */
/*0c20*/ IADD3 R11, R17, -0x1, RZ ; /* 0xffffffff110b7810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0c40*/ @!P0 BRA 0xe50 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c50*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*0c60*/ @P0 BRA 0xe20 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0c80*/ @P0 BRA 0xe60 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c90*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0ca0*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fd600078ec0ff */
/*0cb0*/ @!P0 BRA 0xe60 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ FFMA.RZ R11, R14.reuse, R19.reuse, R15.reuse ; /* 0x000000130e0b7223 */
/* 0x1c0fe2000000c00f */
/*0cd0*/ IADD3 R16, R17.reuse, 0x20, RZ ; /* 0x0000002011107810 */
/* 0x040fe40007ffe0ff */
/*0ce0*/ ISETP.NE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f45270 */
/*0cf0*/ LOP3.LUT R13, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0d7812 */
/* 0x000fe200078ec0ff */
/*0d00*/ FFMA.RP R11, R14.reuse, R19.reuse, R15.reuse ; /* 0x000000130e0b7223 */
/* 0x1c0fe2000000800f */
/*0d10*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f25270 */
/*0d20*/ FFMA.RM R14, R14, R19, R15 ; /* 0x000000130e0e7223 */
/* 0x000fe2000000400f */
/*0d30*/ LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d0d7812 */
/* 0x000fe200078efcff */
/*0d40*/ IMAD.MOV R15, RZ, RZ, -R17 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0a11 */
/*0d50*/ SHF.L.U32 R16, R13, R16, RZ ; /* 0x000000100d107219 */
/* 0x000fe400000006ff */
/*0d60*/ FSETP.NEU.FTZ.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720b */
/* 0x000fe40003f1d000 */
/*0d70*/ SEL R14, R15, RZ, P2 ; /* 0x000000ff0f0e7207 */
/* 0x000fe40001000000 */
/*0d80*/ ISETP.NE.AND P1, PT, R16, RZ, P1 ; /* 0x000000ff1000720c */
/* 0x000fe40000f25270 */
/*0d90*/ SHF.R.U32.HI R14, RZ, R14, R13 ; /* 0x0000000eff0e7219 */
/* 0x000fe4000001160d */
/*0da0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0db0*/ SHF.R.U32.HI R16, RZ, 0x1, R14 ; /* 0x00000001ff107819 */
/* 0x000fe4000001160e */
/*0dc0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0dd0*/ LOP3.LUT R11, R11, 0x1, R16, 0xf8, !PT ; /* 0x000000010b0b7812 */
/* 0x000fc800078ef810 */
/*0de0*/ LOP3.LUT R11, R11, R14, RZ, 0xc0, !PT ; /* 0x0000000e0b0b7212 */
/* 0x000fca00078ec0ff */
/*0df0*/ IMAD.IADD R11, R16, 0x1, R11 ; /* 0x00000001100b7824 */
/* 0x000fca00078e020b */
/*0e00*/ LOP3.LUT R12, R11, R12, RZ, 0xfc, !PT ; /* 0x0000000c0b0c7212 */
/* 0x000fe200078efcff */
/*0e10*/ BRA 0xe60 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e20*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fc800078ec0ff */
/*0e30*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0e40*/ BRA 0xe60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e50*/ LEA R12, R16, R12, 0x17 ; /* 0x0000000c100c7211 */
/* 0x000fe400078eb8ff */
/*0e60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e70*/ BRA 0xf00 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e80*/ LOP3.LUT R12, R15, 0x80000000, R12, 0x48, !PT ; /* 0x800000000f0c7812 */
/* 0x000fc800078e480c */
/*0e90*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0ea0*/ BRA 0xf00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0eb0*/ LOP3.LUT R12, R15, 0x80000000, R12, 0x48, !PT ; /* 0x800000000f0c7812 */
/* 0x000fe200078e480c */
/*0ec0*/ BRA 0xf00 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ed0*/ MUFU.RSQ R12, -QNAN ; /* 0xffc00000000c7908 */
/* 0x000e220000001400 */
/*0ee0*/ BRA 0xf00 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ef0*/ FADD.FTZ R12, R12, R0 ; /* 0x000000000c0c7221 */
/* 0x000fe40000010000 */
/*0f00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f10*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0f20*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0d00a007950 */
/* 0x000fea0003c3ffff */
/*0f30*/ BRA 0xf30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void backward_avgpool_layer_kernel(int n, int w, int h, int c, float *in_delta, float *out_delta)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if(id >= n) return;
int k = id % c;
id /= c;
int b = id;
int i;
int out_index = (k + c*b);
for(i = 0; i < w*h; ++i){
int in_index = i + h*w*(k + b*c);
in_delta[in_index] += out_delta[out_index] / (w*h);
}
} | .file "tmpxft_00128afb_00000000-6_backward_avgpool_layer_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_
.type _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_, @function
_Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29backward_avgpool_layer_kerneliiiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_, .-_Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_
.globl _Z29backward_avgpool_layer_kerneliiiiPfS_
.type _Z29backward_avgpool_layer_kerneliiiiPfS_, @function
_Z29backward_avgpool_layer_kerneliiiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z29backward_avgpool_layer_kerneliiiiPfS_, .-_Z29backward_avgpool_layer_kerneliiiiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29backward_avgpool_layer_kerneliiiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29backward_avgpool_layer_kerneliiiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void backward_avgpool_layer_kernel(int n, int w, int h, int c, float *in_delta, float *out_delta)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if(id >= n) return;
int k = id % c;
id /= c;
int b = id;
int i;
int out_index = (k + c*b);
for(i = 0; i < w*h; ++i){
int in_index = i + h*w*(k + b*c);
in_delta[in_index] += out_delta[out_index] / (w*h);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_avgpool_layer_kernel(int n, int w, int h, int c, float *in_delta, float *out_delta)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if(id >= n) return;
int k = id % c;
id /= c;
int b = id;
int i;
int out_index = (k + c*b);
for(i = 0; i < w*h; ++i){
int in_index = i + h*w*(k + b*c);
in_delta[in_index] += out_delta[out_index] / (w*h);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_avgpool_layer_kernel(int n, int w, int h, int c, float *in_delta, float *out_delta)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if(id >= n) return;
int k = id % c;
id /= c;
int b = id;
int i;
int out_index = (k + c*b);
for(i = 0; i < w*h; ++i){
int in_index = i + h*w*(k + b*c);
in_delta[in_index] += out_delta[out_index] / (w*h);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29backward_avgpool_layer_kerneliiiiPfS_
.globl _Z29backward_avgpool_layer_kerneliiiiPfS_
.p2align 8
.type _Z29backward_avgpool_layer_kerneliiiiPfS_,@function
_Z29backward_avgpool_layer_kerneliiiiPfS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v5, v1, s2
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(1)
v_div_scale_f32 v7, null, v4, v4, v5
v_div_scale_f32 v9, vcc_lo, v5, v4, v5
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v8
v_mul_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v10, v9
v_fmac_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v10, v9
v_div_fmas_f32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v7, v4, v5
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29backward_avgpool_layer_kerneliiiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29backward_avgpool_layer_kerneliiiiPfS_, .Lfunc_end0-_Z29backward_avgpool_layer_kerneliiiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29backward_avgpool_layer_kerneliiiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29backward_avgpool_layer_kerneliiiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void backward_avgpool_layer_kernel(int n, int w, int h, int c, float *in_delta, float *out_delta)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if(id >= n) return;
int k = id % c;
id /= c;
int b = id;
int i;
int out_index = (k + c*b);
for(i = 0; i < w*h; ++i){
int in_index = i + h*w*(k + b*c);
in_delta[in_index] += out_delta[out_index] / (w*h);
}
} | .text
.file "backward_avgpool_layer_kernel.hip"
.globl _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_ # -- Begin function _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.p2align 4, 0x90
.type _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_,@function
_Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_: # @_Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29backward_avgpool_layer_kerneliiiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_, .Lfunc_end0-_Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29backward_avgpool_layer_kerneliiiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29backward_avgpool_layer_kerneliiiiPfS_,@object # @_Z29backward_avgpool_layer_kerneliiiiPfS_
.section .rodata,"a",@progbits
.globl _Z29backward_avgpool_layer_kerneliiiiPfS_
.p2align 3, 0x0
_Z29backward_avgpool_layer_kerneliiiiPfS_:
.quad _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.size _Z29backward_avgpool_layer_kerneliiiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29backward_avgpool_layer_kerneliiiiPfS_"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29backward_avgpool_layer_kerneliiiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29backward_avgpool_layer_kerneliiiiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000000087919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R8, R8, c[0x0][0xc], R3 ; /* 0x0000030008087a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R5 ; /* 0x0000000008087a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD R7, R7, c[0x0][0x164], RZ ; /* 0x0000590007077a24 */
/* 0x000fca00078e02ff */
/*00a0*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R7.reuse, -0x1, RZ ; /* 0xffffffff07027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x0000620000201400 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ LOP3.LUT R6, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307067812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD.WIDE R2, R8, R5, c[0x0][0x178] ; /* 0x00005e0008027625 */
/* 0x000fd400078e0205 */
/*0140*/ @!P0 BRA 0x6b0 ; /* 0x0000056000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD R4, R8, R7, RZ ; /* 0x0000000708047224 */
/* 0x003fe200078e02ff */
/*0160*/ IADD3 R9, R7, -R6, RZ ; /* 0x8000000607097210 */
/* 0x000fe20007ffe0ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0180*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*0190*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*01a0*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0005 */
/*01b0*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000e220000001000 */
/*01d0*/ BSSY B0, 0x2c0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*01e0*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*01f0*/ FFMA R4, R5, R4, R5 ; /* 0x0000000405047223 */
/* 0x000fe40000000005 */
/*0200*/ FCHK P0, R11, R0 ; /* 0x000000000b007302 */
/* 0x004e240000000000 */
/*0210*/ FFMA R5, R11, R4, RZ ; /* 0x000000040b057223 */
/* 0x000fc800000000ff */
/*0220*/ FFMA R10, -R0, R5, R11 ; /* 0x00000005000a7223 */
/* 0x000fc8000000010b */
/*0230*/ FFMA R10, R4, R10, R5 ; /* 0x0000000a040a7223 */
/* 0x000fe20000000005 */
/*0240*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe20000000f00 */
/*0250*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0260*/ @!P0 BRA 0x2b0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0270*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000b */
/*0280*/ MOV R10, 0x2a0 ; /* 0x000002a0000a7802 */
/* 0x000fe40000000f00 */
/*0290*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000062000007944 */
/* 0x000fea0003c00000 */
/*02a0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000c */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ MUFU.RCP R15, R0 ; /* 0x00000000000f7308 */
/* 0x000e220000001000 */
/*02e0*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*02f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0003e8000c101906 */
/*0300*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0310*/ FFMA R10, -R0, R15, 1 ; /* 0x3f800000000a7423 */
/* 0x001fe2000000010f */
/*0320*/ BSSY B0, 0x3e0 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0330*/ FFMA R12, R15, R10, R15 ; /* 0x0000000a0f0c7223 */
/* 0x000fe2000000000f */
/*0340*/ FCHK P0, R13, R0 ; /* 0x000000000d007302 */
/* 0x004e260000000000 */
/*0350*/ FFMA R10, R12, R13, RZ ; /* 0x0000000d0c0a7223 */
/* 0x000fc800000000ff */
/*0360*/ FFMA R15, -R0, R10, R13 ; /* 0x0000000a000f7223 */
/* 0x000fc8000000010d */
/*0370*/ FFMA R10, R12, R15, R10 ; /* 0x0000000f0c0a7223 */
/* 0x000fe2000000000a */
/*0380*/ @!P0 BRA 0x3d0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0390*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x002fe200078e000d */
/*03a0*/ MOV R10, 0x3c0 ; /* 0x000003c0000a7802 */
/* 0x000fe40000000f00 */
/*03b0*/ CALL.REL.NOINC 0x8c0 ; /* 0x0000050000007944 */
/* 0x000fea0003c00000 */
/*03c0*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x001fe40000000f00 */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*03e0*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000406040b7981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ MUFU.RCP R15, R0 ; /* 0x00000000000f7308 */
/* 0x000e220000001000 */
/*0400*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*0410*/ STG.E [R4.64+0x4], R11 ; /* 0x0000040b04007986 */
/* 0x0003e8000c101906 */
/*0420*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ FFMA R10, -R0, R15, 1 ; /* 0x3f800000000a7423 */
/* 0x001fe2000000010f */
/*0440*/ BSSY B0, 0x500 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0450*/ FFMA R12, R15, R10, R15 ; /* 0x0000000a0f0c7223 */
/* 0x000fe2000000000f */
/*0460*/ FCHK P0, R13, R0 ; /* 0x000000000d007302 */
/* 0x004e260000000000 */
/*0470*/ FFMA R10, R12, R13, RZ ; /* 0x0000000d0c0a7223 */
/* 0x000fc800000000ff */
/*0480*/ FFMA R15, -R0, R10, R13 ; /* 0x0000000a000f7223 */
/* 0x000fc8000000010d */
/*0490*/ FFMA R10, R12, R15, R10 ; /* 0x0000000f0c0a7223 */
/* 0x000fe2000000000a */
/*04a0*/ @!P0 BRA 0x4f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*04b0*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x002fe200078e000d */
/*04c0*/ MOV R10, 0x4e0 ; /* 0x000004e0000a7802 */
/* 0x000fe40000000f00 */
/*04d0*/ CALL.REL.NOINC 0x8c0 ; /* 0x000003e000007944 */
/* 0x000fea0003c00000 */
/*04e0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e000c */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0500*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000806040b7981 */
/* 0x000ea2000c1e1900 */
/*0510*/ MUFU.RCP R15, R0 ; /* 0x00000000000f7308 */
/* 0x000e220000001000 */
/*0520*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*0530*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c101906 */
/*0540*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ FFMA R10, -R0, R15, 1 ; /* 0x3f800000000a7423 */
/* 0x001fe2000000010f */
/*0560*/ BSSY B0, 0x620 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*0570*/ FFMA R12, R15, R10, R15 ; /* 0x0000000a0f0c7223 */
/* 0x000fe2000000000f */
/*0580*/ FCHK P0, R13, R0 ; /* 0x000000000d007302 */
/* 0x004e260000000000 */
/*0590*/ FFMA R10, R12, R13, RZ ; /* 0x0000000d0c0a7223 */
/* 0x000fc800000000ff */
/*05a0*/ FFMA R15, -R0, R10, R13 ; /* 0x0000000a000f7223 */
/* 0x000fc8000000010d */
/*05b0*/ FFMA R10, R12, R15, R10 ; /* 0x0000000f0c0a7223 */
/* 0x000fe2000000000a */
/*05c0*/ @!P0 BRA 0x610 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*05d0*/ IMAD.MOV.U32 R12, RZ, RZ, R13 ; /* 0x000000ffff0c7224 */
/* 0x002fe200078e000d */
/*05e0*/ MOV R10, 0x600 ; /* 0x00000600000a7802 */
/* 0x000fe40000000f00 */
/*05f0*/ CALL.REL.NOINC 0x8c0 ; /* 0x000002c000007944 */
/* 0x000fea0003c00000 */
/*0600*/ MOV R10, R12 ; /* 0x0000000c000a7202 */
/* 0x001fe40000000f00 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0620*/ LDG.E R11, [R4.64+0xc] ; /* 0x00000c06040b7981 */
/* 0x000ea2000c1e1900 */
/*0630*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fe20007ffe0ff */
/*0640*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0650*/ IADD3 R12, P1, R4, 0x10, RZ ; /* 0x00000010040c7810 */
/* 0x000fe40007f3e0ff */
/*0660*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*0670*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe400008e0605 */
/*0680*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x004fca0000000000 */
/*0690*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0001e6000c101906 */
/*06a0*/ @P0 BRA 0x1b0 ; /* 0xfffffb0000000947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x003fda0003f05270 */
/*06c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD R4, R8, R7, UR4 ; /* 0x0000000408047e24 */
/* 0x000fc8000f8e0207 */
/*06f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0205 */
/*0700*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0710*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe40000000f00 */
/*0720*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x001ea2000c1e1900 */
/*0730*/ MUFU.RCP R5, R0 ; /* 0x0000000000057308 */
/* 0x000e220000001000 */
/*0740*/ BSSY B0, 0x830 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0750*/ FFMA R4, -R0, R5, 1 ; /* 0x3f80000000047423 */
/* 0x001fc80000000105 */
/*0760*/ FFMA R8, R5, R4, R5 ; /* 0x0000000405087223 */
/* 0x000fe40000000005 */
/*0770*/ FCHK P0, R7, R0 ; /* 0x0000000007007302 */
/* 0x004e240000000000 */
/*0780*/ FFMA R4, R8, R7, RZ ; /* 0x0000000708047223 */
/* 0x000fc800000000ff */
/*0790*/ FFMA R5, -R0, R4, R7 ; /* 0x0000000400057223 */
/* 0x000fc80000000107 */
/*07a0*/ FFMA R8, R8, R5, R4 ; /* 0x0000000508087223 */
/* 0x000fe40000000004 */
/*07b0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0009 */
/*07c0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*07d0*/ @!P0 BRA 0x820 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*07e0*/ MOV R12, R7 ; /* 0x00000007000c7202 */
/* 0x000fe40000000f00 */
/*07f0*/ MOV R10, 0x810 ; /* 0x00000810000a7802 */
/* 0x000fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0x8c0 ; /* 0x000000b000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000c */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea2000c1e1900 */
/*0840*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3 R9, P1, R4, 0x4, RZ ; /* 0x0000000404097810 */
/* 0x000fc40007f3e0ff */
/*0860*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0870*/ IMAD.X R10, RZ, RZ, R5, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe400008e0605 */
/*0880*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e6000c101906 */
/*08a0*/ @P0 BRA 0x720 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*08b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08c0*/ SHF.R.U32.HI R13, RZ, 0x17, R0 ; /* 0x00000017ff0d7819 */
/* 0x000fe20000011600 */
/*08d0*/ BSSY B1, 0xf10 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*08e0*/ SHF.R.U32.HI R11, RZ, 0x17, R12 ; /* 0x00000017ff0b7819 */
/* 0x000fe4000001160c */
/*08f0*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fe400078ec0ff */
/*0900*/ LOP3.LUT R16, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b107812 */
/* 0x000fe400078ec0ff */
/*0910*/ IADD3 R17, R13, -0x1, RZ ; /* 0xffffffff0d117810 */
/* 0x000fc40007ffe0ff */
/*0920*/ IADD3 R14, R16, -0x1, RZ ; /* 0xffffffff100e7810 */
/* 0x000fe40007ffe0ff */
/*0930*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fe40003f04070 */
/*0940*/ MOV R15, R0 ; /* 0x00000000000f7202 */
/* 0x000fe40000000f00 */
/*0950*/ ISETP.GT.U32.OR P0, PT, R14, 0xfd, P0 ; /* 0x000000fd0e00780c */
/* 0x000fda0000704470 */
/*0960*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e00ff */
/*0970*/ @!P0 BRA 0xaf0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0980*/ FSETP.GTU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f1c200 */
/*0990*/ FSETP.GTU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f3c200 */
/*09a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*09b0*/ @P0 BRA 0xef0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*09c0*/ LOP3.LUT P0, RZ, R15, 0x7fffffff, R12, 0xc8, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fda000780c80c */
/*09d0*/ @!P0 BRA 0xed0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*09e0*/ FSETP.NEU.FTZ.AND P2, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f5d200 */
/*09f0*/ FSETP.NEU.FTZ.AND P1, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe40003f3d200 */
/*0a00*/ FSETP.NEU.FTZ.AND P0, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fd60003f1d200 */
/*0a10*/ @!P1 BRA !P2, 0xed0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0a20*/ LOP3.LUT P2, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000784c0ff */
/*0a30*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0a40*/ @P1 BRA 0xeb0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0a50*/ LOP3.LUT P1, RZ, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0fff7812 */
/* 0x000fc8000782c0ff */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a70*/ @P0 BRA 0xe80 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a80*/ ISETP.GE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f06270 */
/*0a90*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0aa0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e00ff */
/*0ab0*/ @!P0 MOV R11, 0xffffffc0 ; /* 0xffffffc0000b8802 */
/* 0x000fe20000000f00 */
/*0ac0*/ @!P0 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c8823 */
/* 0x000fe400000000ff */
/*0ad0*/ @!P1 FFMA R15, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f800000000f9823 */
/* 0x000fe200000000ff */
/*0ae0*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0af0*/ LEA R14, R13, 0xc0800000, 0x17 ; /* 0xc08000000d0e7811 */
/* 0x000fe200078eb8ff */
/*0b00*/ BSSY B2, 0xe70 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0b10*/ IADD3 R16, R16, -0x7f, RZ ; /* 0xffffff8110107810 */
/* 0x000fc60007ffe0ff */
/*0b20*/ IMAD.IADD R17, R15, 0x1, -R14 ; /* 0x000000010f117824 */
/* 0x000fe400078e0a0e */
/*0b30*/ IMAD R12, R16.reuse, -0x800000, R12 ; /* 0xff800000100c7824 */
/* 0x040fe200078e020c */
/*0b40*/ IADD3 R16, R16, 0x7f, -R13 ; /* 0x0000007f10107810 */
/* 0x000fe20007ffe80d */
/*0b50*/ MUFU.RCP R14, R17 ; /* 0x00000011000e7308 */
/* 0x000e220000001000 */
/*0b60*/ FADD.FTZ R19, -R17, -RZ ; /* 0x800000ff11137221 */
/* 0x000fc60000010100 */
/*0b70*/ IMAD.IADD R16, R16, 0x1, R11 ; /* 0x0000000110107824 */
/* 0x000fe400078e020b */
/*0b80*/ FFMA R15, R14, R19, 1 ; /* 0x3f8000000e0f7423 */
/* 0x001fc80000000013 */
/*0b90*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fc8000000000e */
/*0ba0*/ FFMA R15, R12, R14, RZ ; /* 0x0000000e0c0f7223 */
/* 0x000fc800000000ff */
/*0bb0*/ FFMA R18, R19, R15, R12 ; /* 0x0000000f13127223 */
/* 0x000fc8000000000c */
/*0bc0*/ FFMA R15, R14, R18, R15 ; /* 0x000000120e0f7223 */
/* 0x000fc8000000000f */
/*0bd0*/ FFMA R19, R19, R15, R12 ; /* 0x0000000f13137223 */
/* 0x000fc8000000000c */
/*0be0*/ FFMA R12, R14, R19, R15 ; /* 0x000000130e0c7223 */
/* 0x000fca000000000f */
/*0bf0*/ SHF.R.U32.HI R13, RZ, 0x17, R12 ; /* 0x00000017ff0d7819 */
/* 0x000fc8000001160c */
/*0c00*/ LOP3.LUT R13, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0d7812 */
/* 0x000fc800078ec0ff */
/*0c10*/ IADD3 R17, R13, R16, RZ ; /* 0x000000100d117210 */
/* 0x000fc80007ffe0ff */
/*0c20*/ IADD3 R11, R17, -0x1, RZ ; /* 0xffffffff110b7810 */
/* 0x000fc80007ffe0ff */
/*0c30*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0c40*/ @!P0 BRA 0xe50 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0c50*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*0c60*/ @P0 BRA 0xe20 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0c80*/ @P0 BRA 0xe60 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c90*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0ca0*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fd600078ec0ff */
/*0cb0*/ @!P0 BRA 0xe60 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ FFMA.RZ R11, R14.reuse, R19.reuse, R15.reuse ; /* 0x000000130e0b7223 */
/* 0x1c0fe2000000c00f */
/*0cd0*/ IADD3 R16, R17.reuse, 0x20, RZ ; /* 0x0000002011107810 */
/* 0x040fe40007ffe0ff */
/*0ce0*/ ISETP.NE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f45270 */
/*0cf0*/ LOP3.LUT R13, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0d7812 */
/* 0x000fe200078ec0ff */
/*0d00*/ FFMA.RP R11, R14.reuse, R19.reuse, R15.reuse ; /* 0x000000130e0b7223 */
/* 0x1c0fe2000000800f */
/*0d10*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f25270 */
/*0d20*/ FFMA.RM R14, R14, R19, R15 ; /* 0x000000130e0e7223 */
/* 0x000fe2000000400f */
/*0d30*/ LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d0d7812 */
/* 0x000fe200078efcff */
/*0d40*/ IMAD.MOV R15, RZ, RZ, -R17 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e0a11 */
/*0d50*/ SHF.L.U32 R16, R13, R16, RZ ; /* 0x000000100d107219 */
/* 0x000fe400000006ff */
/*0d60*/ FSETP.NEU.FTZ.AND P0, PT, R11, R14, PT ; /* 0x0000000e0b00720b */
/* 0x000fe40003f1d000 */
/*0d70*/ SEL R14, R15, RZ, P2 ; /* 0x000000ff0f0e7207 */
/* 0x000fe40001000000 */
/*0d80*/ ISETP.NE.AND P1, PT, R16, RZ, P1 ; /* 0x000000ff1000720c */
/* 0x000fe40000f25270 */
/*0d90*/ SHF.R.U32.HI R14, RZ, R14, R13 ; /* 0x0000000eff0e7219 */
/* 0x000fe4000001160d */
/*0da0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0db0*/ SHF.R.U32.HI R16, RZ, 0x1, R14 ; /* 0x00000001ff107819 */
/* 0x000fe4000001160e */
/*0dc0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0dd0*/ LOP3.LUT R11, R11, 0x1, R16, 0xf8, !PT ; /* 0x000000010b0b7812 */
/* 0x000fc800078ef810 */
/*0de0*/ LOP3.LUT R11, R11, R14, RZ, 0xc0, !PT ; /* 0x0000000e0b0b7212 */
/* 0x000fca00078ec0ff */
/*0df0*/ IMAD.IADD R11, R16, 0x1, R11 ; /* 0x00000001100b7824 */
/* 0x000fca00078e020b */
/*0e00*/ LOP3.LUT R12, R11, R12, RZ, 0xfc, !PT ; /* 0x0000000c0b0c7212 */
/* 0x000fe200078efcff */
/*0e10*/ BRA 0xe60 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0e20*/ LOP3.LUT R12, R12, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000c0c7812 */
/* 0x000fc800078ec0ff */
/*0e30*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0e40*/ BRA 0xe60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e50*/ LEA R12, R16, R12, 0x17 ; /* 0x0000000c100c7211 */
/* 0x000fe400078eb8ff */
/*0e60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e70*/ BRA 0xf00 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e80*/ LOP3.LUT R12, R15, 0x80000000, R12, 0x48, !PT ; /* 0x800000000f0c7812 */
/* 0x000fc800078e480c */
/*0e90*/ LOP3.LUT R12, R12, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000c0c7812 */
/* 0x000fe200078efcff */
/*0ea0*/ BRA 0xf00 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0eb0*/ LOP3.LUT R12, R15, 0x80000000, R12, 0x48, !PT ; /* 0x800000000f0c7812 */
/* 0x000fe200078e480c */
/*0ec0*/ BRA 0xf00 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0ed0*/ MUFU.RSQ R12, -QNAN ; /* 0xffc00000000c7908 */
/* 0x000e220000001400 */
/*0ee0*/ BRA 0xf00 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ef0*/ FADD.FTZ R12, R12, R0 ; /* 0x000000000c0c7221 */
/* 0x000fe40000010000 */
/*0f00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f10*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0f20*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff0d00a007950 */
/* 0x000fea0003c3ffff */
/*0f30*/ BRA 0xf30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29backward_avgpool_layer_kerneliiiiPfS_
.globl _Z29backward_avgpool_layer_kerneliiiiPfS_
.p2align 8
.type _Z29backward_avgpool_layer_kerneliiiiPfS_,@function
_Z29backward_avgpool_layer_kerneliiiiPfS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v5, v1, s2
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v[2:3], off
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(1)
v_div_scale_f32 v7, null, v4, v4, v5
v_div_scale_f32 v9, vcc_lo, v5, v4, v5
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v10, v8
v_mul_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v10, v9
v_fmac_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v10, v9
v_div_fmas_f32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v7, v4, v5
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29backward_avgpool_layer_kerneliiiiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z29backward_avgpool_layer_kerneliiiiPfS_, .Lfunc_end0-_Z29backward_avgpool_layer_kerneliiiiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29backward_avgpool_layer_kerneliiiiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29backward_avgpool_layer_kerneliiiiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00128afb_00000000-6_backward_avgpool_layer_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_
.type _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_, @function
_Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29backward_avgpool_layer_kerneliiiiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_, .-_Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_
.globl _Z29backward_avgpool_layer_kerneliiiiPfS_
.type _Z29backward_avgpool_layer_kerneliiiiPfS_, @function
_Z29backward_avgpool_layer_kerneliiiiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z29backward_avgpool_layer_kerneliiiiPfS_iiiiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z29backward_avgpool_layer_kerneliiiiPfS_, .-_Z29backward_avgpool_layer_kerneliiiiPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z29backward_avgpool_layer_kerneliiiiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z29backward_avgpool_layer_kerneliiiiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "backward_avgpool_layer_kernel.hip"
.globl _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_ # -- Begin function _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.p2align 4, 0x90
.type _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_,@function
_Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_: # @_Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29backward_avgpool_layer_kerneliiiiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_, .Lfunc_end0-_Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29backward_avgpool_layer_kerneliiiiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z29backward_avgpool_layer_kerneliiiiPfS_,@object # @_Z29backward_avgpool_layer_kerneliiiiPfS_
.section .rodata,"a",@progbits
.globl _Z29backward_avgpool_layer_kerneliiiiPfS_
.p2align 3, 0x0
_Z29backward_avgpool_layer_kerneliiiiPfS_:
.quad _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.size _Z29backward_avgpool_layer_kerneliiiiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z29backward_avgpool_layer_kerneliiiiPfS_"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z44__device_stub__backward_avgpool_layer_kerneliiiiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z29backward_avgpool_layer_kerneliiiiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <time.h>
#include <math.h>
#include <unistd.h>
#include <curand.h>
#include <curand_kernel.h>
#define ISLAND 6
#define POPULATION 20
#define FACILITY 20
#define GENERATION 1
#define CROSSOVER 0.6
#define MUTATION 0.03
#define MIGRATION 15
#define INDIVIDUAL 5
#define H 15 // BAY height
#define W 10 // BAY width
__global__ void init(unsigned int seed, curandState_t* states) {
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
/* we have to initialize the state */
curand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
0, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[x]);
}
__global__ void randomData(curandState_t* states, short* GA){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
for(int j=0;j<FACILITY;j++){ // setup
GA[x*FACILITY + j] = j;
}
int i; // shuffle
for(i = 0; i < FACILITY; i++) {
short k = curand(&states[x]) % FACILITY;
int tmp = GA[x*FACILITY + i];
GA[x*FACILITY + i] = GA[x*FACILITY + k];
GA[x*FACILITY + k] = tmp;
}
}
__global__ void randomBay(curandState_t* states, bool* GB){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
int i; // shuffle
for(i = 0; i < FACILITY-1; i++) {
GB[x*(FACILITY-1) + i] = curand(&states[x]) % 2;
}
}
__global__ void calPosition(short *data, bool *bay, float *position){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
short posit = x * FACILITY;
short bayposit = x * (FACILITY-1);
// int posit=b*POPULATION*FACILITY+t*FACILITY; //執行緒在陣列中對應的位置
// int posofposit = b*POPULATION*FACILITY*2+t*FACILITY*2;
for(int i=0;i<ISLAND*POPULATION*FACILITY*2;i++){
position[i] = 0;
}
short len = 1;
short next = 0;
for(short f=0;f<FACILITY;f++){
if(bay[bayposit+f] == 0){
len = len + 1;
}
if(bay[bayposit+f] == 1 || f == FACILITY - 1 ){
if(f == FACILITY - 1 && bay[bayposit+f] == 0){
len = len - 1;
}
float x = W / 2.0 + next;
for(short j=0;j<len;j++){
position[posit*2+(f+j-len+1)*2] = x;
float y = H / (len * 2.0) * ( (j * 2) + 1) ;
position[posit*2+(f+j-len+1)*2+1] = y;
}
len = 1;
next = next + W;
}
}
}
int main(){
float START, END;
START = clock();
curandState_t* states;
cudaMalloc((void**) &states, ISLAND * POPULATION * sizeof(curandState_t));
// init seed
init<<<ISLAND, POPULATION>>>(time(NULL), states);
// generate random data
short *GA;
cudaMalloc((void**)&GA, ISLAND*POPULATION*FACILITY*sizeof(short));
bool *GB;
cudaMalloc((void**)&GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool));
randomData<<<ISLAND, POPULATION>>>(states, GA);
randomBay<<<ISLAND, POPULATION>>>(states, GB);
short data[ISLAND][POPULATION][FACILITY];
bool bay[ISLAND][POPULATION][FACILITY-1];
cudaMemcpy(data, GA, ISLAND*POPULATION*FACILITY*sizeof(short), cudaMemcpyDeviceToHost);
cudaMemcpy(bay, GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool), cudaMemcpyDeviceToHost);
// print data
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY;k++){
printf("%hu ", data[i][j][k]);
}
printf("\n");
}
}
// print bay
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY-1;k++){
printf("%d ", bay[i][j][k]);
}
printf("\n");
}
}
FILE *fPtr;
int ttt = FACILITY * (FACILITY-1) ;
fPtr=fopen("cost.txt","r");
int cost[FACILITY][FACILITY] = {0};
int temp[ttt][3]; // cost
for(int i=0;i<ttt;i++){
fscanf(fPtr , "%d %d %d" , &temp[i][0], &temp[i][1], &temp[i][2]);
}
fclose(fPtr);
for(int i=0;i<ttt;i++){ // 2 dimention cost
cost[ temp[i][0]-1 ][ temp[i][1]-1] = temp[i][2];
}
for(int i=0;i<FACILITY;i++){
for(int j=0;j<FACILITY;j++){
printf("%d ", cost[i][j]);
}
printf("\n");
}
int *Gcost;
cudaMalloc((void**)&Gcost, FACILITY*FACILITY*sizeof(int));
cudaMemcpy(Gcost, cost, FACILITY*FACILITY*sizeof(int), cudaMemcpyHostToDevice);
for(int gggggg=0;gggggg<GENERATION;gggggg++){ // generation start
float *Gposition;
cudaMalloc((void**)&Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float));
// calculate position
calPosition<<<ISLAND, POPULATION>>>(GA, GB, Gposition);
float position[ISLAND][POPULATION][FACILITY][2];
cudaMemcpy(position, Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<ISLAND;i++){
for(int p=0;p<POPULATION;p++){
for(int f=0;f<FACILITY;f++){
for(int t=0;t<2;t++){
printf("%.2f ", position[i][p][f][t]);
}
printf("\n");
}
}
}
} // generation end
END = clock();
printf("%f\n", (END - START) / CLOCKS_PER_SEC);
return 0;
} | .file "tmpxft_000c0e4d_00000000-6_ff.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2287:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2287:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.type _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, @function
_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW:
.LFB2309:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initjP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2309:
.size _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, .-_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.globl _Z4initjP17curandStateXORWOW
.type _Z4initjP17curandStateXORWOW, @function
_Z4initjP17curandStateXORWOW:
.LFB2310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2310:
.size _Z4initjP17curandStateXORWOW, .-_Z4initjP17curandStateXORWOW
.globl _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
.type _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs, @function
_Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs:
.LFB2311:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10randomDataP17curandStateXORWOWPs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2311:
.size _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs, .-_Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
.globl _Z10randomDataP17curandStateXORWOWPs
.type _Z10randomDataP17curandStateXORWOWPs, @function
_Z10randomDataP17curandStateXORWOWPs:
.LFB2312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2312:
.size _Z10randomDataP17curandStateXORWOWPs, .-_Z10randomDataP17curandStateXORWOWPs
.globl _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
.type _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb, @function
_Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb:
.LFB2313:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9randomBayP17curandStateXORWOWPb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2313:
.size _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb, .-_Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
.globl _Z9randomBayP17curandStateXORWOWPb
.type _Z9randomBayP17curandStateXORWOWPb, @function
_Z9randomBayP17curandStateXORWOWPb:
.LFB2314:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2314:
.size _Z9randomBayP17curandStateXORWOWPb, .-_Z9randomBayP17curandStateXORWOWPb
.globl _Z35__device_stub__Z11calPositionPsPbPfPsPbPf
.type _Z35__device_stub__Z11calPositionPsPbPfPsPbPf, @function
_Z35__device_stub__Z11calPositionPsPbPfPsPbPf:
.LFB2315:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11calPositionPsPbPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2315:
.size _Z35__device_stub__Z11calPositionPsPbPfPsPbPf, .-_Z35__device_stub__Z11calPositionPsPbPfPsPbPf
.globl _Z11calPositionPsPbPf
.type _Z11calPositionPsPbPf, @function
_Z11calPositionPsPbPf:
.LFB2316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11calPositionPsPbPfPsPbPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2316:
.size _Z11calPositionPsPbPf, .-_Z11calPositionPsPbPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%hu "
.LC1:
.string "\n"
.LC2:
.string "%d "
.LC3:
.string "r"
.LC4:
.string "cost.txt"
.LC5:
.string "%d %d %d"
.LC6:
.string "%.2f "
.LC8:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2284:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
leaq -24576(%rsp), %r11
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
subq $3416, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
call clock@PLT
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
movss %xmm1, -28028(%rbp)
leaq -28016(%rbp), %rdi
movl $5760, %esi
call cudaMalloc@PLT
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L36:
leaq -28008(%rbp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
leaq -28000(%rbp), %rdi
movl $2280, %esi
call cudaMalloc@PLT
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L37:
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L38:
leaq -24064(%rbp), %rdi
movl $2, %ecx
movl $4800, %edx
movq -28008(%rbp), %rsi
call cudaMemcpy@PLT
leaq -26352(%rbp), %rdi
movl $2, %ecx
movl $2280, %edx
movq -28000(%rbp), %rsi
call cudaMemcpy@PLT
leaq -23224(%rbp), %r14
movq $0, -28024(%rbp)
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L39
.L71:
movq -28016(%rbp), %rbx
movl $0, %edi
call time@PLT
movq %rbx, %rsi
movl %eax, %edi
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
jmp .L36
.L72:
movq -28008(%rbp), %rsi
movq -28016(%rbp), %rdi
call _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
jmp .L37
.L73:
movq -28000(%rbp), %rsi
movq -28016(%rbp), %rdi
call _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
jmp .L38
.L74:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %r12
cmpq %r14, %r12
je .L41
.L43:
leaq -40(%r12), %rbx
.L40:
movswl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $2, %rbx
cmpq %r12, %rbx
jne .L40
jmp .L74
.L41:
addq $800, %r14
addq $800, -28024(%rbp)
movq -28024(%rbp), %rax
cmpq $4800, %rax
je .L75
.L39:
leaq -800(%r14), %r12
jmp .L43
.L75:
leaq -26352(%rbp), %r14
movq $0, -28024(%rbp)
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L42
.L76:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $19, %r12
cmpq %r14, %r12
je .L45
.L47:
movl $0, %ebx
.L44:
movzbl (%r12,%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $19, %rbx
jne .L44
jmp .L76
.L45:
addq $380, -28024(%rbp)
movq -28024(%rbp), %rax
cmpq $2280, %rax
je .L46
.L42:
movq %r14, %r12
addq $380, %r14
jmp .L47
.L46:
leaq .LC3(%rip), %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, %r14
leaq -27952(%rbp), %rdi
movl $200, %ecx
movl $0, %eax
rep stosq
leaq -4096(%rsp), %rax
.L48:
cmpq %rax, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
subq $464, %rsp
orq $0, 456(%rsp)
movq %rsp, %rbx
movq %rbx, %r12
leaq 4560(%rbx), %r13
leaq .LC5(%rip), %r15
.L51:
leaq 4(%rbx), %rcx
leaq 8(%rbx), %r8
movq %rbx, %rdx
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $12, %rbx
cmpq %r13, %rbx
jne .L51
movq %r14, %rdi
call fclose@PLT
.L52:
movl 4(%r12), %eax
leal -1(%rax), %edx
movslq %edx, %rdx
movl (%r12), %eax
subl $1, %eax
cltq
leaq (%rax,%rax,4), %rax
leaq (%rdx,%rax,4), %rax
movl 8(%r12), %edx
movl %edx, -27952(%rbp,%rax,4)
addq $12, %r12
cmpq %r13, %r12
jne .L52
leaq -27872(%rbp), %r12
leaq -26272(%rbp), %r15
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r14
.L53:
leaq -80(%r12), %rbx
.L54:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L54
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $80, %r12
cmpq %r15, %r12
jne .L53
leaq -27992(%rbp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq -27952(%rbp), %rsi
movl $1, %ecx
movl $1600, %edx
movq -27992(%rbp), %rdi
call cudaMemcpy@PLT
leaq -27984(%rbp), %rdi
movl $19200, %esi
call cudaMalloc@PLT
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L56:
leaq -19264(%rbp), %rdi
movl $2, %ecx
movl $19200, %edx
movq -27984(%rbp), %rsi
call cudaMemcpy@PLT
leaq -15904(%rbp), %r15
movq $0, -28024(%rbp)
leaq .LC6(%rip), %r12
leaq .LC1(%rip), %r14
.L57:
leaq -3200(%r15), %r13
.L61:
leaq -160(%r13), %rbx
.L58:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbx, %r13
jne .L58
addq $160, %r13
cmpq %r15, %r13
jne .L61
addq $3200, %r15
addq $3200, -28024(%rbp)
movq -28024(%rbp), %rax
cmpq $19200, %rax
jne .L57
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
subss -28028(%rbp), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L77:
.cfi_restore_state
movq -27984(%rbp), %rdx
movq -28000(%rbp), %rsi
movq -28008(%rbp), %rdi
call _Z35__device_stub__Z11calPositionPsPbPfPsPbPf
jmp .L56
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2284:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11calPositionPsPbPf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z9randomBayP17curandStateXORWOWPb"
.align 8
.LC11:
.string "_Z10randomDataP17curandStateXORWOWPs"
.section .rodata.str1.1
.LC12:
.string "_Z4initjP17curandStateXORWOW"
.LC13:
.string "precalc_xorwow_matrix"
.LC14:
.string "precalc_xorwow_offset_matrix"
.LC15:
.string "mrg32k3aM1"
.LC16:
.string "mrg32k3aM2"
.LC17:
.string "mrg32k3aM1SubSeq"
.LC18:
.string "mrg32k3aM2SubSeq"
.LC19:
.string "mrg32k3aM1Seq"
.LC20:
.string "mrg32k3aM2Seq"
.LC21:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2318:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calPositionPsPbPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9randomBayP17curandStateXORWOWPb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10randomDataP17curandStateXORWOWPs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initjP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2318:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <time.h>
#include <math.h>
#include <unistd.h>
#include <curand.h>
#include <curand_kernel.h>
#define ISLAND 6
#define POPULATION 20
#define FACILITY 20
#define GENERATION 1
#define CROSSOVER 0.6
#define MUTATION 0.03
#define MIGRATION 15
#define INDIVIDUAL 5
#define H 15 // BAY height
#define W 10 // BAY width
__global__ void init(unsigned int seed, curandState_t* states) {
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
/* we have to initialize the state */
curand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
0, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[x]);
}
__global__ void randomData(curandState_t* states, short* GA){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
for(int j=0;j<FACILITY;j++){ // setup
GA[x*FACILITY + j] = j;
}
int i; // shuffle
for(i = 0; i < FACILITY; i++) {
short k = curand(&states[x]) % FACILITY;
int tmp = GA[x*FACILITY + i];
GA[x*FACILITY + i] = GA[x*FACILITY + k];
GA[x*FACILITY + k] = tmp;
}
}
__global__ void randomBay(curandState_t* states, bool* GB){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
int i; // shuffle
for(i = 0; i < FACILITY-1; i++) {
GB[x*(FACILITY-1) + i] = curand(&states[x]) % 2;
}
}
__global__ void calPosition(short *data, bool *bay, float *position){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
short posit = x * FACILITY;
short bayposit = x * (FACILITY-1);
// int posit=b*POPULATION*FACILITY+t*FACILITY; //執行緒在陣列中對應的位置
// int posofposit = b*POPULATION*FACILITY*2+t*FACILITY*2;
for(int i=0;i<ISLAND*POPULATION*FACILITY*2;i++){
position[i] = 0;
}
short len = 1;
short next = 0;
for(short f=0;f<FACILITY;f++){
if(bay[bayposit+f] == 0){
len = len + 1;
}
if(bay[bayposit+f] == 1 || f == FACILITY - 1 ){
if(f == FACILITY - 1 && bay[bayposit+f] == 0){
len = len - 1;
}
float x = W / 2.0 + next;
for(short j=0;j<len;j++){
position[posit*2+(f+j-len+1)*2] = x;
float y = H / (len * 2.0) * ( (j * 2) + 1) ;
position[posit*2+(f+j-len+1)*2+1] = y;
}
len = 1;
next = next + W;
}
}
}
int main(){
float START, END;
START = clock();
curandState_t* states;
cudaMalloc((void**) &states, ISLAND * POPULATION * sizeof(curandState_t));
// init seed
init<<<ISLAND, POPULATION>>>(time(NULL), states);
// generate random data
short *GA;
cudaMalloc((void**)&GA, ISLAND*POPULATION*FACILITY*sizeof(short));
bool *GB;
cudaMalloc((void**)&GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool));
randomData<<<ISLAND, POPULATION>>>(states, GA);
randomBay<<<ISLAND, POPULATION>>>(states, GB);
short data[ISLAND][POPULATION][FACILITY];
bool bay[ISLAND][POPULATION][FACILITY-1];
cudaMemcpy(data, GA, ISLAND*POPULATION*FACILITY*sizeof(short), cudaMemcpyDeviceToHost);
cudaMemcpy(bay, GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool), cudaMemcpyDeviceToHost);
// print data
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY;k++){
printf("%hu ", data[i][j][k]);
}
printf("\n");
}
}
// print bay
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY-1;k++){
printf("%d ", bay[i][j][k]);
}
printf("\n");
}
}
FILE *fPtr;
int ttt = FACILITY * (FACILITY-1) ;
fPtr=fopen("cost.txt","r");
int cost[FACILITY][FACILITY] = {0};
int temp[ttt][3]; // cost
for(int i=0;i<ttt;i++){
fscanf(fPtr , "%d %d %d" , &temp[i][0], &temp[i][1], &temp[i][2]);
}
fclose(fPtr);
for(int i=0;i<ttt;i++){ // 2 dimention cost
cost[ temp[i][0]-1 ][ temp[i][1]-1] = temp[i][2];
}
for(int i=0;i<FACILITY;i++){
for(int j=0;j<FACILITY;j++){
printf("%d ", cost[i][j]);
}
printf("\n");
}
int *Gcost;
cudaMalloc((void**)&Gcost, FACILITY*FACILITY*sizeof(int));
cudaMemcpy(Gcost, cost, FACILITY*FACILITY*sizeof(int), cudaMemcpyHostToDevice);
for(int gggggg=0;gggggg<GENERATION;gggggg++){ // generation start
float *Gposition;
cudaMalloc((void**)&Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float));
// calculate position
calPosition<<<ISLAND, POPULATION>>>(GA, GB, Gposition);
float position[ISLAND][POPULATION][FACILITY][2];
cudaMemcpy(position, Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float), cudaMemcpyDeviceToHost);
for(int i=0;i<ISLAND;i++){
for(int p=0;p<POPULATION;p++){
for(int f=0;f<FACILITY;f++){
for(int t=0;t<2;t++){
printf("%.2f ", position[i][p][f][t]);
}
printf("\n");
}
}
}
} // generation end
END = clock();
printf("%f\n", (END - START) / CLOCKS_PER_SEC);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <math.h>
#include <unistd.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define ISLAND 6
#define POPULATION 20
#define FACILITY 20
#define GENERATION 1
#define CROSSOVER 0.6
#define MUTATION 0.03
#define MIGRATION 15
#define INDIVIDUAL 5
#define H 15 // BAY height
#define W 10 // BAY width
__global__ void init(unsigned int seed, hiprandState_t* states) {
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
/* we have to initialize the state */
hiprand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
0, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[x]);
}
__global__ void randomData(hiprandState_t* states, short* GA){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
for(int j=0;j<FACILITY;j++){ // setup
GA[x*FACILITY + j] = j;
}
int i; // shuffle
for(i = 0; i < FACILITY; i++) {
short k = hiprand(&states[x]) % FACILITY;
int tmp = GA[x*FACILITY + i];
GA[x*FACILITY + i] = GA[x*FACILITY + k];
GA[x*FACILITY + k] = tmp;
}
}
__global__ void randomBay(hiprandState_t* states, bool* GB){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
int i; // shuffle
for(i = 0; i < FACILITY-1; i++) {
GB[x*(FACILITY-1) + i] = hiprand(&states[x]) % 2;
}
}
__global__ void calPosition(short *data, bool *bay, float *position){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
short posit = x * FACILITY;
short bayposit = x * (FACILITY-1);
// int posit=b*POPULATION*FACILITY+t*FACILITY; //執行緒在陣列中對應的位置
// int posofposit = b*POPULATION*FACILITY*2+t*FACILITY*2;
for(int i=0;i<ISLAND*POPULATION*FACILITY*2;i++){
position[i] = 0;
}
short len = 1;
short next = 0;
for(short f=0;f<FACILITY;f++){
if(bay[bayposit+f] == 0){
len = len + 1;
}
if(bay[bayposit+f] == 1 || f == FACILITY - 1 ){
if(f == FACILITY - 1 && bay[bayposit+f] == 0){
len = len - 1;
}
float x = W / 2.0 + next;
for(short j=0;j<len;j++){
position[posit*2+(f+j-len+1)*2] = x;
float y = H / (len * 2.0) * ( (j * 2) + 1) ;
position[posit*2+(f+j-len+1)*2+1] = y;
}
len = 1;
next = next + W;
}
}
}
int main(){
float START, END;
START = clock();
hiprandState_t* states;
hipMalloc((void**) &states, ISLAND * POPULATION * sizeof(hiprandState_t));
// init seed
init<<<ISLAND, POPULATION>>>(time(NULL), states);
// generate random data
short *GA;
hipMalloc((void**)&GA, ISLAND*POPULATION*FACILITY*sizeof(short));
bool *GB;
hipMalloc((void**)&GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool));
randomData<<<ISLAND, POPULATION>>>(states, GA);
randomBay<<<ISLAND, POPULATION>>>(states, GB);
short data[ISLAND][POPULATION][FACILITY];
bool bay[ISLAND][POPULATION][FACILITY-1];
hipMemcpy(data, GA, ISLAND*POPULATION*FACILITY*sizeof(short), hipMemcpyDeviceToHost);
hipMemcpy(bay, GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool), hipMemcpyDeviceToHost);
// print data
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY;k++){
printf("%hu ", data[i][j][k]);
}
printf("\n");
}
}
// print bay
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY-1;k++){
printf("%d ", bay[i][j][k]);
}
printf("\n");
}
}
FILE *fPtr;
int ttt = FACILITY * (FACILITY-1) ;
fPtr=fopen("cost.txt","r");
int cost[FACILITY][FACILITY] = {0};
int temp[ttt][3]; // cost
for(int i=0;i<ttt;i++){
fscanf(fPtr , "%d %d %d" , &temp[i][0], &temp[i][1], &temp[i][2]);
}
fclose(fPtr);
for(int i=0;i<ttt;i++){ // 2 dimention cost
cost[ temp[i][0]-1 ][ temp[i][1]-1] = temp[i][2];
}
for(int i=0;i<FACILITY;i++){
for(int j=0;j<FACILITY;j++){
printf("%d ", cost[i][j]);
}
printf("\n");
}
int *Gcost;
hipMalloc((void**)&Gcost, FACILITY*FACILITY*sizeof(int));
hipMemcpy(Gcost, cost, FACILITY*FACILITY*sizeof(int), hipMemcpyHostToDevice);
for(int gggggg=0;gggggg<GENERATION;gggggg++){ // generation start
float *Gposition;
hipMalloc((void**)&Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float));
// calculate position
calPosition<<<ISLAND, POPULATION>>>(GA, GB, Gposition);
float position[ISLAND][POPULATION][FACILITY][2];
hipMemcpy(position, Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float), hipMemcpyDeviceToHost);
for(int i=0;i<ISLAND;i++){
for(int p=0;p<POPULATION;p++){
for(int f=0;f<FACILITY;f++){
for(int t=0;t<2;t++){
printf("%.2f ", position[i][p][f][t]);
}
printf("\n");
}
}
}
} // generation end
END = clock();
printf("%f\n", (END - START) / CLOCKS_PER_SEC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#include <math.h>
#include <unistd.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define ISLAND 6
#define POPULATION 20
#define FACILITY 20
#define GENERATION 1
#define CROSSOVER 0.6
#define MUTATION 0.03
#define MIGRATION 15
#define INDIVIDUAL 5
#define H 15 // BAY height
#define W 10 // BAY width
__global__ void init(unsigned int seed, hiprandState_t* states) {
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
/* we have to initialize the state */
hiprand_init(seed, /* the seed can be the same for each core, here we pass the time in from the CPU */
x, /* the sequence number should be different for each core (unless you want all
cores to get the same sequence of numbers for some reason - use thread id! */
0, /* the offset is how much extra we advance in the sequence for each call, can be 0 */
&states[x]);
}
__global__ void randomData(hiprandState_t* states, short* GA){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
for(int j=0;j<FACILITY;j++){ // setup
GA[x*FACILITY + j] = j;
}
int i; // shuffle
for(i = 0; i < FACILITY; i++) {
short k = hiprand(&states[x]) % FACILITY;
int tmp = GA[x*FACILITY + i];
GA[x*FACILITY + i] = GA[x*FACILITY + k];
GA[x*FACILITY + k] = tmp;
}
}
__global__ void randomBay(hiprandState_t* states, bool* GB){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
int i; // shuffle
for(i = 0; i < FACILITY-1; i++) {
GB[x*(FACILITY-1) + i] = hiprand(&states[x]) % 2;
}
}
__global__ void calPosition(short *data, bool *bay, float *position){
short b=blockIdx.x; //區塊索引 == ISLAND
short t=threadIdx.x; //執行緒索引 == POPULATION
short n=blockDim.x; //區塊中包含的執行緒數目 == num of ISLAND
short x=b*n+t;
short posit = x * FACILITY;
short bayposit = x * (FACILITY-1);
// int posit=b*POPULATION*FACILITY+t*FACILITY; //執行緒在陣列中對應的位置
// int posofposit = b*POPULATION*FACILITY*2+t*FACILITY*2;
for(int i=0;i<ISLAND*POPULATION*FACILITY*2;i++){
position[i] = 0;
}
short len = 1;
short next = 0;
for(short f=0;f<FACILITY;f++){
if(bay[bayposit+f] == 0){
len = len + 1;
}
if(bay[bayposit+f] == 1 || f == FACILITY - 1 ){
if(f == FACILITY - 1 && bay[bayposit+f] == 0){
len = len - 1;
}
float x = W / 2.0 + next;
for(short j=0;j<len;j++){
position[posit*2+(f+j-len+1)*2] = x;
float y = H / (len * 2.0) * ( (j * 2) + 1) ;
position[posit*2+(f+j-len+1)*2+1] = y;
}
len = 1;
next = next + W;
}
}
}
int main(){
float START, END;
START = clock();
hiprandState_t* states;
hipMalloc((void**) &states, ISLAND * POPULATION * sizeof(hiprandState_t));
// init seed
init<<<ISLAND, POPULATION>>>(time(NULL), states);
// generate random data
short *GA;
hipMalloc((void**)&GA, ISLAND*POPULATION*FACILITY*sizeof(short));
bool *GB;
hipMalloc((void**)&GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool));
randomData<<<ISLAND, POPULATION>>>(states, GA);
randomBay<<<ISLAND, POPULATION>>>(states, GB);
short data[ISLAND][POPULATION][FACILITY];
bool bay[ISLAND][POPULATION][FACILITY-1];
hipMemcpy(data, GA, ISLAND*POPULATION*FACILITY*sizeof(short), hipMemcpyDeviceToHost);
hipMemcpy(bay, GB, ISLAND*POPULATION*(FACILITY-1)*sizeof(bool), hipMemcpyDeviceToHost);
// print data
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY;k++){
printf("%hu ", data[i][j][k]);
}
printf("\n");
}
}
// print bay
for(int i=0;i<ISLAND;i++){
for(int j=0;j<POPULATION;j++){
for(int k=0;k<FACILITY-1;k++){
printf("%d ", bay[i][j][k]);
}
printf("\n");
}
}
FILE *fPtr;
int ttt = FACILITY * (FACILITY-1) ;
fPtr=fopen("cost.txt","r");
int cost[FACILITY][FACILITY] = {0};
int temp[ttt][3]; // cost
for(int i=0;i<ttt;i++){
fscanf(fPtr , "%d %d %d" , &temp[i][0], &temp[i][1], &temp[i][2]);
}
fclose(fPtr);
for(int i=0;i<ttt;i++){ // 2 dimention cost
cost[ temp[i][0]-1 ][ temp[i][1]-1] = temp[i][2];
}
for(int i=0;i<FACILITY;i++){
for(int j=0;j<FACILITY;j++){
printf("%d ", cost[i][j]);
}
printf("\n");
}
int *Gcost;
hipMalloc((void**)&Gcost, FACILITY*FACILITY*sizeof(int));
hipMemcpy(Gcost, cost, FACILITY*FACILITY*sizeof(int), hipMemcpyHostToDevice);
for(int gggggg=0;gggggg<GENERATION;gggggg++){ // generation start
float *Gposition;
hipMalloc((void**)&Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float));
// calculate position
calPosition<<<ISLAND, POPULATION>>>(GA, GB, Gposition);
float position[ISLAND][POPULATION][FACILITY][2];
hipMemcpy(position, Gposition, ISLAND*POPULATION*FACILITY*2*sizeof(float), hipMemcpyDeviceToHost);
for(int i=0;i<ISLAND;i++){
for(int p=0;p<POPULATION;p++){
for(int f=0;f<FACILITY;f++){
for(int t=0;t<2;t++){
printf("%.2f ", position[i][p][f][t]);
}
printf("\n");
}
}
}
} // generation end
END = clock();
printf("%f\n", (END - START) / CLOCKS_PER_SEC);
return 0;
} | .text
.file "ff.hip"
.globl _Z19__device_stub__initjP12hiprandState # -- Begin function _Z19__device_stub__initjP12hiprandState
.p2align 4, 0x90
.type _Z19__device_stub__initjP12hiprandState,@function
_Z19__device_stub__initjP12hiprandState: # @_Z19__device_stub__initjP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__initjP12hiprandState, .Lfunc_end0-_Z19__device_stub__initjP12hiprandState
.cfi_endproc
# -- End function
.globl _Z25__device_stub__randomDataP12hiprandStatePs # -- Begin function _Z25__device_stub__randomDataP12hiprandStatePs
.p2align 4, 0x90
.type _Z25__device_stub__randomDataP12hiprandStatePs,@function
_Z25__device_stub__randomDataP12hiprandStatePs: # @_Z25__device_stub__randomDataP12hiprandStatePs
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10randomDataP12hiprandStatePs, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__randomDataP12hiprandStatePs, .Lfunc_end1-_Z25__device_stub__randomDataP12hiprandStatePs
.cfi_endproc
# -- End function
.globl _Z24__device_stub__randomBayP12hiprandStatePb # -- Begin function _Z24__device_stub__randomBayP12hiprandStatePb
.p2align 4, 0x90
.type _Z24__device_stub__randomBayP12hiprandStatePb,@function
_Z24__device_stub__randomBayP12hiprandStatePb: # @_Z24__device_stub__randomBayP12hiprandStatePb
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9randomBayP12hiprandStatePb, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__randomBayP12hiprandStatePb, .Lfunc_end2-_Z24__device_stub__randomBayP12hiprandStatePb
.cfi_endproc
# -- End function
.globl _Z26__device_stub__calPositionPsPbPf # -- Begin function _Z26__device_stub__calPositionPsPbPf
.p2align 4, 0x90
.type _Z26__device_stub__calPositionPsPbPf,@function
_Z26__device_stub__calPositionPsPbPf: # @_Z26__device_stub__calPositionPsPbPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11calPositionPsPbPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z26__device_stub__calPositionPsPbPf, .Lfunc_end3-_Z26__device_stub__calPositionPsPbPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $28040, %rsp # imm = 0x6D88
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movabsq $4294967302, %rbx # imm = 0x100000006
callq clock
movq %rax, -136(%rbp) # 8-byte Spill
leaq -112(%rbp), %rdi
movl $5760, %esi # imm = 0x1680
callq hipMalloc
leaq 14(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
xorl %edi, %edi
callq time
movq -112(%rbp), %rcx
movl %eax, -48(%rbp)
movq %rcx, -1792(%rbp)
leaq -48(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -1792(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -8880(%rbp), %rdi
leaq -4080(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -72(%rbp), %rcx
callq __hipPopCallConfiguration
movq -8880(%rbp), %rsi
movl -8872(%rbp), %edx
movq -4080(%rbp), %rcx
movl -4072(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq -72(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_2:
leaq -104(%rbp), %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
leaq -96(%rbp), %rdi
movl $2280, %esi # imm = 0x8E8
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq -112(%rbp), %rax
movq -104(%rbp), %rcx
movq %rax, -1792(%rbp)
movq %rcx, -88(%rbp)
leaq -1792(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -88(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -8880(%rbp), %rdi
leaq -4080(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -8880(%rbp), %rsi
movl -8872(%rbp), %edx
movq -4080(%rbp), %rcx
movl -4072(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z10randomDataP12hiprandStatePs, %edi
pushq -48(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_4:
movq %rbx, %rdi
movl $1, %esi
movq %r14, -56(%rbp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq -112(%rbp), %rax
movq -96(%rbp), %rcx
movq %rax, -1792(%rbp)
movq %rcx, -88(%rbp)
leaq -1792(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -88(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -8880(%rbp), %rdi
leaq -4080(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -8880(%rbp), %rsi
movl -8872(%rbp), %edx
movq -4080(%rbp), %rcx
movl -4072(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z9randomBayP12hiprandStatePb, %edi
pushq -48(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_6:
movq -104(%rbp), %rsi
leaq -8880(%rbp), %r13
movl $4800, %edx # imm = 0x12C0
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq -96(%rbp), %rsi
leaq -4080(%rbp), %rdi
movl $2280, %edx # imm = 0x8E8
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_7: # %.preheader137
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_8: # %.preheader136
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_9: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Inner Loop Header: Depth=3
movswl (%r14,%r12,2), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $20, %r12
jne .LBB4_9
# %bb.10: # in Loop: Header=BB4_8 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r14
cmpq $20, %r15
jne .LBB4_8
# %bb.11: # in Loop: Header=BB4_7 Depth=1
incq %rbx
addq $800, %r13 # imm = 0x320
cmpq $6, %rbx
jne .LBB4_7
# %bb.12: # %.preheader134.preheader
xorl %ebx, %ebx
leaq -4080(%rbp), %r13
.p2align 4, 0x90
.LBB4_13: # %.preheader134
# =>This Loop Header: Depth=1
# Child Loop BB4_14 Depth 2
# Child Loop BB4_15 Depth 3
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_14: # %.preheader133
# Parent Loop BB4_13 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_15 Depth 3
movq $-19, %r12
.p2align 4, 0x90
.LBB4_15: # Parent Loop BB4_13 Depth=1
# Parent Loop BB4_14 Depth=2
# => This Inner Loop Header: Depth=3
movzbl 19(%r14,%r12), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
jne .LBB4_15
# %bb.16: # in Loop: Header=BB4_14 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r15
addq $19, %r14
cmpq $20, %r15
jne .LBB4_14
# %bb.17: # in Loop: Header=BB4_13 Depth=1
incq %rbx
addq $380, %r13 # imm = 0x17C
cmpq $6, %rbx
jne .LBB4_13
# %bb.18:
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r13
leaq -1792(%rbp), %r12
movl $1600, %edx # imm = 0x640
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rsp, -128(%rbp) # 8-byte Spill
movq %rsp, %r14
addq $-4560, %r14 # imm = 0xEE30
movq %r14, %rsp
movl $380, %r15d # imm = 0x17C
movq %r14, %rbx
.p2align 4, 0x90
.LBB4_19: # =>This Inner Loop Header: Depth=1
leaq 4(%rbx), %rcx
leaq 8(%rbx), %r8
movl $.L.str.5, %esi
movq %r13, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $12, %rbx
decq %r15
jne .LBB4_19
# %bb.20:
movq %r13, %rdi
callq fclose
movl $8, %eax
.p2align 4, 0x90
.LBB4_21: # =>This Inner Loop Header: Depth=1
movl (%r14,%rax), %ecx
movslq -8(%r14,%rax), %rdx
leaq (%rdx,%rdx,4), %rdx
shlq $4, %rdx
movslq -4(%r14,%rax), %rsi
addq %r12, %rdx
movl %ecx, -84(%rdx,%rsi,4)
addq $12, %rax
cmpq $4568, %rax # imm = 0x11D8
jne .LBB4_21
# %bb.22: # %.preheader131.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_23: # %.preheader131
# =>This Loop Header: Depth=1
# Child Loop BB4_24 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_24: # Parent Loop BB4_23 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $20, %r14
jne .LBB4_24
# %bb.25: # in Loop: Header=BB4_23 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
addq $80, %r12
cmpq $20, %rbx
jne .LBB4_23
# %bb.26: # %.critedge
leaq -152(%rbp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
movq -152(%rbp), %rdi
leaq -1792(%rbp), %rsi
movl $1600, %edx # imm = 0x640
movl $1, %ecx
callq hipMemcpy
leaq -120(%rbp), %rdi
movl $19200, %esi # imm = 0x4B00
callq hipMalloc
movabsq $4294967302, %rdi # imm = 0x100000006
movl $1, %esi
movq -56(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27:
movq -104(%rbp), %rax
movq -96(%rbp), %rcx
movq -120(%rbp), %rdx
movq %rax, -48(%rbp)
movq %rcx, -184(%rbp)
movq %rdx, -176(%rbp)
leaq -48(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -184(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -176(%rbp), %rax
movq %rax, -28064(%rbp)
leaq -88(%rbp), %rdi
leaq -72(%rbp), %rsi
leaq -168(%rbp), %rdx
leaq -160(%rbp), %rcx
callq __hipPopCallConfiguration
movq -88(%rbp), %rsi
movl -80(%rbp), %edx
movq -72(%rbp), %rcx
movl -64(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z11calPositionPsPbPf, %edi
pushq -160(%rbp)
pushq -168(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_28:
movq -120(%rbp), %rsi
leaq -28080(%rbp), %rbx
movl $19200, %edx # imm = 0x4B00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_29: # %.preheader130
# =>This Loop Header: Depth=1
# Child Loop BB4_30 Depth 2
# Child Loop BB4_31 Depth 3
# Child Loop BB4_32 Depth 4
movq %rax, -144(%rbp) # 8-byte Spill
movq %rbx, -56(%rbp) # 8-byte Spill
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_30: # %.preheader129
# Parent Loop BB4_29 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_31 Depth 3
# Child Loop BB4_32 Depth 4
movq %r15, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_31: # %.preheader
# Parent Loop BB4_29 Depth=1
# Parent Loop BB4_30 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_32 Depth 4
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_32: # Parent Loop BB4_29 Depth=1
# Parent Loop BB4_30 Depth=2
# Parent Loop BB4_31 Depth=3
# => This Inner Loop Header: Depth=4
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $1, %rbx
je .LBB4_32
# %bb.33: # in Loop: Header=BB4_31 Depth=3
movl $10, %edi
callq putchar@PLT
incq %r14
addq $8, %r13
cmpq $20, %r14
jne .LBB4_31
# %bb.34: # in Loop: Header=BB4_30 Depth=2
incq %r12
addq $160, %r15
cmpq $20, %r12
jne .LBB4_30
# %bb.35: # in Loop: Header=BB4_29 Depth=1
movq -144(%rbp), %rax # 8-byte Reload
incq %rax
movq -56(%rbp), %rbx # 8-byte Reload
addq $3200, %rbx # imm = 0xC80
cmpq $6, %rax
jne .LBB4_29
# %bb.36:
xorps %xmm0, %xmm0
cvtsi2ssq -136(%rbp), %xmm0 # 8-byte Folded Reload
movss %xmm0, -56(%rbp) # 4-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss -56(%rbp), %xmm0 # 4-byte Folded Reload
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq -128(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initjP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10randomDataP12hiprandStatePs, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9randomBayP12hiprandStatePb, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calPositionPsPbPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initjP12hiprandState,@object # @_Z4initjP12hiprandState
.section .rodata,"a",@progbits
.globl _Z4initjP12hiprandState
.p2align 3, 0x0
_Z4initjP12hiprandState:
.quad _Z19__device_stub__initjP12hiprandState
.size _Z4initjP12hiprandState, 8
.type _Z10randomDataP12hiprandStatePs,@object # @_Z10randomDataP12hiprandStatePs
.globl _Z10randomDataP12hiprandStatePs
.p2align 3, 0x0
_Z10randomDataP12hiprandStatePs:
.quad _Z25__device_stub__randomDataP12hiprandStatePs
.size _Z10randomDataP12hiprandStatePs, 8
.type _Z9randomBayP12hiprandStatePb,@object # @_Z9randomBayP12hiprandStatePb
.globl _Z9randomBayP12hiprandStatePb
.p2align 3, 0x0
_Z9randomBayP12hiprandStatePb:
.quad _Z24__device_stub__randomBayP12hiprandStatePb
.size _Z9randomBayP12hiprandStatePb, 8
.type _Z11calPositionPsPbPf,@object # @_Z11calPositionPsPbPf
.globl _Z11calPositionPsPbPf
.p2align 3, 0x0
_Z11calPositionPsPbPf:
.quad _Z26__device_stub__calPositionPsPbPf
.size _Z11calPositionPsPbPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%hu "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cost.txt"
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d %d"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%.2f "
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%f\n"
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initjP12hiprandState"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10randomDataP12hiprandStatePs"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9randomBayP12hiprandStatePb"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11calPositionPsPbPf"
.size .L__unnamed_4, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initjP12hiprandState
.addrsig_sym _Z25__device_stub__randomDataP12hiprandStatePs
.addrsig_sym _Z24__device_stub__randomBayP12hiprandStatePb
.addrsig_sym _Z26__device_stub__calPositionPsPbPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initjP12hiprandState
.addrsig_sym _Z10randomDataP12hiprandStatePs
.addrsig_sym _Z9randomBayP12hiprandStatePb
.addrsig_sym _Z11calPositionPsPbPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0e4d_00000000-6_ff.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2287:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2287:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.type _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, @function
_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW:
.LFB2309:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4initjP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2309:
.size _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW, .-_Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
.globl _Z4initjP17curandStateXORWOW
.type _Z4initjP17curandStateXORWOW, @function
_Z4initjP17curandStateXORWOW:
.LFB2310:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2310:
.size _Z4initjP17curandStateXORWOW, .-_Z4initjP17curandStateXORWOW
.globl _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
.type _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs, @function
_Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs:
.LFB2311:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10randomDataP17curandStateXORWOWPs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2311:
.size _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs, .-_Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
.globl _Z10randomDataP17curandStateXORWOWPs
.type _Z10randomDataP17curandStateXORWOWPs, @function
_Z10randomDataP17curandStateXORWOWPs:
.LFB2312:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2312:
.size _Z10randomDataP17curandStateXORWOWPs, .-_Z10randomDataP17curandStateXORWOWPs
.globl _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
.type _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb, @function
_Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb:
.LFB2313:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9randomBayP17curandStateXORWOWPb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2313:
.size _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb, .-_Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
.globl _Z9randomBayP17curandStateXORWOWPb
.type _Z9randomBayP17curandStateXORWOWPb, @function
_Z9randomBayP17curandStateXORWOWPb:
.LFB2314:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2314:
.size _Z9randomBayP17curandStateXORWOWPb, .-_Z9randomBayP17curandStateXORWOWPb
.globl _Z35__device_stub__Z11calPositionPsPbPfPsPbPf
.type _Z35__device_stub__Z11calPositionPsPbPfPsPbPf, @function
_Z35__device_stub__Z11calPositionPsPbPfPsPbPf:
.LFB2315:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11calPositionPsPbPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2315:
.size _Z35__device_stub__Z11calPositionPsPbPfPsPbPf, .-_Z35__device_stub__Z11calPositionPsPbPfPsPbPf
.globl _Z11calPositionPsPbPf
.type _Z11calPositionPsPbPf, @function
_Z11calPositionPsPbPf:
.LFB2316:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11calPositionPsPbPfPsPbPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2316:
.size _Z11calPositionPsPbPf, .-_Z11calPositionPsPbPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%hu "
.LC1:
.string "\n"
.LC2:
.string "%d "
.LC3:
.string "r"
.LC4:
.string "cost.txt"
.LC5:
.string "%d %d %d"
.LC6:
.string "%.2f "
.LC8:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2284:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
leaq -24576(%rsp), %r11
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
subq $3416, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
call clock@PLT
pxor %xmm1, %xmm1
cvtsi2ssq %rax, %xmm1
movss %xmm1, -28028(%rbp)
leaq -28016(%rbp), %rdi
movl $5760, %esi
call cudaMalloc@PLT
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L71
.L36:
leaq -28008(%rbp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
leaq -28000(%rbp), %rdi
movl $2280, %esi
call cudaMalloc@PLT
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L72
.L37:
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L38:
leaq -24064(%rbp), %rdi
movl $2, %ecx
movl $4800, %edx
movq -28008(%rbp), %rsi
call cudaMemcpy@PLT
leaq -26352(%rbp), %rdi
movl $2, %ecx
movl $2280, %edx
movq -28000(%rbp), %rsi
call cudaMemcpy@PLT
leaq -23224(%rbp), %r14
movq $0, -28024(%rbp)
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L39
.L71:
movq -28016(%rbp), %rbx
movl $0, %edi
call time@PLT
movq %rbx, %rsi
movl %eax, %edi
call _Z42__device_stub__Z4initjP17curandStateXORWOWjP17curandStateXORWOW
jmp .L36
.L72:
movq -28008(%rbp), %rsi
movq -28016(%rbp), %rdi
call _Z50__device_stub__Z10randomDataP17curandStateXORWOWPsP17curandStateXORWOWPs
jmp .L37
.L73:
movq -28000(%rbp), %rsi
movq -28016(%rbp), %rdi
call _Z48__device_stub__Z9randomBayP17curandStateXORWOWPbP17curandStateXORWOWPb
jmp .L38
.L74:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %r12
cmpq %r14, %r12
je .L41
.L43:
leaq -40(%r12), %rbx
.L40:
movswl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $2, %rbx
cmpq %r12, %rbx
jne .L40
jmp .L74
.L41:
addq $800, %r14
addq $800, -28024(%rbp)
movq -28024(%rbp), %rax
cmpq $4800, %rax
je .L75
.L39:
leaq -800(%r14), %r12
jmp .L43
.L75:
leaq -26352(%rbp), %r14
movq $0, -28024(%rbp)
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L42
.L76:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $19, %r12
cmpq %r14, %r12
je .L45
.L47:
movl $0, %ebx
.L44:
movzbl (%r12,%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $19, %rbx
jne .L44
jmp .L76
.L45:
addq $380, -28024(%rbp)
movq -28024(%rbp), %rax
cmpq $2280, %rax
je .L46
.L42:
movq %r14, %r12
addq $380, %r14
jmp .L47
.L46:
leaq .LC3(%rip), %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
movq %rax, %r14
leaq -27952(%rbp), %rdi
movl $200, %ecx
movl $0, %eax
rep stosq
leaq -4096(%rsp), %rax
.L48:
cmpq %rax, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
subq $464, %rsp
orq $0, 456(%rsp)
movq %rsp, %rbx
movq %rbx, %r12
leaq 4560(%rbx), %r13
leaq .LC5(%rip), %r15
.L51:
leaq 4(%rbx), %rcx
leaq 8(%rbx), %r8
movq %rbx, %rdx
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $12, %rbx
cmpq %r13, %rbx
jne .L51
movq %r14, %rdi
call fclose@PLT
.L52:
movl 4(%r12), %eax
leal -1(%rax), %edx
movslq %edx, %rdx
movl (%r12), %eax
subl $1, %eax
cltq
leaq (%rax,%rax,4), %rax
leaq (%rdx,%rax,4), %rax
movl 8(%r12), %edx
movl %edx, -27952(%rbp,%rax,4)
addq $12, %r12
cmpq %r13, %r12
jne .L52
leaq -27872(%rbp), %r12
leaq -26272(%rbp), %r15
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r14
.L53:
leaq -80(%r12), %rbx
.L54:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L54
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $80, %r12
cmpq %r15, %r12
jne .L53
leaq -27992(%rbp), %rdi
movl $1600, %esi
call cudaMalloc@PLT
leaq -27952(%rbp), %rsi
movl $1, %ecx
movl $1600, %edx
movq -27992(%rbp), %rdi
call cudaMemcpy@PLT
leaq -27984(%rbp), %rdi
movl $19200, %esi
call cudaMalloc@PLT
movl $20, -27964(%rbp)
movl $1, -27960(%rbp)
movl $1, -27956(%rbp)
movl $6, -27976(%rbp)
movl $1, -27972(%rbp)
movl $1, -27968(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -27964(%rbp), %rdx
movl $1, %ecx
movq -27976(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L56:
leaq -19264(%rbp), %rdi
movl $2, %ecx
movl $19200, %edx
movq -27984(%rbp), %rsi
call cudaMemcpy@PLT
leaq -15904(%rbp), %r15
movq $0, -28024(%rbp)
leaq .LC6(%rip), %r12
leaq .LC1(%rip), %r14
.L57:
leaq -3200(%r15), %r13
.L61:
leaq -160(%r13), %rbx
.L58:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbx, %r13
jne .L58
addq $160, %r13
cmpq %r15, %r13
jne .L61
addq $3200, %r15
addq $3200, -28024(%rbp)
movq -28024(%rbp), %rax
cmpq $19200, %rax
jne .L57
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
subss -28028(%rbp), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L77:
.cfi_restore_state
movq -27984(%rbp), %rdx
movq -28000(%rbp), %rsi
movq -28008(%rbp), %rdi
call _Z35__device_stub__Z11calPositionPsPbPfPsPbPf
jmp .L56
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2284:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z11calPositionPsPbPf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z9randomBayP17curandStateXORWOWPb"
.align 8
.LC11:
.string "_Z10randomDataP17curandStateXORWOWPs"
.section .rodata.str1.1
.LC12:
.string "_Z4initjP17curandStateXORWOW"
.LC13:
.string "precalc_xorwow_matrix"
.LC14:
.string "precalc_xorwow_offset_matrix"
.LC15:
.string "mrg32k3aM1"
.LC16:
.string "mrg32k3aM2"
.LC17:
.string "mrg32k3aM1SubSeq"
.LC18:
.string "mrg32k3aM2SubSeq"
.LC19:
.string "mrg32k3aM1Seq"
.LC20:
.string "mrg32k3aM2Seq"
.LC21:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2318:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calPositionPsPbPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9randomBayP17curandStateXORWOWPb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10randomDataP17curandStateXORWOWPs(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z4initjP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2318:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ff.hip"
.globl _Z19__device_stub__initjP12hiprandState # -- Begin function _Z19__device_stub__initjP12hiprandState
.p2align 4, 0x90
.type _Z19__device_stub__initjP12hiprandState,@function
_Z19__device_stub__initjP12hiprandState: # @_Z19__device_stub__initjP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__initjP12hiprandState, .Lfunc_end0-_Z19__device_stub__initjP12hiprandState
.cfi_endproc
# -- End function
.globl _Z25__device_stub__randomDataP12hiprandStatePs # -- Begin function _Z25__device_stub__randomDataP12hiprandStatePs
.p2align 4, 0x90
.type _Z25__device_stub__randomDataP12hiprandStatePs,@function
_Z25__device_stub__randomDataP12hiprandStatePs: # @_Z25__device_stub__randomDataP12hiprandStatePs
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10randomDataP12hiprandStatePs, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__randomDataP12hiprandStatePs, .Lfunc_end1-_Z25__device_stub__randomDataP12hiprandStatePs
.cfi_endproc
# -- End function
.globl _Z24__device_stub__randomBayP12hiprandStatePb # -- Begin function _Z24__device_stub__randomBayP12hiprandStatePb
.p2align 4, 0x90
.type _Z24__device_stub__randomBayP12hiprandStatePb,@function
_Z24__device_stub__randomBayP12hiprandStatePb: # @_Z24__device_stub__randomBayP12hiprandStatePb
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9randomBayP12hiprandStatePb, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z24__device_stub__randomBayP12hiprandStatePb, .Lfunc_end2-_Z24__device_stub__randomBayP12hiprandStatePb
.cfi_endproc
# -- End function
.globl _Z26__device_stub__calPositionPsPbPf # -- Begin function _Z26__device_stub__calPositionPsPbPf
.p2align 4, 0x90
.type _Z26__device_stub__calPositionPsPbPf,@function
_Z26__device_stub__calPositionPsPbPf: # @_Z26__device_stub__calPositionPsPbPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11calPositionPsPbPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z26__device_stub__calPositionPsPbPf, .Lfunc_end3-_Z26__device_stub__calPositionPsPbPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $28040, %rsp # imm = 0x6D88
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movabsq $4294967302, %rbx # imm = 0x100000006
callq clock
movq %rax, -136(%rbp) # 8-byte Spill
leaq -112(%rbp), %rdi
movl $5760, %esi # imm = 0x1680
callq hipMalloc
leaq 14(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
xorl %edi, %edi
callq time
movq -112(%rbp), %rcx
movl %eax, -48(%rbp)
movq %rcx, -1792(%rbp)
leaq -48(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -1792(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -8880(%rbp), %rdi
leaq -4080(%rbp), %rsi
leaq -88(%rbp), %rdx
leaq -72(%rbp), %rcx
callq __hipPopCallConfiguration
movq -8880(%rbp), %rsi
movl -8872(%rbp), %edx
movq -4080(%rbp), %rcx
movl -4072(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z4initjP12hiprandState, %edi
pushq -72(%rbp)
pushq -88(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_2:
leaq -104(%rbp), %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
leaq -96(%rbp), %rdi
movl $2280, %esi # imm = 0x8E8
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq -112(%rbp), %rax
movq -104(%rbp), %rcx
movq %rax, -1792(%rbp)
movq %rcx, -88(%rbp)
leaq -1792(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -88(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -8880(%rbp), %rdi
leaq -4080(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -8880(%rbp), %rsi
movl -8872(%rbp), %edx
movq -4080(%rbp), %rcx
movl -4072(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z10randomDataP12hiprandStatePs, %edi
pushq -48(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_4:
movq %rbx, %rdi
movl $1, %esi
movq %r14, -56(%rbp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq -112(%rbp), %rax
movq -96(%rbp), %rcx
movq %rax, -1792(%rbp)
movq %rcx, -88(%rbp)
leaq -1792(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -88(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -8880(%rbp), %rdi
leaq -4080(%rbp), %rsi
leaq -72(%rbp), %rdx
leaq -48(%rbp), %rcx
callq __hipPopCallConfiguration
movq -8880(%rbp), %rsi
movl -8872(%rbp), %edx
movq -4080(%rbp), %rcx
movl -4072(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z9randomBayP12hiprandStatePb, %edi
pushq -48(%rbp)
pushq -72(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_6:
movq -104(%rbp), %rsi
leaq -8880(%rbp), %r13
movl $4800, %edx # imm = 0x12C0
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
movq -96(%rbp), %rsi
leaq -4080(%rbp), %rdi
movl $2280, %edx # imm = 0x8E8
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_7: # %.preheader137
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_8: # %.preheader136
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_9: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Inner Loop Header: Depth=3
movswl (%r14,%r12,2), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $20, %r12
jne .LBB4_9
# %bb.10: # in Loop: Header=BB4_8 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r15
addq $40, %r14
cmpq $20, %r15
jne .LBB4_8
# %bb.11: # in Loop: Header=BB4_7 Depth=1
incq %rbx
addq $800, %r13 # imm = 0x320
cmpq $6, %rbx
jne .LBB4_7
# %bb.12: # %.preheader134.preheader
xorl %ebx, %ebx
leaq -4080(%rbp), %r13
.p2align 4, 0x90
.LBB4_13: # %.preheader134
# =>This Loop Header: Depth=1
# Child Loop BB4_14 Depth 2
# Child Loop BB4_15 Depth 3
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_14: # %.preheader133
# Parent Loop BB4_13 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_15 Depth 3
movq $-19, %r12
.p2align 4, 0x90
.LBB4_15: # Parent Loop BB4_13 Depth=1
# Parent Loop BB4_14 Depth=2
# => This Inner Loop Header: Depth=3
movzbl 19(%r14,%r12), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
jne .LBB4_15
# %bb.16: # in Loop: Header=BB4_14 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r15
addq $19, %r14
cmpq $20, %r15
jne .LBB4_14
# %bb.17: # in Loop: Header=BB4_13 Depth=1
incq %rbx
addq $380, %r13 # imm = 0x17C
cmpq $6, %rbx
jne .LBB4_13
# %bb.18:
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r13
leaq -1792(%rbp), %r12
movl $1600, %edx # imm = 0x640
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
movq %rsp, -128(%rbp) # 8-byte Spill
movq %rsp, %r14
addq $-4560, %r14 # imm = 0xEE30
movq %r14, %rsp
movl $380, %r15d # imm = 0x17C
movq %r14, %rbx
.p2align 4, 0x90
.LBB4_19: # =>This Inner Loop Header: Depth=1
leaq 4(%rbx), %rcx
leaq 8(%rbx), %r8
movl $.L.str.5, %esi
movq %r13, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $12, %rbx
decq %r15
jne .LBB4_19
# %bb.20:
movq %r13, %rdi
callq fclose
movl $8, %eax
.p2align 4, 0x90
.LBB4_21: # =>This Inner Loop Header: Depth=1
movl (%r14,%rax), %ecx
movslq -8(%r14,%rax), %rdx
leaq (%rdx,%rdx,4), %rdx
shlq $4, %rdx
movslq -4(%r14,%rax), %rsi
addq %r12, %rdx
movl %ecx, -84(%rdx,%rsi,4)
addq $12, %rax
cmpq $4568, %rax # imm = 0x11D8
jne .LBB4_21
# %bb.22: # %.preheader131.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_23: # %.preheader131
# =>This Loop Header: Depth=1
# Child Loop BB4_24 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_24: # Parent Loop BB4_23 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $20, %r14
jne .LBB4_24
# %bb.25: # in Loop: Header=BB4_23 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbx
addq $80, %r12
cmpq $20, %rbx
jne .LBB4_23
# %bb.26: # %.critedge
leaq -152(%rbp), %rdi
movl $1600, %esi # imm = 0x640
callq hipMalloc
movq -152(%rbp), %rdi
leaq -1792(%rbp), %rsi
movl $1600, %edx # imm = 0x640
movl $1, %ecx
callq hipMemcpy
leaq -120(%rbp), %rdi
movl $19200, %esi # imm = 0x4B00
callq hipMalloc
movabsq $4294967302, %rdi # imm = 0x100000006
movl $1, %esi
movq -56(%rbp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27:
movq -104(%rbp), %rax
movq -96(%rbp), %rcx
movq -120(%rbp), %rdx
movq %rax, -48(%rbp)
movq %rcx, -184(%rbp)
movq %rdx, -176(%rbp)
leaq -48(%rbp), %rax
movq %rax, -28080(%rbp)
leaq -184(%rbp), %rax
movq %rax, -28072(%rbp)
leaq -176(%rbp), %rax
movq %rax, -28064(%rbp)
leaq -88(%rbp), %rdi
leaq -72(%rbp), %rsi
leaq -168(%rbp), %rdx
leaq -160(%rbp), %rcx
callq __hipPopCallConfiguration
movq -88(%rbp), %rsi
movl -80(%rbp), %edx
movq -72(%rbp), %rcx
movl -64(%rbp), %r8d
leaq -28080(%rbp), %r9
movl $_Z11calPositionPsPbPf, %edi
pushq -160(%rbp)
pushq -168(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_28:
movq -120(%rbp), %rsi
leaq -28080(%rbp), %rbx
movl $19200, %edx # imm = 0x4B00
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_29: # %.preheader130
# =>This Loop Header: Depth=1
# Child Loop BB4_30 Depth 2
# Child Loop BB4_31 Depth 3
# Child Loop BB4_32 Depth 4
movq %rax, -144(%rbp) # 8-byte Spill
movq %rbx, -56(%rbp) # 8-byte Spill
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_30: # %.preheader129
# Parent Loop BB4_29 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_31 Depth 3
# Child Loop BB4_32 Depth 4
movq %r15, %r13
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_31: # %.preheader
# Parent Loop BB4_29 Depth=1
# Parent Loop BB4_30 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB4_32 Depth 4
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_32: # Parent Loop BB4_29 Depth=1
# Parent Loop BB4_30 Depth=2
# Parent Loop BB4_31 Depth=3
# => This Inner Loop Header: Depth=4
movss (%r13,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $1, %rbx
je .LBB4_32
# %bb.33: # in Loop: Header=BB4_31 Depth=3
movl $10, %edi
callq putchar@PLT
incq %r14
addq $8, %r13
cmpq $20, %r14
jne .LBB4_31
# %bb.34: # in Loop: Header=BB4_30 Depth=2
incq %r12
addq $160, %r15
cmpq $20, %r12
jne .LBB4_30
# %bb.35: # in Loop: Header=BB4_29 Depth=1
movq -144(%rbp), %rax # 8-byte Reload
incq %rax
movq -56(%rbp), %rbx # 8-byte Reload
addq $3200, %rbx # imm = 0xC80
cmpq $6, %rax
jne .LBB4_29
# %bb.36:
xorps %xmm0, %xmm0
cvtsi2ssq -136(%rbp), %xmm0 # 8-byte Folded Reload
movss %xmm0, -56(%rbp) # 4-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss -56(%rbp), %xmm0 # 4-byte Folded Reload
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq -128(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4initjP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10randomDataP12hiprandStatePs, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9randomBayP12hiprandStatePb, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calPositionPsPbPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4initjP12hiprandState,@object # @_Z4initjP12hiprandState
.section .rodata,"a",@progbits
.globl _Z4initjP12hiprandState
.p2align 3, 0x0
_Z4initjP12hiprandState:
.quad _Z19__device_stub__initjP12hiprandState
.size _Z4initjP12hiprandState, 8
.type _Z10randomDataP12hiprandStatePs,@object # @_Z10randomDataP12hiprandStatePs
.globl _Z10randomDataP12hiprandStatePs
.p2align 3, 0x0
_Z10randomDataP12hiprandStatePs:
.quad _Z25__device_stub__randomDataP12hiprandStatePs
.size _Z10randomDataP12hiprandStatePs, 8
.type _Z9randomBayP12hiprandStatePb,@object # @_Z9randomBayP12hiprandStatePb
.globl _Z9randomBayP12hiprandStatePb
.p2align 3, 0x0
_Z9randomBayP12hiprandStatePb:
.quad _Z24__device_stub__randomBayP12hiprandStatePb
.size _Z9randomBayP12hiprandStatePb, 8
.type _Z11calPositionPsPbPf,@object # @_Z11calPositionPsPbPf
.globl _Z11calPositionPsPbPf
.p2align 3, 0x0
_Z11calPositionPsPbPf:
.quad _Z26__device_stub__calPositionPsPbPf
.size _Z11calPositionPsPbPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%hu "
.size .L.str, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cost.txt"
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d %d %d"
.size .L.str.5, 9
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%.2f "
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%f\n"
.size .L.str.7, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4initjP12hiprandState"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10randomDataP12hiprandStatePs"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z9randomBayP12hiprandStatePb"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11calPositionPsPbPf"
.size .L__unnamed_4, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__initjP12hiprandState
.addrsig_sym _Z25__device_stub__randomDataP12hiprandStatePs
.addrsig_sym _Z24__device_stub__randomBayP12hiprandStatePb
.addrsig_sym _Z26__device_stub__calPositionPsPbPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4initjP12hiprandState
.addrsig_sym _Z10randomDataP12hiprandStatePs
.addrsig_sym _Z9randomBayP12hiprandStatePb
.addrsig_sym _Z11calPositionPsPbPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define BLOCKSIZE 256
__global__ void MatrixAddI(int *matrix1, int *matrix2, int *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
__global__ void MatrixAddF(float *matrix1, float *matrix2, float *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
void read_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (int *)calloc(t1*t2, sizeof(int));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%d,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%d\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void read_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (float *)calloc(t1*t2, sizeof(float));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%f,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%f\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void write_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%d,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%d\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void write_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%f,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%f\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void matrix_check(int m1, int n1, int m2, int n2)
{
if ((m1-m2)+(n1-n2) != 0)
{
printf("Matrix dimensions must be PxQ and PxQ respectively\n");
exit(1);
}
}
int main(int argc, char *argv[])
{
int m1, n1, m2, n2;
if (argc != 5)
{
printf("Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n");
exit(1);
}
if (strcmp(argv[4], "float") == 0)
{
float *hostmatrix1, *hostmatrix2, *hostmatrix3;
float *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_fmatrix(argv[1], &m1, &n1, &hostmatrix1);
read_fmatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(float);
hostmatrix3 = (float *)calloc(matrix_size, sizeof(float));
cudaMalloc(&devicematrix1, matrix_size);
cudaMalloc(&devicematrix2, matrix_size);
cudaMalloc(&devicematrix3, matrix_size);
cudaMemcpy(devicematrix1, hostmatrix1, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(devicematrix2, hostmatrix2, matrix_size, cudaMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddF <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
cudaMemcpy(hostmatrix3, devicematrix3, matrix_size, cudaMemcpyDeviceToHost);
write_fmatrix(argv[3], &m1, &n1, &hostmatrix3);
cudaFree(devicematrix1);
cudaFree(devicematrix2);
cudaFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
if (strcmp(argv[4], "int") == 0)
{
int *hostmatrix1, *hostmatrix2, *hostmatrix3;
int *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_imatrix(argv[1], &m1, &n1, &hostmatrix1);
read_imatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(int);
hostmatrix3 = (int *)calloc(m1*n1, sizeof(int));
cudaMalloc(&devicematrix1, matrix_size);
cudaMalloc(&devicematrix2, matrix_size);
cudaMalloc(&devicematrix3, matrix_size);
cudaMemcpy(devicematrix1, hostmatrix1, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(devicematrix2, hostmatrix2, matrix_size, cudaMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddI <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
cudaMemcpy(hostmatrix3, devicematrix3, matrix_size, cudaMemcpyDeviceToHost);
write_imatrix(argv[3], &m1, &n1, &hostmatrix3);
cudaFree(devicematrix1);
cudaFree(devicematrix2);
cudaFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
return 0;
} | code for sm_80
Function : _Z10MatrixAddFPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10MatrixAddIPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define BLOCKSIZE 256
__global__ void MatrixAddI(int *matrix1, int *matrix2, int *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
__global__ void MatrixAddF(float *matrix1, float *matrix2, float *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
void read_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (int *)calloc(t1*t2, sizeof(int));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%d,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%d\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void read_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (float *)calloc(t1*t2, sizeof(float));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%f,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%f\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void write_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%d,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%d\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void write_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%f,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%f\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void matrix_check(int m1, int n1, int m2, int n2)
{
if ((m1-m2)+(n1-n2) != 0)
{
printf("Matrix dimensions must be PxQ and PxQ respectively\n");
exit(1);
}
}
int main(int argc, char *argv[])
{
int m1, n1, m2, n2;
if (argc != 5)
{
printf("Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n");
exit(1);
}
if (strcmp(argv[4], "float") == 0)
{
float *hostmatrix1, *hostmatrix2, *hostmatrix3;
float *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_fmatrix(argv[1], &m1, &n1, &hostmatrix1);
read_fmatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(float);
hostmatrix3 = (float *)calloc(matrix_size, sizeof(float));
cudaMalloc(&devicematrix1, matrix_size);
cudaMalloc(&devicematrix2, matrix_size);
cudaMalloc(&devicematrix3, matrix_size);
cudaMemcpy(devicematrix1, hostmatrix1, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(devicematrix2, hostmatrix2, matrix_size, cudaMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddF <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
cudaMemcpy(hostmatrix3, devicematrix3, matrix_size, cudaMemcpyDeviceToHost);
write_fmatrix(argv[3], &m1, &n1, &hostmatrix3);
cudaFree(devicematrix1);
cudaFree(devicematrix2);
cudaFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
if (strcmp(argv[4], "int") == 0)
{
int *hostmatrix1, *hostmatrix2, *hostmatrix3;
int *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_imatrix(argv[1], &m1, &n1, &hostmatrix1);
read_imatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(int);
hostmatrix3 = (int *)calloc(m1*n1, sizeof(int));
cudaMalloc(&devicematrix1, matrix_size);
cudaMalloc(&devicematrix2, matrix_size);
cudaMalloc(&devicematrix3, matrix_size);
cudaMemcpy(devicematrix1, hostmatrix1, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(devicematrix2, hostmatrix2, matrix_size, cudaMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddI <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
cudaMemcpy(hostmatrix3, devicematrix3, matrix_size, cudaMemcpyDeviceToHost);
write_imatrix(argv[3], &m1, &n1, &hostmatrix3);
cudaFree(devicematrix1);
cudaFree(devicematrix2);
cudaFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
return 0;
} | .file "tmpxft_0017c93c_00000000-6_matrix-addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r+"
.LC1:
.string "%d %d\n"
.LC2:
.string "%d,"
.LC3:
.string "%d\n"
.LC4:
.string "File read failed\n"
.text
.globl _Z12read_imatrixPcPiS0_PS0_
.type _Z12read_imatrixPcPiS0_PS0_, @function
_Z12read_imatrixPcPiS0_PS0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r12
movq %rdx, %rbp
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L4
movq %rax, %r13
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 28(%rsp), %ebx
movl %ebx, (%r12)
movl 32(%rsp), %eax
movl %eax, 0(%rbp)
imull %ebx, %eax
movslq %eax, %rdi
movl $4, %esi
call calloc@PLT
movq %rax, (%r14)
movl $0, %edx
movl $1, 12(%rsp)
leaq 36(%rsp), %r15
testl %ebx, %ebx
jg .L5
.L6:
movq %r13, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movq %r15, %rdx
leaq .LC3(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq (%r14), %rax
movl 36(%rsp), %edx
movl %edx, (%rax,%rbp)
movl %r12d, %edx
.L8:
addl $1, %ebx
movl 32(%rsp), %eax
addl $1, %r12d
addq $4, %rbp
cmpl %ebx, %eax
jl .L11
.L9:
cmpl %ebx, %eax
jle .L7
movq %r15, %rdx
leaq .LC2(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq (%r14), %rax
movl 36(%rsp), %edx
movl %edx, (%rax,%rbp)
movl %r12d, %edx
jmp .L8
.L11:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl %eax, 28(%rsp)
jl .L6
.L5:
movl 32(%rsp), %eax
testl %eax, %eax
jle .L11
leal 1(%rdx), %r12d
movslq %edx, %rdx
leaq 0(,%rdx,4), %rbp
movl $1, %ebx
jmp .L9
.L4:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z12read_imatrixPcPiS0_PS0_, .-_Z12read_imatrixPcPiS0_PS0_
.section .rodata.str1.1
.LC5:
.string "%f,"
.LC6:
.string "%f\n"
.text
.globl _Z12read_fmatrixPcPiS0_PPf
.type _Z12read_fmatrixPcPiS0_PPf, @function
_Z12read_fmatrixPcPiS0_PPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r12
movq %rdx, %rbp
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L20
movq %rax, %r13
leaq 32(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 28(%rsp), %ebx
movl %ebx, (%r12)
movl 32(%rsp), %eax
movl %eax, 0(%rbp)
imull %ebx, %eax
movslq %eax, %rdi
movl $4, %esi
call calloc@PLT
movq %rax, (%r14)
movl $0, %edx
movl $1, 12(%rsp)
leaq 36(%rsp), %r15
testl %ebx, %ebx
jg .L21
.L22:
movq %r13, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq %r15, %rdx
leaq .LC6(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq (%r14), %rax
movss 36(%rsp), %xmm0
movss %xmm0, (%rax,%rbp)
movl %r12d, %edx
.L24:
addl $1, %ebx
movl 32(%rsp), %eax
addl $1, %r12d
addq $4, %rbp
cmpl %ebx, %eax
jl .L27
.L25:
cmpl %ebx, %eax
jle .L23
movq %r15, %rdx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq (%r14), %rax
movss 36(%rsp), %xmm0
movss %xmm0, (%rax,%rbp)
movl %r12d, %edx
jmp .L24
.L27:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl %eax, 28(%rsp)
jl .L22
.L21:
movl 32(%rsp), %eax
testl %eax, %eax
jle .L27
leal 1(%rdx), %r12d
movslq %edx, %rdx
leaq 0(,%rdx,4), %rbp
movl $1, %ebx
jmp .L25
.L20:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12read_fmatrixPcPiS0_PPf, .-_Z12read_fmatrixPcPiS0_PPf
.section .rodata.str1.1
.LC7:
.string "w+"
.LC8:
.string "File write failed\n"
.text
.globl _Z13write_imatrixPcPiS0_PS0_
.type _Z13write_imatrixPcPiS0_PS0_, @function
_Z13write_imatrixPcPiS0_PS0_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %rbx
movq %rcx, %r15
leaq .LC7(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L36
movq %rax, %r14
movl 0(%rbp), %eax
movl %eax, 12(%rsp)
movl (%rbx), %r13d
movl %r13d, %r8d
movl %eax, %ebx
movl %eax, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
movl $1, 8(%rsp)
testl %ebx, %ebx
jg .L37
.L38:
movq %r14, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movq (%r15), %rax
movl (%rax,%rbp), %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %eax
.L40:
addl $1, %ebx
addl $1, %r12d
addq $4, %rbp
cmpl %ebx, %r13d
jl .L43
.L41:
cmpl %ebx, %r13d
jle .L39
movq (%r15), %rax
movl (%rax,%rbp), %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %eax
jmp .L40
.L43:
addl $1, 8(%rsp)
movl 8(%rsp), %edx
cmpl %edx, 12(%rsp)
jl .L38
.L37:
testl %r13d, %r13d
jle .L43
leal 1(%rax), %r12d
cltq
leaq 0(,%rax,4), %rbp
movl $1, %ebx
jmp .L41
.L36:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z13write_imatrixPcPiS0_PS0_, .-_Z13write_imatrixPcPiS0_PS0_
.globl _Z13write_fmatrixPcPiS0_PPf
.type _Z13write_fmatrixPcPiS0_PPf, @function
_Z13write_fmatrixPcPiS0_PPf:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %rbx
movq %rcx, %r15
leaq .LC7(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L50
movq %rax, %r14
movl 0(%rbp), %eax
movl %eax, 12(%rsp)
movl (%rbx), %r13d
movl %r13d, %r8d
movl %eax, %ebx
movl %eax, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %eax
movl $1, 8(%rsp)
testl %ebx, %ebx
jg .L51
.L52:
movq %r14, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movq (%r15), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
leaq .LC6(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl %r12d, %eax
.L54:
addl $1, %ebx
addl $1, %r12d
addq $4, %rbp
cmpl %ebx, %r13d
jl .L57
.L55:
cmpl %ebx, %r13d
jle .L53
movq (%r15), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl %r12d, %eax
jmp .L54
.L57:
addl $1, 8(%rsp)
movl 8(%rsp), %ecx
cmpl %ecx, 12(%rsp)
jl .L52
.L51:
testl %r13d, %r13d
jle .L57
leal 1(%rax), %r12d
cltq
leaq 0(,%rax,4), %rbp
movl $1, %ebx
jmp .L55
.L50:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z13write_fmatrixPcPiS0_PPf, .-_Z13write_fmatrixPcPiS0_PPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Matrix dimensions must be PxQ and PxQ respectively\n"
.text
.globl _Z12matrix_checkiiii
.type _Z12matrix_checkiiii, @function
_Z12matrix_checkiiii:
.LFB2061:
.cfi_startproc
endbr64
subl %edx, %edi
subl %ecx, %esi
addl %esi, %edi
jne .L68
ret
.L68:
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z12matrix_checkiiii, .-_Z12matrix_checkiiii
.globl _Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii
.type _Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10MatrixAddIPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii
.globl _Z10MatrixAddIPiS_S_ii
.type _Z10MatrixAddIPiS_S_ii, @function
_Z10MatrixAddIPiS_S_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z10MatrixAddIPiS_S_ii, .-_Z10MatrixAddIPiS_S_ii
.globl _Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii
.type _Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii, @function
_Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L81
.L77:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L82
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10MatrixAddFPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L77
.L82:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii, .-_Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii
.globl _Z10MatrixAddFPfS_S_ii
.type _Z10MatrixAddFPfS_S_ii, @function
_Z10MatrixAddFPfS_S_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z10MatrixAddFPfS_S_ii, .-_Z10MatrixAddFPfS_S_ii
.section .rodata.str1.8
.align 8
.LC10:
.string "Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n"
.section .rodata.str1.1
.LC11:
.string "float"
.LC13:
.string "int"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L93
movq %rsi, %rbx
movq 32(%rsi), %rdi
leaq .LC11(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
je .L94
.L87:
movq 32(%rbx), %rdi
leaq .LC13(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
je .L95
.L89:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L96
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L93:
.cfi_restore_state
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
leaq 32(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rsi
movq 8(%rbx), %rdi
call _Z12read_fmatrixPcPiS0_PPf
leaq 40(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
movq 16(%rbx), %rdi
call _Z12read_fmatrixPcPiS0_PPf
movl 20(%rsp), %r14d
movl 16(%rsp), %r13d
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movl %r14d, %esi
movl %r13d, %edi
call _Z12matrix_checkiiii
movl %r14d, %eax
imull %r13d, %eax
movl %eax, 4(%rsp)
movslq %eax, %rbp
salq $2, %rbp
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, %r12
movq %rax, 48(%rsp)
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq 32(%rsp), %r15
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdx
movq %rdx, %rsi
movq %rdx, 8(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC12(%rip), %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $256, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L97
.L88:
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rsi
movq 24(%rbx), %rdi
call _Z13write_fmatrixPcPiS0_PPf
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
jmp .L87
.L97:
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z36__device_stub__Z10MatrixAddFPfS_S_iiPfS_S_ii
jmp .L88
.L95:
leaq 32(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rsi
movq 8(%rbx), %rdi
call _Z12read_imatrixPcPiS0_PS0_
leaq 40(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
movq 16(%rbx), %rdi
call _Z12read_imatrixPcPiS0_PS0_
movl 20(%rsp), %r14d
movl 16(%rsp), %r13d
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movl %r14d, %esi
movl %r13d, %edi
call _Z12matrix_checkiiii
movl %r14d, %eax
imull %r13d, %eax
movl %eax, 4(%rsp)
movslq %eax, %rdi
leaq 0(,%rdi,4), %rbp
movl $4, %esi
call calloc@PLT
movq %rax, %r12
movq %rax, 48(%rsp)
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq 32(%rsp), %r15
movl $1, %ecx
movq %rbp, %rdx
movq %r15, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rcx
movq %rcx, %rsi
movq %rcx, 8(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
mulss .LC12(%rip), %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $256, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L90:
movl $2, %ecx
movq %rbp, %rdx
movq 72(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq 16(%rsp), %rsi
movq 24(%rbx), %rdi
call _Z13write_imatrixPcPiS0_PS0_
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
jmp .L89
.L98:
movl %r14d, %r8d
movl %r13d, %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z36__device_stub__Z10MatrixAddIPiS_S_iiPiS_S_ii
jmp .L90
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10MatrixAddFPfS_S_ii"
.LC15:
.string "_Z10MatrixAddIPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MatrixAddFPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MatrixAddIPiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC12:
.long 998244352
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define BLOCKSIZE 256
__global__ void MatrixAddI(int *matrix1, int *matrix2, int *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
__global__ void MatrixAddF(float *matrix1, float *matrix2, float *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
void read_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (int *)calloc(t1*t2, sizeof(int));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%d,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%d\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void read_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (float *)calloc(t1*t2, sizeof(float));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%f,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%f\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void write_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%d,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%d\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void write_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%f,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%f\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void matrix_check(int m1, int n1, int m2, int n2)
{
if ((m1-m2)+(n1-n2) != 0)
{
printf("Matrix dimensions must be PxQ and PxQ respectively\n");
exit(1);
}
}
int main(int argc, char *argv[])
{
int m1, n1, m2, n2;
if (argc != 5)
{
printf("Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n");
exit(1);
}
if (strcmp(argv[4], "float") == 0)
{
float *hostmatrix1, *hostmatrix2, *hostmatrix3;
float *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_fmatrix(argv[1], &m1, &n1, &hostmatrix1);
read_fmatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(float);
hostmatrix3 = (float *)calloc(matrix_size, sizeof(float));
cudaMalloc(&devicematrix1, matrix_size);
cudaMalloc(&devicematrix2, matrix_size);
cudaMalloc(&devicematrix3, matrix_size);
cudaMemcpy(devicematrix1, hostmatrix1, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(devicematrix2, hostmatrix2, matrix_size, cudaMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddF <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
cudaMemcpy(hostmatrix3, devicematrix3, matrix_size, cudaMemcpyDeviceToHost);
write_fmatrix(argv[3], &m1, &n1, &hostmatrix3);
cudaFree(devicematrix1);
cudaFree(devicematrix2);
cudaFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
if (strcmp(argv[4], "int") == 0)
{
int *hostmatrix1, *hostmatrix2, *hostmatrix3;
int *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_imatrix(argv[1], &m1, &n1, &hostmatrix1);
read_imatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(int);
hostmatrix3 = (int *)calloc(m1*n1, sizeof(int));
cudaMalloc(&devicematrix1, matrix_size);
cudaMalloc(&devicematrix2, matrix_size);
cudaMalloc(&devicematrix3, matrix_size);
cudaMemcpy(devicematrix1, hostmatrix1, matrix_size, cudaMemcpyHostToDevice);
cudaMemcpy(devicematrix2, hostmatrix2, matrix_size, cudaMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddI <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
cudaMemcpy(hostmatrix3, devicematrix3, matrix_size, cudaMemcpyDeviceToHost);
write_imatrix(argv[3], &m1, &n1, &hostmatrix3);
cudaFree(devicematrix1);
cudaFree(devicematrix2);
cudaFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE 256
__global__ void MatrixAddI(int *matrix1, int *matrix2, int *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
__global__ void MatrixAddF(float *matrix1, float *matrix2, float *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
void read_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (int *)calloc(t1*t2, sizeof(int));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%d,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%d\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void read_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (float *)calloc(t1*t2, sizeof(float));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%f,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%f\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void write_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%d,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%d\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void write_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%f,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%f\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void matrix_check(int m1, int n1, int m2, int n2)
{
if ((m1-m2)+(n1-n2) != 0)
{
printf("Matrix dimensions must be PxQ and PxQ respectively\n");
exit(1);
}
}
int main(int argc, char *argv[])
{
int m1, n1, m2, n2;
if (argc != 5)
{
printf("Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n");
exit(1);
}
if (strcmp(argv[4], "float") == 0)
{
float *hostmatrix1, *hostmatrix2, *hostmatrix3;
float *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_fmatrix(argv[1], &m1, &n1, &hostmatrix1);
read_fmatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(float);
hostmatrix3 = (float *)calloc(matrix_size, sizeof(float));
hipMalloc(&devicematrix1, matrix_size);
hipMalloc(&devicematrix2, matrix_size);
hipMalloc(&devicematrix3, matrix_size);
hipMemcpy(devicematrix1, hostmatrix1, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(devicematrix2, hostmatrix2, matrix_size, hipMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddF <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
hipMemcpy(hostmatrix3, devicematrix3, matrix_size, hipMemcpyDeviceToHost);
write_fmatrix(argv[3], &m1, &n1, &hostmatrix3);
hipFree(devicematrix1);
hipFree(devicematrix2);
hipFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
if (strcmp(argv[4], "int") == 0)
{
int *hostmatrix1, *hostmatrix2, *hostmatrix3;
int *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_imatrix(argv[1], &m1, &n1, &hostmatrix1);
read_imatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(int);
hostmatrix3 = (int *)calloc(m1*n1, sizeof(int));
hipMalloc(&devicematrix1, matrix_size);
hipMalloc(&devicematrix2, matrix_size);
hipMalloc(&devicematrix3, matrix_size);
hipMemcpy(devicematrix1, hostmatrix1, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(devicematrix2, hostmatrix2, matrix_size, hipMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddI <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
hipMemcpy(hostmatrix3, devicematrix3, matrix_size, hipMemcpyDeviceToHost);
write_imatrix(argv[3], &m1, &n1, &hostmatrix3);
hipFree(devicematrix1);
hipFree(devicematrix2);
hipFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE 256
__global__ void MatrixAddI(int *matrix1, int *matrix2, int *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
__global__ void MatrixAddF(float *matrix1, float *matrix2, float *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
void read_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (int *)calloc(t1*t2, sizeof(int));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%d,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%d\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void read_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (float *)calloc(t1*t2, sizeof(float));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%f,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%f\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void write_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%d,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%d\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void write_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%f,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%f\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void matrix_check(int m1, int n1, int m2, int n2)
{
if ((m1-m2)+(n1-n2) != 0)
{
printf("Matrix dimensions must be PxQ and PxQ respectively\n");
exit(1);
}
}
int main(int argc, char *argv[])
{
int m1, n1, m2, n2;
if (argc != 5)
{
printf("Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n");
exit(1);
}
if (strcmp(argv[4], "float") == 0)
{
float *hostmatrix1, *hostmatrix2, *hostmatrix3;
float *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_fmatrix(argv[1], &m1, &n1, &hostmatrix1);
read_fmatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(float);
hostmatrix3 = (float *)calloc(matrix_size, sizeof(float));
hipMalloc(&devicematrix1, matrix_size);
hipMalloc(&devicematrix2, matrix_size);
hipMalloc(&devicematrix3, matrix_size);
hipMemcpy(devicematrix1, hostmatrix1, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(devicematrix2, hostmatrix2, matrix_size, hipMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddF <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
hipMemcpy(hostmatrix3, devicematrix3, matrix_size, hipMemcpyDeviceToHost);
write_fmatrix(argv[3], &m1, &n1, &hostmatrix3);
hipFree(devicematrix1);
hipFree(devicematrix2);
hipFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
if (strcmp(argv[4], "int") == 0)
{
int *hostmatrix1, *hostmatrix2, *hostmatrix3;
int *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_imatrix(argv[1], &m1, &n1, &hostmatrix1);
read_imatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(int);
hostmatrix3 = (int *)calloc(m1*n1, sizeof(int));
hipMalloc(&devicematrix1, matrix_size);
hipMalloc(&devicematrix2, matrix_size);
hipMalloc(&devicematrix3, matrix_size);
hipMemcpy(devicematrix1, hostmatrix1, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(devicematrix2, hostmatrix2, matrix_size, hipMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddI <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
hipMemcpy(hostmatrix3, devicematrix3, matrix_size, hipMemcpyDeviceToHost);
write_imatrix(argv[3], &m1, &n1, &hostmatrix3);
hipFree(devicematrix1);
hipFree(devicematrix2);
hipFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10MatrixAddIPiS_S_ii
.globl _Z10MatrixAddIPiS_S_ii
.p2align 8
.type _Z10MatrixAddIPiS_S_ii,@function
_Z10MatrixAddIPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MatrixAddIPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10MatrixAddIPiS_S_ii, .Lfunc_end0-_Z10MatrixAddIPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10MatrixAddFPfS_S_ii
.globl _Z10MatrixAddFPfS_S_ii
.p2align 8
.type _Z10MatrixAddFPfS_S_ii,@function
_Z10MatrixAddFPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MatrixAddFPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10MatrixAddFPfS_S_ii, .Lfunc_end1-_Z10MatrixAddFPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MatrixAddIPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10MatrixAddIPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MatrixAddFPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10MatrixAddFPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define BLOCKSIZE 256
__global__ void MatrixAddI(int *matrix1, int *matrix2, int *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
__global__ void MatrixAddF(float *matrix1, float *matrix2, float *matrix3, int m, int n)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
if (x < m*n)
{
matrix3[x] = matrix1[x] + matrix2[x];
}
}
void read_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (int *)calloc(t1*t2, sizeof(int));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%d,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%d\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void read_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "r+");
if(name != NULL)
{
k = 0;
fscanf(name, "%d %d\n", &t1, &t2);
*m = t1;
*n = t2;
*values = (float *)calloc(t1*t2, sizeof(float));
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
fscanf(name, "%f,", &t3);
*(*values+k) = t3;
k++;
}
else
{
fscanf(name, "%f\n", &t3);
*(*values+k) = t3;
k++;
}
}
}
fclose(name);
}
else
{
printf("File read failed\n");
exit(1);
}
}
void write_imatrix(char *filename, int *m, int *n, int **values)
{
FILE* name;
int i, j, k;
int t1, t2, t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%d,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%d\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void write_fmatrix(char *filename, int *m, int *n, float **values)
{
FILE* name;
int i, j, k;
int t1, t2;
float t3;
name = fopen(filename, "w+");
if(name != NULL)
{
k = 0;
t1 = *m;
t2 = *n;
fprintf(name, "%d %d\n", t1, t2);
for(i = 1; i <= t1; i++)
{
for(j = 1; j <= t2; j++)
{
if(j < t2)
{
t3 = *(*values+k);
fprintf(name, "%f,", t3);
k++;
}
else
{
t3 = *(*values+k);
fprintf(name, "%f\n", t3);
k++;
}
}
}
fclose(name);
}
else
{
printf("File write failed\n");
exit(1);
}
}
void matrix_check(int m1, int n1, int m2, int n2)
{
if ((m1-m2)+(n1-n2) != 0)
{
printf("Matrix dimensions must be PxQ and PxQ respectively\n");
exit(1);
}
}
int main(int argc, char *argv[])
{
int m1, n1, m2, n2;
if (argc != 5)
{
printf("Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int \n");
exit(1);
}
if (strcmp(argv[4], "float") == 0)
{
float *hostmatrix1, *hostmatrix2, *hostmatrix3;
float *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_fmatrix(argv[1], &m1, &n1, &hostmatrix1);
read_fmatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(float);
hostmatrix3 = (float *)calloc(matrix_size, sizeof(float));
hipMalloc(&devicematrix1, matrix_size);
hipMalloc(&devicematrix2, matrix_size);
hipMalloc(&devicematrix3, matrix_size);
hipMemcpy(devicematrix1, hostmatrix1, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(devicematrix2, hostmatrix2, matrix_size, hipMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddF <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
hipMemcpy(hostmatrix3, devicematrix3, matrix_size, hipMemcpyDeviceToHost);
write_fmatrix(argv[3], &m1, &n1, &hostmatrix3);
hipFree(devicematrix1);
hipFree(devicematrix2);
hipFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
if (strcmp(argv[4], "int") == 0)
{
int *hostmatrix1, *hostmatrix2, *hostmatrix3;
int *devicematrix1, *devicematrix2, *devicematrix3;
int GRIDSIZE;
read_imatrix(argv[1], &m1, &n1, &hostmatrix1);
read_imatrix(argv[2], &m2, &n2, &hostmatrix2);
matrix_check(m1, n1, m2, n2);
size_t matrix_size = m1*n1*sizeof(int);
hostmatrix3 = (int *)calloc(m1*n1, sizeof(int));
hipMalloc(&devicematrix1, matrix_size);
hipMalloc(&devicematrix2, matrix_size);
hipMalloc(&devicematrix3, matrix_size);
hipMemcpy(devicematrix1, hostmatrix1, matrix_size, hipMemcpyHostToDevice);
hipMemcpy(devicematrix2, hostmatrix2, matrix_size, hipMemcpyHostToDevice);
GRIDSIZE = (int)ceil((float)(m1*n1)/BLOCKSIZE);
dim3 dimGrid(GRIDSIZE, 1, 1);
dim3 dimBlock(BLOCKSIZE, 1, 1);
MatrixAddI <<< dimGrid, dimBlock >>> (devicematrix1, devicematrix2, devicematrix3, m1, n1);
hipMemcpy(hostmatrix3, devicematrix3, matrix_size, hipMemcpyDeviceToHost);
write_imatrix(argv[3], &m1, &n1, &hostmatrix3);
hipFree(devicematrix1);
hipFree(devicematrix2);
hipFree(devicematrix3);
free(hostmatrix1);
free(hostmatrix2);
free(hostmatrix3);
}
return 0;
} | .text
.file "matrix-addition.hip"
.globl _Z25__device_stub__MatrixAddIPiS_S_ii # -- Begin function _Z25__device_stub__MatrixAddIPiS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__MatrixAddIPiS_S_ii,@function
_Z25__device_stub__MatrixAddIPiS_S_ii: # @_Z25__device_stub__MatrixAddIPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10MatrixAddIPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__MatrixAddIPiS_S_ii, .Lfunc_end0-_Z25__device_stub__MatrixAddIPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__MatrixAddFPfS_S_ii # -- Begin function _Z25__device_stub__MatrixAddFPfS_S_ii
.p2align 4, 0x90
.type _Z25__device_stub__MatrixAddFPfS_S_ii,@function
_Z25__device_stub__MatrixAddFPfS_S_ii: # @_Z25__device_stub__MatrixAddFPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10MatrixAddFPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__MatrixAddFPfS_S_ii, .Lfunc_end1-_Z25__device_stub__MatrixAddFPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z12read_imatrixPcPiS0_PS0_ # -- Begin function _Z12read_imatrixPcPiS0_PS0_
.p2align 4, 0x90
.type _Z12read_imatrixPcPiS0_PS0_,@function
_Z12read_imatrixPcPiS0_PS0_: # @_Z12read_imatrixPcPiS0_PS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB2_12
# %bb.1:
movq %rax, %r14
leaq 12(%rsp), %rdx
leaq 8(%rsp), %rcx
movl $.L.str.1, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movl %eax, (%r12)
movl 8(%rsp), %ecx
movl %ecx, (%r15)
imull %eax, %ecx
movslq %ecx, %rdi
movl $4, %esi
callq calloc
movq %rax, (%rbx)
cmpl $0, 12(%rsp)
jle .LBB2_11
# %bb.2: # %.preheader.preheader
movl $1, %r12d
leaq 20(%rsp), %r15
xorl %ecx, %ecx
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_9: # %._crit_edge.loopexit
# in Loop: Header=BB2_3 Depth=1
movl 16(%rsp), %ecx # 4-byte Reload
addl %ebp, %ecx
.LBB2_10: # %._crit_edge
# in Loop: Header=BB2_3 Depth=1
leal 1(%r12), %eax
cmpl 12(%rsp), %r12d
movl %eax, %r12d
jge .LBB2_11
.LBB2_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_5 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB2_10
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB2_3 Depth=1
movl %ecx, 16(%rsp) # 4-byte Spill
movslq %ecx, %r13
shlq $2, %r13
xorl %ebp, %ebp
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=2
movl $.L.str.3, %esi
.LBB2_8: # in Loop: Header=BB2_5 Depth=2
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 20(%rsp), %eax
movq (%rbx), %rcx
addq %r13, %rcx
movl %eax, (%rcx,%rbp,4)
movl 8(%rsp), %eax
incq %rbp
cmpl %eax, %ebp
jge .LBB2_9
.LBB2_5: # %.lr.ph
# Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
leal 1(%rbp), %ecx
cmpl %eax, %ecx
jge .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=2
movl $.L.str.2, %esi
jmp .LBB2_8
.LBB2_11: # %._crit_edge31
movq %r14, %rdi
callq fclose
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_12:
.cfi_def_cfa_offset 80
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z12read_imatrixPcPiS0_PS0_, .Lfunc_end2-_Z12read_imatrixPcPiS0_PS0_
.cfi_endproc
# -- End function
.globl _Z12read_fmatrixPcPiS0_PPf # -- Begin function _Z12read_fmatrixPcPiS0_PPf
.p2align 4, 0x90
.type _Z12read_fmatrixPcPiS0_PPf,@function
_Z12read_fmatrixPcPiS0_PPf: # @_Z12read_fmatrixPcPiS0_PPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB3_12
# %bb.1:
movq %rax, %r14
leaq 12(%rsp), %rdx
leaq 8(%rsp), %rcx
movl $.L.str.1, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 12(%rsp), %eax
movl %eax, (%r12)
movl 8(%rsp), %ecx
movl %ecx, (%r15)
imull %eax, %ecx
movslq %ecx, %rdi
movl $4, %esi
callq calloc
movq %rax, (%rbx)
cmpl $0, 12(%rsp)
jle .LBB3_11
# %bb.2: # %.preheader.preheader
movl $1, %r12d
leaq 20(%rsp), %r15
xorl %ecx, %ecx
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_9: # %._crit_edge.loopexit
# in Loop: Header=BB3_3 Depth=1
movl 16(%rsp), %ecx # 4-byte Reload
addl %ebp, %ecx
.LBB3_10: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
leal 1(%r12), %eax
cmpl 12(%rsp), %r12d
movl %eax, %r12d
jge .LBB3_11
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB3_10
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=1
movl %ecx, 16(%rsp) # 4-byte Spill
movslq %ecx, %r13
shlq $2, %r13
xorl %ebp, %ebp
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # in Loop: Header=BB3_5 Depth=2
movl $.L.str.6, %esi
.LBB3_8: # in Loop: Header=BB3_5 Depth=2
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq (%rbx), %rax
addq %r13, %rax
movss %xmm0, (%rax,%rbp,4)
movl 8(%rsp), %eax
incq %rbp
cmpl %eax, %ebp
jge .LBB3_9
.LBB3_5: # %.lr.ph
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
leal 1(%rbp), %ecx
cmpl %eax, %ecx
jge .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=2
movl $.L.str.5, %esi
jmp .LBB3_8
.LBB3_11: # %._crit_edge31
movq %r14, %rdi
callq fclose
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 80
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z12read_fmatrixPcPiS0_PPf, .Lfunc_end3-_Z12read_fmatrixPcPiS0_PPf
.cfi_endproc
# -- End function
.globl _Z13write_imatrixPcPiS0_PS0_ # -- Begin function _Z13write_imatrixPcPiS0_PS0_
.p2align 4, 0x90
.type _Z13write_imatrixPcPiS0_PS0_,@function
_Z13write_imatrixPcPiS0_PS0_: # @_Z13write_imatrixPcPiS0_PS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB4_9
# %bb.1:
movq %rax, %r14
movl (%r12), %ebp
movl (%r15), %r15d
movl $.L.str.1, %esi
movq %rax, %rdi
movl %ebp, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
jle .LBB4_8
# %bb.2: # %.preheader.lr.ph
movl %r15d, %r12d
negl %r12d
movl $1, %edx
movl $.L.str.2, %ecx
xorl %ebp, %ebp
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_3 Depth=1
leal 1(%rdx), %eax
cmpl 12(%rsp), %edx # 4-byte Folded Reload
movl %eax, %edx
je .LBB4_8
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
testl %r15d, %r15d
jle .LBB4_7
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB4_3 Depth=1
movq %rdx, 16(%rsp) # 8-byte Spill
movslq %ebp, %rbp
movl $1, %r13d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %r15d, %r13d
movq (%rbx), %rax
movl (%rax,%rbp,4), %edx
movl $.L.str.3, %esi
cmovlq %rcx, %rsi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %rbp
leal (%r12,%r13), %eax
incl %eax
movl %r13d, %ecx
incl %ecx
movl %ecx, %r13d
movl $.L.str.2, %ecx
cmpl $1, %eax
jne .LBB4_5
# %bb.6: # in Loop: Header=BB4_3 Depth=1
movq 16(%rsp), %rdx # 8-byte Reload
jmp .LBB4_7
.LBB4_8: # %._crit_edge37
movq %r14, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB4_9:
.cfi_def_cfa_offset 80
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z13write_imatrixPcPiS0_PS0_, .Lfunc_end4-_Z13write_imatrixPcPiS0_PS0_
.cfi_endproc
# -- End function
.globl _Z13write_fmatrixPcPiS0_PPf # -- Begin function _Z13write_fmatrixPcPiS0_PPf
.p2align 4, 0x90
.type _Z13write_fmatrixPcPiS0_PPf,@function
_Z13write_fmatrixPcPiS0_PPf: # @_Z13write_fmatrixPcPiS0_PPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movl $.L.str.7, %esi
callq fopen
testq %rax, %rax
je .LBB5_9
# %bb.1:
movq %rax, %r14
movl (%r12), %ebp
movl (%r15), %r15d
xorl %r12d, %r12d
movl $.L.str.1, %esi
movq %rax, %rdi
movl %ebp, %edx
movl %r15d, %ecx
xorl %eax, %eax
callq fprintf
movl %ebp, 12(%rsp) # 4-byte Spill
testl %ebp, %ebp
jle .LBB5_8
# %bb.2: # %.preheader.lr.ph
movl %r15d, %r13d
negl %r13d
movl $1, %edx
movl $.L.str.5, %ecx
jmp .LBB5_3
.p2align 4, 0x90
.LBB5_7: # %._crit_edge
# in Loop: Header=BB5_3 Depth=1
leal 1(%rdx), %eax
cmpl 12(%rsp), %edx # 4-byte Folded Reload
movl %eax, %edx
je .LBB5_8
.LBB5_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_5 Depth 2
testl %r15d, %r15d
jle .LBB5_7
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB5_3 Depth=1
movq %rdx, 16(%rsp) # 8-byte Spill
movslq %r12d, %r12
movl $1, %ebp
.p2align 4, 0x90
.LBB5_5: # %.lr.ph
# Parent Loop BB5_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %r15d, %ebp
movq (%rbx), %rax
movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %esi
cmovlq %rcx, %rsi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %r12
leal 1(%r13,%rbp), %eax
movl %ebp, %ecx
incl %ecx
movl %ecx, %ebp
movl $.L.str.5, %ecx
cmpl $1, %eax
jne .LBB5_5
# %bb.6: # in Loop: Header=BB5_3 Depth=1
movq 16(%rsp), %rdx # 8-byte Reload
jmp .LBB5_7
.LBB5_8: # %._crit_edge37
movq %r14, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.LBB5_9:
.cfi_def_cfa_offset 80
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end5:
.size _Z13write_fmatrixPcPiS0_PPf, .Lfunc_end5-_Z13write_fmatrixPcPiS0_PPf
.cfi_endproc
# -- End function
.globl _Z12matrix_checkiiii # -- Begin function _Z12matrix_checkiiii
.p2align 4, 0x90
.type _Z12matrix_checkiiii,@function
_Z12matrix_checkiiii: # @_Z12matrix_checkiiii
.cfi_startproc
# %bb.0:
subl %edx, %edi
subl %esi, %ecx
cmpl %ecx, %edi
jne .LBB6_2
# %bb.1:
retq
.LBB6_2:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.4, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end6:
.size _Z12matrix_checkiiii, .Lfunc_end6-_Z12matrix_checkiiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI7_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB7_1
# %bb.3:
movq %rsi, %rbx
movq 32(%rsi), %rdi
movl $.L.str.11, %esi
callq strcmp
testl %eax, %eax
jne .LBB7_9
# %bb.4:
movq 8(%rbx), %rdi
leaq 4(%rsp), %rsi
movq %rsp, %rdx
leaq 80(%rsp), %rcx
callq _Z12read_fmatrixPcPiS0_PPf
movq 16(%rbx), %rdi
leaq 36(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 72(%rsp), %rcx
callq _Z12read_fmatrixPcPiS0_PPf
movl 4(%rsp), %ebp
movl (%rsp), %r15d
movl 32(%rsp), %eax
movl %ebp, %ecx
subl 36(%rsp), %ecx
subl %r15d, %eax
cmpl %eax, %ecx
jne .LBB7_5
# %bb.6: # %_Z12matrix_checkiiii.exit
movl %r15d, %eax
imull %ebp, %eax
movslq %eax, %r13
leaq (,%r13,4), %r12
movl $4, %esi
movq %r12, %rdi
callq calloc
movq %rax, %r14
movq %rax, 64(%rsp)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq 80(%rsp), %rsi
movq %rsi, 56(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi
movq %rsi, 48(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r13d, %xmm0
mulss .LCPI7_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %ebp, 44(%rsp)
movl %r15d, 40(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10MatrixAddFPfS_S_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_8:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rbx), %rdi
leaq 4(%rsp), %rsi
movq %rsp, %rdx
leaq 64(%rsp), %rcx
callq _Z13write_fmatrixPcPiS0_PPf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
.LBB7_9:
movq 32(%rbx), %rdi
movl $.L.str.12, %esi
callq strcmp
testl %eax, %eax
jne .LBB7_14
# %bb.10:
movq 8(%rbx), %rdi
leaq 4(%rsp), %rsi
movq %rsp, %rdx
leaq 80(%rsp), %rcx
callq _Z12read_imatrixPcPiS0_PS0_
movq 16(%rbx), %rdi
leaq 36(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 72(%rsp), %rcx
callq _Z12read_imatrixPcPiS0_PS0_
movl 4(%rsp), %r15d
movl (%rsp), %r13d
movl 32(%rsp), %eax
movl %r15d, %ecx
subl 36(%rsp), %ecx
subl %r13d, %eax
cmpl %eax, %ecx
jne .LBB7_5
# %bb.11: # %_Z12matrix_checkiiii.exit42
movl %r13d, %eax
imull %r15d, %eax
movslq %eax, %rbp
leaq (,%rbp,4), %r12
movl $4, %esi
movq %rbp, %rdi
callq calloc
movq %rax, %r14
movq %rax, 64(%rsp)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq 80(%rsp), %rsi
movq %rsi, 56(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi
movq %rsi, 48(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %ebp, %xmm0
mulss .LCPI7_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r15d, 44(%rsp)
movl %r13d, 40(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10MatrixAddIPiS_S_ii, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_13:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rbx), %rdi
leaq 4(%rsp), %rsi
movq %rsp, %rdx
leaq 64(%rsp), %rcx
callq _Z13write_imatrixPcPiS0_PS0_
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi # 8-byte Reload
callq free
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
.LBB7_14:
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_1:
.cfi_def_cfa_offset 256
movl $.Lstr.5, %edi
jmp .LBB7_2
.LBB7_5:
movl $.Lstr.4, %edi
.LBB7_2:
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MatrixAddIPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MatrixAddFPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10MatrixAddIPiS_S_ii,@object # @_Z10MatrixAddIPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z10MatrixAddIPiS_S_ii
.p2align 3, 0x0
_Z10MatrixAddIPiS_S_ii:
.quad _Z25__device_stub__MatrixAddIPiS_S_ii
.size _Z10MatrixAddIPiS_S_ii, 8
.type _Z10MatrixAddFPfS_S_ii,@object # @_Z10MatrixAddFPfS_S_ii
.globl _Z10MatrixAddFPfS_S_ii
.p2align 3, 0x0
_Z10MatrixAddFPfS_S_ii:
.quad _Z25__device_stub__MatrixAddFPfS_S_ii
.size _Z10MatrixAddFPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r+"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d\n"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d,"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d\n"
.size .L.str.3, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f,"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%f\n"
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w+"
.size .L.str.7, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "float"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "int"
.size .L.str.12, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10MatrixAddIPiS_S_ii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10MatrixAddFPfS_S_ii"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "File read failed"
.size .Lstr.1, 17
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "File write failed"
.size .Lstr.3, 18
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Matrix dimensions must be PxQ and PxQ respectively"
.size .Lstr.4, 51
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Usage: ./matrix-addition matrix1.mat matrix2.mat matrix3.mat float/int "
.size .Lstr.5, 72
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__MatrixAddIPiS_S_ii
.addrsig_sym _Z25__device_stub__MatrixAddFPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10MatrixAddIPiS_S_ii
.addrsig_sym _Z10MatrixAddFPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10MatrixAddFPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10MatrixAddIPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00f0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10MatrixAddIPiS_S_ii
.globl _Z10MatrixAddIPiS_S_ii
.p2align 8
.type _Z10MatrixAddIPiS_S_ii,@function
_Z10MatrixAddIPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MatrixAddIPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10MatrixAddIPiS_S_ii, .Lfunc_end0-_Z10MatrixAddIPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10MatrixAddFPfS_S_ii
.globl _Z10MatrixAddFPfS_S_ii
.p2align 8
.type _Z10MatrixAddFPfS_S_ii,@function
_Z10MatrixAddFPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MatrixAddFPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10MatrixAddFPfS_S_ii, .Lfunc_end1-_Z10MatrixAddFPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MatrixAddIPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10MatrixAddIPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MatrixAddFPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10MatrixAddFPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //xfail:BOOGIE_ERROR
//--blockDim=2 --gridDim=1 --no-inline
//Write by thread .+kernel.cu:8:4:
// to threadIdx.x != 0 we have 'data race'.
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>
#define N 8 //2
__global__ void init_test(curandState *state, unsigned int *A) {
curand_init(0, 0, 0, state);
__syncthreads();
A[threadIdx.x] = curand(&state[threadIdx.x]);
// if (threadIdx.x == 0) {
// A[0] = curand(state);
//}
} | code for sm_80
Function : _Z9init_testP17curandStateXORWOWPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R15, -RZ, RZ, 132.125, 1.705078125 ; /* 0x58213ed2ff0f7435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R19, -RZ, RZ, 40.90625, -0.151123046875 ; /* 0x511db0d6ff137435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R14, RZ, RZ, 0x2abc4dd5 ; /* 0x2abc4dd5ff0e7424 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R17, 0xf8a42704 ; /* 0xf8a4270400117802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R16, RZ, RZ, 0x455f2458 ; /* 0x455f2458ff107424 */
/* 0x000fe200078e00ff */
/*0080*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0090*/ IMAD.MOV.U32 R18, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff127424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x30 ; /* 0x00000030ff037424 */
/* 0x000fe200078e00ff */
/*00c0*/ STG.E.64 [R8.64], R14 ; /* 0x0000000e08007986 */
/* 0x000fe8000c101b04 */
/*00d0*/ STG.E.64 [R8.64+0x8], R16 ; /* 0x0000081008007986 */
/* 0x000fe8000c101b04 */
/*00e0*/ STG.E.64 [R8.64+0x10], R18 ; /* 0x0000101208007986 */
/* 0x000fe8000c101b04 */
/*00f0*/ STG.E.64 [R8.64+0x18], RZ ; /* 0x000018ff08007986 */
/* 0x000fe8000c101b04 */
/*0100*/ STG.E [R8.64+0x20], RZ ; /* 0x000020ff08007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E.64 [R8.64+0x28], RZ ; /* 0x000028ff08007986 */
/* 0x0003e2000c101b04 */
/*0120*/ IMAD.WIDE.U32 R2, R12, R3, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x001fc600078e0003 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ee8000c1e1b00 */
/*0160*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000f22000c1e1b00 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE.U32 R8, R12, R13, c[0x0][0x168] ; /* 0x00005a000c087625 */
/* 0x002fe200078e000d */
/*0190*/ SHF.R.U32.HI R0, RZ, 0x2, R11 ; /* 0x00000002ff007819 */
/* 0x004fe4000001160b */
/*01a0*/ IADD3 R10, R10, 0x587c5, RZ ; /* 0x000587c50a0a7810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ LOP3.LUT R0, R0, R11, RZ, 0x3c, !PT ; /* 0x0000000b00007212 */
/* 0x000fe200078e3cff */
/*01c0*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x008fe200078e0004 */
/*01d0*/ MOV R14, R5 ; /* 0x00000005000e7202 */
/* 0x000fe40000000f00 */
/*01e0*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x000fe200000006ff */
/*01f0*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x010fc600078e0007 */
/*0200*/ LOP3.LUT R11, R5.reuse, R11, R0, 0x96, !PT ; /* 0x0000000b050b7212 */
/* 0x040fe400078e9600 */
/*0210*/ SHF.L.U32 R0, R5, 0x4, RZ ; /* 0x0000000405007819 */
/* 0x000fe200000006ff */
/*0220*/ STG.E.64 [R2.64+0x8], R12 ; /* 0x0000080c02007986 */
/* 0x000fe6000c101b04 */
/*0230*/ LOP3.LUT R15, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0f7212 */
/* 0x000fe400078e3cff */
/*0240*/ MOV R11, R6 ; /* 0x00000006000b7202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.IADD R5, R15, 0x1, R10 ; /* 0x000000010f057824 */
/* 0x000fe200078e020a */
/*0260*/ STG.E.64 [R2.64+0x10], R14 ; /* 0x0000100e02007986 */
/* 0x000fe8000c101b04 */
/*0270*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe8000c101b04 */
/*0280*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //xfail:BOOGIE_ERROR
//--blockDim=2 --gridDim=1 --no-inline
//Write by thread .+kernel.cu:8:4:
// to threadIdx.x != 0 we have 'data race'.
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>
#define N 8 //2
__global__ void init_test(curandState *state, unsigned int *A) {
curand_init(0, 0, 0, state);
__syncthreads();
A[threadIdx.x] = curand(&state[threadIdx.x]);
// if (threadIdx.x == 0) {
// A[0] = curand(state);
//}
} | .file "tmpxft_00040f59_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj
.type _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj, @function
_Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj:
.LFB2295:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9init_testP17curandStateXORWOWPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj, .-_Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj
.globl _Z9init_testP17curandStateXORWOWPj
.type _Z9init_testP17curandStateXORWOWPj, @function
_Z9init_testP17curandStateXORWOWPj:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size _Z9init_testP17curandStateXORWOWPj, .-_Z9init_testP17curandStateXORWOWPj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z9init_testP17curandStateXORWOWPj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9init_testP17curandStateXORWOWPj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //xfail:BOOGIE_ERROR
//--blockDim=2 --gridDim=1 --no-inline
//Write by thread .+kernel.cu:8:4:
// to threadIdx.x != 0 we have 'data race'.
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>
#define N 8 //2
__global__ void init_test(curandState *state, unsigned int *A) {
curand_init(0, 0, 0, state);
__syncthreads();
A[threadIdx.x] = curand(&state[threadIdx.x]);
// if (threadIdx.x == 0) {
// A[0] = curand(state);
//}
} | //xfail:BOOGIE_ERROR
//--blockDim=2 --gridDim=1 --no-inline
//Write by thread .+kernel.cu:8:4:
// to threadIdx.x != 0 we have 'data race'.
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
#define N 8 //2
__global__ void init_test(hiprandState *state, unsigned int *A) {
hiprand_init(0, 0, 0, state);
__syncthreads();
A[threadIdx.x] = hiprand(&state[threadIdx.x]);
// if (threadIdx.x == 0) {
// A[0] = curand(state);
//}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //xfail:BOOGIE_ERROR
//--blockDim=2 --gridDim=1 --no-inline
//Write by thread .+kernel.cu:8:4:
// to threadIdx.x != 0 we have 'data race'.
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
#define N 8 //2
__global__ void init_test(hiprandState *state, unsigned int *A) {
hiprand_init(0, 0, 0, state);
__syncthreads();
A[threadIdx.x] = hiprand(&state[threadIdx.x]);
// if (threadIdx.x == 0) {
// A[0] = curand(state);
//}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9init_testP12hiprandStatePj
.globl _Z9init_testP12hiprandStatePj
.p2align 8
.type _Z9init_testP12hiprandStatePj,@function
_Z9init_testP12hiprandStatePj:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v1, 0x61de28f4
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v5, 0xe544adf7
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0x4f180e3a :: v_dual_mov_b32 v7, v6
v_mov_b32_e32 v3, 0xa96f9d04
v_mov_b32_e32 v4, 0x8f14727c
v_mov_b32_e32 v11, 0x5ada9af8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[8:9], null, v0, 48, s[0:1]
v_lshlrev_b32_e32 v0, 2, v0
s_clause 0x2
global_store_b96 v10, v[5:7], s[0:1]
global_store_b128 v10, v[1:4], s[0:1] offset:24
global_store_b32 v10, v11, s[0:1] offset:40
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x2
global_load_b128 v[1:4], v[8:9], off offset:24
global_load_b32 v5, v[8:9], off offset:40
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v7, 2, v1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, 0x587c5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v7, v1
v_lshlrev_b32_e32 v7, 4, v5
v_lshlrev_b32_e32 v10, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v7, v10, v7
v_xor3_b32 v1, v7, v1, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v6, v1
s_clause 0x2
global_store_b32 v[8:9], v1, off offset:40
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b32 v[8:9], v6, off
global_store_b32 v0, v7, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9init_testP12hiprandStatePj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9init_testP12hiprandStatePj, .Lfunc_end0-_Z9init_testP12hiprandStatePj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9init_testP12hiprandStatePj
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9init_testP12hiprandStatePj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //xfail:BOOGIE_ERROR
//--blockDim=2 --gridDim=1 --no-inline
//Write by thread .+kernel.cu:8:4:
// to threadIdx.x != 0 we have 'data race'.
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
#define N 8 //2
__global__ void init_test(hiprandState *state, unsigned int *A) {
hiprand_init(0, 0, 0, state);
__syncthreads();
A[threadIdx.x] = hiprand(&state[threadIdx.x]);
// if (threadIdx.x == 0) {
// A[0] = curand(state);
//}
} | .text
.file "main.hip"
.globl _Z24__device_stub__init_testP12hiprandStatePj # -- Begin function _Z24__device_stub__init_testP12hiprandStatePj
.p2align 4, 0x90
.type _Z24__device_stub__init_testP12hiprandStatePj,@function
_Z24__device_stub__init_testP12hiprandStatePj: # @_Z24__device_stub__init_testP12hiprandStatePj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9init_testP12hiprandStatePj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__init_testP12hiprandStatePj, .Lfunc_end0-_Z24__device_stub__init_testP12hiprandStatePj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9init_testP12hiprandStatePj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9init_testP12hiprandStatePj,@object # @_Z9init_testP12hiprandStatePj
.section .rodata,"a",@progbits
.globl _Z9init_testP12hiprandStatePj
.p2align 3, 0x0
_Z9init_testP12hiprandStatePj:
.quad _Z24__device_stub__init_testP12hiprandStatePj
.size _Z9init_testP12hiprandStatePj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9init_testP12hiprandStatePj"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__init_testP12hiprandStatePj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9init_testP12hiprandStatePj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9init_testP17curandStateXORWOWPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ HFMA2.MMA R15, -RZ, RZ, 132.125, 1.705078125 ; /* 0x58213ed2ff0f7435 */
/* 0x000fe200000001ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R19, -RZ, RZ, 40.90625, -0.151123046875 ; /* 0x511db0d6ff137435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R14, RZ, RZ, 0x2abc4dd5 ; /* 0x2abc4dd5ff0e7424 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R17, 0xf8a42704 ; /* 0xf8a4270400117802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R16, RZ, RZ, 0x455f2458 ; /* 0x455f2458ff107424 */
/* 0x000fe200078e00ff */
/*0080*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0090*/ IMAD.MOV.U32 R18, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff127424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x30 ; /* 0x00000030ff037424 */
/* 0x000fe200078e00ff */
/*00c0*/ STG.E.64 [R8.64], R14 ; /* 0x0000000e08007986 */
/* 0x000fe8000c101b04 */
/*00d0*/ STG.E.64 [R8.64+0x8], R16 ; /* 0x0000081008007986 */
/* 0x000fe8000c101b04 */
/*00e0*/ STG.E.64 [R8.64+0x10], R18 ; /* 0x0000101208007986 */
/* 0x000fe8000c101b04 */
/*00f0*/ STG.E.64 [R8.64+0x18], RZ ; /* 0x000018ff08007986 */
/* 0x000fe8000c101b04 */
/*0100*/ STG.E [R8.64+0x20], RZ ; /* 0x000020ff08007986 */
/* 0x000fe8000c101904 */
/*0110*/ STG.E.64 [R8.64+0x28], RZ ; /* 0x000028ff08007986 */
/* 0x0003e2000c101b04 */
/*0120*/ IMAD.WIDE.U32 R2, R12, R3, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x001fc600078e0003 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ee8000c1e1b00 */
/*0160*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000f22000c1e1b00 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE.U32 R8, R12, R13, c[0x0][0x168] ; /* 0x00005a000c087625 */
/* 0x002fe200078e000d */
/*0190*/ SHF.R.U32.HI R0, RZ, 0x2, R11 ; /* 0x00000002ff007819 */
/* 0x004fe4000001160b */
/*01a0*/ IADD3 R10, R10, 0x587c5, RZ ; /* 0x000587c50a0a7810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ LOP3.LUT R0, R0, R11, RZ, 0x3c, !PT ; /* 0x0000000b00007212 */
/* 0x000fe200078e3cff */
/*01c0*/ IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d7224 */
/* 0x008fe200078e0004 */
/*01d0*/ MOV R14, R5 ; /* 0x00000005000e7202 */
/* 0x000fe40000000f00 */
/*01e0*/ SHF.L.U32 R11, R0, 0x1, RZ ; /* 0x00000001000b7819 */
/* 0x000fe200000006ff */
/*01f0*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x010fc600078e0007 */
/*0200*/ LOP3.LUT R11, R5.reuse, R11, R0, 0x96, !PT ; /* 0x0000000b050b7212 */
/* 0x040fe400078e9600 */
/*0210*/ SHF.L.U32 R0, R5, 0x4, RZ ; /* 0x0000000405007819 */
/* 0x000fe200000006ff */
/*0220*/ STG.E.64 [R2.64+0x8], R12 ; /* 0x0000080c02007986 */
/* 0x000fe6000c101b04 */
/*0230*/ LOP3.LUT R15, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b0f7212 */
/* 0x000fe400078e3cff */
/*0240*/ MOV R11, R6 ; /* 0x00000006000b7202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.IADD R5, R15, 0x1, R10 ; /* 0x000000010f057824 */
/* 0x000fe200078e020a */
/*0260*/ STG.E.64 [R2.64+0x10], R14 ; /* 0x0000100e02007986 */
/* 0x000fe8000c101b04 */
/*0270*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x000fe8000c101b04 */
/*0280*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9init_testP12hiprandStatePj
.globl _Z9init_testP12hiprandStatePj
.p2align 8
.type _Z9init_testP12hiprandStatePj,@function
_Z9init_testP12hiprandStatePj:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v1, 0x61de28f4
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v5, 0xe544adf7
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0x4f180e3a :: v_dual_mov_b32 v7, v6
v_mov_b32_e32 v3, 0xa96f9d04
v_mov_b32_e32 v4, 0x8f14727c
v_mov_b32_e32 v11, 0x5ada9af8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[8:9], null, v0, 48, s[0:1]
v_lshlrev_b32_e32 v0, 2, v0
s_clause 0x2
global_store_b96 v10, v[5:7], s[0:1]
global_store_b128 v10, v[1:4], s[0:1] offset:24
global_store_b32 v10, v11, s[0:1] offset:40
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_clause 0x2
global_load_b128 v[1:4], v[8:9], off offset:24
global_load_b32 v5, v[8:9], off offset:40
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v7, 2, v1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, 0x587c5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v7, v1
v_lshlrev_b32_e32 v7, 4, v5
v_lshlrev_b32_e32 v10, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v7, v10, v7
v_xor3_b32 v1, v7, v1, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v7, v6, v1
s_clause 0x2
global_store_b32 v[8:9], v1, off offset:40
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b32 v[8:9], v6, off
global_store_b32 v0, v7, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9init_testP12hiprandStatePj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9init_testP12hiprandStatePj, .Lfunc_end0-_Z9init_testP12hiprandStatePj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9init_testP12hiprandStatePj
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9init_testP12hiprandStatePj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00040f59_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2273:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2273:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj
.type _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj, @function
_Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj:
.LFB2295:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9init_testP17curandStateXORWOWPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2295:
.size _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj, .-_Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj
.globl _Z9init_testP17curandStateXORWOWPj
.type _Z9init_testP17curandStateXORWOWPj, @function
_Z9init_testP17curandStateXORWOWPj:
.LFB2296:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z9init_testP17curandStateXORWOWPjP17curandStateXORWOWPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2296:
.size _Z9init_testP17curandStateXORWOWPj, .-_Z9init_testP17curandStateXORWOWPj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z9init_testP17curandStateXORWOWPj"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "precalc_xorwow_matrix"
.LC2:
.string "precalc_xorwow_offset_matrix"
.LC3:
.string "mrg32k3aM1"
.LC4:
.string "mrg32k3aM2"
.LC5:
.string "mrg32k3aM1SubSeq"
.LC6:
.string "mrg32k3aM2SubSeq"
.LC7:
.string "mrg32k3aM1Seq"
.LC8:
.string "mrg32k3aM2Seq"
.LC9:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2298:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9init_testP17curandStateXORWOWPj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z24__device_stub__init_testP12hiprandStatePj # -- Begin function _Z24__device_stub__init_testP12hiprandStatePj
.p2align 4, 0x90
.type _Z24__device_stub__init_testP12hiprandStatePj,@function
_Z24__device_stub__init_testP12hiprandStatePj: # @_Z24__device_stub__init_testP12hiprandStatePj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9init_testP12hiprandStatePj, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__init_testP12hiprandStatePj, .Lfunc_end0-_Z24__device_stub__init_testP12hiprandStatePj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9init_testP12hiprandStatePj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9init_testP12hiprandStatePj,@object # @_Z9init_testP12hiprandStatePj
.section .rodata,"a",@progbits
.globl _Z9init_testP12hiprandStatePj
.p2align 3, 0x0
_Z9init_testP12hiprandStatePj:
.quad _Z24__device_stub__init_testP12hiprandStatePj
.size _Z9init_testP12hiprandStatePj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9init_testP12hiprandStatePj"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__init_testP12hiprandStatePj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9init_testP12hiprandStatePj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#texture-functions | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#texture-functions | .file "tmpxft_00186d10_00000000-6_textures.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#texture-functions | #include <hip/hip_runtime.h>
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#texture-functions |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#texture-functions | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#texture-functions | .text
.file "textures.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00186d10_00000000-6_textures.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "textures.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
#define n 1024
#define block_size 32
/*
__global__ void mult_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y, blockCol = blockIdx.x;
int row = threadIdx.y, col = threadIdx.x;
for (int m = 0; m < (n/block_size); ++m) {
}
}
*/
__global__ void mul_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
int i,j;
int myx = blockIdx.x * blockDim.x + threadIdx.x;
int myy = blockIdx.y * blockDim.y + threadIdx.y;
int local=0;
__shared__ int As[32][32];
__shared__ int Bs[32][32];
for(i=0;i<n/block_size;i++) {
As[row][col] = a[myx*n + (i*blockDim.y + col)];
Bs[row][col] = b[(i*blockDim.x+row)*n + myy];
__syncthreads();
for(j=0;j<block_size;j++)
local += As[row][j]*Bs[j][col];
__syncthreads();
}
c[myx*n+myy] = local;
}
int main() {
int i;
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
cudaEvent_t start, stop;
float time;
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for(i=0;i<n*n;i++) {
a[i] = 1;
b[i] = 2;
c[i] = 0;
}
int *gpua, *gpub, *gpuc;
cudaMalloc((void**)&gpua, sizeof(int)*n*n);
cudaMalloc((void**)&gpub, sizeof(int)*n*n);
cudaMalloc((void**)&gpuc, sizeof(int)*n*n);
cudaMemcpy(gpua, a, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpub, b, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
mul_mat<<<dimGrid, dimBlock>>> (gpua, gpub, gpuc);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaMemcpy(c, gpuc, sizeof(int)*n*n, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&time, start, stop);
printf("C[451][451] = %d\n",c[451*1024 + 451]);
printf("Time - %f\n", time);
free(a);
free(b);
free(c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(gpua);
cudaFree(gpub);
cudaFree(gpuc);
return 0;
} | code for sm_80
Function : _Z7mul_matPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R16, SR_TID.X ; /* 0x0000000000107919 */
/* 0x000ee20000002100 */
/*0080*/ IMAD R2, R17, c[0x0][0x0], RZ ; /* 0x0000000011027a24 */
/* 0x001fe200078e02ff */
/*0090*/ LEA R4, R0, R0, 0xa ; /* 0x0000000000047211 */
/* 0x002fc800078e50ff */
/*00a0*/ SHF.L.U32 R21, R2, 0xa, RZ ; /* 0x0000000a02157819 */
/* 0x000fe400000006ff */
/*00b0*/ SHF.L.U32 R23, R0, 0x7, RZ ; /* 0x0000000700177819 */
/* 0x000fe200000006ff */
/*00c0*/ IMAD R19, R3, c[0x0][0x4], R4 ; /* 0x0000010003137a24 */
/* 0x004fc600078e0204 */
/*00d0*/ LEA R20, R16.reuse, R23, 0x2 ; /* 0x0000001710147211 */
/* 0x048fe200078e10ff */
/*00e0*/ IMAD R21, R16, 0x401, R21 ; /* 0x0000040110157824 */
/* 0x000fe400078e0215 */
/*00f0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD.WIDE.U32 R4, R21, R2, c[0x0][0x160] ; /* 0x0000580015047625 */
/* 0x000fc800078e0002 */
/*0110*/ IMAD.WIDE.U32 R24, R19, R2, c[0x0][0x168] ; /* 0x00005a0013187625 */
/* 0x000fe400078e0002 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007ffe0ff */
/*0150*/ IADD3 R21, R21, c[0x0][0x4], RZ ; /* 0x0000010015157a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.AND P0, PT, R18, 0x20, PT ; /* 0x000000201200780c */
/* 0x000fe20003f05270 */
/*0170*/ STS [R20], R5 ; /* 0x0000000514007388 */
/* 0x004fe80000000800 */
/*0180*/ STS [R20+0x1000], R29 ; /* 0x0010001d14007388 */
/* 0x008fe80000000800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ LDS R6, [R16.X4+0x1000] ; /* 0x0010000010067984 */
/* 0x000fe80000004800 */
/*01b0*/ LDS.128 R8, [R23] ; /* 0x0000000017087984 */
/* 0x000e280000000c00 */
/*01c0*/ LDS R28, [R16.X4+0x1080] ; /* 0x00108000101c7984 */
/* 0x000e680000004800 */
/*01d0*/ LDS R4, [R16.X4+0x1100] ; /* 0x0011000010047984 */
/* 0x000ea80000004800 */
/*01e0*/ LDS R26, [R16.X4+0x1180] ; /* 0x00118000101a7984 */
/* 0x000ee80000004800 */
/*01f0*/ LDS R27, [R16.X4+0x1200] ; /* 0x00120000101b7984 */
/* 0x000fe80000004800 */
/*0200*/ LDS.128 R12, [R23+0x10] ; /* 0x00001000170c7984 */
/* 0x000f280000000c00 */
/*0210*/ LDS R22, [R16.X4+0x1280] ; /* 0x0012800010167984 */
/* 0x000f680000004800 */
/*0220*/ LDS R25, [R16.X4+0x1300] ; /* 0x0013000010197984 */
/* 0x000f680000004800 */
/*0230*/ LDS R24, [R16.X4+0x1380] ; /* 0x0013800010187984 */
/* 0x000f680000004800 */
/*0240*/ LDS R29, [R16.X4+0x1800] ; /* 0x00180000101d7984 */
/* 0x000fe20000004800 */
/*0250*/ IMAD R6, R6, R8, R7 ; /* 0x0000000806067224 */
/* 0x001fc600078e0207 */
/*0260*/ LDS R8, [R16.X4+0x1480] ; /* 0x0014800010087984 */
/* 0x000fe20000004800 */
/*0270*/ IMAD R9, R28, R9, R6 ; /* 0x000000091c097224 */
/* 0x002fc600078e0206 */
/*0280*/ LDS R28, [R16.X4+0x1a80] ; /* 0x001a8000101c7984 */
/* 0x000fe20000004800 */
/*0290*/ IMAD R10, R4, R10, R9 ; /* 0x0000000a040a7224 */
/* 0x004fc600078e0209 */
/*02a0*/ LDS R9, [R16.X4+0x1400] ; /* 0x0014000010097984 */
/* 0x000fe20000004800 */
/*02b0*/ IMAD R10, R26, R11, R10 ; /* 0x0000000b1a0a7224 */
/* 0x008fc600078e020a */
/*02c0*/ LDS.128 R4, [R23+0x20] ; /* 0x0000200017047984 */
/* 0x000e280000000c00 */
/*02d0*/ LDS R11, [R16.X4+0x1500] ; /* 0x00150000100b7984 */
/* 0x000e620000004800 */
/*02e0*/ IMAD R10, R27, R12, R10 ; /* 0x0000000c1b0a7224 */
/* 0x010fc600078e020a */
/*02f0*/ LDS R27, [R16.X4+0x1700] ; /* 0x00170000101b7984 */
/* 0x000fe20000004800 */
/*0300*/ IMAD R10, R22, R13, R10 ; /* 0x0000000d160a7224 */
/* 0x020fc600078e020a */
/*0310*/ LDS R22, [R16.X4+0x1580] ; /* 0x0015800010167984 */
/* 0x000ea20000004800 */
/*0320*/ IMAD R10, R25, R14, R10 ; /* 0x0000000e190a7224 */
/* 0x000fc600078e020a */
/*0330*/ LDS R25, [R16.X4+0x1600] ; /* 0x0016000010197984 */
/* 0x000fe20000004800 */
/*0340*/ IMAD R10, R24, R15, R10 ; /* 0x0000000f180a7224 */
/* 0x000fc600078e020a */
/*0350*/ LDS.128 R12, [R23+0x30] ; /* 0x00003000170c7984 */
/* 0x000ee80000000c00 */
/*0360*/ LDS R24, [R16.X4+0x1680] ; /* 0x0016800010187984 */
/* 0x000f280000004800 */
/*0370*/ LDS R26, [R16.X4+0x1880] ; /* 0x00188000101a7984 */
/* 0x000fe20000004800 */
/*0380*/ IMAD R9, R9, R4, R10 ; /* 0x0000000409097224 */
/* 0x001fc600078e020a */
/*0390*/ LDS R4, [R16.X4+0x1780] ; /* 0x0017800010047984 */
/* 0x000e220000004800 */
/*03a0*/ IMAD R5, R8, R5, R9 ; /* 0x0000000508057224 */
/* 0x000fc800078e0209 */
/*03b0*/ IMAD R5, R11, R6, R5 ; /* 0x000000060b057224 */
/* 0x002fe400078e0205 */
/*03c0*/ LDS.128 R8, [R23+0x40] ; /* 0x0000400017087984 */
/* 0x000e640000000c00 */
/*03d0*/ IMAD R5, R22, R7, R5 ; /* 0x0000000716057224 */
/* 0x004fe400078e0205 */
/*03e0*/ LDS R22, [R16.X4+0x1900] ; /* 0x0019000010167984 */
/* 0x000ea40000004800 */
/*03f0*/ IMAD R5, R25, R12, R5 ; /* 0x0000000c19057224 */
/* 0x008fe400078e0205 */
/*0400*/ LDS R25, [R16.X4+0x1b00] ; /* 0x001b000010197984 */
/* 0x000fe40000004800 */
/*0410*/ IMAD R5, R24, R13, R5 ; /* 0x0000000d18057224 */
/* 0x010fc400078e0205 */
/*0420*/ LDS R24, [R16.X4+0x1980] ; /* 0x0019800010187984 */
/* 0x000ee40000004800 */
/*0430*/ IMAD R5, R27, R14, R5 ; /* 0x0000000e1b057224 */
/* 0x000fe400078e0205 */
/*0440*/ LDS R27, [R16.X4+0x1a00] ; /* 0x001a0000101b7984 */
/* 0x000fe40000004800 */
/*0450*/ IMAD R15, R4, R15, R5 ; /* 0x0000000f040f7224 */
/* 0x001fe400078e0205 */
/*0460*/ LDS.128 R4, [R23+0x50] ; /* 0x0000500017047984 */
/* 0x000e240000000c00 */
/*0470*/ IMAD R15, R29, R8, R15 ; /* 0x000000081d0f7224 */
/* 0x002fc400078e020f */
/*0480*/ LDS R8, [R16.X4+0x1b80] ; /* 0x001b800010087984 */
/* 0x000e640000004800 */
/*0490*/ IMAD R9, R26, R9, R15 ; /* 0x000000091a097224 */
/* 0x000fe400078e020f */
/*04a0*/ LDS.128 R12, [R23+0x60] ; /* 0x00006000170c7984 */
/* 0x000fe40000000c00 */
/*04b0*/ IMAD R10, R22, R10, R9 ; /* 0x0000000a160a7224 */
/* 0x004fe400078e0209 */
/*04c0*/ LDS R9, [R16.X4+0x1c00] ; /* 0x001c000010097984 */
/* 0x000ea80000004800 */
/*04d0*/ LDS R22, [R16.X4+0x1d80] ; /* 0x001d800010167984 */
/* 0x000fe20000004800 */
/*04e0*/ IMAD R10, R24, R11, R10 ; /* 0x0000000b180a7224 */
/* 0x008fc600078e020a */
/*04f0*/ LDS R11, [R16.X4+0x1d00] ; /* 0x001d0000100b7984 */
/* 0x000fe20000004800 */
/*0500*/ IMAD R4, R27, R4, R10 ; /* 0x000000041b047224 */
/* 0x001fc600078e020a */
/*0510*/ LDS R10, [R16.X4+0x1c80] ; /* 0x001c8000100a7984 */
/* 0x000e220000004800 */
/*0520*/ IMAD R4, R28, R5, R4 ; /* 0x000000051c047224 */
/* 0x000fc600078e0204 */
/*0530*/ LDS R27, [R16.X4+0x1e00] ; /* 0x001e0000101b7984 */
/* 0x000fe20000004800 */
/*0540*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc600078e0204 */
/*0550*/ LDS R25, [R16.X4+0x1f00] ; /* 0x001f000010197984 */
/* 0x000fe20000004800 */
/*0560*/ IMAD R24, R8, R7, R4 ; /* 0x0000000708187224 */
/* 0x002fc600078e0204 */
/*0570*/ LDS.128 R4, [R23+0x70] ; /* 0x0000700017047984 */
/* 0x000e620000000c00 */
/*0580*/ IMAD R9, R9, R12, R24 ; /* 0x0000000c09097224 */
/* 0x004fc600078e0218 */
/*0590*/ LDS R8, [R16.X4+0x1e80] ; /* 0x001e800010087984 */
/* 0x000ea80000004800 */
/*05a0*/ LDS R12, [R16.X4+0x1f80] ; /* 0x001f8000100c7984 */
/* 0x000ee20000004800 */
/*05b0*/ IMAD R9, R10, R13, R9 ; /* 0x0000000d0a097224 */
/* 0x001fc800078e0209 */
/*05c0*/ IMAD R9, R11, R14, R9 ; /* 0x0000000e0b097224 */
/* 0x000fc800078e0209 */
/*05d0*/ IMAD R9, R22, R15, R9 ; /* 0x0000000f16097224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R4, R27, R4, R9 ; /* 0x000000041b047224 */
/* 0x002fc800078e0209 */
/*05f0*/ IMAD R4, R8, R5, R4 ; /* 0x0000000508047224 */
/* 0x004fe200078e0204 */
/*0600*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fc60000000f00 */
/*0610*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fe200078e0204 */
/*0620*/ LEA R19, R8, R19, 0xa ; /* 0x0000001308137211 */
/* 0x000fc600078e50ff */
/*0630*/ IMAD R7, R12, R7, R4 ; /* 0x000000070c077224 */
/* 0x008fe200078e0204 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ @P0 BRA 0xf0 ; /* 0xfffffa9000000947 */
/* 0x000fea000383ffff */
/*0660*/ IMAD R16, R17, c[0x0][0x0], R16 ; /* 0x0000000011107a24 */
/* 0x000fe400078e0210 */
/*0670*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x000fca00078e0200 */
/*0680*/ LEA R3, R16, R3, 0xa ; /* 0x0000000310037211 */
/* 0x000fca00078e50ff */
/*0690*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*06a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
#define n 1024
#define block_size 32
/*
__global__ void mult_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y, blockCol = blockIdx.x;
int row = threadIdx.y, col = threadIdx.x;
for (int m = 0; m < (n/block_size); ++m) {
}
}
*/
__global__ void mul_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
int i,j;
int myx = blockIdx.x * blockDim.x + threadIdx.x;
int myy = blockIdx.y * blockDim.y + threadIdx.y;
int local=0;
__shared__ int As[32][32];
__shared__ int Bs[32][32];
for(i=0;i<n/block_size;i++) {
As[row][col] = a[myx*n + (i*blockDim.y + col)];
Bs[row][col] = b[(i*blockDim.x+row)*n + myy];
__syncthreads();
for(j=0;j<block_size;j++)
local += As[row][j]*Bs[j][col];
__syncthreads();
}
c[myx*n+myy] = local;
}
int main() {
int i;
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
cudaEvent_t start, stop;
float time;
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for(i=0;i<n*n;i++) {
a[i] = 1;
b[i] = 2;
c[i] = 0;
}
int *gpua, *gpub, *gpuc;
cudaMalloc((void**)&gpua, sizeof(int)*n*n);
cudaMalloc((void**)&gpub, sizeof(int)*n*n);
cudaMalloc((void**)&gpuc, sizeof(int)*n*n);
cudaMemcpy(gpua, a, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpub, b, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
mul_mat<<<dimGrid, dimBlock>>> (gpua, gpub, gpuc);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaMemcpy(c, gpuc, sizeof(int)*n*n, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&time, start, stop);
printf("C[451][451] = %d\n",c[451*1024 + 451]);
printf("Time - %f\n", time);
free(a);
free(b);
free(c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(gpua);
cudaFree(gpub);
cudaFree(gpuc);
return 0;
} | .file "tmpxft_0016e965_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7mul_matPiS_S_PiS_S_
.type _Z30__device_stub__Z7mul_matPiS_S_PiS_S_, @function
_Z30__device_stub__Z7mul_matPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mul_matPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7mul_matPiS_S_PiS_S_, .-_Z30__device_stub__Z7mul_matPiS_S_PiS_S_
.globl _Z7mul_matPiS_S_
.type _Z7mul_matPiS_S_, @function
_Z7mul_matPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mul_matPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7mul_matPiS_S_, .-_Z7mul_matPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "C[451][451] = %d\n"
.LC1:
.string "Time - %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %eax
.L12:
movl $1, (%r12,%rax)
movl $2, 0(%rbp,%rax)
movl $0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 1849100(%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z7mul_matPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7mul_matPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mul_matPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
#define n 1024
#define block_size 32
/*
__global__ void mult_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y, blockCol = blockIdx.x;
int row = threadIdx.y, col = threadIdx.x;
for (int m = 0; m < (n/block_size); ++m) {
}
}
*/
__global__ void mul_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
int i,j;
int myx = blockIdx.x * blockDim.x + threadIdx.x;
int myy = blockIdx.y * blockDim.y + threadIdx.y;
int local=0;
__shared__ int As[32][32];
__shared__ int Bs[32][32];
for(i=0;i<n/block_size;i++) {
As[row][col] = a[myx*n + (i*blockDim.y + col)];
Bs[row][col] = b[(i*blockDim.x+row)*n + myy];
__syncthreads();
for(j=0;j<block_size;j++)
local += As[row][j]*Bs[j][col];
__syncthreads();
}
c[myx*n+myy] = local;
}
int main() {
int i;
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
cudaEvent_t start, stop;
float time;
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for(i=0;i<n*n;i++) {
a[i] = 1;
b[i] = 2;
c[i] = 0;
}
int *gpua, *gpub, *gpuc;
cudaMalloc((void**)&gpua, sizeof(int)*n*n);
cudaMalloc((void**)&gpub, sizeof(int)*n*n);
cudaMalloc((void**)&gpuc, sizeof(int)*n*n);
cudaMemcpy(gpua, a, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaMemcpy(gpub, b, sizeof(int)*n*n, cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
mul_mat<<<dimGrid, dimBlock>>> (gpua, gpub, gpuc);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaMemcpy(c, gpuc, sizeof(int)*n*n, cudaMemcpyDeviceToHost);
cudaEventElapsedTime(&time, start, stop);
printf("C[451][451] = %d\n",c[451*1024 + 451]);
printf("Time - %f\n", time);
free(a);
free(b);
free(c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(gpua);
cudaFree(gpub);
cudaFree(gpuc);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
#define n 1024
#define block_size 32
/*
__global__ void mult_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y, blockCol = blockIdx.x;
int row = threadIdx.y, col = threadIdx.x;
for (int m = 0; m < (n/block_size); ++m) {
}
}
*/
__global__ void mul_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
int i,j;
int myx = blockIdx.x * blockDim.x + threadIdx.x;
int myy = blockIdx.y * blockDim.y + threadIdx.y;
int local=0;
__shared__ int As[32][32];
__shared__ int Bs[32][32];
for(i=0;i<n/block_size;i++) {
As[row][col] = a[myx*n + (i*blockDim.y + col)];
Bs[row][col] = b[(i*blockDim.x+row)*n + myy];
__syncthreads();
for(j=0;j<block_size;j++)
local += As[row][j]*Bs[j][col];
__syncthreads();
}
c[myx*n+myy] = local;
}
int main() {
int i;
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
hipEvent_t start, stop;
float time;
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for(i=0;i<n*n;i++) {
a[i] = 1;
b[i] = 2;
c[i] = 0;
}
int *gpua, *gpub, *gpuc;
hipMalloc((void**)&gpua, sizeof(int)*n*n);
hipMalloc((void**)&gpub, sizeof(int)*n*n);
hipMalloc((void**)&gpuc, sizeof(int)*n*n);
hipMemcpy(gpua, a, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipMemcpy(gpub, b, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
mul_mat<<<dimGrid, dimBlock>>> (gpua, gpub, gpuc);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipMemcpy(c, gpuc, sizeof(int)*n*n, hipMemcpyDeviceToHost);
hipEventElapsedTime(&time, start, stop);
printf("C[451][451] = %d\n",c[451*1024 + 451]);
printf("Time - %f\n", time);
free(a);
free(b);
free(c);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(gpua);
hipFree(gpub);
hipFree(gpuc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
#define n 1024
#define block_size 32
/*
__global__ void mult_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y, blockCol = blockIdx.x;
int row = threadIdx.y, col = threadIdx.x;
for (int m = 0; m < (n/block_size); ++m) {
}
}
*/
__global__ void mul_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
int i,j;
int myx = blockIdx.x * blockDim.x + threadIdx.x;
int myy = blockIdx.y * blockDim.y + threadIdx.y;
int local=0;
__shared__ int As[32][32];
__shared__ int Bs[32][32];
for(i=0;i<n/block_size;i++) {
As[row][col] = a[myx*n + (i*blockDim.y + col)];
Bs[row][col] = b[(i*blockDim.x+row)*n + myy];
__syncthreads();
for(j=0;j<block_size;j++)
local += As[row][j]*Bs[j][col];
__syncthreads();
}
c[myx*n+myy] = local;
}
int main() {
int i;
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
hipEvent_t start, stop;
float time;
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for(i=0;i<n*n;i++) {
a[i] = 1;
b[i] = 2;
c[i] = 0;
}
int *gpua, *gpub, *gpuc;
hipMalloc((void**)&gpua, sizeof(int)*n*n);
hipMalloc((void**)&gpub, sizeof(int)*n*n);
hipMalloc((void**)&gpuc, sizeof(int)*n*n);
hipMemcpy(gpua, a, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipMemcpy(gpub, b, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
mul_mat<<<dimGrid, dimBlock>>> (gpua, gpub, gpuc);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipMemcpy(c, gpuc, sizeof(int)*n*n, hipMemcpyDeviceToHost);
hipEventElapsedTime(&time, start, stop);
printf("C[451][451] = %d\n",c[451*1024 + 451]);
printf("Time - %f\n", time);
free(a);
free(b);
free(c);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(gpua);
hipFree(gpub);
hipFree(gpuc);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mul_matPiS_S_
.globl _Z7mul_matPiS_S_
.p2align 8
.type _Z7mul_matPiS_S_,@function
_Z7mul_matPiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v7, 7, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_or_b32_e32 v8, 0x1000, v5
v_add_nc_u32_e32 v9, v7, v5
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
v_lshl_or_b32 v6, v1, 10, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v10, v8, v7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_mad_u64_u32 v[11:12], null, s8, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[12:13], null, s8, s3, v[6:7]
v_mov_b32_e32 v13, v4
s_mov_b32 s9, 0
v_lshl_add_u32 v3, v11, 10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[12:13]
v_lshlrev_b64 v[13:14], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v3, v[11:12], off
global_load_b32 v12, v[13:14], off
v_mov_b32_e32 v11, v8
s_waitcnt vmcnt(1)
ds_store_b32 v9, v3
s_waitcnt vmcnt(0)
ds_store_b32 v10, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v3, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v13, v11
ds_load_b32 v14, v3
v_add_nc_u32_e32 v11, 0x80, v11
s_cmpk_lg_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v13, v14, v[12:13]
s_cbranch_scc1 .LBB0_2
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 32
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mul_matPiS_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mul_matPiS_S_, .Lfunc_end0-_Z7mul_matPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mul_matPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mul_matPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
#define n 1024
#define block_size 32
/*
__global__ void mult_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y, blockCol = blockIdx.x;
int row = threadIdx.y, col = threadIdx.x;
for (int m = 0; m < (n/block_size); ++m) {
}
}
*/
__global__ void mul_mat(int *a, int *b, int *c) {
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;
int row = threadIdx.y;
int col = threadIdx.x;
int i,j;
int myx = blockIdx.x * blockDim.x + threadIdx.x;
int myy = blockIdx.y * blockDim.y + threadIdx.y;
int local=0;
__shared__ int As[32][32];
__shared__ int Bs[32][32];
for(i=0;i<n/block_size;i++) {
As[row][col] = a[myx*n + (i*blockDim.y + col)];
Bs[row][col] = b[(i*blockDim.x+row)*n + myy];
__syncthreads();
for(j=0;j<block_size;j++)
local += As[row][j]*Bs[j][col];
__syncthreads();
}
c[myx*n+myy] = local;
}
int main() {
int i;
int *a = (int*)malloc(sizeof(int)*n*n);
int *b = (int*)malloc(sizeof(int)*n*n);
int *c = (int*)malloc(sizeof(int)*n*n);
hipEvent_t start, stop;
float time;
dim3 dimGrid(32,32);
dim3 dimBlock(32,32);
for(i=0;i<n*n;i++) {
a[i] = 1;
b[i] = 2;
c[i] = 0;
}
int *gpua, *gpub, *gpuc;
hipMalloc((void**)&gpua, sizeof(int)*n*n);
hipMalloc((void**)&gpub, sizeof(int)*n*n);
hipMalloc((void**)&gpuc, sizeof(int)*n*n);
hipMemcpy(gpua, a, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipMemcpy(gpub, b, sizeof(int)*n*n, hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
mul_mat<<<dimGrid, dimBlock>>> (gpua, gpub, gpuc);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipMemcpy(c, gpuc, sizeof(int)*n*n, hipMemcpyDeviceToHost);
hipEventElapsedTime(&time, start, stop);
printf("C[451][451] = %d\n",c[451*1024 + 451]);
printf("Time - %f\n", time);
free(a);
free(b);
free(c);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(gpua);
hipFree(gpub);
hipFree(gpuc);
return 0;
} | .text
.file "p2.hip"
.globl _Z22__device_stub__mul_matPiS_S_ # -- Begin function _Z22__device_stub__mul_matPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mul_matPiS_S_,@function
_Z22__device_stub__mul_matPiS_S_: # @_Z22__device_stub__mul_matPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mul_matPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__mul_matPiS_S_, .Lfunc_end0-_Z22__device_stub__mul_matPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r12,4)
movl $2, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7mul_matPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl 1849100(%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mul_matPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mul_matPiS_S_,@object # @_Z7mul_matPiS_S_
.section .rodata,"a",@progbits
.globl _Z7mul_matPiS_S_
.p2align 3, 0x0
_Z7mul_matPiS_S_:
.quad _Z22__device_stub__mul_matPiS_S_
.size _Z7mul_matPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "C[451][451] = %d\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time - %f\n"
.size .L.str.1, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mul_matPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mul_matPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mul_matPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mul_matPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R16, SR_TID.X ; /* 0x0000000000107919 */
/* 0x000ee20000002100 */
/*0080*/ IMAD R2, R17, c[0x0][0x0], RZ ; /* 0x0000000011027a24 */
/* 0x001fe200078e02ff */
/*0090*/ LEA R4, R0, R0, 0xa ; /* 0x0000000000047211 */
/* 0x002fc800078e50ff */
/*00a0*/ SHF.L.U32 R21, R2, 0xa, RZ ; /* 0x0000000a02157819 */
/* 0x000fe400000006ff */
/*00b0*/ SHF.L.U32 R23, R0, 0x7, RZ ; /* 0x0000000700177819 */
/* 0x000fe200000006ff */
/*00c0*/ IMAD R19, R3, c[0x0][0x4], R4 ; /* 0x0000010003137a24 */
/* 0x004fc600078e0204 */
/*00d0*/ LEA R20, R16.reuse, R23, 0x2 ; /* 0x0000001710147211 */
/* 0x048fe200078e10ff */
/*00e0*/ IMAD R21, R16, 0x401, R21 ; /* 0x0000040110157824 */
/* 0x000fe400078e0215 */
/*00f0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD.WIDE.U32 R4, R21, R2, c[0x0][0x160] ; /* 0x0000580015047625 */
/* 0x000fc800078e0002 */
/*0110*/ IMAD.WIDE.U32 R24, R19, R2, c[0x0][0x168] ; /* 0x00005a0013187625 */
/* 0x000fe400078e0002 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007ffe0ff */
/*0150*/ IADD3 R21, R21, c[0x0][0x4], RZ ; /* 0x0000010015157a10 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.NE.AND P0, PT, R18, 0x20, PT ; /* 0x000000201200780c */
/* 0x000fe20003f05270 */
/*0170*/ STS [R20], R5 ; /* 0x0000000514007388 */
/* 0x004fe80000000800 */
/*0180*/ STS [R20+0x1000], R29 ; /* 0x0010001d14007388 */
/* 0x008fe80000000800 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01a0*/ LDS R6, [R16.X4+0x1000] ; /* 0x0010000010067984 */
/* 0x000fe80000004800 */
/*01b0*/ LDS.128 R8, [R23] ; /* 0x0000000017087984 */
/* 0x000e280000000c00 */
/*01c0*/ LDS R28, [R16.X4+0x1080] ; /* 0x00108000101c7984 */
/* 0x000e680000004800 */
/*01d0*/ LDS R4, [R16.X4+0x1100] ; /* 0x0011000010047984 */
/* 0x000ea80000004800 */
/*01e0*/ LDS R26, [R16.X4+0x1180] ; /* 0x00118000101a7984 */
/* 0x000ee80000004800 */
/*01f0*/ LDS R27, [R16.X4+0x1200] ; /* 0x00120000101b7984 */
/* 0x000fe80000004800 */
/*0200*/ LDS.128 R12, [R23+0x10] ; /* 0x00001000170c7984 */
/* 0x000f280000000c00 */
/*0210*/ LDS R22, [R16.X4+0x1280] ; /* 0x0012800010167984 */
/* 0x000f680000004800 */
/*0220*/ LDS R25, [R16.X4+0x1300] ; /* 0x0013000010197984 */
/* 0x000f680000004800 */
/*0230*/ LDS R24, [R16.X4+0x1380] ; /* 0x0013800010187984 */
/* 0x000f680000004800 */
/*0240*/ LDS R29, [R16.X4+0x1800] ; /* 0x00180000101d7984 */
/* 0x000fe20000004800 */
/*0250*/ IMAD R6, R6, R8, R7 ; /* 0x0000000806067224 */
/* 0x001fc600078e0207 */
/*0260*/ LDS R8, [R16.X4+0x1480] ; /* 0x0014800010087984 */
/* 0x000fe20000004800 */
/*0270*/ IMAD R9, R28, R9, R6 ; /* 0x000000091c097224 */
/* 0x002fc600078e0206 */
/*0280*/ LDS R28, [R16.X4+0x1a80] ; /* 0x001a8000101c7984 */
/* 0x000fe20000004800 */
/*0290*/ IMAD R10, R4, R10, R9 ; /* 0x0000000a040a7224 */
/* 0x004fc600078e0209 */
/*02a0*/ LDS R9, [R16.X4+0x1400] ; /* 0x0014000010097984 */
/* 0x000fe20000004800 */
/*02b0*/ IMAD R10, R26, R11, R10 ; /* 0x0000000b1a0a7224 */
/* 0x008fc600078e020a */
/*02c0*/ LDS.128 R4, [R23+0x20] ; /* 0x0000200017047984 */
/* 0x000e280000000c00 */
/*02d0*/ LDS R11, [R16.X4+0x1500] ; /* 0x00150000100b7984 */
/* 0x000e620000004800 */
/*02e0*/ IMAD R10, R27, R12, R10 ; /* 0x0000000c1b0a7224 */
/* 0x010fc600078e020a */
/*02f0*/ LDS R27, [R16.X4+0x1700] ; /* 0x00170000101b7984 */
/* 0x000fe20000004800 */
/*0300*/ IMAD R10, R22, R13, R10 ; /* 0x0000000d160a7224 */
/* 0x020fc600078e020a */
/*0310*/ LDS R22, [R16.X4+0x1580] ; /* 0x0015800010167984 */
/* 0x000ea20000004800 */
/*0320*/ IMAD R10, R25, R14, R10 ; /* 0x0000000e190a7224 */
/* 0x000fc600078e020a */
/*0330*/ LDS R25, [R16.X4+0x1600] ; /* 0x0016000010197984 */
/* 0x000fe20000004800 */
/*0340*/ IMAD R10, R24, R15, R10 ; /* 0x0000000f180a7224 */
/* 0x000fc600078e020a */
/*0350*/ LDS.128 R12, [R23+0x30] ; /* 0x00003000170c7984 */
/* 0x000ee80000000c00 */
/*0360*/ LDS R24, [R16.X4+0x1680] ; /* 0x0016800010187984 */
/* 0x000f280000004800 */
/*0370*/ LDS R26, [R16.X4+0x1880] ; /* 0x00188000101a7984 */
/* 0x000fe20000004800 */
/*0380*/ IMAD R9, R9, R4, R10 ; /* 0x0000000409097224 */
/* 0x001fc600078e020a */
/*0390*/ LDS R4, [R16.X4+0x1780] ; /* 0x0017800010047984 */
/* 0x000e220000004800 */
/*03a0*/ IMAD R5, R8, R5, R9 ; /* 0x0000000508057224 */
/* 0x000fc800078e0209 */
/*03b0*/ IMAD R5, R11, R6, R5 ; /* 0x000000060b057224 */
/* 0x002fe400078e0205 */
/*03c0*/ LDS.128 R8, [R23+0x40] ; /* 0x0000400017087984 */
/* 0x000e640000000c00 */
/*03d0*/ IMAD R5, R22, R7, R5 ; /* 0x0000000716057224 */
/* 0x004fe400078e0205 */
/*03e0*/ LDS R22, [R16.X4+0x1900] ; /* 0x0019000010167984 */
/* 0x000ea40000004800 */
/*03f0*/ IMAD R5, R25, R12, R5 ; /* 0x0000000c19057224 */
/* 0x008fe400078e0205 */
/*0400*/ LDS R25, [R16.X4+0x1b00] ; /* 0x001b000010197984 */
/* 0x000fe40000004800 */
/*0410*/ IMAD R5, R24, R13, R5 ; /* 0x0000000d18057224 */
/* 0x010fc400078e0205 */
/*0420*/ LDS R24, [R16.X4+0x1980] ; /* 0x0019800010187984 */
/* 0x000ee40000004800 */
/*0430*/ IMAD R5, R27, R14, R5 ; /* 0x0000000e1b057224 */
/* 0x000fe400078e0205 */
/*0440*/ LDS R27, [R16.X4+0x1a00] ; /* 0x001a0000101b7984 */
/* 0x000fe40000004800 */
/*0450*/ IMAD R15, R4, R15, R5 ; /* 0x0000000f040f7224 */
/* 0x001fe400078e0205 */
/*0460*/ LDS.128 R4, [R23+0x50] ; /* 0x0000500017047984 */
/* 0x000e240000000c00 */
/*0470*/ IMAD R15, R29, R8, R15 ; /* 0x000000081d0f7224 */
/* 0x002fc400078e020f */
/*0480*/ LDS R8, [R16.X4+0x1b80] ; /* 0x001b800010087984 */
/* 0x000e640000004800 */
/*0490*/ IMAD R9, R26, R9, R15 ; /* 0x000000091a097224 */
/* 0x000fe400078e020f */
/*04a0*/ LDS.128 R12, [R23+0x60] ; /* 0x00006000170c7984 */
/* 0x000fe40000000c00 */
/*04b0*/ IMAD R10, R22, R10, R9 ; /* 0x0000000a160a7224 */
/* 0x004fe400078e0209 */
/*04c0*/ LDS R9, [R16.X4+0x1c00] ; /* 0x001c000010097984 */
/* 0x000ea80000004800 */
/*04d0*/ LDS R22, [R16.X4+0x1d80] ; /* 0x001d800010167984 */
/* 0x000fe20000004800 */
/*04e0*/ IMAD R10, R24, R11, R10 ; /* 0x0000000b180a7224 */
/* 0x008fc600078e020a */
/*04f0*/ LDS R11, [R16.X4+0x1d00] ; /* 0x001d0000100b7984 */
/* 0x000fe20000004800 */
/*0500*/ IMAD R4, R27, R4, R10 ; /* 0x000000041b047224 */
/* 0x001fc600078e020a */
/*0510*/ LDS R10, [R16.X4+0x1c80] ; /* 0x001c8000100a7984 */
/* 0x000e220000004800 */
/*0520*/ IMAD R4, R28, R5, R4 ; /* 0x000000051c047224 */
/* 0x000fc600078e0204 */
/*0530*/ LDS R27, [R16.X4+0x1e00] ; /* 0x001e0000101b7984 */
/* 0x000fe20000004800 */
/*0540*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fc600078e0204 */
/*0550*/ LDS R25, [R16.X4+0x1f00] ; /* 0x001f000010197984 */
/* 0x000fe20000004800 */
/*0560*/ IMAD R24, R8, R7, R4 ; /* 0x0000000708187224 */
/* 0x002fc600078e0204 */
/*0570*/ LDS.128 R4, [R23+0x70] ; /* 0x0000700017047984 */
/* 0x000e620000000c00 */
/*0580*/ IMAD R9, R9, R12, R24 ; /* 0x0000000c09097224 */
/* 0x004fc600078e0218 */
/*0590*/ LDS R8, [R16.X4+0x1e80] ; /* 0x001e800010087984 */
/* 0x000ea80000004800 */
/*05a0*/ LDS R12, [R16.X4+0x1f80] ; /* 0x001f8000100c7984 */
/* 0x000ee20000004800 */
/*05b0*/ IMAD R9, R10, R13, R9 ; /* 0x0000000d0a097224 */
/* 0x001fc800078e0209 */
/*05c0*/ IMAD R9, R11, R14, R9 ; /* 0x0000000e0b097224 */
/* 0x000fc800078e0209 */
/*05d0*/ IMAD R9, R22, R15, R9 ; /* 0x0000000f16097224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R4, R27, R4, R9 ; /* 0x000000041b047224 */
/* 0x002fc800078e0209 */
/*05f0*/ IMAD R4, R8, R5, R4 ; /* 0x0000000508047224 */
/* 0x004fe200078e0204 */
/*0600*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fc60000000f00 */
/*0610*/ IMAD R4, R25, R6, R4 ; /* 0x0000000619047224 */
/* 0x000fe200078e0204 */
/*0620*/ LEA R19, R8, R19, 0xa ; /* 0x0000001308137211 */
/* 0x000fc600078e50ff */
/*0630*/ IMAD R7, R12, R7, R4 ; /* 0x000000070c077224 */
/* 0x008fe200078e0204 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ @P0 BRA 0xf0 ; /* 0xfffffa9000000947 */
/* 0x000fea000383ffff */
/*0660*/ IMAD R16, R17, c[0x0][0x0], R16 ; /* 0x0000000011107a24 */
/* 0x000fe400078e0210 */
/*0670*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x000fca00078e0200 */
/*0680*/ LEA R3, R16, R3, 0xa ; /* 0x0000000310037211 */
/* 0x000fca00078e50ff */
/*0690*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*06a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*06b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mul_matPiS_S_
.globl _Z7mul_matPiS_S_
.p2align 8
.type _Z7mul_matPiS_S_,@function
_Z7mul_matPiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v7, 7, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v5, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, v4
v_or_b32_e32 v8, 0x1000, v5
v_add_nc_u32_e32 v9, v7, v5
v_mad_u64_u32 v[5:6], null, s15, s3, v[0:1]
v_lshl_or_b32 v6, v1, 10, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v10, v8, v7
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_mad_u64_u32 v[11:12], null, s8, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[12:13], null, s8, s3, v[6:7]
v_mov_b32_e32 v13, v4
s_mov_b32 s9, 0
v_lshl_add_u32 v3, v11, 10, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[12:13]
v_lshlrev_b64 v[13:14], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v3, v[11:12], off
global_load_b32 v12, v[13:14], off
v_mov_b32_e32 v11, v8
s_waitcnt vmcnt(1)
ds_store_b32 v9, v3
s_waitcnt vmcnt(0)
ds_store_b32 v10, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v3, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v13, v11
ds_load_b32 v14, v3
v_add_nc_u32_e32 v11, 0x80, v11
s_cmpk_lg_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v13, v14, v[12:13]
s_cbranch_scc1 .LBB0_2
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 32
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mul_matPiS_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mul_matPiS_S_, .Lfunc_end0-_Z7mul_matPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mul_matPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7mul_matPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016e965_00000000-6_p2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7mul_matPiS_S_PiS_S_
.type _Z30__device_stub__Z7mul_matPiS_S_PiS_S_, @function
_Z30__device_stub__Z7mul_matPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mul_matPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z7mul_matPiS_S_PiS_S_, .-_Z30__device_stub__Z7mul_matPiS_S_PiS_S_
.globl _Z7mul_matPiS_S_
.type _Z7mul_matPiS_S_, @function
_Z7mul_matPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7mul_matPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7mul_matPiS_S_, .-_Z7mul_matPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "C[451][451] = %d\n"
.LC1:
.string "Time - %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %eax
.L12:
movl $1, (%r12,%rax)
movl $2, 0(%rbp,%rax)
movl $0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 1849100(%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z7mul_matPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7mul_matPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mul_matPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "p2.hip"
.globl _Z22__device_stub__mul_matPiS_S_ # -- Begin function _Z22__device_stub__mul_matPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__mul_matPiS_S_,@function
_Z22__device_stub__mul_matPiS_S_: # @_Z22__device_stub__mul_matPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7mul_matPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__mul_matPiS_S_, .Lfunc_end0-_Z22__device_stub__mul_matPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4194304, %edx # imm = 0x400000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r12,4)
movl $2, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 32(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
leaq 144(%rsp), %rax
movq %rax, 48(%rsp)
leaq 136(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7mul_matPiS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl 1849100(%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7mul_matPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7mul_matPiS_S_,@object # @_Z7mul_matPiS_S_
.section .rodata,"a",@progbits
.globl _Z7mul_matPiS_S_
.p2align 3, 0x0
_Z7mul_matPiS_S_:
.quad _Z22__device_stub__mul_matPiS_S_
.size _Z7mul_matPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "C[451][451] = %d\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time - %f\n"
.size .L.str.1, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7mul_matPiS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__mul_matPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7mul_matPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define tam 1.0
#define dx 0.00001
#define dt 0.000001
#define T 0.01
#define kappa 0.000045
__global__ void Inicializacao( double *uprev, const int n ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
double x = idx * dx;
if( idx < n + 1 ) {
if( x <= 0.5 ) {
uprev[ idx ] = 200 * x;
}
else {
uprev[ idx ] = 200 * ( 1. - x );
}
}
} | code for sm_80
Function : _Z13InicializacaoPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e220000201c00 */
/*0070*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00a0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x001e0c0000000000 */
/*00b0*/ DSETP.GTU.AND P0, PT, R2, 0.5, PT ; /* 0x3fe000000200742a */
/* 0x001e1c0003f0c000 */
/*00c0*/ @!P0 DMUL R6, R2, 200 ; /* 0x4069000002068828 */
/* 0x001e0e0000000000 */
/*00d0*/ @!P0 STG.E.64 [R4.64], R6 ; /* 0x0000000604008986 */
/* 0x0011e2000c101b04 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ DADD R2, -R2, 1 ; /* 0x3ff0000002027429 */
/* 0x000e4c0000000100 */
/*0100*/ DMUL R2, R2, 200 ; /* 0x4069000002027828 */
/* 0x002e4e0000000000 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define tam 1.0
#define dx 0.00001
#define dt 0.000001
#define T 0.01
#define kappa 0.000045
__global__ void Inicializacao( double *uprev, const int n ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
double x = idx * dx;
if( idx < n + 1 ) {
if( x <= 0.5 ) {
uprev[ idx ] = 200 * x;
}
else {
uprev[ idx ] = 200 * ( 1. - x );
}
}
} | .file "tmpxft_0012e3d0_00000000-6_Inicializacao.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13InicializacaoPdiPdi
.type _Z34__device_stub__Z13InicializacaoPdiPdi, @function
_Z34__device_stub__Z13InicializacaoPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13InicializacaoPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z13InicializacaoPdiPdi, .-_Z34__device_stub__Z13InicializacaoPdiPdi
.globl _Z13InicializacaoPdi
.type _Z13InicializacaoPdi, @function
_Z13InicializacaoPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13InicializacaoPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13InicializacaoPdi, .-_Z13InicializacaoPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13InicializacaoPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13InicializacaoPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define tam 1.0
#define dx 0.00001
#define dt 0.000001
#define T 0.01
#define kappa 0.000045
__global__ void Inicializacao( double *uprev, const int n ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
double x = idx * dx;
if( idx < n + 1 ) {
if( x <= 0.5 ) {
uprev[ idx ] = 200 * x;
}
else {
uprev[ idx ] = 200 * ( 1. - x );
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define tam 1.0
#define dx 0.00001
#define dt 0.000001
#define T 0.01
#define kappa 0.000045
__global__ void Inicializacao( double *uprev, const int n ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
double x = idx * dx;
if( idx < n + 1 ) {
if( x <= 0.5 ) {
uprev[ idx ] = 200 * x;
}
else {
uprev[ idx ] = 200 * ( 1. - x );
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define tam 1.0
#define dx 0.00001
#define dt 0.000001
#define T 0.01
#define kappa 0.000045
__global__ void Inicializacao( double *uprev, const int n ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
double x = idx * dx;
if( idx < n + 1 ) {
if( x <= 0.5 ) {
uprev[ idx ] = 200 * x;
}
else {
uprev[ idx ] = 200 * ( 1. - x );
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13InicializacaoPdi
.globl _Z13InicializacaoPdi
.p2align 8
.type _Z13InicializacaoPdi,@function
_Z13InicializacaoPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[2:3], v1
s_mov_b32 s3, 0x3ee4f8b5
s_mov_b32 s2, 0x88e368f1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[4:5], v[2:3], s[2:3]
s_mov_b32 s3, 0xbee4f8b5
v_fma_f64 v[2:3], v[2:3], s[2:3], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_nge_f64_e32 vcc_lo, 0.5, v[4:5]
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[2:3], 0x40690000
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13InicializacaoPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13InicializacaoPdi, .Lfunc_end0-_Z13InicializacaoPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13InicializacaoPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13InicializacaoPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define tam 1.0
#define dx 0.00001
#define dt 0.000001
#define T 0.01
#define kappa 0.000045
__global__ void Inicializacao( double *uprev, const int n ) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
double x = idx * dx;
if( idx < n + 1 ) {
if( x <= 0.5 ) {
uprev[ idx ] = 200 * x;
}
else {
uprev[ idx ] = 200 * ( 1. - x );
}
}
} | .text
.file "Inicializacao.hip"
.globl _Z28__device_stub__InicializacaoPdi # -- Begin function _Z28__device_stub__InicializacaoPdi
.p2align 4, 0x90
.type _Z28__device_stub__InicializacaoPdi,@function
_Z28__device_stub__InicializacaoPdi: # @_Z28__device_stub__InicializacaoPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13InicializacaoPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__InicializacaoPdi, .Lfunc_end0-_Z28__device_stub__InicializacaoPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13InicializacaoPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13InicializacaoPdi,@object # @_Z13InicializacaoPdi
.section .rodata,"a",@progbits
.globl _Z13InicializacaoPdi
.p2align 3, 0x0
_Z13InicializacaoPdi:
.quad _Z28__device_stub__InicializacaoPdi
.size _Z13InicializacaoPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13InicializacaoPdi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__InicializacaoPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13InicializacaoPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13InicializacaoPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e220000201c00 */
/*0070*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fe200078e0205 */
/*00a0*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x001e0c0000000000 */
/*00b0*/ DSETP.GTU.AND P0, PT, R2, 0.5, PT ; /* 0x3fe000000200742a */
/* 0x001e1c0003f0c000 */
/*00c0*/ @!P0 DMUL R6, R2, 200 ; /* 0x4069000002068828 */
/* 0x001e0e0000000000 */
/*00d0*/ @!P0 STG.E.64 [R4.64], R6 ; /* 0x0000000604008986 */
/* 0x0011e2000c101b04 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ DADD R2, -R2, 1 ; /* 0x3ff0000002027429 */
/* 0x000e4c0000000100 */
/*0100*/ DMUL R2, R2, 200 ; /* 0x4069000002027828 */
/* 0x002e4e0000000000 */
/*0110*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13InicializacaoPdi
.globl _Z13InicializacaoPdi
.p2align 8
.type _Z13InicializacaoPdi,@function
_Z13InicializacaoPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[2:3], v1
s_mov_b32 s3, 0x3ee4f8b5
s_mov_b32 s2, 0x88e368f1
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_f64 v[4:5], v[2:3], s[2:3]
s_mov_b32 s3, 0xbee4f8b5
v_fma_f64 v[2:3], v[2:3], s[2:3], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_nge_f64_e32 vcc_lo, 0.5, v[4:5]
v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[2:3], 0x40690000
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13InicializacaoPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13InicializacaoPdi, .Lfunc_end0-_Z13InicializacaoPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13InicializacaoPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13InicializacaoPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012e3d0_00000000-6_Inicializacao.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z13InicializacaoPdiPdi
.type _Z34__device_stub__Z13InicializacaoPdiPdi, @function
_Z34__device_stub__Z13InicializacaoPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13InicializacaoPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z13InicializacaoPdiPdi, .-_Z34__device_stub__Z13InicializacaoPdiPdi
.globl _Z13InicializacaoPdi
.type _Z13InicializacaoPdi, @function
_Z13InicializacaoPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13InicializacaoPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13InicializacaoPdi, .-_Z13InicializacaoPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13InicializacaoPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13InicializacaoPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Inicializacao.hip"
.globl _Z28__device_stub__InicializacaoPdi # -- Begin function _Z28__device_stub__InicializacaoPdi
.p2align 4, 0x90
.type _Z28__device_stub__InicializacaoPdi,@function
_Z28__device_stub__InicializacaoPdi: # @_Z28__device_stub__InicializacaoPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13InicializacaoPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__InicializacaoPdi, .Lfunc_end0-_Z28__device_stub__InicializacaoPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13InicializacaoPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13InicializacaoPdi,@object # @_Z13InicializacaoPdi
.section .rodata,"a",@progbits
.globl _Z13InicializacaoPdi
.p2align 3, 0x0
_Z13InicializacaoPdi:
.quad _Z28__device_stub__InicializacaoPdi
.size _Z13InicializacaoPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13InicializacaoPdi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__InicializacaoPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13InicializacaoPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void wave1Drusanov1(double * f_nm, double * f_in,
double nu,int N){
int tid=threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p==N) x_p=0;
double fp = f_in[x_p];
double f = f_in[tid];
f_nm[tid]=0.5*(fp+f)-(nu/3.)*(fp-f);
}
} | code for sm_80
Function : _Z14wave1Drusanov1PdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f05270 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc600078e0207 */
/*00b0*/ SEL R6, R2, RZ, P0 ; /* 0x000000ff02067207 */
/* 0x000fc60000000000 */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ MUFU.RCP64H R3, -3 ; /* 0xc008000000037908 */
/* 0x000e220000001800 */
/*0100*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40080000 ; /* 0x40080000ff0b7424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0130*/ DFMA R8, R2, R10, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c000000000a */
/*0140*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0150*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0160*/ DFMA R2, R8, R10, 1 ; /* 0x3ff000000802742b */
/* 0x001e0c000000000a */
/*0170*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*0180*/ DMUL R8, R2, c[0x0][0x170] ; /* 0x00005c0002087a28 */
/* 0x001e0c0000000000 */
/*0190*/ DFMA R10, R8, R10, c[0x0][0x170] ; /* 0x00005c00080a762b */
/* 0x001e0c000000000a */
/*01a0*/ DFMA R8, R2, R10, R8 ; /* 0x0000000a0208722b */
/* 0x0010640000000008 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x001fd000078e00ff */
/*01c0*/ FFMA R10, RZ, -2.125, R9 ; /* 0xc0080000ff0a7823 */
/* 0x002fe20000000009 */
/*01d0*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fc80003f2e200 */
/*01e0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fe20003f04200 */
/*01f0*/ DADD R2, R4, R6 ; /* 0x0000000004027229 */
/* 0x0040480000000006 */
/*0200*/ DADD R4, -R4, R6 ; /* 0x0000000004047229 */
/* 0x0000900000000106 */
/*0210*/ @P0 BRA P1, 0x240 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0220*/ MOV R10, 0x240 ; /* 0x00000240000a7802 */
/* 0x002fe40000000f00 */
/*0230*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000006000007944 */
/* 0x005fea0003c00000 */
/*0240*/ DMUL R4, R4, R8 ; /* 0x0000000804047228 */
/* 0x007e220000000000 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fca00078e00ff */
/*0260*/ DFMA R2, R2, 0.5, R4 ; /* 0x3fe000000202782b */
/* 0x0010640000000004 */
/*0270*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x001fca00078e0207 */
/*0280*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, -0x40080000 ; /* 0xbff80000ff077424 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe400078e00ff */
/*02c0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x000e220000001800 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*02f0*/ FSETP.GEU.AND P1, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f2e200 */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R12, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0c7812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R22, RZ, RZ, 0x40000000 ; /* 0x40000000ff167424 */
/* 0x000fc600078e00ff */
/*0330*/ ISETP.GE.U32.AND P0, PT, R12, 0x40000000, PT ; /* 0x400000000c00780c */
/* 0x000fe40003f06070 */
/*0340*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe20007ffe0ff */
/*0350*/ DFMA R14, R8, -R6, 1 ; /* 0x3ff00000080e742b */
/* 0x001e0c0000000806 */
/*0360*/ DFMA R16, R14, R14, R14 ; /* 0x0000000e0e10722b */
/* 0x001064000000000e */
/*0370*/ SEL R14, R13, 0x63400000, !P0 ; /* 0x634000000d0e7807 */
/* 0x001fe20004000000 */
/*0380*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e000c */
/*0390*/ @!P1 LOP3.LUT R13, R14.reuse, 0x80000000, R11.reuse, 0xf8, !PT ; /* 0x800000000e0d9812 */
/* 0x140fe200078ef80b */
/*03a0*/ DFMA R18, R8, R16, R8 ; /* 0x000000100812722b */
/* 0x0020640000000008 */
/*03b0*/ LOP3.LUT R9, R14, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff0e097812 */
/* 0x001fe200078ef80b */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P1 LOP3.LUT R17, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d119812 */
/* 0x000fe200078efcff */
/*03e0*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fe200078e00ff */
/*03f0*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x002e0a0000000806 */
/*0400*/ @!P1 DFMA R8, R8, 2, -R16 ; /* 0x400000000808982b */
/* 0x000e480000000810 */
/*0410*/ DFMA R16, R18, R20, R18 ; /* 0x000000141210722b */
/* 0x001e0c0000000012 */
/*0420*/ @!P1 LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f9812 */
/* 0x002fe200078ec0ff */
/*0430*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x001e060000000000 */
/*0440*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fc60007ffe0ff */
/*0450*/ DFMA R20, R18, -R6, R8 ; /* 0x800000061214722b */
/* 0x001e220000000008 */
/*0460*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc80003f04070 */
/*0470*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fe20000704470 */
/*0480*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010580000000012 */
/*0490*/ @P0 BRA 0x640 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R12, R12, -0x40000000, RZ ; /* 0xc00000000c0c7810 */
/* 0x003fc80007ffe0ff */
/*04b0*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*04c0*/ IMNMX R11, R12, 0x46a00000, PT ; /* 0x46a000000c0b7817 */
/* 0x000fca0003800200 */
/*04d0*/ IMAD.IADD R11, R11, 0x1, -R14 ; /* 0x000000010b0b7824 */
/* 0x000fe400078e0a0e */
/*04e0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e00ff */
/*04f0*/ IADD3 R15, R11, 0x7fe00000, RZ ; /* 0x7fe000000b0f7810 */
/* 0x000fcc0007ffe0ff */
/*0500*/ DMUL R12, R16, R14 ; /* 0x0000000e100c7228 */
/* 0x000e140000000000 */
/*0510*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0520*/ @P0 BRA 0x770 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0530*/ DFMA R6, R16, -R6, R8 ; /* 0x800000061006722b */
/* 0x000e220000000008 */
/*0540*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0550*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0560*/ LOP3.LUT R6, R7, 0xc0080000, RZ, 0x3c, !PT ; /* 0xc008000007067812 */
/* 0x000fc800078e3cff */
/*0570*/ LOP3.LUT R9, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006097812 */
/* 0x000fc800078ec0ff */
/*0580*/ LOP3.LUT R15, R9, R15, RZ, 0xfc, !PT ; /* 0x0000000f090f7212 */
/* 0x000fc600078efcff */
/*0590*/ @!P0 BRA 0x770 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*05b0*/ DMUL.RP R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x000e220000008000 */
/*05c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*05d0*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*05e0*/ DFMA R6, R12, -R6, R16 ; /* 0x800000060c06722b */
/* 0x000e460000000010 */
/*05f0*/ LOP3.LUT R9, R15, R9, RZ, 0x3c, !PT ; /* 0x000000090f097212 */
/* 0x001fce00078e3cff */
/*0600*/ FSETP.NEU.AND P0, PT, |R7|, R11, PT ; /* 0x0000000b0700720b */
/* 0x002fc80003f0d200 */
/*0610*/ FSEL R12, R14, R12, !P0 ; /* 0x0000000c0e0c7208 */
/* 0x000fe40004000000 */
/*0620*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0630*/ BRA 0x770 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x003fe400078e00ff */
/*0650*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fcc00078e00ff */
/*0660*/ DSETP.NAN.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c000600762a */
/* 0x000e1c0003f08000 */
/*0670*/ @P0 BRA 0x750 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0680*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0690*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*06b0*/ @!P0 BRA 0x770 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06c0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*06d0*/ LOP3.LUT R11, R11, 0xc0080000, RZ, 0x3c, !PT ; /* 0xc00800000b0b7812 */
/* 0x000fe400078e3cff */
/*06e0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fe40004702670 */
/*06f0*/ LOP3.LUT R13, R11, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000b0d7812 */
/* 0x000fd600078ec0ff */
/*0700*/ @P0 LOP3.LUT R6, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d060812 */
/* 0x000fe200078efcff */
/*0710*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0720*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0730*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0006 */
/*0740*/ BRA 0x770 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0760*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000c */
/*0790*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*07a0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff8500a007950 */
/* 0x000fec0003c3ffff */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void wave1Drusanov1(double * f_nm, double * f_in,
double nu,int N){
int tid=threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p==N) x_p=0;
double fp = f_in[x_p];
double f = f_in[tid];
f_nm[tid]=0.5*(fp+f)-(nu/3.)*(fp-f);
}
} | .file "tmpxft_0014b0bc_00000000-6_wave1Drusanov1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di
.type _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di, @function
_Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14wave1Drusanov1PdS_di(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di, .-_Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di
.globl _Z14wave1Drusanov1PdS_di
.type _Z14wave1Drusanov1PdS_di, @function
_Z14wave1Drusanov1PdS_di:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14wave1Drusanov1PdS_di, .-_Z14wave1Drusanov1PdS_di
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14wave1Drusanov1PdS_di"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14wave1Drusanov1PdS_di(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void wave1Drusanov1(double * f_nm, double * f_in,
double nu,int N){
int tid=threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p==N) x_p=0;
double fp = f_in[x_p];
double f = f_in[tid];
f_nm[tid]=0.5*(fp+f)-(nu/3.)*(fp-f);
}
} | #include <hip/hip_runtime.h>
__global__ void wave1Drusanov1(double * f_nm, double * f_in,
double nu,int N){
int tid=threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p==N) x_p=0;
double fp = f_in[x_p];
double f = f_in[tid];
f_nm[tid]=0.5*(fp+f)-(nu/3.)*(fp-f);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void wave1Drusanov1(double * f_nm, double * f_in,
double nu,int N){
int tid=threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p==N) x_p=0;
double fp = f_in[x_p];
double f = f_in[tid];
f_nm[tid]=0.5*(fp+f)-(nu/3.)*(fp-f);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14wave1Drusanov1PdS_di
.globl _Z14wave1Drusanov1PdS_di
.p2align 8
.type _Z14wave1Drusanov1PdS_di,@function
_Z14wave1Drusanov1PdS_di:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v0, 1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s8, 0
s_mov_b32 s9, 0xc0080000
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ne_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v3, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[5:6], null, s[8:9], s[8:9], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[7:8], v[7:8], off
v_div_scale_f64 v[13:14], vcc_lo, s[6:7], 0xc0080000, s[6:7]
v_rcp_f64_e32 v[9:10], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[5:6], v[11:12], v[13:14]
v_div_fmas_f64 v[4:5], v[4:5], v[9:10], v[11:12]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[9:10], v[2:3], -v[7:8]
v_add_f64 v[2:3], v[2:3], v[7:8]
v_div_fixup_f64 v[4:5], v[4:5], 0xc0080000, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[9:10]
v_fma_f64 v[2:3], v[2:3], 0.5, v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14wave1Drusanov1PdS_di
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14wave1Drusanov1PdS_di, .Lfunc_end0-_Z14wave1Drusanov1PdS_di
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14wave1Drusanov1PdS_di
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14wave1Drusanov1PdS_di.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void wave1Drusanov1(double * f_nm, double * f_in,
double nu,int N){
int tid=threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p==N) x_p=0;
double fp = f_in[x_p];
double f = f_in[tid];
f_nm[tid]=0.5*(fp+f)-(nu/3.)*(fp-f);
}
} | .text
.file "wave1Drusanov1.hip"
.globl _Z29__device_stub__wave1Drusanov1PdS_di # -- Begin function _Z29__device_stub__wave1Drusanov1PdS_di
.p2align 4, 0x90
.type _Z29__device_stub__wave1Drusanov1PdS_di,@function
_Z29__device_stub__wave1Drusanov1PdS_di: # @_Z29__device_stub__wave1Drusanov1PdS_di
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14wave1Drusanov1PdS_di, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__wave1Drusanov1PdS_di, .Lfunc_end0-_Z29__device_stub__wave1Drusanov1PdS_di
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14wave1Drusanov1PdS_di, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14wave1Drusanov1PdS_di,@object # @_Z14wave1Drusanov1PdS_di
.section .rodata,"a",@progbits
.globl _Z14wave1Drusanov1PdS_di
.p2align 3, 0x0
_Z14wave1Drusanov1PdS_di:
.quad _Z29__device_stub__wave1Drusanov1PdS_di
.size _Z14wave1Drusanov1PdS_di, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14wave1Drusanov1PdS_di"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__wave1Drusanov1PdS_di
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14wave1Drusanov1PdS_di
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14wave1Drusanov1PdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.NE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe20003f05270 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc600078e0207 */
/*00b0*/ SEL R6, R2, RZ, P0 ; /* 0x000000ff02067207 */
/* 0x000fc60000000000 */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ MUFU.RCP64H R3, -3 ; /* 0xc008000000037908 */
/* 0x000e220000001800 */
/*0100*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40080000 ; /* 0x40080000ff0b7424 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fcc00078e00ff */
/*0130*/ DFMA R8, R2, R10, 1 ; /* 0x3ff000000208742b */
/* 0x001e0c000000000a */
/*0140*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0150*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0160*/ DFMA R2, R8, R10, 1 ; /* 0x3ff000000802742b */
/* 0x001e0c000000000a */
/*0170*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*0180*/ DMUL R8, R2, c[0x0][0x170] ; /* 0x00005c0002087a28 */
/* 0x001e0c0000000000 */
/*0190*/ DFMA R10, R8, R10, c[0x0][0x170] ; /* 0x00005c00080a762b */
/* 0x001e0c000000000a */
/*01a0*/ DFMA R8, R2, R10, R8 ; /* 0x0000000a0208722b */
/* 0x0010640000000008 */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x001fd000078e00ff */
/*01c0*/ FFMA R10, RZ, -2.125, R9 ; /* 0xc0080000ff0a7823 */
/* 0x002fe20000000009 */
/*01d0*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fc80003f2e200 */
/*01e0*/ FSETP.GT.AND P0, PT, |R10|, 1.469367938527859385e-39, PT ; /* 0x001000000a00780b */
/* 0x000fe20003f04200 */
/*01f0*/ DADD R2, R4, R6 ; /* 0x0000000004027229 */
/* 0x0040480000000006 */
/*0200*/ DADD R4, -R4, R6 ; /* 0x0000000004047229 */
/* 0x0000900000000106 */
/*0210*/ @P0 BRA P1, 0x240 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0220*/ MOV R10, 0x240 ; /* 0x00000240000a7802 */
/* 0x002fe40000000f00 */
/*0230*/ CALL.REL.NOINC 0x2a0 ; /* 0x0000006000007944 */
/* 0x005fea0003c00000 */
/*0240*/ DMUL R4, R4, R8 ; /* 0x0000000804047228 */
/* 0x007e220000000000 */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fca00078e00ff */
/*0260*/ DFMA R2, R2, 0.5, R4 ; /* 0x3fe000000202782b */
/* 0x0010640000000004 */
/*0270*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x001fca00078e0207 */
/*0280*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x002fe2000c101b04 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, -0x40080000 ; /* 0xbff80000ff077424 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0b7624 */
/* 0x000fe400078e00ff */
/*02c0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x000e220000001800 */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*02f0*/ FSETP.GEU.AND P1, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f2e200 */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R12, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0c7812 */
/* 0x000fe200078ec0ff */
/*0320*/ IMAD.MOV.U32 R22, RZ, RZ, 0x40000000 ; /* 0x40000000ff167424 */
/* 0x000fc600078e00ff */
/*0330*/ ISETP.GE.U32.AND P0, PT, R12, 0x40000000, PT ; /* 0x400000000c00780c */
/* 0x000fe40003f06070 */
/*0340*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fe20007ffe0ff */
/*0350*/ DFMA R14, R8, -R6, 1 ; /* 0x3ff00000080e742b */
/* 0x001e0c0000000806 */
/*0360*/ DFMA R16, R14, R14, R14 ; /* 0x0000000e0e10722b */
/* 0x001064000000000e */
/*0370*/ SEL R14, R13, 0x63400000, !P0 ; /* 0x634000000d0e7807 */
/* 0x001fe20004000000 */
/*0380*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fc600078e000c */
/*0390*/ @!P1 LOP3.LUT R13, R14.reuse, 0x80000000, R11.reuse, 0xf8, !PT ; /* 0x800000000e0d9812 */
/* 0x140fe200078ef80b */
/*03a0*/ DFMA R18, R8, R16, R8 ; /* 0x000000100812722b */
/* 0x0020640000000008 */
/*03b0*/ LOP3.LUT R9, R14, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff0e097812 */
/* 0x001fe200078ef80b */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P1 LOP3.LUT R17, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d119812 */
/* 0x000fe200078efcff */
/*03e0*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fe200078e00ff */
/*03f0*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x002e0a0000000806 */
/*0400*/ @!P1 DFMA R8, R8, 2, -R16 ; /* 0x400000000808982b */
/* 0x000e480000000810 */
/*0410*/ DFMA R16, R18, R20, R18 ; /* 0x000000141210722b */
/* 0x001e0c0000000012 */
/*0420*/ @!P1 LOP3.LUT R15, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090f9812 */
/* 0x002fe200078ec0ff */
/*0430*/ DMUL R18, R16, R8 ; /* 0x0000000810127228 */
/* 0x001e060000000000 */
/*0440*/ IADD3 R13, R15, -0x1, RZ ; /* 0xffffffff0f0d7810 */
/* 0x000fc60007ffe0ff */
/*0450*/ DFMA R20, R18, -R6, R8 ; /* 0x800000061214722b */
/* 0x001e220000000008 */
/*0460*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc80003f04070 */
/*0470*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fe20000704470 */
/*0480*/ DFMA R16, R16, R20, R18 ; /* 0x000000141010722b */
/* 0x0010580000000012 */
/*0490*/ @P0 BRA 0x640 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R12, R12, -0x40000000, RZ ; /* 0xc00000000c0c7810 */
/* 0x003fc80007ffe0ff */
/*04b0*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*04c0*/ IMNMX R11, R12, 0x46a00000, PT ; /* 0x46a000000c0b7817 */
/* 0x000fca0003800200 */
/*04d0*/ IMAD.IADD R11, R11, 0x1, -R14 ; /* 0x000000010b0b7824 */
/* 0x000fe400078e0a0e */
/*04e0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e00ff */
/*04f0*/ IADD3 R15, R11, 0x7fe00000, RZ ; /* 0x7fe000000b0f7810 */
/* 0x000fcc0007ffe0ff */
/*0500*/ DMUL R12, R16, R14 ; /* 0x0000000e100c7228 */
/* 0x000e140000000000 */
/*0510*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0520*/ @P0 BRA 0x770 ; /* 0x0000024000000947 */
/* 0x000fea0003800000 */
/*0530*/ DFMA R6, R16, -R6, R8 ; /* 0x800000061006722b */
/* 0x000e220000000008 */
/*0540*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fd200078e00ff */
/*0550*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0560*/ LOP3.LUT R6, R7, 0xc0080000, RZ, 0x3c, !PT ; /* 0xc008000007067812 */
/* 0x000fc800078e3cff */
/*0570*/ LOP3.LUT R9, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006097812 */
/* 0x000fc800078ec0ff */
/*0580*/ LOP3.LUT R15, R9, R15, RZ, 0xfc, !PT ; /* 0x0000000f090f7212 */
/* 0x000fc600078efcff */
/*0590*/ @!P0 BRA 0x770 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*05b0*/ DMUL.RP R14, R16, R14 ; /* 0x0000000e100e7228 */
/* 0x000e220000008000 */
/*05c0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*05d0*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*05e0*/ DFMA R6, R12, -R6, R16 ; /* 0x800000060c06722b */
/* 0x000e460000000010 */
/*05f0*/ LOP3.LUT R9, R15, R9, RZ, 0x3c, !PT ; /* 0x000000090f097212 */
/* 0x001fce00078e3cff */
/*0600*/ FSETP.NEU.AND P0, PT, |R7|, R11, PT ; /* 0x0000000b0700720b */
/* 0x002fc80003f0d200 */
/*0610*/ FSEL R12, R14, R12, !P0 ; /* 0x0000000c0e0c7208 */
/* 0x000fe40004000000 */
/*0620*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0630*/ BRA 0x770 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x003fe400078e00ff */
/*0650*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fcc00078e00ff */
/*0660*/ DSETP.NAN.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c000600762a */
/* 0x000e1c0003f08000 */
/*0670*/ @P0 BRA 0x750 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0680*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0690*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*06b0*/ @!P0 BRA 0x770 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*06c0*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*06d0*/ LOP3.LUT R11, R11, 0xc0080000, RZ, 0x3c, !PT ; /* 0xc00800000b0b7812 */
/* 0x000fe400078e3cff */
/*06e0*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fe40004702670 */
/*06f0*/ LOP3.LUT R13, R11, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000b0d7812 */
/* 0x000fd600078ec0ff */
/*0700*/ @P0 LOP3.LUT R6, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d060812 */
/* 0x000fe200078efcff */
/*0710*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0720*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0730*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0006 */
/*0740*/ BRA 0x770 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R13, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0d7812 */
/* 0x000fe200078efcff */
/*0760*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0c7624 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000c */
/*0790*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*07a0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff8500a007950 */
/* 0x000fec0003c3ffff */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14wave1Drusanov1PdS_di
.globl _Z14wave1Drusanov1PdS_di
.p2align 8
.type _Z14wave1Drusanov1PdS_di,@function
_Z14wave1Drusanov1PdS_di:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x10
v_add_nc_u32_e32 v0, 1, v1
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s8, 0
s_mov_b32 s9, 0xc0080000
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_ne_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v3, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[5:6], null, s[8:9], s[8:9], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v1, vcc_lo
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[7:8], v[7:8], off
v_div_scale_f64 v[13:14], vcc_lo, s[6:7], 0xc0080000, s[6:7]
v_rcp_f64_e32 v[9:10], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[5:6], v[11:12], v[13:14]
v_div_fmas_f64 v[4:5], v[4:5], v[9:10], v[11:12]
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[9:10], v[2:3], -v[7:8]
v_add_f64 v[2:3], v[2:3], v[7:8]
v_div_fixup_f64 v[4:5], v[4:5], 0xc0080000, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[9:10]
v_fma_f64 v[2:3], v[2:3], 0.5, v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14wave1Drusanov1PdS_di
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14wave1Drusanov1PdS_di, .Lfunc_end0-_Z14wave1Drusanov1PdS_di
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14wave1Drusanov1PdS_di
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14wave1Drusanov1PdS_di.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b0bc_00000000-6_wave1Drusanov1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di
.type _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di, @function
_Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14wave1Drusanov1PdS_di(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di, .-_Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di
.globl _Z14wave1Drusanov1PdS_di
.type _Z14wave1Drusanov1PdS_di, @function
_Z14wave1Drusanov1PdS_di:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14wave1Drusanov1PdS_diPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14wave1Drusanov1PdS_di, .-_Z14wave1Drusanov1PdS_di
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14wave1Drusanov1PdS_di"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14wave1Drusanov1PdS_di(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wave1Drusanov1.hip"
.globl _Z29__device_stub__wave1Drusanov1PdS_di # -- Begin function _Z29__device_stub__wave1Drusanov1PdS_di
.p2align 4, 0x90
.type _Z29__device_stub__wave1Drusanov1PdS_di,@function
_Z29__device_stub__wave1Drusanov1PdS_di: # @_Z29__device_stub__wave1Drusanov1PdS_di
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14wave1Drusanov1PdS_di, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__wave1Drusanov1PdS_di, .Lfunc_end0-_Z29__device_stub__wave1Drusanov1PdS_di
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14wave1Drusanov1PdS_di, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14wave1Drusanov1PdS_di,@object # @_Z14wave1Drusanov1PdS_di
.section .rodata,"a",@progbits
.globl _Z14wave1Drusanov1PdS_di
.p2align 3, 0x0
_Z14wave1Drusanov1PdS_di:
.quad _Z29__device_stub__wave1Drusanov1PdS_di
.size _Z14wave1Drusanov1PdS_di, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14wave1Drusanov1PdS_di"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__wave1Drusanov1PdS_di
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14wave1Drusanov1PdS_di
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | ///*
// * Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
// *
// * Please refer to the NVIDIA end user license agreement (EULA) associated
// * with this source code for terms and conditions that govern your use of
// * this software. Any use, reproduction, disclosure, or distribution of
// * this software and related documentation outside the terms of the EULA
// * is strictly prohibited.
// *
// */
// /* This example demonstrates how to use the Cuda OpenGL bindings with the
// * runtime API.
// * Device code.
// */
//#ifndef _SIMPLEGL_KERNEL_H_
//#define _SIMPLEGL_KERNEL_H_
//#include <stdio.h>
//#include <cutil_inline.h>
//#ifndef max
//#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
//#endif
//#ifndef min
//#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
//#endif
///////////////////////////////////////////////////////////////////////////////////
//////! Simple kernel to modify vertex positions in sine wave pattern
//////! @param data data in global memory
///////////////////////////////////////////////////////////////////////////////////
////__global__ void kernel(int *d_Darray, int size)
////{
////// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
////// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
//// // write output vertex
////// printf("d_Darray[%d]= %d",threadIdx.x,d_Darray[threadIdx.x]);
////}
//__global__ void kernel_dualp(float *px, float *py, float *ux_, float *uy_, float sigma, unsigned int stride, unsigned int width, unsigned int height)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// // write output vertex
// px[y*stride+x] = px[y*stride+x] + sigma* ux_[y*stride+x];
// py[y*stride+x] = py[y*stride+x] + sigma* uy_[y*stride+x];
// float pxval = px[y*stride+x];
// float pyval = py[y*stride+x];
// float reprojection = 0;
// reprojection = sqrt(pxval*pxval + pyval*pyval);
// reprojection = max(1,reprojection);
// px[y*stride+x] = px[y*stride+x]/reprojection;
// py[y*stride+x] = py[y*stride+x]/reprojection;
//}
//__global__ void kernel_update_u(float *px, float *py, float *u, float *u_, float* g ,unsigned int stride, unsigned int width, unsigned int height, float tau, float lambda)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// float dxp = 0 , dyp = 0;
// if ( x >= 1 && x < width ) dxp = px[y*stride+x] - px[y*stride+(x-1)];
// if ( y >= 1 && y < height ) dyp = py[y*stride+x] - py[(y-1)*stride+x];
// float divp = dxp + dyp;
// float u_prev = u[y*stride+x];
// u[y*stride+x] = (u_prev + tau*divp+ tau*lambda*g[y*stride+x])/(1+tau*lambda);
// u_[y*stride+x] = 2*u[y*stride+x] - u_prev;
// // u_[y*stride+x] = u[y*stride+x];// - u_prev;
//}
////extern "C" void launch_kernel(int *d_Darray, int size)
////{
//// dim3 block(size,1,1);
//// dim3 grid(1,1);
//// kernel<<< grid, block>>>(d_Darray,size);
//// cutilCheckMsg("execution failed\n");
////}
//#endif // #ifndef _SIMPLEGL_KERNEL_H_ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | ///*
// * Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
// *
// * Please refer to the NVIDIA end user license agreement (EULA) associated
// * with this source code for terms and conditions that govern your use of
// * this software. Any use, reproduction, disclosure, or distribution of
// * this software and related documentation outside the terms of the EULA
// * is strictly prohibited.
// *
// */
// /* This example demonstrates how to use the Cuda OpenGL bindings with the
// * runtime API.
// * Device code.
// */
//#ifndef _SIMPLEGL_KERNEL_H_
//#define _SIMPLEGL_KERNEL_H_
//#include <stdio.h>
//#include <cutil_inline.h>
//#ifndef max
//#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
//#endif
//#ifndef min
//#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
//#endif
///////////////////////////////////////////////////////////////////////////////////
//////! Simple kernel to modify vertex positions in sine wave pattern
//////! @param data data in global memory
///////////////////////////////////////////////////////////////////////////////////
////__global__ void kernel(int *d_Darray, int size)
////{
////// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
////// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
//// // write output vertex
////// printf("d_Darray[%d]= %d",threadIdx.x,d_Darray[threadIdx.x]);
////}
//__global__ void kernel_dualp(float *px, float *py, float *ux_, float *uy_, float sigma, unsigned int stride, unsigned int width, unsigned int height)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// // write output vertex
// px[y*stride+x] = px[y*stride+x] + sigma* ux_[y*stride+x];
// py[y*stride+x] = py[y*stride+x] + sigma* uy_[y*stride+x];
// float pxval = px[y*stride+x];
// float pyval = py[y*stride+x];
// float reprojection = 0;
// reprojection = sqrt(pxval*pxval + pyval*pyval);
// reprojection = max(1,reprojection);
// px[y*stride+x] = px[y*stride+x]/reprojection;
// py[y*stride+x] = py[y*stride+x]/reprojection;
//}
//__global__ void kernel_update_u(float *px, float *py, float *u, float *u_, float* g ,unsigned int stride, unsigned int width, unsigned int height, float tau, float lambda)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// float dxp = 0 , dyp = 0;
// if ( x >= 1 && x < width ) dxp = px[y*stride+x] - px[y*stride+(x-1)];
// if ( y >= 1 && y < height ) dyp = py[y*stride+x] - py[(y-1)*stride+x];
// float divp = dxp + dyp;
// float u_prev = u[y*stride+x];
// u[y*stride+x] = (u_prev + tau*divp+ tau*lambda*g[y*stride+x])/(1+tau*lambda);
// u_[y*stride+x] = 2*u[y*stride+x] - u_prev;
// // u_[y*stride+x] = u[y*stride+x];// - u_prev;
//}
////extern "C" void launch_kernel(int *d_Darray, int size)
////{
//// dim3 block(size,1,1);
//// dim3 grid(1,1);
//// kernel<<< grid, block>>>(d_Darray,size);
//// cutilCheckMsg("execution failed\n");
////}
//#endif // #ifndef _SIMPLEGL_KERNEL_H_ | .file "tmpxft_0001cba2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | ///*
// * Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
// *
// * Please refer to the NVIDIA end user license agreement (EULA) associated
// * with this source code for terms and conditions that govern your use of
// * this software. Any use, reproduction, disclosure, or distribution of
// * this software and related documentation outside the terms of the EULA
// * is strictly prohibited.
// *
// */
// /* This example demonstrates how to use the Cuda OpenGL bindings with the
// * runtime API.
// * Device code.
// */
//#ifndef _SIMPLEGL_KERNEL_H_
//#define _SIMPLEGL_KERNEL_H_
//#include <stdio.h>
//#include <cutil_inline.h>
//#ifndef max
//#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
//#endif
//#ifndef min
//#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
//#endif
///////////////////////////////////////////////////////////////////////////////////
//////! Simple kernel to modify vertex positions in sine wave pattern
//////! @param data data in global memory
///////////////////////////////////////////////////////////////////////////////////
////__global__ void kernel(int *d_Darray, int size)
////{
////// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
////// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
//// // write output vertex
////// printf("d_Darray[%d]= %d",threadIdx.x,d_Darray[threadIdx.x]);
////}
//__global__ void kernel_dualp(float *px, float *py, float *ux_, float *uy_, float sigma, unsigned int stride, unsigned int width, unsigned int height)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// // write output vertex
// px[y*stride+x] = px[y*stride+x] + sigma* ux_[y*stride+x];
// py[y*stride+x] = py[y*stride+x] + sigma* uy_[y*stride+x];
// float pxval = px[y*stride+x];
// float pyval = py[y*stride+x];
// float reprojection = 0;
// reprojection = sqrt(pxval*pxval + pyval*pyval);
// reprojection = max(1,reprojection);
// px[y*stride+x] = px[y*stride+x]/reprojection;
// py[y*stride+x] = py[y*stride+x]/reprojection;
//}
//__global__ void kernel_update_u(float *px, float *py, float *u, float *u_, float* g ,unsigned int stride, unsigned int width, unsigned int height, float tau, float lambda)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// float dxp = 0 , dyp = 0;
// if ( x >= 1 && x < width ) dxp = px[y*stride+x] - px[y*stride+(x-1)];
// if ( y >= 1 && y < height ) dyp = py[y*stride+x] - py[(y-1)*stride+x];
// float divp = dxp + dyp;
// float u_prev = u[y*stride+x];
// u[y*stride+x] = (u_prev + tau*divp+ tau*lambda*g[y*stride+x])/(1+tau*lambda);
// u_[y*stride+x] = 2*u[y*stride+x] - u_prev;
// // u_[y*stride+x] = u[y*stride+x];// - u_prev;
//}
////extern "C" void launch_kernel(int *d_Darray, int size)
////{
//// dim3 block(size,1,1);
//// dim3 grid(1,1);
//// kernel<<< grid, block>>>(d_Darray,size);
//// cutilCheckMsg("execution failed\n");
////}
//#endif // #ifndef _SIMPLEGL_KERNEL_H_ | #include <hip/hip_runtime.h>
///*
// * Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
// *
// * Please refer to the NVIDIA end user license agreement (EULA) associated
// * with this source code for terms and conditions that govern your use of
// * this software. Any use, reproduction, disclosure, or distribution of
// * this software and related documentation outside the terms of the EULA
// * is strictly prohibited.
// *
// */
// /* This example demonstrates how to use the Cuda OpenGL bindings with the
// * runtime API.
// * Device code.
// */
//#ifndef _SIMPLEGL_KERNEL_H_
//#define _SIMPLEGL_KERNEL_H_
//#include <stdio.h>
//#include <cutil_inline.h>
//#ifndef max
//#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
//#endif
//#ifndef min
//#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
//#endif
///////////////////////////////////////////////////////////////////////////////////
//////! Simple kernel to modify vertex positions in sine wave pattern
//////! @param data data in global memory
///////////////////////////////////////////////////////////////////////////////////
////__global__ void kernel(int *d_Darray, int size)
////{
////// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
////// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
//// // write output vertex
////// printf("d_Darray[%d]= %d",threadIdx.x,d_Darray[threadIdx.x]);
////}
//__global__ void kernel_dualp(float *px, float *py, float *ux_, float *uy_, float sigma, unsigned int stride, unsigned int width, unsigned int height)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// // write output vertex
// px[y*stride+x] = px[y*stride+x] + sigma* ux_[y*stride+x];
// py[y*stride+x] = py[y*stride+x] + sigma* uy_[y*stride+x];
// float pxval = px[y*stride+x];
// float pyval = py[y*stride+x];
// float reprojection = 0;
// reprojection = sqrt(pxval*pxval + pyval*pyval);
// reprojection = max(1,reprojection);
// px[y*stride+x] = px[y*stride+x]/reprojection;
// py[y*stride+x] = py[y*stride+x]/reprojection;
//}
//__global__ void kernel_update_u(float *px, float *py, float *u, float *u_, float* g ,unsigned int stride, unsigned int width, unsigned int height, float tau, float lambda)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// float dxp = 0 , dyp = 0;
// if ( x >= 1 && x < width ) dxp = px[y*stride+x] - px[y*stride+(x-1)];
// if ( y >= 1 && y < height ) dyp = py[y*stride+x] - py[(y-1)*stride+x];
// float divp = dxp + dyp;
// float u_prev = u[y*stride+x];
// u[y*stride+x] = (u_prev + tau*divp+ tau*lambda*g[y*stride+x])/(1+tau*lambda);
// u_[y*stride+x] = 2*u[y*stride+x] - u_prev;
// // u_[y*stride+x] = u[y*stride+x];// - u_prev;
//}
////extern "C" void launch_kernel(int *d_Darray, int size)
////{
//// dim3 block(size,1,1);
//// dim3 grid(1,1);
//// kernel<<< grid, block>>>(d_Darray,size);
//// cutilCheckMsg("execution failed\n");
////}
//#endif // #ifndef _SIMPLEGL_KERNEL_H_ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
///*
// * Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
// *
// * Please refer to the NVIDIA end user license agreement (EULA) associated
// * with this source code for terms and conditions that govern your use of
// * this software. Any use, reproduction, disclosure, or distribution of
// * this software and related documentation outside the terms of the EULA
// * is strictly prohibited.
// *
// */
// /* This example demonstrates how to use the Cuda OpenGL bindings with the
// * runtime API.
// * Device code.
// */
//#ifndef _SIMPLEGL_KERNEL_H_
//#define _SIMPLEGL_KERNEL_H_
//#include <stdio.h>
//#include <cutil_inline.h>
//#ifndef max
//#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
//#endif
//#ifndef min
//#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
//#endif
///////////////////////////////////////////////////////////////////////////////////
//////! Simple kernel to modify vertex positions in sine wave pattern
//////! @param data data in global memory
///////////////////////////////////////////////////////////////////////////////////
////__global__ void kernel(int *d_Darray, int size)
////{
////// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
////// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
//// // write output vertex
////// printf("d_Darray[%d]= %d",threadIdx.x,d_Darray[threadIdx.x]);
////}
//__global__ void kernel_dualp(float *px, float *py, float *ux_, float *uy_, float sigma, unsigned int stride, unsigned int width, unsigned int height)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// // write output vertex
// px[y*stride+x] = px[y*stride+x] + sigma* ux_[y*stride+x];
// py[y*stride+x] = py[y*stride+x] + sigma* uy_[y*stride+x];
// float pxval = px[y*stride+x];
// float pyval = py[y*stride+x];
// float reprojection = 0;
// reprojection = sqrt(pxval*pxval + pyval*pyval);
// reprojection = max(1,reprojection);
// px[y*stride+x] = px[y*stride+x]/reprojection;
// py[y*stride+x] = py[y*stride+x]/reprojection;
//}
//__global__ void kernel_update_u(float *px, float *py, float *u, float *u_, float* g ,unsigned int stride, unsigned int width, unsigned int height, float tau, float lambda)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// float dxp = 0 , dyp = 0;
// if ( x >= 1 && x < width ) dxp = px[y*stride+x] - px[y*stride+(x-1)];
// if ( y >= 1 && y < height ) dyp = py[y*stride+x] - py[(y-1)*stride+x];
// float divp = dxp + dyp;
// float u_prev = u[y*stride+x];
// u[y*stride+x] = (u_prev + tau*divp+ tau*lambda*g[y*stride+x])/(1+tau*lambda);
// u_[y*stride+x] = 2*u[y*stride+x] - u_prev;
// // u_[y*stride+x] = u[y*stride+x];// - u_prev;
//}
////extern "C" void launch_kernel(int *d_Darray, int size)
////{
//// dim3 block(size,1,1);
//// dim3 grid(1,1);
//// kernel<<< grid, block>>>(d_Darray,size);
//// cutilCheckMsg("execution failed\n");
////}
//#endif // #ifndef _SIMPLEGL_KERNEL_H_ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
///*
// * Copyright 1993-2010 NVIDIA Corporation. All rights reserved.
// *
// * Please refer to the NVIDIA end user license agreement (EULA) associated
// * with this source code for terms and conditions that govern your use of
// * this software. Any use, reproduction, disclosure, or distribution of
// * this software and related documentation outside the terms of the EULA
// * is strictly prohibited.
// *
// */
// /* This example demonstrates how to use the Cuda OpenGL bindings with the
// * runtime API.
// * Device code.
// */
//#ifndef _SIMPLEGL_KERNEL_H_
//#define _SIMPLEGL_KERNEL_H_
//#include <stdio.h>
//#include <cutil_inline.h>
//#ifndef max
//#define max( a, b ) ( ((a) > (b)) ? (a) : (b) )
//#endif
//#ifndef min
//#define min( a, b ) ( ((a) < (b)) ? (a) : (b) )
//#endif
///////////////////////////////////////////////////////////////////////////////////
//////! Simple kernel to modify vertex positions in sine wave pattern
//////! @param data data in global memory
///////////////////////////////////////////////////////////////////////////////////
////__global__ void kernel(int *d_Darray, int size)
////{
////// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
////// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
//// // write output vertex
////// printf("d_Darray[%d]= %d",threadIdx.x,d_Darray[threadIdx.x]);
////}
//__global__ void kernel_dualp(float *px, float *py, float *ux_, float *uy_, float sigma, unsigned int stride, unsigned int width, unsigned int height)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// // write output vertex
// px[y*stride+x] = px[y*stride+x] + sigma* ux_[y*stride+x];
// py[y*stride+x] = py[y*stride+x] + sigma* uy_[y*stride+x];
// float pxval = px[y*stride+x];
// float pyval = py[y*stride+x];
// float reprojection = 0;
// reprojection = sqrt(pxval*pxval + pyval*pyval);
// reprojection = max(1,reprojection);
// px[y*stride+x] = px[y*stride+x]/reprojection;
// py[y*stride+x] = py[y*stride+x]/reprojection;
//}
//__global__ void kernel_update_u(float *px, float *py, float *u, float *u_, float* g ,unsigned int stride, unsigned int width, unsigned int height, float tau, float lambda)
//{
// unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
// unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// float dxp = 0 , dyp = 0;
// if ( x >= 1 && x < width ) dxp = px[y*stride+x] - px[y*stride+(x-1)];
// if ( y >= 1 && y < height ) dyp = py[y*stride+x] - py[(y-1)*stride+x];
// float divp = dxp + dyp;
// float u_prev = u[y*stride+x];
// u[y*stride+x] = (u_prev + tau*divp+ tau*lambda*g[y*stride+x])/(1+tau*lambda);
// u_[y*stride+x] = 2*u[y*stride+x] - u_prev;
// // u_[y*stride+x] = u[y*stride+x];// - u_prev;
//}
////extern "C" void launch_kernel(int *d_Darray, int size)
////{
//// dim3 block(size,1,1);
//// dim3 grid(1,1);
//// kernel<<< grid, block>>>(d_Darray,size);
//// cutilCheckMsg("execution failed\n");
////}
//#endif // #ifndef _SIMPLEGL_KERNEL_H_ | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001cba2_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__device__ void WarpReduce(volatile int* shared_data, int tid) {
shared_data[tid] += shared_data[tid + 32];
shared_data[tid] += shared_data[tid + 16];
shared_data[tid] += shared_data[tid + 8];
shared_data[tid] += shared_data[tid + 4];
shared_data[tid] += shared_data[tid + 2];
shared_data[tid] += shared_data[tid + 1];
}
__global__ void Reduce(int* in_data, int* out_data) {
extern __shared__ int shared_data[];
unsigned int tid = threadIdx.x;
unsigned int index = blockIdx.x * blockDim.x * 2 + threadIdx.x;
shared_data[tid] = in_data[index] + in_data[index + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s) {
shared_data[tid] += shared_data[tid + s];
}
__syncthreads();
}
if (tid < 32) {
WarpReduce(shared_data, tid);
}
if (tid == 0) {
out_data[blockIdx.x] = shared_data[0];
}
}
int main() {
const int block_size = 256;
// __shared__ int shared_data[];
const int array_size = 1 << 26;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
// int* d_array;
// cudaMalloc(&d_array, sizeof(int) * array_size);
// cudaMemcpy(d_array, h_array, sizeof(int) * array_size, cudaMemcpyHostToDevice);
// int num_blocks = array_size / block_size / 2;
// int* d_blocksum;
// cudaMalloc(&d_blocksum, sizeof(int) * num_blocks);
// int* h_blocksum = new int[num_blocks];
cudaEvent_t start;
cudaEvent_t stop;
// Creating event
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
// Reduce<<<num_blocks, block_size, sizeof(int) * block_size>>>(d_array, d_blocksum);
cudaEventRecord(stop);
// cudaMemcpy(h_blocksum, d_blocksum, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | code for sm_80
Function : _Z6ReducePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ SHF.L.U32 R2, R8, 0x1, RZ ; /* 0x0000000108027819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD R2, R2, R0, R3 ; /* 0x0000000002027224 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE.U32 R4, R2.reuse, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x040fe200078e0007 */
/*0090*/ IADD3 R6, R2, c[0x0][0x0], RZ ; /* 0x0000000002067a10 */
/* 0x000fca0007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000eaa000c1e1900 */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GE.U32.AND P2, PT, R8, 0x42, PT ; /* 0x000000420800780c */
/* 0x000fe40003f46070 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3.reuse, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x040fe40003f04070 */
/*00f0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f25270 */
/*0100*/ IADD3 R2, R6, R5, RZ ; /* 0x0000000506027210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x0001e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P2 BRA 0x210 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x001fe200078e00ff */
/*0150*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc80000000f00 */
/*0160*/ SHF.R.U32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fc80000011604 */
/*0170*/ ISETP.GE.U32.AND P2, PT, R3, R7, PT ; /* 0x000000070300720c */
/* 0x000fda0003f46070 */
/*0180*/ @!P2 IMAD R5, R7, 0x4, R2 ; /* 0x000000040705a824 */
/* 0x000fe200078e0202 */
/*0190*/ @!P2 LDS R6, [R3.X4] ; /* 0x000000000306a984 */
/* 0x000fea0000004800 */
/*01a0*/ @!P2 LDS R5, [R5] ; /* 0x000000000505a984 */
/* 0x000e240000000800 */
/*01b0*/ @!P2 IADD3 R6, R6, R5, RZ ; /* 0x000000050606a210 */
/* 0x001fca0007ffe0ff */
/*01c0*/ @!P2 STS [R3.X4], R6 ; /* 0x000000060300a388 */
/* 0x0001e80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R4, 0x83, PT ; /* 0x000000830400780c */
/* 0x000fe20003f44070 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0007 */
/*0200*/ @P2 BRA 0x160 ; /* 0xffffff5000002947 */
/* 0x001fea000383ffff */
/*0210*/ BSSY B0, 0x3c0 ; /* 0x000001a000007945 */
/* 0x001fe20003800000 */
/*0220*/ @P0 BRA 0x3b0 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0230*/ LDS R2, [R3.X4] ; /* 0x0000000003027984 */
/* 0x000fe80000004800 */
/*0240*/ LDS R5, [R3.X4+0x80] ; /* 0x0000800003057984 */
/* 0x000e240000004800 */
/*0250*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x001fca0007ffe0ff */
/*0260*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe80000004800 */
/*0270*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0280*/ LDS R5, [R3.X4+0x40] ; /* 0x0000400003057984 */
/* 0x000e240000004800 */
/*0290*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x001fca00078e0205 */
/*02a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*02b0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R6, [R3.X4+0x20] ; /* 0x0000200003067984 */
/* 0x000e240000004800 */
/*02d0*/ IADD3 R6, R5, R6, RZ ; /* 0x0000000605067210 */
/* 0x001fca0007ffe0ff */
/*02e0*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000004800 */
/*02f0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R8, [R3.X4+0x10] ; /* 0x0000100003087984 */
/* 0x000e240000004800 */
/*0310*/ IMAD.IADD R8, R5, 0x1, R8 ; /* 0x0000000105087824 */
/* 0x001fca00078e0208 */
/*0320*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*0330*/ LDS R2, [R3.X4] ; /* 0x0000000003027984 */
/* 0x000fe80000004800 */
/*0340*/ LDS R5, [R3.X4+0x8] ; /* 0x0000080003057984 */
/* 0x000e240000004800 */
/*0350*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x001fca0007ffe0ff */
/*0360*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe80000004800 */
/*0370*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0380*/ LDS R5, [R3.X4+0x4] ; /* 0x0000040003057984 */
/* 0x000e240000004800 */
/*0390*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x001fca00078e0205 */
/*03a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0001e40000004800 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*03d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*03e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*03f0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__device__ void WarpReduce(volatile int* shared_data, int tid) {
shared_data[tid] += shared_data[tid + 32];
shared_data[tid] += shared_data[tid + 16];
shared_data[tid] += shared_data[tid + 8];
shared_data[tid] += shared_data[tid + 4];
shared_data[tid] += shared_data[tid + 2];
shared_data[tid] += shared_data[tid + 1];
}
__global__ void Reduce(int* in_data, int* out_data) {
extern __shared__ int shared_data[];
unsigned int tid = threadIdx.x;
unsigned int index = blockIdx.x * blockDim.x * 2 + threadIdx.x;
shared_data[tid] = in_data[index] + in_data[index + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s) {
shared_data[tid] += shared_data[tid + s];
}
__syncthreads();
}
if (tid < 32) {
WarpReduce(shared_data, tid);
}
if (tid == 0) {
out_data[blockIdx.x] = shared_data[0];
}
}
int main() {
const int block_size = 256;
// __shared__ int shared_data[];
const int array_size = 1 << 26;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
// int* d_array;
// cudaMalloc(&d_array, sizeof(int) * array_size);
// cudaMemcpy(d_array, h_array, sizeof(int) * array_size, cudaMemcpyHostToDevice);
// int num_blocks = array_size / block_size / 2;
// int* d_blocksum;
// cudaMalloc(&d_blocksum, sizeof(int) * num_blocks);
// int* h_blocksum = new int[num_blocks];
cudaEvent_t start;
cudaEvent_t stop;
// Creating event
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
// Reduce<<<num_blocks, block_size, sizeof(int) * block_size>>>(d_array, d_blocksum);
cudaEventRecord(stop);
// cudaMemcpy(h_blocksum, d_blocksum, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | .file "tmpxft_000d4da4_00000000-6_naive_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10WarpReducePVii
.type _Z10WarpReducePVii, @function
_Z10WarpReducePVii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10WarpReducePVii, .-_Z10WarpReducePVii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " elapsed"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $268435456, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 268435456(%rax), %rdx
.L6:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
movl $268435456, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 0(%rbp), %eax
movl %eax, (%rbx)
movl $4, %eax
.L7:
movl 0(%rbp,%rax), %edx
addl -4(%rbx,%rax), %edx
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq $268435456, %rax
jne .L7
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 268435452(%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z27__device_stub__Z6ReducePiS_PiS_
.type _Z27__device_stub__Z6ReducePiS_PiS_, @function
_Z27__device_stub__Z6ReducePiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6ReducePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z27__device_stub__Z6ReducePiS_PiS_, .-_Z27__device_stub__Z6ReducePiS_PiS_
.globl _Z6ReducePiS_
.type _Z6ReducePiS_, @function
_Z6ReducePiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6ReducePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6ReducePiS_, .-_Z6ReducePiS_
.section .rodata.str1.1
.LC2:
.string "_Z6ReducePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6ReducePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__device__ void WarpReduce(volatile int* shared_data, int tid) {
shared_data[tid] += shared_data[tid + 32];
shared_data[tid] += shared_data[tid + 16];
shared_data[tid] += shared_data[tid + 8];
shared_data[tid] += shared_data[tid + 4];
shared_data[tid] += shared_data[tid + 2];
shared_data[tid] += shared_data[tid + 1];
}
__global__ void Reduce(int* in_data, int* out_data) {
extern __shared__ int shared_data[];
unsigned int tid = threadIdx.x;
unsigned int index = blockIdx.x * blockDim.x * 2 + threadIdx.x;
shared_data[tid] = in_data[index] + in_data[index + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s) {
shared_data[tid] += shared_data[tid + s];
}
__syncthreads();
}
if (tid < 32) {
WarpReduce(shared_data, tid);
}
if (tid == 0) {
out_data[blockIdx.x] = shared_data[0];
}
}
int main() {
const int block_size = 256;
// __shared__ int shared_data[];
const int array_size = 1 << 26;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
// int* d_array;
// cudaMalloc(&d_array, sizeof(int) * array_size);
// cudaMemcpy(d_array, h_array, sizeof(int) * array_size, cudaMemcpyHostToDevice);
// int num_blocks = array_size / block_size / 2;
// int* d_blocksum;
// cudaMalloc(&d_blocksum, sizeof(int) * num_blocks);
// int* h_blocksum = new int[num_blocks];
cudaEvent_t start;
cudaEvent_t stop;
// Creating event
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
// Reduce<<<num_blocks, block_size, sizeof(int) * block_size>>>(d_array, d_blocksum);
cudaEventRecord(stop);
// cudaMemcpy(h_blocksum, d_blocksum, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | #include <hip/hip_runtime.h>
#include <iostream>
__device__ void WarpReduce(volatile int* shared_data, int tid) {
shared_data[tid] += shared_data[tid + 32];
shared_data[tid] += shared_data[tid + 16];
shared_data[tid] += shared_data[tid + 8];
shared_data[tid] += shared_data[tid + 4];
shared_data[tid] += shared_data[tid + 2];
shared_data[tid] += shared_data[tid + 1];
}
__global__ void Reduce(int* in_data, int* out_data) {
extern __shared__ int shared_data[];
unsigned int tid = threadIdx.x;
unsigned int index = blockIdx.x * blockDim.x * 2 + threadIdx.x;
shared_data[tid] = in_data[index] + in_data[index + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s) {
shared_data[tid] += shared_data[tid + s];
}
__syncthreads();
}
if (tid < 32) {
WarpReduce(shared_data, tid);
}
if (tid == 0) {
out_data[blockIdx.x] = shared_data[0];
}
}
int main() {
const int block_size = 256;
// __shared__ int shared_data[];
const int array_size = 1 << 26;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
// int* d_array;
// cudaMalloc(&d_array, sizeof(int) * array_size);
// cudaMemcpy(d_array, h_array, sizeof(int) * array_size, cudaMemcpyHostToDevice);
// int num_blocks = array_size / block_size / 2;
// int* d_blocksum;
// cudaMalloc(&d_blocksum, sizeof(int) * num_blocks);
// int* h_blocksum = new int[num_blocks];
hipEvent_t start;
hipEvent_t stop;
// Creating event
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
// Reduce<<<num_blocks, block_size, sizeof(int) * block_size>>>(d_array, d_blocksum);
hipEventRecord(stop);
// cudaMemcpy(h_blocksum, d_blocksum, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__device__ void WarpReduce(volatile int* shared_data, int tid) {
shared_data[tid] += shared_data[tid + 32];
shared_data[tid] += shared_data[tid + 16];
shared_data[tid] += shared_data[tid + 8];
shared_data[tid] += shared_data[tid + 4];
shared_data[tid] += shared_data[tid + 2];
shared_data[tid] += shared_data[tid + 1];
}
__global__ void Reduce(int* in_data, int* out_data) {
extern __shared__ int shared_data[];
unsigned int tid = threadIdx.x;
unsigned int index = blockIdx.x * blockDim.x * 2 + threadIdx.x;
shared_data[tid] = in_data[index] + in_data[index + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s) {
shared_data[tid] += shared_data[tid + s];
}
__syncthreads();
}
if (tid < 32) {
WarpReduce(shared_data, tid);
}
if (tid == 0) {
out_data[blockIdx.x] = shared_data[0];
}
}
int main() {
const int block_size = 256;
// __shared__ int shared_data[];
const int array_size = 1 << 26;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
// int* d_array;
// cudaMalloc(&d_array, sizeof(int) * array_size);
// cudaMemcpy(d_array, h_array, sizeof(int) * array_size, cudaMemcpyHostToDevice);
// int num_blocks = array_size / block_size / 2;
// int* d_blocksum;
// cudaMalloc(&d_blocksum, sizeof(int) * num_blocks);
// int* h_blocksum = new int[num_blocks];
hipEvent_t start;
hipEvent_t stop;
// Creating event
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
// Reduce<<<num_blocks, block_size, sizeof(int) * block_size>>>(d_array, d_blocksum);
hipEventRecord(stop);
// cudaMemcpy(h_blocksum, d_blocksum, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6ReducePiS_
.globl _Z6ReducePiS_
.p2align 8
.type _Z6ReducePiS_,@function
_Z6ReducePiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s3, s15, s2
s_cmpk_lt_u32 s2, 0x42
v_lshl_add_u32 v1, s3, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmpk_lt_u32 s2, 0x84
s_mov_b32 s2, s3
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s3, s2, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_7
v_lshl_add_u32 v5, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x80, v5
v_cmp_ne_u32_e64 s2, -1, v5
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, v5, s2
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, s2
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 64, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 32, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 16, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 8, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6ReducePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6ReducePiS_, .Lfunc_end0-_Z6ReducePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym shared_data
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6ReducePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6ReducePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__device__ void WarpReduce(volatile int* shared_data, int tid) {
shared_data[tid] += shared_data[tid + 32];
shared_data[tid] += shared_data[tid + 16];
shared_data[tid] += shared_data[tid + 8];
shared_data[tid] += shared_data[tid + 4];
shared_data[tid] += shared_data[tid + 2];
shared_data[tid] += shared_data[tid + 1];
}
__global__ void Reduce(int* in_data, int* out_data) {
extern __shared__ int shared_data[];
unsigned int tid = threadIdx.x;
unsigned int index = blockIdx.x * blockDim.x * 2 + threadIdx.x;
shared_data[tid] = in_data[index] + in_data[index + blockDim.x];
__syncthreads();
for (unsigned int s = blockDim.x / 2; s > 32; s >>= 1) {
if (tid < s) {
shared_data[tid] += shared_data[tid + s];
}
__syncthreads();
}
if (tid < 32) {
WarpReduce(shared_data, tid);
}
if (tid == 0) {
out_data[blockIdx.x] = shared_data[0];
}
}
int main() {
const int block_size = 256;
// __shared__ int shared_data[];
const int array_size = 1 << 26;
int* h_array = new int[array_size];
for (int i = 0; i < array_size; ++i) {
h_array[i] = 1;
}
int* output = new int[array_size];
// int* d_array;
// cudaMalloc(&d_array, sizeof(int) * array_size);
// cudaMemcpy(d_array, h_array, sizeof(int) * array_size, cudaMemcpyHostToDevice);
// int num_blocks = array_size / block_size / 2;
// int* d_blocksum;
// cudaMalloc(&d_blocksum, sizeof(int) * num_blocks);
// int* h_blocksum = new int[num_blocks];
hipEvent_t start;
hipEvent_t stop;
// Creating event
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
output[0] = h_array[0];
for (int i = 1; i < array_size; ++i) {
output[i] = output[i - 1] + h_array[i];
}
// Reduce<<<num_blocks, block_size, sizeof(int) * block_size>>>(d_array, d_blocksum);
hipEventRecord(stop);
// cudaMemcpy(h_blocksum, d_blocksum, sizeof(int) * num_blocks, cudaMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
std::cout << milliseconds << " elapsed" << std::endl;
std::cout << output[array_size - 1] << std::endl;
delete[] h_array;
delete[] output;
} | .text
.file "naive_scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__ReducePiS_ # -- Begin function _Z21__device_stub__ReducePiS_
.p2align 4, 0x90
.type _Z21__device_stub__ReducePiS_,@function
_Z21__device_stub__ReducePiS_: # @_Z21__device_stub__ReducePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6ReducePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__ReducePiS_, .Lfunc_end0-_Z21__device_stub__ReducePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $268435456, %edi # imm = 0x10000000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $67108864, %rax # imm = 0x4000000
jne .LBB1_1
# %bb.2:
movl $268435456, %edi # imm = 0x10000000
callq _Znam
movq %rax, %r14
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rbx), %eax
movl %eax, (%r14)
movl $1, %ecx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %eax
movl %eax, (%r14,%rcx,4)
incq %rcx
cmpq $67108864, %rcx # imm = 0x4000000
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 268435452(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6ReducePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6ReducePiS_,@object # @_Z6ReducePiS_
.section .rodata,"a",@progbits
.globl _Z6ReducePiS_
.p2align 3, 0x0
_Z6ReducePiS_:
.quad _Z21__device_stub__ReducePiS_
.size _Z6ReducePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " elapsed"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6ReducePiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__ReducePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6ReducePiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6ReducePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ SHF.L.U32 R2, R8, 0x1, RZ ; /* 0x0000000108027819 */
/* 0x000fca00000006ff */
/*0070*/ IMAD R2, R2, R0, R3 ; /* 0x0000000002027224 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE.U32 R4, R2.reuse, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x040fe200078e0007 */
/*0090*/ IADD3 R6, R2, c[0x0][0x0], RZ ; /* 0x0000000002067a10 */
/* 0x000fca0007ffe0ff */
/*00a0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0007 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000eaa000c1e1900 */
/*00c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ISETP.GE.U32.AND P2, PT, R8, 0x42, PT ; /* 0x000000420800780c */
/* 0x000fe40003f46070 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3.reuse, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x040fe40003f04070 */
/*00f0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f25270 */
/*0100*/ IADD3 R2, R6, R5, RZ ; /* 0x0000000506027210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x0001e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P2 BRA 0x210 ; /* 0x000000d00000a947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.SHL.U32 R2, R3, 0x4, RZ ; /* 0x0000000403027824 */
/* 0x001fe200078e00ff */
/*0150*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x000fc80000000f00 */
/*0160*/ SHF.R.U32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fc80000011604 */
/*0170*/ ISETP.GE.U32.AND P2, PT, R3, R7, PT ; /* 0x000000070300720c */
/* 0x000fda0003f46070 */
/*0180*/ @!P2 IMAD R5, R7, 0x4, R2 ; /* 0x000000040705a824 */
/* 0x000fe200078e0202 */
/*0190*/ @!P2 LDS R6, [R3.X4] ; /* 0x000000000306a984 */
/* 0x000fea0000004800 */
/*01a0*/ @!P2 LDS R5, [R5] ; /* 0x000000000505a984 */
/* 0x000e240000000800 */
/*01b0*/ @!P2 IADD3 R6, R6, R5, RZ ; /* 0x000000050606a210 */
/* 0x001fca0007ffe0ff */
/*01c0*/ @!P2 STS [R3.X4], R6 ; /* 0x000000060300a388 */
/* 0x0001e80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R4, 0x83, PT ; /* 0x000000830400780c */
/* 0x000fe20003f44070 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0007 */
/*0200*/ @P2 BRA 0x160 ; /* 0xffffff5000002947 */
/* 0x001fea000383ffff */
/*0210*/ BSSY B0, 0x3c0 ; /* 0x000001a000007945 */
/* 0x001fe20003800000 */
/*0220*/ @P0 BRA 0x3b0 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0230*/ LDS R2, [R3.X4] ; /* 0x0000000003027984 */
/* 0x000fe80000004800 */
/*0240*/ LDS R5, [R3.X4+0x80] ; /* 0x0000800003057984 */
/* 0x000e240000004800 */
/*0250*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x001fca0007ffe0ff */
/*0260*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe80000004800 */
/*0270*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0280*/ LDS R5, [R3.X4+0x40] ; /* 0x0000400003057984 */
/* 0x000e240000004800 */
/*0290*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x001fca00078e0205 */
/*02a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x000fe80000004800 */
/*02b0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS R6, [R3.X4+0x20] ; /* 0x0000200003067984 */
/* 0x000e240000004800 */
/*02d0*/ IADD3 R6, R5, R6, RZ ; /* 0x0000000605067210 */
/* 0x001fca0007ffe0ff */
/*02e0*/ STS [R3.X4], R6 ; /* 0x0000000603007388 */
/* 0x000fe80000004800 */
/*02f0*/ LDS R5, [R3.X4] ; /* 0x0000000003057984 */
/* 0x000fe80000004800 */
/*0300*/ LDS R8, [R3.X4+0x10] ; /* 0x0000100003087984 */
/* 0x000e240000004800 */
/*0310*/ IMAD.IADD R8, R5, 0x1, R8 ; /* 0x0000000105087824 */
/* 0x001fca00078e0208 */
/*0320*/ STS [R3.X4], R8 ; /* 0x0000000803007388 */
/* 0x000fe80000004800 */
/*0330*/ LDS R2, [R3.X4] ; /* 0x0000000003027984 */
/* 0x000fe80000004800 */
/*0340*/ LDS R5, [R3.X4+0x8] ; /* 0x0000080003057984 */
/* 0x000e240000004800 */
/*0350*/ IADD3 R2, R2, R5, RZ ; /* 0x0000000502027210 */
/* 0x001fca0007ffe0ff */
/*0360*/ STS [R3.X4], R2 ; /* 0x0000000203007388 */
/* 0x000fe80000004800 */
/*0370*/ LDS R4, [R3.X4] ; /* 0x0000000003047984 */
/* 0x000fe80000004800 */
/*0380*/ LDS R5, [R3.X4+0x4] ; /* 0x0000040003057984 */
/* 0x000e240000004800 */
/*0390*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x001fca00078e0205 */
/*03a0*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0001e40000004800 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*03d0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*03e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*03f0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6ReducePiS_
.globl _Z6ReducePiS_
.p2align 8
.type _Z6ReducePiS_,@function
_Z6ReducePiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s3, s15, s2
s_cmpk_lt_u32 s2, 0x42
v_lshl_add_u32 v1, s3, 1, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmpk_lt_u32 s2, 0x84
s_mov_b32 s2, s3
.LBB0_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
s_lshr_b32 s3, s2, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_1
.LBB0_5:
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_7
v_lshl_add_u32 v5, v0, 2, 0
s_mov_b64 s[6:7], src_shared_base
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x80, v5
v_cmp_ne_u32_e64 s2, -1, v5
v_cmp_ne_u32_e32 vcc_lo, -1, v2
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, v5, s2
v_cndmask_b32_e32 v3, 0, v2, vcc_lo
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, s2
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 64, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 32, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 16, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 8, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_waitcnt lgkmcnt(0)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v6 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v4, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v6, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 4, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v4
v_cndmask_b32_e64 v4, 0, s7, vcc_lo
flat_store_b32 v[1:2], v5 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v3, v[3:4] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v4, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6ReducePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6ReducePiS_, .Lfunc_end0-_Z6ReducePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym shared_data
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6ReducePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6ReducePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d4da4_00000000-6_naive_scan.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10WarpReducePVii
.type _Z10WarpReducePVii, @function
_Z10WarpReducePVii:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10WarpReducePVii, .-_Z10WarpReducePVii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " elapsed"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $268435456, %edi
call _Znam@PLT
movq %rax, %rbp
leaq 268435456(%rax), %rdx
.L6:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L6
movl $268435456, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 0(%rbp), %eax
movl %eax, (%rbx)
movl $4, %eax
.L7:
movl 0(%rbp,%rax), %edx
addl -4(%rbx,%rax), %edx
movl %edx, (%rbx,%rax)
addq $4, %rax
cmpq $268435456, %rax
jne .L7
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 268435452(%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.globl _Z27__device_stub__Z6ReducePiS_PiS_
.type _Z27__device_stub__Z6ReducePiS_PiS_, @function
_Z27__device_stub__Z6ReducePiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6ReducePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z27__device_stub__Z6ReducePiS_PiS_, .-_Z27__device_stub__Z6ReducePiS_PiS_
.globl _Z6ReducePiS_
.type _Z6ReducePiS_, @function
_Z6ReducePiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6ReducePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6ReducePiS_, .-_Z6ReducePiS_
.section .rodata.str1.1
.LC2:
.string "_Z6ReducePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6ReducePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naive_scan.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__ReducePiS_ # -- Begin function _Z21__device_stub__ReducePiS_
.p2align 4, 0x90
.type _Z21__device_stub__ReducePiS_,@function
_Z21__device_stub__ReducePiS_: # @_Z21__device_stub__ReducePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6ReducePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__ReducePiS_, .Lfunc_end0-_Z21__device_stub__ReducePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $268435456, %edi # imm = 0x10000000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
incq %rax
cmpq $67108864, %rax # imm = 0x4000000
jne .LBB1_1
# %bb.2:
movl $268435456, %edi # imm = 0x10000000
callq _Znam
movq %rax, %r14
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl (%rbx), %eax
movl %eax, (%r14)
movl $1, %ecx
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addl (%rbx,%rcx,4), %eax
movl %eax, (%r14,%rcx,4)
incq %rcx
cmpq $67108864, %rcx # imm = 0x4000000
jne .LBB1_3
# %bb.4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 4(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_13
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB1_8
.LBB1_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 268435452(%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6ReducePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6ReducePiS_,@object # @_Z6ReducePiS_
.section .rodata,"a",@progbits
.globl _Z6ReducePiS_
.p2align 3, 0x0
_Z6ReducePiS_:
.quad _Z21__device_stub__ReducePiS_
.size _Z6ReducePiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " elapsed"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6ReducePiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__ReducePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6ReducePiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#define ARR_SIZE 10
__global__ void add(int *a, int *b, int *c) {
int i = blockIdx.x;
if (i < ARR_SIZE)
c[i] = a[i] + b[i];
}
int main() {
int i;
int h_A[ARR_SIZE], h_B[ARR_SIZE], h_C[ARR_SIZE];
int *d_A, *d_B, *d_C;
// Popula os vetores a serem somados
for (i = 0; i < ARR_SIZE; i++) {
h_A[i] = i;
h_B[i] = i + 1;
}
// Aloca-se memória para os três no dispositivo (GPU)
cudaMalloc((void**) &d_A, ARR_SIZE * sizeof(int));
cudaMalloc((void**) &d_B, ARR_SIZE * sizeof(int));
cudaMalloc((void**) &d_C, ARR_SIZE * sizeof(int));
// Copia o conteudo DRAM -> VRAM
cudaMemcpy(d_A, h_A, ARR_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, ARR_SIZE * sizeof(int), cudaMemcpyHostToDevice);
// Despacha ARR_SIZE blocos de execucao paralela na GPU
add<<<ARR_SIZE, 1>>> (d_A, d_B, d_C);
// Copia o conteudo VRAM -> DRAM
cudaMemcpy(h_C, d_C, ARR_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
for (i = 0; i < ARR_SIZE; i++) {
printf ("[%d] -> %d + %d = %d\n", i, h_A[i], h_B[i], h_C[i]);
}
// Desaloca memoria da GPU
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#define ARR_SIZE 10
__global__ void add(int *a, int *b, int *c) {
int i = blockIdx.x;
if (i < ARR_SIZE)
c[i] = a[i] + b[i];
}
int main() {
int i;
int h_A[ARR_SIZE], h_B[ARR_SIZE], h_C[ARR_SIZE];
int *d_A, *d_B, *d_C;
// Popula os vetores a serem somados
for (i = 0; i < ARR_SIZE; i++) {
h_A[i] = i;
h_B[i] = i + 1;
}
// Aloca-se memória para os três no dispositivo (GPU)
cudaMalloc((void**) &d_A, ARR_SIZE * sizeof(int));
cudaMalloc((void**) &d_B, ARR_SIZE * sizeof(int));
cudaMalloc((void**) &d_C, ARR_SIZE * sizeof(int));
// Copia o conteudo DRAM -> VRAM
cudaMemcpy(d_A, h_A, ARR_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, ARR_SIZE * sizeof(int), cudaMemcpyHostToDevice);
// Despacha ARR_SIZE blocos de execucao paralela na GPU
add<<<ARR_SIZE, 1>>> (d_A, d_B, d_C);
// Copia o conteudo VRAM -> DRAM
cudaMemcpy(h_C, d_C, ARR_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
for (i = 0; i < ARR_SIZE; i++) {
printf ("[%d] -> %d + %d = %d\n", i, h_A[i], h_B[i], h_C[i]);
}
// Desaloca memoria da GPU
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
return 0;
} | .file "tmpxft_0000d503_00000000-6_example1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[%d] -> %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $200, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
leal 1(%rax), %edx
movl %edx, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 48(%rsp,%rbx,4), %ecx
movl 144(%rsp,%rbx,4), %r9d
movl 96(%rsp,%rbx,4), %r8d
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#define ARR_SIZE 10
__global__ void add(int *a, int *b, int *c) {
int i = blockIdx.x;
if (i < ARR_SIZE)
c[i] = a[i] + b[i];
}
int main() {
int i;
int h_A[ARR_SIZE], h_B[ARR_SIZE], h_C[ARR_SIZE];
int *d_A, *d_B, *d_C;
// Popula os vetores a serem somados
for (i = 0; i < ARR_SIZE; i++) {
h_A[i] = i;
h_B[i] = i + 1;
}
// Aloca-se memória para os três no dispositivo (GPU)
cudaMalloc((void**) &d_A, ARR_SIZE * sizeof(int));
cudaMalloc((void**) &d_B, ARR_SIZE * sizeof(int));
cudaMalloc((void**) &d_C, ARR_SIZE * sizeof(int));
// Copia o conteudo DRAM -> VRAM
cudaMemcpy(d_A, h_A, ARR_SIZE * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, ARR_SIZE * sizeof(int), cudaMemcpyHostToDevice);
// Despacha ARR_SIZE blocos de execucao paralela na GPU
add<<<ARR_SIZE, 1>>> (d_A, d_B, d_C);
// Copia o conteudo VRAM -> DRAM
cudaMemcpy(h_C, d_C, ARR_SIZE * sizeof(int), cudaMemcpyDeviceToHost);
for (i = 0; i < ARR_SIZE; i++) {
printf ("[%d] -> %d + %d = %d\n", i, h_A[i], h_B[i], h_C[i]);
}
// Desaloca memoria da GPU
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define ARR_SIZE 10
__global__ void add(int *a, int *b, int *c) {
int i = blockIdx.x;
if (i < ARR_SIZE)
c[i] = a[i] + b[i];
}
int main() {
int i;
int h_A[ARR_SIZE], h_B[ARR_SIZE], h_C[ARR_SIZE];
int *d_A, *d_B, *d_C;
// Popula os vetores a serem somados
for (i = 0; i < ARR_SIZE; i++) {
h_A[i] = i;
h_B[i] = i + 1;
}
// Aloca-se memória para os três no dispositivo (GPU)
hipMalloc((void**) &d_A, ARR_SIZE * sizeof(int));
hipMalloc((void**) &d_B, ARR_SIZE * sizeof(int));
hipMalloc((void**) &d_C, ARR_SIZE * sizeof(int));
// Copia o conteudo DRAM -> VRAM
hipMemcpy(d_A, h_A, ARR_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, ARR_SIZE * sizeof(int), hipMemcpyHostToDevice);
// Despacha ARR_SIZE blocos de execucao paralela na GPU
add<<<ARR_SIZE, 1>>> (d_A, d_B, d_C);
// Copia o conteudo VRAM -> DRAM
hipMemcpy(h_C, d_C, ARR_SIZE * sizeof(int), hipMemcpyDeviceToHost);
for (i = 0; i < ARR_SIZE; i++) {
printf ("[%d] -> %d + %d = %d\n", i, h_A[i], h_B[i], h_C[i]);
}
// Desaloca memoria da GPU
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define ARR_SIZE 10
__global__ void add(int *a, int *b, int *c) {
int i = blockIdx.x;
if (i < ARR_SIZE)
c[i] = a[i] + b[i];
}
int main() {
int i;
int h_A[ARR_SIZE], h_B[ARR_SIZE], h_C[ARR_SIZE];
int *d_A, *d_B, *d_C;
// Popula os vetores a serem somados
for (i = 0; i < ARR_SIZE; i++) {
h_A[i] = i;
h_B[i] = i + 1;
}
// Aloca-se memória para os três no dispositivo (GPU)
hipMalloc((void**) &d_A, ARR_SIZE * sizeof(int));
hipMalloc((void**) &d_B, ARR_SIZE * sizeof(int));
hipMalloc((void**) &d_C, ARR_SIZE * sizeof(int));
// Copia o conteudo DRAM -> VRAM
hipMemcpy(d_A, h_A, ARR_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, ARR_SIZE * sizeof(int), hipMemcpyHostToDevice);
// Despacha ARR_SIZE blocos de execucao paralela na GPU
add<<<ARR_SIZE, 1>>> (d_A, d_B, d_C);
// Copia o conteudo VRAM -> DRAM
hipMemcpy(h_C, d_C, ARR_SIZE * sizeof(int), hipMemcpyDeviceToHost);
for (i = 0; i < ARR_SIZE; i++) {
printf ("[%d] -> %d + %d = %d\n", i, h_A[i], h_B[i], h_C[i]);
}
// Desaloca memoria da GPU
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_cmp_gt_i32 s15, 9
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define ARR_SIZE 10
__global__ void add(int *a, int *b, int *c) {
int i = blockIdx.x;
if (i < ARR_SIZE)
c[i] = a[i] + b[i];
}
int main() {
int i;
int h_A[ARR_SIZE], h_B[ARR_SIZE], h_C[ARR_SIZE];
int *d_A, *d_B, *d_C;
// Popula os vetores a serem somados
for (i = 0; i < ARR_SIZE; i++) {
h_A[i] = i;
h_B[i] = i + 1;
}
// Aloca-se memória para os três no dispositivo (GPU)
hipMalloc((void**) &d_A, ARR_SIZE * sizeof(int));
hipMalloc((void**) &d_B, ARR_SIZE * sizeof(int));
hipMalloc((void**) &d_C, ARR_SIZE * sizeof(int));
// Copia o conteudo DRAM -> VRAM
hipMemcpy(d_A, h_A, ARR_SIZE * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, ARR_SIZE * sizeof(int), hipMemcpyHostToDevice);
// Despacha ARR_SIZE blocos de execucao paralela na GPU
add<<<ARR_SIZE, 1>>> (d_A, d_B, d_C);
// Copia o conteudo VRAM -> DRAM
hipMemcpy(h_C, d_C, ARR_SIZE * sizeof(int), hipMemcpyDeviceToHost);
for (i = 0; i < ARR_SIZE; i++) {
printf ("[%d] -> %d + %d = %d\n", i, h_A[i], h_B[i], h_C[i]);
}
// Desaloca memoria da GPU
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
return 0;
} | .text
.file "example1.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
leaq 1(%rax), %rcx
movl %ecx, 144(%rsp,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 192(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %ecx
movl 96(%rsp,%rbx,4), %r8d
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[%d] -> %d + %d = %d\n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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