system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
#ifndef PI
#define PI 3.14159265359
#endif
extern "C"
__global__
void Shear(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, hipfftComplex * input_fk // input
, hipfftComplex * sheared_fk // sheared
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
float sz = 0;
float dz = 1.0f / nz;
hipfftComplex kernel;
for (int i = 0,kz=0; i < nz; i++, k_1 += nx*ny,kz++)
{
sz += dz;
kernel.x = cosf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
kernel.y = -sinf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
sheared_fk[k_1].x = ldg(&input_fk[k_1].x)*kernel.x - ldg(&input_fk[k_1].y)*kernel.y;
sheared_fk[k_1].y = ldg(&input_fk[k_1].x)*kernel.y + ldg(&input_fk[k_1].y)*kernel.x;
}
}
}
extern "C"
__global__
void ShearTimeDomain(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, float * input // input
, float * sheared // sheared
)
{
int kz = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kz < nz && ky+1 < ny && ky)
{
float sz = (float)(kz) / (nz);
int k = nx*ny*kz + nx*ky;
float w0, w1, _w0, _w1, w00, w01, w10, w11;
float X, Y;
for (int i = 0, kx = 0; i+1 < nx; i++, kx++)
{
X = kx + sz*shift_x + center_shift_x;
Y = ky + sz*shift_y + center_shift_y;
w0 = X - (int)X; w1 = Y - (int)Y;
_w0 = 1 - w0; _w1 = 1 - w1;
//w0 *= w0;w1 *= w1;w0 *= w0;w1 *= w1;
//_w0 *= _w0;_w1 *= _w1;_w0 *= _w0;_w1 *= _w1;
//s0 = 1.0f / (w0 + _w0);s1 = 1.0f / (w1 + _w1);
//w0 *= s0;w1 *= s1;_w0 *= s0;_w1 *= s1;
w00 = _w0*_w1; w01 = _w0*w1; w10 = w0*_w1; w11 = w0*w1;
sheared[k + i] = w00*ldg(&input[k + i]) + w10*ldg(&input[k + i + 1]) + w01*ldg(&input[k + i + nx]) + w11*ldg(&input[k + i + 1 + nx]);
}
}
} | .text
.file "cu_shear.hip"
.globl __device_stub__Shear # -- Begin function __device_stub__Shear
.p2align 4, 0x90
.type __device_stub__Shear,@function
__device_stub__Shear: # @__device_stub__Shear
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $Shear, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__Shear, .Lfunc_end0-__device_stub__Shear
.cfi_endproc
# -- End function
.globl __device_stub__ShearTimeDomain # -- Begin function __device_stub__ShearTimeDomain
.p2align 4, 0x90
.type __device_stub__ShearTimeDomain,@function
__device_stub__ShearTimeDomain: # @__device_stub__ShearTimeDomain
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $ShearTimeDomain, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub__ShearTimeDomain, .Lfunc_end1-__device_stub__ShearTimeDomain
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Shear, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ShearTimeDomain, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type Shear,@object # @Shear
.section .rodata,"a",@progbits
.globl Shear
.p2align 3, 0x0
Shear:
.quad __device_stub__Shear
.size Shear, 8
.type ShearTimeDomain,@object # @ShearTimeDomain
.globl ShearTimeDomain
.p2align 3, 0x0
ShearTimeDomain:
.quad __device_stub__ShearTimeDomain
.size ShearTimeDomain, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Shear"
.size .L__unnamed_1, 6
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "ShearTimeDomain"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Shear
.addrsig_sym __device_stub__ShearTimeDomain
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Shear
.addrsig_sym ShearTimeDomain
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e3a81_00000000-6_cu_shear.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_
.type _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_, @function
_Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_:
.LFB2105:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq Shear(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_, .-_Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_
.globl Shear
.type Shear, @function
Shear:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size Shear, .-Shear
.globl _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_
.type _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_, @function
_Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_:
.LFB2107:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq ShearTimeDomain(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_, .-_Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_
.globl ShearTimeDomain
.type ShearTimeDomain, @function
ShearTimeDomain:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size ShearTimeDomain, .-ShearTimeDomain
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ShearTimeDomain"
.LC1:
.string "Shear"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ShearTimeDomain(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq Shear(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu_shear.hip"
.globl __device_stub__Shear # -- Begin function __device_stub__Shear
.p2align 4, 0x90
.type __device_stub__Shear,@function
__device_stub__Shear: # @__device_stub__Shear
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $Shear, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__Shear, .Lfunc_end0-__device_stub__Shear
.cfi_endproc
# -- End function
.globl __device_stub__ShearTimeDomain # -- Begin function __device_stub__ShearTimeDomain
.p2align 4, 0x90
.type __device_stub__ShearTimeDomain,@function
__device_stub__ShearTimeDomain: # @__device_stub__ShearTimeDomain
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $ShearTimeDomain, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub__ShearTimeDomain, .Lfunc_end1-__device_stub__ShearTimeDomain
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $Shear, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ShearTimeDomain, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type Shear,@object # @Shear
.section .rodata,"a",@progbits
.globl Shear
.p2align 3, 0x0
Shear:
.quad __device_stub__Shear
.size Shear, 8
.type ShearTimeDomain,@object # @ShearTimeDomain
.globl ShearTimeDomain
.p2align 3, 0x0
ShearTimeDomain:
.quad __device_stub__ShearTimeDomain
.size ShearTimeDomain, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "Shear"
.size .L__unnamed_1, 6
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "ShearTimeDomain"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__Shear
.addrsig_sym __device_stub__ShearTimeDomain
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Shear
.addrsig_sym ShearTimeDomain
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
int N;
scanf("%d\n",&N);
int startNode;
scanf("%d\n",&startNode);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*MAX_EDGE);
memset(H_offset,-1,sizeof(int)*N);
int a,b;
int prev_node = -1;
int edge_size = 0;
while(scanf("%d %d\n",&a,&b)!=EOF){
if(a==prev_node){
H_edges[edge_size]=b;
edge_size++;
}
else{
H_offset[a]=edge_size;
H_edges[edge_size]=b;
edge_size++;
prev_node = a;
}
}
for(int i=0;i<N;i++){
if(H_offset[i]==-1){
int j = i+1;
int flag = 0;
while(j<N){
if(H_offset[j]==-1){
}
else{
H_offset[i]=H_offset[j];
flag= 1;
break;
}
j++;
}
if(flag==0){
H_offset[i] = edge_size;
}
}
}
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
cudaMalloc(&D_offset,sizeof(int)*N);
cudaMalloc(&D_visited,sizeof(int)*N);
cudaMalloc(&D_edges,sizeof(int)*edge_size);
cudaMalloc(&D_current_node1,sizeof(int)*edge_size);
cudaMalloc(&D_c_size1,sizeof(int));
cudaMalloc(&D_current_node2,sizeof(int)*edge_size);
cudaMalloc(&D_c_size2,sizeof(int));
cudaMemcpy(D_offset,H_offset,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_edges,H_edges,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_visited,H_visited,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size1,a1,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
int i=1;
cudaEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
cudaMemcpy(H_c_size,D_c_size2, sizeof(int),cudaMemcpyDeviceToHost);
// reset the index
cudaMemcpy(D_c_size1,a0,sizeof(int),cudaMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
cudaMemcpy(H_c_size,D_c_size1, sizeof(int),cudaMemcpyDeviceToHost);
//reset index
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
}
i++;
}
cudaEventRecord(stop);
cudaMemcpy(H_visited,D_visited, sizeof(int)*N,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
return 0;
} | code for sm_80
Function : _Z3BFSPiS_S_S_iiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fcc00078e0204 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0100*/ ISETP.NE.AND P0, PT, R3.reuse, UR4, PT ; /* 0x0000000403007c0c */
/* 0x044fe2000bf05270 */
/*0110*/ IMAD.WIDE R6, R3, R4, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000eae000c1e1900 */
/*0130*/ @P0 LDG.E R0, [R6.64+0x4] ; /* 0x0000040606000981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x004fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.IADD R5, R0, 0x1, -R9 ; /* 0x0000000100057824 */
/* 0x000fe200078e0a09 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fe20000011403 */
/*0180*/ BSSY B0, 0x420 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0190*/ LEA R2, P1, R3, c[0x0][0x198], 0x2 ; /* 0x0000660003027a11 */
/* 0x000fe400078210ff */
/*01a0*/ LOP3.LUT P0, R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe2000780c0ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*01c0*/ LEA.HI.X R3, R3, c[0x0][0x19c], R6, 0x2, P1 ; /* 0x0000670003037a11 */
/* 0x000fd600008f1406 */
/*01d0*/ @!P0 BRA 0x410 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.WIDE R10, R9, R4, c[0x0][0x168] ; /* 0x00005a00090a7625 */
/* 0x000fc800078e0204 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0200*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x001ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R6, R21, R4, c[0x0][0x198] ; /* 0x0000660015067625 */
/* 0x004fca00078e0204 */
/*0230*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0250*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0260*/ BSSY B1, 0x3e0 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0270*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*0280*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0290*/ ISETP.GT.AND P2, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f44270 */
/*02a0*/ @P2 BRA 0x3d0 ; /* 0x0000012000002947 */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*02d0*/ FLO.U32 R16, UR4 ; /* 0x0000000400107d00 */
/* 0x000e2200080e0000 */
/*02e0*/ S2R R13, SR_LANEID ; /* 0x00000000000d7919 */
/* 0x000e2e0000000000 */
/*02f0*/ POPC R19, UR4 ; /* 0x0000000400137d09 */
/* 0x000e620008000000 */
/*0300*/ ISETP.EQ.U32.AND P2, PT, R16, R13, PT ; /* 0x0000000d1000720c */
/* 0x001fe20003f42070 */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x004fe20007ffe0ff */
/*0330*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fc800078e00ff */
/*0340*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fec000c101906 */
/*0350*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R19 ; /* 0x000000130c0d29a8 */
/* 0x002ea800081ee1c6 */
/*0360*/ S2R R14, SR_LTMASK ; /* 0x00000000000e7919 */
/* 0x000e240000003900 */
/*0370*/ LOP3.LUT R18, R14, UR4, RZ, 0xc0, !PT ; /* 0x000000040e127c12 */
/* 0x001fcc000f8ec0ff */
/*0380*/ POPC R18, R18 ; /* 0x0000001200127309 */
/* 0x000e220000000000 */
/*0390*/ SHFL.IDX PT, R15, R13, R16, 0x1f ; /* 0x00001f100d0f7589 */
/* 0x004e2400000e0000 */
/*03a0*/ IADD3 R15, R15, R18, RZ ; /* 0x000000120f0f7210 */
/* 0x001fca0007ffe0ff */
/*03b0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x188] ; /* 0x000062000f0e7625 */
/* 0x000fca00078e0204 */
/*03c0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e4000c101906 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*0400*/ @P0 BRA 0x200 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT R7, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff077212 */
/* 0x000fca00078e33ff */
/*0430*/ IMAD.IADD R7, R7, 0x1, R0 ; /* 0x0000000107077824 */
/* 0x000fca00078e0200 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*0450*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.WIDE R8, R5, R4, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x000fc800078e0204 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff067624 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff077624 */
/* 0x000fe400078e00ff */
/*0490*/ LDG.E R19, [R8.64] ; /* 0x0000000608137981 */
/* 0x001ea2000c1e1900 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*04c0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*04e0*/ BSSY B0, 0x620 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*04f0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0500*/ @P0 BRA 0x610 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0530*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x001e2200080e0000 */
/*0540*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0550*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0560*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0570*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0580*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0590*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*05a0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*05b0*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*05c0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*05d0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*05e0*/ IADD3 R11, R11, R16, RZ ; /* 0x000000100b0b7210 */
/* 0x001fca0007ffe0ff */
/*05f0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0600*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040608137981 */
/* 0x001ea4000c1e1900 */
/*0630*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0640*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ BSSY B0, 0x790 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0670*/ @P0 BRA 0x780 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0680*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0690*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*06a0*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*06b0*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*06c0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*06d0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*06e0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*06f0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0700*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0710*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0720*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0730*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0740*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0750*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0760*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0770*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080608137981 */
/* 0x001ea4000c1e1900 */
/*07a0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*07b0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ BSSY B0, 0x900 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*07d0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*07e0*/ @P0 BRA 0x8f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0810*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0820*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0830*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0840*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0850*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0860*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0870*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0880*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0890*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*08a0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*08b0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*08c0*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*08d0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*08e0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0608137981 */
/* 0x001ea4000c1e1900 */
/*0910*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0920*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ BSSY B0, 0xa70 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0940*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0950*/ @P0 BRA 0xa60 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0970*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0980*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0990*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*09a0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*09b0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*09c0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*09e0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*09f0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0a00*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0a10*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0a20*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0a30*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0a40*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0a50*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0a90*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fc60003f06270 */
/*0aa0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0ab0*/ @!P0 BRA 0x490 ; /* 0xfffff9d000008947 */
/* 0x000fea000383ffff */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
int N;
scanf("%d\n",&N);
int startNode;
scanf("%d\n",&startNode);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*MAX_EDGE);
memset(H_offset,-1,sizeof(int)*N);
int a,b;
int prev_node = -1;
int edge_size = 0;
while(scanf("%d %d\n",&a,&b)!=EOF){
if(a==prev_node){
H_edges[edge_size]=b;
edge_size++;
}
else{
H_offset[a]=edge_size;
H_edges[edge_size]=b;
edge_size++;
prev_node = a;
}
}
for(int i=0;i<N;i++){
if(H_offset[i]==-1){
int j = i+1;
int flag = 0;
while(j<N){
if(H_offset[j]==-1){
}
else{
H_offset[i]=H_offset[j];
flag= 1;
break;
}
j++;
}
if(flag==0){
H_offset[i] = edge_size;
}
}
}
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
cudaMalloc(&D_offset,sizeof(int)*N);
cudaMalloc(&D_visited,sizeof(int)*N);
cudaMalloc(&D_edges,sizeof(int)*edge_size);
cudaMalloc(&D_current_node1,sizeof(int)*edge_size);
cudaMalloc(&D_c_size1,sizeof(int));
cudaMalloc(&D_current_node2,sizeof(int)*edge_size);
cudaMalloc(&D_c_size2,sizeof(int));
cudaMemcpy(D_offset,H_offset,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_edges,H_edges,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_visited,H_visited,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size1,a1,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
int i=1;
cudaEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
cudaMemcpy(H_c_size,D_c_size2, sizeof(int),cudaMemcpyDeviceToHost);
// reset the index
cudaMemcpy(D_c_size1,a0,sizeof(int),cudaMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
cudaMemcpy(H_c_size,D_c_size1, sizeof(int),cudaMemcpyDeviceToHost);
//reset index
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
}
i++;
}
cudaEventRecord(stop);
cudaMemcpy(H_visited,D_visited, sizeof(int)*N,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
return 0;
} | .file "tmpxft_0008439f_00000000-6_bfs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.type _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, @function
_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, .-_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.type _Z3BFSPiS_S_S_iiS_S_S_, @function
_Z3BFSPiS_S_S_iiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3BFSPiS_S_S_iiS_S_S_, .-_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.LC1:
.string "%d %d\n"
.LC2:
.string "completed input\n"
.LC4:
.string "max-level: %d\n"
.LC5:
.string "time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rsi
leaq .LC0(%rip), %rbx
movq %rbx, %rdi
call __isoc23_scanf@PLT
leaq 44(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 40(%rsp), %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $400000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 16(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movl $-1, %esi
movq %rbx, %rdi
call __memset_chk@PLT
movl $1, %ebp
movl $-1, %r14d
leaq .LC1(%rip), %r15
jmp .L12
.L38:
movl 52(%rsp), %edx
movl %edx, 0(%r13)
.L14:
addl $1, %ebp
addq $4, %r13
movl %eax, %r14d
.L12:
leal -1(%rbp), %r12d
leaq 52(%rsp), %rdx
leaq 48(%rsp), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $-1, %eax
je .L37
movl 48(%rsp), %eax
cmpl %r14d, %eax
je .L38
movslq %eax, %rdx
movl %r12d, (%rbx,%rdx,4)
movl 52(%rsp), %edx
movl %edx, 0(%r13)
jmp .L14
.L37:
movl 40(%rsp), %esi
testl %esi, %esi
jle .L16
movslq %esi, %rdi
movl $1, %edx
jmp .L21
.L39:
movl %ecx, -4(%rbx,%rdx,4)
jmp .L17
.L18:
movl %r12d, -4(%rbx,%rdx,4)
.L17:
leaq 1(%rdx), %rax
cmpq %rdi, %rdx
je .L16
movq %rax, %rdx
.L21:
cmpl $-1, -4(%rbx,%rdx,4)
jne .L17
cmpl %edx, %esi
jle .L18
movq %rdx, %rax
.L20:
movl (%rbx,%rax,4), %ecx
cmpl $-1, %ecx
jne .L39
addq $1, %rax
cmpl %eax, %esi
jg .L20
jmp .L18
.L16:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movl 44(%rsp), %edi
movq %rax, 24(%rsp)
movl %edi, 8(%rsp)
movl %edi, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, (%rax)
movslq 40(%rsp), %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %rcx
movq %r15, %rdx
movl $-1, %esi
movq %rax, %rdi
call __memset_chk@PLT
movslq 8(%rsp), %rax
movl $0, (%r14,%rax,4)
movl $4, %edi
call malloc@PLT
movq %rax, %r15
movl $0, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $1, (%rax)
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 0(%rbp), %eax
testl %eax, %eax
jle .L22
movl $1, %ebx
jmp .L27
.L41:
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $512, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L24:
movl $2, %ecx
movl $4, %edx
movq 120(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L25
.L40:
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 96(%rsp)
.cfi_def_cfa_offset 240
pushq 136(%rsp)
.cfi_def_cfa_offset 248
pushq 136(%rsp)
.cfi_def_cfa_offset 256
movl %r12d, %r9d
movl 72(%rsp), %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L24
.L26:
movl $2, %ecx
movl $4, %edx
movq 104(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
.L25:
addl $1, %ebx
movl 0(%rbp), %eax
testl %eax, %eax
jle .L22
.L27:
leal 1022(%rax), %edx
addl $511, %eax
cmovs %edx, %eax
sarl $9, %eax
movl %ebx, %ecx
shrl $31, %ecx
leal (%rbx,%rcx), %edx
andl $1, %edx
subl %ecx, %edx
cmpl $1, %edx
je .L41
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $512, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 96(%rsp)
.cfi_def_cfa_offset 240
pushq 120(%rsp)
.cfi_def_cfa_offset 248
pushq 120(%rsp)
.cfi_def_cfa_offset 256
movl %r12d, %r9d
movl 72(%rsp), %r8d
movq 152(%rsp), %rcx
movq 144(%rsp), %rdx
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L26
.L22:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 140(%rsp)
leaq 140(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 40(%rsp), %edx
testl %edx, %edx
jle .L32
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rsi
movl $0, %edx
.L29:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L29
.L28:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 140(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $0, %edx
jmp .L28
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3BFSPiS_S_S_iiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
int N;
scanf("%d\n",&N);
int startNode;
scanf("%d\n",&startNode);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*MAX_EDGE);
memset(H_offset,-1,sizeof(int)*N);
int a,b;
int prev_node = -1;
int edge_size = 0;
while(scanf("%d %d\n",&a,&b)!=EOF){
if(a==prev_node){
H_edges[edge_size]=b;
edge_size++;
}
else{
H_offset[a]=edge_size;
H_edges[edge_size]=b;
edge_size++;
prev_node = a;
}
}
for(int i=0;i<N;i++){
if(H_offset[i]==-1){
int j = i+1;
int flag = 0;
while(j<N){
if(H_offset[j]==-1){
}
else{
H_offset[i]=H_offset[j];
flag= 1;
break;
}
j++;
}
if(flag==0){
H_offset[i] = edge_size;
}
}
}
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
cudaMalloc(&D_offset,sizeof(int)*N);
cudaMalloc(&D_visited,sizeof(int)*N);
cudaMalloc(&D_edges,sizeof(int)*edge_size);
cudaMalloc(&D_current_node1,sizeof(int)*edge_size);
cudaMalloc(&D_c_size1,sizeof(int));
cudaMalloc(&D_current_node2,sizeof(int)*edge_size);
cudaMalloc(&D_c_size2,sizeof(int));
cudaMemcpy(D_offset,H_offset,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_edges,H_edges,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_visited,H_visited,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size1,a1,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
int i=1;
cudaEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
cudaMemcpy(H_c_size,D_c_size2, sizeof(int),cudaMemcpyDeviceToHost);
// reset the index
cudaMemcpy(D_c_size1,a0,sizeof(int),cudaMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
cudaMemcpy(H_c_size,D_c_size1, sizeof(int),cudaMemcpyDeviceToHost);
//reset index
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
}
i++;
}
cudaEventRecord(stop);
cudaMemcpy(H_visited,D_visited, sizeof(int)*N,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
int N;
scanf("%d\n",&N);
int startNode;
scanf("%d\n",&startNode);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*MAX_EDGE);
memset(H_offset,-1,sizeof(int)*N);
int a,b;
int prev_node = -1;
int edge_size = 0;
while(scanf("%d %d\n",&a,&b)!=EOF){
if(a==prev_node){
H_edges[edge_size]=b;
edge_size++;
}
else{
H_offset[a]=edge_size;
H_edges[edge_size]=b;
edge_size++;
prev_node = a;
}
}
for(int i=0;i<N;i++){
if(H_offset[i]==-1){
int j = i+1;
int flag = 0;
while(j<N){
if(H_offset[j]==-1){
}
else{
H_offset[i]=H_offset[j];
flag= 1;
break;
}
j++;
}
if(flag==0){
H_offset[i] = edge_size;
}
}
}
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
hipMalloc(&D_offset,sizeof(int)*N);
hipMalloc(&D_visited,sizeof(int)*N);
hipMalloc(&D_edges,sizeof(int)*edge_size);
hipMalloc(&D_current_node1,sizeof(int)*edge_size);
hipMalloc(&D_c_size1,sizeof(int));
hipMalloc(&D_current_node2,sizeof(int)*edge_size);
hipMalloc(&D_c_size2,sizeof(int));
hipMemcpy(D_offset,H_offset,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_edges,H_edges,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_visited,H_visited,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_c_size1,a1,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
int i=1;
hipEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
hipMemcpy(H_c_size,D_c_size2, sizeof(int),hipMemcpyDeviceToHost);
// reset the index
hipMemcpy(D_c_size1,a0,sizeof(int),hipMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
hipMemcpy(H_c_size,D_c_size1, sizeof(int),hipMemcpyDeviceToHost);
//reset index
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
}
i++;
}
hipEventRecord(stop);
hipMemcpy(H_visited,D_visited, sizeof(int)*N,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
int N;
scanf("%d\n",&N);
int startNode;
scanf("%d\n",&startNode);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*MAX_EDGE);
memset(H_offset,-1,sizeof(int)*N);
int a,b;
int prev_node = -1;
int edge_size = 0;
while(scanf("%d %d\n",&a,&b)!=EOF){
if(a==prev_node){
H_edges[edge_size]=b;
edge_size++;
}
else{
H_offset[a]=edge_size;
H_edges[edge_size]=b;
edge_size++;
prev_node = a;
}
}
for(int i=0;i<N;i++){
if(H_offset[i]==-1){
int j = i+1;
int flag = 0;
while(j<N){
if(H_offset[j]==-1){
}
else{
H_offset[i]=H_offset[j];
flag= 1;
break;
}
j++;
}
if(flag==0){
H_offset[i] = edge_size;
}
}
}
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
hipMalloc(&D_offset,sizeof(int)*N);
hipMalloc(&D_visited,sizeof(int)*N);
hipMalloc(&D_edges,sizeof(int)*edge_size);
hipMalloc(&D_current_node1,sizeof(int)*edge_size);
hipMalloc(&D_c_size1,sizeof(int));
hipMalloc(&D_current_node2,sizeof(int)*edge_size);
hipMalloc(&D_c_size2,sizeof(int));
hipMemcpy(D_offset,H_offset,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_edges,H_edges,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_visited,H_visited,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_c_size1,a1,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
int i=1;
hipEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
hipMemcpy(H_c_size,D_c_size2, sizeof(int),hipMemcpyDeviceToHost);
// reset the index
hipMemcpy(D_c_size1,a0,sizeof(int),hipMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
hipMemcpy(H_c_size,D_c_size1, sizeof(int),hipMemcpyDeviceToHost);
//reset index
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
}
i++;
}
hipEventRecord(stop);
hipMemcpy(H_visited,D_visited, sizeof(int)*N,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3BFSPiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 8
.type _Z3BFSPiS_S_S_iiS_S_S_,@function
_Z3BFSPiS_S_S_iiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[4:5], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v8, s5
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_add_i32 s2, s4, -1
v_cmp_ne_u32_e32 vcc_lo, s2, v2
global_load_b32 v0, v[4:5], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v8, v[4:5], off offset:4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x28
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v9, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s8, v10
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_10
.LBB0_7:
global_load_b32 v5, v[3:4], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v10, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0, v10
s_cbranch_execz .LBB0_6
global_load_b32 v11, v[1:2], off
s_mov_b32 s8, exec_lo
s_mov_b32 s9, exec_lo
v_mbcnt_lo_u32_b32 v10, s8, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
global_store_b32 v[6:7], v11, off
v_cmpx_eq_u32_e32 0, v10
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v6, s8
global_atomic_add_u32 v6, v9, v6, s[6:7] glc
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3BFSPiS_S_S_iiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z3BFSPiS_S_S_iiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3BFSPiS_S_S_iiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3BFSPiS_S_S_iiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
int N;
scanf("%d\n",&N);
int startNode;
scanf("%d\n",&startNode);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*MAX_EDGE);
memset(H_offset,-1,sizeof(int)*N);
int a,b;
int prev_node = -1;
int edge_size = 0;
while(scanf("%d %d\n",&a,&b)!=EOF){
if(a==prev_node){
H_edges[edge_size]=b;
edge_size++;
}
else{
H_offset[a]=edge_size;
H_edges[edge_size]=b;
edge_size++;
prev_node = a;
}
}
for(int i=0;i<N;i++){
if(H_offset[i]==-1){
int j = i+1;
int flag = 0;
while(j<N){
if(H_offset[j]==-1){
}
else{
H_offset[i]=H_offset[j];
flag= 1;
break;
}
j++;
}
if(flag==0){
H_offset[i] = edge_size;
}
}
}
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
hipMalloc(&D_offset,sizeof(int)*N);
hipMalloc(&D_visited,sizeof(int)*N);
hipMalloc(&D_edges,sizeof(int)*edge_size);
hipMalloc(&D_current_node1,sizeof(int)*edge_size);
hipMalloc(&D_c_size1,sizeof(int));
hipMalloc(&D_current_node2,sizeof(int)*edge_size);
hipMalloc(&D_c_size2,sizeof(int));
hipMemcpy(D_offset,H_offset,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_edges,H_edges,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_visited,H_visited,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_c_size1,a1,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
int i=1;
hipEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
hipMemcpy(H_c_size,D_c_size2, sizeof(int),hipMemcpyDeviceToHost);
// reset the index
hipMemcpy(D_c_size1,a0,sizeof(int),hipMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numThreads,numBlocks>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
hipMemcpy(H_c_size,D_c_size1, sizeof(int),hipMemcpyDeviceToHost);
//reset index
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
}
i++;
}
hipEventRecord(stop);
hipMemcpy(H_visited,D_visited, sizeof(int)*N,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
return 0;
} | .text
.file "bfs.hip"
.globl _Z18__device_stub__BFSPiS_S_S_iiS_S_S_ # -- Begin function _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__BFSPiS_S_S_iiS_S_S_,@function
_Z18__device_stub__BFSPiS_S_S_iiS_S_S_: # @_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z18__device_stub__BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r13d, %r13d
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 204(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbp
movq %r12, %rdi
movl $255, %esi
movq %rbx, %rdx
callq memset@PLT
leaq 44(%rsp), %rsi
leaq 40(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $-1, %eax
je .LBB1_5
# %bb.1: # %.lr.ph.preheader
movl $-1, %r15d
leaq 44(%rsp), %rbx
leaq 40(%rsp), %r14
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl 40(%rsp), %eax
movl %eax, (%rbp,%r13,4)
incq %r13
movl $.L.str.1, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_scanf
cmpl $-1, %eax
je .LBB1_5
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl 44(%rsp), %eax
cmpl %r15d, %eax
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movslq %eax, %rcx
movl %r13d, (%r12,%rcx,4)
movl %eax, %r15d
jmp .LBB1_4
.LBB1_5: # %.preheader107
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_11
# %bb.6: # %.lr.ph112.preheader
leal -1(%rax), %ecx
movq %r12, %rdx
addq $4, %rdx
xorl %esi, %esi
jmp .LBB1_7
.LBB1_10: # in Loop: Header=BB1_7 Depth=1
movl %r13d, %r8d
.LBB1_18: # %.sink.split
# in Loop: Header=BB1_7 Depth=1
movl %r8d, (%r12,%rsi,4)
.LBB1_19: # in Loop: Header=BB1_7 Depth=1
incq %rsi
decq %rcx
addq $4, %rdx
cmpq %rax, %rsi
je .LBB1_11
.LBB1_7: # %.lr.ph112
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
cmpl $-1, (%r12,%rsi,4)
jne .LBB1_19
# %bb.8: # %.preheader.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_9: # %.preheader
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdi, %rcx
je .LBB1_10
# %bb.17: # in Loop: Header=BB1_9 Depth=2
movl (%rdx,%rdi,4), %r8d
incq %rdi
cmpl $-1, %r8d
je .LBB1_9
jmp .LBB1_18
.LBB1_11: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movl %r13d, %edi
shlq $2, %rdi
movq %rdi, 208(%rsp) # 8-byte Spill
callq malloc
movq %rax, 320(%rsp) # 8-byte Spill
movslq 204(%rsp), %rcx
movq %rcx, 56(%rsp) # 8-byte Spill
movl %ecx, (%rax)
movl $4, %edi
callq malloc
movq %rax, %r14
movl $1, (%rax)
movslq 12(%rsp), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %rax, 216(%rsp) # 8-byte Spill
movl $255, %esi
movq %r15, %rdx
callq memset@PLT
movq 56(%rsp), %rax # 8-byte Reload
movl $0, (%rbx,%rax,4)
movl $4, %edi
callq malloc
movq %rax, %r15
movl $0, (%rax)
movl $4, %edi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $1, (%rax)
leaq 232(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 80(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 72(%rsp), %rdi
movq 208(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 224(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 80(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movl $1, %ebx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq %rbp, %rsi
movq 208(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movq 320(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq 216(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4, %edx
movq 56(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 232(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movl (%r14), %edx
testl %edx, %edx
jle .LBB1_24
# %bb.12: # %.lr.ph115
movabsq $4294967296, %rax # imm = 0x100000000
leaq 512(%rax), %r12
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_13 Depth=1
testl %eax, %eax
je .LBB1_21
.LBB1_22: # in Loop: Header=BB1_13 Depth=1
movq 32(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 24(%rsp), %rax
.LBB1_23: # in Loop: Header=BB1_13 Depth=1
movq (%rax), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
incl %ebx
movl (%r14), %edx
testl %edx, %edx
jle .LBB1_24
.LBB1_13: # =>This Inner Loop Header: Depth=1
addl $511, %edx # imm = 0x1FF
shrl $9, %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %bl
je .LBB1_20
# %bb.14: # in Loop: Header=BB1_13 Depth=1
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_13 Depth=1
movq 80(%rsp), %rax
movq %rax, 192(%rsp)
movq 72(%rsp), %rax
movq %rax, 184(%rsp)
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movq 32(%rsp), %rax
movq %rax, 168(%rsp)
movl 12(%rsp), %eax
movl %eax, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movl %r13d, 16(%rsp)
leaq 192(%rsp), %rax
movq %rax, 240(%rsp)
leaq 184(%rsp), %rax
movq %rax, 248(%rsp)
leaq 176(%rsp), %rax
movq %rax, 256(%rsp)
leaq 168(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 240(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16: # in Loop: Header=BB1_13 Depth=1
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rax
jmp .LBB1_23
.LBB1_21: # in Loop: Header=BB1_13 Depth=1
movq 80(%rsp), %rax
movq %rax, 192(%rsp)
movq 72(%rsp), %rax
movq %rax, 184(%rsp)
movq 224(%rsp), %rax
movq %rax, 176(%rsp)
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movl 12(%rsp), %eax
movl %eax, 20(%rsp)
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
movq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movl %r13d, 16(%rsp)
leaq 192(%rsp), %rax
movq %rax, 240(%rsp)
leaq 184(%rsp), %rax
movq %rax, 248(%rsp)
leaq 176(%rsp), %rax
movq %rax, 256(%rsp)
leaq 168(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 240(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_22
.LBB1_24: # %._crit_edge116
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq 216(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
callq hipEventSynchronize
movl $0, 240(%rsp)
movq 232(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_27
# %bb.25: # %.lr.ph120.preheader
xorl %ecx, %ecx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_26: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
cmpl %ebp, %edx
cmovgl %edx, %ebp
incq %rcx
cmpq %rcx, %rax
jne .LBB1_26
.LBB1_27: # %._crit_edge121
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3BFSPiS_S_S_iiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3BFSPiS_S_S_iiS_S_S_,@object # @_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata,"a",@progbits
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 3, 0x0
_Z3BFSPiS_S_S_iiS_S_S_:
.quad _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.size _Z3BFSPiS_S_S_iiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d\n"
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "max-level: %d\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time: %f\n"
.size .L.str.4, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3BFSPiS_S_S_iiS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "completed input"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3BFSPiS_S_S_iiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fcc00078e0204 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0100*/ ISETP.NE.AND P0, PT, R3.reuse, UR4, PT ; /* 0x0000000403007c0c */
/* 0x044fe2000bf05270 */
/*0110*/ IMAD.WIDE R6, R3, R4, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000eae000c1e1900 */
/*0130*/ @P0 LDG.E R0, [R6.64+0x4] ; /* 0x0000040606000981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x004fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.IADD R5, R0, 0x1, -R9 ; /* 0x0000000100057824 */
/* 0x000fe200078e0a09 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fe20000011403 */
/*0180*/ BSSY B0, 0x420 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0190*/ LEA R2, P1, R3, c[0x0][0x198], 0x2 ; /* 0x0000660003027a11 */
/* 0x000fe400078210ff */
/*01a0*/ LOP3.LUT P0, R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe2000780c0ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*01c0*/ LEA.HI.X R3, R3, c[0x0][0x19c], R6, 0x2, P1 ; /* 0x0000670003037a11 */
/* 0x000fd600008f1406 */
/*01d0*/ @!P0 BRA 0x410 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.WIDE R10, R9, R4, c[0x0][0x168] ; /* 0x00005a00090a7625 */
/* 0x000fc800078e0204 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0200*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x001ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R6, R21, R4, c[0x0][0x198] ; /* 0x0000660015067625 */
/* 0x004fca00078e0204 */
/*0230*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0250*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0260*/ BSSY B1, 0x3e0 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0270*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*0280*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0290*/ ISETP.GT.AND P2, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f44270 */
/*02a0*/ @P2 BRA 0x3d0 ; /* 0x0000012000002947 */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*02d0*/ FLO.U32 R16, UR4 ; /* 0x0000000400107d00 */
/* 0x000e2200080e0000 */
/*02e0*/ S2R R13, SR_LANEID ; /* 0x00000000000d7919 */
/* 0x000e2e0000000000 */
/*02f0*/ POPC R19, UR4 ; /* 0x0000000400137d09 */
/* 0x000e620008000000 */
/*0300*/ ISETP.EQ.U32.AND P2, PT, R16, R13, PT ; /* 0x0000000d1000720c */
/* 0x001fe20003f42070 */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x004fe20007ffe0ff */
/*0330*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fc800078e00ff */
/*0340*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fec000c101906 */
/*0350*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R19 ; /* 0x000000130c0d29a8 */
/* 0x002ea800081ee1c6 */
/*0360*/ S2R R14, SR_LTMASK ; /* 0x00000000000e7919 */
/* 0x000e240000003900 */
/*0370*/ LOP3.LUT R18, R14, UR4, RZ, 0xc0, !PT ; /* 0x000000040e127c12 */
/* 0x001fcc000f8ec0ff */
/*0380*/ POPC R18, R18 ; /* 0x0000001200127309 */
/* 0x000e220000000000 */
/*0390*/ SHFL.IDX PT, R15, R13, R16, 0x1f ; /* 0x00001f100d0f7589 */
/* 0x004e2400000e0000 */
/*03a0*/ IADD3 R15, R15, R18, RZ ; /* 0x000000120f0f7210 */
/* 0x001fca0007ffe0ff */
/*03b0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x188] ; /* 0x000062000f0e7625 */
/* 0x000fca00078e0204 */
/*03c0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e4000c101906 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*0400*/ @P0 BRA 0x200 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT R7, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff077212 */
/* 0x000fca00078e33ff */
/*0430*/ IMAD.IADD R7, R7, 0x1, R0 ; /* 0x0000000107077824 */
/* 0x000fca00078e0200 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*0450*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.WIDE R8, R5, R4, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x000fc800078e0204 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff067624 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff077624 */
/* 0x000fe400078e00ff */
/*0490*/ LDG.E R19, [R8.64] ; /* 0x0000000608137981 */
/* 0x001ea2000c1e1900 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*04c0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*04e0*/ BSSY B0, 0x620 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*04f0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0500*/ @P0 BRA 0x610 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0530*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x001e2200080e0000 */
/*0540*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0550*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0560*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0570*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0580*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0590*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*05a0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*05b0*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*05c0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*05d0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*05e0*/ IADD3 R11, R11, R16, RZ ; /* 0x000000100b0b7210 */
/* 0x001fca0007ffe0ff */
/*05f0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0600*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040608137981 */
/* 0x001ea4000c1e1900 */
/*0630*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0640*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ BSSY B0, 0x790 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0670*/ @P0 BRA 0x780 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0680*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0690*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*06a0*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*06b0*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*06c0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*06d0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*06e0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*06f0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0700*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0710*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0720*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0730*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0740*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0750*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0760*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0770*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080608137981 */
/* 0x001ea4000c1e1900 */
/*07a0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*07b0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ BSSY B0, 0x900 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*07d0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*07e0*/ @P0 BRA 0x8f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0810*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0820*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0830*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0840*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0850*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0860*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0870*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0880*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0890*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*08a0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*08b0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*08c0*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*08d0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*08e0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0608137981 */
/* 0x001ea4000c1e1900 */
/*0910*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0920*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ BSSY B0, 0xa70 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0940*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0950*/ @P0 BRA 0xa60 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0970*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0980*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0990*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*09a0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*09b0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*09c0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*09e0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*09f0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0a00*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0a10*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0a20*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0a30*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0a40*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0a50*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0a90*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fc60003f06270 */
/*0aa0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0ab0*/ @!P0 BRA 0x490 ; /* 0xfffff9d000008947 */
/* 0x000fea000383ffff */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3BFSPiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 8
.type _Z3BFSPiS_S_S_iiS_S_S_,@function
_Z3BFSPiS_S_S_iiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[4:5], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v8, s5
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_add_i32 s2, s4, -1
v_cmp_ne_u32_e32 vcc_lo, s2, v2
global_load_b32 v0, v[4:5], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v8, v[4:5], off offset:4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x28
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v9, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s8, v10
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_10
.LBB0_7:
global_load_b32 v5, v[3:4], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v10, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0, v10
s_cbranch_execz .LBB0_6
global_load_b32 v11, v[1:2], off
s_mov_b32 s8, exec_lo
s_mov_b32 s9, exec_lo
v_mbcnt_lo_u32_b32 v10, s8, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
global_store_b32 v[6:7], v11, off
v_cmpx_eq_u32_e32 0, v10
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v6, s8
global_atomic_add_u32 v6, v9, v6, s[6:7] glc
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3BFSPiS_S_S_iiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z3BFSPiS_S_S_iiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3BFSPiS_S_S_iiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3BFSPiS_S_S_iiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008439f_00000000-6_bfs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.type _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, @function
_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, .-_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.type _Z3BFSPiS_S_S_iiS_S_S_, @function
_Z3BFSPiS_S_S_iiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3BFSPiS_S_S_iiS_S_S_, .-_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.LC1:
.string "%d %d\n"
.LC2:
.string "completed input\n"
.LC4:
.string "max-level: %d\n"
.LC5:
.string "time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rsi
leaq .LC0(%rip), %rbx
movq %rbx, %rdi
call __isoc23_scanf@PLT
leaq 44(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq 40(%rsp), %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $400000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 16(%rsp)
movq %rbp, %rcx
movq %rbp, %rdx
movl $-1, %esi
movq %rbx, %rdi
call __memset_chk@PLT
movl $1, %ebp
movl $-1, %r14d
leaq .LC1(%rip), %r15
jmp .L12
.L38:
movl 52(%rsp), %edx
movl %edx, 0(%r13)
.L14:
addl $1, %ebp
addq $4, %r13
movl %eax, %r14d
.L12:
leal -1(%rbp), %r12d
leaq 52(%rsp), %rdx
leaq 48(%rsp), %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $-1, %eax
je .L37
movl 48(%rsp), %eax
cmpl %r14d, %eax
je .L38
movslq %eax, %rdx
movl %r12d, (%rbx,%rdx,4)
movl 52(%rsp), %edx
movl %edx, 0(%r13)
jmp .L14
.L37:
movl 40(%rsp), %esi
testl %esi, %esi
jle .L16
movslq %esi, %rdi
movl $1, %edx
jmp .L21
.L39:
movl %ecx, -4(%rbx,%rdx,4)
jmp .L17
.L18:
movl %r12d, -4(%rbx,%rdx,4)
.L17:
leaq 1(%rdx), %rax
cmpq %rdi, %rdx
je .L16
movq %rax, %rdx
.L21:
cmpl $-1, -4(%rbx,%rdx,4)
jne .L17
cmpl %edx, %esi
jle .L18
movq %rdx, %rax
.L20:
movl (%rbx,%rax,4), %ecx
cmpl $-1, %ecx
jne .L39
addq $1, %rax
cmpl %eax, %esi
jg .L20
jmp .L18
.L16:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movl 44(%rsp), %edi
movq %rax, 24(%rsp)
movl %edi, 8(%rsp)
movl %edi, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $1, (%rax)
movslq 40(%rsp), %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movq %r15, %rcx
movq %r15, %rdx
movl $-1, %esi
movq %rax, %rdi
call __memset_chk@PLT
movslq 8(%rsp), %rax
movl $0, (%r14,%rax,4)
movl $4, %edi
call malloc@PLT
movq %rax, %r15
movl $0, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $1, (%rax)
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 40(%rsp), %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 0(%rbp), %eax
testl %eax, %eax
jle .L22
movl $1, %ebx
jmp .L27
.L41:
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $512, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L24:
movl $2, %ecx
movl $4, %edx
movq 120(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L25
.L40:
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 96(%rsp)
.cfi_def_cfa_offset 240
pushq 136(%rsp)
.cfi_def_cfa_offset 248
pushq 136(%rsp)
.cfi_def_cfa_offset 256
movl %r12d, %r9d
movl 72(%rsp), %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L24
.L26:
movl $2, %ecx
movl $4, %edx
movq 104(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
.L25:
addl $1, %ebx
movl 0(%rbp), %eax
testl %eax, %eax
jle .L22
.L27:
leal 1022(%rax), %edx
addl $511, %eax
cmovs %edx, %eax
sarl $9, %eax
movl %ebx, %ecx
shrl $31, %ecx
leal (%rbx,%rcx), %edx
andl $1, %edx
subl %ecx, %edx
cmpl $1, %edx
je .L41
movl %eax, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $512, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L26
subq $8, %rsp
.cfi_def_cfa_offset 232
pushq 96(%rsp)
.cfi_def_cfa_offset 240
pushq 120(%rsp)
.cfi_def_cfa_offset 248
pushq 120(%rsp)
.cfi_def_cfa_offset 256
movl %r12d, %r9d
movl 72(%rsp), %r8d
movq 152(%rsp), %rcx
movq 144(%rsp), %rdx
movq 112(%rsp), %rsi
movq 104(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 224
jmp .L26
.L22:
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movslq 40(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 88(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 140(%rsp)
leaq 140(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 40(%rsp), %edx
testl %edx, %edx
jle .L32
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rsi
movl $0, %edx
.L29:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L29
.L28:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 140(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $0, %edx
jmp .L28
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3BFSPiS_S_S_iiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bfs.hip"
.globl _Z18__device_stub__BFSPiS_S_S_iiS_S_S_ # -- Begin function _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__BFSPiS_S_S_iiS_S_S_,@function
_Z18__device_stub__BFSPiS_S_S_iiS_S_S_: # @_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z18__device_stub__BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r13d, %r13d
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 204(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbp
movq %r12, %rdi
movl $255, %esi
movq %rbx, %rdx
callq memset@PLT
leaq 44(%rsp), %rsi
leaq 40(%rsp), %rdx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $-1, %eax
je .LBB1_5
# %bb.1: # %.lr.ph.preheader
movl $-1, %r15d
leaq 44(%rsp), %rbx
leaq 40(%rsp), %r14
xorl %r13d, %r13d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl 40(%rsp), %eax
movl %eax, (%rbp,%r13,4)
incq %r13
movl $.L.str.1, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_scanf
cmpl $-1, %eax
je .LBB1_5
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl 44(%rsp), %eax
cmpl %r15d, %eax
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movslq %eax, %rcx
movl %r13d, (%r12,%rcx,4)
movl %eax, %r15d
jmp .LBB1_4
.LBB1_5: # %.preheader107
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_11
# %bb.6: # %.lr.ph112.preheader
leal -1(%rax), %ecx
movq %r12, %rdx
addq $4, %rdx
xorl %esi, %esi
jmp .LBB1_7
.LBB1_10: # in Loop: Header=BB1_7 Depth=1
movl %r13d, %r8d
.LBB1_18: # %.sink.split
# in Loop: Header=BB1_7 Depth=1
movl %r8d, (%r12,%rsi,4)
.LBB1_19: # in Loop: Header=BB1_7 Depth=1
incq %rsi
decq %rcx
addq $4, %rdx
cmpq %rax, %rsi
je .LBB1_11
.LBB1_7: # %.lr.ph112
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
cmpl $-1, (%r12,%rsi,4)
jne .LBB1_19
# %bb.8: # %.preheader.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_9: # %.preheader
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdi, %rcx
je .LBB1_10
# %bb.17: # in Loop: Header=BB1_9 Depth=2
movl (%rdx,%rdi,4), %r8d
incq %rdi
cmpl $-1, %r8d
je .LBB1_9
jmp .LBB1_18
.LBB1_11: # %._crit_edge
movl $.Lstr, %edi
callq puts@PLT
movl %r13d, %edi
shlq $2, %rdi
movq %rdi, 208(%rsp) # 8-byte Spill
callq malloc
movq %rax, 320(%rsp) # 8-byte Spill
movslq 204(%rsp), %rcx
movq %rcx, 56(%rsp) # 8-byte Spill
movl %ecx, (%rax)
movl $4, %edi
callq malloc
movq %rax, %r14
movl $1, (%rax)
movslq 12(%rsp), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %rax, 216(%rsp) # 8-byte Spill
movl $255, %esi
movq %r15, %rdx
callq memset@PLT
movq 56(%rsp), %rax # 8-byte Reload
movl $0, (%rbx,%rax,4)
movl $4, %edi
callq malloc
movq %rax, %r15
movl $0, (%rax)
movl $4, %edi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movl $1, (%rax)
leaq 232(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 80(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 72(%rsp), %rdi
movq 208(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 224(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 80(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movl $1, %ebx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq %rbp, %rsi
movq 208(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movq 320(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq 216(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4, %edx
movq 56(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 232(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movl (%r14), %edx
testl %edx, %edx
jle .LBB1_24
# %bb.12: # %.lr.ph115
movabsq $4294967296, %rax # imm = 0x100000000
leaq 512(%rax), %r12
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_20: # in Loop: Header=BB1_13 Depth=1
testl %eax, %eax
je .LBB1_21
.LBB1_22: # in Loop: Header=BB1_13 Depth=1
movq 32(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 24(%rsp), %rax
.LBB1_23: # in Loop: Header=BB1_13 Depth=1
movq (%rax), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
incl %ebx
movl (%r14), %edx
testl %edx, %edx
jle .LBB1_24
.LBB1_13: # =>This Inner Loop Header: Depth=1
addl $511, %edx # imm = 0x1FF
shrl $9, %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %bl
je .LBB1_20
# %bb.14: # in Loop: Header=BB1_13 Depth=1
testl %eax, %eax
jne .LBB1_16
# %bb.15: # in Loop: Header=BB1_13 Depth=1
movq 80(%rsp), %rax
movq %rax, 192(%rsp)
movq 72(%rsp), %rax
movq %rax, 184(%rsp)
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movq 32(%rsp), %rax
movq %rax, 168(%rsp)
movl 12(%rsp), %eax
movl %eax, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movl %r13d, 16(%rsp)
leaq 192(%rsp), %rax
movq %rax, 240(%rsp)
leaq 184(%rsp), %rax
movq %rax, 248(%rsp)
leaq 176(%rsp), %rax
movq %rax, 256(%rsp)
leaq 168(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 240(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16: # in Loop: Header=BB1_13 Depth=1
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rax
jmp .LBB1_23
.LBB1_21: # in Loop: Header=BB1_13 Depth=1
movq 80(%rsp), %rax
movq %rax, 192(%rsp)
movq 72(%rsp), %rax
movq %rax, 184(%rsp)
movq 224(%rsp), %rax
movq %rax, 176(%rsp)
movq 24(%rsp), %rax
movq %rax, 168(%rsp)
movl 12(%rsp), %eax
movl %eax, 20(%rsp)
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
movq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movl %r13d, 16(%rsp)
leaq 192(%rsp), %rax
movq %rax, 240(%rsp)
leaq 184(%rsp), %rax
movq %rax, 248(%rsp)
leaq 176(%rsp), %rax
movq %rax, 256(%rsp)
leaq 168(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 160(%rsp), %rax
movq %rax, 288(%rsp)
leaq 152(%rsp), %rax
movq %rax, 296(%rsp)
leaq 144(%rsp), %rax
movq %rax, 304(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 240(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_22
.LBB1_24: # %._crit_edge116
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq 216(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 88(%rsp), %rdi
callq hipEventSynchronize
movl $0, 240(%rsp)
movq 232(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_27
# %bb.25: # %.lr.ph120.preheader
xorl %ecx, %ecx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_26: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
cmpl %ebp, %edx
cmovgl %edx, %ebp
incq %rcx
cmpq %rcx, %rax
jne .LBB1_26
.LBB1_27: # %._crit_edge121
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3BFSPiS_S_S_iiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3BFSPiS_S_S_iiS_S_S_,@object # @_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata,"a",@progbits
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 3, 0x0
_Z3BFSPiS_S_S_iiS_S_S_:
.quad _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.size _Z3BFSPiS_S_S_iiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d\n"
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "max-level: %d\n"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time: %f\n"
.size .L.str.4, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3BFSPiS_S_S_iiS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "completed input"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* purpose: CUDA managed unified memory for >= pascal architectures;
* this version just uses cudaMallocManaged() on the host,
* then runs a kernel on the GPU to add together two arrays
* of size 1 GB and save the results into a third array;
* result: working great ! when running a loop over 25 attemps with
* 'watch nvidia-smi' open in a background terminal, we see
* Memory-Usage 3185MiB / 8114MiB
* n.b. for visual clarity, the printout section below should be
* commented out when starting to do some profiling runs,
* e.g. nvprof ./a.out
* compilation: nvcc ./unified_memory_example_1.cu
* usage: ./a.out
*/
#include <stdio.h>
#define ARRAYDIM 268435456
/*
* GPU kernel working with unified memory which had been
* allocated using cudaMallocManaged() on the host
*/
__global__ void KrnlDmmy(float *x, float *y, float *z)
{
int i;
i = (blockIdx.x * blockDim.x) + threadIdx.x;
x[i] = (float) i;
y[i] = (float) (i + 1);
z[i] = x[i] + y[i];
return;
}
/*
* host main
*/
int main()
{
int i, cudaRtrn;
dim3 thrds_per_block, blcks_per_grid;
float *a, *b, *c;
/*
* Let us make use of cudaMallocManaged() to allocate 3 arrays
* of size 1 GB each for subsequent usage on the GPU.
*/
if (cudaRtrn = cudaMallocManaged(&a, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array a[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = cudaMallocManaged(&b, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array b[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = cudaMallocManaged(&c, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array c[], %d ***\n", cudaRtrn);
}
/*
* next we want to call a simple kernel that sets array elements
* a[] and b[] with thread-specific values and then adds together
* these values and stores back the result into array c[]
*/
thrds_per_block.x = 256;
blcks_per_grid.x = ARRAYDIM / thrds_per_block.x;
KrnlDmmy<<<blcks_per_grid, thrds_per_block>>>(a, b, c);
cudaDeviceSynchronize();
//for (i=0; i<=100; i++) {
// printf("%6d%6.1f%6.1f%6.1f\n", i, a[i], b[i], c[i]);
//}
cudaFree(c);
cudaFree(b);
cudaFree(a);
return(0);
} | code for sm_80
Function : _Z8KrnlDmmyPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x000e220000201400 */
/*0070*/ IADD3 R8, R0.reuse, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x040fe20007ffe0ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ I2F R11, R8 ; /* 0x00000008000b7306 */
/* 0x000e620000201400 */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x001fe8000c101904 */
/*00c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x002fe8000c101904 */
/*00d0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* purpose: CUDA managed unified memory for >= pascal architectures;
* this version just uses cudaMallocManaged() on the host,
* then runs a kernel on the GPU to add together two arrays
* of size 1 GB and save the results into a third array;
* result: working great ! when running a loop over 25 attemps with
* 'watch nvidia-smi' open in a background terminal, we see
* Memory-Usage 3185MiB / 8114MiB
* n.b. for visual clarity, the printout section below should be
* commented out when starting to do some profiling runs,
* e.g. nvprof ./a.out
* compilation: nvcc ./unified_memory_example_1.cu
* usage: ./a.out
*/
#include <stdio.h>
#define ARRAYDIM 268435456
/*
* GPU kernel working with unified memory which had been
* allocated using cudaMallocManaged() on the host
*/
__global__ void KrnlDmmy(float *x, float *y, float *z)
{
int i;
i = (blockIdx.x * blockDim.x) + threadIdx.x;
x[i] = (float) i;
y[i] = (float) (i + 1);
z[i] = x[i] + y[i];
return;
}
/*
* host main
*/
int main()
{
int i, cudaRtrn;
dim3 thrds_per_block, blcks_per_grid;
float *a, *b, *c;
/*
* Let us make use of cudaMallocManaged() to allocate 3 arrays
* of size 1 GB each for subsequent usage on the GPU.
*/
if (cudaRtrn = cudaMallocManaged(&a, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array a[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = cudaMallocManaged(&b, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array b[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = cudaMallocManaged(&c, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array c[], %d ***\n", cudaRtrn);
}
/*
* next we want to call a simple kernel that sets array elements
* a[] and b[] with thread-specific values and then adds together
* these values and stores back the result into array c[]
*/
thrds_per_block.x = 256;
blcks_per_grid.x = ARRAYDIM / thrds_per_block.x;
KrnlDmmy<<<blcks_per_grid, thrds_per_block>>>(a, b, c);
cudaDeviceSynchronize();
//for (i=0; i<=100; i++) {
// printf("%6d%6.1f%6.1f%6.1f\n", i, a[i], b[i], c[i]);
//}
cudaFree(c);
cudaFree(b);
cudaFree(a);
return(0);
} | .file "tmpxft_0003936f_00000000-6_unified_memory_example_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
.type _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_, @function
_Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8KrnlDmmyPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_, .-_Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
.globl _Z8KrnlDmmyPfS_S_
.type _Z8KrnlDmmyPfS_S_, @function
_Z8KrnlDmmyPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8KrnlDmmyPfS_S_, .-_Z8KrnlDmmyPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "*** allocation failed for array a[], %d ***\n"
.align 8
.LC1:
.string "*** allocation failed for array b[], %d ***\n"
.align 8
.LC2:
.string "*** allocation failed for array c[], %d ***\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L18
.L12:
leaq 16(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L19
.L13:
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L20
.L14:
movl $1048576, 44(%rsp)
movl $256, 32(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L19:
movl $1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L20:
movl $1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z8KrnlDmmyPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8KrnlDmmyPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* purpose: CUDA managed unified memory for >= pascal architectures;
* this version just uses cudaMallocManaged() on the host,
* then runs a kernel on the GPU to add together two arrays
* of size 1 GB and save the results into a third array;
* result: working great ! when running a loop over 25 attemps with
* 'watch nvidia-smi' open in a background terminal, we see
* Memory-Usage 3185MiB / 8114MiB
* n.b. for visual clarity, the printout section below should be
* commented out when starting to do some profiling runs,
* e.g. nvprof ./a.out
* compilation: nvcc ./unified_memory_example_1.cu
* usage: ./a.out
*/
#include <stdio.h>
#define ARRAYDIM 268435456
/*
* GPU kernel working with unified memory which had been
* allocated using cudaMallocManaged() on the host
*/
__global__ void KrnlDmmy(float *x, float *y, float *z)
{
int i;
i = (blockIdx.x * blockDim.x) + threadIdx.x;
x[i] = (float) i;
y[i] = (float) (i + 1);
z[i] = x[i] + y[i];
return;
}
/*
* host main
*/
int main()
{
int i, cudaRtrn;
dim3 thrds_per_block, blcks_per_grid;
float *a, *b, *c;
/*
* Let us make use of cudaMallocManaged() to allocate 3 arrays
* of size 1 GB each for subsequent usage on the GPU.
*/
if (cudaRtrn = cudaMallocManaged(&a, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array a[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = cudaMallocManaged(&b, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array b[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = cudaMallocManaged(&c, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array c[], %d ***\n", cudaRtrn);
}
/*
* next we want to call a simple kernel that sets array elements
* a[] and b[] with thread-specific values and then adds together
* these values and stores back the result into array c[]
*/
thrds_per_block.x = 256;
blcks_per_grid.x = ARRAYDIM / thrds_per_block.x;
KrnlDmmy<<<blcks_per_grid, thrds_per_block>>>(a, b, c);
cudaDeviceSynchronize();
//for (i=0; i<=100; i++) {
// printf("%6d%6.1f%6.1f%6.1f\n", i, a[i], b[i], c[i]);
//}
cudaFree(c);
cudaFree(b);
cudaFree(a);
return(0);
} | /*
* purpose: CUDA managed unified memory for >= pascal architectures;
* this version just uses cudaMallocManaged() on the host,
* then runs a kernel on the GPU to add together two arrays
* of size 1 GB and save the results into a third array;
* result: working great ! when running a loop over 25 attemps with
* 'watch nvidia-smi' open in a background terminal, we see
* Memory-Usage 3185MiB / 8114MiB
* n.b. for visual clarity, the printout section below should be
* commented out when starting to do some profiling runs,
* e.g. nvprof ./a.out
* compilation: nvcc ./unified_memory_example_1.cu
* usage: ./a.out
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define ARRAYDIM 268435456
/*
* GPU kernel working with unified memory which had been
* allocated using cudaMallocManaged() on the host
*/
__global__ void KrnlDmmy(float *x, float *y, float *z)
{
int i;
i = (blockIdx.x * blockDim.x) + threadIdx.x;
x[i] = (float) i;
y[i] = (float) (i + 1);
z[i] = x[i] + y[i];
return;
}
/*
* host main
*/
int main()
{
int i, cudaRtrn;
dim3 thrds_per_block, blcks_per_grid;
float *a, *b, *c;
/*
* Let us make use of cudaMallocManaged() to allocate 3 arrays
* of size 1 GB each for subsequent usage on the GPU.
*/
if (cudaRtrn = hipMallocManaged(&a, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array a[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = hipMallocManaged(&b, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array b[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = hipMallocManaged(&c, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array c[], %d ***\n", cudaRtrn);
}
/*
* next we want to call a simple kernel that sets array elements
* a[] and b[] with thread-specific values and then adds together
* these values and stores back the result into array c[]
*/
thrds_per_block.x = 256;
blcks_per_grid.x = ARRAYDIM / thrds_per_block.x;
KrnlDmmy<<<blcks_per_grid, thrds_per_block>>>(a, b, c);
hipDeviceSynchronize();
//for (i=0; i<=100; i++) {
// printf("%6d%6.1f%6.1f%6.1f\n", i, a[i], b[i], c[i]);
//}
hipFree(c);
hipFree(b);
hipFree(a);
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* purpose: CUDA managed unified memory for >= pascal architectures;
* this version just uses cudaMallocManaged() on the host,
* then runs a kernel on the GPU to add together two arrays
* of size 1 GB and save the results into a third array;
* result: working great ! when running a loop over 25 attemps with
* 'watch nvidia-smi' open in a background terminal, we see
* Memory-Usage 3185MiB / 8114MiB
* n.b. for visual clarity, the printout section below should be
* commented out when starting to do some profiling runs,
* e.g. nvprof ./a.out
* compilation: nvcc ./unified_memory_example_1.cu
* usage: ./a.out
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define ARRAYDIM 268435456
/*
* GPU kernel working with unified memory which had been
* allocated using cudaMallocManaged() on the host
*/
__global__ void KrnlDmmy(float *x, float *y, float *z)
{
int i;
i = (blockIdx.x * blockDim.x) + threadIdx.x;
x[i] = (float) i;
y[i] = (float) (i + 1);
z[i] = x[i] + y[i];
return;
}
/*
* host main
*/
int main()
{
int i, cudaRtrn;
dim3 thrds_per_block, blcks_per_grid;
float *a, *b, *c;
/*
* Let us make use of cudaMallocManaged() to allocate 3 arrays
* of size 1 GB each for subsequent usage on the GPU.
*/
if (cudaRtrn = hipMallocManaged(&a, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array a[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = hipMallocManaged(&b, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array b[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = hipMallocManaged(&c, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array c[], %d ***\n", cudaRtrn);
}
/*
* next we want to call a simple kernel that sets array elements
* a[] and b[] with thread-specific values and then adds together
* these values and stores back the result into array c[]
*/
thrds_per_block.x = 256;
blcks_per_grid.x = ARRAYDIM / thrds_per_block.x;
KrnlDmmy<<<blcks_per_grid, thrds_per_block>>>(a, b, c);
hipDeviceSynchronize();
//for (i=0; i<=100; i++) {
// printf("%6d%6.1f%6.1f%6.1f\n", i, a[i], b[i], c[i]);
//}
hipFree(c);
hipFree(b);
hipFree(a);
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8KrnlDmmyPfS_S_
.globl _Z8KrnlDmmyPfS_S_
.p2align 8
.type _Z8KrnlDmmyPfS_S_,@function
_Z8KrnlDmmyPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, 1, v1
v_cvt_f32_i32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cvt_f32_i32_e32 v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[0:1], v6, off
global_store_b32 v[4:5], v7, off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v7
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8KrnlDmmyPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8KrnlDmmyPfS_S_, .Lfunc_end0-_Z8KrnlDmmyPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8KrnlDmmyPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8KrnlDmmyPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* purpose: CUDA managed unified memory for >= pascal architectures;
* this version just uses cudaMallocManaged() on the host,
* then runs a kernel on the GPU to add together two arrays
* of size 1 GB and save the results into a third array;
* result: working great ! when running a loop over 25 attemps with
* 'watch nvidia-smi' open in a background terminal, we see
* Memory-Usage 3185MiB / 8114MiB
* n.b. for visual clarity, the printout section below should be
* commented out when starting to do some profiling runs,
* e.g. nvprof ./a.out
* compilation: nvcc ./unified_memory_example_1.cu
* usage: ./a.out
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define ARRAYDIM 268435456
/*
* GPU kernel working with unified memory which had been
* allocated using cudaMallocManaged() on the host
*/
__global__ void KrnlDmmy(float *x, float *y, float *z)
{
int i;
i = (blockIdx.x * blockDim.x) + threadIdx.x;
x[i] = (float) i;
y[i] = (float) (i + 1);
z[i] = x[i] + y[i];
return;
}
/*
* host main
*/
int main()
{
int i, cudaRtrn;
dim3 thrds_per_block, blcks_per_grid;
float *a, *b, *c;
/*
* Let us make use of cudaMallocManaged() to allocate 3 arrays
* of size 1 GB each for subsequent usage on the GPU.
*/
if (cudaRtrn = hipMallocManaged(&a, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array a[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = hipMallocManaged(&b, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array b[], %d ***\n", cudaRtrn);
}
if (cudaRtrn = hipMallocManaged(&c, ARRAYDIM * sizeof(float)) != 0) {
printf("*** allocation failed for array c[], %d ***\n", cudaRtrn);
}
/*
* next we want to call a simple kernel that sets array elements
* a[] and b[] with thread-specific values and then adds together
* these values and stores back the result into array c[]
*/
thrds_per_block.x = 256;
blcks_per_grid.x = ARRAYDIM / thrds_per_block.x;
KrnlDmmy<<<blcks_per_grid, thrds_per_block>>>(a, b, c);
hipDeviceSynchronize();
//for (i=0; i<=100; i++) {
// printf("%6d%6.1f%6.1f%6.1f\n", i, a[i], b[i], c[i]);
//}
hipFree(c);
hipFree(b);
hipFree(a);
return(0);
} | .text
.file "unified_memory_example_1.hip"
.globl _Z23__device_stub__KrnlDmmyPfS_S_ # -- Begin function _Z23__device_stub__KrnlDmmyPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__KrnlDmmyPfS_S_,@function
_Z23__device_stub__KrnlDmmyPfS_S_: # @_Z23__device_stub__KrnlDmmyPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8KrnlDmmyPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__KrnlDmmyPfS_S_, .Lfunc_end0-_Z23__device_stub__KrnlDmmyPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl $.L.str, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
.LBB1_2:
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl $.L.str.1, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
.LBB1_4:
movq %rsp, %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $.L.str.2, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
.LBB1_6:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 1048320(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8KrnlDmmyPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8KrnlDmmyPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8KrnlDmmyPfS_S_,@object # @_Z8KrnlDmmyPfS_S_
.section .rodata,"a",@progbits
.globl _Z8KrnlDmmyPfS_S_
.p2align 3, 0x0
_Z8KrnlDmmyPfS_S_:
.quad _Z23__device_stub__KrnlDmmyPfS_S_
.size _Z8KrnlDmmyPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "*** allocation failed for array a[], %d ***\n"
.size .L.str, 45
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "*** allocation failed for array b[], %d ***\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "*** allocation failed for array c[], %d ***\n"
.size .L.str.2, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8KrnlDmmyPfS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__KrnlDmmyPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8KrnlDmmyPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8KrnlDmmyPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x000e220000201400 */
/*0070*/ IADD3 R8, R0.reuse, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x040fe20007ffe0ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ I2F R11, R8 ; /* 0x00000008000b7306 */
/* 0x000e620000201400 */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x001fe8000c101904 */
/*00c0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x002fe8000c101904 */
/*00d0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8KrnlDmmyPfS_S_
.globl _Z8KrnlDmmyPfS_S_
.p2align 8
.type _Z8KrnlDmmyPfS_S_,@function
_Z8KrnlDmmyPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, 1, v1
v_cvt_f32_i32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cvt_f32_i32_e32 v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[0:1], v6, off
global_store_b32 v[4:5], v7, off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v0, v7
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8KrnlDmmyPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8KrnlDmmyPfS_S_, .Lfunc_end0-_Z8KrnlDmmyPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8KrnlDmmyPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8KrnlDmmyPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003936f_00000000-6_unified_memory_example_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
.type _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_, @function
_Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8KrnlDmmyPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_, .-_Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
.globl _Z8KrnlDmmyPfS_S_
.type _Z8KrnlDmmyPfS_S_, @function
_Z8KrnlDmmyPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8KrnlDmmyPfS_S_, .-_Z8KrnlDmmyPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "*** allocation failed for array a[], %d ***\n"
.align 8
.LC1:
.string "*** allocation failed for array b[], %d ***\n"
.align 8
.LC2:
.string "*** allocation failed for array c[], %d ***\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L18
.L12:
leaq 16(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L19
.L13:
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L20
.L14:
movl $1048576, 44(%rsp)
movl $256, 32(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $1, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L19:
movl $1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L20:
movl $1, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8KrnlDmmyPfS_S_PfS_S_
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z8KrnlDmmyPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8KrnlDmmyPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unified_memory_example_1.hip"
.globl _Z23__device_stub__KrnlDmmyPfS_S_ # -- Begin function _Z23__device_stub__KrnlDmmyPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__KrnlDmmyPfS_S_,@function
_Z23__device_stub__KrnlDmmyPfS_S_: # @_Z23__device_stub__KrnlDmmyPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8KrnlDmmyPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__KrnlDmmyPfS_S_, .Lfunc_end0-_Z23__device_stub__KrnlDmmyPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl $.L.str, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
.LBB1_2:
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl $.L.str.1, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
.LBB1_4:
movq %rsp, %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $.L.str.2, %edi
movl $1, %esi
xorl %eax, %eax
callq printf
.LBB1_6:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 1048320(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8KrnlDmmyPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8KrnlDmmyPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8KrnlDmmyPfS_S_,@object # @_Z8KrnlDmmyPfS_S_
.section .rodata,"a",@progbits
.globl _Z8KrnlDmmyPfS_S_
.p2align 3, 0x0
_Z8KrnlDmmyPfS_S_:
.quad _Z23__device_stub__KrnlDmmyPfS_S_
.size _Z8KrnlDmmyPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "*** allocation failed for array a[], %d ***\n"
.size .L.str, 45
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "*** allocation failed for array b[], %d ***\n"
.size .L.str.1, 45
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "*** allocation failed for array c[], %d ***\n"
.size .L.str.2, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8KrnlDmmyPfS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__KrnlDmmyPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8KrnlDmmyPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime_api.h>
#include <chrono>
//#define DEBUG_DEV
#ifdef DEBUG_DEV
#define getErrorCuda(command)\
command;\
cudaDeviceSynchronize();\
cudaThreadSynchronize();\
if (cudaPeekAtLastError() != cudaSuccess){\
std::cout << #command << " : " << cudaGetErrorString(cudaGetLastError())\
<< " in file " << __FILE__ << " at line " << __LINE__ << std::endl;\
exit(1);\
}
#endif
#ifndef DEBUG_DEV
#define getErrorCuda(command) command;
#endif
__constant__ float const_stencilWeight[21];
// base case
__global__ void stencil(float *src, float *dst, int size, float *stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += src[idx+i] * stencilWeight[i+10];
}
dst[idx] = out;
}
// read only cache stencil coefficients
__global__ void stencilReadOnly1(float *src, float *dst, int size, float* stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += src[idx+i] * __ldg(&stencilWeight[i+10]);
}
dst[idx] = out;
}
// read only data
__global__ void stencilReadOnly2(float *src, float *dst, int size, float* stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += __ldg(&src[idx+i]) * stencilWeight[i+10];
}
dst[idx] = out;
}
// read only coefficients and data
__global__ void stencilReadOnly3(float *src, float *dst, int size, float* stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += __ldg(&src[idx+i]) * __ldg(&stencilWeight[i+10]);
}
dst[idx] = out;
}
// constat memory coefficients
__global__ void stencilConst1(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += src[idx+i] * const_stencilWeight[i+10];
}
dst[idx] = out;
}
// constant memory coefficients and data through read only cache
__global__ void stencilConst2(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += __ldg(&src[idx+i]) * const_stencilWeight[i+10];
}
dst[idx] = out;
}
// constant memory coefficients and data from shared
__global__ void stencilShared1(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float buffer[1024+21];
for(int i = threadIdx.x; i < 1024+21; i = i + 1024)
{
buffer[i] = src[idx+i];
}
idx += 11;
if (idx >= size)
return;
__syncthreads();
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += buffer[threadIdx.x+10+i] * const_stencilWeight[i+10];
}
dst[idx] = out;
}
// constant memory coefficients and data from shared thorugh read only
__global__ void stencilShared2(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float buffer[1024+21];
for(int i = threadIdx.x; i < 1024+21; i = i + 1024)
{
buffer[i] = __ldg(&src[idx+i]);
}
idx += 11;
if (idx >= size)
return;
__syncthreads();
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += buffer[threadIdx.x+10+i] * const_stencilWeight[i+10];
}
dst[idx] = out;
}
void verify(float *arr, float *corr, int count)
{
for(int i = 40; i < count; i++)
{
if(arr[i] != corr[i])
{
std::cout << "error verifying resutls" << std::endl;
exit(1);
}
}
}
int main()
{
float *a;
float *b;
float *bOut;
float *bCorr;
float *weights;
getErrorCuda(cudaMalloc(&a, sizeof(float)*102400000));
getErrorCuda(cudaMalloc(&b, sizeof(float)*102400000));
getErrorCuda(cudaMallocHost(&bOut, sizeof(float)*102400000));
getErrorCuda(cudaMallocManaged(&bCorr, sizeof(float)*102400000));
getErrorCuda(cudaMallocManaged(&weights, sizeof(float)*21));
cudaDeviceSynchronize();
for(int i = 0; i < 102400000;i++)
{
//a[i] = 0;
//b[i] = 0;
bCorr[i] = 0;
}
cudaDeviceSynchronize();
int blockSize = 1024;
int blocks = 10000;
for(int i = 0; i < 21;i++)
weights[i] = i-10;
cudaDeviceSynchronize();
cudaMemcpyToSymbol(const_stencilWeight, weights, sizeof(float)*21);
stencil<<<blocks, blockSize>>>(a, bCorr, 10240000-11, weights);
cudaDeviceSynchronize();
stencil<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
cudaDeviceSynchronize();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
cudaSetDevice(0);
float minTime = 10000;
for(int i = 0; i < 100; i++)
{
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencil<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "Non optimized time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
std::cout << std::endl;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilReadOnly1<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "read only cache stencil coefficients time " <<(blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilReadOnly2<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "read only data time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilReadOnly3<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "read only coefficients and data time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
std::cout << std::endl;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilConst1<<<blocks, blockSize>>>(a, b, 10240000);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilConst2<<<blocks, blockSize>>>(a, b, 10240000);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients and data through read only cache time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
std::cout << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilShared1<<<blocks, blockSize>>>(a, b, 10240000);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients and data from shared time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
cudaDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilShared2<<<blocks, blockSize>>>(a, b, 10240000);
cudaDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(cudaMemcpy(bOut, b, sizeof(float)*10240000, cudaMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients and data from shared thorugh read only time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
#include <chrono>
//#define DEBUG_DEV
#ifdef DEBUG_DEV
#define getErrorCuda(command)\
command;\
hipDeviceSynchronize();\
hipDeviceSynchronize();\
if (hipPeekAtLastError() != hipSuccess){\
std::cout << #command << " : " << hipGetErrorString(hipGetLastError())\
<< " in file " << __FILE__ << " at line " << __LINE__ << std::endl;\
exit(1);\
}
#endif
#ifndef DEBUG_DEV
#define getErrorCuda(command) command;
#endif
__constant__ float const_stencilWeight[21];
// base case
__global__ void stencil(float *src, float *dst, int size, float *stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += src[idx+i] * stencilWeight[i+10];
}
dst[idx] = out;
}
// read only cache stencil coefficients
__global__ void stencilReadOnly1(float *src, float *dst, int size, float* stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += src[idx+i] * __ldg(&stencilWeight[i+10]);
}
dst[idx] = out;
}
// read only data
__global__ void stencilReadOnly2(float *src, float *dst, int size, float* stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += __ldg(&src[idx+i]) * stencilWeight[i+10];
}
dst[idx] = out;
}
// read only coefficients and data
__global__ void stencilReadOnly3(float *src, float *dst, int size, float* stencilWeight)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += __ldg(&src[idx+i]) * __ldg(&stencilWeight[i+10]);
}
dst[idx] = out;
}
// constat memory coefficients
__global__ void stencilConst1(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += src[idx+i] * const_stencilWeight[i+10];
}
dst[idx] = out;
}
// constant memory coefficients and data through read only cache
__global__ void stencilConst2(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
idx += 11;
if (idx >= size)
return;
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += __ldg(&src[idx+i]) * const_stencilWeight[i+10];
}
dst[idx] = out;
}
// constant memory coefficients and data from shared
__global__ void stencilShared1(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float buffer[1024+21];
for(int i = threadIdx.x; i < 1024+21; i = i + 1024)
{
buffer[i] = src[idx+i];
}
idx += 11;
if (idx >= size)
return;
__syncthreads();
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += buffer[threadIdx.x+10+i] * const_stencilWeight[i+10];
}
dst[idx] = out;
}
// constant memory coefficients and data from shared thorugh read only
__global__ void stencilShared2(float *src, float *dst, int size)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float buffer[1024+21];
for(int i = threadIdx.x; i < 1024+21; i = i + 1024)
{
buffer[i] = __ldg(&src[idx+i]);
}
idx += 11;
if (idx >= size)
return;
__syncthreads();
float out = 0;
#pragma unroll
for(int i = -10;i <= 10; i++)
{
out += buffer[threadIdx.x+10+i] * const_stencilWeight[i+10];
}
dst[idx] = out;
}
void verify(float *arr, float *corr, int count)
{
for(int i = 40; i < count; i++)
{
if(arr[i] != corr[i])
{
std::cout << "error verifying resutls" << std::endl;
exit(1);
}
}
}
int main()
{
float *a;
float *b;
float *bOut;
float *bCorr;
float *weights;
getErrorCuda(hipMalloc(&a, sizeof(float)*102400000));
getErrorCuda(hipMalloc(&b, sizeof(float)*102400000));
getErrorCuda(hipHostMalloc(&bOut, sizeof(float)*102400000, hipHostMallocDefault));
getErrorCuda(hipMallocManaged(&bCorr, sizeof(float)*102400000));
getErrorCuda(hipMallocManaged(&weights, sizeof(float)*21));
hipDeviceSynchronize();
for(int i = 0; i < 102400000;i++)
{
//a[i] = 0;
//b[i] = 0;
bCorr[i] = 0;
}
hipDeviceSynchronize();
int blockSize = 1024;
int blocks = 10000;
for(int i = 0; i < 21;i++)
weights[i] = i-10;
hipDeviceSynchronize();
hipMemcpyToSymbol(HIP_SYMBOL(const_stencilWeight), weights, sizeof(float)*21);
stencil<<<blocks, blockSize>>>(a, bCorr, 10240000-11, weights);
hipDeviceSynchronize();
stencil<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
hipDeviceSynchronize();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
hipSetDevice(0);
float minTime = 10000;
for(int i = 0; i < 100; i++)
{
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencil<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "Non optimized time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
std::cout << std::endl;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilReadOnly1<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "read only cache stencil coefficients time " <<(blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilReadOnly2<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "read only data time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilReadOnly3<<<blocks, blockSize>>>(a, b, 10240000-11, weights);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "read only coefficients and data time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
std::cout << std::endl;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilConst1<<<blocks, blockSize>>>(a, b, 10240000);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilConst2<<<blocks, blockSize>>>(a, b, 10240000);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients and data through read only cache time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
std::cout << std::endl;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilShared1<<<blocks, blockSize>>>(a, b, 10240000);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients and data from shared time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
minTime = 10000;
for(int i = 0; i < 100; i++)
{
hipDeviceSynchronize();
std::chrono::time_point<std::chrono::system_clock> start, end;
start = std::chrono::system_clock::now();
stencilShared2<<<blocks, blockSize>>>(a, b, 10240000);
hipDeviceSynchronize();
end = std::chrono::system_clock::now();
getErrorCuda(hipMemcpy(bOut, b, sizeof(float)*10240000, hipMemcpyDefault));
verify(bOut, bCorr, 1000);
std::chrono::duration<float> elapsed_seconds = end-start;
minTime = std::min(elapsed_seconds.count(), minTime);
}
std::cout << "constant memory coefficients and data from shared thorugh read only time " << (blockSize*blocks)/minTime << " elem/s" << " Read BW " << (21*blockSize*blocks*sizeof(float)/1000.0/1000.0/1000.0 )/minTime << " GB/s" << std::endl;
minTime = 10000;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //iojpegparts.cu
#include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <jpeglib.h>
#include <sys/time.h>
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int usage(char *name){
printf("Code to blur parts of image using GPUs.\n");
printf("Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n",name);
exit(1);
}
__global__ void GaussianBlurCuda (unsigned char *pic, unsigned char * outpic, double *mask, int *size){ // size: width, height, mask_width
int pxPosCen = blockIdx.x * blockDim.x + threadIdx.x;
if (pxPosCen >= size[0]*size[1] || pxPosCen < 0) return;
int row, col, x, y, pos;
row = pxPosCen/size[0]; // pixel position taken as width major
col = pxPosCen%size[0];
double sumout[3];
sumout[0] = 0;
sumout[1] = 0;
sumout[2] = 0;
if (row < size[2]/2 || row >= (size[1] - (size[2]/2))) return;
if (col < size[2]/2 || col >= (size[0] - (size[2]/2))) return;
for (int i=0;i<size[2]*size[2];i++){
x = i%size[2] + col - size[2]/2;
y = i/size[2] + row - size[2]/2;
pos = (y*size[0] + x)*3;
sumout[0]+=(double)(*(pic+pos )) * mask[i];
sumout[1]+=(double)(*(pic+pos+1)) * mask[i];
sumout[2]+=(double)(*(pic+pos+2)) * mask[i];
}
pos = pxPosCen*3;
*(outpic+pos) = (unsigned char) sumout[0];
*(outpic+pos+1) = (unsigned char) sumout[1];
*(outpic+pos+2) = (unsigned char) sumout[2];
}
int main (int argc, char *argv[]){
if (argc != 5) usage(argv[0]);
int width, height;
char *name = argv[1];
char *out = argv[2];
int mask_width = atoi(argv[3]);
double peak_width = atof(argv[4]);
if (mask_width%2 !=1){
printf("Mask width must be odd.\n");
exit(1);
}
double tStart = cpuSecond();
FILE *infile = fopen(name,"rb");
FILE *outfile = fopen(out,"wb");
if (infile == NULL){
printf("Could not read file\n");
return 1;
}
struct jpeg_decompress_struct cinfo;
struct jpeg_compress_struct cinfo1;
struct jpeg_error_mgr jerr;
JSAMPARRAY pJpegBuffer;
cinfo.err = jpeg_std_error(&jerr);
jpeg_create_decompress(&cinfo);
jpeg_stdio_src(&cinfo, infile);
jpeg_read_header(&cinfo, TRUE);
jpeg_start_decompress(&cinfo);
int row_stride = cinfo.output_width * cinfo.output_components;
width = cinfo.output_width;
height = cinfo.output_height;
unsigned char *pic, *outpic;
pic = (unsigned char *) malloc(width*height*3*sizeof(pic));
outpic = (unsigned char *) malloc(width*height*3*sizeof(outpic));
pJpegBuffer = (*cinfo.mem->alloc_sarray) ((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
while (cinfo.output_scanline < cinfo.output_height) {
(void) jpeg_read_scanlines(&cinfo, pJpegBuffer, 1);
for (int x=0;x<width;x++) {
*(pic++) = pJpegBuffer[0][cinfo.output_components*x];
if (cinfo.output_components>2){
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+1];
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+2];
} else {
*(pic++) = *(pic-1);
*(pic++) = *(pic-1);
}
}
}
pic -= width*height*3;
fclose(infile);
(void) jpeg_finish_decompress(&cinfo);
jpeg_destroy_decompress(&cinfo);
double * mask;
mask = (double *) malloc(mask_width*mask_width*sizeof(mask));
int x,y,xcen=mask_width/2,ycen=xcen;
double a = 1/(peak_width*peak_width * 44/7), sum=0;
for (int i=0;i<mask_width*mask_width;i++){
x = i%mask_width;
y = i/mask_width;
mask[i] = a * exp(-(x-xcen)*(x-xcen)/(2*peak_width*peak_width)
-(y-ycen)*(y-ycen)/(2*peak_width*peak_width));
sum+=mask[i];
}
for (int i=0;i<mask_width*mask_width;i++){
mask[i] /= sum;
}
// CUDA work
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp,0);
size_t gpuGlobalMem = deviceProp.totalGlobalMem;
fprintf(stderr, "GPU global memory = %zu MBytes\n", gpuGlobalMem/(1024*1024));
size_t freeMem, totalMem;
cudaMemGetInfo(&freeMem, &totalMem);
fprintf(stderr, "Free = %zu MB, Total = %zu MB\n", freeMem/(1024*1024), totalMem/(1024*1024));
unsigned char *cudaPic, *cudaOutPic;
double *cudaMask;
int *sizeCuda, size[3];
size[0] = width;
size[1] = height;
size[2] = mask_width;
cudaMalloc((int **)&sizeCuda,3*sizeof(int));
cudaMalloc((unsigned char**)&cudaPic, width*height*3*sizeof(unsigned char));
cudaMalloc((unsigned char**)&cudaOutPic, width*height*3*sizeof(unsigned char));
cudaMalloc((double **)&cudaMask, mask_width*mask_width*sizeof(double));
cudaMemcpy(sizeCuda,size,3*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cudaPic,pic,width*height*3*sizeof(unsigned char),cudaMemcpyHostToDevice);
cudaMemcpy(cudaMask,mask,mask_width*mask_width*sizeof(double),cudaMemcpyHostToDevice);
cudaMemset(cudaOutPic,0,width*height*3*sizeof(unsigned char));
dim3 block (1024);
dim3 grid (((width*height)/block.x)+1);
printf("%d %d\n",block.x, grid.x);
GaussianBlurCuda<<<grid,block>>>(cudaPic, cudaOutPic, cudaMask, sizeCuda);
cudaDeviceSynchronize();
cudaMemcpy(outpic, cudaOutPic, width*height*3*sizeof(unsigned char), cudaMemcpyDeviceToHost);
// Output file structure
cinfo1.err = jpeg_std_error(&jerr);
jpeg_create_compress(&cinfo1);
jpeg_stdio_dest(&cinfo1, outfile);
cinfo1.image_width = width;
cinfo1.image_height = height;
cinfo1.input_components = 3;
cinfo1.in_color_space = JCS_RGB;
jpeg_set_defaults(&cinfo1);
int quality = 70;
jpeg_set_quality(&cinfo1, quality, TRUE);
jpeg_start_compress(&cinfo1, TRUE);
JSAMPROW row_pointer[1];
while(cinfo1.next_scanline < cinfo1.image_height){
row_pointer[0] = &outpic[cinfo1.next_scanline*width*3];
(void) jpeg_write_scanlines(&cinfo1, row_pointer, 1);
}
jpeg_finish_compress(&cinfo1);
fclose(outfile);
jpeg_destroy_compress(&cinfo1);
double tFinish = cpuSecond();
printf("Time elapsed: %lf seconds.\n",tFinish-tStart);
} | code for sm_80
Function : _Z16GaussianBlurCudaPhS_PdPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040604087981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea2000c1e1900 */
/*0080*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000ff1e03f */
/*0090*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*00a0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*00b0*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fe400078e0202 */
/*00c0*/ IMAD R2, R8, R0, RZ ; /* 0x0000000008027224 */
/* 0x004fca00078e02ff */
/*00d0*/ ISETP.GE.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x000fc80003f06270 */
/*00e0*/ ISETP.LT.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000701670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe4000f8e00ff */
/*0110*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x000fca000f8e00ff */
/*0120*/ LDG.E R2, [R4.64+0x4] ; /* 0x0000040604027981 */
/* 0x0000a2000c1e1900 */
/*0130*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fc80000000000 */
/*0140*/ I2F.RP R9, R10 ; /* 0x0000000a00097306 */
/* 0x000e620000209400 */
/*0150*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x001fe40000000000 */
/*0160*/ IABS R5, R3 ; /* 0x0000000300057213 */
/* 0x000fca0000000000 */
/*0170*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e240000001000 */
/*0180*/ IADD3 R6, R9, 0xffffffe, RZ ; /* 0x0ffffffe09067810 */
/* 0x001fe20007ffe0ff */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R4 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0a04 */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*01c0*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*01d0*/ IMAD R11, R11, R10, RZ ; /* 0x0000000a0b0b7224 */
/* 0x000fc800078e02ff */
/*01e0*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*01f0*/ IMAD.HI.U32 R4, R7, R5, RZ ; /* 0x0000000507047227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD R5, R4, R9, R5 ; /* 0x0000000904057224 */
/* 0x000fca00078e0205 */
/*0210*/ ISETP.GT.U32.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f24070 */
/*0220*/ @!P1 IMAD.IADD R5, R5, 0x1, -R10 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a0a */
/*0230*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0250*/ ISETP.GE.U32.AND P0, PT, R5, R10, PT ; /* 0x0000000a0500720c */
/* 0x000fe40003f06070 */
/*0260*/ LOP3.LUT R5, R3, R0, RZ, 0x3c, !PT ; /* 0x0000000003057212 */
/* 0x000fc800078e3cff */
/*0270*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fce0003f46270 */
/*0280*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fcc0007ffe0ff */
/*0290*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*02a0*/ @!P1 LOP3.LUT R4, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff049212 */
/* 0x000fca00078e33ff */
/*02b0*/ IMAD.MOV R6, RZ, RZ, -R4 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a04 */
/*02c0*/ IMAD R6, R0, R6, R3 ; /* 0x0000000600067224 */
/* 0x000fe200078e0203 */
/*02d0*/ LEA.HI R5, R2, R2, RZ, 0x1 ; /* 0x0000000202057211 */
/* 0x004fc800078f08ff */
/*02e0*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc80000011405 */
/*02f0*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe20003f06270 */
/*0300*/ IMAD.IADD R7, R8, 0x1, -R5 ; /* 0x0000000108077824 */
/* 0x000fca00078e0a05 */
/*0310*/ ISETP.GE.OR P0, PT, R4, R7, !P0 ; /* 0x000000070400720c */
/* 0x000fe20004706670 */
/*0320*/ IMAD.IADD R7, R0, 0x1, -R5 ; /* 0x0000000100077824 */
/* 0x000fc600078e0a05 */
/*0330*/ ISETP.LT.OR P0, PT, R6, R5, P0 ; /* 0x000000050600720c */
/* 0x000fc80000701670 */
/*0340*/ ISETP.GE.OR P0, PT, R6, R7, P0 ; /* 0x000000070600720c */
/* 0x000fda0000706670 */
/*0350*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0360*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x000fe200078e02ff */
/*0370*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0380*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0390*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe4000001ff00 */
/*03a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*03b0*/ @!P0 BRA 0x11a0 ; /* 0x00000de000008947 */
/* 0x000fea0003800000 */
/*03c0*/ IADD3 R9, R7.reuse, -0x1, RZ ; /* 0xffffffff07097810 */
/* 0x040fe20007ffe0ff */
/*03d0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*03e0*/ LOP3.LUT R8, R7, 0x3, RZ, 0xc0, !PT ; /* 0x0000000307087812 */
/* 0x000fe200078ec0ff */
/*03f0*/ CS2R R10, SRZ ; /* 0x00000000000a7805 */
/* 0x000fe2000001ff00 */
/*0400*/ ISETP.GE.U32.AND P1, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fe20003f26070 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0420*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0430*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fd4000001ff00 */
/*0440*/ @!P1 BRA 0xe30 ; /* 0x000009e000009947 */
/* 0x000fea0003800000 */
/*0450*/ IABS R28, R2 ; /* 0x00000002001c7213 */
/* 0x000fe20000000000 */
/*0460*/ IMAD.MOV.U32 R30, RZ, RZ, RZ ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e00ff */
/*0470*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0480*/ IMAD.IADD R7, R7, 0x1, -R8 ; /* 0x0000000107077824 */
/* 0x000fe200078e0a08 */
/*0490*/ I2F.RP R15, R28 ; /* 0x0000001c000f7306 */
/* 0x000e220000209400 */
/*04a0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*04b0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0e7624 */
/* 0x000fca00078e00ff */
/*04c0*/ MUFU.RCP R15, R15 ; /* 0x0000000f000f7308 */
/* 0x001e240000001000 */
/*04d0*/ IADD3 R31, R15, 0xffffffe, RZ ; /* 0x0ffffffe0f1f7810 */
/* 0x001fe20007ffe0ff */
/*04e0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0f7624 */
/* 0x000fca00078e00ff */
/*04f0*/ F2I.FTZ.U32.TRUNC.NTZ R31, R31 ; /* 0x0000001f001f7305 */
/* 0x000e24000021f000 */
/*0500*/ IMAD.MOV R17, RZ, RZ, -R31 ; /* 0x000000ffff117224 */
/* 0x001fc800078e0a1f */
/*0510*/ IMAD R17, R17, R28, RZ ; /* 0x0000001c11117224 */
/* 0x000fc800078e02ff */
/*0520*/ IMAD.HI.U32 R30, R31, R17, R30 ; /* 0x000000111f1e7227 */
/* 0x000fc800078e001e */
/*0530*/ IABS R17, R9 ; /* 0x0000000900117213 */
/* 0x001fe40000000000 */
/*0540*/ IABS R16, R2.reuse ; /* 0x0000000200107213 */
/* 0x080fe40000000000 */
/*0550*/ IABS R34, R2.reuse ; /* 0x0000000200227213 */
/* 0x080fe20000000000 */
/*0560*/ IMAD.HI.U32 R30, R30, R17, RZ ; /* 0x000000111e1e7227 */
/* 0x000fe200078e00ff */
/*0570*/ LOP3.LUT R29, RZ, R2.reuse, RZ, 0x33, !PT ; /* 0x00000002ff1d7212 */
/* 0x080fe400078e33ff */
/*0580*/ I2F.RP R20, R34 ; /* 0x0000002200147306 */
/* 0x000e220000209400 */
/*0590*/ IMAD.MOV R33, RZ, RZ, -R16 ; /* 0x000000ffff217224 */
/* 0x000fe200078e0a10 */
/*05a0*/ LOP3.LUT R16, R9, R2, RZ, 0x3c, !PT ; /* 0x0000000209107212 */
/* 0x000fc600078e3cff */
/*05b0*/ IMAD R17, R30, R33, R17 ; /* 0x000000211e117224 */
/* 0x000fe200078e0211 */
/*05c0*/ ISETP.GE.AND P3, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc80003f66270 */
/*05d0*/ ISETP.GT.U32.AND P2, PT, R28, R17, PT ; /* 0x000000111c00720c */
/* 0x000fe20003f44070 */
/*05e0*/ MUFU.RCP R20, R20 ; /* 0x0000001400147308 */
/* 0x001e180000001000 */
/*05f0*/ @!P2 IMAD.IADD R17, R17, 0x1, -R34 ; /* 0x000000011111a824 */
/* 0x000fe200078e0a22 */
/*0600*/ @!P2 IADD3 R30, R30, 0x1, RZ ; /* 0x000000011e1ea810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GE.U32.AND P1, PT, R17, R28, PT ; /* 0x0000001c1100720c */
/* 0x000fda0003f26070 */
/*0620*/ @P1 IADD3 R30, R30, 0x1, RZ ; /* 0x000000011e1e1810 */
/* 0x000fe40007ffe0ff */
/*0630*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f25270 */
/*0640*/ @!P3 IMAD.MOV R30, RZ, RZ, -R30 ; /* 0x000000ffff1eb224 */
/* 0x000fca00078e0a1e */
/*0650*/ SEL R30, R29, R30, !P1 ; /* 0x0000001e1d1e7207 */
/* 0x000fca0004800000 */
/*0660*/ IMAD.MOV R16, RZ, RZ, -R30 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0a1e */
/*0670*/ IADD3 R30, -R5, R30, R4 ; /* 0x0000001e051e7210 */
/* 0x000fc60007ffe104 */
/*0680*/ IMAD R16, R2, R16, R9 ; /* 0x0000001002107224 */
/* 0x000fca00078e0209 */
/*0690*/ IADD3 R17, -R5, R16, R6 ; /* 0x0000001005117210 */
/* 0x000fca0007ffe106 */
/*06a0*/ IMAD R17, R0, R30, R17 ; /* 0x0000001e00117224 */
/* 0x000fe200078e0211 */
/*06b0*/ IADD3 R30, R20, 0xffffffe, RZ ; /* 0x0ffffffe141e7810 */
/* 0x001fc60007ffe0ff */
/*06c0*/ IMAD R17, R17, 0x3, RZ ; /* 0x0000000311117824 */
/* 0x000fe200078e02ff */
/*06d0*/ F2I.FTZ.U32.TRUNC.NTZ R31, R30 ; /* 0x0000001e001f7305 */
/* 0x000e28000021f000 */
/*06e0*/ IADD3 R18, P2, R17, c[0x0][0x160], RZ ; /* 0x0000580011127a10 */
/* 0x000fc80007f5e0ff */
/*06f0*/ LEA.HI.X.SX32 R19, R17, c[0x0][0x164], 0x1, P2 ; /* 0x0000590011137a11 */
/* 0x000fe400010f0eff */
/*0700*/ IADD3 R21, R9, 0x1, RZ ; /* 0x0000000109157810 */
/* 0x000fe20007ffe0ff */
/*0710*/ LDG.E.64 R16, [R14.64] ; /* 0x000000060e107981 */
/* 0x000ea8000c1e1b00 */
/*0720*/ LDG.E.U8 R37, [R18.64] ; /* 0x0000000612257981 */
/* 0x0082e2000c1e1100 */
/*0730*/ IMAD.MOV R23, RZ, RZ, -R31 ; /* 0x000000ffff177224 */
/* 0x001fc600078e0a1f */
/*0740*/ LDG.E.U8 R35, [R18.64+0x2] ; /* 0x0000020612237981 */
/* 0x000322000c1e1100 */
/*0750*/ IMAD R23, R23, R34, RZ ; /* 0x0000002217177224 */
/* 0x000fc600078e02ff */
/*0760*/ LDG.E.U8 R36, [R18.64+0x1] ; /* 0x0000010612247981 */
/* 0x000362000c1e1100 */
/*0770*/ IMAD.MOV.U32 R30, RZ, RZ, RZ ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e00ff */
/*0780*/ IABS R20, R21 ; /* 0x0000001500147213 */
/* 0x000fc60000000000 */
/*0790*/ IMAD.HI.U32 R30, R31, R23, R30 ; /* 0x000000171f1e7227 */
/* 0x000fc800078e001e */
/*07a0*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fc800078e0014 */
/*07b0*/ IMAD.HI.U32 R20, R30, R23, RZ ; /* 0x000000171e147227 */
/* 0x000fc800078e00ff */
/*07c0*/ IMAD R23, R20, R33, R23 ; /* 0x0000002114177224 */
/* 0x000fe400078e0217 */
/*07d0*/ IMAD.MOV.U32 R28, RZ, RZ, R34 ; /* 0x000000ffff1c7224 */
/* 0x000fca00078e0022 */
/*07e0*/ ISETP.GT.U32.AND P3, PT, R28, R23, PT ; /* 0x000000171c00720c */
/* 0x000fe40003f64070 */
/*07f0*/ LOP3.LUT R18, R21, R2, RZ, 0x3c, !PT ; /* 0x0000000215127212 */
/* 0x002fd600078e3cff */
/*0800*/ @!P3 IMAD.IADD R23, R23, 0x1, -R34 ; /* 0x000000011717b824 */
/* 0x000fca00078e0a22 */
/*0810*/ ISETP.GE.U32.AND P2, PT, R23, R28, PT ; /* 0x0000001c1700720c */
/* 0x000fe40003f46070 */
/*0820*/ ISETP.GE.AND P4, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f86270 */
/*0830*/ @!P3 IADD3 R20, R20, 0x1, RZ ; /* 0x000000011414b810 */
/* 0x000fd20007ffe0ff */
/*0840*/ @P2 IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114142810 */
/* 0x000fca0007ffe0ff */
/*0850*/ @!P4 IMAD.MOV R20, RZ, RZ, -R20 ; /* 0x000000ffff14c224 */
/* 0x000fca00078e0a14 */
/*0860*/ SEL R20, R29, R20, !P1 ; /* 0x000000141d147207 */
/* 0x000fca0004800000 */
/*0870*/ IMAD.MOV R18, RZ, RZ, -R20 ; /* 0x000000ffff127224 */
/* 0x000fc800078e0a14 */
/*0880*/ IMAD R21, R2, R18, R21 ; /* 0x0000001202157224 */
/* 0x000fe200078e0215 */
/*0890*/ IADD3 R20, -R5, R20, R4 ; /* 0x0000001405147210 */
/* 0x000fc80007ffe104 */
/*08a0*/ IADD3 R21, -R5, R21, R6 ; /* 0x0000001505157210 */
/* 0x000fca0007ffe106 */
/*08b0*/ IMAD R20, R0, R20, R21 ; /* 0x0000001400147224 */
/* 0x000fc800078e0215 */
/*08c0*/ IMAD R20, R20, 0x3, RZ ; /* 0x0000000314147824 */
/* 0x000fca00078e02ff */
/*08d0*/ IADD3 R18, P2, R20, c[0x0][0x160], RZ ; /* 0x0000580014127a10 */
/* 0x000fc80007f5e0ff */
/*08e0*/ LEA.HI.X.SX32 R19, R20, c[0x0][0x164], 0x1, P2 ; /* 0x0000590014137a11 */
/* 0x000fe400010f0eff */
/*08f0*/ LDG.E.64 R20, [R14.64+0x8] ; /* 0x000008060e147981 */
/* 0x000f68000c1e1b00 */
/*0900*/ LDG.E.U8 R31, [R18.64] ; /* 0x00000006121f7981 */
/* 0x000f68000c1e1100 */
/*0910*/ LDG.E.U8 R32, [R18.64+0x1] ; /* 0x0000010612207981 */
/* 0x000162000c1e1100 */
/*0920*/ I2F.F64.U16 R22, R37 ; /* 0x0000002500167312 */
/* 0x008eb00000101800 */
/*0930*/ I2F.F64.U16 R26, R35 ; /* 0x00000023001a7312 */
/* 0x010e620000101800 */
/*0940*/ DFMA R22, R22, R16, R24 ; /* 0x000000101616722b */
/* 0x004a8e0000000018 */
/*0950*/ I2F.F64.U16 R24, R36 ; /* 0x0000002400187312 */
/* 0x020ee20000101800 */
/*0960*/ DFMA R26, R16.reuse, R26, R12 ; /* 0x0000001a101a722b */
/* 0x0423e4000000000c */
/*0970*/ IADD3 R13, R9.reuse, 0x2, RZ ; /* 0x00000002090d7810 */
/* 0x042fe40007ffe0ff */
/*0980*/ DFMA R24, R16, R24, R10 ; /* 0x000000181018722b */
/* 0x0082e4000000000a */
/*0990*/ IABS R17, R13 ; /* 0x0000000d00117213 */
/* 0x002fe40000000000 */
/*09a0*/ IADD3 R11, R9, 0x3, RZ ; /* 0x00000003090b7810 */
/* 0x000fc60007ffe0ff */
/*09b0*/ IMAD.HI.U32 R12, R30, R17, RZ ; /* 0x000000111e0c7227 */
/* 0x000fe200078e00ff */
/*09c0*/ IABS R37, R11 ; /* 0x0000000b00257213 */
/* 0x000fc60000000000 */
/*09d0*/ IMAD R17, R12, R33, R17 ; /* 0x000000210c117224 */
/* 0x000fe400078e0211 */
/*09e0*/ IMAD.HI.U32 R10, R30, R37, RZ ; /* 0x000000251e0a7227 */
/* 0x000fc600078e00ff */
/*09f0*/ ISETP.GT.U32.AND P5, PT, R28, R17, PT ; /* 0x000000111c00720c */
/* 0x000fe20003fa4070 */
/*0a00*/ IMAD R33, R10, R33, R37 ; /* 0x000000210a217224 */
/* 0x000fca00078e0225 */
/*0a10*/ ISETP.GT.U32.AND P2, PT, R28, R33, PT ; /* 0x000000211c00720c */
/* 0x000fce0003f44070 */
/*0a20*/ @!P5 IMAD.IADD R17, R17, 0x1, -R34 ; /* 0x000000011111d824 */
/* 0x000fe200078e0a22 */
/*0a30*/ LOP3.LUT R16, R13, R2, RZ, 0x3c, !PT ; /* 0x000000020d107212 */
/* 0x000fc800078e3cff */
/*0a40*/ ISETP.GE.U32.AND P3, PT, R17, R28, PT ; /* 0x0000001c1100720c */
/* 0x000fe40003f66070 */
/*0a50*/ ISETP.GE.AND P4, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f86270 */
/*0a60*/ @!P2 IMAD.IADD R33, R33, 0x1, -R34 ; /* 0x000000012121a824 */
/* 0x000fe200078e0a22 */
/*0a70*/ @!P5 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0cd810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ LOP3.LUT R16, R11, R2, RZ, 0x3c, !PT ; /* 0x000000020b107212 */
/* 0x000fe400078e3cff */
/*0a90*/ ISETP.GE.U32.AND P5, PT, R33, R28, PT ; /* 0x0000001c2100720c */
/* 0x000fca0003fa6070 */
/*0aa0*/ @P3 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c3810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ ISETP.GE.AND P3, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fc60003f66270 */
/*0ac0*/ @!P4 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cc224 */
/* 0x000fe200078e0a0c */
/*0ad0*/ @!P2 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0aa810 */
/* 0x000fc80007ffe0ff */
/*0ae0*/ SEL R12, R29, R12, !P1 ; /* 0x0000000c1d0c7207 */
/* 0x000fe40004800000 */
/*0af0*/ @P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a5810 */
/* 0x000fc60007ffe0ff */
/*0b00*/ IMAD.MOV R16, RZ, RZ, -R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a0c */
/*0b10*/ @!P3 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0ab224 */
/* 0x000fe400078e0a0a */
/*0b20*/ IMAD R13, R2, R16, R13 ; /* 0x00000010020d7224 */
/* 0x000fe200078e020d */
/*0b30*/ IADD3 R12, -R5, R12, R4 ; /* 0x0000000c050c7210 */
/* 0x000fe40007ffe104 */
/*0b40*/ SEL R10, R29, R10, !P1 ; /* 0x0000000a1d0a7207 */
/* 0x000fe40004800000 */
/*0b50*/ IADD3 R13, -R5, R13, R6 ; /* 0x0000000d050d7210 */
/* 0x000fe20007ffe106 */
/*0b60*/ LDG.E.U8 R29, [R18.64+0x2] ; /* 0x00000206121d7981 */
/* 0x000124000c1e1100 */
/*0b70*/ IMAD.MOV R17, RZ, RZ, -R10 ; /* 0x000000ffff117224 */
/* 0x000fc400078e0a0a */
/*0b80*/ IMAD R16, R0, R12, R13 ; /* 0x0000000c00107224 */
/* 0x000fe400078e020d */
/*0b90*/ IMAD R11, R2, R17, R11 ; /* 0x00000011020b7224 */
/* 0x000fe400078e020b */
/*0ba0*/ IMAD R16, R16, 0x3, RZ ; /* 0x0000000310107824 */
/* 0x000fe200078e02ff */
/*0bb0*/ IADD3 R17, -R5.reuse, R10, R4 ; /* 0x0000000a05117210 */
/* 0x040fe20007ffe104 */
/*0bc0*/ I2F.F64.U16 R12, R31 ; /* 0x0000001f000c7312 */
/* 0x0002a20000101800 */
/*0bd0*/ IADD3 R11, -R5, R11, R6 ; /* 0x0000000b050b7210 */
/* 0x000fe20007ffe106 */
/*0be0*/ LDG.E.64 R18, [R14.64+0x10] ; /* 0x000010060e127981 */
/* 0x001162000c1e1b00 */
/*0bf0*/ IADD3 R10, P1, R16, c[0x0][0x160], RZ ; /* 0x00005800100a7a10 */
/* 0x000fc60007f3e0ff */
/*0c00*/ IMAD R17, R0, R17, R11 ; /* 0x0000001100117224 */
/* 0x000fe200078e020b */
/*0c10*/ LEA.HI.X.SX32 R11, R16, c[0x0][0x164], 0x1, P1 ; /* 0x00005900100b7a11 */
/* 0x000fc600008f0eff */
/*0c20*/ IMAD R17, R17, 0x3, RZ ; /* 0x0000000311117824 */
/* 0x000fe400078e02ff */
/*0c30*/ LDG.E.U8 R31, [R10.64] ; /* 0x000000060a1f7981 */
/* 0x002f62000c1e1100 */
/*0c40*/ DFMA R22, R12, R20, R22 ; /* 0x000000140c16722b */
/* 0x0042860000000016 */
/*0c50*/ LDG.E.U8 R34, [R10.64+0x1] ; /* 0x000001060a227981 */
/* 0x000ea2000c1e1100 */
/*0c60*/ IADD3 R12, P1, R17, c[0x0][0x160], RZ ; /* 0x00005800110c7a10 */
/* 0x002fc60007f3e0ff */
/*0c70*/ LDG.E.U8 R36, [R10.64+0x2] ; /* 0x000002060a247981 */
/* 0x000ea2000c1e1100 */
/*0c80*/ LEA.HI.X.SX32 R13, R17, c[0x0][0x164], 0x1, P1 ; /* 0x00005900110d7a11 */
/* 0x000fc600008f0eff */
/*0c90*/ LDG.E.64 R16, [R14.64+0x18] ; /* 0x000018060e107981 */
/* 0x0000a8000c1e1b00 */
/*0ca0*/ LDG.E.U8 R35, [R12.64] ; /* 0x000000060c237981 */
/* 0x0002a8000c1e1100 */
/*0cb0*/ LDG.E.U8 R37, [R12.64+0x1] ; /* 0x000001060c257981 */
/* 0x0002a8000c1e1100 */
/*0cc0*/ LDG.E.U8 R12, [R12.64+0x2] ; /* 0x000002060c0c7981 */
/* 0x002ea2000c1e1100 */
/*0cd0*/ I2F.F64.U16 R32, R32 ; /* 0x0000002000207312 */
/* 0x000ee40000101800 */
/*0ce0*/ DFMA R24, R20, R32, R24 ; /* 0x000000201418722b */
/* 0x0088620000000018 */
/*0cf0*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fc80007ffe0ff */
/*0d00*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*0d10*/ IADD3 R14, P2, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x001fe40007f5e0ff */
/*0d20*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*0d30*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e060f */
/*0d40*/ I2F.F64.U16 R32, R29 ; /* 0x0000001d00207312 */
/* 0x010e240000101800 */
/*0d50*/ DFMA R26, R20, R32, R26 ; /* 0x00000020141a722b */
/* 0x001a0c000000001a */
/*0d60*/ I2F.F64.U16 R20, R31 ; /* 0x0000001f00147312 */
/* 0x020ef00000101800 */
/*0d70*/ I2F.F64.U16 R32, R34 ; /* 0x0000002200207312 */
/* 0x004e700000101800 */
/*0d80*/ I2F.F64.U16 R10, R36 ; /* 0x00000024000a7312 */
/* 0x000e220000101800 */
/*0d90*/ DFMA R20, R20, R18, R22 ; /* 0x000000121414722b */
/* 0x0084ce0000000016 */
/*0da0*/ I2F.F64.U16 R34, R35 ; /* 0x0000002300227312 */
/* 0x000ef00000101800 */
/*0db0*/ I2F.F64.U16 R22, R37 ; /* 0x0000002500167312 */
/* 0x004eb00000101800 */
/*0dc0*/ I2F.F64.U16 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x000f220000101800 */
/*0dd0*/ DFMA R32, R18, R32, R24 ; /* 0x000000201220722b */
/* 0x002e880000000018 */
/*0de0*/ DFMA R26, R18, R10, R26 ; /* 0x0000000a121a722b */
/* 0x001f08000000001a */
/*0df0*/ DFMA R24, R34, R16, R20 ; /* 0x000000102218722b */
/* 0x0080480000000014 */
/*0e00*/ DFMA R10, R16, R22, R32 ; /* 0x00000016100a722b */
/* 0x0040880000000020 */
/*0e10*/ DFMA R12, R16, R12, R26 ; /* 0x0000000c100c722b */
/* 0x0100e2000000001a */
/*0e20*/ @P1 BRA 0x530 ; /* 0xfffff70000001947 */
/* 0x006fea000383ffff */
/*0e30*/ @!P0 BRA 0x11a0 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*0e40*/ IABS R7, R2 ; /* 0x0000000200077213 */
/* 0x000fe20000000000 */
/*0e50*/ IMAD.MOV.U32 R22, RZ, RZ, 0x8 ; /* 0x00000008ff167424 */
/* 0x001fe200078e00ff */
/*0e60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0e70*/ I2F.RP R16, R7 ; /* 0x0000000700107306 */
/* 0x000e220000209400 */
/*0e80*/ IMAD.WIDE R22, R9, R22, c[0x0][0x170] ; /* 0x00005c0009167625 */
/* 0x000fe200078e0216 */
/*0e90*/ LOP3.LUT R26, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff1a7212 */
/* 0x000fcc00078e33ff */
/*0ea0*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x001e240000001000 */
/*0eb0*/ IADD3 R14, R16, 0xffffffe, RZ ; /* 0x0ffffffe100e7810 */
/* 0x001fcc0007ffe0ff */
/*0ec0*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x000064000021f000 */
/*0ed0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0ee0*/ IMAD.MOV R18, RZ, RZ, -R15 ; /* 0x000000ffff127224 */
/* 0x002fc800078e0a0f */
/*0ef0*/ IMAD R27, R18, R7, RZ ; /* 0x00000007121b7224 */
/* 0x000fc800078e02ff */
/*0f00*/ IMAD.HI.U32 R27, R15, R27, R14 ; /* 0x0000001b0f1b7227 */
/* 0x000fc800078e000e */
/*0f10*/ IABS R14, R2 ; /* 0x00000002000e7213 */
/* 0x004fe40000000000 */
/*0f20*/ IABS R16, R9 ; /* 0x0000000900107213 */
/* 0x000fc60000000000 */
/*0f30*/ IMAD.MOV R15, RZ, RZ, -R14 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0a0e */
/*0f40*/ IMAD.HI.U32 R14, R27, R16, RZ ; /* 0x000000101b0e7227 */
/* 0x000fc800078e00ff */
/*0f50*/ IMAD R16, R14, R15, R16 ; /* 0x0000000f0e107224 */
/* 0x000fe200078e0210 */
/*0f60*/ IABS R15, R2 ; /* 0x00000002000f7213 */
/* 0x000fc80000000000 */
/*0f70*/ ISETP.GT.U32.AND P2, PT, R7, R16, PT ; /* 0x000000100700720c */
/* 0x000fda0003f44070 */
/*0f80*/ @!P2 IMAD.IADD R16, R16, 0x1, -R15 ; /* 0x000000011010a824 */
/* 0x000fe200078e0a0f */
/*0f90*/ LOP3.LUT R15, R9, R2, RZ, 0x3c, !PT ; /* 0x00000002090f7212 */
/* 0x000fe400078e3cff */
/*0fa0*/ @!P2 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0ea810 */
/* 0x000fe40007ffe0ff */
/*0fb0*/ ISETP.GE.U32.AND P1, PT, R16, R7, PT ; /* 0x000000071000720c */
/* 0x000fe40003f26070 */
/*0fc0*/ ISETP.GE.AND P3, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fd60003f66270 */
/*0fd0*/ @P1 IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e1810 */
/* 0x000fca0007ffe0ff */
/*0fe0*/ @!P3 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0eb224 */
/* 0x000fca00078e0a0e */
/*0ff0*/ SEL R14, R26, R14, !P0 ; /* 0x0000000e1a0e7207 */
/* 0x000fca0004000000 */
/*1000*/ IMAD.MOV R15, RZ, RZ, -R14 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0a0e */
/*1010*/ IADD3 R14, -R5, R14, R4 ; /* 0x0000000e050e7210 */
/* 0x000fc60007ffe104 */
/*1020*/ IMAD R15, R2, R15, R9 ; /* 0x0000000f020f7224 */
/* 0x000fca00078e0209 */
/*1030*/ IADD3 R15, -R5, R15, R6 ; /* 0x0000000f050f7210 */
/* 0x000fca0007ffe106 */
/*1040*/ IMAD R14, R0, R14, R15 ; /* 0x0000000e000e7224 */
/* 0x000fc800078e020f */
/*1050*/ IMAD R14, R14, 0x3, RZ ; /* 0x000000030e0e7824 */
/* 0x000fca00078e02ff */
/*1060*/ IADD3 R28, P1, R14, c[0x0][0x160], RZ ; /* 0x000058000e1c7a10 */
/* 0x000fc80007f3e0ff */
/*1070*/ LEA.HI.X.SX32 R29, R14, c[0x0][0x164], 0x1, P1 ; /* 0x000059000e1d7a11 */
/* 0x000fca00008f0eff */
/*1080*/ LDG.E.U8 R16, [R28.64] ; /* 0x000000061c107981 */
/* 0x000ea8000c1e1100 */
/*1090*/ LDG.E.U8 R18, [R28.64+0x1] ; /* 0x000001061c127981 */
/* 0x000f28000c1e1100 */
/*10a0*/ LDG.E.U8 R20, [R28.64+0x2] ; /* 0x000002061c147981 */
/* 0x000f62000c1e1100 */
/*10b0*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0016 */
/*10c0*/ IMAD.MOV.U32 R15, RZ, RZ, R23 ; /* 0x000000ffff0f7224 */
/* 0x000fcc00078e0017 */
/*10d0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x008ee2000c1e1b00 */
/*10e0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*10f0*/ IADD3 R22, P2, R22, 0x8, RZ ; /* 0x0000000816167810 */
/* 0x000fe40007f5e0ff */
/*1100*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*1110*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe20007ffe0ff */
/*1120*/ IMAD.X R23, RZ, RZ, R23, P2 ; /* 0x000000ffff177224 */
/* 0x000fe200010e0617 */
/*1130*/ I2F.F64.U16 R16, R16 ; /* 0x0000001000107312 */
/* 0x004ef00000101800 */
/*1140*/ I2F.F64.U16 R18, R18 ; /* 0x0000001200127312 */
/* 0x010e300000101800 */
/*1150*/ I2F.F64.U16 R20, R20 ; /* 0x0000001400147312 */
/* 0x022e620000101800 */
/*1160*/ DFMA R24, R16, R14, R24 ; /* 0x0000000e1018722b */
/* 0x0084c80000000018 */
/*1170*/ DFMA R10, R14, R18, R10 ; /* 0x000000120e0a722b */
/* 0x001408000000000a */
/*1180*/ DFMA R12, R14, R20, R12 ; /* 0x000000140e0c722b */
/* 0x002462000000000c */
/*1190*/ @P1 BRA 0xf10 ; /* 0xfffffd7000001947 */
/* 0x009fea000383ffff */
/*11a0*/ F2I.U32.F64.TRUNC R25, R24 ; /* 0x0000001800197311 */
/* 0x000f22000030d000 */
/*11b0*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fca00078e02ff */
/*11c0*/ IADD3 R2, P0, R3.reuse, c[0x0][0x168], RZ ; /* 0x00005a0003027a10 */
/* 0x040fe40007f1e0ff */
/*11d0*/ F2I.U32.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */
/* 0x000f64000030d000 */
/*11e0*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0003037a11 */
/* 0x000fcc00000f0eff */
/*11f0*/ F2I.U32.F64.TRUNC R13, R12 ; /* 0x0000000c000d7311 */
/* 0x00ae62000030d000 */
/*1200*/ STG.E.U8 [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x010fe8000c101106 */
/*1210*/ STG.E.U8 [R2.64+0x1], R11 ; /* 0x0000010b02007986 */
/* 0x020fe8000c101106 */
/*1220*/ STG.E.U8 [R2.64+0x2], R13 ; /* 0x0000020d02007986 */
/* 0x002fe2000c101106 */
/*1230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1240*/ BRA 0x1240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //iojpegparts.cu
#include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <jpeglib.h>
#include <sys/time.h>
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int usage(char *name){
printf("Code to blur parts of image using GPUs.\n");
printf("Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n",name);
exit(1);
}
__global__ void GaussianBlurCuda (unsigned char *pic, unsigned char * outpic, double *mask, int *size){ // size: width, height, mask_width
int pxPosCen = blockIdx.x * blockDim.x + threadIdx.x;
if (pxPosCen >= size[0]*size[1] || pxPosCen < 0) return;
int row, col, x, y, pos;
row = pxPosCen/size[0]; // pixel position taken as width major
col = pxPosCen%size[0];
double sumout[3];
sumout[0] = 0;
sumout[1] = 0;
sumout[2] = 0;
if (row < size[2]/2 || row >= (size[1] - (size[2]/2))) return;
if (col < size[2]/2 || col >= (size[0] - (size[2]/2))) return;
for (int i=0;i<size[2]*size[2];i++){
x = i%size[2] + col - size[2]/2;
y = i/size[2] + row - size[2]/2;
pos = (y*size[0] + x)*3;
sumout[0]+=(double)(*(pic+pos )) * mask[i];
sumout[1]+=(double)(*(pic+pos+1)) * mask[i];
sumout[2]+=(double)(*(pic+pos+2)) * mask[i];
}
pos = pxPosCen*3;
*(outpic+pos) = (unsigned char) sumout[0];
*(outpic+pos+1) = (unsigned char) sumout[1];
*(outpic+pos+2) = (unsigned char) sumout[2];
}
int main (int argc, char *argv[]){
if (argc != 5) usage(argv[0]);
int width, height;
char *name = argv[1];
char *out = argv[2];
int mask_width = atoi(argv[3]);
double peak_width = atof(argv[4]);
if (mask_width%2 !=1){
printf("Mask width must be odd.\n");
exit(1);
}
double tStart = cpuSecond();
FILE *infile = fopen(name,"rb");
FILE *outfile = fopen(out,"wb");
if (infile == NULL){
printf("Could not read file\n");
return 1;
}
struct jpeg_decompress_struct cinfo;
struct jpeg_compress_struct cinfo1;
struct jpeg_error_mgr jerr;
JSAMPARRAY pJpegBuffer;
cinfo.err = jpeg_std_error(&jerr);
jpeg_create_decompress(&cinfo);
jpeg_stdio_src(&cinfo, infile);
jpeg_read_header(&cinfo, TRUE);
jpeg_start_decompress(&cinfo);
int row_stride = cinfo.output_width * cinfo.output_components;
width = cinfo.output_width;
height = cinfo.output_height;
unsigned char *pic, *outpic;
pic = (unsigned char *) malloc(width*height*3*sizeof(pic));
outpic = (unsigned char *) malloc(width*height*3*sizeof(outpic));
pJpegBuffer = (*cinfo.mem->alloc_sarray) ((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
while (cinfo.output_scanline < cinfo.output_height) {
(void) jpeg_read_scanlines(&cinfo, pJpegBuffer, 1);
for (int x=0;x<width;x++) {
*(pic++) = pJpegBuffer[0][cinfo.output_components*x];
if (cinfo.output_components>2){
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+1];
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+2];
} else {
*(pic++) = *(pic-1);
*(pic++) = *(pic-1);
}
}
}
pic -= width*height*3;
fclose(infile);
(void) jpeg_finish_decompress(&cinfo);
jpeg_destroy_decompress(&cinfo);
double * mask;
mask = (double *) malloc(mask_width*mask_width*sizeof(mask));
int x,y,xcen=mask_width/2,ycen=xcen;
double a = 1/(peak_width*peak_width * 44/7), sum=0;
for (int i=0;i<mask_width*mask_width;i++){
x = i%mask_width;
y = i/mask_width;
mask[i] = a * exp(-(x-xcen)*(x-xcen)/(2*peak_width*peak_width)
-(y-ycen)*(y-ycen)/(2*peak_width*peak_width));
sum+=mask[i];
}
for (int i=0;i<mask_width*mask_width;i++){
mask[i] /= sum;
}
// CUDA work
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp,0);
size_t gpuGlobalMem = deviceProp.totalGlobalMem;
fprintf(stderr, "GPU global memory = %zu MBytes\n", gpuGlobalMem/(1024*1024));
size_t freeMem, totalMem;
cudaMemGetInfo(&freeMem, &totalMem);
fprintf(stderr, "Free = %zu MB, Total = %zu MB\n", freeMem/(1024*1024), totalMem/(1024*1024));
unsigned char *cudaPic, *cudaOutPic;
double *cudaMask;
int *sizeCuda, size[3];
size[0] = width;
size[1] = height;
size[2] = mask_width;
cudaMalloc((int **)&sizeCuda,3*sizeof(int));
cudaMalloc((unsigned char**)&cudaPic, width*height*3*sizeof(unsigned char));
cudaMalloc((unsigned char**)&cudaOutPic, width*height*3*sizeof(unsigned char));
cudaMalloc((double **)&cudaMask, mask_width*mask_width*sizeof(double));
cudaMemcpy(sizeCuda,size,3*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cudaPic,pic,width*height*3*sizeof(unsigned char),cudaMemcpyHostToDevice);
cudaMemcpy(cudaMask,mask,mask_width*mask_width*sizeof(double),cudaMemcpyHostToDevice);
cudaMemset(cudaOutPic,0,width*height*3*sizeof(unsigned char));
dim3 block (1024);
dim3 grid (((width*height)/block.x)+1);
printf("%d %d\n",block.x, grid.x);
GaussianBlurCuda<<<grid,block>>>(cudaPic, cudaOutPic, cudaMask, sizeCuda);
cudaDeviceSynchronize();
cudaMemcpy(outpic, cudaOutPic, width*height*3*sizeof(unsigned char), cudaMemcpyDeviceToHost);
// Output file structure
cinfo1.err = jpeg_std_error(&jerr);
jpeg_create_compress(&cinfo1);
jpeg_stdio_dest(&cinfo1, outfile);
cinfo1.image_width = width;
cinfo1.image_height = height;
cinfo1.input_components = 3;
cinfo1.in_color_space = JCS_RGB;
jpeg_set_defaults(&cinfo1);
int quality = 70;
jpeg_set_quality(&cinfo1, quality, TRUE);
jpeg_start_compress(&cinfo1, TRUE);
JSAMPROW row_pointer[1];
while(cinfo1.next_scanline < cinfo1.image_height){
row_pointer[0] = &outpic[cinfo1.next_scanline*width*3];
(void) jpeg_write_scanlines(&cinfo1, row_pointer, 1);
}
jpeg_finish_compress(&cinfo1);
fclose(outfile);
jpeg_destroy_compress(&cinfo1);
double tFinish = cpuSecond();
printf("Time elapsed: %lf seconds.\n",tFinish-tStart);
} | .file "tmpxft_000d80ab_00000000-6_iojpegCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Code to blur parts of image using GPUs.\n"
.align 8
.LC2:
.string "Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n"
.text
.globl _Z5usagePc
.type _Z5usagePc, @function
_Z5usagePc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5usagePc, .-_Z5usagePc
.globl _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
.type _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi, @function
_Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16GaussianBlurCudaPhS_PdPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi, .-_Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
.globl _Z16GaussianBlurCudaPhS_PdPi
.type _Z16GaussianBlurCudaPhS_PdPi, @function
_Z16GaussianBlurCudaPhS_PdPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16GaussianBlurCudaPhS_PdPi, .-_Z16GaussianBlurCudaPhS_PdPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Mask width must be odd.\n"
.LC5:
.string "rb"
.LC6:
.string "wb"
.LC7:
.string "Could not read file\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "GPU global memory = %zu MBytes\n"
.align 8
.LC12:
.string "Free = %zu MB, Total = %zu MB\n"
.section .rodata.str1.1
.LC13:
.string "%d %d\n"
.LC14:
.string "Time elapsed: %lf seconds.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2664, %rsp
.cfi_def_cfa_offset 2720
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 2648(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L41
movq 8(%rsi), %r12
movq 16(%rsi), %rbp
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 48(%rsp)
movl %eax, 88(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movl %r15d, %edx
shrl $31, %edx
movl %r15d, %eax
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, %ebx
cmpl $1, %eax
jne .L42
call _Z9cpuSecondv
movsd %xmm0, 64(%rsp)
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, 40(%rsp)
testq %r14, %r14
je .L43
leaq 192(%rsp), %rdi
call jpeg_std_error@PLT
movq %rax, 960(%rsp)
leaq 960(%rsp), %rbx
movl $656, %edx
movl $80, %esi
movq %rbx, %rdi
call jpeg_CreateDecompress@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
call jpeg_stdio_src@PLT
movl $1, %esi
movq %rbx, %rdi
call jpeg_read_header@PLT
movq %rbx, %rdi
call jpeg_start_decompress@PLT
movl 1096(%rsp), %r12d
movl %r12d, %r13d
imull 1108(%rsp), %r13d
movl 1100(%rsp), %eax
movl %eax, 56(%rsp)
imull %r12d, %eax
movl %eax, 60(%rsp)
leal (%rax,%rax,2), %eax
cltq
movq %rax, 32(%rsp)
leaq 0(,%rax,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, 72(%rsp)
movl $1, %ecx
movl %r13d, %edx
movl $1, %esi
movq %rbx, %rdi
movq 968(%rsp), %rax
call *16(%rax)
movq %rax, %rbx
movl 1100(%rsp), %eax
cmpl %eax, 1128(%rsp)
jnb .L23
leal -1(%r12), %eax
leaq (%rax,%rax,2), %r15
leaq 3(%rax,%rax,2), %r14
leaq 960(%rsp), %r13
jmp .L28
.L41:
movq 2648(%rsp), %rax
subq %fs:40, %rax
jne .L44
movq (%rsi), %rdi
call _Z5usagePc
.L44:
call __stack_chk_fail@PLT
.L42:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L25:
movb %cl, -2(%rax)
.L26:
movb %cl, -1(%rsi)
addq %r9, %rdx
addq $3, %rax
cmpq %r8, %rax
je .L45
.L27:
movq (%rbx), %rcx
movzbl (%rcx,%rdx), %ecx
movq %rax, %rsi
movb %cl, -3(%rax)
cmpl $2, %edi
jle .L25
movq (%rbx), %rcx
movzbl 1(%rcx,%rdx), %ecx
movb %cl, -2(%rax)
movq (%rbx), %rcx
movzbl 2(%rcx,%rdx), %ecx
jmp .L26
.L45:
addq %r14, %rbp
.L24:
movl 1100(%rsp), %eax
cmpl %eax, 1128(%rsp)
jnb .L23
.L28:
movl $1, %edx
movq %rbx, %rsi
movq %r13, %rdi
call jpeg_read_scanlines@PLT
testl %r12d, %r12d
jle .L24
movl 1108(%rsp), %edi
movslq %edi, %r9
leaq 3(%rbp), %rax
leaq 6(%rbp,%r15), %r8
movl $0, %edx
jmp .L27
.L23:
movq 32(%rsp), %rax
subq %rax, %rbp
movq %rbp, 80(%rsp)
movq 8(%rsp), %rdi
call fclose@PLT
leaq 960(%rsp), %rbx
movq %rbx, %rdi
call jpeg_finish_decompress@PLT
movq %rbx, %rdi
call jpeg_destroy_decompress@PLT
movq 48(%rsp), %rbx
movl %ebx, %r14d
imull %ebx, %r14d
movslq %r14d, %r14
leaq 0(,%r14,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %ebp
shrl $31, %ebp
addl %ebx, %ebp
sarl %ebp
movsd 16(%rsp), %xmm7
movapd %xmm7, %xmm0
mulsd %xmm7, %xmm0
mulsd .LC8(%rip), %xmm0
divsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp)
movapd %xmm7, %xmm0
addsd %xmm7, %xmm0
mulsd %xmm7, %xmm0
movsd %xmm0, 16(%rsp)
movl $0, %ebx
movq $0x000000000, 8(%rsp)
movl %r12d, 92(%rsp)
movl 88(%rsp), %r12d
.L29:
movl %ebx, %eax
cltd
idivl %r12d
subl %ebp, %eax
movl %ebp, %ecx
subl %edx, %ecx
subl %ebp, %edx
imull %edx, %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
movsd 16(%rsp), %xmm2
divsd %xmm2, %xmm0
imull %eax, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
call exp@PLT
mulsd 24(%rsp), %xmm0
movsd %xmm0, 0(%r13,%rbx,8)
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rbx
cmpq %rbx, %r14
jne .L29
movl 92(%rsp), %r12d
movq %r13, %rax
leaq (%r15,%r13), %rdx
.L30:
movsd (%rax), %xmm0
divsd 8(%rsp), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L30
leaq 1616(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movq 1904(%rsp), %rcx
shrq $20, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdi
call cudaMemGetInfo@PLT
movq 96(%rsp), %rcx
shrq $20, %rcx
movq 104(%rsp), %r8
shrq $20, %r8
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, 180(%rsp)
movl 56(%rsp), %eax
movl %eax, 184(%rsp)
movl 48(%rsp), %eax
movl %eax, 188(%rsp)
leaq 136(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq 32(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 180(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq 120(%rsp), %rdi
call cudaMemset@PLT
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl 60(%rsp), %ebx
shrl $10, %ebx
addl $1, %ebx
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl %ebx, %ecx
movl $1024, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, 156(%rsp)
movl $1024, 144(%rsp)
movl 152(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 144(%rsp), %rdx
movq 156(%rsp), %rdi
movl 164(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L31:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq 32(%rsp), %rdx
movq 120(%rsp), %rsi
movq 72(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 192(%rsp), %rdi
call jpeg_std_error@PLT
movq %rax, 368(%rsp)
leaq 368(%rsp), %rbx
movl $584, %edx
movl $80, %esi
movq %rbx, %rdi
call jpeg_CreateCompress@PLT
movq 40(%rsp), %rsi
movq %rbx, %rdi
call jpeg_stdio_dest@PLT
movl %r12d, 416(%rsp)
movl 56(%rsp), %eax
movl %eax, 420(%rsp)
movl $3, 424(%rsp)
movl $2, 428(%rsp)
movq %rbx, %rdi
call jpeg_set_defaults@PLT
movl $1, %edx
movl $70, %esi
movq %rbx, %rdi
call jpeg_set_quality@PLT
movl $1, %esi
movq %rbx, %rdi
call jpeg_start_compress@PLT
movl 708(%rsp), %eax
cmpl 420(%rsp), %eax
jnb .L32
leaq 168(%rsp), %rbx
.L33:
imull %r12d, %eax
leal (%rax,%rax,2), %eax
addq %rbp, %rax
movq %rax, 168(%rsp)
leaq 368(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call jpeg_write_scanlines@PLT
movl 708(%rsp), %eax
cmpl 420(%rsp), %eax
jb .L33
.L32:
leaq 368(%rsp), %rbx
movq %rbx, %rdi
call jpeg_finish_compress@PLT
movq 40(%rsp), %rdi
call fclose@PLT
movq %rbx, %rdi
call jpeg_destroy_compress@PLT
call _Z9cpuSecondv
subsd 64(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
.L17:
movq 2648(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl %ebx, %eax
addq $2664, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
jmp .L31
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z16GaussianBlurCudaPhS_PdPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z16GaussianBlurCudaPhS_PdPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC8:
.long 0
.long 1078329344
.align 8
.LC9:
.long 0
.long 1075576832
.align 8
.LC10:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //iojpegparts.cu
#include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <jpeglib.h>
#include <sys/time.h>
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int usage(char *name){
printf("Code to blur parts of image using GPUs.\n");
printf("Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n",name);
exit(1);
}
__global__ void GaussianBlurCuda (unsigned char *pic, unsigned char * outpic, double *mask, int *size){ // size: width, height, mask_width
int pxPosCen = blockIdx.x * blockDim.x + threadIdx.x;
if (pxPosCen >= size[0]*size[1] || pxPosCen < 0) return;
int row, col, x, y, pos;
row = pxPosCen/size[0]; // pixel position taken as width major
col = pxPosCen%size[0];
double sumout[3];
sumout[0] = 0;
sumout[1] = 0;
sumout[2] = 0;
if (row < size[2]/2 || row >= (size[1] - (size[2]/2))) return;
if (col < size[2]/2 || col >= (size[0] - (size[2]/2))) return;
for (int i=0;i<size[2]*size[2];i++){
x = i%size[2] + col - size[2]/2;
y = i/size[2] + row - size[2]/2;
pos = (y*size[0] + x)*3;
sumout[0]+=(double)(*(pic+pos )) * mask[i];
sumout[1]+=(double)(*(pic+pos+1)) * mask[i];
sumout[2]+=(double)(*(pic+pos+2)) * mask[i];
}
pos = pxPosCen*3;
*(outpic+pos) = (unsigned char) sumout[0];
*(outpic+pos+1) = (unsigned char) sumout[1];
*(outpic+pos+2) = (unsigned char) sumout[2];
}
int main (int argc, char *argv[]){
if (argc != 5) usage(argv[0]);
int width, height;
char *name = argv[1];
char *out = argv[2];
int mask_width = atoi(argv[3]);
double peak_width = atof(argv[4]);
if (mask_width%2 !=1){
printf("Mask width must be odd.\n");
exit(1);
}
double tStart = cpuSecond();
FILE *infile = fopen(name,"rb");
FILE *outfile = fopen(out,"wb");
if (infile == NULL){
printf("Could not read file\n");
return 1;
}
struct jpeg_decompress_struct cinfo;
struct jpeg_compress_struct cinfo1;
struct jpeg_error_mgr jerr;
JSAMPARRAY pJpegBuffer;
cinfo.err = jpeg_std_error(&jerr);
jpeg_create_decompress(&cinfo);
jpeg_stdio_src(&cinfo, infile);
jpeg_read_header(&cinfo, TRUE);
jpeg_start_decompress(&cinfo);
int row_stride = cinfo.output_width * cinfo.output_components;
width = cinfo.output_width;
height = cinfo.output_height;
unsigned char *pic, *outpic;
pic = (unsigned char *) malloc(width*height*3*sizeof(pic));
outpic = (unsigned char *) malloc(width*height*3*sizeof(outpic));
pJpegBuffer = (*cinfo.mem->alloc_sarray) ((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
while (cinfo.output_scanline < cinfo.output_height) {
(void) jpeg_read_scanlines(&cinfo, pJpegBuffer, 1);
for (int x=0;x<width;x++) {
*(pic++) = pJpegBuffer[0][cinfo.output_components*x];
if (cinfo.output_components>2){
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+1];
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+2];
} else {
*(pic++) = *(pic-1);
*(pic++) = *(pic-1);
}
}
}
pic -= width*height*3;
fclose(infile);
(void) jpeg_finish_decompress(&cinfo);
jpeg_destroy_decompress(&cinfo);
double * mask;
mask = (double *) malloc(mask_width*mask_width*sizeof(mask));
int x,y,xcen=mask_width/2,ycen=xcen;
double a = 1/(peak_width*peak_width * 44/7), sum=0;
for (int i=0;i<mask_width*mask_width;i++){
x = i%mask_width;
y = i/mask_width;
mask[i] = a * exp(-(x-xcen)*(x-xcen)/(2*peak_width*peak_width)
-(y-ycen)*(y-ycen)/(2*peak_width*peak_width));
sum+=mask[i];
}
for (int i=0;i<mask_width*mask_width;i++){
mask[i] /= sum;
}
// CUDA work
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp,0);
size_t gpuGlobalMem = deviceProp.totalGlobalMem;
fprintf(stderr, "GPU global memory = %zu MBytes\n", gpuGlobalMem/(1024*1024));
size_t freeMem, totalMem;
cudaMemGetInfo(&freeMem, &totalMem);
fprintf(stderr, "Free = %zu MB, Total = %zu MB\n", freeMem/(1024*1024), totalMem/(1024*1024));
unsigned char *cudaPic, *cudaOutPic;
double *cudaMask;
int *sizeCuda, size[3];
size[0] = width;
size[1] = height;
size[2] = mask_width;
cudaMalloc((int **)&sizeCuda,3*sizeof(int));
cudaMalloc((unsigned char**)&cudaPic, width*height*3*sizeof(unsigned char));
cudaMalloc((unsigned char**)&cudaOutPic, width*height*3*sizeof(unsigned char));
cudaMalloc((double **)&cudaMask, mask_width*mask_width*sizeof(double));
cudaMemcpy(sizeCuda,size,3*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(cudaPic,pic,width*height*3*sizeof(unsigned char),cudaMemcpyHostToDevice);
cudaMemcpy(cudaMask,mask,mask_width*mask_width*sizeof(double),cudaMemcpyHostToDevice);
cudaMemset(cudaOutPic,0,width*height*3*sizeof(unsigned char));
dim3 block (1024);
dim3 grid (((width*height)/block.x)+1);
printf("%d %d\n",block.x, grid.x);
GaussianBlurCuda<<<grid,block>>>(cudaPic, cudaOutPic, cudaMask, sizeCuda);
cudaDeviceSynchronize();
cudaMemcpy(outpic, cudaOutPic, width*height*3*sizeof(unsigned char), cudaMemcpyDeviceToHost);
// Output file structure
cinfo1.err = jpeg_std_error(&jerr);
jpeg_create_compress(&cinfo1);
jpeg_stdio_dest(&cinfo1, outfile);
cinfo1.image_width = width;
cinfo1.image_height = height;
cinfo1.input_components = 3;
cinfo1.in_color_space = JCS_RGB;
jpeg_set_defaults(&cinfo1);
int quality = 70;
jpeg_set_quality(&cinfo1, quality, TRUE);
jpeg_start_compress(&cinfo1, TRUE);
JSAMPROW row_pointer[1];
while(cinfo1.next_scanline < cinfo1.image_height){
row_pointer[0] = &outpic[cinfo1.next_scanline*width*3];
(void) jpeg_write_scanlines(&cinfo1, row_pointer, 1);
}
jpeg_finish_compress(&cinfo1);
fclose(outfile);
jpeg_destroy_compress(&cinfo1);
double tFinish = cpuSecond();
printf("Time elapsed: %lf seconds.\n",tFinish-tStart);
} | //iojpegparts.cu
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <jpeglib.h>
#include <sys/time.h>
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int usage(char *name){
printf("Code to blur parts of image using GPUs.\n");
printf("Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n",name);
exit(1);
}
__global__ void GaussianBlurCuda (unsigned char *pic, unsigned char * outpic, double *mask, int *size){ // size: width, height, mask_width
int pxPosCen = blockIdx.x * blockDim.x + threadIdx.x;
if (pxPosCen >= size[0]*size[1] || pxPosCen < 0) return;
int row, col, x, y, pos;
row = pxPosCen/size[0]; // pixel position taken as width major
col = pxPosCen%size[0];
double sumout[3];
sumout[0] = 0;
sumout[1] = 0;
sumout[2] = 0;
if (row < size[2]/2 || row >= (size[1] - (size[2]/2))) return;
if (col < size[2]/2 || col >= (size[0] - (size[2]/2))) return;
for (int i=0;i<size[2]*size[2];i++){
x = i%size[2] + col - size[2]/2;
y = i/size[2] + row - size[2]/2;
pos = (y*size[0] + x)*3;
sumout[0]+=(double)(*(pic+pos )) * mask[i];
sumout[1]+=(double)(*(pic+pos+1)) * mask[i];
sumout[2]+=(double)(*(pic+pos+2)) * mask[i];
}
pos = pxPosCen*3;
*(outpic+pos) = (unsigned char) sumout[0];
*(outpic+pos+1) = (unsigned char) sumout[1];
*(outpic+pos+2) = (unsigned char) sumout[2];
}
int main (int argc, char *argv[]){
if (argc != 5) usage(argv[0]);
int width, height;
char *name = argv[1];
char *out = argv[2];
int mask_width = atoi(argv[3]);
double peak_width = atof(argv[4]);
if (mask_width%2 !=1){
printf("Mask width must be odd.\n");
exit(1);
}
double tStart = cpuSecond();
FILE *infile = fopen(name,"rb");
FILE *outfile = fopen(out,"wb");
if (infile == NULL){
printf("Could not read file\n");
return 1;
}
struct jpeg_decompress_struct cinfo;
struct jpeg_compress_struct cinfo1;
struct jpeg_error_mgr jerr;
JSAMPARRAY pJpegBuffer;
cinfo.err = jpeg_std_error(&jerr);
jpeg_create_decompress(&cinfo);
jpeg_stdio_src(&cinfo, infile);
jpeg_read_header(&cinfo, TRUE);
jpeg_start_decompress(&cinfo);
int row_stride = cinfo.output_width * cinfo.output_components;
width = cinfo.output_width;
height = cinfo.output_height;
unsigned char *pic, *outpic;
pic = (unsigned char *) malloc(width*height*3*sizeof(pic));
outpic = (unsigned char *) malloc(width*height*3*sizeof(outpic));
pJpegBuffer = (*cinfo.mem->alloc_sarray) ((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
while (cinfo.output_scanline < cinfo.output_height) {
(void) jpeg_read_scanlines(&cinfo, pJpegBuffer, 1);
for (int x=0;x<width;x++) {
*(pic++) = pJpegBuffer[0][cinfo.output_components*x];
if (cinfo.output_components>2){
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+1];
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+2];
} else {
*(pic++) = *(pic-1);
*(pic++) = *(pic-1);
}
}
}
pic -= width*height*3;
fclose(infile);
(void) jpeg_finish_decompress(&cinfo);
jpeg_destroy_decompress(&cinfo);
double * mask;
mask = (double *) malloc(mask_width*mask_width*sizeof(mask));
int x,y,xcen=mask_width/2,ycen=xcen;
double a = 1/(peak_width*peak_width * 44/7), sum=0;
for (int i=0;i<mask_width*mask_width;i++){
x = i%mask_width;
y = i/mask_width;
mask[i] = a * exp(-(x-xcen)*(x-xcen)/(2*peak_width*peak_width)
-(y-ycen)*(y-ycen)/(2*peak_width*peak_width));
sum+=mask[i];
}
for (int i=0;i<mask_width*mask_width;i++){
mask[i] /= sum;
}
// CUDA work
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp,0);
size_t gpuGlobalMem = deviceProp.totalGlobalMem;
fprintf(stderr, "GPU global memory = %zu MBytes\n", gpuGlobalMem/(1024*1024));
size_t freeMem, totalMem;
hipMemGetInfo(&freeMem, &totalMem);
fprintf(stderr, "Free = %zu MB, Total = %zu MB\n", freeMem/(1024*1024), totalMem/(1024*1024));
unsigned char *cudaPic, *cudaOutPic;
double *cudaMask;
int *sizeCuda, size[3];
size[0] = width;
size[1] = height;
size[2] = mask_width;
hipMalloc((int **)&sizeCuda,3*sizeof(int));
hipMalloc((unsigned char**)&cudaPic, width*height*3*sizeof(unsigned char));
hipMalloc((unsigned char**)&cudaOutPic, width*height*3*sizeof(unsigned char));
hipMalloc((double **)&cudaMask, mask_width*mask_width*sizeof(double));
hipMemcpy(sizeCuda,size,3*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cudaPic,pic,width*height*3*sizeof(unsigned char),hipMemcpyHostToDevice);
hipMemcpy(cudaMask,mask,mask_width*mask_width*sizeof(double),hipMemcpyHostToDevice);
hipMemset(cudaOutPic,0,width*height*3*sizeof(unsigned char));
dim3 block (1024);
dim3 grid (((width*height)/block.x)+1);
printf("%d %d\n",block.x, grid.x);
GaussianBlurCuda<<<grid,block>>>(cudaPic, cudaOutPic, cudaMask, sizeCuda);
hipDeviceSynchronize();
hipMemcpy(outpic, cudaOutPic, width*height*3*sizeof(unsigned char), hipMemcpyDeviceToHost);
// Output file structure
cinfo1.err = jpeg_std_error(&jerr);
jpeg_create_compress(&cinfo1);
jpeg_stdio_dest(&cinfo1, outfile);
cinfo1.image_width = width;
cinfo1.image_height = height;
cinfo1.input_components = 3;
cinfo1.in_color_space = JCS_RGB;
jpeg_set_defaults(&cinfo1);
int quality = 70;
jpeg_set_quality(&cinfo1, quality, TRUE);
jpeg_start_compress(&cinfo1, TRUE);
JSAMPROW row_pointer[1];
while(cinfo1.next_scanline < cinfo1.image_height){
row_pointer[0] = &outpic[cinfo1.next_scanline*width*3];
(void) jpeg_write_scanlines(&cinfo1, row_pointer, 1);
}
jpeg_finish_compress(&cinfo1);
fclose(outfile);
jpeg_destroy_compress(&cinfo1);
double tFinish = cpuSecond();
printf("Time elapsed: %lf seconds.\n",tFinish-tStart);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //iojpegparts.cu
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <jpeglib.h>
#include <sys/time.h>
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int usage(char *name){
printf("Code to blur parts of image using GPUs.\n");
printf("Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n",name);
exit(1);
}
__global__ void GaussianBlurCuda (unsigned char *pic, unsigned char * outpic, double *mask, int *size){ // size: width, height, mask_width
int pxPosCen = blockIdx.x * blockDim.x + threadIdx.x;
if (pxPosCen >= size[0]*size[1] || pxPosCen < 0) return;
int row, col, x, y, pos;
row = pxPosCen/size[0]; // pixel position taken as width major
col = pxPosCen%size[0];
double sumout[3];
sumout[0] = 0;
sumout[1] = 0;
sumout[2] = 0;
if (row < size[2]/2 || row >= (size[1] - (size[2]/2))) return;
if (col < size[2]/2 || col >= (size[0] - (size[2]/2))) return;
for (int i=0;i<size[2]*size[2];i++){
x = i%size[2] + col - size[2]/2;
y = i/size[2] + row - size[2]/2;
pos = (y*size[0] + x)*3;
sumout[0]+=(double)(*(pic+pos )) * mask[i];
sumout[1]+=(double)(*(pic+pos+1)) * mask[i];
sumout[2]+=(double)(*(pic+pos+2)) * mask[i];
}
pos = pxPosCen*3;
*(outpic+pos) = (unsigned char) sumout[0];
*(outpic+pos+1) = (unsigned char) sumout[1];
*(outpic+pos+2) = (unsigned char) sumout[2];
}
int main (int argc, char *argv[]){
if (argc != 5) usage(argv[0]);
int width, height;
char *name = argv[1];
char *out = argv[2];
int mask_width = atoi(argv[3]);
double peak_width = atof(argv[4]);
if (mask_width%2 !=1){
printf("Mask width must be odd.\n");
exit(1);
}
double tStart = cpuSecond();
FILE *infile = fopen(name,"rb");
FILE *outfile = fopen(out,"wb");
if (infile == NULL){
printf("Could not read file\n");
return 1;
}
struct jpeg_decompress_struct cinfo;
struct jpeg_compress_struct cinfo1;
struct jpeg_error_mgr jerr;
JSAMPARRAY pJpegBuffer;
cinfo.err = jpeg_std_error(&jerr);
jpeg_create_decompress(&cinfo);
jpeg_stdio_src(&cinfo, infile);
jpeg_read_header(&cinfo, TRUE);
jpeg_start_decompress(&cinfo);
int row_stride = cinfo.output_width * cinfo.output_components;
width = cinfo.output_width;
height = cinfo.output_height;
unsigned char *pic, *outpic;
pic = (unsigned char *) malloc(width*height*3*sizeof(pic));
outpic = (unsigned char *) malloc(width*height*3*sizeof(outpic));
pJpegBuffer = (*cinfo.mem->alloc_sarray) ((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
while (cinfo.output_scanline < cinfo.output_height) {
(void) jpeg_read_scanlines(&cinfo, pJpegBuffer, 1);
for (int x=0;x<width;x++) {
*(pic++) = pJpegBuffer[0][cinfo.output_components*x];
if (cinfo.output_components>2){
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+1];
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+2];
} else {
*(pic++) = *(pic-1);
*(pic++) = *(pic-1);
}
}
}
pic -= width*height*3;
fclose(infile);
(void) jpeg_finish_decompress(&cinfo);
jpeg_destroy_decompress(&cinfo);
double * mask;
mask = (double *) malloc(mask_width*mask_width*sizeof(mask));
int x,y,xcen=mask_width/2,ycen=xcen;
double a = 1/(peak_width*peak_width * 44/7), sum=0;
for (int i=0;i<mask_width*mask_width;i++){
x = i%mask_width;
y = i/mask_width;
mask[i] = a * exp(-(x-xcen)*(x-xcen)/(2*peak_width*peak_width)
-(y-ycen)*(y-ycen)/(2*peak_width*peak_width));
sum+=mask[i];
}
for (int i=0;i<mask_width*mask_width;i++){
mask[i] /= sum;
}
// CUDA work
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp,0);
size_t gpuGlobalMem = deviceProp.totalGlobalMem;
fprintf(stderr, "GPU global memory = %zu MBytes\n", gpuGlobalMem/(1024*1024));
size_t freeMem, totalMem;
hipMemGetInfo(&freeMem, &totalMem);
fprintf(stderr, "Free = %zu MB, Total = %zu MB\n", freeMem/(1024*1024), totalMem/(1024*1024));
unsigned char *cudaPic, *cudaOutPic;
double *cudaMask;
int *sizeCuda, size[3];
size[0] = width;
size[1] = height;
size[2] = mask_width;
hipMalloc((int **)&sizeCuda,3*sizeof(int));
hipMalloc((unsigned char**)&cudaPic, width*height*3*sizeof(unsigned char));
hipMalloc((unsigned char**)&cudaOutPic, width*height*3*sizeof(unsigned char));
hipMalloc((double **)&cudaMask, mask_width*mask_width*sizeof(double));
hipMemcpy(sizeCuda,size,3*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cudaPic,pic,width*height*3*sizeof(unsigned char),hipMemcpyHostToDevice);
hipMemcpy(cudaMask,mask,mask_width*mask_width*sizeof(double),hipMemcpyHostToDevice);
hipMemset(cudaOutPic,0,width*height*3*sizeof(unsigned char));
dim3 block (1024);
dim3 grid (((width*height)/block.x)+1);
printf("%d %d\n",block.x, grid.x);
GaussianBlurCuda<<<grid,block>>>(cudaPic, cudaOutPic, cudaMask, sizeCuda);
hipDeviceSynchronize();
hipMemcpy(outpic, cudaOutPic, width*height*3*sizeof(unsigned char), hipMemcpyDeviceToHost);
// Output file structure
cinfo1.err = jpeg_std_error(&jerr);
jpeg_create_compress(&cinfo1);
jpeg_stdio_dest(&cinfo1, outfile);
cinfo1.image_width = width;
cinfo1.image_height = height;
cinfo1.input_components = 3;
cinfo1.in_color_space = JCS_RGB;
jpeg_set_defaults(&cinfo1);
int quality = 70;
jpeg_set_quality(&cinfo1, quality, TRUE);
jpeg_start_compress(&cinfo1, TRUE);
JSAMPROW row_pointer[1];
while(cinfo1.next_scanline < cinfo1.image_height){
row_pointer[0] = &outpic[cinfo1.next_scanline*width*3];
(void) jpeg_write_scanlines(&cinfo1, row_pointer, 1);
}
jpeg_finish_compress(&cinfo1);
fclose(outfile);
jpeg_destroy_compress(&cinfo1);
double tFinish = cpuSecond();
printf("Time elapsed: %lf seconds.\n",tFinish-tStart);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16GaussianBlurCudaPhS_PdPi
.globl _Z16GaussianBlurCudaPhS_PdPi
.p2align 8
.type _Z16GaussianBlurCudaPhS_PdPi,@function
_Z16GaussianBlurCudaPhS_PdPi:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[6:7], 0x0
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_lt_i32_e64 s2, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s8, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s8, v0
s_load_b32 s8, s[6:7], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s8, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_hi_u32 v0, v4, v0
s_add_i32 s2, s8, s2
s_ashr_i32 s11, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_sub_i32 s2, s5, s11
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_cmp_le_i32_e32 vcc_lo, s11, v0
v_cmp_gt_i32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v2, v0, s4
s_sub_i32 s2, s4, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v1, v2
v_cmp_le_i32_e32 vcc_lo, s11, v4
v_cmp_gt_i32_e64 s2, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s8, 0
s_mov_b32 s5, 0
s_cbranch_scc1 .LBB0_7
s_ashr_i32 s9, s8, 31
v_subrev_nc_u32_e32 v0, s11, v0
s_add_i32 s2, s8, s9
v_subrev_nc_u32_e32 v8, s11, v4
s_xor_b32 s10, s2, s9
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x10
v_cvt_f32_u32_e32 v2, s10
s_mul_i32 s12, s8, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_max_u32 s11, s12, 1
s_sub_i32 s12, 0, s10
v_rcp_iflag_f32_e32 v5, v2
v_mov_b32_e32 v2, 0
s_waitcnt_depctr 0xfff
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v6, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
v_cvt_u32_f32_e32 v9, v6
v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s13, v9
s_mul_i32 s14, s12, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s14, s13, s14
s_add_i32 s13, s13, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s13, s5, s13
s_mul_i32 s14, s13, s10
s_add_i32 s15, s13, 1
s_sub_i32 s14, s5, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s16, s14, s10
s_cmp_ge_u32 s14, s10
s_cselect_b32 s13, s15, s13
s_cselect_b32 s14, s16, s14
s_add_i32 s15, s13, 1
s_cmp_ge_u32 s14, s10
s_cselect_b32 s13, s15, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s13, s13, s9
s_sub_i32 s13, s13, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v10, s13, v0
s_mul_i32 s13, s13, s8
v_mul_lo_u32 v10, v10, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v10, s13, v10
v_add3_u32 v10, v8, s5, v10
s_add_i32 s5, s5, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v10, v10, 1, v10
v_ashrrev_i32_e32 v11, 31, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
s_clause 0x2
global_load_u8 v12, v[10:11], off
global_load_u8 v13, v[10:11], off offset:1
global_load_u8 v14, v[10:11], off offset:2
s_load_b64 s[14:15], s[6:7], 0x0
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s11, s5
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[10:11], v12
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[12:13], v13
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[14:15], v14
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[2:3], s[14:15], v[10:11], v[2:3]
v_fma_f64 v[4:5], s[14:15], v[12:13], v[4:5]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[6:7], s[14:15], v[14:15], v[6:7]
s_cbranch_scc0 .LBB0_5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f64_e32 v2, v[2:3]
v_cvt_i32_f64_e32 v3, v[4:5]
s_delay_alu instid0(VALU_DEP_3)
v_cvt_i32_f64_e32 v5, v[6:7]
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v3, off offset:1
global_store_b8 v[0:1], v5, off offset:2
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16GaussianBlurCudaPhS_PdPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16GaussianBlurCudaPhS_PdPi, .Lfunc_end0-_Z16GaussianBlurCudaPhS_PdPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16GaussianBlurCudaPhS_PdPi
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z16GaussianBlurCudaPhS_PdPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //iojpegparts.cu
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <jpeglib.h>
#include <sys/time.h>
double cpuSecond(){
struct timeval tp;
gettimeofday(&tp,NULL);
return((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
int usage(char *name){
printf("Code to blur parts of image using GPUs.\n");
printf("Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n",name);
exit(1);
}
__global__ void GaussianBlurCuda (unsigned char *pic, unsigned char * outpic, double *mask, int *size){ // size: width, height, mask_width
int pxPosCen = blockIdx.x * blockDim.x + threadIdx.x;
if (pxPosCen >= size[0]*size[1] || pxPosCen < 0) return;
int row, col, x, y, pos;
row = pxPosCen/size[0]; // pixel position taken as width major
col = pxPosCen%size[0];
double sumout[3];
sumout[0] = 0;
sumout[1] = 0;
sumout[2] = 0;
if (row < size[2]/2 || row >= (size[1] - (size[2]/2))) return;
if (col < size[2]/2 || col >= (size[0] - (size[2]/2))) return;
for (int i=0;i<size[2]*size[2];i++){
x = i%size[2] + col - size[2]/2;
y = i/size[2] + row - size[2]/2;
pos = (y*size[0] + x)*3;
sumout[0]+=(double)(*(pic+pos )) * mask[i];
sumout[1]+=(double)(*(pic+pos+1)) * mask[i];
sumout[2]+=(double)(*(pic+pos+2)) * mask[i];
}
pos = pxPosCen*3;
*(outpic+pos) = (unsigned char) sumout[0];
*(outpic+pos+1) = (unsigned char) sumout[1];
*(outpic+pos+2) = (unsigned char) sumout[2];
}
int main (int argc, char *argv[]){
if (argc != 5) usage(argv[0]);
int width, height;
char *name = argv[1];
char *out = argv[2];
int mask_width = atoi(argv[3]);
double peak_width = atof(argv[4]);
if (mask_width%2 !=1){
printf("Mask width must be odd.\n");
exit(1);
}
double tStart = cpuSecond();
FILE *infile = fopen(name,"rb");
FILE *outfile = fopen(out,"wb");
if (infile == NULL){
printf("Could not read file\n");
return 1;
}
struct jpeg_decompress_struct cinfo;
struct jpeg_compress_struct cinfo1;
struct jpeg_error_mgr jerr;
JSAMPARRAY pJpegBuffer;
cinfo.err = jpeg_std_error(&jerr);
jpeg_create_decompress(&cinfo);
jpeg_stdio_src(&cinfo, infile);
jpeg_read_header(&cinfo, TRUE);
jpeg_start_decompress(&cinfo);
int row_stride = cinfo.output_width * cinfo.output_components;
width = cinfo.output_width;
height = cinfo.output_height;
unsigned char *pic, *outpic;
pic = (unsigned char *) malloc(width*height*3*sizeof(pic));
outpic = (unsigned char *) malloc(width*height*3*sizeof(outpic));
pJpegBuffer = (*cinfo.mem->alloc_sarray) ((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
while (cinfo.output_scanline < cinfo.output_height) {
(void) jpeg_read_scanlines(&cinfo, pJpegBuffer, 1);
for (int x=0;x<width;x++) {
*(pic++) = pJpegBuffer[0][cinfo.output_components*x];
if (cinfo.output_components>2){
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+1];
*(pic++) = pJpegBuffer[0][cinfo.output_components*x+2];
} else {
*(pic++) = *(pic-1);
*(pic++) = *(pic-1);
}
}
}
pic -= width*height*3;
fclose(infile);
(void) jpeg_finish_decompress(&cinfo);
jpeg_destroy_decompress(&cinfo);
double * mask;
mask = (double *) malloc(mask_width*mask_width*sizeof(mask));
int x,y,xcen=mask_width/2,ycen=xcen;
double a = 1/(peak_width*peak_width * 44/7), sum=0;
for (int i=0;i<mask_width*mask_width;i++){
x = i%mask_width;
y = i/mask_width;
mask[i] = a * exp(-(x-xcen)*(x-xcen)/(2*peak_width*peak_width)
-(y-ycen)*(y-ycen)/(2*peak_width*peak_width));
sum+=mask[i];
}
for (int i=0;i<mask_width*mask_width;i++){
mask[i] /= sum;
}
// CUDA work
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp,0);
size_t gpuGlobalMem = deviceProp.totalGlobalMem;
fprintf(stderr, "GPU global memory = %zu MBytes\n", gpuGlobalMem/(1024*1024));
size_t freeMem, totalMem;
hipMemGetInfo(&freeMem, &totalMem);
fprintf(stderr, "Free = %zu MB, Total = %zu MB\n", freeMem/(1024*1024), totalMem/(1024*1024));
unsigned char *cudaPic, *cudaOutPic;
double *cudaMask;
int *sizeCuda, size[3];
size[0] = width;
size[1] = height;
size[2] = mask_width;
hipMalloc((int **)&sizeCuda,3*sizeof(int));
hipMalloc((unsigned char**)&cudaPic, width*height*3*sizeof(unsigned char));
hipMalloc((unsigned char**)&cudaOutPic, width*height*3*sizeof(unsigned char));
hipMalloc((double **)&cudaMask, mask_width*mask_width*sizeof(double));
hipMemcpy(sizeCuda,size,3*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(cudaPic,pic,width*height*3*sizeof(unsigned char),hipMemcpyHostToDevice);
hipMemcpy(cudaMask,mask,mask_width*mask_width*sizeof(double),hipMemcpyHostToDevice);
hipMemset(cudaOutPic,0,width*height*3*sizeof(unsigned char));
dim3 block (1024);
dim3 grid (((width*height)/block.x)+1);
printf("%d %d\n",block.x, grid.x);
GaussianBlurCuda<<<grid,block>>>(cudaPic, cudaOutPic, cudaMask, sizeCuda);
hipDeviceSynchronize();
hipMemcpy(outpic, cudaOutPic, width*height*3*sizeof(unsigned char), hipMemcpyDeviceToHost);
// Output file structure
cinfo1.err = jpeg_std_error(&jerr);
jpeg_create_compress(&cinfo1);
jpeg_stdio_dest(&cinfo1, outfile);
cinfo1.image_width = width;
cinfo1.image_height = height;
cinfo1.input_components = 3;
cinfo1.in_color_space = JCS_RGB;
jpeg_set_defaults(&cinfo1);
int quality = 70;
jpeg_set_quality(&cinfo1, quality, TRUE);
jpeg_start_compress(&cinfo1, TRUE);
JSAMPROW row_pointer[1];
while(cinfo1.next_scanline < cinfo1.image_height){
row_pointer[0] = &outpic[cinfo1.next_scanline*width*3];
(void) jpeg_write_scanlines(&cinfo1, row_pointer, 1);
}
jpeg_finish_compress(&cinfo1);
fclose(outfile);
jpeg_destroy_compress(&cinfo1);
double tFinish = cpuSecond();
printf("Time elapsed: %lf seconds.\n",tFinish-tStart);
} | .text
.file "iojpegCUDA.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z5usagePc # -- Begin function _Z5usagePc
.p2align 4, 0x90
.type _Z5usagePc,@function
_Z5usagePc: # @_Z5usagePc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z5usagePc, .Lfunc_end1-_Z5usagePc
.cfi_endproc
# -- End function
.globl _Z31__device_stub__GaussianBlurCudaPhS_PdPi # -- Begin function _Z31__device_stub__GaussianBlurCudaPhS_PdPi
.p2align 4, 0x90
.type _Z31__device_stub__GaussianBlurCudaPhS_PdPi,@function
_Z31__device_stub__GaussianBlurCudaPhS_PdPi: # @_Z31__device_stub__GaussianBlurCudaPhS_PdPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16GaussianBlurCudaPhS_PdPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z31__device_stub__GaussianBlurCudaPhS_PdPi, .Lfunc_end2-_Z31__device_stub__GaussianBlurCudaPhS_PdPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI3_1:
.quad 0x4046000000000000 # double 44
.LCPI3_2:
.quad 0x401c000000000000 # double 7
.LCPI3_3:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $3128, %rsp # imm = 0xC38
.cfi_def_cfa_offset 3184
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $5, %edi
jne .LBB3_26
# %bb.1:
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl %r12d, %eax
andl $-2147483647, %eax # imm = 0x80000001
cmpl $1, %eax
jne .LBB3_27
# %bb.2:
movq 8(%rbx), %r14
movq 16(%rbx), %r15
leaq 1656(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 1656(%rsp), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 1664(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.3, %esi
movq %r14, %rdi
callq fopen
movq %rax, %rbx
movl $.L.str.4, %esi
movq %r15, %rdi
callq fopen
testq %rbx, %rbx
jne .LBB3_4
# %bb.3:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %ebx
.LBB3_25:
movl %ebx, %eax
addq $3128, %rsp # imm = 0xC38
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_4:
.cfi_def_cfa_offset 3184
movq %r12, 8(%rsp) # 8-byte Spill
movq %rax, 56(%rsp) # 8-byte Spill
leaq 1488(%rsp), %rdi
callq jpeg_std_error
movq %rax, 832(%rsp)
leaq 832(%rsp), %r12
movl $656, %edx # imm = 0x290
movq %r12, %rdi
movl $80, %esi
callq jpeg_CreateDecompress
movq %r12, %rdi
movq %rbx, %rsi
callq jpeg_stdio_src
movq %r12, %rdi
movl $1, %esi
callq jpeg_read_header
movq %r12, %rdi
callq jpeg_start_decompress
movl 968(%rsp), %r14d
movl 972(%rsp), %eax
movl 980(%rsp), %r13d
imull %r14d, %r13d
movl %eax, 36(%rsp) # 4-byte Spill
# kill: def $eax killed $eax def $rax
imull %r14d, %eax
movq %rax, 128(%rsp) # 8-byte Spill
leal (%rax,%rax,2), %eax
cltq
movq %rax, 136(%rsp) # 8-byte Spill
leaq (,%rax,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbp
movq %r15, %rdi
callq malloc
movq %rax, 144(%rsp) # 8-byte Spill
movq 840(%rsp), %rax
movq %r12, %rdi
movl $1, %esi
movl %r13d, %edx
movl $1, %ecx
callq *16(%rax)
movq %rax, %r15
movl 1000(%rsp), %eax
cmpl 972(%rsp), %eax
jae .LBB3_13
# %bb.5:
leaq 832(%rsp), %r13
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_6: # %.loopexit
# in Loop: Header=BB3_7 Depth=1
movl 1000(%rsp), %eax
cmpl 972(%rsp), %eax
jae .LBB3_13
.LBB3_7: # =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
movq %r13, %rdi
movq %r15, %rsi
movl $1, %edx
callq jpeg_read_scanlines
testl %r14d, %r14d
jle .LBB3_6
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB3_7 Depth=1
xorl %eax, %eax
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_9 Depth=2
movb %sil, 1(%rbp)
movb %sil, 2(%rbp)
.LBB3_12: # in Loop: Header=BB3_9 Depth=2
addq $3, %rbp
incl %eax
cmpl %eax, %r14d
je .LBB3_6
.LBB3_9: # %.lr.ph
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r15), %rdx
movslq 980(%rsp), %rsi
movslq %eax, %rcx
imulq %rcx, %rsi
movzbl (%rdx,%rsi), %esi
movb %sil, (%rbp)
movl 980(%rsp), %edx
cmpl $3, %edx
jl .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=2
movq (%r15), %rsi
imull %eax, %edx
movzbl 1(%rsi,%rdx), %edx
movb %dl, 1(%rbp)
movq (%r15), %rdx
movslq 980(%rsp), %rsi
imulq %rcx, %rsi
movzbl 2(%rdx,%rsi), %ecx
movb %cl, 2(%rbp)
jmp .LBB3_12
.LBB3_13: # %._crit_edge
movq %rbx, %rdi
callq fclose
leaq 832(%rsp), %rbx
movq %rbx, %rdi
callq jpeg_finish_decompress
movq %rbx, %rdi
callq jpeg_destroy_decompress
movq 8(%rsp), %r12 # 8-byte Reload
movl %r12d, %r15d
imull %r15d, %r15d
leaq (,%r15,8), %rdi
movq %rdi, 120(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
xorpd %xmm1, %xmm1
movl %r15d, %r13d
testl %r12d, %r12d
je .LBB3_16
# %bb.14: # %.lr.ph139
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %r12d
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
shrl %r12d
movsd .LCPI3_3(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm0, %xmm2
movsd %xmm2, 168(%rsp) # 8-byte Spill
movapd %xmm1, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
xorpd %xmm1, %xmm1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_15: # =>This Inner Loop Header: Depth=1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movl %r15d, %eax
xorl %edx, %edx
divl 8(%rsp) # 4-byte Folded Reload
subl %r12d, %edx
imull %edx, %edx
negl %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd 160(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
divsd %xmm2, %xmm0
subl %r12d, %eax
imull %eax, %eax
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
callq exp
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd 168(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r15,8)
addsd %xmm0, %xmm1
incq %r15
cmpq %r15, %r13
jne .LBB3_15
.LBB3_16: # %.preheader
movq 136(%rsp), %r15 # 8-byte Reload
subq %r15, %rbp
movq 8(%rsp), %r12 # 8-byte Reload
testl %r12d, %r12d
je .LBB3_19
# %bb.17: # %.lr.ph142.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_18: # %.lr.ph142
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq %rax, %r13
jne .LBB3_18
.LBB3_19: # %._crit_edge143
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
leaq 1656(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq 1944(%rsp), %rdx
movq stderr(%rip), %rdi
shrq $20, %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
leaq 184(%rsp), %rdi
leaq 176(%rsp), %rsi
callq hipMemGetInfo
movq stderr(%rip), %rdi
movq 184(%rsp), %rdx
shrq $20, %rdx
movq 176(%rsp), %rcx
shrq $20, %rcx
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
movl %r14d, 108(%rsp)
movl 36(%rsp), %r13d # 4-byte Reload
movl %r13d, 112(%rsp)
movl %r12d, 116(%rsp)
leaq 64(%rsp), %rdi
movl $12, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq 120(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
leaq 108(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq hipMemset
movq 128(%rsp), %rdx # 8-byte Reload
shrl $10, %edx
incl %edx
movabsq $4294967296, %rbx # imm = 0x100000000
movq %r15, %rbp
leaq (%rdx,%rbx), %r15
movl $.L.str.8, %edi
movl $1024, %esi # imm = 0x400
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
orq $1024, %rbx # imm = 0x400
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 144(%rsp), %r12 # 8-byte Reload
jne .LBB3_21
# %bb.20:
movq 80(%rsp), %rax
movq 24(%rsp), %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 88(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 200(%rsp), %rdx
leaq 192(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z16GaussianBlurCudaPhS_PdPi, %edi
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 152(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 1488(%rsp), %rdi
callq jpeg_std_error
movq %rax, 240(%rsp)
leaq 240(%rsp), %rbx
movl $584, %edx # imm = 0x248
movq %rbx, %rdi
movl $80, %esi
callq jpeg_CreateCompress
movq %rbx, %rdi
movq 56(%rsp), %rsi # 8-byte Reload
callq jpeg_stdio_dest
movl %r14d, 288(%rsp)
movl %r13d, 292(%rsp)
movabsq $8589934595, %rax # imm = 0x200000003
movq %rax, 296(%rsp)
movq %rbx, %rdi
callq jpeg_set_defaults
movq %rbx, %rdi
movl $70, %esi
movl $1, %edx
callq jpeg_set_quality
movq %rbx, %rdi
movl $1, %esi
callq jpeg_start_compress
movl 580(%rsp), %eax
cmpl 292(%rsp), %eax
jae .LBB3_24
# %bb.22: # %.lr.ph145
leal (%r14,%r14,2), %ebp
leaq 240(%rsp), %rbx
leaq 40(%rsp), %r15
.p2align 4, 0x90
.LBB3_23: # =>This Inner Loop Header: Depth=1
imull %ebp, %eax
addq %r12, %rax
movq %rax, 40(%rsp)
movq %rbx, %rdi
movq %r15, %rsi
movl $1, %edx
callq jpeg_write_scanlines
movl 580(%rsp), %eax
cmpl 292(%rsp), %eax
jb .LBB3_23
.LBB3_24: # %._crit_edge146
leaq 240(%rsp), %rbx
movq %rbx, %rdi
callq jpeg_finish_compress
movq 56(%rsp), %rdi # 8-byte Reload
callq fclose
movq %rbx, %rdi
callq jpeg_destroy_compress
xorl %ebx, %ebx
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 88(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 96(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.9, %edi
movb $1, %al
callq printf
jmp .LBB3_25
.LBB3_26:
movq (%rbx), %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_27:
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16GaussianBlurCudaPhS_PdPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n"
.size .L.str.1, 71
.type _Z16GaussianBlurCudaPhS_PdPi,@object # @_Z16GaussianBlurCudaPhS_PdPi
.section .rodata,"a",@progbits
.globl _Z16GaussianBlurCudaPhS_PdPi
.p2align 3, 0x0
_Z16GaussianBlurCudaPhS_PdPi:
.quad _Z31__device_stub__GaussianBlurCudaPhS_PdPi
.size _Z16GaussianBlurCudaPhS_PdPi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "rb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "wb"
.size .L.str.4, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU global memory = %zu MBytes\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Free = %zu MB, Total = %zu MB\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Time elapsed: %lf seconds.\n"
.size .L.str.9, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16GaussianBlurCudaPhS_PdPi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Code to blur parts of image using GPUs."
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Could not read file"
.size .Lstr.1, 20
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Mask width must be odd."
.size .Lstr.2, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__GaussianBlurCudaPhS_PdPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16GaussianBlurCudaPhS_PdPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d80ab_00000000-6_iojpegCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Code to blur parts of image using GPUs.\n"
.align 8
.LC2:
.string "Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n"
.text
.globl _Z5usagePc
.type _Z5usagePc, @function
_Z5usagePc:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5usagePc, .-_Z5usagePc
.globl _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
.type _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi, @function
_Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16GaussianBlurCudaPhS_PdPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi, .-_Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
.globl _Z16GaussianBlurCudaPhS_PdPi
.type _Z16GaussianBlurCudaPhS_PdPi, @function
_Z16GaussianBlurCudaPhS_PdPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16GaussianBlurCudaPhS_PdPi, .-_Z16GaussianBlurCudaPhS_PdPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Mask width must be odd.\n"
.LC5:
.string "rb"
.LC6:
.string "wb"
.LC7:
.string "Could not read file\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "GPU global memory = %zu MBytes\n"
.align 8
.LC12:
.string "Free = %zu MB, Total = %zu MB\n"
.section .rodata.str1.1
.LC13:
.string "%d %d\n"
.LC14:
.string "Time elapsed: %lf seconds.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $2664, %rsp
.cfi_def_cfa_offset 2720
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 2648(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L41
movq 8(%rsi), %r12
movq 16(%rsi), %rbp
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 48(%rsp)
movl %eax, 88(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movl %r15d, %edx
shrl $31, %edx
movl %r15d, %eax
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, %ebx
cmpl $1, %eax
jne .L42
call _Z9cpuSecondv
movsd %xmm0, 64(%rsp)
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, 40(%rsp)
testq %r14, %r14
je .L43
leaq 192(%rsp), %rdi
call jpeg_std_error@PLT
movq %rax, 960(%rsp)
leaq 960(%rsp), %rbx
movl $656, %edx
movl $80, %esi
movq %rbx, %rdi
call jpeg_CreateDecompress@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
call jpeg_stdio_src@PLT
movl $1, %esi
movq %rbx, %rdi
call jpeg_read_header@PLT
movq %rbx, %rdi
call jpeg_start_decompress@PLT
movl 1096(%rsp), %r12d
movl %r12d, %r13d
imull 1108(%rsp), %r13d
movl 1100(%rsp), %eax
movl %eax, 56(%rsp)
imull %r12d, %eax
movl %eax, 60(%rsp)
leal (%rax,%rax,2), %eax
cltq
movq %rax, 32(%rsp)
leaq 0(,%rax,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, 72(%rsp)
movl $1, %ecx
movl %r13d, %edx
movl $1, %esi
movq %rbx, %rdi
movq 968(%rsp), %rax
call *16(%rax)
movq %rax, %rbx
movl 1100(%rsp), %eax
cmpl %eax, 1128(%rsp)
jnb .L23
leal -1(%r12), %eax
leaq (%rax,%rax,2), %r15
leaq 3(%rax,%rax,2), %r14
leaq 960(%rsp), %r13
jmp .L28
.L41:
movq 2648(%rsp), %rax
subq %fs:40, %rax
jne .L44
movq (%rsi), %rdi
call _Z5usagePc
.L44:
call __stack_chk_fail@PLT
.L42:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L25:
movb %cl, -2(%rax)
.L26:
movb %cl, -1(%rsi)
addq %r9, %rdx
addq $3, %rax
cmpq %r8, %rax
je .L45
.L27:
movq (%rbx), %rcx
movzbl (%rcx,%rdx), %ecx
movq %rax, %rsi
movb %cl, -3(%rax)
cmpl $2, %edi
jle .L25
movq (%rbx), %rcx
movzbl 1(%rcx,%rdx), %ecx
movb %cl, -2(%rax)
movq (%rbx), %rcx
movzbl 2(%rcx,%rdx), %ecx
jmp .L26
.L45:
addq %r14, %rbp
.L24:
movl 1100(%rsp), %eax
cmpl %eax, 1128(%rsp)
jnb .L23
.L28:
movl $1, %edx
movq %rbx, %rsi
movq %r13, %rdi
call jpeg_read_scanlines@PLT
testl %r12d, %r12d
jle .L24
movl 1108(%rsp), %edi
movslq %edi, %r9
leaq 3(%rbp), %rax
leaq 6(%rbp,%r15), %r8
movl $0, %edx
jmp .L27
.L23:
movq 32(%rsp), %rax
subq %rax, %rbp
movq %rbp, 80(%rsp)
movq 8(%rsp), %rdi
call fclose@PLT
leaq 960(%rsp), %rbx
movq %rbx, %rdi
call jpeg_finish_decompress@PLT
movq %rbx, %rdi
call jpeg_destroy_decompress@PLT
movq 48(%rsp), %rbx
movl %ebx, %r14d
imull %ebx, %r14d
movslq %r14d, %r14
leaq 0(,%r14,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %ebp
shrl $31, %ebp
addl %ebx, %ebp
sarl %ebp
movsd 16(%rsp), %xmm7
movapd %xmm7, %xmm0
mulsd %xmm7, %xmm0
mulsd .LC8(%rip), %xmm0
divsd .LC9(%rip), %xmm0
movsd .LC10(%rip), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp)
movapd %xmm7, %xmm0
addsd %xmm7, %xmm0
mulsd %xmm7, %xmm0
movsd %xmm0, 16(%rsp)
movl $0, %ebx
movq $0x000000000, 8(%rsp)
movl %r12d, 92(%rsp)
movl 88(%rsp), %r12d
.L29:
movl %ebx, %eax
cltd
idivl %r12d
subl %ebp, %eax
movl %ebp, %ecx
subl %edx, %ecx
subl %ebp, %edx
imull %edx, %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
movsd 16(%rsp), %xmm2
divsd %xmm2, %xmm0
imull %eax, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
call exp@PLT
mulsd 24(%rsp), %xmm0
movsd %xmm0, 0(%r13,%rbx,8)
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rbx
cmpq %rbx, %r14
jne .L29
movl 92(%rsp), %r12d
movq %r13, %rax
leaq (%r15,%r13), %rdx
.L30:
movsd (%rax), %xmm0
divsd 8(%rsp), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L30
leaq 1616(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movq 1904(%rsp), %rcx
shrq $20, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdi
call cudaMemGetInfo@PLT
movq 96(%rsp), %rcx
shrq $20, %rcx
movq 104(%rsp), %r8
shrq $20, %r8
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, 180(%rsp)
movl 56(%rsp), %eax
movl %eax, 184(%rsp)
movl 48(%rsp), %eax
movl %eax, 188(%rsp)
leaq 136(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq 32(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 180(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 136(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq 120(%rsp), %rdi
call cudaMemset@PLT
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl 60(%rsp), %ebx
shrl $10, %ebx
addl $1, %ebx
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl %ebx, %ecx
movl $1024, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, 156(%rsp)
movl $1024, 144(%rsp)
movl 152(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 144(%rsp), %rdx
movq 156(%rsp), %rdi
movl 164(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L31:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq 32(%rsp), %rdx
movq 120(%rsp), %rsi
movq 72(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 192(%rsp), %rdi
call jpeg_std_error@PLT
movq %rax, 368(%rsp)
leaq 368(%rsp), %rbx
movl $584, %edx
movl $80, %esi
movq %rbx, %rdi
call jpeg_CreateCompress@PLT
movq 40(%rsp), %rsi
movq %rbx, %rdi
call jpeg_stdio_dest@PLT
movl %r12d, 416(%rsp)
movl 56(%rsp), %eax
movl %eax, 420(%rsp)
movl $3, 424(%rsp)
movl $2, 428(%rsp)
movq %rbx, %rdi
call jpeg_set_defaults@PLT
movl $1, %edx
movl $70, %esi
movq %rbx, %rdi
call jpeg_set_quality@PLT
movl $1, %esi
movq %rbx, %rdi
call jpeg_start_compress@PLT
movl 708(%rsp), %eax
cmpl 420(%rsp), %eax
jnb .L32
leaq 168(%rsp), %rbx
.L33:
imull %r12d, %eax
leal (%rax,%rax,2), %eax
addq %rbp, %rax
movq %rax, 168(%rsp)
leaq 368(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call jpeg_write_scanlines@PLT
movl 708(%rsp), %eax
cmpl 420(%rsp), %eax
jb .L33
.L32:
leaq 368(%rsp), %rbx
movq %rbx, %rdi
call jpeg_finish_compress@PLT
movq 40(%rsp), %rdi
call fclose@PLT
movq %rbx, %rdi
call jpeg_destroy_compress@PLT
call _Z9cpuSecondv
subsd 64(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %ebx
.L17:
movq 2648(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl %ebx, %eax
addq $2664, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 120(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z42__device_stub__Z16GaussianBlurCudaPhS_PdPiPhS_PdPi
jmp .L31
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z16GaussianBlurCudaPhS_PdPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z16GaussianBlurCudaPhS_PdPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC8:
.long 0
.long 1078329344
.align 8
.LC9:
.long 0
.long 1075576832
.align 8
.LC10:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "iojpegCUDA.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z5usagePc # -- Begin function _Z5usagePc
.p2align 4, 0x90
.type _Z5usagePc,@function
_Z5usagePc: # @_Z5usagePc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z5usagePc, .Lfunc_end1-_Z5usagePc
.cfi_endproc
# -- End function
.globl _Z31__device_stub__GaussianBlurCudaPhS_PdPi # -- Begin function _Z31__device_stub__GaussianBlurCudaPhS_PdPi
.p2align 4, 0x90
.type _Z31__device_stub__GaussianBlurCudaPhS_PdPi,@function
_Z31__device_stub__GaussianBlurCudaPhS_PdPi: # @_Z31__device_stub__GaussianBlurCudaPhS_PdPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16GaussianBlurCudaPhS_PdPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z31__device_stub__GaussianBlurCudaPhS_PdPi, .Lfunc_end2-_Z31__device_stub__GaussianBlurCudaPhS_PdPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI3_1:
.quad 0x4046000000000000 # double 44
.LCPI3_2:
.quad 0x401c000000000000 # double 7
.LCPI3_3:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $3128, %rsp # imm = 0xC38
.cfi_def_cfa_offset 3184
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $5, %edi
jne .LBB3_26
# %bb.1:
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl %r12d, %eax
andl $-2147483647, %eax # imm = 0x80000001
cmpl $1, %eax
jne .LBB3_27
# %bb.2:
movq 8(%rbx), %r14
movq 16(%rbx), %r15
leaq 1656(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 1656(%rsp), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 1664(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.3, %esi
movq %r14, %rdi
callq fopen
movq %rax, %rbx
movl $.L.str.4, %esi
movq %r15, %rdi
callq fopen
testq %rbx, %rbx
jne .LBB3_4
# %bb.3:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %ebx
.LBB3_25:
movl %ebx, %eax
addq $3128, %rsp # imm = 0xC38
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_4:
.cfi_def_cfa_offset 3184
movq %r12, 8(%rsp) # 8-byte Spill
movq %rax, 56(%rsp) # 8-byte Spill
leaq 1488(%rsp), %rdi
callq jpeg_std_error
movq %rax, 832(%rsp)
leaq 832(%rsp), %r12
movl $656, %edx # imm = 0x290
movq %r12, %rdi
movl $80, %esi
callq jpeg_CreateDecompress
movq %r12, %rdi
movq %rbx, %rsi
callq jpeg_stdio_src
movq %r12, %rdi
movl $1, %esi
callq jpeg_read_header
movq %r12, %rdi
callq jpeg_start_decompress
movl 968(%rsp), %r14d
movl 972(%rsp), %eax
movl 980(%rsp), %r13d
imull %r14d, %r13d
movl %eax, 36(%rsp) # 4-byte Spill
# kill: def $eax killed $eax def $rax
imull %r14d, %eax
movq %rax, 128(%rsp) # 8-byte Spill
leal (%rax,%rax,2), %eax
cltq
movq %rax, 136(%rsp) # 8-byte Spill
leaq (,%rax,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbp
movq %r15, %rdi
callq malloc
movq %rax, 144(%rsp) # 8-byte Spill
movq 840(%rsp), %rax
movq %r12, %rdi
movl $1, %esi
movl %r13d, %edx
movl $1, %ecx
callq *16(%rax)
movq %rax, %r15
movl 1000(%rsp), %eax
cmpl 972(%rsp), %eax
jae .LBB3_13
# %bb.5:
leaq 832(%rsp), %r13
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_6: # %.loopexit
# in Loop: Header=BB3_7 Depth=1
movl 1000(%rsp), %eax
cmpl 972(%rsp), %eax
jae .LBB3_13
.LBB3_7: # =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
movq %r13, %rdi
movq %r15, %rsi
movl $1, %edx
callq jpeg_read_scanlines
testl %r14d, %r14d
jle .LBB3_6
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB3_7 Depth=1
xorl %eax, %eax
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_9 Depth=2
movb %sil, 1(%rbp)
movb %sil, 2(%rbp)
.LBB3_12: # in Loop: Header=BB3_9 Depth=2
addq $3, %rbp
incl %eax
cmpl %eax, %r14d
je .LBB3_6
.LBB3_9: # %.lr.ph
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r15), %rdx
movslq 980(%rsp), %rsi
movslq %eax, %rcx
imulq %rcx, %rsi
movzbl (%rdx,%rsi), %esi
movb %sil, (%rbp)
movl 980(%rsp), %edx
cmpl $3, %edx
jl .LBB3_11
# %bb.10: # in Loop: Header=BB3_9 Depth=2
movq (%r15), %rsi
imull %eax, %edx
movzbl 1(%rsi,%rdx), %edx
movb %dl, 1(%rbp)
movq (%r15), %rdx
movslq 980(%rsp), %rsi
imulq %rcx, %rsi
movzbl 2(%rdx,%rsi), %ecx
movb %cl, 2(%rbp)
jmp .LBB3_12
.LBB3_13: # %._crit_edge
movq %rbx, %rdi
callq fclose
leaq 832(%rsp), %rbx
movq %rbx, %rdi
callq jpeg_finish_decompress
movq %rbx, %rdi
callq jpeg_destroy_decompress
movq 8(%rsp), %r12 # 8-byte Reload
movl %r12d, %r15d
imull %r15d, %r15d
leaq (,%r15,8), %rdi
movq %rdi, 120(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
xorpd %xmm1, %xmm1
movl %r15d, %r13d
testl %r12d, %r12d
je .LBB3_16
# %bb.14: # %.lr.ph139
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %r12d
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movapd %xmm1, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd .LCPI3_2(%rip), %xmm0
shrl %r12d
movsd .LCPI3_3(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm0, %xmm2
movsd %xmm2, 168(%rsp) # 8-byte Spill
movapd %xmm1, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
xorpd %xmm1, %xmm1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_15: # =>This Inner Loop Header: Depth=1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movl %r15d, %eax
xorl %edx, %edx
divl 8(%rsp) # 4-byte Folded Reload
subl %r12d, %edx
imull %edx, %edx
negl %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd 160(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
divsd %xmm2, %xmm0
subl %r12d, %eax
imull %eax, %eax
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
divsd %xmm2, %xmm1
subsd %xmm1, %xmm0
callq exp
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd 168(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r15,8)
addsd %xmm0, %xmm1
incq %r15
cmpq %r15, %r13
jne .LBB3_15
.LBB3_16: # %.preheader
movq 136(%rsp), %r15 # 8-byte Reload
subq %r15, %rbp
movq 8(%rsp), %r12 # 8-byte Reload
testl %r12d, %r12d
je .LBB3_19
# %bb.17: # %.lr.ph142.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_18: # %.lr.ph142
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq %rax, %r13
jne .LBB3_18
.LBB3_19: # %._crit_edge143
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
leaq 1656(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq 1944(%rsp), %rdx
movq stderr(%rip), %rdi
shrq $20, %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
leaq 184(%rsp), %rdi
leaq 176(%rsp), %rsi
callq hipMemGetInfo
movq stderr(%rip), %rdi
movq 184(%rsp), %rdx
shrq $20, %rdx
movq 176(%rsp), %rcx
shrq $20, %rcx
movl $.L.str.7, %esi
xorl %eax, %eax
callq fprintf
movl %r14d, 108(%rsp)
movl 36(%rsp), %r13d # 4-byte Reload
movl %r13d, 112(%rsp)
movl %r12d, 116(%rsp)
leaq 64(%rsp), %rdi
movl $12, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 72(%rsp), %rdi
movq 120(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
leaq 108(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq hipMemset
movq 128(%rsp), %rdx # 8-byte Reload
shrl $10, %edx
incl %edx
movabsq $4294967296, %rbx # imm = 0x100000000
movq %r15, %rbp
leaq (%rdx,%rbx), %r15
movl $.L.str.8, %edi
movl $1024, %esi # imm = 0x400
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
orq $1024, %rbx # imm = 0x400
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 144(%rsp), %r12 # 8-byte Reload
jne .LBB3_21
# %bb.20:
movq 80(%rsp), %rax
movq 24(%rsp), %rcx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 88(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 200(%rsp), %rdx
leaq 192(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z16GaussianBlurCudaPhS_PdPi, %edi
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
pushq 208(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 152(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
leaq 1488(%rsp), %rdi
callq jpeg_std_error
movq %rax, 240(%rsp)
leaq 240(%rsp), %rbx
movl $584, %edx # imm = 0x248
movq %rbx, %rdi
movl $80, %esi
callq jpeg_CreateCompress
movq %rbx, %rdi
movq 56(%rsp), %rsi # 8-byte Reload
callq jpeg_stdio_dest
movl %r14d, 288(%rsp)
movl %r13d, 292(%rsp)
movabsq $8589934595, %rax # imm = 0x200000003
movq %rax, 296(%rsp)
movq %rbx, %rdi
callq jpeg_set_defaults
movq %rbx, %rdi
movl $70, %esi
movl $1, %edx
callq jpeg_set_quality
movq %rbx, %rdi
movl $1, %esi
callq jpeg_start_compress
movl 580(%rsp), %eax
cmpl 292(%rsp), %eax
jae .LBB3_24
# %bb.22: # %.lr.ph145
leal (%r14,%r14,2), %ebp
leaq 240(%rsp), %rbx
leaq 40(%rsp), %r15
.p2align 4, 0x90
.LBB3_23: # =>This Inner Loop Header: Depth=1
imull %ebp, %eax
addq %r12, %rax
movq %rax, 40(%rsp)
movq %rbx, %rdi
movq %r15, %rsi
movl $1, %edx
callq jpeg_write_scanlines
movl 580(%rsp), %eax
cmpl 292(%rsp), %eax
jb .LBB3_23
.LBB3_24: # %._crit_edge146
leaq 240(%rsp), %rbx
movq %rbx, %rdi
callq jpeg_finish_compress
movq 56(%rsp), %rdi # 8-byte Reload
callq fclose
movq %rbx, %rdi
callq jpeg_destroy_compress
xorl %ebx, %ebx
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 88(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 96(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.9, %edi
movb $1, %al
callq printf
jmp .LBB3_25
.LBB3_26:
movq (%rbx), %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB3_27:
movl $.Lstr.2, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16GaussianBlurCudaPhS_PdPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Usage as follows: %s InputFileName OutputFileName MaskWidth PeakWidth\n"
.size .L.str.1, 71
.type _Z16GaussianBlurCudaPhS_PdPi,@object # @_Z16GaussianBlurCudaPhS_PdPi
.section .rodata,"a",@progbits
.globl _Z16GaussianBlurCudaPhS_PdPi
.p2align 3, 0x0
_Z16GaussianBlurCudaPhS_PdPi:
.quad _Z31__device_stub__GaussianBlurCudaPhS_PdPi
.size _Z16GaussianBlurCudaPhS_PdPi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "rb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "wb"
.size .L.str.4, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU global memory = %zu MBytes\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Free = %zu MB, Total = %zu MB\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Time elapsed: %lf seconds.\n"
.size .L.str.9, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16GaussianBlurCudaPhS_PdPi"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Code to blur parts of image using GPUs."
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Could not read file"
.size .Lstr.1, 20
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Mask width must be odd."
.size .Lstr.2, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__GaussianBlurCudaPhS_PdPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16GaussianBlurCudaPhS_PdPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Subtract(float *d_Result, float *d_Data1, float *d_Data2, int width, int pitch, int height)
{
const int x = blockIdx.x*SUBTRACT_W + threadIdx.x;
const int y = blockIdx.y*SUBTRACT_H + threadIdx.y;
int p = y*pitch + x;
if (x<width && y<height)
d_Result[p] = d_Data1[p] - d_Data2[p];
__syncthreads();
} | code for sm_80
Function : _Z8SubtractPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ BSSY B0, 0x160 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x001fc800078e20ff */
/*0070*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe40003f06270 */
/*0080*/ LEA R0, R0, R5, 0x5 ; /* 0x0000000500007211 */
/* 0x002fc800078e28ff */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00a0*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x000fd800078e0200 */
/*00b0*/ @P0 BRA 0x150 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000100 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Subtract(float *d_Result, float *d_Data1, float *d_Data2, int width, int pitch, int height)
{
const int x = blockIdx.x*SUBTRACT_W + threadIdx.x;
const int y = blockIdx.y*SUBTRACT_H + threadIdx.y;
int p = y*pitch + x;
if (x<width && y<height)
d_Result[p] = d_Data1[p] - d_Data2[p];
__syncthreads();
} | .file "tmpxft_000aa2be_00000000-6_Subtract.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8SubtractPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii
.globl _Z8SubtractPfS_S_iii
.type _Z8SubtractPfS_S_iii, @function
_Z8SubtractPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8SubtractPfS_S_iii, .-_Z8SubtractPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8SubtractPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SubtractPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Subtract(float *d_Result, float *d_Data1, float *d_Data2, int width, int pitch, int height)
{
const int x = blockIdx.x*SUBTRACT_W + threadIdx.x;
const int y = blockIdx.y*SUBTRACT_H + threadIdx.y;
int p = y*pitch + x;
if (x<width && y<height)
d_Result[p] = d_Data1[p] - d_Data2[p];
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Subtract(float *d_Result, float *d_Data1, float *d_Data2, int width, int pitch, int height)
{
const int x = blockIdx.x*SUBTRACT_W + threadIdx.x;
const int y = blockIdx.y*SUBTRACT_H + threadIdx.y;
int p = y*pitch + x;
if (x<width && y<height)
d_Result[p] = d_Data1[p] - d_Data2[p];
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Subtract(float *d_Result, float *d_Data1, float *d_Data2, int width, int pitch, int height)
{
const int x = blockIdx.x*SUBTRACT_W + threadIdx.x;
const int y = blockIdx.y*SUBTRACT_H + threadIdx.y;
int p = y*pitch + x;
if (x<width && y<height)
d_Result[p] = d_Data1[p] - d_Data2[p];
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SubtractPfS_S_iii
.globl _Z8SubtractPfS_S_iii
.p2align 8
.type _Z8SubtractPfS_S_iii,@function
_Z8SubtractPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 4, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SubtractPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SubtractPfS_S_iii, .Lfunc_end0-_Z8SubtractPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SubtractPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8SubtractPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Subtract(float *d_Result, float *d_Data1, float *d_Data2, int width, int pitch, int height)
{
const int x = blockIdx.x*SUBTRACT_W + threadIdx.x;
const int y = blockIdx.y*SUBTRACT_H + threadIdx.y;
int p = y*pitch + x;
if (x<width && y<height)
d_Result[p] = d_Data1[p] - d_Data2[p];
__syncthreads();
} | .text
.file "Subtract.hip"
.globl _Z23__device_stub__SubtractPfS_S_iii # -- Begin function _Z23__device_stub__SubtractPfS_S_iii
.p2align 4, 0x90
.type _Z23__device_stub__SubtractPfS_S_iii,@function
_Z23__device_stub__SubtractPfS_S_iii: # @_Z23__device_stub__SubtractPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8SubtractPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__SubtractPfS_S_iii, .Lfunc_end0-_Z23__device_stub__SubtractPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SubtractPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SubtractPfS_S_iii,@object # @_Z8SubtractPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z8SubtractPfS_S_iii
.p2align 3, 0x0
_Z8SubtractPfS_S_iii:
.quad _Z23__device_stub__SubtractPfS_S_iii
.size _Z8SubtractPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8SubtractPfS_S_iii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SubtractPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SubtractPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8SubtractPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ BSSY B0, 0x160 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ LEA R3, R3, R2, 0x4 ; /* 0x0000000203037211 */
/* 0x001fc800078e20ff */
/*0070*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fe40003f06270 */
/*0080*/ LEA R0, R0, R5, 0x5 ; /* 0x0000000500007211 */
/* 0x002fc800078e28ff */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00a0*/ IMAD R0, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003007a24 */
/* 0x000fd800078e0200 */
/*00b0*/ @P0 BRA 0x150 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0130*/ FADD R9, -R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000100 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8SubtractPfS_S_iii
.globl _Z8SubtractPfS_S_iii
.p2align 8
.type _Z8SubtractPfS_S_iii,@function
_Z8SubtractPfS_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v1, s15, 4, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s2
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s3, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8SubtractPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8SubtractPfS_S_iii, .Lfunc_end0-_Z8SubtractPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8SubtractPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8SubtractPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aa2be_00000000-6_Subtract.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8SubtractPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii
.globl _Z8SubtractPfS_S_iii
.type _Z8SubtractPfS_S_iii, @function
_Z8SubtractPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8SubtractPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8SubtractPfS_S_iii, .-_Z8SubtractPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8SubtractPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8SubtractPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Subtract.hip"
.globl _Z23__device_stub__SubtractPfS_S_iii # -- Begin function _Z23__device_stub__SubtractPfS_S_iii
.p2align 4, 0x90
.type _Z23__device_stub__SubtractPfS_S_iii,@function
_Z23__device_stub__SubtractPfS_S_iii: # @_Z23__device_stub__SubtractPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8SubtractPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__SubtractPfS_S_iii, .Lfunc_end0-_Z23__device_stub__SubtractPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8SubtractPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8SubtractPfS_S_iii,@object # @_Z8SubtractPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z8SubtractPfS_S_iii
.p2align 3, 0x0
_Z8SubtractPfS_S_iii:
.quad _Z23__device_stub__SubtractPfS_S_iii
.size _Z8SubtractPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8SubtractPfS_S_iii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__SubtractPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8SubtractPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computeVertices_kernel(float4* pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int y = blockIdx.x * blockDim.x + threadIdx.x;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0 - 1.0f;
v = v*2.0 - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sin(u*freq + time) * cos(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | .file "tmpxft_0013d0af_00000000-6_computeVertices_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf
.type _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf, @function
_Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22computeVertices_kernelP6float4jjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf, .-_Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf
.globl _Z22computeVertices_kernelP6float4jjf
.type _Z22computeVertices_kernelP6float4jjf, @function
_Z22computeVertices_kernelP6float4jjf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22computeVertices_kernelP6float4jjf, .-_Z22computeVertices_kernelP6float4jjf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22computeVertices_kernelP6float4jjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22computeVertices_kernelP6float4jjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computeVertices_kernel(float4* pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int y = blockIdx.x * blockDim.x + threadIdx.x;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0 - 1.0f;
v = v*2.0 - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sin(u*freq + time) * cos(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeVertices_kernel(float4* pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int y = blockIdx.x * blockDim.x + threadIdx.x;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0 - 1.0f;
v = v*2.0 - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sin(u*freq + time) * cos(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeVertices_kernel(float4* pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int y = blockIdx.x * blockDim.x + threadIdx.x;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0 - 1.0f;
v = v*2.0 - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sin(u*freq + time) * cos(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.globl _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.p2align 8
.type _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf,@function
_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s5, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s6, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_cvt_f32_u32_e32 v1, s4
v_cvt_f32_u32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v1, v1, v3
v_div_scale_f32 v7, vcc_lo, v3, v1, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v4, v1, v3
v_cvt_f64_f32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], 2.0, -1.0
v_cvt_f32_f64_e32 v1, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v1, 4.0, s5
v_and_b32_e32 v7, 0x7fffffff, v6
v_cmpx_ngt_f32_e64 0x48000000, |v6|
s_xor_b32 s7, exec_lo, s3
s_cbranch_execz .LBB0_2
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v5, 0
v_and_or_b32 v15, v7, s2, 0x800000
v_lshrrev_b32_e32 v12, 23, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v15, 0xfe5163ab, 0
v_add_nc_u32_e32 v13, 0xffffff88, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v13
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[4:5]
v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v9
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v9, v3 :: v_dual_add_nc_u32 v14, v14, v13
v_mov_b32_e32 v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s2, 31, v14
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s2
v_add_nc_u32_e32 v16, v16, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v4, v11
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e64 s3, 31, v16
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v8, v3, s2
v_mov_b32_e32 v4, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[4:5]
v_mov_b32_e32 v4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
v_cndmask_b32_e32 v5, v12, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v4, v4, v16
v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e64 v10, v13, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v13, s2
v_cndmask_b32_e64 v5, v5, v11, s2
v_sub_nc_u32_e32 v13, 32, v4
v_cndmask_b32_e64 v11, v11, v8, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v10, s3
v_cndmask_b32_e64 v10, v10, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v5, v11, s3
v_cndmask_b32_e64 v3, v11, v3, s3
v_alignbit_b32 v14, v12, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v10, v5, v13
v_cndmask_b32_e32 v4, v14, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v5, v3, v13
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v9, v4, 29, 1
v_cndmask_b32_e32 v5, v12, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v4, v8, 30
v_sub_nc_u32_e32 v11, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v8, v5, 30
v_alignbit_b32 v3, v5, v3, 30
v_xor_b32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v8, v11
v_xor_b32_e32 v3, v3, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v12, v10
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
v_alignbit_b32 v10, v10, v5, v8
v_alignbit_b32 v3, v5, v3, v8
v_lshrrev_b32_e32 v8, 29, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v5, v10, v3, 9
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v11, v5
v_or_b32_e32 v13, 0.5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v13, v13, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v15, 31, v11
v_alignbit_b32 v3, v5, v3, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
v_lshrrev_b32_e32 v3, 9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, 0x3fc90fda, v5
v_sub_nc_u32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, v5, 0x3fc90fda, -v11
v_add_nc_u32_e32 v3, 0x33000000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v5, v5, 0x33a22168, v10
v_or_b32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0x3fc90fda, v3
v_lshrrev_b32_e32 v3, 30, v4
v_dual_add_f32 v8, v11, v5 :: v_dual_add_nc_u32 v9, v9, v3
.LBB0_2:
s_and_not1_saveexec_b32 s2, s7
v_mul_f32_e64 v3, 0x3f22f983, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v3, v3
v_fma_f32 v4, v3, 0xbfc90fda, |v6|
v_cvt_i32_f32_e32 v9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v3, 0xb3a22168, v4
v_fmamk_f32 v8, v3, 0xa7c234c4, v4
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s2, s[0:1], 0xc
v_and_b32_e32 v0, 0x3ff, v0
s_and_b32 s3, 0xffff, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s14, s3, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v4
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v3, s2
v_div_scale_f32 v5, null, v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v5, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v11, vcc_lo, v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v11, v10
v_fma_f32 v13, -v5, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v10
v_fma_f32 v5, -v5, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v10, v12
v_div_fixup_f32 v0, v5, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[10:11], v0
v_fma_f64 v[10:11], v[10:11], 2.0, -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v3, v[10:11]
v_fma_f32 v0, v3, 4.0, s5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v5, 0x7fffffff, v0
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v20, v5, s2, 0x800000
v_lshrrev_b32_e32 v5, 23, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v20, 0xfe5163ab, 0
v_add_nc_u32_e32 v5, 0xffffff88, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v5
v_mad_u64_u32 v[13:14], null, v20, 0x3c439041, v[11:12]
v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v14
v_add_nc_u32_e32 v5, v18, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[14:15], null, v20, 0xdb629599, v[11:12]
v_cmp_lt_u32_e64 s2, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
v_dual_mov_b32 v11, v15 :: v_dual_cndmask_b32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v19, v5
v_mad_u64_u32 v[15:16], null, v20, 0xf534ddc0, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v5
v_mov_b32_e32 v11, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[16:17], null, v20, 0xfc2757d1, v[11:12]
v_mov_b32_e32 v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[17:18], null, v20, 0x4e441529, v[11:12]
v_mov_b32_e32 v11, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[18:19], null, v20, 0xa2f9836e, v[11:12]
v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v12, v17, v15 :: v_dual_add_nc_u32 v5, v11, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v18, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v11, v15, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v18, v12, s2
v_cndmask_b32_e64 v15, v17, v18, s2
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v16, s2
v_sub_nc_u32_e32 v17, 32, v5
v_cndmask_b32_e64 v16, v16, v11, s2
v_cndmask_b32_e64 v10, v11, v10, s2
v_cndmask_b32_e64 v15, v15, v13, s3
v_cndmask_b32_e64 v13, v13, v12, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v16, s3
v_cndmask_b32_e64 v10, v16, v10, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v18, v15, v13, v17
v_alignbit_b32 v14, v13, v12, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v12, v10, v17
v_cndmask_b32_e32 v5, v18, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v11, v14, v13 :: v_dual_cndmask_b32 v12, v16, v12
v_bfe_u32 v13, v5, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v5, v11, 30
v_alignbit_b32 v11, v11, v12, 30
v_alignbit_b32 v10, v12, v10, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v15, 0, v13
v_xor_b32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v11, v11, v15
v_xor_b32_e32 v10, v10, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v16, v14
v_min_u32_e32 v16, 32, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, 31, v16
v_lshlrev_b32_e32 v18, 23, v16
v_alignbit_b32 v14, v14, v11, v12
v_alignbit_b32 v10, v11, v10, v12
v_lshrrev_b32_e32 v12, 29, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v11, v14, v10, 9
v_lshlrev_b32_e32 v12, 31, v12
v_lshrrev_b32_e32 v14, 9, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v15, v11
v_or_b32_e32 v17, 0.5, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v15, 32, v15
v_sub_nc_u32_e32 v17, v17, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v19, 31, v15
v_alignbit_b32 v10, v11, v10, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v11, v14, v17
v_add_lshl_u32 v14, v15, v16, 23
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, 0x3fc90fda, v11
v_sub_nc_u32_e32 v10, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, v11, 0x3fc90fda, -v15
v_add_nc_u32_e32 v10, 0x33000000, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v11, v11, 0x33a22168, v14
v_or_b32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, 0x3fc90fda, v10
v_lshrrev_b32_e32 v10, 30, v5
v_dual_add_f32 v5, v15, v11 :: v_dual_add_nc_u32 v10, v13, v10
.LBB0_6:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v10, v5
v_fma_f32 v5, v10, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v10, 0xb3a22168, v5
v_fmamk_f32 v5, v10, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v10, v10
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v11, v8, v8 :: v_dual_mul_f32 v12, v5, v5
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
v_xor_b32_e32 v7, v7, v6
v_dual_fmaak_f32 v13, s2, v11, 0x3c0881c4 :: v_dual_lshlrev_b32 v16, 30, v9
v_dual_fmaak_f32 v14, s3, v11, 0xbab64f3b :: v_dual_fmaak_f32 v17, s3, v12, 0xbab64f3b
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v13, v11, v13, 0xbe2aaa9d
v_dual_fmaak_f32 v14, v11, v14, 0x3d2aabf7 :: v_dual_and_b32 v9, 1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v17, v12, v17, 0x3d2aabf7
v_dual_mul_f32 v13, v11, v13 :: v_dual_and_b32 v16, 0x80000000, v16
v_fmaak_f32 v15, s2, v12, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmaak_f32 v14, v11, v14, 0xbf000004
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_fmaak_f32 v17, v12, v17, 0xbf000004
v_dual_fmac_f32 v8, v8, v13 :: v_dual_and_b32 v13, 1, v10
v_fma_f32 v11, v11, v14, 1.0
v_dual_fmaak_f32 v15, v12, v15, 0xbe2aaa9d :: v_dual_lshlrev_b32 v10, 30, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v8, v11, v8 :: v_dual_mul_f32 v15, v12, v15
v_fma_f32 v12, v12, v17, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v13
v_and_b32_e32 v9, 0x80000000, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor3_b32 v7, v7, v16, v8
v_fmac_f32_e32 v5, v5, v15
v_cndmask_b32_e64 v5, -v5, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v8, v9, v5
v_mad_u64_u32 v[5:6], null, v4, s4, v[2:3]
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, 1.0
v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 4, v[5:6]
v_mul_f32_e32 v0, v7, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, 0.5, v0
global_store_b128 v[5:6], v[1:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, .Lfunc_end0-_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeVertices_kernel(float4* pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int y = blockIdx.x * blockDim.x + threadIdx.x;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0 - 1.0f;
v = v*2.0 - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sin(u*freq + time) * cos(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | .text
.file "computeVertices_kernel.hip"
.globl _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf # -- Begin function _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.p2align 4, 0x90
.type _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf,@function
_Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf: # @_Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, .Lfunc_end0-_Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf,@object # @_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.section .rodata,"a",@progbits
.globl _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.p2align 3, 0x0
_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf:
.quad _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.size _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013d0af_00000000-6_computeVertices_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf
.type _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf, @function
_Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22computeVertices_kernelP6float4jjf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf, .-_Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf
.globl _Z22computeVertices_kernelP6float4jjf
.type _Z22computeVertices_kernelP6float4jjf, @function
_Z22computeVertices_kernelP6float4jjf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22computeVertices_kernelP6float4jjfP6float4jjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22computeVertices_kernelP6float4jjf, .-_Z22computeVertices_kernelP6float4jjf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22computeVertices_kernelP6float4jjf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22computeVertices_kernelP6float4jjf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computeVertices_kernel.hip"
.globl _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf # -- Begin function _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.p2align 4, 0x90
.type _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf,@function
_Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf: # @_Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, .Lfunc_end0-_Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf,@object # @_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.section .rodata,"a",@progbits
.globl _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.p2align 3, 0x0
_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf:
.quad _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.size _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22computeVertices_kernelP15HIP_vector_typeIfLj4EEjjf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
// utility function provided by https://gist.github.com/jefflarkin/5390993
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s' (err: %d)\n",__FILE__,__LINE__,cudaGetErrorString(e), e); \
exit(0); \
} \
}
class cuStopwatch{
public:
cuStopwatch();
~cuStopwatch();
void start();
float stop();
private:
float elapsedTime;
bool started;
cudaEvent_t startTime;
cudaEvent_t endTime;
};
cuStopwatch::cuStopwatch(){
started = false;
elapsedTime = 0;
cudaError_t res = cudaEventCreate(&startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
res = cudaEventCreate(&endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
}
cuStopwatch::~cuStopwatch(){
cudaEventDestroy(startTime);
cudaEventDestroy(endTime);
}
void cuStopwatch::start(){
if (started) {
return;
}
cudaError_t res = cudaEventRecord(startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
started = true;
}
float cuStopwatch::stop(){
if (! started) {
return 0;
}
cudaError_t res = cudaEventRecord(endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
cudaEventSynchronize(endTime); /*cudaCheckError();*/
res = cudaEventElapsedTime(&elapsedTime, startTime, endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when computing elapsed time : %d\n", res);
started = false;
return elapsedTime;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
// utility function provided by https://gist.github.com/jefflarkin/5390993
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s' (err: %d)\n",__FILE__,__LINE__,cudaGetErrorString(e), e); \
exit(0); \
} \
}
class cuStopwatch{
public:
cuStopwatch();
~cuStopwatch();
void start();
float stop();
private:
float elapsedTime;
bool started;
cudaEvent_t startTime;
cudaEvent_t endTime;
};
cuStopwatch::cuStopwatch(){
started = false;
elapsedTime = 0;
cudaError_t res = cudaEventCreate(&startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
res = cudaEventCreate(&endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
}
cuStopwatch::~cuStopwatch(){
cudaEventDestroy(startTime);
cudaEventDestroy(endTime);
}
void cuStopwatch::start(){
if (started) {
return;
}
cudaError_t res = cudaEventRecord(startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
started = true;
}
float cuStopwatch::stop(){
if (! started) {
return 0;
}
cudaError_t res = cudaEventRecord(endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
cudaEventSynchronize(endTime); /*cudaCheckError();*/
res = cudaEventElapsedTime(&elapsedTime, startTime, endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when computing elapsed time : %d\n", res);
started = false;
return elapsedTime;
} | .file "tmpxft_001a0eec_00000000-6_cuStopwatch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Return code when recording startTime : %d\n"
.align 8
.LC2:
.string "Return code when recording endTime : %d\n"
.text
.align 2
.globl _ZN11cuStopwatchC2Ev
.type _ZN11cuStopwatchC2Ev, @function
_ZN11cuStopwatchC2Ev:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movb $0, 4(%rdi)
movl $0x00000000, (%rdi)
leaq 8(%rdi), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L7
.L4:
leaq 16(%rbx), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L8
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2058:
.size _ZN11cuStopwatchC2Ev, .-_ZN11cuStopwatchC2Ev
.globl _ZN11cuStopwatchC1Ev
.set _ZN11cuStopwatchC1Ev,_ZN11cuStopwatchC2Ev
.align 2
.globl _ZN11cuStopwatchD2Ev
.type _ZN11cuStopwatchD2Ev, @function
_ZN11cuStopwatchD2Ev:
.LFB2061:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2061
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
call cudaEventDestroy@PLT
movq 16(%rbx), %rdi
call cudaEventDestroy@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2061:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2061-.LLSDACSB2061
.LLSDACSB2061:
.LLSDACSE2061:
.text
.size _ZN11cuStopwatchD2Ev, .-_ZN11cuStopwatchD2Ev
.globl _ZN11cuStopwatchD1Ev
.set _ZN11cuStopwatchD1Ev,_ZN11cuStopwatchD2Ev
.align 2
.globl _ZN11cuStopwatch5startEv
.type _ZN11cuStopwatch5startEv, @function
_ZN11cuStopwatch5startEv:
.LFB2063:
.cfi_startproc
endbr64
cmpb $0, 4(%rdi)
je .L18
ret
.L18:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
movl $0, %esi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L19
.L13:
movb $1, 4(%rbx)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2063:
.size _ZN11cuStopwatch5startEv, .-_ZN11cuStopwatch5startEv
.section .rodata.str1.8
.align 8
.LC3:
.string "Return code when computing elapsed time : %d\n"
.text
.align 2
.globl _ZN11cuStopwatch4stopEv
.type _ZN11cuStopwatch4stopEv, @function
_ZN11cuStopwatch4stopEv:
.LFB2064:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cmpb $0, 4(%rdi)
jne .L29
ret
.L29:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
movl $0, %esi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L30
.L22:
movq 16(%rbx), %rdi
call cudaEventSynchronize@PLT
movq 16(%rbx), %rdx
movq 8(%rbx), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L31
.L23:
movb $0, 4(%rbx)
movss (%rbx), %xmm0
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L31:
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.cfi_endproc
.LFE2064:
.size _ZN11cuStopwatch4stopEv, .-_ZN11cuStopwatch4stopEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
// utility function provided by https://gist.github.com/jefflarkin/5390993
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s' (err: %d)\n",__FILE__,__LINE__,cudaGetErrorString(e), e); \
exit(0); \
} \
}
class cuStopwatch{
public:
cuStopwatch();
~cuStopwatch();
void start();
float stop();
private:
float elapsedTime;
bool started;
cudaEvent_t startTime;
cudaEvent_t endTime;
};
cuStopwatch::cuStopwatch(){
started = false;
elapsedTime = 0;
cudaError_t res = cudaEventCreate(&startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
res = cudaEventCreate(&endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
}
cuStopwatch::~cuStopwatch(){
cudaEventDestroy(startTime);
cudaEventDestroy(endTime);
}
void cuStopwatch::start(){
if (started) {
return;
}
cudaError_t res = cudaEventRecord(startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
started = true;
}
float cuStopwatch::stop(){
if (! started) {
return 0;
}
cudaError_t res = cudaEventRecord(endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
cudaEventSynchronize(endTime); /*cudaCheckError();*/
res = cudaEventElapsedTime(&elapsedTime, startTime, endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when computing elapsed time : %d\n", res);
started = false;
return elapsedTime;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// utility function provided by https://gist.github.com/jefflarkin/5390993
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s' (err: %d)\n",__FILE__,__LINE__,hipGetErrorString(e), e); \
exit(0); \
} \
}
class cuStopwatch{
public:
cuStopwatch();
~cuStopwatch();
void start();
float stop();
private:
float elapsedTime;
bool started;
hipEvent_t startTime;
hipEvent_t endTime;
};
cuStopwatch::cuStopwatch(){
started = false;
elapsedTime = 0;
hipError_t res = hipEventCreate(&startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
res = hipEventCreate(&endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
}
cuStopwatch::~cuStopwatch(){
hipEventDestroy(startTime);
hipEventDestroy(endTime);
}
void cuStopwatch::start(){
if (started) {
return;
}
hipError_t res = hipEventRecord(startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
started = true;
}
float cuStopwatch::stop(){
if (! started) {
return 0;
}
hipError_t res = hipEventRecord(endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
hipEventSynchronize(endTime); /*cudaCheckError();*/
res = hipEventElapsedTime(&elapsedTime, startTime, endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when computing elapsed time : %d\n", res);
started = false;
return elapsedTime;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// utility function provided by https://gist.github.com/jefflarkin/5390993
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s' (err: %d)\n",__FILE__,__LINE__,hipGetErrorString(e), e); \
exit(0); \
} \
}
class cuStopwatch{
public:
cuStopwatch();
~cuStopwatch();
void start();
float stop();
private:
float elapsedTime;
bool started;
hipEvent_t startTime;
hipEvent_t endTime;
};
cuStopwatch::cuStopwatch(){
started = false;
elapsedTime = 0;
hipError_t res = hipEventCreate(&startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
res = hipEventCreate(&endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
}
cuStopwatch::~cuStopwatch(){
hipEventDestroy(startTime);
hipEventDestroy(endTime);
}
void cuStopwatch::start(){
if (started) {
return;
}
hipError_t res = hipEventRecord(startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
started = true;
}
float cuStopwatch::stop(){
if (! started) {
return 0;
}
hipError_t res = hipEventRecord(endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
hipEventSynchronize(endTime); /*cudaCheckError();*/
res = hipEventElapsedTime(&elapsedTime, startTime, endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when computing elapsed time : %d\n", res);
started = false;
return elapsedTime;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// utility function provided by https://gist.github.com/jefflarkin/5390993
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s' (err: %d)\n",__FILE__,__LINE__,hipGetErrorString(e), e); \
exit(0); \
} \
}
class cuStopwatch{
public:
cuStopwatch();
~cuStopwatch();
void start();
float stop();
private:
float elapsedTime;
bool started;
hipEvent_t startTime;
hipEvent_t endTime;
};
cuStopwatch::cuStopwatch(){
started = false;
elapsedTime = 0;
hipError_t res = hipEventCreate(&startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
res = hipEventCreate(&endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
}
cuStopwatch::~cuStopwatch(){
hipEventDestroy(startTime);
hipEventDestroy(endTime);
}
void cuStopwatch::start(){
if (started) {
return;
}
hipError_t res = hipEventRecord(startTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording startTime : %d\n", res);
started = true;
}
float cuStopwatch::stop(){
if (! started) {
return 0;
}
hipError_t res = hipEventRecord(endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when recording endTime : %d\n", res);
hipEventSynchronize(endTime); /*cudaCheckError();*/
res = hipEventElapsedTime(&elapsedTime, startTime, endTime); /*cudaCheckError();*/
if (res != 0)
printf("Return code when computing elapsed time : %d\n", res);
started = false;
return elapsedTime;
} | .text
.file "cuStopwatch.hip"
.globl _ZN11cuStopwatchC2Ev # -- Begin function _ZN11cuStopwatchC2Ev
.p2align 4, 0x90
.type _ZN11cuStopwatchC2Ev,@function
_ZN11cuStopwatchC2Ev: # @_ZN11cuStopwatchC2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movb $0, 4(%rdi)
movl $0, (%rdi)
addq $8, %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
addq $16, %rbx
movq %rbx, %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB0_3
# %bb.4:
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_3:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN11cuStopwatchC2Ev, .Lfunc_end0-_ZN11cuStopwatchC2Ev
.cfi_endproc
# -- End function
.globl _ZN11cuStopwatchD2Ev # -- Begin function _ZN11cuStopwatchD2Ev
.p2align 4, 0x90
.type _ZN11cuStopwatchD2Ev,@function
_ZN11cuStopwatchD2Ev: # @_ZN11cuStopwatchD2Ev
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
.Ltmp0:
callq hipEventDestroy
.Ltmp1:
# %bb.1:
movq 16(%rbx), %rdi
.Ltmp2:
callq hipEventDestroy
.Ltmp3:
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 16
.Ltmp4:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size _ZN11cuStopwatchD2Ev, .Lfunc_end1-_ZN11cuStopwatchD2Ev
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 1 # On action: 1
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.globl _ZN11cuStopwatch5startEv # -- Begin function _ZN11cuStopwatch5startEv
.p2align 4, 0x90
.type _ZN11cuStopwatch5startEv,@function
_ZN11cuStopwatch5startEv: # @_ZN11cuStopwatch5startEv
.cfi_startproc
# %bb.0:
cmpb $0, 4(%rdi)
je .LBB3_1
# %bb.4:
retq
.LBB3_1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
je .LBB3_3
# %bb.2:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB3_3:
movb $1, 4(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.Lfunc_end3:
.size _ZN11cuStopwatch5startEv, .Lfunc_end3-_ZN11cuStopwatch5startEv
.cfi_endproc
# -- End function
.globl _ZN11cuStopwatch4stopEv # -- Begin function _ZN11cuStopwatch4stopEv
.p2align 4, 0x90
.type _ZN11cuStopwatch4stopEv,@function
_ZN11cuStopwatch4stopEv: # @_ZN11cuStopwatch4stopEv
.cfi_startproc
# %bb.0:
cmpb $0, 4(%rdi)
je .LBB4_1
# %bb.2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
je .LBB4_4
# %bb.3:
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_4:
movq 16(%rbx), %rdi
callq hipEventSynchronize
movq 8(%rbx), %rsi
movq 16(%rbx), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_6:
movb $0, 4(%rbx)
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _ZN11cuStopwatch4stopEv, .Lfunc_end4-_ZN11cuStopwatch4stopEv
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Return code when recording startTime : %d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Return code when recording endTime : %d\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Return code when computing elapsed time : %d\n"
.size .L.str.2, 46
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN11cuStopwatchC1Ev
.type _ZN11cuStopwatchC1Ev,@function
.set _ZN11cuStopwatchC1Ev, _ZN11cuStopwatchC2Ev
.globl _ZN11cuStopwatchD1Ev
.type _ZN11cuStopwatchD1Ev,@function
.set _ZN11cuStopwatchD1Ev, _ZN11cuStopwatchD2Ev
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a0eec_00000000-6_cuStopwatch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Return code when recording startTime : %d\n"
.align 8
.LC2:
.string "Return code when recording endTime : %d\n"
.text
.align 2
.globl _ZN11cuStopwatchC2Ev
.type _ZN11cuStopwatchC2Ev, @function
_ZN11cuStopwatchC2Ev:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movb $0, 4(%rdi)
movl $0x00000000, (%rdi)
leaq 8(%rdi), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L7
.L4:
leaq 16(%rbx), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L8
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2058:
.size _ZN11cuStopwatchC2Ev, .-_ZN11cuStopwatchC2Ev
.globl _ZN11cuStopwatchC1Ev
.set _ZN11cuStopwatchC1Ev,_ZN11cuStopwatchC2Ev
.align 2
.globl _ZN11cuStopwatchD2Ev
.type _ZN11cuStopwatchD2Ev, @function
_ZN11cuStopwatchD2Ev:
.LFB2061:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2061
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
call cudaEventDestroy@PLT
movq 16(%rbx), %rdi
call cudaEventDestroy@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2061:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2061-.LLSDACSB2061
.LLSDACSB2061:
.LLSDACSE2061:
.text
.size _ZN11cuStopwatchD2Ev, .-_ZN11cuStopwatchD2Ev
.globl _ZN11cuStopwatchD1Ev
.set _ZN11cuStopwatchD1Ev,_ZN11cuStopwatchD2Ev
.align 2
.globl _ZN11cuStopwatch5startEv
.type _ZN11cuStopwatch5startEv, @function
_ZN11cuStopwatch5startEv:
.LFB2063:
.cfi_startproc
endbr64
cmpb $0, 4(%rdi)
je .L18
ret
.L18:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
movl $0, %esi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L19
.L13:
movb $1, 4(%rbx)
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %eax, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE2063:
.size _ZN11cuStopwatch5startEv, .-_ZN11cuStopwatch5startEv
.section .rodata.str1.8
.align 8
.LC3:
.string "Return code when computing elapsed time : %d\n"
.text
.align 2
.globl _ZN11cuStopwatch4stopEv
.type _ZN11cuStopwatch4stopEv, @function
_ZN11cuStopwatch4stopEv:
.LFB2064:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cmpb $0, 4(%rdi)
jne .L29
ret
.L29:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
movl $0, %esi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L30
.L22:
movq 16(%rbx), %rdi
call cudaEventSynchronize@PLT
movq 16(%rbx), %rdx
movq 8(%rbx), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L31
.L23:
movb $0, 4(%rbx)
movss (%rbx), %xmm0
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L31:
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.cfi_endproc
.LFE2064:
.size _ZN11cuStopwatch4stopEv, .-_ZN11cuStopwatch4stopEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuStopwatch.hip"
.globl _ZN11cuStopwatchC2Ev # -- Begin function _ZN11cuStopwatchC2Ev
.p2align 4, 0x90
.type _ZN11cuStopwatchC2Ev,@function
_ZN11cuStopwatchC2Ev: # @_ZN11cuStopwatchC2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movb $0, 4(%rdi)
movl $0, (%rdi)
addq $8, %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
addq $16, %rbx
movq %rbx, %rdi
callq hipEventCreate
testl %eax, %eax
je .LBB0_3
# %bb.4:
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB0_3:
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN11cuStopwatchC2Ev, .Lfunc_end0-_ZN11cuStopwatchC2Ev
.cfi_endproc
# -- End function
.globl _ZN11cuStopwatchD2Ev # -- Begin function _ZN11cuStopwatchD2Ev
.p2align 4, 0x90
.type _ZN11cuStopwatchD2Ev,@function
_ZN11cuStopwatchD2Ev: # @_ZN11cuStopwatchD2Ev
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
.Ltmp0:
callq hipEventDestroy
.Ltmp1:
# %bb.1:
movq 16(%rbx), %rdi
.Ltmp2:
callq hipEventDestroy
.Ltmp3:
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 16
.Ltmp4:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end1:
.size _ZN11cuStopwatchD2Ev, .Lfunc_end1-_ZN11cuStopwatchD2Ev
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 1 # On action: 1
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.text
.globl _ZN11cuStopwatch5startEv # -- Begin function _ZN11cuStopwatch5startEv
.p2align 4, 0x90
.type _ZN11cuStopwatch5startEv,@function
_ZN11cuStopwatch5startEv: # @_ZN11cuStopwatch5startEv
.cfi_startproc
# %bb.0:
cmpb $0, 4(%rdi)
je .LBB3_1
# %bb.4:
retq
.LBB3_1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
je .LBB3_3
# %bb.2:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB3_3:
movb $1, 4(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.Lfunc_end3:
.size _ZN11cuStopwatch5startEv, .Lfunc_end3-_ZN11cuStopwatch5startEv
.cfi_endproc
# -- End function
.globl _ZN11cuStopwatch4stopEv # -- Begin function _ZN11cuStopwatch4stopEv
.p2align 4, 0x90
.type _ZN11cuStopwatch4stopEv,@function
_ZN11cuStopwatch4stopEv: # @_ZN11cuStopwatch4stopEv
.cfi_startproc
# %bb.0:
cmpb $0, 4(%rdi)
je .LBB4_1
# %bb.2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 16(%rdi), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
je .LBB4_4
# %bb.3:
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_4:
movq 16(%rbx), %rdi
callq hipEventSynchronize
movq 8(%rbx), %rsi
movq 16(%rbx), %rdx
movq %rbx, %rdi
callq hipEventElapsedTime
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_6:
movb $0, 4(%rbx)
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.LBB4_1:
xorps %xmm0, %xmm0
retq
.Lfunc_end4:
.size _ZN11cuStopwatch4stopEv, .Lfunc_end4-_ZN11cuStopwatch4stopEv
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Return code when recording startTime : %d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Return code when recording endTime : %d\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Return code when computing elapsed time : %d\n"
.size .L.str.2, 46
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN11cuStopwatchC1Ev
.type _ZN11cuStopwatchC1Ev,@function
.set _ZN11cuStopwatchC1Ev, _ZN11cuStopwatchC2Ev
.globl _ZN11cuStopwatchD1Ev
.type _ZN11cuStopwatchD1Ev,@function
.set _ZN11cuStopwatchD1Ev, _ZN11cuStopwatchD2Ev
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void cuda_hello(){
printf("Hello from your GPU\n");
}
int main(void){
cuda_hello<<<1,1>>>();
return 0;
} | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void cuda_hello(){
printf("Hello from your GPU\n");
}
int main(void){
cuda_hello<<<1,1>>>();
return 0;
} | .file "tmpxft_0019d02a_00000000-6_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void cuda_hello(){
printf("Hello from your GPU\n");
}
int main(void){
cuda_hello<<<1,1>>>();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello from your GPU\n");
}
int main(void){
cuda_hello<<<1,1>>>();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello from your GPU\n");
}
int main(void){
cuda_hello<<<1,1>>>();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 21
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello from your GPU\n"
.size .str, 21
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void cuda_hello(){
printf("Hello from your GPU\n");
}
int main(void){
cuda_hello<<<1,1>>>();
return 0;
} | .text
.file "device.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 21
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello from your GPU\n"
.size .str, 21
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d02a_00000000-6_device.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
} | code for sm_80
Function : _Z21globalMemOffsetKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
} | .file "tmpxft_000c6952_00000000-6_globalMemOffsetKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z21globalMemOffsetKernelvv
.type _Z40__device_stub__Z21globalMemOffsetKernelvv, @function
_Z40__device_stub__Z21globalMemOffsetKernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z21globalMemOffsetKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z21globalMemOffsetKernelvv, .-_Z40__device_stub__Z21globalMemOffsetKernelvv
.globl _Z21globalMemOffsetKernelv
.type _Z21globalMemOffsetKernelv, @function
_Z21globalMemOffsetKernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z21globalMemOffsetKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21globalMemOffsetKernelv, .-_Z21globalMemOffsetKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21globalMemOffsetKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21globalMemOffsetKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21globalMemOffsetKernelv
.globl _Z21globalMemOffsetKernelv
.p2align 8
.type _Z21globalMemOffsetKernelv,@function
_Z21globalMemOffsetKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21globalMemOffsetKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21globalMemOffsetKernelv, .Lfunc_end0-_Z21globalMemOffsetKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21globalMemOffsetKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z21globalMemOffsetKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
} | .text
.file "globalMemOffsetKernel.hip"
.globl _Z36__device_stub__globalMemOffsetKernelv # -- Begin function _Z36__device_stub__globalMemOffsetKernelv
.p2align 4, 0x90
.type _Z36__device_stub__globalMemOffsetKernelv,@function
_Z36__device_stub__globalMemOffsetKernelv: # @_Z36__device_stub__globalMemOffsetKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemOffsetKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z36__device_stub__globalMemOffsetKernelv, .Lfunc_end0-_Z36__device_stub__globalMemOffsetKernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21globalMemOffsetKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21globalMemOffsetKernelv,@object # @_Z21globalMemOffsetKernelv
.section .rodata,"a",@progbits
.globl _Z21globalMemOffsetKernelv
.p2align 3, 0x0
_Z21globalMemOffsetKernelv:
.quad _Z36__device_stub__globalMemOffsetKernelv
.size _Z21globalMemOffsetKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21globalMemOffsetKernelv"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__globalMemOffsetKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21globalMemOffsetKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21globalMemOffsetKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21globalMemOffsetKernelv
.globl _Z21globalMemOffsetKernelv
.p2align 8
.type _Z21globalMemOffsetKernelv,@function
_Z21globalMemOffsetKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21globalMemOffsetKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21globalMemOffsetKernelv, .Lfunc_end0-_Z21globalMemOffsetKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21globalMemOffsetKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z21globalMemOffsetKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6952_00000000-6_globalMemOffsetKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z21globalMemOffsetKernelvv
.type _Z40__device_stub__Z21globalMemOffsetKernelvv, @function
_Z40__device_stub__Z21globalMemOffsetKernelvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z21globalMemOffsetKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z21globalMemOffsetKernelvv, .-_Z40__device_stub__Z21globalMemOffsetKernelvv
.globl _Z21globalMemOffsetKernelv
.type _Z21globalMemOffsetKernelv, @function
_Z21globalMemOffsetKernelv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z21globalMemOffsetKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21globalMemOffsetKernelv, .-_Z21globalMemOffsetKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21globalMemOffsetKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21globalMemOffsetKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "globalMemOffsetKernel.hip"
.globl _Z36__device_stub__globalMemOffsetKernelv # -- Begin function _Z36__device_stub__globalMemOffsetKernelv
.p2align 4, 0x90
.type _Z36__device_stub__globalMemOffsetKernelv,@function
_Z36__device_stub__globalMemOffsetKernelv: # @_Z36__device_stub__globalMemOffsetKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemOffsetKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z36__device_stub__globalMemOffsetKernelv, .Lfunc_end0-_Z36__device_stub__globalMemOffsetKernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21globalMemOffsetKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21globalMemOffsetKernelv,@object # @_Z21globalMemOffsetKernelv
.section .rodata,"a",@progbits
.globl _Z21globalMemOffsetKernelv
.p2align 3, 0x0
_Z21globalMemOffsetKernelv:
.quad _Z36__device_stub__globalMemOffsetKernelv
.size _Z21globalMemOffsetKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21globalMemOffsetKernelv"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__globalMemOffsetKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21globalMemOffsetKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#define SIZE 10
int main(int argc,char *argv[]){
if(argc<3){
printf("Usage: ./test.cu <ptx_file> <cuda_device>\n");
exit(0);
}
// Error code
CUresult error;
int i;
// Host variables
float *h_A, *h_B, *h_C;
h_A = (float *)malloc(sizeof(float)*SIZE);
h_B = (float *)malloc(sizeof(float)*SIZE);
h_C = (float *)malloc(sizeof(float)*SIZE);
for (i=0;i<SIZE;i++){
h_A[i] = 12;
h_B[i] = i;
h_C[i] = 0;
}
// Initialize driver API
error = cuInit(0);
if((int)error!=0){
printf("Error! cuInit returned: %d\n",(int)error);
exit(0);
}
// Get Cuda Device and give handle
CUdevice cu_device;
error = cuDeviceGet(&cu_device,atoi(argv[2]));
if((int)error!=0){
printf("Error! cuDeviceGet returned: %d\n",(int)error);
exit(0);
}
// Create context to run on device
CUcontext cu_context;
error = cuCtxCreate(&cu_context, 0, cu_device);
if((int)error!=0){
printf("Error! cuCtxCreate returned: %d\n",(int)error);
exit(0);
}
// Load ptx code
CUmodule cu_module;
error = cuModuleLoad(&cu_module,argv[1]);
if((int)error!=0){
printf("Error! cuModuleLoad returned: %d\n",(int)error);
exit(0);
}
// Get kernel function
CUfunction func;
error = cuModuleGetFunction(&func,cu_module,"VectorAdd");
if((int)error!=0){
printf("Error! cuModuleGetFunction returned: %d\n",(int)error);
exit(0);
}
CUdeviceptr var1,var2,var3;
// Allocate device memory
unsigned int size = sizeof(float)*SIZE;
error = cuMemAlloc(&var1, size);
error = cuMemAlloc(&var2, size);
error = cuMemAlloc(&var3, size);
if((int)error!=0){
printf("Error! cuMemAlloc returned: %d\n",(int)error);
exit(0);
}
// Copy variables to host
error = cuMemcpyHtoD(var1,h_C,size);
error = cuMemcpyHtoD(var2,h_A,size);
error = cuMemcpyHtoD(var3,h_B,size);
if((int)error!=0){
printf("Error! cuMemcpyHtoD returned: %d\n",(int)error);
exit(0);
}
// Lauch kernel
void *args[] = {&var1, &var2, &var3};
error = cuLaunchKernel(func, 10, 1, 1, 1, 1, 1, 0, NULL, args, NULL);
if((int)error!=0){
printf("Error! cuLaunchKernel returned: %d\n",(int)error);
exit(0);
}
// Get result to host
error = cuMemcpyDtoH(h_C,var1,size);
if((int)error!=0){
printf("Error! cuMemcpyDtoH returned: %d\n",(int)error);
exit(0);
}
// Free device memory
error = cuMemFree(var1);
error = cuMemFree(var2);
error = cuMemFree(var3);
if((int)error!=0){
printf("Error! cuMemFree returned: %d\n",(int)error);
exit(0);
}
// Destroy context
error = cuCtxDestroy(cu_context);
if((int)error!=0){
printf("Error! cuCtxDestroy returned: %d\n",(int)error);
exit(0);
}
// Print result
for (i=0;i<SIZE;i++)
printf("%f\n",h_C[i]);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#define SIZE 10
int main(int argc,char *argv[]){
if(argc<3){
printf("Usage: ./test.cu <ptx_file> <cuda_device>\n");
exit(0);
}
// Error code
CUresult error;
int i;
// Host variables
float *h_A, *h_B, *h_C;
h_A = (float *)malloc(sizeof(float)*SIZE);
h_B = (float *)malloc(sizeof(float)*SIZE);
h_C = (float *)malloc(sizeof(float)*SIZE);
for (i=0;i<SIZE;i++){
h_A[i] = 12;
h_B[i] = i;
h_C[i] = 0;
}
// Initialize driver API
error = cuInit(0);
if((int)error!=0){
printf("Error! cuInit returned: %d\n",(int)error);
exit(0);
}
// Get Cuda Device and give handle
CUdevice cu_device;
error = cuDeviceGet(&cu_device,atoi(argv[2]));
if((int)error!=0){
printf("Error! cuDeviceGet returned: %d\n",(int)error);
exit(0);
}
// Create context to run on device
CUcontext cu_context;
error = cuCtxCreate(&cu_context, 0, cu_device);
if((int)error!=0){
printf("Error! cuCtxCreate returned: %d\n",(int)error);
exit(0);
}
// Load ptx code
CUmodule cu_module;
error = cuModuleLoad(&cu_module,argv[1]);
if((int)error!=0){
printf("Error! cuModuleLoad returned: %d\n",(int)error);
exit(0);
}
// Get kernel function
CUfunction func;
error = cuModuleGetFunction(&func,cu_module,"VectorAdd");
if((int)error!=0){
printf("Error! cuModuleGetFunction returned: %d\n",(int)error);
exit(0);
}
CUdeviceptr var1,var2,var3;
// Allocate device memory
unsigned int size = sizeof(float)*SIZE;
error = cuMemAlloc(&var1, size);
error = cuMemAlloc(&var2, size);
error = cuMemAlloc(&var3, size);
if((int)error!=0){
printf("Error! cuMemAlloc returned: %d\n",(int)error);
exit(0);
}
// Copy variables to host
error = cuMemcpyHtoD(var1,h_C,size);
error = cuMemcpyHtoD(var2,h_A,size);
error = cuMemcpyHtoD(var3,h_B,size);
if((int)error!=0){
printf("Error! cuMemcpyHtoD returned: %d\n",(int)error);
exit(0);
}
// Lauch kernel
void *args[] = {&var1, &var2, &var3};
error = cuLaunchKernel(func, 10, 1, 1, 1, 1, 1, 0, NULL, args, NULL);
if((int)error!=0){
printf("Error! cuLaunchKernel returned: %d\n",(int)error);
exit(0);
}
// Get result to host
error = cuMemcpyDtoH(h_C,var1,size);
if((int)error!=0){
printf("Error! cuMemcpyDtoH returned: %d\n",(int)error);
exit(0);
}
// Free device memory
error = cuMemFree(var1);
error = cuMemFree(var2);
error = cuMemFree(var3);
if((int)error!=0){
printf("Error! cuMemFree returned: %d\n",(int)error);
exit(0);
}
// Destroy context
error = cuCtxDestroy(cu_context);
if((int)error!=0){
printf("Error! cuCtxDestroy returned: %d\n",(int)error);
exit(0);
}
// Print result
for (i=0;i<SIZE;i++)
printf("%f\n",h_C[i]);
} | .file "tmpxft_0006b864_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: ./test.cu <ptx_file> <cuda_device>\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error! cuInit returned: %d\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Error! cuDeviceGet returned: %d\n"
.align 8
.LC5:
.string "Error! cuCtxCreate returned: %d\n"
.align 8
.LC6:
.string "Error! cuModuleLoad returned: %d\n"
.section .rodata.str1.1
.LC7:
.string "VectorAdd"
.section .rodata.str1.8
.align 8
.LC8:
.string "Error! cuModuleGetFunction returned: %d\n"
.align 8
.LC9:
.string "Error! cuMemAlloc returned: %d\n"
.align 8
.LC10:
.string "Error! cuMemcpyHtoD returned: %d\n"
.align 8
.LC11:
.string "Error! cuLaunchKernel returned: %d\n"
.align 8
.LC12:
.string "Error! cuMemcpyDtoH returned: %d\n"
.align 8
.LC13:
.string "Error! cuMemFree returned: %d\n"
.align 8
.LC14:
.string "Error! cuCtxDestroy returned: %d\n"
.section .rodata.str1.1
.LC15:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jg .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L4:
movq %rsi, %r13
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movss .LC1(%rip), %xmm1
.L5:
movss %xmm1, (%r12,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L5
movl $0, %edi
call cuInit@PLT
testl %eax, %eax
je .L6
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L6:
movq 16(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leaq 12(%rsp), %rdi
movl %eax, %esi
call cuDeviceGet@PLT
testl %eax, %eax
je .L7
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L7:
leaq 16(%rsp), %rdi
movl 12(%rsp), %edx
movl $0, %esi
call cuCtxCreate_v2@PLT
testl %eax, %eax
je .L8
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L8:
movq 8(%r13), %rsi
leaq 24(%rsp), %rdi
call cuModuleLoad@PLT
testl %eax, %eax
je .L9
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L9:
leaq 32(%rsp), %rdi
leaq .LC7(%rip), %rdx
movq 24(%rsp), %rsi
call cuModuleGetFunction@PLT
testl %eax, %eax
je .L10
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L10:
leaq 40(%rsp), %rdi
movl $40, %esi
call cuMemAlloc_v2@PLT
leaq 48(%rsp), %rdi
movl $40, %esi
call cuMemAlloc_v2@PLT
leaq 56(%rsp), %rdi
movl $40, %esi
call cuMemAlloc_v2@PLT
testl %eax, %eax
je .L11
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L11:
movl $40, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cuMemcpyHtoD_v2@PLT
movl $40, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cuMemcpyHtoD_v2@PLT
movl $40, %edx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cuMemcpyHtoD_v2@PLT
movl %eax, %edx
testl %eax, %eax
je .L12
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq $0
.cfi_def_cfa_offset 160
leaq 80(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 168
pushq $0
.cfi_def_cfa_offset 176
pushq $0
.cfi_def_cfa_offset 184
pushq $1
.cfi_def_cfa_offset 192
movl $1, %r9d
movl $1, %r8d
movl $1, %ecx
movl $1, %edx
movl $10, %esi
movq 80(%rsp), %rdi
call cuLaunchKernel@PLT
movl %eax, %edx
addq $48, %rsp
.cfi_def_cfa_offset 144
testl %eax, %eax
je .L13
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movl $40, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cuMemcpyDtoH_v2@PLT
movl %eax, %edx
testl %eax, %eax
je .L14
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L14:
movq 40(%rsp), %rdi
call cuMemFree_v2@PLT
movq 48(%rsp), %rdi
call cuMemFree_v2@PLT
movq 56(%rsp), %rdi
call cuMemFree_v2@PLT
movl %eax, %edx
testl %eax, %eax
je .L15
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L15:
movq 16(%rsp), %rdi
call cuCtxDestroy_v2@PLT
movl %eax, %edx
movl $0, %ebp
leaq .LC15(%rip), %r12
testl %eax, %eax
jne .L23
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%rbp,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq $10, %rbp
jne .L16
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1094713344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#define SIZE 10
int main(int argc,char *argv[]){
if(argc<3){
printf("Usage: ./test.cu <ptx_file> <cuda_device>\n");
exit(0);
}
// Error code
CUresult error;
int i;
// Host variables
float *h_A, *h_B, *h_C;
h_A = (float *)malloc(sizeof(float)*SIZE);
h_B = (float *)malloc(sizeof(float)*SIZE);
h_C = (float *)malloc(sizeof(float)*SIZE);
for (i=0;i<SIZE;i++){
h_A[i] = 12;
h_B[i] = i;
h_C[i] = 0;
}
// Initialize driver API
error = cuInit(0);
if((int)error!=0){
printf("Error! cuInit returned: %d\n",(int)error);
exit(0);
}
// Get Cuda Device and give handle
CUdevice cu_device;
error = cuDeviceGet(&cu_device,atoi(argv[2]));
if((int)error!=0){
printf("Error! cuDeviceGet returned: %d\n",(int)error);
exit(0);
}
// Create context to run on device
CUcontext cu_context;
error = cuCtxCreate(&cu_context, 0, cu_device);
if((int)error!=0){
printf("Error! cuCtxCreate returned: %d\n",(int)error);
exit(0);
}
// Load ptx code
CUmodule cu_module;
error = cuModuleLoad(&cu_module,argv[1]);
if((int)error!=0){
printf("Error! cuModuleLoad returned: %d\n",(int)error);
exit(0);
}
// Get kernel function
CUfunction func;
error = cuModuleGetFunction(&func,cu_module,"VectorAdd");
if((int)error!=0){
printf("Error! cuModuleGetFunction returned: %d\n",(int)error);
exit(0);
}
CUdeviceptr var1,var2,var3;
// Allocate device memory
unsigned int size = sizeof(float)*SIZE;
error = cuMemAlloc(&var1, size);
error = cuMemAlloc(&var2, size);
error = cuMemAlloc(&var3, size);
if((int)error!=0){
printf("Error! cuMemAlloc returned: %d\n",(int)error);
exit(0);
}
// Copy variables to host
error = cuMemcpyHtoD(var1,h_C,size);
error = cuMemcpyHtoD(var2,h_A,size);
error = cuMemcpyHtoD(var3,h_B,size);
if((int)error!=0){
printf("Error! cuMemcpyHtoD returned: %d\n",(int)error);
exit(0);
}
// Lauch kernel
void *args[] = {&var1, &var2, &var3};
error = cuLaunchKernel(func, 10, 1, 1, 1, 1, 1, 0, NULL, args, NULL);
if((int)error!=0){
printf("Error! cuLaunchKernel returned: %d\n",(int)error);
exit(0);
}
// Get result to host
error = cuMemcpyDtoH(h_C,var1,size);
if((int)error!=0){
printf("Error! cuMemcpyDtoH returned: %d\n",(int)error);
exit(0);
}
// Free device memory
error = cuMemFree(var1);
error = cuMemFree(var2);
error = cuMemFree(var3);
if((int)error!=0){
printf("Error! cuMemFree returned: %d\n",(int)error);
exit(0);
}
// Destroy context
error = cuCtxDestroy(cu_context);
if((int)error!=0){
printf("Error! cuCtxDestroy returned: %d\n",(int)error);
exit(0);
}
// Print result
for (i=0;i<SIZE;i++)
printf("%f\n",h_C[i]);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 10
int main(int argc,char *argv[]){
if(argc<3){
printf("Usage: ./test.cu <ptx_file> <cuda_device>\n");
exit(0);
}
// Error code
hipError_t error;
int i;
// Host variables
float *h_A, *h_B, *h_C;
h_A = (float *)malloc(sizeof(float)*SIZE);
h_B = (float *)malloc(sizeof(float)*SIZE);
h_C = (float *)malloc(sizeof(float)*SIZE);
for (i=0;i<SIZE;i++){
h_A[i] = 12;
h_B[i] = i;
h_C[i] = 0;
}
// Initialize driver API
error = hipInit(0);
if((int)error!=0){
printf("Error! hipInit returned: %d\n",(int)error);
exit(0);
}
// Get Cuda Device and give handle
hipDevice_t cu_device;
error = hipDeviceGet(&cu_device,atoi(argv[2]));
if((int)error!=0){
printf("Error! hipDeviceGet returned: %d\n",(int)error);
exit(0);
}
// Create context to run on device
hipCtx_t cu_context;
error = hipCtxCreate(&cu_context, 0, cu_device);
if((int)error!=0){
printf("Error! hipCtxCreate returned: %d\n",(int)error);
exit(0);
}
// Load ptx code
hipModule_t cu_module;
error = hipModuleLoad(&cu_module,argv[1]);
if((int)error!=0){
printf("Error! hipModuleLoad returned: %d\n",(int)error);
exit(0);
}
// Get kernel function
hipFunction_t func;
error = hipModuleGetFunction(&func,cu_module,"VectorAdd");
if((int)error!=0){
printf("Error! hipModuleGetFunction returned: %d\n",(int)error);
exit(0);
}
hipDeviceptr_t var1,var2,var3;
// Allocate device memory
unsigned int size = sizeof(float)*SIZE;
error = hipMalloc(&var1, size);
error = hipMalloc(&var2, size);
error = hipMalloc(&var3, size);
if((int)error!=0){
printf("Error! hipMalloc returned: %d\n",(int)error);
exit(0);
}
// Copy variables to host
error = hipMemcpyHtoD(var1,h_C,size);
error = hipMemcpyHtoD(var2,h_A,size);
error = hipMemcpyHtoD(var3,h_B,size);
if((int)error!=0){
printf("Error! hipMemcpyHtoD returned: %d\n",(int)error);
exit(0);
}
// Lauch kernel
void *args[] = {&var1, &var2, &var3};
error = hipModuleLaunchKernel(func, 10, 1, 1, 1, 1, 1, 0, NULL, args, NULL);
if((int)error!=0){
printf("Error! hipModuleLaunchKernel returned: %d\n",(int)error);
exit(0);
}
// Get result to host
error = hipMemcpyDtoH(h_C,var1,size);
if((int)error!=0){
printf("Error! hipMemcpyDtoH returned: %d\n",(int)error);
exit(0);
}
// Free device memory
error = hipFree(var1);
error = hipFree(var2);
error = hipFree(var3);
if((int)error!=0){
printf("Error! hipFree returned: %d\n",(int)error);
exit(0);
}
// Destroy context
error = hipCtxDestroy(cu_context);
if((int)error!=0){
printf("Error! hipCtxDestroy returned: %d\n",(int)error);
exit(0);
}
// Print result
for (i=0;i<SIZE;i++)
printf("%f\n",h_C[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 10
int main(int argc,char *argv[]){
if(argc<3){
printf("Usage: ./test.cu <ptx_file> <cuda_device>\n");
exit(0);
}
// Error code
hipError_t error;
int i;
// Host variables
float *h_A, *h_B, *h_C;
h_A = (float *)malloc(sizeof(float)*SIZE);
h_B = (float *)malloc(sizeof(float)*SIZE);
h_C = (float *)malloc(sizeof(float)*SIZE);
for (i=0;i<SIZE;i++){
h_A[i] = 12;
h_B[i] = i;
h_C[i] = 0;
}
// Initialize driver API
error = hipInit(0);
if((int)error!=0){
printf("Error! hipInit returned: %d\n",(int)error);
exit(0);
}
// Get Cuda Device and give handle
hipDevice_t cu_device;
error = hipDeviceGet(&cu_device,atoi(argv[2]));
if((int)error!=0){
printf("Error! hipDeviceGet returned: %d\n",(int)error);
exit(0);
}
// Create context to run on device
hipCtx_t cu_context;
error = hipCtxCreate(&cu_context, 0, cu_device);
if((int)error!=0){
printf("Error! hipCtxCreate returned: %d\n",(int)error);
exit(0);
}
// Load ptx code
hipModule_t cu_module;
error = hipModuleLoad(&cu_module,argv[1]);
if((int)error!=0){
printf("Error! hipModuleLoad returned: %d\n",(int)error);
exit(0);
}
// Get kernel function
hipFunction_t func;
error = hipModuleGetFunction(&func,cu_module,"VectorAdd");
if((int)error!=0){
printf("Error! hipModuleGetFunction returned: %d\n",(int)error);
exit(0);
}
hipDeviceptr_t var1,var2,var3;
// Allocate device memory
unsigned int size = sizeof(float)*SIZE;
error = hipMalloc(&var1, size);
error = hipMalloc(&var2, size);
error = hipMalloc(&var3, size);
if((int)error!=0){
printf("Error! hipMalloc returned: %d\n",(int)error);
exit(0);
}
// Copy variables to host
error = hipMemcpyHtoD(var1,h_C,size);
error = hipMemcpyHtoD(var2,h_A,size);
error = hipMemcpyHtoD(var3,h_B,size);
if((int)error!=0){
printf("Error! hipMemcpyHtoD returned: %d\n",(int)error);
exit(0);
}
// Lauch kernel
void *args[] = {&var1, &var2, &var3};
error = hipModuleLaunchKernel(func, 10, 1, 1, 1, 1, 1, 0, NULL, args, NULL);
if((int)error!=0){
printf("Error! hipModuleLaunchKernel returned: %d\n",(int)error);
exit(0);
}
// Get result to host
error = hipMemcpyDtoH(h_C,var1,size);
if((int)error!=0){
printf("Error! hipMemcpyDtoH returned: %d\n",(int)error);
exit(0);
}
// Free device memory
error = hipFree(var1);
error = hipFree(var2);
error = hipFree(var3);
if((int)error!=0){
printf("Error! hipFree returned: %d\n",(int)error);
exit(0);
}
// Destroy context
error = hipCtxDestroy(cu_context);
if((int)error!=0){
printf("Error! hipCtxDestroy returned: %d\n",(int)error);
exit(0);
}
// Print result
for (i=0;i<SIZE;i++)
printf("%f\n",h_C[i]);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define SIZE 10
int main(int argc,char *argv[]){
if(argc<3){
printf("Usage: ./test.cu <ptx_file> <cuda_device>\n");
exit(0);
}
// Error code
hipError_t error;
int i;
// Host variables
float *h_A, *h_B, *h_C;
h_A = (float *)malloc(sizeof(float)*SIZE);
h_B = (float *)malloc(sizeof(float)*SIZE);
h_C = (float *)malloc(sizeof(float)*SIZE);
for (i=0;i<SIZE;i++){
h_A[i] = 12;
h_B[i] = i;
h_C[i] = 0;
}
// Initialize driver API
error = hipInit(0);
if((int)error!=0){
printf("Error! hipInit returned: %d\n",(int)error);
exit(0);
}
// Get Cuda Device and give handle
hipDevice_t cu_device;
error = hipDeviceGet(&cu_device,atoi(argv[2]));
if((int)error!=0){
printf("Error! hipDeviceGet returned: %d\n",(int)error);
exit(0);
}
// Create context to run on device
hipCtx_t cu_context;
error = hipCtxCreate(&cu_context, 0, cu_device);
if((int)error!=0){
printf("Error! hipCtxCreate returned: %d\n",(int)error);
exit(0);
}
// Load ptx code
hipModule_t cu_module;
error = hipModuleLoad(&cu_module,argv[1]);
if((int)error!=0){
printf("Error! hipModuleLoad returned: %d\n",(int)error);
exit(0);
}
// Get kernel function
hipFunction_t func;
error = hipModuleGetFunction(&func,cu_module,"VectorAdd");
if((int)error!=0){
printf("Error! hipModuleGetFunction returned: %d\n",(int)error);
exit(0);
}
hipDeviceptr_t var1,var2,var3;
// Allocate device memory
unsigned int size = sizeof(float)*SIZE;
error = hipMalloc(&var1, size);
error = hipMalloc(&var2, size);
error = hipMalloc(&var3, size);
if((int)error!=0){
printf("Error! hipMalloc returned: %d\n",(int)error);
exit(0);
}
// Copy variables to host
error = hipMemcpyHtoD(var1,h_C,size);
error = hipMemcpyHtoD(var2,h_A,size);
error = hipMemcpyHtoD(var3,h_B,size);
if((int)error!=0){
printf("Error! hipMemcpyHtoD returned: %d\n",(int)error);
exit(0);
}
// Lauch kernel
void *args[] = {&var1, &var2, &var3};
error = hipModuleLaunchKernel(func, 10, 1, 1, 1, 1, 1, 0, NULL, args, NULL);
if((int)error!=0){
printf("Error! hipModuleLaunchKernel returned: %d\n",(int)error);
exit(0);
}
// Get result to host
error = hipMemcpyDtoH(h_C,var1,size);
if((int)error!=0){
printf("Error! hipMemcpyDtoH returned: %d\n",(int)error);
exit(0);
}
// Free device memory
error = hipFree(var1);
error = hipFree(var2);
error = hipFree(var3);
if((int)error!=0){
printf("Error! hipFree returned: %d\n",(int)error);
exit(0);
}
// Destroy context
error = hipCtxDestroy(cu_context);
if((int)error!=0){
printf("Error! hipCtxDestroy returned: %d\n",(int)error);
exit(0);
}
// Print result
for (i=0;i<SIZE;i++)
printf("%f\n",h_C[i]);
} | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jle .LBB0_28
# %bb.1:
movq %rsi, %r12
movl $40, %edi
callq malloc
movq %rax, %r15
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl $1094713344, (%r15,%rax,4) # imm = 0x41400000
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_2
# %bb.3:
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB0_4
# %bb.6:
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leaq 20(%rsp), %rdi
movl %eax, %esi
callq hipDeviceGet
testl %eax, %eax
jne .LBB0_7
# %bb.8:
movl 20(%rsp), %edx
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq hipCtxCreate
testl %eax, %eax
jne .LBB0_9
# %bb.10:
movq 8(%r12), %rsi
leaq 48(%rsp), %rdi
callq hipModuleLoad
testl %eax, %eax
jne .LBB0_11
# %bb.12:
movq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
movl $.L.str.5, %edx
callq hipModuleGetFunction
testl %eax, %eax
jne .LBB0_13
# %bb.14:
leaq 8(%rsp), %r12
movl $40, %esi
movq %r12, %rdi
callq hipMalloc
leaq 32(%rsp), %r13
movl $40, %esi
movq %r13, %rdi
callq hipMalloc
leaq 24(%rsp), %rbp
movl $40, %esi
movq %rbp, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB0_15
# %bb.16:
movq 8(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
callq hipMemcpyHtoD
movq 32(%rsp), %rdi
movl $40, %edx
movq %r15, %rsi
callq hipMemcpyHtoD
movq 24(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
callq hipMemcpyHtoD
testl %eax, %eax
jne .LBB0_17
# %bb.18:
movq %r12, 64(%rsp)
movq %r13, 72(%rsp)
movq %rbp, 80(%rsp)
movq 40(%rsp), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 72(%rsp), %rax
movl $10, %esi
movl $1, %edx
movl $1, %ecx
movl $1, %r8d
movl $1, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipModuleLaunchKernel
addq $48, %rsp
.cfi_adjust_cfa_offset -48
testl %eax, %eax
jne .LBB0_19
# %bb.20:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
callq hipMemcpyDtoH
testl %eax, %eax
jne .LBB0_21
# %bb.22:
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_23
# %bb.24:
movq 56(%rsp), %rdi
callq hipCtxDestroy
testl %eax, %eax
jne .LBB0_29
# %bb.25: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_26: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB0_26
# %bb.27:
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_28:
.cfi_def_cfa_offset 144
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB0_4:
movl $.L.str.1, %edi
jmp .LBB0_5
.LBB0_7:
movl $.L.str.2, %edi
jmp .LBB0_5
.LBB0_9:
movl $.L.str.3, %edi
jmp .LBB0_5
.LBB0_11:
movl $.L.str.4, %edi
jmp .LBB0_5
.LBB0_13:
movl $.L.str.6, %edi
jmp .LBB0_5
.LBB0_15:
movl $.L.str.7, %edi
jmp .LBB0_5
.LBB0_17:
movl $.L.str.8, %edi
jmp .LBB0_5
.LBB0_19:
movl $.L.str.9, %edi
jmp .LBB0_5
.LBB0_21:
movl $.L.str.10, %edi
jmp .LBB0_5
.LBB0_23:
movl $.L.str.11, %edi
jmp .LBB0_5
.LBB0_29:
movl $.L.str.12, %edi
.LBB0_5:
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Error! hipInit returned: %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error! hipDeviceGet returned: %d\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error! hipCtxCreate returned: %d\n"
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error! hipModuleLoad returned: %d\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "VectorAdd"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error! hipModuleGetFunction returned: %d\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error! hipMalloc returned: %d\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error! hipMemcpyHtoD returned: %d\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error! hipModuleLaunchKernel returned: %d\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Error! hipMemcpyDtoH returned: %d\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error! hipFree returned: %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Error! hipCtxDestroy returned: %d\n"
.size .L.str.12, 35
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f\n"
.size .L.str.13, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./test.cu <ptx_file> <cuda_device>"
.size .Lstr, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006b864_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: ./test.cu <ptx_file> <cuda_device>\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Error! cuInit returned: %d\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "Error! cuDeviceGet returned: %d\n"
.align 8
.LC5:
.string "Error! cuCtxCreate returned: %d\n"
.align 8
.LC6:
.string "Error! cuModuleLoad returned: %d\n"
.section .rodata.str1.1
.LC7:
.string "VectorAdd"
.section .rodata.str1.8
.align 8
.LC8:
.string "Error! cuModuleGetFunction returned: %d\n"
.align 8
.LC9:
.string "Error! cuMemAlloc returned: %d\n"
.align 8
.LC10:
.string "Error! cuMemcpyHtoD returned: %d\n"
.align 8
.LC11:
.string "Error! cuLaunchKernel returned: %d\n"
.align 8
.LC12:
.string "Error! cuMemcpyDtoH returned: %d\n"
.align 8
.LC13:
.string "Error! cuMemFree returned: %d\n"
.align 8
.LC14:
.string "Error! cuCtxDestroy returned: %d\n"
.section .rodata.str1.1
.LC15:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $104, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jg .L4
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L4:
movq %rsi, %r13
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movss .LC1(%rip), %xmm1
.L5:
movss %xmm1, (%r12,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movl $0x00000000, (%rbx,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L5
movl $0, %edi
call cuInit@PLT
testl %eax, %eax
je .L6
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L6:
movq 16(%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leaq 12(%rsp), %rdi
movl %eax, %esi
call cuDeviceGet@PLT
testl %eax, %eax
je .L7
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L7:
leaq 16(%rsp), %rdi
movl 12(%rsp), %edx
movl $0, %esi
call cuCtxCreate_v2@PLT
testl %eax, %eax
je .L8
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L8:
movq 8(%r13), %rsi
leaq 24(%rsp), %rdi
call cuModuleLoad@PLT
testl %eax, %eax
je .L9
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L9:
leaq 32(%rsp), %rdi
leaq .LC7(%rip), %rdx
movq 24(%rsp), %rsi
call cuModuleGetFunction@PLT
testl %eax, %eax
je .L10
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L10:
leaq 40(%rsp), %rdi
movl $40, %esi
call cuMemAlloc_v2@PLT
leaq 48(%rsp), %rdi
movl $40, %esi
call cuMemAlloc_v2@PLT
leaq 56(%rsp), %rdi
movl $40, %esi
call cuMemAlloc_v2@PLT
testl %eax, %eax
je .L11
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L11:
movl $40, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cuMemcpyHtoD_v2@PLT
movl $40, %edx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cuMemcpyHtoD_v2@PLT
movl $40, %edx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cuMemcpyHtoD_v2@PLT
movl %eax, %edx
testl %eax, %eax
je .L12
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
leaq 40(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq $0
.cfi_def_cfa_offset 160
leaq 80(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 168
pushq $0
.cfi_def_cfa_offset 176
pushq $0
.cfi_def_cfa_offset 184
pushq $1
.cfi_def_cfa_offset 192
movl $1, %r9d
movl $1, %r8d
movl $1, %ecx
movl $1, %edx
movl $10, %esi
movq 80(%rsp), %rdi
call cuLaunchKernel@PLT
movl %eax, %edx
addq $48, %rsp
.cfi_def_cfa_offset 144
testl %eax, %eax
je .L13
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movl $40, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cuMemcpyDtoH_v2@PLT
movl %eax, %edx
testl %eax, %eax
je .L14
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L14:
movq 40(%rsp), %rdi
call cuMemFree_v2@PLT
movq 48(%rsp), %rdi
call cuMemFree_v2@PLT
movq 56(%rsp), %rdi
call cuMemFree_v2@PLT
movl %eax, %edx
testl %eax, %eax
je .L15
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L15:
movq 16(%rsp), %rdi
call cuCtxDestroy_v2@PLT
movl %eax, %edx
movl $0, %ebp
leaq .LC15(%rip), %r12
testl %eax, %eax
jne .L23
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%rbp,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbp
cmpq $10, %rbp
jne .L16
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1094713344
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jle .LBB0_28
# %bb.1:
movq %rsi, %r12
movl $40, %edi
callq malloc
movq %rax, %r15
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl $1094713344, (%r15,%rax,4) # imm = 0x41400000
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB0_2
# %bb.3:
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB0_4
# %bb.6:
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leaq 20(%rsp), %rdi
movl %eax, %esi
callq hipDeviceGet
testl %eax, %eax
jne .LBB0_7
# %bb.8:
movl 20(%rsp), %edx
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq hipCtxCreate
testl %eax, %eax
jne .LBB0_9
# %bb.10:
movq 8(%r12), %rsi
leaq 48(%rsp), %rdi
callq hipModuleLoad
testl %eax, %eax
jne .LBB0_11
# %bb.12:
movq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
movl $.L.str.5, %edx
callq hipModuleGetFunction
testl %eax, %eax
jne .LBB0_13
# %bb.14:
leaq 8(%rsp), %r12
movl $40, %esi
movq %r12, %rdi
callq hipMalloc
leaq 32(%rsp), %r13
movl $40, %esi
movq %r13, %rdi
callq hipMalloc
leaq 24(%rsp), %rbp
movl $40, %esi
movq %rbp, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB0_15
# %bb.16:
movq 8(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
callq hipMemcpyHtoD
movq 32(%rsp), %rdi
movl $40, %edx
movq %r15, %rsi
callq hipMemcpyHtoD
movq 24(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
callq hipMemcpyHtoD
testl %eax, %eax
jne .LBB0_17
# %bb.18:
movq %r12, 64(%rsp)
movq %r13, 72(%rsp)
movq %rbp, 80(%rsp)
movq 40(%rsp), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
leaq 72(%rsp), %rax
movl $10, %esi
movl $1, %edx
movl $1, %ecx
movl $1, %r8d
movl $1, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
pushq %rax
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq hipModuleLaunchKernel
addq $48, %rsp
.cfi_adjust_cfa_offset -48
testl %eax, %eax
jne .LBB0_19
# %bb.20:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
callq hipMemcpyDtoH
testl %eax, %eax
jne .LBB0_21
# %bb.22:
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_23
# %bb.24:
movq 56(%rsp), %rdi
callq hipCtxDestroy
testl %eax, %eax
jne .LBB0_29
# %bb.25: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_26: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq $10, %r14
jne .LBB0_26
# %bb.27:
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_28:
.cfi_def_cfa_offset 144
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB0_4:
movl $.L.str.1, %edi
jmp .LBB0_5
.LBB0_7:
movl $.L.str.2, %edi
jmp .LBB0_5
.LBB0_9:
movl $.L.str.3, %edi
jmp .LBB0_5
.LBB0_11:
movl $.L.str.4, %edi
jmp .LBB0_5
.LBB0_13:
movl $.L.str.6, %edi
jmp .LBB0_5
.LBB0_15:
movl $.L.str.7, %edi
jmp .LBB0_5
.LBB0_17:
movl $.L.str.8, %edi
jmp .LBB0_5
.LBB0_19:
movl $.L.str.9, %edi
jmp .LBB0_5
.LBB0_21:
movl $.L.str.10, %edi
jmp .LBB0_5
.LBB0_23:
movl $.L.str.11, %edi
jmp .LBB0_5
.LBB0_29:
movl $.L.str.12, %edi
.LBB0_5:
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Error! hipInit returned: %d\n"
.size .L.str.1, 29
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error! hipDeviceGet returned: %d\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error! hipCtxCreate returned: %d\n"
.size .L.str.3, 34
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error! hipModuleLoad returned: %d\n"
.size .L.str.4, 35
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "VectorAdd"
.size .L.str.5, 10
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error! hipModuleGetFunction returned: %d\n"
.size .L.str.6, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error! hipMalloc returned: %d\n"
.size .L.str.7, 31
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error! hipMemcpyHtoD returned: %d\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Error! hipModuleLaunchKernel returned: %d\n"
.size .L.str.9, 43
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Error! hipMemcpyDtoH returned: %d\n"
.size .L.str.10, 35
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error! hipFree returned: %d\n"
.size .L.str.11, 29
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Error! hipCtxDestroy returned: %d\n"
.size .L.str.12, 35
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%f\n"
.size .L.str.13, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: ./test.cu <ptx_file> <cuda_device>"
.size .Lstr, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
#include <cuda.h>
//#include <cooperative_groups.h>
//using namespace cooperative_groups;
//// Alternatively use an alias to avoid polluting the namespace with collective algorithms
////namespace cg = cooperative_groups;
////for __syncthreads()
//#ifndef __CUDACC__
//#define __CUDACC__
//#endif
//#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <cooperative_groups.h>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << "Error Name: " << cudaGetErrorName( err ) << std::endl;
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
enum PolygonType { none, rect, triang };
struct PolygonInfo {
public:
int width, height;
PolygonType ptype;
__host__ __device__ PolygonInfo(int w, int h, PolygonType t) :
width(w), height(h), ptype(t) {}
};
class Polygon {
protected:
int width, height;
public:
__host__ __device__ Polygon(int w, int h) : width(w), height(h) {}
__host__ __device__ Polygon(const PolygonInfo& pi) : width(pi.width), height(pi.height) {}
__host__ __device__ void set_values(int a, int b) {
width=a;
height=b;
}
__host__ __device__ virtual int area() {
printf("\nLOL here!\n");
printf(" width = %d\n height = %d\n", width, height);
return 0;
}
__host__ __device__ virtual PolygonInfo get_info() {
return PolygonInfo(width,height,PolygonType::none);
}
};
class Rectangle: public Polygon {
public:
__host__ __device__ Rectangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Rectangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return width * height;
}
__host__ __device__ PolygonInfo get_info() override {
printf("rect get_info\n");
return PolygonInfo(width,height,PolygonType::rect);
}
};
class Triangle: public Polygon {
public:
__host__ __device__ Triangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Triangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return (width * height / 2);
}
__host__ __device__ PolygonInfo get_info() override {
printf("triang get_info\n");
return PolygonInfo(width,height,PolygonType::triang);
}
};
static __global__ void wrong_example_kernel(Polygon *pols, int n_pols) {
Polygon *p = pols;
for (int i=0; i<n_pols; i++) {
printf("(device) p->area() = %d", p->area());
p++;
}
}
static __global__ void inst_obj_dev_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//printf("%d %d\n", x,y);
size_t pols_size = sizeof(Polygon)*n_pols;
Polygon *pols = (Polygon*) malloc(pols_size);
for (int i=0; i<n_pols; i++) {
Polygon *tmp_p = nullptr;
//PolygonInfo tmp_pi = *(pols_infos+i);
PolygonInfo *pi_p = pols_infos+i;
//printf("w=%d, h=%d, ptype=%d\n", pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*(pols_infos+i));
} else {
printf("we have a problem...\n");
}
memcpy(pols+i, tmp_p, sizeof(*tmp_p));
}
printf("%d %d\n", x,y);
for (int i=0; i<n_pols; i++) {
printf("\t area = %d\n", pols[i].area());
}
}
__device__ Polygon *d_pols = nullptr;
__device__ int d_n_pols = 0;
static __global__ void copy_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
//printf("%d %d\n", x,y);
if (x >= n_pols) return;
if (x == 0) {
// only the first thread inits vars
printf("(%d) \n init...\n", x);
size_t pols_size = sizeof(Polygon)*n_pols;
d_pols = (Polygon*) malloc(pols_size);
d_n_pols = n_pols;
}
__syncthreads(); // all threads must wait
//cooperative_groups::this_thread_block().sync(); // alternative // does the same
Polygon *tmp_p = nullptr;
PolygonInfo *pi_p = pols_infos+x;
printf("(%d)\n w=%d, h=%d, ptype=%d\n", x, pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*pi_p);
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*pi_p);
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*pi_p);
} else {
printf("we have a problem...\n");
}
memcpy(d_pols+x, tmp_p, sizeof(*tmp_p));
}
static __global__ void kernel() {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (d_pols == nullptr) {
printf("%d %d\n pols=%p, d_n_pols=%d\n", x, y, d_pols, d_n_pols);
return;
}
for (int i=0; i<d_n_pols; i++) {
int area = d_pols[i].area();
if (area != 6 && area != 35)
printf("%d %d\n pols=%p, area = %d\n", x, y, d_pols, d_pols[i].area());
}
}
int main() {
cudaDeviceProp prop;
int dev;
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.major = 1;
prop.minor = 0;
HANDLE_ERROR(
cudaChooseDevice(&dev,&prop)
);
// Host init
//Polygon tri = Triangle(3,4);
Triangle tri(3,4);
std::cout << "tri.area() = " << tri.area() << std::endl;
Rectangle rec(5,7);
std::cout << "rec.area() = " << rec.area() << std::endl;
std::vector<Polygon*> pols;
pols.push_back(&tri);
pols.push_back(&rec);
for (Polygon *p : pols) {
std::cout << "p->area() = " << p->area() << std::endl;
}
// Now I want to move the vector to GPU and
// for each elem call area() from device
// { /// WRONG WAY
// size_t total_size = 0;
// for (Polygon *p : pols) {
// total_size += sizeof(*p);
// }
// Polygon *dev_pols = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols, total_size)
// );
// int offset = 0;
// for (Polygon *p : pols) {
// HANDLE_ERROR(
// cudaMemcpy((void*)(dev_pols+offset), (void*)p, sizeof(*p), cudaMemcpyHostToDevice)
// );
// offset++;
// }
// float grids = 1;
// float threads = 1;
// wrong_example_kernel<<<grids,threads>>>(dev_pols, pols.size());
// // this generate a wrong mem access because vtable on host
// } /// END // WRONG WAY
//{ /// INSTACING OBJS ON DEVICE
// size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
// PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
// int i = 0;
// for (Polygon *p : pols) {
// PolygonInfo pi = p->get_info();
// memcpy(&pols_infos[i], &pi, sizeof(pi));
// i++;
// }
// PolygonInfo *dev_pols_infos = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols_infos, pols_infos_size)
// );
// HANDLE_ERROR(
// cudaMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, cudaMemcpyHostToDevice)
// );
// free(pols_infos);
// dim3 grids(1);
// dim3 threads(1);
// inst_obj_dev_kernel<<<grids,threads>>>(dev_pols_infos, pols.size());
//} /// END // INSTACING OBJS ON DEVICE
{ /// AS BEFORE BUT ONE KERNEL INST AND THE OTHER USE
size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
int i = 0;
for (Polygon *p : pols) {
PolygonInfo pi = p->get_info();
memcpy(&pols_infos[i], &pi, sizeof(pi));
i++;
}
PolygonInfo *dev_pols_infos = nullptr;
HANDLE_ERROR(
cudaMalloc((void**)&dev_pols_infos, pols_infos_size)
);
HANDLE_ERROR(
cudaMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, cudaMemcpyHostToDevice)
);
free(pols_infos);
copy_kernel<<<1,pols.size()>>>(dev_pols_infos, pols.size());
HANDLE_ERROR(cudaDeviceSynchronize());
dim3 grids(3,3);
dim3 threads(10,10);
kernel<<<grids,threads>>>();
} /// END
HANDLE_ERROR(cudaDeviceSynchronize());
HANDLE_ERROR(cudaDeviceReset());
return 0;
} | .file "tmpxft_000152a7_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._ZN9Rectangle4areaEv,"axG",@progbits,_ZN9Rectangle4areaEv,comdat
.align 2
.weak _ZN9Rectangle4areaEv
.type _ZN9Rectangle4areaEv, @function
_ZN9Rectangle4areaEv:
.LFB7248:
.cfi_startproc
endbr64
movl 8(%rdi), %eax
imull 12(%rdi), %eax
ret
.cfi_endproc
.LFE7248:
.size _ZN9Rectangle4areaEv, .-_ZN9Rectangle4areaEv
.section .text._ZN8Triangle4areaEv,"axG",@progbits,_ZN8Triangle4areaEv,comdat
.align 2
.weak _ZN8Triangle4areaEv
.type _ZN8Triangle4areaEv, @function
_ZN8Triangle4areaEv:
.LFB7256:
.cfi_startproc
endbr64
movl 8(%rdi), %edx
imull 12(%rdi), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
ret
.cfi_endproc
.LFE7256:
.size _ZN8Triangle4areaEv, .-_ZN8Triangle4areaEv
.section .rodata._ZN8Triangle8get_infoEv.str1.1,"aMS",@progbits,1
.LC0:
.string "triang get_info\n"
.section .text._ZN8Triangle8get_infoEv,"axG",@progbits,_ZN8Triangle8get_infoEv,comdat
.align 2
.weak _ZN8Triangle8get_infoEv
.type _ZN8Triangle8get_infoEv, @function
_ZN8Triangle8get_infoEv:
.LFB7257:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rbx), %eax
movl 8(%rbx), %edx
movl %edx, 20(%rsp)
movl %eax, 24(%rsp)
movq 20(%rsp), %rax
movl $2, %edx
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7257:
.size _ZN8Triangle8get_infoEv, .-_ZN8Triangle8get_infoEv
.section .rodata._ZN9Rectangle8get_infoEv.str1.1,"aMS",@progbits,1
.LC1:
.string "rect get_info\n"
.section .text._ZN9Rectangle8get_infoEv,"axG",@progbits,_ZN9Rectangle8get_infoEv,comdat
.align 2
.weak _ZN9Rectangle8get_infoEv
.type _ZN9Rectangle8get_infoEv, @function
_ZN9Rectangle8get_infoEv:
.LFB7249:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rbx), %eax
movl 8(%rbx), %edx
movl %edx, 20(%rsp)
movl %eax, 24(%rsp)
movq 20(%rsp), %rax
movl $1, %edx
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7249:
.size _ZN9Rectangle8get_infoEv, .-_ZN9Rectangle8get_infoEv
.text
.type _ZL11copy_kernelP11PolygonInfoi, @function
_ZL11copy_kernelP11PolygonInfoi:
.LFB7298:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL11copy_kernelP11PolygonInfoi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7298:
.size _ZL11copy_kernelP11PolygonInfoi, .-_ZL11copy_kernelP11PolygonInfoi
.type _ZL6kernelv, @function
_ZL6kernelv:
.LFB7300:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _ZL6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7300:
.size _ZL6kernelv, .-_ZL6kernelv
.type _ZL20wrong_example_kernelP7Polygoni, @function
_ZL20wrong_example_kernelP7Polygoni:
.LFB7294:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL20wrong_example_kernelP7Polygoni(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7294:
.size _ZL20wrong_example_kernelP7Polygoni, .-_ZL20wrong_example_kernelP7Polygoni
.type _ZL19inst_obj_dev_kernelP11PolygonInfoi, @function
_ZL19inst_obj_dev_kernelP11PolygonInfoi:
.LFB7296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL19inst_obj_dev_kernelP11PolygonInfoi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7296:
.size _ZL19inst_obj_dev_kernelP11PolygonInfoi, .-_ZL19inst_obj_dev_kernelP11PolygonInfoi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Error Name: "
.LC3:
.string " in "
.LC4:
.string " line "
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB7229:
.cfi_startproc
testl %edi, %edi
jne .L36
ret
.L36:
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebx
movq %rsi, %r12
movl %edx, %ebp
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r14
movl %ebx, %edi
call cudaGetErrorName@PLT
movq %rax, %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE7229:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB7271:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7271:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC5:
.string "_Z6kernelv"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z11copy_kernelP11PolygonInfoi"
.align 8
.LC7:
.string "_Z19inst_obj_dev_kernelP11PolygonInfoi"
.align 8
.LC8:
.string "_Z20wrong_example_kernelP7Polygoni"
.section .rodata.str1.1
.LC9:
.string "d_pols"
.LC10:
.string "d_n_pols"
.section .rodata.str1.8
.align 8
.LC11:
.string "_ZN35_INTERNAL_d6263787_7_main_cu_d_pols4cuda3std3__419piecewise_constructE"
.align 8
.LC12:
.string "_ZN35_INTERNAL_d6263787_7_main_cu_d_pols4cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC13:
.string "_ZN35_INTERNAL_d6263787_7_main_cu_d_pols4cuda3std6ranges3__45__cpo9iter_moveE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB7302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6kernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11copy_kernelP11PolygonInfoi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19inst_obj_dev_kernelP11PolygonInfoi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL20wrong_example_kernelP7Polygoni(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6d_pols(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8d_n_pols(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE7302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIP7PolygonSaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorIP7PolygonSaIS1_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIP7PolygonSaIS1_EED2Ev
.type _ZNSt6vectorIP7PolygonSaIS1_EED2Ev, @function
_ZNSt6vectorIP7PolygonSaIS1_EED2Ev:
.LFB7754:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE7754:
.size _ZNSt6vectorIP7PolygonSaIS1_EED2Ev, .-_ZNSt6vectorIP7PolygonSaIS1_EED2Ev
.weak _ZNSt6vectorIP7PolygonSaIS1_EED1Ev
.set _ZNSt6vectorIP7PolygonSaIS1_EED1Ev,_ZNSt6vectorIP7PolygonSaIS1_EED2Ev
.section .rodata._ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.str1.1,"aMS",@progbits,1
.LC14:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,"axG",@progbits,_ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.type _ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, @function
_ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_:
.LFB8070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L64
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L50
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L51
jmp .L58
.L64:
leaq .LC14(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L65:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L53
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L57
.L50:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L58:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L51:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L65
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L55
.L53:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L55:
addq %rbp, %r15
testq %r13, %r13
je .L56
movq 16(%rbx), %rsi
subq %r13, %rsi
.L57:
movq %r13, %rdi
call _ZdlPvm@PLT
.L56:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE8070:
.size _ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, .-_ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.section .text._ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_,"axG",@progbits,_ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_,comdat
.align 2
.weak _ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_
.type _ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_, @function
_ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_:
.LFB7955:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
je .L67
movq (%rsi), %rdx
movq %rdx, (%rax)
addq $8, 8(%rdi)
.L68:
movq 8(%rbx), %rax
subq $8, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movq %rsi, %rdx
movq %rax, %rsi
call _ZNSt6vectorIP7PolygonSaIS1_EE17_M_realloc_insertIJS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
jmp .L68
.cfi_endproc
.LFE7955:
.size _ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_, .-_ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_
.section .rodata.str1.8
.align 8
.LC15:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Nyriu/Esercizi_Esempi_CUDA/main/07_polymorphism/02_passing_arguments/src/main.cu"
.section .rodata.str1.1
.LC16:
.string "tri.area() = "
.LC17:
.string "rec.area() = "
.LC18:
.string "p->area() = "
.text
.globl main
.type main, @function
main:
.LFB7258:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA7258
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1176, %rsp
.cfi_def_cfa_offset 1232
movq %fs:40, %rax
movq %rax, 1160(%rsp)
xorl %eax, %eax
leaq 128(%rsp), %rsi
movl $129, %ecx
movq %rsi, %rdi
rep stosq
movl $1, 488(%rsp)
leaq 20(%rsp), %rdi
.LEHB0:
call cudaChooseDevice@PLT
movl %eax, %edi
movl $183, %edx
leaq .LC15(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $3, 72(%rsp)
movl $4, 76(%rsp)
leaq 16+_ZTV8Triangle(%rip), %rax
movq %rax, 64(%rsp)
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 76(%rsp), %edx
imull 72(%rsp), %edx
movl %edx, %esi
shrl $31, %esi
addl %edx, %esi
sarl %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $5, 88(%rsp)
movl $7, 92(%rsp)
leaq 16+_ZTV9Rectangle(%rip), %rax
movq %rax, 80(%rsp)
leaq .LC17(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 88(%rsp), %esi
imull 92(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE0:
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rsi
leaq 96(%rsp), %rdi
.LEHB1:
call _ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rsi
leaq 96(%rsp), %rdi
call _ZNSt6vectorIP7PolygonSaIS1_EE12emplace_backIJS1_EEERS1_DpOT_
movq 96(%rsp), %rax
movq %rax, 8(%rsp)
movq 104(%rsp), %r14
cmpq %rax, %r14
je .L71
movq %rax, %r12
movq %rax, %r13
movq %rbx, %r15
jmp .L76
.L93:
movq (%rbx), %rax
movq %rbx, %rdi
call *(%rax)
movl %eax, %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L89
cmpb $0, 56(%rbp)
je .L74
movzbl 67(%rbp), %esi
.L75:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L90
.L89:
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L91
call _ZSt16__throw_bad_castv@PLT
.L84:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIP7PolygonSaIS1_EED1Ev
movq 1160(%rsp), %rax
subq %fs:40, %rax
je .L81
call __stack_chk_fail@PLT
.L91:
call __stack_chk_fail@PLT
.L74:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L75
.L90:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %r13
cmpq %r13, %r14
je .L92
.L76:
movq 0(%r13), %rbx
movl $12, %edx
leaq .LC18(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L93
.L92:
movq %r14, %rax
movq 8(%rsp), %rdx
subq %rdx, %rax
sarq $3, %rax
movq %rax, 8(%rsp)
leaq (%rax,%rax,2), %rdi
salq $2, %rdi
movq %rdi, %rbp
call malloc@PLT
movq %rax, %r13
movl $0, %ebx
leaq 48(%rsp), %r15
jmp .L77
.L94:
movq %rax, 48(%rsp)
movl %edx, 56(%rsp)
cmpq %rbx, %rbp
movq %rbx, %rcx
cmovnb %rbp, %rcx
subq %rbx, %rcx
leaq 0(%r13,%rbx), %rdi
movl $12, %edx
movq %r15, %rsi
call __memcpy_chk@PLT
addq $8, %r12
addq $12, %rbx
cmpq %r12, %r14
je .L82
.L77:
movq (%r12), %rdi
movq (%rdi), %rax
call *8(%rax)
jmp .L94
.L96:
movl %eax, %edi
movl $267, %edx
leaq .LC15(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $270, %edx
leaq .LC15(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rbx
movl %ebx, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L78
movl %ebx, %esi
movq 24(%rsp), %rdi
call _ZL11copy_kernelP11PolygonInfoi
.L78:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $277, %edx
leaq .LC15(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $3, 36(%rsp)
movl $3, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 48(%rsp)
movl $10, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L79
call _ZL6kernelv
.L79:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $283, %edx
leaq .LC15(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
call cudaDeviceReset@PLT
movl %eax, %edi
movl $284, %edx
leaq .LC15(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
.LEHE1:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIP7PolygonSaIS1_EED1Ev
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L95
movl $0, %eax
addq $1176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L81:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L71:
movl $0, %edi
call malloc@PLT
movq %rax, %r13
movq $0, 8(%rsp)
movl $0, %ebp
.L82:
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movq %rbp, %rsi
.LEHB3:
call cudaMalloc@PLT
.LEHE3:
jmp .L96
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE7258:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA7258:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE7258-.LLSDACSB7258
.LLSDACSB7258:
.uleb128 .LEHB0-.LFB7258
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB7258
.uleb128 .LEHE1-.LEHB1
.uleb128 .L84-.LFB7258
.uleb128 0
.uleb128 .LEHB2-.LFB7258
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB7258
.uleb128 .LEHE3-.LEHB3
.uleb128 .L84-.LFB7258
.uleb128 0
.LLSDACSE7258:
.text
.size main, .-main
.weak _ZTS7Polygon
.section .rodata._ZTS7Polygon,"aG",@progbits,_ZTS7Polygon,comdat
.align 8
.type _ZTS7Polygon, @object
.size _ZTS7Polygon, 9
_ZTS7Polygon:
.string "7Polygon"
.weak _ZTI7Polygon
.section .data.rel.ro._ZTI7Polygon,"awG",@progbits,_ZTI7Polygon,comdat
.align 8
.type _ZTI7Polygon, @object
.size _ZTI7Polygon, 16
_ZTI7Polygon:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS7Polygon
.weak _ZTS9Rectangle
.section .rodata._ZTS9Rectangle,"aG",@progbits,_ZTS9Rectangle,comdat
.align 8
.type _ZTS9Rectangle, @object
.size _ZTS9Rectangle, 11
_ZTS9Rectangle:
.string "9Rectangle"
.weak _ZTI9Rectangle
.section .data.rel.ro._ZTI9Rectangle,"awG",@progbits,_ZTI9Rectangle,comdat
.align 8
.type _ZTI9Rectangle, @object
.size _ZTI9Rectangle, 24
_ZTI9Rectangle:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTS9Rectangle
.quad _ZTI7Polygon
.weak _ZTS8Triangle
.section .rodata._ZTS8Triangle,"aG",@progbits,_ZTS8Triangle,comdat
.align 8
.type _ZTS8Triangle, @object
.size _ZTS8Triangle, 10
_ZTS8Triangle:
.string "8Triangle"
.weak _ZTI8Triangle
.section .data.rel.ro._ZTI8Triangle,"awG",@progbits,_ZTI8Triangle,comdat
.align 8
.type _ZTI8Triangle, @object
.size _ZTI8Triangle, 24
_ZTI8Triangle:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTS8Triangle
.quad _ZTI7Polygon
.weak _ZTV9Rectangle
.section .data.rel.ro.local._ZTV9Rectangle,"awG",@progbits,_ZTV9Rectangle,comdat
.align 8
.type _ZTV9Rectangle, @object
.size _ZTV9Rectangle, 32
_ZTV9Rectangle:
.quad 0
.quad _ZTI9Rectangle
.quad _ZN9Rectangle4areaEv
.quad _ZN9Rectangle8get_infoEv
.weak _ZTV8Triangle
.section .data.rel.ro.local._ZTV8Triangle,"awG",@progbits,_ZTV8Triangle,comdat
.align 8
.type _ZTV8Triangle, @object
.size _ZTV8Triangle, 32
_ZTV8Triangle:
.quad 0
.quad _ZTI8Triangle
.quad _ZN8Triangle4areaEv
.quad _ZN8Triangle8get_infoEv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8d_n_pols
.comm _ZL8d_n_pols,4,4
.local _ZL6d_pols
.comm _ZL6d_pols,8,8
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
#include <cuda.h>
//#include <cooperative_groups.h>
//using namespace cooperative_groups;
//// Alternatively use an alias to avoid polluting the namespace with collective algorithms
////namespace cg = cooperative_groups;
////for __syncthreads()
//#ifndef __CUDACC__
//#define __CUDACC__
//#endif
//#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <cooperative_groups.h>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << "Error Name: " << cudaGetErrorName( err ) << std::endl;
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
enum PolygonType { none, rect, triang };
struct PolygonInfo {
public:
int width, height;
PolygonType ptype;
__host__ __device__ PolygonInfo(int w, int h, PolygonType t) :
width(w), height(h), ptype(t) {}
};
class Polygon {
protected:
int width, height;
public:
__host__ __device__ Polygon(int w, int h) : width(w), height(h) {}
__host__ __device__ Polygon(const PolygonInfo& pi) : width(pi.width), height(pi.height) {}
__host__ __device__ void set_values(int a, int b) {
width=a;
height=b;
}
__host__ __device__ virtual int area() {
printf("\nLOL here!\n");
printf(" width = %d\n height = %d\n", width, height);
return 0;
}
__host__ __device__ virtual PolygonInfo get_info() {
return PolygonInfo(width,height,PolygonType::none);
}
};
class Rectangle: public Polygon {
public:
__host__ __device__ Rectangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Rectangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return width * height;
}
__host__ __device__ PolygonInfo get_info() override {
printf("rect get_info\n");
return PolygonInfo(width,height,PolygonType::rect);
}
};
class Triangle: public Polygon {
public:
__host__ __device__ Triangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Triangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return (width * height / 2);
}
__host__ __device__ PolygonInfo get_info() override {
printf("triang get_info\n");
return PolygonInfo(width,height,PolygonType::triang);
}
};
static __global__ void wrong_example_kernel(Polygon *pols, int n_pols) {
Polygon *p = pols;
for (int i=0; i<n_pols; i++) {
printf("(device) p->area() = %d", p->area());
p++;
}
}
static __global__ void inst_obj_dev_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//printf("%d %d\n", x,y);
size_t pols_size = sizeof(Polygon)*n_pols;
Polygon *pols = (Polygon*) malloc(pols_size);
for (int i=0; i<n_pols; i++) {
Polygon *tmp_p = nullptr;
//PolygonInfo tmp_pi = *(pols_infos+i);
PolygonInfo *pi_p = pols_infos+i;
//printf("w=%d, h=%d, ptype=%d\n", pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*(pols_infos+i));
} else {
printf("we have a problem...\n");
}
memcpy(pols+i, tmp_p, sizeof(*tmp_p));
}
printf("%d %d\n", x,y);
for (int i=0; i<n_pols; i++) {
printf("\t area = %d\n", pols[i].area());
}
}
__device__ Polygon *d_pols = nullptr;
__device__ int d_n_pols = 0;
static __global__ void copy_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
//printf("%d %d\n", x,y);
if (x >= n_pols) return;
if (x == 0) {
// only the first thread inits vars
printf("(%d) \n init...\n", x);
size_t pols_size = sizeof(Polygon)*n_pols;
d_pols = (Polygon*) malloc(pols_size);
d_n_pols = n_pols;
}
__syncthreads(); // all threads must wait
//cooperative_groups::this_thread_block().sync(); // alternative // does the same
Polygon *tmp_p = nullptr;
PolygonInfo *pi_p = pols_infos+x;
printf("(%d)\n w=%d, h=%d, ptype=%d\n", x, pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*pi_p);
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*pi_p);
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*pi_p);
} else {
printf("we have a problem...\n");
}
memcpy(d_pols+x, tmp_p, sizeof(*tmp_p));
}
static __global__ void kernel() {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (d_pols == nullptr) {
printf("%d %d\n pols=%p, d_n_pols=%d\n", x, y, d_pols, d_n_pols);
return;
}
for (int i=0; i<d_n_pols; i++) {
int area = d_pols[i].area();
if (area != 6 && area != 35)
printf("%d %d\n pols=%p, area = %d\n", x, y, d_pols, d_pols[i].area());
}
}
int main() {
cudaDeviceProp prop;
int dev;
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.major = 1;
prop.minor = 0;
HANDLE_ERROR(
cudaChooseDevice(&dev,&prop)
);
// Host init
//Polygon tri = Triangle(3,4);
Triangle tri(3,4);
std::cout << "tri.area() = " << tri.area() << std::endl;
Rectangle rec(5,7);
std::cout << "rec.area() = " << rec.area() << std::endl;
std::vector<Polygon*> pols;
pols.push_back(&tri);
pols.push_back(&rec);
for (Polygon *p : pols) {
std::cout << "p->area() = " << p->area() << std::endl;
}
// Now I want to move the vector to GPU and
// for each elem call area() from device
// { /// WRONG WAY
// size_t total_size = 0;
// for (Polygon *p : pols) {
// total_size += sizeof(*p);
// }
// Polygon *dev_pols = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols, total_size)
// );
// int offset = 0;
// for (Polygon *p : pols) {
// HANDLE_ERROR(
// cudaMemcpy((void*)(dev_pols+offset), (void*)p, sizeof(*p), cudaMemcpyHostToDevice)
// );
// offset++;
// }
// float grids = 1;
// float threads = 1;
// wrong_example_kernel<<<grids,threads>>>(dev_pols, pols.size());
// // this generate a wrong mem access because vtable on host
// } /// END // WRONG WAY
//{ /// INSTACING OBJS ON DEVICE
// size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
// PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
// int i = 0;
// for (Polygon *p : pols) {
// PolygonInfo pi = p->get_info();
// memcpy(&pols_infos[i], &pi, sizeof(pi));
// i++;
// }
// PolygonInfo *dev_pols_infos = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols_infos, pols_infos_size)
// );
// HANDLE_ERROR(
// cudaMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, cudaMemcpyHostToDevice)
// );
// free(pols_infos);
// dim3 grids(1);
// dim3 threads(1);
// inst_obj_dev_kernel<<<grids,threads>>>(dev_pols_infos, pols.size());
//} /// END // INSTACING OBJS ON DEVICE
{ /// AS BEFORE BUT ONE KERNEL INST AND THE OTHER USE
size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
int i = 0;
for (Polygon *p : pols) {
PolygonInfo pi = p->get_info();
memcpy(&pols_infos[i], &pi, sizeof(pi));
i++;
}
PolygonInfo *dev_pols_infos = nullptr;
HANDLE_ERROR(
cudaMalloc((void**)&dev_pols_infos, pols_infos_size)
);
HANDLE_ERROR(
cudaMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, cudaMemcpyHostToDevice)
);
free(pols_infos);
copy_kernel<<<1,pols.size()>>>(dev_pols_infos, pols.size());
HANDLE_ERROR(cudaDeviceSynchronize());
dim3 grids(3,3);
dim3 threads(10,10);
kernel<<<grids,threads>>>();
} /// END
HANDLE_ERROR(cudaDeviceSynchronize());
HANDLE_ERROR(cudaDeviceReset());
return 0;
} | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
//#include <cooperative_groups.h>
//using namespace cooperative_groups;
//// Alternatively use an alias to avoid polluting the namespace with collective algorithms
////namespace cg = cooperative_groups;
////for __syncthreads()
//#ifndef __CUDACC__
//#define __CUDACC__
//#endif
//#include <device_functions.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_cooperative_groups.h>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << "Error Name: " << hipGetErrorName( err ) << std::endl;
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
enum PolygonType { none, rect, triang };
struct PolygonInfo {
public:
int width, height;
PolygonType ptype;
__host__ __device__ PolygonInfo(int w, int h, PolygonType t) :
width(w), height(h), ptype(t) {}
};
class Polygon {
protected:
int width, height;
public:
__host__ __device__ Polygon(int w, int h) : width(w), height(h) {}
__host__ __device__ Polygon(const PolygonInfo& pi) : width(pi.width), height(pi.height) {}
__host__ __device__ void set_values(int a, int b) {
width=a;
height=b;
}
__host__ __device__ virtual int area() {
printf("\nLOL here!\n");
printf(" width = %d\n height = %d\n", width, height);
return 0;
}
__host__ __device__ virtual PolygonInfo get_info() {
return PolygonInfo(width,height,PolygonType::none);
}
};
class Rectangle: public Polygon {
public:
__host__ __device__ Rectangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Rectangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return width * height;
}
__host__ __device__ PolygonInfo get_info() override {
printf("rect get_info\n");
return PolygonInfo(width,height,PolygonType::rect);
}
};
class Triangle: public Polygon {
public:
__host__ __device__ Triangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Triangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return (width * height / 2);
}
__host__ __device__ PolygonInfo get_info() override {
printf("triang get_info\n");
return PolygonInfo(width,height,PolygonType::triang);
}
};
static __global__ void wrong_example_kernel(Polygon *pols, int n_pols) {
Polygon *p = pols;
for (int i=0; i<n_pols; i++) {
printf("(device) p->area() = %d", p->area());
p++;
}
}
static __global__ void inst_obj_dev_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//printf("%d %d\n", x,y);
size_t pols_size = sizeof(Polygon)*n_pols;
Polygon *pols = (Polygon*) malloc(pols_size);
for (int i=0; i<n_pols; i++) {
Polygon *tmp_p = nullptr;
//PolygonInfo tmp_pi = *(pols_infos+i);
PolygonInfo *pi_p = pols_infos+i;
//printf("w=%d, h=%d, ptype=%d\n", pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*(pols_infos+i));
} else {
printf("we have a problem...\n");
}
memcpy(pols+i, tmp_p, sizeof(*tmp_p));
}
printf("%d %d\n", x,y);
for (int i=0; i<n_pols; i++) {
printf("\t area = %d\n", pols[i].area());
}
}
__device__ Polygon *d_pols = nullptr;
__device__ int d_n_pols = 0;
static __global__ void copy_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
//printf("%d %d\n", x,y);
if (x >= n_pols) return;
if (x == 0) {
// only the first thread inits vars
printf("(%d) \n init...\n", x);
size_t pols_size = sizeof(Polygon)*n_pols;
d_pols = (Polygon*) malloc(pols_size);
d_n_pols = n_pols;
}
__syncthreads(); // all threads must wait
//cooperative_groups::this_thread_block().sync(); // alternative // does the same
Polygon *tmp_p = nullptr;
PolygonInfo *pi_p = pols_infos+x;
printf("(%d)\n w=%d, h=%d, ptype=%d\n", x, pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*pi_p);
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*pi_p);
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*pi_p);
} else {
printf("we have a problem...\n");
}
memcpy(d_pols+x, tmp_p, sizeof(*tmp_p));
}
static __global__ void kernel() {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (d_pols == nullptr) {
printf("%d %d\n pols=%p, d_n_pols=%d\n", x, y, d_pols, d_n_pols);
return;
}
for (int i=0; i<d_n_pols; i++) {
int area = d_pols[i].area();
if (area != 6 && area != 35)
printf("%d %d\n pols=%p, area = %d\n", x, y, d_pols, d_pols[i].area());
}
}
int main() {
hipDeviceProp_t prop;
int dev;
memset(&prop, 0, sizeof(hipDeviceProp_t));
prop.major = 1;
prop.minor = 0;
HANDLE_ERROR(
hipChooseDevice(&dev,&prop)
);
// Host init
//Polygon tri = Triangle(3,4);
Triangle tri(3,4);
std::cout << "tri.area() = " << tri.area() << std::endl;
Rectangle rec(5,7);
std::cout << "rec.area() = " << rec.area() << std::endl;
std::vector<Polygon*> pols;
pols.push_back(&tri);
pols.push_back(&rec);
for (Polygon *p : pols) {
std::cout << "p->area() = " << p->area() << std::endl;
}
// Now I want to move the vector to GPU and
// for each elem call area() from device
// { /// WRONG WAY
// size_t total_size = 0;
// for (Polygon *p : pols) {
// total_size += sizeof(*p);
// }
// Polygon *dev_pols = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols, total_size)
// );
// int offset = 0;
// for (Polygon *p : pols) {
// HANDLE_ERROR(
// cudaMemcpy((void*)(dev_pols+offset), (void*)p, sizeof(*p), cudaMemcpyHostToDevice)
// );
// offset++;
// }
// float grids = 1;
// float threads = 1;
// wrong_example_kernel<<<grids,threads>>>(dev_pols, pols.size());
// // this generate a wrong mem access because vtable on host
// } /// END // WRONG WAY
//{ /// INSTACING OBJS ON DEVICE
// size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
// PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
// int i = 0;
// for (Polygon *p : pols) {
// PolygonInfo pi = p->get_info();
// memcpy(&pols_infos[i], &pi, sizeof(pi));
// i++;
// }
// PolygonInfo *dev_pols_infos = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols_infos, pols_infos_size)
// );
// HANDLE_ERROR(
// cudaMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, cudaMemcpyHostToDevice)
// );
// free(pols_infos);
// dim3 grids(1);
// dim3 threads(1);
// inst_obj_dev_kernel<<<grids,threads>>>(dev_pols_infos, pols.size());
//} /// END // INSTACING OBJS ON DEVICE
{ /// AS BEFORE BUT ONE KERNEL INST AND THE OTHER USE
size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
int i = 0;
for (Polygon *p : pols) {
PolygonInfo pi = p->get_info();
memcpy(&pols_infos[i], &pi, sizeof(pi));
i++;
}
PolygonInfo *dev_pols_infos = nullptr;
HANDLE_ERROR(
hipMalloc((void**)&dev_pols_infos, pols_infos_size)
);
HANDLE_ERROR(
hipMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, hipMemcpyHostToDevice)
);
free(pols_infos);
copy_kernel<<<1,pols.size()>>>(dev_pols_infos, pols.size());
HANDLE_ERROR(hipDeviceSynchronize());
dim3 grids(3,3);
dim3 threads(10,10);
kernel<<<grids,threads>>>();
} /// END
HANDLE_ERROR(hipDeviceSynchronize());
HANDLE_ERROR(hipDeviceReset());
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
//#include <cooperative_groups.h>
//using namespace cooperative_groups;
//// Alternatively use an alias to avoid polluting the namespace with collective algorithms
////namespace cg = cooperative_groups;
////for __syncthreads()
//#ifndef __CUDACC__
//#define __CUDACC__
//#endif
//#include <device_functions.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_cooperative_groups.h>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << "Error Name: " << hipGetErrorName( err ) << std::endl;
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(HandleError(err, __FILE__, __LINE__))
enum PolygonType { none, rect, triang };
struct PolygonInfo {
public:
int width, height;
PolygonType ptype;
__host__ __device__ PolygonInfo(int w, int h, PolygonType t) :
width(w), height(h), ptype(t) {}
};
class Polygon {
protected:
int width, height;
public:
__host__ __device__ Polygon(int w, int h) : width(w), height(h) {}
__host__ __device__ Polygon(const PolygonInfo& pi) : width(pi.width), height(pi.height) {}
__host__ __device__ void set_values(int a, int b) {
width=a;
height=b;
}
__host__ __device__ virtual int area() {
printf("\nLOL here!\n");
printf(" width = %d\n height = %d\n", width, height);
return 0;
}
__host__ __device__ virtual PolygonInfo get_info() {
return PolygonInfo(width,height,PolygonType::none);
}
};
class Rectangle: public Polygon {
public:
__host__ __device__ Rectangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Rectangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return width * height;
}
__host__ __device__ PolygonInfo get_info() override {
printf("rect get_info\n");
return PolygonInfo(width,height,PolygonType::rect);
}
};
class Triangle: public Polygon {
public:
__host__ __device__ Triangle(int w, int h) : Polygon(w,h) {}
__host__ __device__ Triangle(const PolygonInfo& pi) : Polygon(pi) {}
__host__ __device__ int area() override {
return (width * height / 2);
}
__host__ __device__ PolygonInfo get_info() override {
printf("triang get_info\n");
return PolygonInfo(width,height,PolygonType::triang);
}
};
static __global__ void wrong_example_kernel(Polygon *pols, int n_pols) {
Polygon *p = pols;
for (int i=0; i<n_pols; i++) {
printf("(device) p->area() = %d", p->area());
p++;
}
}
static __global__ void inst_obj_dev_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
//printf("%d %d\n", x,y);
size_t pols_size = sizeof(Polygon)*n_pols;
Polygon *pols = (Polygon*) malloc(pols_size);
for (int i=0; i<n_pols; i++) {
Polygon *tmp_p = nullptr;
//PolygonInfo tmp_pi = *(pols_infos+i);
PolygonInfo *pi_p = pols_infos+i;
//printf("w=%d, h=%d, ptype=%d\n", pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*(pols_infos+i));
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*(pols_infos+i));
} else {
printf("we have a problem...\n");
}
memcpy(pols+i, tmp_p, sizeof(*tmp_p));
}
printf("%d %d\n", x,y);
for (int i=0; i<n_pols; i++) {
printf("\t area = %d\n", pols[i].area());
}
}
__device__ Polygon *d_pols = nullptr;
__device__ int d_n_pols = 0;
static __global__ void copy_kernel(PolygonInfo *pols_infos, int n_pols) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
//printf("%d %d\n", x,y);
if (x >= n_pols) return;
if (x == 0) {
// only the first thread inits vars
printf("(%d) \n init...\n", x);
size_t pols_size = sizeof(Polygon)*n_pols;
d_pols = (Polygon*) malloc(pols_size);
d_n_pols = n_pols;
}
__syncthreads(); // all threads must wait
//cooperative_groups::this_thread_block().sync(); // alternative // does the same
Polygon *tmp_p = nullptr;
PolygonInfo *pi_p = pols_infos+x;
printf("(%d)\n w=%d, h=%d, ptype=%d\n", x, pi_p->width, pi_p->height, pi_p->ptype);
if (pi_p->ptype == PolygonType::rect) {
tmp_p = new Rectangle(*pi_p);
} else if (pi_p->ptype == PolygonType::triang) {
tmp_p = new Triangle(*pi_p);
} else if (pi_p->ptype == PolygonType::none) {
tmp_p = new Polygon(*pi_p);
} else {
printf("we have a problem...\n");
}
memcpy(d_pols+x, tmp_p, sizeof(*tmp_p));
}
static __global__ void kernel() {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (d_pols == nullptr) {
printf("%d %d\n pols=%p, d_n_pols=%d\n", x, y, d_pols, d_n_pols);
return;
}
for (int i=0; i<d_n_pols; i++) {
int area = d_pols[i].area();
if (area != 6 && area != 35)
printf("%d %d\n pols=%p, area = %d\n", x, y, d_pols, d_pols[i].area());
}
}
int main() {
hipDeviceProp_t prop;
int dev;
memset(&prop, 0, sizeof(hipDeviceProp_t));
prop.major = 1;
prop.minor = 0;
HANDLE_ERROR(
hipChooseDevice(&dev,&prop)
);
// Host init
//Polygon tri = Triangle(3,4);
Triangle tri(3,4);
std::cout << "tri.area() = " << tri.area() << std::endl;
Rectangle rec(5,7);
std::cout << "rec.area() = " << rec.area() << std::endl;
std::vector<Polygon*> pols;
pols.push_back(&tri);
pols.push_back(&rec);
for (Polygon *p : pols) {
std::cout << "p->area() = " << p->area() << std::endl;
}
// Now I want to move the vector to GPU and
// for each elem call area() from device
// { /// WRONG WAY
// size_t total_size = 0;
// for (Polygon *p : pols) {
// total_size += sizeof(*p);
// }
// Polygon *dev_pols = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols, total_size)
// );
// int offset = 0;
// for (Polygon *p : pols) {
// HANDLE_ERROR(
// cudaMemcpy((void*)(dev_pols+offset), (void*)p, sizeof(*p), cudaMemcpyHostToDevice)
// );
// offset++;
// }
// float grids = 1;
// float threads = 1;
// wrong_example_kernel<<<grids,threads>>>(dev_pols, pols.size());
// // this generate a wrong mem access because vtable on host
// } /// END // WRONG WAY
//{ /// INSTACING OBJS ON DEVICE
// size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
// PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
// int i = 0;
// for (Polygon *p : pols) {
// PolygonInfo pi = p->get_info();
// memcpy(&pols_infos[i], &pi, sizeof(pi));
// i++;
// }
// PolygonInfo *dev_pols_infos = nullptr;
// HANDLE_ERROR(
// cudaMalloc((void**)&dev_pols_infos, pols_infos_size)
// );
// HANDLE_ERROR(
// cudaMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, cudaMemcpyHostToDevice)
// );
// free(pols_infos);
// dim3 grids(1);
// dim3 threads(1);
// inst_obj_dev_kernel<<<grids,threads>>>(dev_pols_infos, pols.size());
//} /// END // INSTACING OBJS ON DEVICE
{ /// AS BEFORE BUT ONE KERNEL INST AND THE OTHER USE
size_t pols_infos_size = sizeof(PolygonInfo)*pols.size();
PolygonInfo *pols_infos = (PolygonInfo *) malloc(pols_infos_size);
int i = 0;
for (Polygon *p : pols) {
PolygonInfo pi = p->get_info();
memcpy(&pols_infos[i], &pi, sizeof(pi));
i++;
}
PolygonInfo *dev_pols_infos = nullptr;
HANDLE_ERROR(
hipMalloc((void**)&dev_pols_infos, pols_infos_size)
);
HANDLE_ERROR(
hipMemcpy((void*)dev_pols_infos, (void*)pols_infos, pols_infos_size, hipMemcpyHostToDevice)
);
free(pols_infos);
copy_kernel<<<1,pols.size()>>>(dev_pols_infos, pols.size());
HANDLE_ERROR(hipDeviceSynchronize());
dim3 grids(3,3);
dim3 threads(10,10);
kernel<<<grids,threads>>>();
} /// END
HANDLE_ERROR(hipDeviceSynchronize());
HANDLE_ERROR(hipDeviceReset());
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movq $1, 480(%rsp)
.cfi_escape 0x2e, 0x00
leaq 116(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $185, %esi
callq _ZL11HandleError10hipError_tPKci
movabsq $17179869187, %rax # imm = 0x400000003
movq %rax, 96(%rsp)
movq $_ZTV8Triangle+16, 88(%rsp)
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 100(%rsp), %eax
imull 96(%rsp), %eax
movl %eax, %esi
shrl $31, %esi
addl %eax, %esi
sarl %esi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_58
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $30064771077, %rax # imm = 0x700000005
movq %rax, 80(%rsp)
movq $_ZTV9Rectangle+16, 72(%rsp)
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 84(%rsp), %esi
imull 80(%rsp), %esi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_59
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB0_8
.LBB0_7:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $8, %edi
callq _Znwm
.Ltmp1:
# %bb.9: # %_ZNSt12_Vector_baseIP7PolygonSaIS1_EE11_M_allocateEm.exit.i.i
movq %rax, %r15
leaq 88(%rsp), %rax
movq %rax, (%r15)
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $16, %edi
callq _Znwm
.Ltmp4:
# %bb.10: # %_ZNSt12_Vector_baseIP7PolygonSaIS1_EE11_M_allocateEm.exit.i.i64
movq %rax, %rbx
leaq 72(%rsp), %rax
movq %rax, 8(%rbx)
movq (%r15), %rax
movq %rax, (%rbx)
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_11: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r12), %r14
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_11 Depth=1
movq (%r14), %rax
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq *(%rax)
.Ltmp9:
# %bb.13: # in Loop: Header=BB0_11 Depth=1
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp11:
# %bb.14: # in Loop: Header=BB0_11 Depth=1
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_15
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i72
# in Loop: Header=BB0_11 Depth=1
cmpb $0, 56(%r15)
je .LBB0_21
# %bb.20: # in Loop: Header=BB0_11 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_23
.p2align 4, 0x90
.LBB0_21: # in Loop: Header=BB0_11 Depth=1
.Ltmp12:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp13:
# %bb.22: # %.noexc76
# in Loop: Header=BB0_11 Depth=1
movq (%r15), %rax
.Ltmp14:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp15:
.LBB0_23: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB0_11 Depth=1
.Ltmp16:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp17:
# %bb.24: # %.noexc78
# in Loop: Header=BB0_11 Depth=1
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp19:
# %bb.25: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB0_11 Depth=1
addq $8, %r12
cmpq $16, %r12
jne .LBB0_11
# %bb.26:
.cfi_escape 0x2e, 0x00
movl $24, %edi
callq malloc
movq %rax, %r14
movq %rax, %r15
addq $8, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_27: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r12), %rdi
movq (%rdi), %rax
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq *8(%rax)
.Ltmp22:
# %bb.28: # in Loop: Header=BB0_27 Depth=1
movq %rax, -8(%r15)
movl %edx, (%r15)
addq $8, %r12
addq $12, %r15
cmpq $16, %r12
jne .LBB0_27
# %bb.29:
movq $0, (%rsp)
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $24, %esi
callq hipMalloc
.Ltmp25:
# %bb.30:
.Ltmp26:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $269, %esi # imm = 0x10D
callq _ZL11HandleError10hipError_tPKci
.Ltmp27:
# %bb.31:
movq (%rsp), %rdi
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl $24, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp29:
# %bb.32:
.Ltmp30:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $272, %esi # imm = 0x110
callq _ZL11HandleError10hipError_tPKci
.Ltmp31:
# %bb.33:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq free
.Ltmp32:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967298, %rdx # imm = 0x100000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp33:
# %bb.34:
testl %eax, %eax
jne .LBB0_37
# %bb.35:
movq (%rsp), %rax
movq %rax, 8(%rsp)
movl $2, 28(%rsp)
leaq 8(%rsp), %rax
movq %rax, 48(%rsp)
leaq 28(%rsp), %rax
movq %rax, 56(%rsp)
.Ltmp34:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp35:
# %bb.36: # %.noexc
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
.Ltmp36:
.cfi_escape 0x2e, 0x10
leaq 48(%rsp), %r9
movl $_ZL11copy_kernelP11PolygonInfoi, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp37:
.LBB0_37:
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp39:
# %bb.38:
.Ltmp40:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $277, %esi # imm = 0x115
callq _ZL11HandleError10hipError_tPKci
.Ltmp41:
# %bb.39:
.Ltmp43:
.cfi_escape 0x2e, 0x00
movabsq $12884901891, %rdi # imm = 0x300000003
movabsq $42949672970, %rdx # imm = 0xA0000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp44:
# %bb.40:
testl %eax, %eax
jne .LBB0_43
# %bb.41:
.Ltmp45:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp46:
# %bb.42: # %.noexc47
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp47:
.cfi_escape 0x2e, 0x10
leaq 64(%rsp), %r9
movl $_ZL6kernelv, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp48:
.LBB0_43:
.Ltmp50:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp51:
# %bb.44:
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $283, %esi # imm = 0x11B
callq _ZL11HandleError10hipError_tPKci
.Ltmp53:
# %bb.45:
.Ltmp54:
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
.Ltmp55:
# %bb.46:
.Ltmp56:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
movl $284, %esi # imm = 0x11C
callq _ZL11HandleError10hipError_tPKci
.Ltmp57:
# %bb.47: # %_ZNSt6vectorIP7PolygonSaIS1_EED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $1592, %rsp # imm = 0x638
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_15:
.cfi_def_cfa_offset 1632
.Ltmp59:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp60:
# %bb.18: # %.noexc75
.LBB0_58:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB0_59:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB0_17:
.Ltmp5:
movq %rax, %r14
movq %r15, %rbx
jmp .LBB0_55
.LBB0_16:
.Ltmp2:
movq %rax, %r14
xorl %ebx, %ebx
jmp .LBB0_55
.LBB0_52:
.Ltmp49:
jmp .LBB0_54
.LBB0_53:
.Ltmp58:
jmp .LBB0_54
.LBB0_51:
.Ltmp42:
jmp .LBB0_54
.LBB0_50:
.Ltmp23:
jmp .LBB0_54
.LBB0_49: # %.loopexit.split-lp
.Ltmp61:
jmp .LBB0_54
.LBB0_48: # %.loopexit
.Ltmp20:
.LBB0_54:
movq %rax, %r14
.LBB0_55:
testq %rbx, %rbx
je .LBB0_57
# %bb.56:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB0_57: # %_ZNSt6vectorIP7PolygonSaIS1_EED2Ev.exit50
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp19-.Ltmp6 # Call between .Ltmp6 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp41-.Ltmp24 # Call between .Ltmp24 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp48-.Ltmp43 # Call between .Ltmp43 and .Ltmp48
.uleb128 .Ltmp49-.Lfunc_begin0 # jumps to .Ltmp49
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp57-.Ltmp50 # Call between .Ltmp50 and .Ltmp57
.uleb128 .Ltmp58-.Lfunc_begin0 # jumps to .Ltmp58
.byte 0 # On action: cleanup
.uleb128 .Ltmp59-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp60-.Ltmp59 # Call between .Ltmp59 and .Ltmp60
.uleb128 .Ltmp61-.Lfunc_begin0 # jumps to .Ltmp61
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end0-.Ltmp60 # Call between .Ltmp60 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL11HandleError10hipError_tPKci
.type _ZL11HandleError10hipError_tPKci,@function
_ZL11HandleError10hipError_tPKci: # @_ZL11HandleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movl $_ZSt4cout, %edi
movl %esi, %ebx
movl $.L.str.4, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorName
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.5, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.6, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _ZL11HandleError10hipError_tPKci, .Lfunc_end1-_ZL11HandleError10hipError_tPKci
.cfi_endproc
# -- End function
.section .text._ZN8Triangle4areaEv,"axG",@progbits,_ZN8Triangle4areaEv,comdat
.weak _ZN8Triangle4areaEv # -- Begin function _ZN8Triangle4areaEv
.p2align 4, 0x90
.type _ZN8Triangle4areaEv,@function
_ZN8Triangle4areaEv: # @_ZN8Triangle4areaEv
.cfi_startproc
# %bb.0:
movl 12(%rdi), %ecx
imull 8(%rdi), %ecx
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
retq
.Lfunc_end2:
.size _ZN8Triangle4areaEv, .Lfunc_end2-_ZN8Triangle4areaEv
.cfi_endproc
# -- End function
.section .text._ZN9Rectangle4areaEv,"axG",@progbits,_ZN9Rectangle4areaEv,comdat
.weak _ZN9Rectangle4areaEv # -- Begin function _ZN9Rectangle4areaEv
.p2align 4, 0x90
.type _ZN9Rectangle4areaEv,@function
_ZN9Rectangle4areaEv: # @_ZN9Rectangle4areaEv
.cfi_startproc
# %bb.0:
movl 12(%rdi), %eax
imull 8(%rdi), %eax
retq
.Lfunc_end3:
.size _ZN9Rectangle4areaEv, .Lfunc_end3-_ZN9Rectangle4areaEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function _ZL26__device_stub__copy_kernelP11PolygonInfoi
.type _ZL26__device_stub__copy_kernelP11PolygonInfoi,@function
_ZL26__device_stub__copy_kernelP11PolygonInfoi: # @_ZL26__device_stub__copy_kernelP11PolygonInfoi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL11copy_kernelP11PolygonInfoi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _ZL26__device_stub__copy_kernelP11PolygonInfoi, .Lfunc_end4-_ZL26__device_stub__copy_kernelP11PolygonInfoi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL21__device_stub__kernelv
.type _ZL21__device_stub__kernelv,@function
_ZL21__device_stub__kernelv: # @_ZL21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_ZL6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end5:
.size _ZL21__device_stub__kernelv, .Lfunc_end5-_ZL21__device_stub__kernelv
.cfi_endproc
# -- End function
.section .text._ZN8Triangle8get_infoEv,"axG",@progbits,_ZN8Triangle8get_infoEv,comdat
.weak _ZN8Triangle8get_infoEv # -- Begin function _ZN8Triangle8get_infoEv
.p2align 4, 0x90
.type _ZN8Triangle8get_infoEv,@function
_ZN8Triangle8get_infoEv: # @_ZN8Triangle8get_infoEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq 8(%rbx), %rax
movl $2, %edx
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _ZN8Triangle8get_infoEv, .Lfunc_end6-_ZN8Triangle8get_infoEv
.cfi_endproc
# -- End function
.section .text._ZN7Polygon4areaEv,"axG",@progbits,_ZN7Polygon4areaEv,comdat
.weak _ZN7Polygon4areaEv # -- Begin function _ZN7Polygon4areaEv
.p2align 4, 0x90
.type _ZN7Polygon4areaEv,@function
_ZN7Polygon4areaEv: # @_ZN7Polygon4areaEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.Lstr.1, %edi
callq puts@PLT
movl 8(%rbx), %esi
movl 12(%rbx), %edx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _ZN7Polygon4areaEv, .Lfunc_end7-_ZN7Polygon4areaEv
.cfi_endproc
# -- End function
.section .text._ZN7Polygon8get_infoEv,"axG",@progbits,_ZN7Polygon8get_infoEv,comdat
.weak _ZN7Polygon8get_infoEv # -- Begin function _ZN7Polygon8get_infoEv
.p2align 4, 0x90
.type _ZN7Polygon8get_infoEv,@function
_ZN7Polygon8get_infoEv: # @_ZN7Polygon8get_infoEv
.cfi_startproc
# %bb.0:
movq 8(%rdi), %rax
xorl %edx, %edx
retq
.Lfunc_end8:
.size _ZN7Polygon8get_infoEv, .Lfunc_end8-_ZN7Polygon8get_infoEv
.cfi_endproc
# -- End function
.section .text._ZN9Rectangle8get_infoEv,"axG",@progbits,_ZN9Rectangle8get_infoEv,comdat
.weak _ZN9Rectangle8get_infoEv # -- Begin function _ZN9Rectangle8get_infoEv
.p2align 4, 0x90
.type _ZN9Rectangle8get_infoEv,@function
_ZN9Rectangle8get_infoEv: # @_ZN9Rectangle8get_infoEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rbx), %rax
movl $1, %edx
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _ZN9Rectangle8get_infoEv, .Lfunc_end9-_ZN9Rectangle8get_infoEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL11copy_kernelP11PolygonInfoi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL6kernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_pols, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $d_n_pols, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_pols,@object # @d_pols
.local d_pols
.comm d_pols,8,8
.type d_n_pols,@object # @d_n_pols
.local d_n_pols
.comm d_n_pols,4,4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Nyriu/Esercizi_Esempi_CUDA/main/07_polymorphism/02_passing_arguments/src/main.hip"
.size .L.str, 139
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "tri.area() = "
.size .L.str.1, 14
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "rec.area() = "
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "p->area() = "
.size .L.str.3, 13
.type _ZL11copy_kernelP11PolygonInfoi,@object # @_ZL11copy_kernelP11PolygonInfoi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL11copy_kernelP11PolygonInfoi:
.quad _ZL26__device_stub__copy_kernelP11PolygonInfoi
.size _ZL11copy_kernelP11PolygonInfoi, 8
.type _ZL6kernelv,@object # @_ZL6kernelv
.p2align 3, 0x0
_ZL6kernelv:
.quad _ZL21__device_stub__kernelv
.size _ZL6kernelv, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "Error Name: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " in "
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " line "
.size .L.str.6, 7
.type _ZTV8Triangle,@object # @_ZTV8Triangle
.section .rodata._ZTV8Triangle,"aG",@progbits,_ZTV8Triangle,comdat
.weak _ZTV8Triangle
.p2align 3, 0x0
_ZTV8Triangle:
.quad 0
.quad _ZTI8Triangle
.quad _ZN8Triangle4areaEv
.quad _ZN8Triangle8get_infoEv
.size _ZTV8Triangle, 32
.type _ZTS8Triangle,@object # @_ZTS8Triangle
.section .rodata._ZTS8Triangle,"aG",@progbits,_ZTS8Triangle,comdat
.weak _ZTS8Triangle
_ZTS8Triangle:
.asciz "8Triangle"
.size _ZTS8Triangle, 10
.type _ZTS7Polygon,@object # @_ZTS7Polygon
.section .rodata._ZTS7Polygon,"aG",@progbits,_ZTS7Polygon,comdat
.weak _ZTS7Polygon
_ZTS7Polygon:
.asciz "7Polygon"
.size _ZTS7Polygon, 9
.type _ZTI7Polygon,@object # @_ZTI7Polygon
.section .rodata._ZTI7Polygon,"aG",@progbits,_ZTI7Polygon,comdat
.weak _ZTI7Polygon
.p2align 3, 0x0
_ZTI7Polygon:
.quad _ZTVN10__cxxabiv117__class_type_infoE+16
.quad _ZTS7Polygon
.size _ZTI7Polygon, 16
.type _ZTI8Triangle,@object # @_ZTI8Triangle
.section .rodata._ZTI8Triangle,"aG",@progbits,_ZTI8Triangle,comdat
.weak _ZTI8Triangle
.p2align 3, 0x0
_ZTI8Triangle:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTS8Triangle
.quad _ZTI7Polygon
.size _ZTI8Triangle, 24
.type _ZTV7Polygon,@object # @_ZTV7Polygon
.section .rodata._ZTV7Polygon,"aG",@progbits,_ZTV7Polygon,comdat
.weak _ZTV7Polygon
.p2align 3, 0x0
_ZTV7Polygon:
.quad 0
.quad _ZTI7Polygon
.quad _ZN7Polygon4areaEv
.quad _ZN7Polygon8get_infoEv
.size _ZTV7Polygon, 32
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz " width = %d\n height = %d\n"
.size .L.str.8, 26
.type _ZTV9Rectangle,@object # @_ZTV9Rectangle
.section .rodata._ZTV9Rectangle,"aG",@progbits,_ZTV9Rectangle,comdat
.weak _ZTV9Rectangle
.p2align 3, 0x0
_ZTV9Rectangle:
.quad 0
.quad _ZTI9Rectangle
.quad _ZN9Rectangle4areaEv
.quad _ZN9Rectangle8get_infoEv
.size _ZTV9Rectangle, 32
.type _ZTS9Rectangle,@object # @_ZTS9Rectangle
.section .rodata._ZTS9Rectangle,"aG",@progbits,_ZTS9Rectangle,comdat
.weak _ZTS9Rectangle
_ZTS9Rectangle:
.asciz "9Rectangle"
.size _ZTS9Rectangle, 11
.type _ZTI9Rectangle,@object # @_ZTI9Rectangle
.section .rodata._ZTI9Rectangle,"aG",@progbits,_ZTI9Rectangle,comdat
.weak _ZTI9Rectangle
.p2align 3, 0x0
_ZTI9Rectangle:
.quad _ZTVN10__cxxabiv120__si_class_type_infoE+16
.quad _ZTS9Rectangle
.quad _ZTI7Polygon
.size _ZTI9Rectangle, 24
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL11copy_kernelP11PolygonInfoi"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL6kernelv"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "d_pols"
.size .L__unnamed_3, 7
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "d_n_pols"
.size .L__unnamed_4, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "triang get_info"
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nLOL here!"
.size .Lstr.1, 11
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "rect get_info"
.size .Lstr.2, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _ZL26__device_stub__copy_kernelP11PolygonInfoi
.addrsig_sym _ZL21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym d_pols
.addrsig_sym d_n_pols
.addrsig_sym _ZSt4cout
.addrsig_sym _ZL11copy_kernelP11PolygonInfoi
.addrsig_sym _ZL6kernelv
.addrsig_sym _ZTVN10__cxxabiv120__si_class_type_infoE
.addrsig_sym _ZTS8Triangle
.addrsig_sym _ZTVN10__cxxabiv117__class_type_infoE
.addrsig_sym _ZTS7Polygon
.addrsig_sym _ZTI7Polygon
.addrsig_sym _ZTI8Triangle
.addrsig_sym _ZTS9Rectangle
.addrsig_sym _ZTI9Rectangle
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <cuda.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
//Tamanhos dos blocos das threads
#define BLOCK_SIZE 32
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void cudaHistogram(PPMPixel* data, int rows, int cols, float* h){
//Definindo variaveis locais na funcao na GPU
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int tid = (cols)*row + col;
int j, k, l;
//Verificao para os limites das threads
if(col < (cols) && row < (rows)){
//Searching for the right value of the pixel
int x = 0;
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[tid].red == j && data[tid].green == k && data[tid].blue == l) {
atomicAdd(&h[x], 1);
}
x++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
cudaEvent_t start, stop;
float milliseconds = 0;
PPMPixel *pixels_dev;
float* h_dev;
float n = image->y * image->x;
//printf("%d, %d\n", rows, cols );
int i;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//Processo para calcular o tempo de alocar memoria na GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMalloc(&pixels_dev, sizeof(PPMPixel)*image->x*image->y);
cudaMalloc(&h_dev, sizeof(float)*64);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("Alocar Memoria = %f\n",milliseconds/1000);
//Calular o tempo de copiar dados da CPU para a GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(pixels_dev, image->data, image->x*image->y*sizeof(PPMPixel), cudaMemcpyHostToDevice);
cudaMemcpy(h_dev, h, 64*sizeof(float), cudaMemcpyHostToDevice);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nOffload do buffer = %f\n",milliseconds/1000);
dim3 blocks(1,1,1);
//variavel para threadsPerBlock e o tamanho do block para cada dimensao 2D
dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE,1);
//define a quantidade de blocos por dimensao/BLOCK_SIZE. se dimensao < block_size, entao define como 1 block
blocks.x=((image->y/BLOCK_SIZE) + (((image->y)%BLOCK_SIZE)==0?0:1));
blocks.y=((image->x/BLOCK_SIZE) + (((image->x)%BLOCK_SIZE)==0?0:1));
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaHistogram<<<blocks, threadsPerBlock>>> (pixels_dev, image->x, image->y, h_dev);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de kernel = %f\n",milliseconds/1000);
//GPU para CPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(h, h_dev, 64*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de offload para receber = %f\n",milliseconds/1001);
cudaFree(h_dev);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float n = image->y * image->x;
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
t_start = rtclock();
Histogram(image, h);
t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]/n);
}
printf("\n");
fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
} | code for sm_80
Function : _Z13cudaHistogramP8PPMPixeliiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3 ; /* 0x00000003ff027424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000037a24 */
/* 0x000fe400078e0203 */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0110*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1100 */
/*0120*/ BSSY B0, 0x210 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0130*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f05270 */
/*0140*/ @P0 BRA 0x200 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0170*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0180*/ @P0 BRA 0x200 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*01b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*01c0*/ @P0 BRA 0x200 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x000fca00078e00ff */
/*01e0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e784 */
/*01f0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fe20003f05270 */
/*0220*/ BSSY B1, 0xf70 ; /* 0x00000d4000017945 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B0, 0xeb0 ; /* 0x00000c7000007945 */
/* 0x000ff60003800000 */
/*0240*/ @P0 BRA 0x410 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0250*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0260*/ BSSY B2, 0x320 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0280*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0290*/ @P0 BRA 0x310 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*02c0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*02d0*/ @P0 BRA 0x310 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*02f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x4], R9 ; /* 0x000004090400798e */
/* 0x0001e8000c10e784 */
/*0300*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0310*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0330*/ @P0 BRA 0x500 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0350*/ BSSY B2, 0x410 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0370*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0380*/ @P0 BRA 0x400 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*03b0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*03c0*/ @P0 BRA 0x400 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*03e0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x8], R9 ; /* 0x000008090400798e */
/* 0x0001e8000c10e784 */
/*03f0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0400*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0420*/ @P0 BRA 0x5f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0440*/ BSSY B2, 0x500 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0450*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0460*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0470*/ @P0 BRA 0x4f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*04a0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*04b0*/ @P0 BRA 0x4f0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*04d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0xc], R9 ; /* 0x00000c090400798e */
/* 0x0001e8000c10e784 */
/*04e0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*04f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0510*/ @P0 BRA 0x6e0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0530*/ BSSY B2, 0x5f0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0540*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*0550*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0560*/ @P0 BRA 0x5e0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0580*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0590*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*05a0*/ @P0 BRA 0x5e0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*05c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x10], R9 ; /* 0x000010090400798e */
/* 0x0001e8000c10e784 */
/*05d0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*05e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0600*/ @P0 BRA 0x7d0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0620*/ BSSY B2, 0x6e0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0630*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0640*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0650*/ @P0 BRA 0x6d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0670*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0680*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0690*/ @P0 BRA 0x6d0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*06b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x14], R9 ; /* 0x000014090400798e */
/* 0x0001e8000c10e784 */
/*06c0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*06d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*06e0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*06f0*/ @P0 BRA 0x8c0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0710*/ BSSY B2, 0x7d0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0720*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0730*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0740*/ @P0 BRA 0x7c0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0760*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0770*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0780*/ @P0 BRA 0x7c0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0790*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*07a0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x18], R9 ; /* 0x000018090400798e */
/* 0x0001e8000c10e784 */
/*07b0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*07c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*07e0*/ @P0 BRA 0x9b0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0800*/ BSSY B2, 0x8c0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0810*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0820*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0830*/ @P0 BRA 0x8b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0850*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0860*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0870*/ @P0 BRA 0x8b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0890*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x1c], R9 ; /* 0x00001c090400798e */
/* 0x0001e8000c10e784 */
/*08a0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*08b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*08d0*/ @P0 BRA 0xaa0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*08f0*/ BSSY B2, 0x9b0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0900*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*0910*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0920*/ @P0 BRA 0x9a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0940*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0950*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0960*/ @P0 BRA 0x9a0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0970*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0980*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x20], R9 ; /* 0x000020090400798e */
/* 0x0001e8000c10e784 */
/*0990*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*09a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*09c0*/ @P0 BRA 0xb90 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*09e0*/ BSSY B2, 0xaa0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0a00*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0a10*/ @P0 BRA 0xa90 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0a20*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0a30*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0a40*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0a50*/ @P0 BRA 0xa90 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0a60*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0a70*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x24], R9 ; /* 0x000024090400798e */
/* 0x0001e8000c10e784 */
/*0a80*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0a90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0ab0*/ @P0 BRA 0xc80 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0ad0*/ BSSY B2, 0xb90 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0ae0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0af0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0b00*/ @P0 BRA 0xb80 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0b20*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0b30*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0b40*/ @P0 BRA 0xb80 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0b60*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x28], R9 ; /* 0x000028090400798e */
/* 0x0001e8000c10e784 */
/*0b70*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0b80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0ba0*/ @P0 BRA 0xd70 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0bc0*/ BSSY B2, 0xc80 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0bd0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0be0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0bf0*/ @P0 BRA 0xc70 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0c00*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0c10*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0c20*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0c30*/ @P0 BRA 0xc70 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0c50*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x2c], R9 ; /* 0x00002c090400798e */
/* 0x0001e8000c10e784 */
/*0c60*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0c70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0c90*/ @P0 BRA 0xe70 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0cb0*/ BSSY B2, 0xd70 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0cc0*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*0cd0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0ce0*/ @P0 BRA 0xd60 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0cf0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0d00*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0d10*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0d20*/ @P0 BRA 0xd60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0d30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0d40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x30], R9 ; /* 0x000030090400798e */
/* 0x0001e8000c10e784 */
/*0d50*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0d60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0d80*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*0d90*/ @P0 BRA 0xf60 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0da0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0db0*/ BSSY B2, 0xe70 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0dc0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0dd0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0de0*/ @P0 BRA 0xe60 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0df0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0e00*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0e10*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0e20*/ @P0 BRA 0xe60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0e30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0e40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x34], R9 ; /* 0x000034090400798e */
/* 0x0001e8000c10e784 */
/*0e50*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0e60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e70*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0e80*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*0e90*/ @P0 BRA 0xf60 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0ea0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0eb0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0ec0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0ed0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0ee0*/ @P0 BRA 0xf60 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0ef0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0f00*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0f10*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0f20*/ @P0 BRA 0xf60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0f30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0f40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x38], R9 ; /* 0x000038090400798e */
/* 0x0001e8000c10e784 */
/*0f50*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0f60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f70*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0f80*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fe20003f05270 */
/*0f90*/ BSSY B1, 0x1040 ; /* 0x000000a000017945 */
/* 0x000fd80003800000 */
/*0fa0*/ @P0 BRA 0x1030 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0fb0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea4000c1e1100 */
/*0fc0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0fd0*/ @P0 BRA 0x1030 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0fe0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea4000c1e1100 */
/*0ff0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*1000*/ @P0 BRA 0x1030 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*1010*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fca00078e00ff */
/*1020*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x3c], R7 ; /* 0x00003c070400798e */
/* 0x0003e4000c10e784 */
/*1030*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1040*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*1050*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x003fe40007f3e0ff */
/*1060*/ ISETP.NE.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fc60003f05270 */
/*1070*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fd400008e0605 */
/*1080*/ @!P0 CALL.REL.NOINC 0x10a0 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*1090*/ BRA 0x110 ; /* 0xfffff07000007947 */
/* 0x000fea000383ffff */
/*10a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10b0*/ BRA 0x10b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <cuda.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
//Tamanhos dos blocos das threads
#define BLOCK_SIZE 32
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void cudaHistogram(PPMPixel* data, int rows, int cols, float* h){
//Definindo variaveis locais na funcao na GPU
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int tid = (cols)*row + col;
int j, k, l;
//Verificao para os limites das threads
if(col < (cols) && row < (rows)){
//Searching for the right value of the pixel
int x = 0;
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[tid].red == j && data[tid].green == k && data[tid].blue == l) {
atomicAdd(&h[x], 1);
}
x++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
cudaEvent_t start, stop;
float milliseconds = 0;
PPMPixel *pixels_dev;
float* h_dev;
float n = image->y * image->x;
//printf("%d, %d\n", rows, cols );
int i;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//Processo para calcular o tempo de alocar memoria na GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMalloc(&pixels_dev, sizeof(PPMPixel)*image->x*image->y);
cudaMalloc(&h_dev, sizeof(float)*64);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("Alocar Memoria = %f\n",milliseconds/1000);
//Calular o tempo de copiar dados da CPU para a GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(pixels_dev, image->data, image->x*image->y*sizeof(PPMPixel), cudaMemcpyHostToDevice);
cudaMemcpy(h_dev, h, 64*sizeof(float), cudaMemcpyHostToDevice);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nOffload do buffer = %f\n",milliseconds/1000);
dim3 blocks(1,1,1);
//variavel para threadsPerBlock e o tamanho do block para cada dimensao 2D
dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE,1);
//define a quantidade de blocos por dimensao/BLOCK_SIZE. se dimensao < block_size, entao define como 1 block
blocks.x=((image->y/BLOCK_SIZE) + (((image->y)%BLOCK_SIZE)==0?0:1));
blocks.y=((image->x/BLOCK_SIZE) + (((image->x)%BLOCK_SIZE)==0?0:1));
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaHistogram<<<blocks, threadsPerBlock>>> (pixels_dev, image->x, image->y, h_dev);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de kernel = %f\n",milliseconds/1000);
//GPU para CPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(h, h_dev, 64*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de offload para receber = %f\n",milliseconds/1001);
cudaFree(h_dev);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float n = image->y * image->x;
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
t_start = rtclock();
Histogram(image, h);
t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]/n);
}
printf("\n");
fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
} | .file "tmpxft_001b2414_00000000-6_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
.type _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf, @function
_Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cudaHistogramP8PPMPixeliiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf, .-_Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
.globl _Z13cudaHistogramP8PPMPixeliiPf
.type _Z13cudaHistogramP8PPMPixeliiPf, @function
_Z13cudaHistogramP8PPMPixeliiPf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13cudaHistogramP8PPMPixeliiPf, .-_Z13cudaHistogramP8PPMPixeliiPf
.globl _Z9HistogramP8PPMImagePf
.type _Z9HistogramP8PPMImagePf, @function
_Z9HistogramP8PPMImagePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 12(%rsp)
movl 4(%rdi), %eax
imull (%rdi), %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movl $0, %eax
movl $0, %edx
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L18
.L20:
movq %rax, %rcx
addq 8(%rbx), %rcx
shrb $6, (%rcx)
movq %rax, %rcx
addq 8(%rbx), %rcx
shrb $6, 2(%rcx)
movq %rax, %rcx
addq 8(%rbx), %rcx
shrb $6, 1(%rcx)
addl $1, %edx
addq $3, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
comiss %xmm0, %xmm1
ja .L20
.L18:
leaq 16(%rsp), %r13
movq %r13, %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %r12
movq %r12, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq (%rbx), %rax
movslq 4(%rbx), %rdx
imulq %rdx, %rax
leaq (%rax,%rax,2), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %r14
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movq %r13, %rdi
call cudaEventCreate@PLT
movq %r12, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl (%rbx), %eax
imull 4(%rbx), %eax
cltq
leaq (%rax,%rax,2), %rdx
movq 8(%rbx), %rsi
movl $1, %ecx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl 4(%rbx), %edx
testb $31, %dl
setne %cl
movzbl %cl, %ecx
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl %ecx, %eax
movl %eax, 48(%rsp)
movl (%rbx), %edx
testb $31, %dl
setne %cl
movzbl %cl, %ecx
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl %ecx, %eax
movl %eax, 52(%rsp)
movq %r13, %rdi
call cudaEventCreate@PLT
movq %r12, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rbx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $256, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl 4(%rbx), %edx
movl (%rbx), %esi
movq 40(%rsp), %rcx
movq 32(%rsp), %rdi
call _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9HistogramP8PPMImagePf, .-_Z9HistogramP8PPMImagePf
.section .rodata.str1.8
.align 8
.LC3:
.string "Too many or no one arguments supplied.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "rb"
.LC5:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC7:
.string "Unable to allocate memory\n"
.LC8:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC9:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC10:
.string "%d"
.section .rodata.str1.8
.align 8
.LC11:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC12:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC13:
.string "Error loading image '%s'\n"
.LC14:
.string "%0.3f "
.LC15:
.string "\n"
.LC16:
.string "\n%0.6lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L53
.L30:
movq 8(%rbx), %rbp
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L54
leaq 48(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L55
cmpb $80, 48(%rsp)
jne .L33
cmpb $54, 49(%rsp)
jne .L33
movl $16, %edi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L56
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L36
.L37:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L37
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L37
.L36:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%r12), %rcx
movq %r12, %rdx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L57
leaq 44(%rsp), %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L58
cmpl $255, 44(%rsp)
jne .L59
.L41:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L41
movl (%r12), %r14d
movl 4(%r12), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%r12)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movq %rax, %rdx
movslq 4(%r12), %rax
cmpq %rax, %rdx
jne .L60
movq %rbx, %rdi
call fclose@PLT
movl 4(%r12), %eax
imull (%r12), %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
movss %xmm2, 12(%rsp)
movl $256, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 256(%rax), %rbp
.L43:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L43
call _Z7rtclockv
movsd %xmm0, 16(%rsp)
movq %r13, %rsi
movq %r12, %rdi
call _Z9HistogramP8PPMImagePf
call _Z7rtclockv
movsd %xmm0, 24(%rsp)
leaq .LC14(%rip), %r12
.L44:
movss (%rbx), %xmm0
divss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L44
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
subsd 16(%rsp), %xmm0
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L30
.L54:
movq %rbp, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movq %rbp, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movq %rbp, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movq %rbp, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movq %rbp, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movq %rbp, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z13cudaHistogramP8PPMPixeliiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaHistogramP8PPMPixeliiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <cuda.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
//Tamanhos dos blocos das threads
#define BLOCK_SIZE 32
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void cudaHistogram(PPMPixel* data, int rows, int cols, float* h){
//Definindo variaveis locais na funcao na GPU
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int tid = (cols)*row + col;
int j, k, l;
//Verificao para os limites das threads
if(col < (cols) && row < (rows)){
//Searching for the right value of the pixel
int x = 0;
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[tid].red == j && data[tid].green == k && data[tid].blue == l) {
atomicAdd(&h[x], 1);
}
x++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
cudaEvent_t start, stop;
float milliseconds = 0;
PPMPixel *pixels_dev;
float* h_dev;
float n = image->y * image->x;
//printf("%d, %d\n", rows, cols );
int i;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//Processo para calcular o tempo de alocar memoria na GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMalloc(&pixels_dev, sizeof(PPMPixel)*image->x*image->y);
cudaMalloc(&h_dev, sizeof(float)*64);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("Alocar Memoria = %f\n",milliseconds/1000);
//Calular o tempo de copiar dados da CPU para a GPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(pixels_dev, image->data, image->x*image->y*sizeof(PPMPixel), cudaMemcpyHostToDevice);
cudaMemcpy(h_dev, h, 64*sizeof(float), cudaMemcpyHostToDevice);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nOffload do buffer = %f\n",milliseconds/1000);
dim3 blocks(1,1,1);
//variavel para threadsPerBlock e o tamanho do block para cada dimensao 2D
dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE,1);
//define a quantidade de blocos por dimensao/BLOCK_SIZE. se dimensao < block_size, entao define como 1 block
blocks.x=((image->y/BLOCK_SIZE) + (((image->y)%BLOCK_SIZE)==0?0:1));
blocks.y=((image->x/BLOCK_SIZE) + (((image->x)%BLOCK_SIZE)==0?0:1));
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaHistogram<<<blocks, threadsPerBlock>>> (pixels_dev, image->x, image->y, h_dev);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de kernel = %f\n",milliseconds/1000);
//GPU para CPU
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(h, h_dev, 64*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de offload para receber = %f\n",milliseconds/1001);
cudaFree(h_dev);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float n = image->y * image->x;
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
t_start = rtclock();
Histogram(image, h);
t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]/n);
}
printf("\n");
fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
} | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
//Tamanhos dos blocos das threads
#define BLOCK_SIZE 32
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void cudaHistogram(PPMPixel* data, int rows, int cols, float* h){
//Definindo variaveis locais na funcao na GPU
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int tid = (cols)*row + col;
int j, k, l;
//Verificao para os limites das threads
if(col < (cols) && row < (rows)){
//Searching for the right value of the pixel
int x = 0;
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[tid].red == j && data[tid].green == k && data[tid].blue == l) {
atomicAdd(&h[x], 1);
}
x++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
hipEvent_t start, stop;
float milliseconds = 0;
PPMPixel *pixels_dev;
float* h_dev;
float n = image->y * image->x;
//printf("%d, %d\n", rows, cols );
int i;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//Processo para calcular o tempo de alocar memoria na GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMalloc(&pixels_dev, sizeof(PPMPixel)*image->x*image->y);
hipMalloc(&h_dev, sizeof(float)*64);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("Alocar Memoria = %f\n",milliseconds/1000);
//Calular o tempo de copiar dados da CPU para a GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(pixels_dev, image->data, image->x*image->y*sizeof(PPMPixel), hipMemcpyHostToDevice);
hipMemcpy(h_dev, h, 64*sizeof(float), hipMemcpyHostToDevice);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nOffload do buffer = %f\n",milliseconds/1000);
dim3 blocks(1,1,1);
//variavel para threadsPerBlock e o tamanho do block para cada dimensao 2D
dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE,1);
//define a quantidade de blocos por dimensao/BLOCK_SIZE. se dimensao < block_size, entao define como 1 block
blocks.x=((image->y/BLOCK_SIZE) + (((image->y)%BLOCK_SIZE)==0?0:1));
blocks.y=((image->x/BLOCK_SIZE) + (((image->x)%BLOCK_SIZE)==0?0:1));
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
cudaHistogram<<<blocks, threadsPerBlock>>> (pixels_dev, image->x, image->y, h_dev);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de kernel = %f\n",milliseconds/1000);
//GPU para CPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(h, h_dev, 64*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de offload para receber = %f\n",milliseconds/1001);
hipFree(h_dev);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float n = image->y * image->x;
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
t_start = rtclock();
Histogram(image, h);
t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]/n);
}
printf("\n");
fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
//Tamanhos dos blocos das threads
#define BLOCK_SIZE 32
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void cudaHistogram(PPMPixel* data, int rows, int cols, float* h){
//Definindo variaveis locais na funcao na GPU
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int tid = (cols)*row + col;
int j, k, l;
//Verificao para os limites das threads
if(col < (cols) && row < (rows)){
//Searching for the right value of the pixel
int x = 0;
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[tid].red == j && data[tid].green == k && data[tid].blue == l) {
atomicAdd(&h[x], 1);
}
x++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
hipEvent_t start, stop;
float milliseconds = 0;
PPMPixel *pixels_dev;
float* h_dev;
float n = image->y * image->x;
//printf("%d, %d\n", rows, cols );
int i;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//Processo para calcular o tempo de alocar memoria na GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMalloc(&pixels_dev, sizeof(PPMPixel)*image->x*image->y);
hipMalloc(&h_dev, sizeof(float)*64);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("Alocar Memoria = %f\n",milliseconds/1000);
//Calular o tempo de copiar dados da CPU para a GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(pixels_dev, image->data, image->x*image->y*sizeof(PPMPixel), hipMemcpyHostToDevice);
hipMemcpy(h_dev, h, 64*sizeof(float), hipMemcpyHostToDevice);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nOffload do buffer = %f\n",milliseconds/1000);
dim3 blocks(1,1,1);
//variavel para threadsPerBlock e o tamanho do block para cada dimensao 2D
dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE,1);
//define a quantidade de blocos por dimensao/BLOCK_SIZE. se dimensao < block_size, entao define como 1 block
blocks.x=((image->y/BLOCK_SIZE) + (((image->y)%BLOCK_SIZE)==0?0:1));
blocks.y=((image->x/BLOCK_SIZE) + (((image->x)%BLOCK_SIZE)==0?0:1));
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
cudaHistogram<<<blocks, threadsPerBlock>>> (pixels_dev, image->x, image->y, h_dev);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de kernel = %f\n",milliseconds/1000);
//GPU para CPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(h, h_dev, 64*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de offload para receber = %f\n",milliseconds/1001);
hipFree(h_dev);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float n = image->y * image->x;
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
t_start = rtclock();
Histogram(image, h);
t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]/n);
}
printf("\n");
fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cudaHistogramP8PPMPixeliiPf
.globl _Z13cudaHistogramP8PPMPixeliiPf
.p2align 8
.type _Z13cudaHistogramP8PPMPixeliiPf,@function
_Z13cudaHistogramP8PPMPixeliiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v8, 0
s_mov_b32 s2, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_i64_i32 v[0:1], null, v2, 3, s[4:5]
v_add_co_u32 v2, vcc_lo, v0, 1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, 2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, 4
s_cbranch_scc0 .LBB0_13
.LBB0_3:
s_mov_b32 s7, 0
s_branch .LBB0_5
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s7, 4
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, 1
s_add_i32 s2, s2, 1
s_cmp_lg_u32 s8, 4
s_cbranch_scc0 .LBB0_4
.LBB0_7:
global_load_u8 v6, v[0:1], off
s_mov_b32 s9, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s6, v6
s_cbranch_execz .LBB0_6
global_load_u8 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s7, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
global_load_u8 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s8, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_mov_b32 s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v6, s10, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 2
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_bcnt1_i32_b32 s3, s10
global_load_b32 v7, v8, s[4:5]
v_cvt_f32_ubyte0_e32 v9, s3
s_mov_b32 s3, 0
.LBB0_12:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v7, v9
global_atomic_cmpswap_b32 v6, v8, v[6:7], s[4:5] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_12
s_branch .LBB0_6
.LBB0_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cudaHistogramP8PPMPixeliiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cudaHistogramP8PPMPixeliiPf, .Lfunc_end0-_Z13cudaHistogramP8PPMPixeliiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cudaHistogramP8PPMPixeliiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cudaHistogramP8PPMPixeliiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define COMMENT "Histogram_GPU"
#define RGB_COMPONENT_COLOR 255
//Tamanhos dos blocos das threads
#define BLOCK_SIZE 32
typedef struct {
unsigned char red, green, blue;
} PPMPixel;
typedef struct {
int x, y;
PPMPixel *data;
} PPMImage;
double rtclock()
{
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday (&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d",stat);
return(Tp.tv_sec + Tp.tv_usec*1.0e-6);
}
static PPMImage *readPPM(const char *filename) {
char buff[16];
PPMImage *img;
FILE *fp;
int c, rgb_comp_color;
fp = fopen(filename, "rb");
if (!fp) {
fprintf(stderr, "Unable to open file '%s'\n", filename);
exit(1);
}
if (!fgets(buff, sizeof(buff), fp)) {
perror(filename);
exit(1);
}
if (buff[0] != 'P' || buff[1] != '6') {
fprintf(stderr, "Invalid image format (must be 'P6')\n");
exit(1);
}
img = (PPMImage *) malloc(sizeof(PPMImage));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
c = getc(fp);
while (c == '#') {
while (getc(fp) != '\n')
;
c = getc(fp);
}
ungetc(c, fp);
if (fscanf(fp, "%d %d", &img->x, &img->y) != 2) {
fprintf(stderr, "Invalid image size (error loading '%s')\n", filename);
exit(1);
}
if (fscanf(fp, "%d", &rgb_comp_color) != 1) {
fprintf(stderr, "Invalid rgb component (error loading '%s')\n",
filename);
exit(1);
}
if (rgb_comp_color != RGB_COMPONENT_COLOR) {
fprintf(stderr, "'%s' does not have 8-bits components\n", filename);
exit(1);
}
while (fgetc(fp) != '\n')
;
img->data = (PPMPixel*) malloc(img->x * img->y * sizeof(PPMPixel));
if (!img) {
fprintf(stderr, "Unable to allocate memory\n");
exit(1);
}
if (fread(img->data, 3 * img->x, img->y, fp) != img->y) {
fprintf(stderr, "Error loading image '%s'\n", filename);
exit(1);
}
fclose(fp);
return img;
}
__global__ void cudaHistogram(PPMPixel* data, int rows, int cols, float* h){
//Definindo variaveis locais na funcao na GPU
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int tid = (cols)*row + col;
int j, k, l;
//Verificao para os limites das threads
if(col < (cols) && row < (rows)){
//Searching for the right value of the pixel
int x = 0;
for (j = 0; j <= 3; j++) {
for (k = 0; k <= 3; k++) {
for (l = 0; l <= 3; l++) {
if (data[tid].red == j && data[tid].green == k && data[tid].blue == l) {
atomicAdd(&h[x], 1);
}
x++;
}
}
}
}
}
void Histogram(PPMImage *image, float *h) {
hipEvent_t start, stop;
float milliseconds = 0;
PPMPixel *pixels_dev;
float* h_dev;
float n = image->y * image->x;
//printf("%d, %d\n", rows, cols );
int i;
for (i = 0; i < n; i++) {
image->data[i].red = floor((image->data[i].red * 4) / 256);
image->data[i].blue = floor((image->data[i].blue * 4) / 256);
image->data[i].green = floor((image->data[i].green * 4) / 256);
}
//Processo para calcular o tempo de alocar memoria na GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMalloc(&pixels_dev, sizeof(PPMPixel)*image->x*image->y);
hipMalloc(&h_dev, sizeof(float)*64);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("Alocar Memoria = %f\n",milliseconds/1000);
//Calular o tempo de copiar dados da CPU para a GPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(pixels_dev, image->data, image->x*image->y*sizeof(PPMPixel), hipMemcpyHostToDevice);
hipMemcpy(h_dev, h, 64*sizeof(float), hipMemcpyHostToDevice);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nOffload do buffer = %f\n",milliseconds/1000);
dim3 blocks(1,1,1);
//variavel para threadsPerBlock e o tamanho do block para cada dimensao 2D
dim3 threadsPerBlock(BLOCK_SIZE,BLOCK_SIZE,1);
//define a quantidade de blocos por dimensao/BLOCK_SIZE. se dimensao < block_size, entao define como 1 block
blocks.x=((image->y/BLOCK_SIZE) + (((image->y)%BLOCK_SIZE)==0?0:1));
blocks.y=((image->x/BLOCK_SIZE) + (((image->x)%BLOCK_SIZE)==0?0:1));
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
cudaHistogram<<<blocks, threadsPerBlock>>> (pixels_dev, image->x, image->y, h_dev);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de kernel = %f\n",milliseconds/1000);
//GPU para CPU
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(h, h_dev, 64*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milliseconds, start, stop);
//printf("\nTempo de offload para receber = %f\n",milliseconds/1001);
hipFree(h_dev);
}
int main(int argc, char *argv[]) {
if( argc != 2 ) {
printf("Too many or no one arguments supplied.\n");
}
double t_start, t_end;
int i;
char *filename = argv[1]; //Recebendo o arquivo!;
//scanf("%s", filename);
PPMImage *image = readPPM(filename);
float n = image->y * image->x;
float *h = (float*)malloc(sizeof(float) * 64);
//Inicializar h
for(i=0; i < 64; i++) h[i] = 0.0;
t_start = rtclock();
Histogram(image, h);
t_end = rtclock();
for (i = 0; i < 64; i++){
printf("%0.3f ", h[i]/n);
}
printf("\n");
fprintf(stdout, "\n%0.6lfs\n", t_end - t_start);
free(h);
} | .text
.file "histogram.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z28__device_stub__cudaHistogramP8PPMPixeliiPf # -- Begin function _Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.p2align 4, 0x90
.type _Z28__device_stub__cudaHistogramP8PPMPixeliiPf,@function
_Z28__device_stub__cudaHistogramP8PPMPixeliiPf: # @_Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cudaHistogramP8PPMPixeliiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__cudaHistogramP8PPMPixeliiPf, .Lfunc_end1-_Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.cfi_endproc
# -- End function
.globl _Z9HistogramP8PPMImagePf # -- Begin function _Z9HistogramP8PPMImagePf
.p2align 4, 0x90
.type _Z9HistogramP8PPMImagePf,@function
_Z9HistogramP8PPMImagePf: # @_Z9HistogramP8PPMImagePf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $0, 20(%rsp)
movl (%rdi), %eax
imull 4(%rdi), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.lr.ph
cvtsi2ss %eax, %xmm0
movq 8(%r14), %rax
addq $2, %rax
movl $1, %ecx
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
shrb $6, -2(%rax)
shrb $6, (%rax)
shrb $6, -1(%rax)
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
addq $3, %rax
incl %ecx
ucomiss %xmm1, %xmm0
ja .LBB2_2
.LBB2_3: # %._crit_edge
leaq 8(%rsp), %r15
movq %r15, %rdi
callq hipEventCreate
movq %rsp, %r12
movq %r12, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq (%r14), %rax
movslq 4(%r14), %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq 8(%r14), %rsi
movslq (%r14), %rax
movslq 4(%r14), %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movl (%r14), %eax
movl 4(%r14), %ecx
leal 31(%rcx), %edx
testl %ecx, %ecx
cmovnsl %ecx, %edx
sarl $5, %edx
andl $31, %ecx
cmpl $1, %ecx
sbbl $-1, %edx
leal 31(%rax), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $5, %r13d
andl $31, %eax
cmpl $1, %eax
sbbl $-1, %r13d
shlq $32, %r13
orq %rdx, %r13
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 40(%rsp), %rax
movl (%r14), %ecx
movl 4(%r14), %edx
movq 24(%rsp), %rsi
movq %rax, 104(%rsp)
movl %ecx, 36(%rsp)
movl %edx, 32(%rsp)
movq %rsi, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13cudaHistogramP8PPMPixeliiPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %r14
movq %r14, %rdi
callq hipEventElapsedTime
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9HistogramP8PPMImagePf, .Lfunc_end2-_Z9HistogramP8PPMImagePf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movq 8(%rbx), %rbx
movl $.L.str.5, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB3_3
# %bb.5:
movq %rax, %r15
movq %rsp, %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB3_31
# %bb.6:
cmpb $80, (%rsp)
jne .LBB3_8
# %bb.7:
cmpb $54, 1(%rsp)
jne .LBB3_8
# %bb.10:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB3_11
# %bb.12:
movq %rax, %r14
.p2align 4, 0x90
.LBB3_13: # =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
movq %r15, %rdi
callq getc
cmpl $35, %eax
jne .LBB3_15
.LBB3_14: # %.preheader44.i
# Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
callq getc
cmpl $10, %eax
jne .LBB3_14
jmp .LBB3_13
.LBB3_15: # %._crit_edge.i
movl %eax, %edi
movq %r15, %rsi
callq ungetc
movq %r14, %rcx
addq $4, %rcx
movl $.L.str.9, %esi
movq %r15, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB3_16
# %bb.17:
leaq 32(%rsp), %rdx
movl $.L.str.11, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB3_18
# %bb.19:
cmpl $255, 32(%rsp)
jne .LBB3_20
.p2align 4, 0x90
.LBB3_21: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB3_21
# %bb.22:
movslq (%r14), %rax
movslq 4(%r14), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r14)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r15, %rcx
callq fread
movslq 4(%r14), %rcx
cmpq %rcx, %rax
jne .LBB3_23
# %bb.24: # %_ZL7readPPMPKc.exit
movq %r15, %rdi
callq fclose
movl (%r14), %ebp
imull 4(%r14), %ebp
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movups %xmm0, 192(%rax)
movups %xmm0, 208(%rax)
movups %xmm0, 224(%rax)
movups %xmm0, 240(%rax)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB3_26
# %bb.25:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB3_26: # %_Z7rtclockv.exit
movq (%rsp), %r15
movq 8(%rsp), %r12
movq %r14, %rdi
movq %rbx, %rsi
callq _Z9HistogramP8PPMImagePf
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB3_28
# %bb.27:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB3_28: # %_Z7rtclockv.exit21
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movss %xmm0, 24(%rsp) # 4-byte Spill
movq (%rsp), %r14
movq 8(%rsp), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_29: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 24(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $64, %rbp
jne .LBB3_29
# %bb.30:
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsi2sd %r14, %xmm2
addsd %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
mulsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
addsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movl $10, %edi
callq putchar@PLT
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
jmp .LBB3_4
.LBB3_31:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB3_8:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $36, %esi
jmp .LBB3_9
.LBB3_11:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $26, %esi
.LBB3_9:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB3_16:
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
jmp .LBB3_4
.LBB3_18:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
jmp .LBB3_4
.LBB3_20:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
jmp .LBB3_4
.LBB3_23:
movq stderr(%rip), %rdi
movl $.L.str.14, %esi
.LBB3_4:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cudaHistogramP8PPMPixeliiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type _Z13cudaHistogramP8PPMPixeliiPf,@object # @_Z13cudaHistogramP8PPMPixeliiPf
.section .rodata,"a",@progbits
.globl _Z13cudaHistogramP8PPMPixeliiPf
.p2align 3, 0x0
_Z13cudaHistogramP8PPMPixeliiPf:
.quad _Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.size _Z13cudaHistogramP8PPMPixeliiPf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%0.3f "
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n%0.6lfs\n"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Unable to open file '%s'\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Unable to allocate memory\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d %d"
.size .L.str.9, 6
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.13, 38
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Error loading image '%s'\n"
.size .L.str.14, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13cudaHistogramP8PPMPixeliiPf"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cudaHistogramP8PPMPixeliiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13cudaHistogramP8PPMPixeliiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x3 ; /* 0x00000003ff027424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000037a24 */
/* 0x000fe400078e0203 */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0110*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1100 */
/*0120*/ BSSY B0, 0x210 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0130*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x004fda0003f05270 */
/*0140*/ @P0 BRA 0x200 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0150*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0170*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0180*/ @P0 BRA 0x200 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*01b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*01c0*/ @P0 BRA 0x200 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x000fca00078e00ff */
/*01e0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e784 */
/*01f0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fe20003f05270 */
/*0220*/ BSSY B1, 0xf70 ; /* 0x00000d4000017945 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B0, 0xeb0 ; /* 0x00000c7000007945 */
/* 0x000ff60003800000 */
/*0240*/ @P0 BRA 0x410 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0250*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0260*/ BSSY B2, 0x320 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0280*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0290*/ @P0 BRA 0x310 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*02a0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*02c0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*02d0*/ @P0 BRA 0x310 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*02f0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x4], R9 ; /* 0x000004090400798e */
/* 0x0001e8000c10e784 */
/*0300*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0310*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0330*/ @P0 BRA 0x500 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0350*/ BSSY B2, 0x410 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0370*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0380*/ @P0 BRA 0x400 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*03b0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*03c0*/ @P0 BRA 0x400 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*03e0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x8], R9 ; /* 0x000008090400798e */
/* 0x0001e8000c10e784 */
/*03f0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0400*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0420*/ @P0 BRA 0x5f0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0430*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0440*/ BSSY B2, 0x500 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0450*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0460*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0470*/ @P0 BRA 0x4f0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*04a0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*04b0*/ @P0 BRA 0x4f0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*04c0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*04d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0xc], R9 ; /* 0x00000c090400798e */
/* 0x0001e8000c10e784 */
/*04e0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*04f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0510*/ @P0 BRA 0x6e0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0530*/ BSSY B2, 0x5f0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0540*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*0550*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0560*/ @P0 BRA 0x5e0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0570*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0580*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0590*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*05a0*/ @P0 BRA 0x5e0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*05b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*05c0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x10], R9 ; /* 0x000010090400798e */
/* 0x0001e8000c10e784 */
/*05d0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*05e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0600*/ @P0 BRA 0x7d0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0610*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0620*/ BSSY B2, 0x6e0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0630*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0640*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0650*/ @P0 BRA 0x6d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0660*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0670*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0680*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0690*/ @P0 BRA 0x6d0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*06b0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x14], R9 ; /* 0x000014090400798e */
/* 0x0001e8000c10e784 */
/*06c0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*06d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*06e0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*06f0*/ @P0 BRA 0x8c0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0710*/ BSSY B2, 0x7d0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0720*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0730*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0740*/ @P0 BRA 0x7c0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0760*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0770*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0780*/ @P0 BRA 0x7c0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0790*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*07a0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x18], R9 ; /* 0x000018090400798e */
/* 0x0001e8000c10e784 */
/*07b0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*07c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*07e0*/ @P0 BRA 0x9b0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0800*/ BSSY B2, 0x8c0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0810*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0820*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0830*/ @P0 BRA 0x8b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0850*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0860*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0870*/ @P0 BRA 0x8b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0890*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x1c], R9 ; /* 0x00001c090400798e */
/* 0x0001e8000c10e784 */
/*08a0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*08b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08c0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*08d0*/ @P0 BRA 0xaa0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*08e0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*08f0*/ BSSY B2, 0x9b0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0900*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*0910*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0920*/ @P0 BRA 0x9a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0940*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0950*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0960*/ @P0 BRA 0x9a0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0970*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0980*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x20], R9 ; /* 0x000020090400798e */
/* 0x0001e8000c10e784 */
/*0990*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*09a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*09c0*/ @P0 BRA 0xb90 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*09e0*/ BSSY B2, 0xaa0 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0a00*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0a10*/ @P0 BRA 0xa90 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0a20*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0a30*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0a40*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0a50*/ @P0 BRA 0xa90 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0a60*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0a70*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x24], R9 ; /* 0x000024090400798e */
/* 0x0001e8000c10e784 */
/*0a80*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0a90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0ab0*/ @P0 BRA 0xc80 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0ad0*/ BSSY B2, 0xb90 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0ae0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0af0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0b00*/ @P0 BRA 0xb80 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0b20*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0b30*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0b40*/ @P0 BRA 0xb80 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0b60*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x28], R9 ; /* 0x000028090400798e */
/* 0x0001e8000c10e784 */
/*0b70*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0b80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0ba0*/ @P0 BRA 0xd70 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0bb0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0bc0*/ BSSY B2, 0xc80 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0bd0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0be0*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0bf0*/ @P0 BRA 0xc70 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0c00*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0c10*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0c20*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0c30*/ @P0 BRA 0xc70 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0c40*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0c50*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x2c], R9 ; /* 0x00002c090400798e */
/* 0x0001e8000c10e784 */
/*0c60*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0c70*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0c90*/ @P0 BRA 0xe70 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0cb0*/ BSSY B2, 0xd70 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0cc0*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe40000000f00 */
/*0cd0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0ce0*/ @P0 BRA 0xd60 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0cf0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0d00*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0d10*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*0d20*/ @P0 BRA 0xd60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0d30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0d40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x30], R9 ; /* 0x000030090400798e */
/* 0x0001e8000c10e784 */
/*0d50*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0d60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0d80*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*0d90*/ @P0 BRA 0xf60 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0da0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0db0*/ BSSY B2, 0xe70 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*0dc0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0dd0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0de0*/ @P0 BRA 0xe60 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0df0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0e00*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0e10*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fda0003f05270 */
/*0e20*/ @P0 BRA 0xe60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0e30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0e40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x34], R9 ; /* 0x000034090400798e */
/* 0x0001e8000c10e784 */
/*0e50*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0e60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e70*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fda0003f05270 */
/*0e80*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*0e90*/ @P0 BRA 0xf60 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*0ea0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0eb0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea2000c1e1100 */
/*0ec0*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0ed0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0ee0*/ @P0 BRA 0xf60 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0ef0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea2000c1e1100 */
/*0f00*/ IMAD.MOV.U32 R7, RZ, RZ, R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0000 */
/*0f10*/ ISETP.NE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x004fda0003f05270 */
/*0f20*/ @P0 BRA 0xf60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0f30*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff097424 */
/* 0x001fca00078e00ff */
/*0f40*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x38], R9 ; /* 0x000038090400798e */
/* 0x0001e8000c10e784 */
/*0f50*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1100 */
/*0f60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f70*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0f80*/ ISETP.NE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x020fe20003f05270 */
/*0f90*/ BSSY B1, 0x1040 ; /* 0x000000a000017945 */
/* 0x000fd80003800000 */
/*0fa0*/ @P0 BRA 0x1030 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0fb0*/ LDG.E.U8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea4000c1e1100 */
/*0fc0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*0fd0*/ @P0 BRA 0x1030 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0fe0*/ LDG.E.U8 R6, [R2.64+0x2] ; /* 0x0000020402067981 */
/* 0x000ea4000c1e1100 */
/*0ff0*/ ISETP.NE.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x004fda0003f05270 */
/*1000*/ @P0 BRA 0x1030 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*1010*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fca00078e00ff */
/*1020*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R4.64+0x3c], R7 ; /* 0x00003c070400798e */
/* 0x0003e4000c10e784 */
/*1030*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1040*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*1050*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x003fe40007f3e0ff */
/*1060*/ ISETP.NE.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fc60003f05270 */
/*1070*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fd400008e0605 */
/*1080*/ @!P0 CALL.REL.NOINC 0x10a0 ; /* 0x0000001000008944 */
/* 0x000fe20003c00000 */
/*1090*/ BRA 0x110 ; /* 0xfffff07000007947 */
/* 0x000fea000383ffff */
/*10a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10b0*/ BRA 0x10b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13cudaHistogramP8PPMPixeliiPf
.globl _Z13cudaHistogramP8PPMPixeliiPf
.p2align 8
.type _Z13cudaHistogramP8PPMPixeliiPf,@function
_Z13cudaHistogramP8PPMPixeliiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_13
s_load_b64 s[4:5], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v8, 0
s_mov_b32 s2, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_i64_i32 v[0:1], null, v2, 3, s[4:5]
v_add_co_u32 v2, vcc_lo, v0, 1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, 2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, 4
s_cbranch_scc0 .LBB0_13
.LBB0_3:
s_mov_b32 s7, 0
s_branch .LBB0_5
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s7, 4
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_mov_b32 s8, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, 1
s_add_i32 s2, s2, 1
s_cmp_lg_u32 s8, 4
s_cbranch_scc0 .LBB0_4
.LBB0_7:
global_load_u8 v6, v[0:1], off
s_mov_b32 s9, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 s6, v6
s_cbranch_execz .LBB0_6
global_load_u8 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s7, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
global_load_u8 v6, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s8, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
s_mov_b32 s10, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v6, s10, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 2
s_add_u32 s4, s0, s4
s_addc_u32 s5, s1, s5
s_bcnt1_i32_b32 s3, s10
global_load_b32 v7, v8, s[4:5]
v_cvt_f32_ubyte0_e32 v9, s3
s_mov_b32 s3, 0
.LBB0_12:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v7, v9
global_atomic_cmpswap_b32 v6, v8, v[6:7], s[4:5] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_12
s_branch .LBB0_6
.LBB0_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13cudaHistogramP8PPMPixeliiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13cudaHistogramP8PPMPixeliiPf, .Lfunc_end0-_Z13cudaHistogramP8PPMPixeliiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13cudaHistogramP8PPMPixeliiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13cudaHistogramP8PPMPixeliiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b2414_00000000-6_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
.type _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf, @function
_Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13cudaHistogramP8PPMPixeliiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf, .-_Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
.globl _Z13cudaHistogramP8PPMPixeliiPf
.type _Z13cudaHistogramP8PPMPixeliiPf, @function
_Z13cudaHistogramP8PPMPixeliiPf:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13cudaHistogramP8PPMPixeliiPf, .-_Z13cudaHistogramP8PPMPixeliiPf
.globl _Z9HistogramP8PPMImagePf
.type _Z9HistogramP8PPMImagePf, @function
_Z9HistogramP8PPMImagePf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %rbx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0x00000000, 12(%rsp)
movl 4(%rdi), %eax
imull (%rdi), %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movl $0, %eax
movl $0, %edx
pxor %xmm0, %xmm0
comiss %xmm0, %xmm1
jbe .L18
.L20:
movq %rax, %rcx
addq 8(%rbx), %rcx
shrb $6, (%rcx)
movq %rax, %rcx
addq 8(%rbx), %rcx
shrb $6, 2(%rcx)
movq %rax, %rcx
addq 8(%rbx), %rcx
shrb $6, 1(%rcx)
addl $1, %edx
addq $3, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
comiss %xmm0, %xmm1
ja .L20
.L18:
leaq 16(%rsp), %r13
movq %r13, %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %r12
movq %r12, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movslq (%rbx), %rax
movslq 4(%rbx), %rdx
imulq %rdx, %rax
leaq (%rax,%rax,2), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %r14
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movq %r13, %rdi
call cudaEventCreate@PLT
movq %r12, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl (%rbx), %eax
imull 4(%rbx), %eax
cltq
leaq (%rax,%rax,2), %rdx
movq 8(%rbx), %rsi
movl $1, %ecx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaEventElapsedTime@PLT
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl 4(%rbx), %edx
testb $31, %dl
setne %cl
movzbl %cl, %ecx
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl %ecx, %eax
movl %eax, 48(%rsp)
movl (%rbx), %edx
testb $31, %dl
setne %cl
movzbl %cl, %ecx
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl %ecx, %eax
movl %eax, 52(%rsp)
movq %r13, %rdi
call cudaEventCreate@PLT
movq %r12, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rbx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $256, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaEventElapsedTime@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl 4(%rbx), %edx
movl (%rbx), %esi
movq 40(%rsp), %rcx
movq 32(%rsp), %rdi
call _Z45__device_stub__Z13cudaHistogramP8PPMPixeliiPfP8PPMPixeliiPf
jmp .L21
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9HistogramP8PPMImagePf, .-_Z9HistogramP8PPMImagePf
.section .rodata.str1.8
.align 8
.LC3:
.string "Too many or no one arguments supplied.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "rb"
.LC5:
.string "Unable to open file '%s'\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Invalid image format (must be 'P6')\n"
.section .rodata.str1.1
.LC7:
.string "Unable to allocate memory\n"
.LC8:
.string "%d %d"
.section .rodata.str1.8
.align 8
.LC9:
.string "Invalid image size (error loading '%s')\n"
.section .rodata.str1.1
.LC10:
.string "%d"
.section .rodata.str1.8
.align 8
.LC11:
.string "Invalid rgb component (error loading '%s')\n"
.align 8
.LC12:
.string "'%s' does not have 8-bits components\n"
.section .rodata.str1.1
.LC13:
.string "Error loading image '%s'\n"
.LC14:
.string "%0.3f "
.LC15:
.string "\n"
.LC16:
.string "\n%0.6lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L53
.L30:
movq 8(%rbx), %rbp
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L54
leaq 48(%rsp), %rdi
movq %rax, %rcx
movl $16, %edx
movl $16, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L55
cmpb $80, 48(%rsp)
jne .L33
cmpb $54, 49(%rsp)
jne .L33
movl $16, %edi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L56
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
jne .L36
.L37:
movq %rbx, %rdi
call getc@PLT
cmpl $10, %eax
jne .L37
movq %rbx, %rdi
call getc@PLT
cmpl $35, %eax
je .L37
.L36:
movq %rbx, %rsi
movl %eax, %edi
call ungetc@PLT
leaq 4(%r12), %rcx
movq %r12, %rdx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $2, %eax
jne .L57
leaq 44(%rsp), %rdx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $1, %eax
jne .L58
cmpl $255, 44(%rsp)
jne .L59
.L41:
movq %rbx, %rdi
call fgetc@PLT
cmpl $10, %eax
jne .L41
movl (%r12), %r14d
movl 4(%r12), %r13d
movl %r14d, %eax
imull %r13d, %eax
cltq
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%r12)
movslq %r13d, %rcx
leal (%r14,%r14,2), %edx
movslq %edx, %rdx
movq %rbx, %r8
movq %r15, %rsi
call __fread_chk@PLT
movq %rax, %rdx
movslq 4(%r12), %rax
cmpq %rax, %rdx
jne .L60
movq %rbx, %rdi
call fclose@PLT
movl 4(%r12), %eax
imull (%r12), %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
movss %xmm2, 12(%rsp)
movl $256, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, %rbx
leaq 256(%rax), %rbp
.L43:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L43
call _Z7rtclockv
movsd %xmm0, 16(%rsp)
movq %r13, %rsi
movq %r12, %rdi
call _Z9HistogramP8PPMImagePf
call _Z7rtclockv
movsd %xmm0, 24(%rsp)
leaq .LC14(%rip), %r12
.L44:
movss (%rbx), %xmm0
divss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L44
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
subsd 16(%rsp), %xmm0
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L30
.L54:
movq %rbp, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movq %rbp, %rdi
call perror@PLT
movl $1, %edi
call exit@PLT
.L33:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movq %rbp, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movq %rbp, %rcx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movq %rbp, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movq %rbp, %rcx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC17:
.string "_Z13cudaHistogramP8PPMPixeliiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z13cudaHistogramP8PPMPixeliiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histogram.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z28__device_stub__cudaHistogramP8PPMPixeliiPf # -- Begin function _Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.p2align 4, 0x90
.type _Z28__device_stub__cudaHistogramP8PPMPixeliiPf,@function
_Z28__device_stub__cudaHistogramP8PPMPixeliiPf: # @_Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13cudaHistogramP8PPMPixeliiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__cudaHistogramP8PPMPixeliiPf, .Lfunc_end1-_Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.cfi_endproc
# -- End function
.globl _Z9HistogramP8PPMImagePf # -- Begin function _Z9HistogramP8PPMImagePf
.p2align 4, 0x90
.type _Z9HistogramP8PPMImagePf,@function
_Z9HistogramP8PPMImagePf: # @_Z9HistogramP8PPMImagePf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $0, 20(%rsp)
movl (%rdi), %eax
imull 4(%rdi), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.lr.ph
cvtsi2ss %eax, %xmm0
movq 8(%r14), %rax
addq $2, %rax
movl $1, %ecx
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
shrb $6, -2(%rax)
shrb $6, (%rax)
shrb $6, -1(%rax)
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
addq $3, %rax
incl %ecx
ucomiss %xmm1, %xmm0
ja .LBB2_2
.LBB2_3: # %._crit_edge
leaq 8(%rsp), %r15
movq %r15, %rdi
callq hipEventCreate
movq %rsp, %r12
movq %r12, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq (%r14), %rax
movslq 4(%r14), %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %r13
movq %r13, %rdi
callq hipEventElapsedTime
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq 8(%r14), %rsi
movslq (%r14), %rax
movslq 4(%r14), %rcx
imulq %rax, %rcx
leaq (%rcx,%rcx,2), %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movl (%r14), %eax
movl 4(%r14), %ecx
leal 31(%rcx), %edx
testl %ecx, %ecx
cmovnsl %ecx, %edx
sarl $5, %edx
andl $31, %ecx
cmpl $1, %ecx
sbbl $-1, %edx
leal 31(%rax), %r13d
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $5, %r13d
andl $31, %eax
cmpl $1, %eax
sbbl $-1, %r13d
shlq $32, %r13
orq %rdx, %r13
movq %r15, %rdi
callq hipEventCreate
movq %r12, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 40(%rsp), %rax
movl (%r14), %ecx
movl 4(%r14), %edx
movq 24(%rsp), %rsi
movq %rax, 104(%rsp)
movl %ecx, 36(%rsp)
movl %edx, 32(%rsp)
movq %rsi, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13cudaHistogramP8PPMPixeliiPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %r14
movq %r14, %rdi
callq hipEventElapsedTime
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9HistogramP8PPMImagePf, .Lfunc_end2-_Z9HistogramP8PPMImagePf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
cmpl $2, %edi
je .LBB3_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_2:
movq 8(%rbx), %rbx
movl $.L.str.5, %esi
movq %rbx, %rdi
callq fopen
testq %rax, %rax
je .LBB3_3
# %bb.5:
movq %rax, %r15
movq %rsp, %rdi
movl $16, %esi
movq %rax, %rdx
callq fgets
testq %rax, %rax
je .LBB3_31
# %bb.6:
cmpb $80, (%rsp)
jne .LBB3_8
# %bb.7:
cmpb $54, 1(%rsp)
jne .LBB3_8
# %bb.10:
movl $16, %edi
callq malloc
testq %rax, %rax
je .LBB3_11
# %bb.12:
movq %rax, %r14
.p2align 4, 0x90
.LBB3_13: # =>This Loop Header: Depth=1
# Child Loop BB3_14 Depth 2
movq %r15, %rdi
callq getc
cmpl $35, %eax
jne .LBB3_15
.LBB3_14: # %.preheader44.i
# Parent Loop BB3_13 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
callq getc
cmpl $10, %eax
jne .LBB3_14
jmp .LBB3_13
.LBB3_15: # %._crit_edge.i
movl %eax, %edi
movq %r15, %rsi
callq ungetc
movq %r14, %rcx
addq $4, %rcx
movl $.L.str.9, %esi
movq %r15, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $2, %eax
jne .LBB3_16
# %bb.17:
leaq 32(%rsp), %rdx
movl $.L.str.11, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $1, %eax
jne .LBB3_18
# %bb.19:
cmpl $255, 32(%rsp)
jne .LBB3_20
.p2align 4, 0x90
.LBB3_21: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq fgetc
cmpl $10, %eax
jne .LBB3_21
# %bb.22:
movslq (%r14), %rax
movslq 4(%r14), %r12
leaq (%rax,%rax,2), %r13
movq %r13, %rdi
imulq %r12, %rdi
callq malloc
movq %rax, 8(%r14)
movq %rax, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %r15, %rcx
callq fread
movslq 4(%r14), %rcx
cmpq %rcx, %rax
jne .LBB3_23
# %bb.24: # %_ZL7readPPMPKc.exit
movq %r15, %rdi
callq fclose
movl (%r14), %ebp
imull 4(%r14), %ebp
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movups %xmm0, 144(%rax)
movups %xmm0, 160(%rax)
movups %xmm0, 176(%rax)
movups %xmm0, 192(%rax)
movups %xmm0, 208(%rax)
movups %xmm0, 224(%rax)
movups %xmm0, 240(%rax)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB3_26
# %bb.25:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB3_26: # %_Z7rtclockv.exit
movq (%rsp), %r15
movq 8(%rsp), %r12
movq %r14, %rdi
movq %rbx, %rsi
callq _Z9HistogramP8PPMImagePf
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB3_28
# %bb.27:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB3_28: # %_Z7rtclockv.exit21
xorps %xmm0, %xmm0
cvtsi2ss %ebp, %xmm0
movss %xmm0, 24(%rsp) # 4-byte Spill
movq (%rsp), %r14
movq 8(%rsp), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_29: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 24(%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %rbp
cmpq $64, %rbp
jne .LBB3_29
# %bb.30:
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsi2sd %r14, %xmm2
addsd %xmm0, %xmm2
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
mulsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
addsd %xmm0, %xmm1
subsd %xmm1, %xmm2
movsd %xmm2, 24(%rsp) # 8-byte Spill
movl $10, %edi
callq putchar@PLT
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq fprintf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 96
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
jmp .LBB3_4
.LBB3_31:
movq %rbx, %rdi
callq perror
movl $1, %edi
callq exit
.LBB3_8:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $36, %esi
jmp .LBB3_9
.LBB3_11:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $26, %esi
.LBB3_9:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB3_16:
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
jmp .LBB3_4
.LBB3_18:
movq stderr(%rip), %rdi
movl $.L.str.12, %esi
jmp .LBB3_4
.LBB3_20:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
jmp .LBB3_4
.LBB3_23:
movq stderr(%rip), %rdi
movl $.L.str.14, %esi
.LBB3_4:
movq %rbx, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13cudaHistogramP8PPMPixeliiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type _Z13cudaHistogramP8PPMPixeliiPf,@object # @_Z13cudaHistogramP8PPMPixeliiPf
.section .rodata,"a",@progbits
.globl _Z13cudaHistogramP8PPMPixeliiPf
.p2align 3, 0x0
_Z13cudaHistogramP8PPMPixeliiPf:
.quad _Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.size _Z13cudaHistogramP8PPMPixeliiPf, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%0.3f "
.size .L.str.2, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n%0.6lfs\n"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "rb"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Unable to open file '%s'\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Invalid image format (must be 'P6')\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Unable to allocate memory\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d %d"
.size .L.str.9, 6
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Invalid image size (error loading '%s')\n"
.size .L.str.10, 41
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "%d"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Invalid rgb component (error loading '%s')\n"
.size .L.str.12, 44
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "'%s' does not have 8-bits components\n"
.size .L.str.13, 38
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Error loading image '%s'\n"
.size .L.str.14, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13cudaHistogramP8PPMPixeliiPf"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Too many or no one arguments supplied."
.size .Lstr, 39
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__cudaHistogramP8PPMPixeliiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13cudaHistogramP8PPMPixeliiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <sys/time.h>
__global__ void saxpyDevice(int n, float a, float *x, float *y){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
}
void saxpy(int n, float a, float *x, float *y){
float *d_x, *d_y;
// allocate GPU memory, and upload data
cudaMalloc(&d_x, n*sizeof(float));
cudaMalloc(&d_y, n*sizeof(float));
cudaMemcpy(d_x, x, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, n*sizeof(float), cudaMemcpyHostToDevice);
// send instructions to GPU
saxpyDevice<<<(n+255)/256, 256>>>(n, 2.0f, d_x, d_y);
// download data, and free GPU memory
cudaMemcpy(y, d_y, n*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_x);
cudaFree(d_y);
}
int main(void){
int N = 1<<20;
float *x, *y;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
struct timeval t0, t1;
gettimeofday(&t0, NULL);
for (int i=0; i<100; i++)
saxpy(N, 2.0f, x, y);
gettimeofday(&t1, NULL);
std::cout<<"CUDA = "<<(t1.tv_sec - t0.tv_sec)*1000 + (t1.tv_usec-t0.tv_usec)/1000<<"ms"<<std::endl;
return 0;
} | code for sm_80
Function : _Z11saxpyDeviceifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <sys/time.h>
__global__ void saxpyDevice(int n, float a, float *x, float *y){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
}
void saxpy(int n, float a, float *x, float *y){
float *d_x, *d_y;
// allocate GPU memory, and upload data
cudaMalloc(&d_x, n*sizeof(float));
cudaMalloc(&d_y, n*sizeof(float));
cudaMemcpy(d_x, x, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, n*sizeof(float), cudaMemcpyHostToDevice);
// send instructions to GPU
saxpyDevice<<<(n+255)/256, 256>>>(n, 2.0f, d_x, d_y);
// download data, and free GPU memory
cudaMemcpy(y, d_y, n*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_x);
cudaFree(d_y);
}
int main(void){
int N = 1<<20;
float *x, *y;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
struct timeval t0, t1;
gettimeofday(&t0, NULL);
for (int i=0; i<100; i++)
saxpy(N, 2.0f, x, y);
gettimeofday(&t1, NULL);
std::cout<<"CUDA = "<<(t1.tv_sec - t0.tv_sec)*1000 + (t1.tv_usec-t0.tv_usec)/1000<<"ms"<<std::endl;
return 0;
} | .file "tmpxft_001abbec_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
.type _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_, @function
_Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11saxpyDeviceifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_, .-_Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
.globl _Z11saxpyDeviceifPfS_
.type _Z11saxpyDeviceifPfS_, @function
_Z11saxpyDeviceifPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z11saxpyDeviceifPfS_, .-_Z11saxpyDeviceifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movq %rsi, %r13
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
leal 510(%rbp), %eax
movl %ebp, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC0(%rip), %xmm0
movl %ebp, %edi
call _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA = "
.LC2:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movl $100, %ebx
.L18:
movq %rbp, %rdx
movq %r12, %rsi
movss .LC0(%rip), %xmm0
movl $1048576, %edi
call _Z5saxpyifPfS_
subl $1, %ebx
jne .L18
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 16(%rsp), %rcx
subq (%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 24(%rsp), %rsi
subq 8(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
leaq (%rcx,%rdx), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11saxpyDeviceifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11saxpyDeviceifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <sys/time.h>
__global__ void saxpyDevice(int n, float a, float *x, float *y){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
}
void saxpy(int n, float a, float *x, float *y){
float *d_x, *d_y;
// allocate GPU memory, and upload data
cudaMalloc(&d_x, n*sizeof(float));
cudaMalloc(&d_y, n*sizeof(float));
cudaMemcpy(d_x, x, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, n*sizeof(float), cudaMemcpyHostToDevice);
// send instructions to GPU
saxpyDevice<<<(n+255)/256, 256>>>(n, 2.0f, d_x, d_y);
// download data, and free GPU memory
cudaMemcpy(y, d_y, n*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_x);
cudaFree(d_y);
}
int main(void){
int N = 1<<20;
float *x, *y;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
struct timeval t0, t1;
gettimeofday(&t0, NULL);
for (int i=0; i<100; i++)
saxpy(N, 2.0f, x, y);
gettimeofday(&t1, NULL);
std::cout<<"CUDA = "<<(t1.tv_sec - t0.tv_sec)*1000 + (t1.tv_usec-t0.tv_usec)/1000<<"ms"<<std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
__global__ void saxpyDevice(int n, float a, float *x, float *y){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
}
void saxpy(int n, float a, float *x, float *y){
float *d_x, *d_y;
// allocate GPU memory, and upload data
hipMalloc(&d_x, n*sizeof(float));
hipMalloc(&d_y, n*sizeof(float));
hipMemcpy(d_x, x, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, n*sizeof(float), hipMemcpyHostToDevice);
// send instructions to GPU
saxpyDevice<<<(n+255)/256, 256>>>(n, 2.0f, d_x, d_y);
// download data, and free GPU memory
hipMemcpy(y, d_y, n*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_x);
hipFree(d_y);
}
int main(void){
int N = 1<<20;
float *x, *y;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
struct timeval t0, t1;
gettimeofday(&t0, NULL);
for (int i=0; i<100; i++)
saxpy(N, 2.0f, x, y);
gettimeofday(&t1, NULL);
std::cout<<"CUDA = "<<(t1.tv_sec - t0.tv_sec)*1000 + (t1.tv_usec-t0.tv_usec)/1000<<"ms"<<std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
__global__ void saxpyDevice(int n, float a, float *x, float *y){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
}
void saxpy(int n, float a, float *x, float *y){
float *d_x, *d_y;
// allocate GPU memory, and upload data
hipMalloc(&d_x, n*sizeof(float));
hipMalloc(&d_y, n*sizeof(float));
hipMemcpy(d_x, x, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, n*sizeof(float), hipMemcpyHostToDevice);
// send instructions to GPU
saxpyDevice<<<(n+255)/256, 256>>>(n, 2.0f, d_x, d_y);
// download data, and free GPU memory
hipMemcpy(y, d_y, n*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_x);
hipFree(d_y);
}
int main(void){
int N = 1<<20;
float *x, *y;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
struct timeval t0, t1;
gettimeofday(&t0, NULL);
for (int i=0; i<100; i++)
saxpy(N, 2.0f, x, y);
gettimeofday(&t1, NULL);
std::cout<<"CUDA = "<<(t1.tv_sec - t0.tv_sec)*1000 + (t1.tv_usec-t0.tv_usec)/1000<<"ms"<<std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11saxpyDeviceifPfS_
.globl _Z11saxpyDeviceifPfS_
.p2align 8
.type _Z11saxpyDeviceifPfS_,@function
_Z11saxpyDeviceifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11saxpyDeviceifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11saxpyDeviceifPfS_, .Lfunc_end0-_Z11saxpyDeviceifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11saxpyDeviceifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11saxpyDeviceifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
__global__ void saxpyDevice(int n, float a, float *x, float *y){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = a*x[i] + y[i];
}
void saxpy(int n, float a, float *x, float *y){
float *d_x, *d_y;
// allocate GPU memory, and upload data
hipMalloc(&d_x, n*sizeof(float));
hipMalloc(&d_y, n*sizeof(float));
hipMemcpy(d_x, x, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, n*sizeof(float), hipMemcpyHostToDevice);
// send instructions to GPU
saxpyDevice<<<(n+255)/256, 256>>>(n, 2.0f, d_x, d_y);
// download data, and free GPU memory
hipMemcpy(y, d_y, n*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_x);
hipFree(d_y);
}
int main(void){
int N = 1<<20;
float *x, *y;
x = (float*)malloc(N*sizeof(float));
y = (float*)malloc(N*sizeof(float));
struct timeval t0, t1;
gettimeofday(&t0, NULL);
for (int i=0; i<100; i++)
saxpy(N, 2.0f, x, y);
gettimeofday(&t1, NULL);
std::cout<<"CUDA = "<<(t1.tv_sec - t0.tv_sec)*1000 + (t1.tv_usec-t0.tv_usec)/1000<<"ms"<<std::endl;
return 0;
} | .text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__saxpyDeviceifPfS_ # -- Begin function _Z26__device_stub__saxpyDeviceifPfS_
.p2align 4, 0x90
.type _Z26__device_stub__saxpyDeviceifPfS_,@function
_Z26__device_stub__saxpyDeviceifPfS_: # @_Z26__device_stub__saxpyDeviceifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11saxpyDeviceifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__saxpyDeviceifPfS_, .Lfunc_end0-_Z26__device_stub__saxpyDeviceifPfS_
.cfi_endproc
# -- End function
.globl _Z5saxpyifPfS_ # -- Begin function _Z5saxpyifPfS_
.p2align 4, 0x90
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_: # @_Z5saxpyifPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r12
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 255(%r15), %eax
addl $510, %r15d # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $8, %r15d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $256, %rdx # imm = 0x100
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl %ebp, 28(%rsp)
movl $1073741824, 24(%rsp) # imm = 0x40000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11saxpyDeviceifPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z5saxpyifPfS_, .Lfunc_end1-_Z5saxpyifPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $100, %ebp
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1048576, %edi # imm = 0x100000
movq %rbx, %rsi
movq %r14, %rdx
callq _Z5saxpyifPfS_
decl %ebp
jne .LBB2_1
# %bb.2:
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rcx
movq 8(%rsp), %rax
subq 16(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 24(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB2_6
.LBB2_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11saxpyDeviceifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11saxpyDeviceifPfS_,@object # @_Z11saxpyDeviceifPfS_
.section .rodata,"a",@progbits
.globl _Z11saxpyDeviceifPfS_
.p2align 3, 0x0
_Z11saxpyDeviceifPfS_:
.quad _Z26__device_stub__saxpyDeviceifPfS_
.size _Z11saxpyDeviceifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA = "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ms"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11saxpyDeviceifPfS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__saxpyDeviceifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11saxpyDeviceifPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11saxpyDeviceifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11saxpyDeviceifPfS_
.globl _Z11saxpyDeviceifPfS_
.p2align 8
.type _Z11saxpyDeviceifPfS_,@function
_Z11saxpyDeviceifPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11saxpyDeviceifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11saxpyDeviceifPfS_, .Lfunc_end0-_Z11saxpyDeviceifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11saxpyDeviceifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11saxpyDeviceifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001abbec_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
.type _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_, @function
_Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11saxpyDeviceifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_, .-_Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
.globl _Z11saxpyDeviceifPfS_
.type _Z11saxpyDeviceifPfS_, @function
_Z11saxpyDeviceifPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z11saxpyDeviceifPfS_, .-_Z11saxpyDeviceifPfS_
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movq %rsi, %r13
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
leal 510(%rbp), %eax
movl %ebp, %edx
addl $255, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movss .LC0(%rip), %xmm0
movl %ebp, %edi
call _Z35__device_stub__Z11saxpyDeviceifPfS_ifPfS_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA = "
.LC2:
.string "ms"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movl $100, %ebx
.L18:
movq %rbp, %rdx
movq %r12, %rsi
movss .LC0(%rip), %xmm0
movl $1048576, %edi
call _Z5saxpyifPfS_
subl $1, %ebx
jne .L18
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 16(%rsp), %rcx
subq (%rsp), %rcx
imulq $1000, %rcx, %rcx
movq 24(%rsp), %rsi
subq 8(%rsp), %rsi
movabsq $2361183241434822607, %rdx
movq %rsi, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rsi
subq %rsi, %rdx
leaq (%rcx,%rdx), %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z11saxpyDeviceifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11saxpyDeviceifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__saxpyDeviceifPfS_ # -- Begin function _Z26__device_stub__saxpyDeviceifPfS_
.p2align 4, 0x90
.type _Z26__device_stub__saxpyDeviceifPfS_,@function
_Z26__device_stub__saxpyDeviceifPfS_: # @_Z26__device_stub__saxpyDeviceifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11saxpyDeviceifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__saxpyDeviceifPfS_, .Lfunc_end0-_Z26__device_stub__saxpyDeviceifPfS_
.cfi_endproc
# -- End function
.globl _Z5saxpyifPfS_ # -- Begin function _Z5saxpyifPfS_
.p2align 4, 0x90
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_: # @_Z5saxpyifPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r12
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,4), %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 255(%r15), %eax
addl $510, %r15d # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %r15d
sarl $8, %r15d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r15
orq $256, %rdx # imm = 0x100
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl %ebp, 28(%rsp)
movl $1073741824, 24(%rsp) # imm = 0x40000000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11saxpyDeviceifPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z5saxpyifPfS_, .Lfunc_end1-_Z5saxpyifPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $100, %ebp
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1048576, %edi # imm = 0x100000
movq %rbx, %rsi
movq %r14, %rdx
callq _Z5saxpyifPfS_
decl %ebp
jne .LBB2_1
# %bb.2:
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rcx
movq 8(%rsp), %rax
subq 16(%rsp), %rcx
imulq $1000, %rcx, %rcx # imm = 0x3E8
subq 24(%rsp), %rax
movabsq $2361183241434822607, %rdx # imm = 0x20C49BA5E353F7CF
imulq %rdx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
addq %rcx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_5
# %bb.4:
movzbl 67(%r14), %eax
jmp .LBB2_6
.LBB2_5:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_7:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11saxpyDeviceifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11saxpyDeviceifPfS_,@object # @_Z11saxpyDeviceifPfS_
.section .rodata,"a",@progbits
.globl _Z11saxpyDeviceifPfS_
.p2align 3, 0x0
_Z11saxpyDeviceifPfS_:
.quad _Z26__device_stub__saxpyDeviceifPfS_
.size _Z11saxpyDeviceifPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA = "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ms"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11saxpyDeviceifPfS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__saxpyDeviceifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11saxpyDeviceifPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 50
#define NewN 100
#define LifeN 500
#define numofthreads 512
int numofeles=0,capacity;
struct chromosome
{
long long weight=0, value=0;
bool chromo[100003];
};
chromosome chromoele[N],*cudaChromo,*cudaNewpopulation,newpopulation[NewN],res,x[2];
int weight[100001],value[100001],*devValue,*devWeight,*devnumeles;
__global__ void evaluate(chromosome *cudaChromo,int *devValue,int *devWeight, int numele)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
for (int i = 0; i < numele; i++){
if (cudaChromo[idx].chromo[i])
cudaChromo[idx].value += devValue[i];
cudaChromo[idx].weight += (cudaChromo[idx].chromo[i] ? 1 : 0)*devWeight[i];
}
} | code for sm_80
Function : _Z8evaluateP10chromosomePiS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0050*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x186b8 ; /* 0x000186b8ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0080*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD R12, R3, c[0x0][0x0], R12 ; /* 0x00000000030c7a24 */
/* 0x001fc800078e020c */
/*00e0*/ IMAD.WIDE R2, R12, R5, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x000fe200078e0205 */
/*00f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R12 ; /* 0x0000001fff0d7819 */
/* 0x000fc6000001140c */
/*0100*/ @!P1 BRA 0x6c0 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.WIDE.U32 R4, R12, R5, c[0x0][0x160] ; /* 0x000058000c047625 */
/* 0x000fe200078e0005 */
/*0120*/ IADD3 R11, -R0, c[0x0][0x178], RZ ; /* 0x00005e00000b7a10 */
/* 0x000fc60007ffe1ff */
/*0130*/ IMAD R7, R13, 0x186b8, RZ ; /* 0x000186b80d077824 */
/* 0x000fe200078e02ff */
/*0140*/ IADD3 R4, P1, R4, 0x13, RZ ; /* 0x0000001304047810 */
/* 0x000fe20007f3e0ff */
/*0150*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff117624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.X R5, R5, 0x1, R7, P1 ; /* 0x0000000105057824 */
/* 0x000fe400008e0607 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff127624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fc400078e00ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe400078e00ff */
/*01b0*/ LDG.E.U8 R8, [R4.64+-0x3] ; /* 0xfffffd0404087981 */
/* 0x000ea4000c1e1100 */
/*01c0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f25270 */
/*01d0*/ @P1 LDG.E R15, [R6.64] ; /* 0x00000004060f1981 */
/* 0x001ea8000c1e1900 */
/*01e0*/ @P1 LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402081981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ PRMT R16, RZ, 0x7610, R16 ; /* 0x00007610ff107816 */
/* 0x000fe40000000010 */
/*0200*/ @P1 IADD3 R8, P2, R15, R8, RZ ; /* 0x000000080f081210 */
/* 0x004fc80007f5e0ff */
/*0210*/ @P1 LEA.HI.X.SX32 R9, R15, R9, 0x1, P2 ; /* 0x000000090f091211 */
/* 0x000fe400010f0eff */
/*0220*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ @P1 STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802001986 */
/* 0x0001e8000c101b04 */
/*0240*/ @P1 LDG.E.U8 R16, [R4.64+-0x3] ; /* 0xfffffd0404101981 */
/* 0x000ee2000c1e1100 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R17 ; /* 0x000000ffff087224 */
/* 0x001fc400078e0011 */
/*0260*/ IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0012 */
/*0270*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000f22000c1e1900 */
/*0280*/ LOP3.LUT P1, RZ, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10ff7812 */
/* 0x008fe4000782c0ff */
/*0290*/ SHF.R.S32.HI R16, RZ, 0x1f, R17 ; /* 0x0000001fff107819 */
/* 0x010fe40000011411 */
/*02a0*/ SEL R17, R17, RZ, P1 ; /* 0x000000ff11117207 */
/* 0x000fe40000800000 */
/*02b0*/ SEL R19, R16, RZ, P1 ; /* 0x000000ff10137207 */
/* 0x000fe40000800000 */
/*02c0*/ IADD3 R14, P1, R14, R17, RZ ; /* 0x000000110e0e7210 */
/* 0x004fca0007f3e0ff */
/*02d0*/ IMAD.X R15, R15, 0x1, R19, P1 ; /* 0x000000010f0f7824 */
/* 0x000fca00008e0613 */
/*02e0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0001e8000c101b04 */
/*02f0*/ LDG.E.U8 R16, [R4.64+-0x2] ; /* 0xfffffe0404107981 */
/* 0x000ea4000c1e1100 */
/*0300*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fda0003f25270 */
/*0310*/ @P1 LDG.E R19, [R6.64+0x4] ; /* 0x0000040406131981 */
/* 0x000ea8000c1e1900 */
/*0320*/ @P1 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402101981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ PRMT R18, RZ, 0x7610, R18 ; /* 0x00007610ff127816 */
/* 0x000fe40000000012 */
/*0340*/ @P1 IADD3 R16, P2, R19, R16, RZ ; /* 0x0000001013101210 */
/* 0x004fc80007f5e0ff */
/*0350*/ @P1 LEA.HI.X.SX32 R17, R19, R17, 0x1, P2 ; /* 0x0000001113111211 */
/* 0x000fca00010f0eff */
/*0360*/ @P1 STG.E.64 [R2.64+0x8], R16 ; /* 0x0000081002001986 */
/* 0x0003e8000c101b04 */
/*0370*/ @P1 LDG.E.U8 R18, [R4.64+-0x2] ; /* 0xfffffe0404121981 */
/* 0x000ea8000c1e1100 */
/*0380*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x000ee2000c1e1900 */
/*0390*/ LOP3.LUT P1, RZ, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12ff7812 */
/* 0x004fe4000782c0ff */
/*03a0*/ SHF.R.S32.HI R18, RZ, 0x1f, R19 ; /* 0x0000001fff127819 */
/* 0x008fc40000011413 */
/*03b0*/ SEL R19, R19, RZ, P1 ; /* 0x000000ff13137207 */
/* 0x000fe40000800000 */
/*03c0*/ SEL R21, R18, RZ, P1 ; /* 0x000000ff12157207 */
/* 0x000fe40000800000 */
/*03d0*/ IADD3 R14, P1, R19, R14, RZ ; /* 0x0000000e130e7210 */
/* 0x001fca0007f3e0ff */
/*03e0*/ IMAD.X R15, R21, 0x1, R15, P1 ; /* 0x00000001150f7824 */
/* 0x000fca00008e060f */
/*03f0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0001e8000c101b04 */
/*0400*/ LDG.E.U8 R18, [R4.64+-0x1] ; /* 0xffffff0404127981 */
/* 0x000ea4000c1e1100 */
/*0410*/ ISETP.NE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x004fda0003f25270 */
/*0420*/ @P1 LDG.E R19, [R6.64+0x8] ; /* 0x0000080406131981 */
/* 0x000ea8000c1e1900 */
/*0430*/ @P1 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402101981 */
/* 0x002ea2000c1e1b00 */
/*0440*/ PRMT R18, RZ, 0x7610, R18 ; /* 0x00007610ff127816 */
/* 0x000fe40000000012 */
/*0450*/ @P1 IADD3 R16, P2, R19, R16, RZ ; /* 0x0000001013101210 */
/* 0x004fc80007f5e0ff */
/*0460*/ @P1 LEA.HI.X.SX32 R17, R19, R17, 0x1, P2 ; /* 0x0000001113111211 */
/* 0x000fca00010f0eff */
/*0470*/ @P1 STG.E.64 [R2.64+0x8], R16 ; /* 0x0000081002001986 */
/* 0x0003e8000c101b04 */
/*0480*/ @P1 LDG.E.U8 R18, [R4.64+-0x1] ; /* 0xffffff0404121981 */
/* 0x000ea8000c1e1100 */
/*0490*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080408137981 */
/* 0x000ee2000c1e1900 */
/*04a0*/ LOP3.LUT P1, RZ, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12ff7812 */
/* 0x004fe4000782c0ff */
/*04b0*/ SHF.R.S32.HI R18, RZ, 0x1f, R19 ; /* 0x0000001fff127819 */
/* 0x008fc40000011413 */
/*04c0*/ SEL R19, R19, RZ, P1 ; /* 0x000000ff13137207 */
/* 0x000fe40000800000 */
/*04d0*/ SEL R21, R18, RZ, P1 ; /* 0x000000ff12157207 */
/* 0x000fe40000800000 */
/*04e0*/ IADD3 R14, P1, R19, R14, RZ ; /* 0x0000000e130e7210 */
/* 0x001fca0007f3e0ff */
/*04f0*/ IMAD.X R15, R21, 0x1, R15, P1 ; /* 0x00000001150f7824 */
/* 0x000fca00008e060f */
/*0500*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe8000c101b04 */
/*0510*/ LDG.E.U8 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1100 */
/*0520*/ ISETP.NE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x004fda0003f25270 */
/*0530*/ @P1 LDG.E R19, [R6.64+0xc] ; /* 0x00000c0406131981 */
/* 0x000ea8000c1e1900 */
/*0540*/ @P1 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402101981 */
/* 0x002ea2000c1e1b00 */
/*0550*/ PRMT R18, RZ, 0x7610, R18 ; /* 0x00007610ff127816 */
/* 0x000fe40000000012 */
/*0560*/ @P1 IADD3 R16, P2, R19, R16, RZ ; /* 0x0000001013101210 */
/* 0x004fc80007f5e0ff */
/*0570*/ @P1 LEA.HI.X.SX32 R17, R19, R17, 0x1, P2 ; /* 0x0000001113111211 */
/* 0x000fca00010f0eff */
/*0580*/ @P1 STG.E.64 [R2.64+0x8], R16 ; /* 0x0000081002001986 */
/* 0x0001e8000c101b04 */
/*0590*/ @P1 LDG.E.U8 R18, [R4.64] ; /* 0x0000000404121981 */
/* 0x0002a8000c1e1100 */
/*05a0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3 R6, P3, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007f7e0ff */
/*05d0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fe40007f5e0ff */
/*05e0*/ IADD3 R17, P4, R8, 0x10, RZ ; /* 0x0000001008117810 */
/* 0x001fe20007f9e0ff */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0607 */
/*0600*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0620*/ LOP3.LUT P1, RZ, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12ff7812 */
/* 0x004fe4000782c0ff */
/*0630*/ SHF.R.S32.HI R18, RZ, 0x1f, R19 ; /* 0x0000001fff127819 */
/* 0x008fe40000011413 */
/*0640*/ SEL R19, R19, RZ, P1 ; /* 0x000000ff13137207 */
/* 0x000fc40000800000 */
/*0650*/ SEL R21, R18, RZ, P1 ; /* 0x000000ff12157207 */
/* 0x000fe40000800000 */
/*0660*/ IADD3 R14, P1, R19, R14, RZ ; /* 0x0000000e130e7210 */
/* 0x000fca0007f3e0ff */
/*0670*/ IMAD.X R15, R21, 0x1, R15, P1 ; /* 0x00000001150f7824 */
/* 0x000fe200008e060f */
/*0680*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0690*/ IMAD.X R18, RZ, RZ, R9, P4 ; /* 0x000000ffff127224 */
/* 0x000fc600020e0609 */
/*06a0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0001f2000c101b04 */
/*06b0*/ @P1 BRA 0x1b0 ; /* 0xfffffaf000001947 */
/* 0x000fea000383ffff */
/*06c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x186b8 ; /* 0x000186b8ff057424 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD R11, R13, 0x186b8, RZ ; /* 0x000186b80d0b7824 */
/* 0x000fc400078e02ff */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0005 */
/*0710*/ IMAD.WIDE R6, R10, R9, c[0x0][0x170] ; /* 0x00005c000a067625 */
/* 0x000fe200078e0209 */
/*0720*/ IADD3 R4, P0, P1, R12, 0x10, R10 ; /* 0x000000100c047810 */
/* 0x000fc6000791e00a */
/*0730*/ IMAD.WIDE R8, R10, R9, c[0x0][0x168] ; /* 0x00005a000a087625 */
/* 0x000fe200078e0209 */
/*0740*/ SHF.R.S32.HI R10, RZ, 0x1f, R10 ; /* 0x0000001fff0a7819 */
/* 0x000fc6000001140a */
/*0750*/ IMAD.IADD R11, R13, 0x1, R11 ; /* 0x000000010d0b7824 */
/* 0x000fca00078e020b */
/*0760*/ IADD3.X R5, R11, RZ, R10, P0, P1 ; /* 0x000000ff0b057210 */
/* 0x000fca00007e240a */
/*0770*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x001ea4000c1e1100 */
/*0780*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0790*/ @P0 LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a0981 */
/* 0x000ea8000c1e1b00 */
/*07a0*/ @P0 LDG.E R13, [R8.64] ; /* 0x00000004080d0981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ PRMT R14, RZ, 0x7610, R14 ; /* 0x00007610ff0e7816 */
/* 0x001fe4000000000e */
/*07c0*/ @P0 IADD3 R12, P1, R13, R10, RZ ; /* 0x0000000a0d0c0210 */
/* 0x004fc80007f3e0ff */
/*07d0*/ @P0 LEA.HI.X.SX32 R13, R13, R11, 0x1, P1 ; /* 0x0000000b0d0d0211 */
/* 0x000fe400008f0eff */
/*07e0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1b00 */
/*07f0*/ @P0 STG.E.64 [R2.64+0x8], R12 ; /* 0x0000080c02000986 */
/* 0x0001e8000c101b04 */
/*0800*/ @P0 LDG.E.U8 R14, [R4.64] ; /* 0x00000004040e0981 */
/* 0x0002e8000c1e1100 */
/*0810*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000962000c1e1900 */
/*0820*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*0830*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f5e0ff */
/*0840*/ IADD3 R4, P3, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007f7e0ff */
/*0850*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc60007f3e0ff */
/*0860*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*0870*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0609 */
/*0880*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0890*/ LOP3.LUT P0, RZ, R14, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0eff7812 */
/* 0x008fe4000780c0ff */
/*08a0*/ SHF.R.S32.HI R14, RZ, 0x1f, R15 ; /* 0x0000001fff0e7819 */
/* 0x020fe4000001140f */
/*08b0*/ SEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7207 */
/* 0x000fe40000000000 */
/*08c0*/ SEL R17, R14, RZ, P0 ; /* 0x000000ff0e117207 */
/* 0x000fc40000000000 */
/*08d0*/ IADD3 R10, P0, R10, R15, RZ ; /* 0x0000000f0a0a7210 */
/* 0x004fca0007f1e0ff */
/*08e0*/ IMAD.X R11, R11, 0x1, R17, P0 ; /* 0x000000010b0b7824 */
/* 0x000fe200000e0611 */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05270 */
/*0900*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0001f2000c101b04 */
/*0910*/ @P0 BRA 0x770 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 50
#define NewN 100
#define LifeN 500
#define numofthreads 512
int numofeles=0,capacity;
struct chromosome
{
long long weight=0, value=0;
bool chromo[100003];
};
chromosome chromoele[N],*cudaChromo,*cudaNewpopulation,newpopulation[NewN],res,x[2];
int weight[100001],value[100001],*devValue,*devWeight,*devnumeles;
__global__ void evaluate(chromosome *cudaChromo,int *devValue,int *devWeight, int numele)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
for (int i = 0; i < numele; i++){
if (cudaChromo[idx].chromo[i])
cudaChromo[idx].value += devValue[i];
cudaChromo[idx].weight += (cudaChromo[idx].chromo[i] ? 1 : 0)*devWeight[i];
}
} | .file "tmpxft_0003b46c_00000000-6_evaluate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i
.type _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i, @function
_Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8evaluateP10chromosomePiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i, .-_Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i
.globl _Z8evaluateP10chromosomePiS1_i
.type _Z8evaluateP10chromosomePiS1_i, @function
_Z8evaluateP10chromosomePiS1_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z8evaluateP10chromosomePiS1_i, .-_Z8evaluateP10chromosomePiS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z8evaluateP10chromosomePiS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8evaluateP10chromosomePiS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_numofeles, @function
_GLOBAL__sub_I_numofeles:
.LFB2174:
.cfi_startproc
endbr64
leaq chromoele(%rip), %rax
leaq 5001200(%rax), %rdx
.L14:
movq $0, (%rax)
movq $0, 8(%rax)
addq $100024, %rax
cmpq %rdx, %rax
jne .L14
leaq newpopulation(%rip), %rax
leaq 10002400(%rax), %rdx
.L15:
movq $0, (%rax)
movq $0, 8(%rax)
addq $100024, %rax
cmpq %rax, %rdx
jne .L15
movq $0, res(%rip)
movq $0, 8+res(%rip)
movq $0, x(%rip)
movq $0, 8+x(%rip)
movq $0, 100024+x(%rip)
movq $0, 100032+x(%rip)
ret
.cfi_endproc
.LFE2174:
.size _GLOBAL__sub_I_numofeles, .-_GLOBAL__sub_I_numofeles
.section .init_array
.align 8
.quad _GLOBAL__sub_I_numofeles
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl devnumeles
.bss
.align 8
.type devnumeles, @object
.size devnumeles, 8
devnumeles:
.zero 8
.globl devWeight
.align 8
.type devWeight, @object
.size devWeight, 8
devWeight:
.zero 8
.globl devValue
.align 8
.type devValue, @object
.size devValue, 8
devValue:
.zero 8
.globl value
.align 32
.type value, @object
.size value, 400004
value:
.zero 400004
.globl weight
.align 32
.type weight, @object
.size weight, 400004
weight:
.zero 400004
.globl x
.align 32
.type x, @object
.size x, 200048
x:
.zero 200048
.globl res
.align 32
.type res, @object
.size res, 100024
res:
.zero 100024
.globl newpopulation
.align 32
.type newpopulation, @object
.size newpopulation, 10002400
newpopulation:
.zero 10002400
.globl cudaNewpopulation
.align 8
.type cudaNewpopulation, @object
.size cudaNewpopulation, 8
cudaNewpopulation:
.zero 8
.globl cudaChromo
.align 8
.type cudaChromo, @object
.size cudaChromo, 8
cudaChromo:
.zero 8
.globl chromoele
.align 32
.type chromoele, @object
.size chromoele, 5001200
chromoele:
.zero 5001200
.globl capacity
.align 4
.type capacity, @object
.size capacity, 4
capacity:
.zero 4
.globl numofeles
.align 4
.type numofeles, @object
.size numofeles, 4
numofeles:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 50
#define NewN 100
#define LifeN 500
#define numofthreads 512
int numofeles=0,capacity;
struct chromosome
{
long long weight=0, value=0;
bool chromo[100003];
};
chromosome chromoele[N],*cudaChromo,*cudaNewpopulation,newpopulation[NewN],res,x[2];
int weight[100001],value[100001],*devValue,*devWeight,*devnumeles;
__global__ void evaluate(chromosome *cudaChromo,int *devValue,int *devWeight, int numele)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
for (int i = 0; i < numele; i++){
if (cudaChromo[idx].chromo[i])
cudaChromo[idx].value += devValue[i];
cudaChromo[idx].weight += (cudaChromo[idx].chromo[i] ? 1 : 0)*devWeight[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 50
#define NewN 100
#define LifeN 500
#define numofthreads 512
int numofeles=0,capacity;
struct chromosome
{
long long weight=0, value=0;
bool chromo[100003];
};
chromosome chromoele[N],*cudaChromo,*cudaNewpopulation,newpopulation[NewN],res,x[2];
int weight[100001],value[100001],*devValue,*devWeight,*devnumeles;
__global__ void evaluate(chromosome *cudaChromo,int *devValue,int *devWeight, int numele)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
for (int i = 0; i < numele; i++){
if (cudaChromo[idx].chromo[i])
cudaChromo[idx].value += devValue[i];
cudaChromo[idx].weight += (cudaChromo[idx].chromo[i] ? 1 : 0)*devWeight[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 50
#define NewN 100
#define LifeN 500
#define numofthreads 512
int numofeles=0,capacity;
struct chromosome
{
long long weight=0, value=0;
bool chromo[100003];
};
chromosome chromoele[N],*cudaChromo,*cudaNewpopulation,newpopulation[NewN],res,x[2];
int weight[100001],value[100001],*devValue,*devWeight,*devnumeles;
__global__ void evaluate(chromosome *cudaChromo,int *devValue,int *devWeight, int numele)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
for (int i = 0; i < numele; i++){
if (cudaChromo[idx].chromo[i])
cudaChromo[idx].value += devValue[i];
cudaChromo[idx].weight += (cudaChromo[idx].chromo[i] ? 1 : 0)*devWeight[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8evaluateP10chromosomePiS1_i
.globl _Z8evaluateP10chromosomePiS1_i
.p2align 8
.type _Z8evaluateP10chromosomePiS1_i,@function
_Z8evaluateP10chromosomePiS1_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x2
s_load_b32 s3, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mad_i64_i32 v[0:1], null, v2, 0x186b8, s[4:5]
global_load_b64 v[2:3], v[0:1], off
v_add_co_u32 v4, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, v0, 16
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x0
v_and_b32_e32 v8, 0xffff, v8
v_add_co_u32 v6, vcc_lo, v6, 1
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v8, s3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v2, vcc_lo, v2, v8
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v9, vcc_lo
s_cbranch_scc1 .LBB0_5
.LBB0_3:
global_load_u8 v8, v[6:7], off
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v8
s_cbranch_execz .LBB0_2
global_load_b64 v[9:10], v[4:5], off
s_load_b32 s4, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_store_b64 v[4:5], v[9:10], off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8evaluateP10chromosomePiS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8evaluateP10chromosomePiS1_i, .Lfunc_end0-_Z8evaluateP10chromosomePiS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8evaluateP10chromosomePiS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8evaluateP10chromosomePiS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 50
#define NewN 100
#define LifeN 500
#define numofthreads 512
int numofeles=0,capacity;
struct chromosome
{
long long weight=0, value=0;
bool chromo[100003];
};
chromosome chromoele[N],*cudaChromo,*cudaNewpopulation,newpopulation[NewN],res,x[2];
int weight[100001],value[100001],*devValue,*devWeight,*devnumeles;
__global__ void evaluate(chromosome *cudaChromo,int *devValue,int *devWeight, int numele)
{
int idx = threadIdx.x+blockDim.x*blockIdx.x;
for (int i = 0; i < numele; i++){
if (cudaChromo[idx].chromo[i])
cudaChromo[idx].value += devValue[i];
cudaChromo[idx].weight += (cudaChromo[idx].chromo[i] ? 1 : 0)*devWeight[i];
}
} | .text
.file "evaluate.hip"
.globl _Z23__device_stub__evaluateP10chromosomePiS1_i # -- Begin function _Z23__device_stub__evaluateP10chromosomePiS1_i
.p2align 4, 0x90
.type _Z23__device_stub__evaluateP10chromosomePiS1_i,@function
_Z23__device_stub__evaluateP10chromosomePiS1_i: # @_Z23__device_stub__evaluateP10chromosomePiS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8evaluateP10chromosomePiS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__evaluateP10chromosomePiS1_i, .Lfunc_end0-_Z23__device_stub__evaluateP10chromosomePiS1_i
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_evaluate.hip
.type _GLOBAL__sub_I_evaluate.hip,@function
_GLOBAL__sub_I_evaluate.hip: # @_GLOBAL__sub_I_evaluate.hip
.cfi_startproc
# %bb.0:
movq $-5001200, %rax # imm = 0xFFB3B010
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movups %xmm0, chromoele+5001200(%rax)
addq $100024, %rax # imm = 0x186B8
jne .LBB1_1
# %bb.2: # %__cxx_global_var_init.exit.preheader
movq $-10002400, %rax # imm = 0xFF676020
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_3: # %__cxx_global_var_init.exit
# =>This Inner Loop Header: Depth=1
movups %xmm0, newpopulation+10002400(%rax)
addq $100024, %rax # imm = 0x186B8
jne .LBB1_3
# %bb.4: # %__cxx_global_var_init.1.exit
xorps %xmm0, %xmm0
movups %xmm0, res(%rip)
movq $-200048, %rax # imm = 0xFFFCF290
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movups %xmm0, x+200048(%rax)
addq $100024, %rax # imm = 0x186B8
jne .LBB1_5
# %bb.6: # %__cxx_global_var_init.3.exit
retq
.Lfunc_end1:
.size _GLOBAL__sub_I_evaluate.hip, .Lfunc_end1-_GLOBAL__sub_I_evaluate.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8evaluateP10chromosomePiS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type numofeles,@object # @numofeles
.bss
.globl numofeles
.p2align 2, 0x0
numofeles:
.long 0 # 0x0
.size numofeles, 4
.type capacity,@object # @capacity
.globl capacity
.p2align 2, 0x0
capacity:
.long 0 # 0x0
.size capacity, 4
.type chromoele,@object # @chromoele
.globl chromoele
.p2align 4, 0x0
chromoele:
.zero 5001200
.size chromoele, 5001200
.type cudaChromo,@object # @cudaChromo
.globl cudaChromo
.p2align 3, 0x0
cudaChromo:
.quad 0
.size cudaChromo, 8
.type cudaNewpopulation,@object # @cudaNewpopulation
.globl cudaNewpopulation
.p2align 3, 0x0
cudaNewpopulation:
.quad 0
.size cudaNewpopulation, 8
.type newpopulation,@object # @newpopulation
.globl newpopulation
.p2align 4, 0x0
newpopulation:
.zero 10002400
.size newpopulation, 10002400
.type res,@object # @res
.globl res
.p2align 3, 0x0
res:
.zero 100024
.size res, 100024
.type x,@object # @x
.globl x
.p2align 4, 0x0
x:
.zero 200048
.size x, 200048
.type weight,@object # @weight
.globl weight
.p2align 4, 0x0
weight:
.zero 400004
.size weight, 400004
.type value,@object # @value
.globl value
.p2align 4, 0x0
value:
.zero 400004
.size value, 400004
.type devValue,@object # @devValue
.globl devValue
.p2align 3, 0x0
devValue:
.quad 0
.size devValue, 8
.type devWeight,@object # @devWeight
.globl devWeight
.p2align 3, 0x0
devWeight:
.quad 0
.size devWeight, 8
.type devnumeles,@object # @devnumeles
.globl devnumeles
.p2align 3, 0x0
devnumeles:
.quad 0
.size devnumeles, 8
.type _Z8evaluateP10chromosomePiS1_i,@object # @_Z8evaluateP10chromosomePiS1_i
.section .rodata,"a",@progbits
.globl _Z8evaluateP10chromosomePiS1_i
.p2align 3, 0x0
_Z8evaluateP10chromosomePiS1_i:
.quad _Z23__device_stub__evaluateP10chromosomePiS1_i
.size _Z8evaluateP10chromosomePiS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8evaluateP10chromosomePiS1_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_evaluate.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__evaluateP10chromosomePiS1_i
.addrsig_sym _GLOBAL__sub_I_evaluate.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8evaluateP10chromosomePiS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8evaluateP10chromosomePiS1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0050*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x186b8 ; /* 0x000186b8ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0080*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD R12, R3, c[0x0][0x0], R12 ; /* 0x00000000030c7a24 */
/* 0x001fc800078e020c */
/*00e0*/ IMAD.WIDE R2, R12, R5, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x000fe200078e0205 */
/*00f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R12 ; /* 0x0000001fff0d7819 */
/* 0x000fc6000001140c */
/*0100*/ @!P1 BRA 0x6c0 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.WIDE.U32 R4, R12, R5, c[0x0][0x160] ; /* 0x000058000c047625 */
/* 0x000fe200078e0005 */
/*0120*/ IADD3 R11, -R0, c[0x0][0x178], RZ ; /* 0x00005e00000b7a10 */
/* 0x000fc60007ffe1ff */
/*0130*/ IMAD R7, R13, 0x186b8, RZ ; /* 0x000186b80d077824 */
/* 0x000fe200078e02ff */
/*0140*/ IADD3 R4, P1, R4, 0x13, RZ ; /* 0x0000001304047810 */
/* 0x000fe20007f3e0ff */
/*0150*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff117624 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.X R5, R5, 0x1, R7, P1 ; /* 0x0000000105057824 */
/* 0x000fe400008e0607 */
/*0180*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff127624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fc400078e00ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe400078e00ff */
/*01b0*/ LDG.E.U8 R8, [R4.64+-0x3] ; /* 0xfffffd0404087981 */
/* 0x000ea4000c1e1100 */
/*01c0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f25270 */
/*01d0*/ @P1 LDG.E R15, [R6.64] ; /* 0x00000004060f1981 */
/* 0x001ea8000c1e1900 */
/*01e0*/ @P1 LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402081981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ PRMT R16, RZ, 0x7610, R16 ; /* 0x00007610ff107816 */
/* 0x000fe40000000010 */
/*0200*/ @P1 IADD3 R8, P2, R15, R8, RZ ; /* 0x000000080f081210 */
/* 0x004fc80007f5e0ff */
/*0210*/ @P1 LEA.HI.X.SX32 R9, R15, R9, 0x1, P2 ; /* 0x000000090f091211 */
/* 0x000fe400010f0eff */
/*0220*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1b00 */
/*0230*/ @P1 STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802001986 */
/* 0x0001e8000c101b04 */
/*0240*/ @P1 LDG.E.U8 R16, [R4.64+-0x3] ; /* 0xfffffd0404101981 */
/* 0x000ee2000c1e1100 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R17 ; /* 0x000000ffff087224 */
/* 0x001fc400078e0011 */
/*0260*/ IMAD.MOV.U32 R9, RZ, RZ, R18 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0012 */
/*0270*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000f22000c1e1900 */
/*0280*/ LOP3.LUT P1, RZ, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10ff7812 */
/* 0x008fe4000782c0ff */
/*0290*/ SHF.R.S32.HI R16, RZ, 0x1f, R17 ; /* 0x0000001fff107819 */
/* 0x010fe40000011411 */
/*02a0*/ SEL R17, R17, RZ, P1 ; /* 0x000000ff11117207 */
/* 0x000fe40000800000 */
/*02b0*/ SEL R19, R16, RZ, P1 ; /* 0x000000ff10137207 */
/* 0x000fe40000800000 */
/*02c0*/ IADD3 R14, P1, R14, R17, RZ ; /* 0x000000110e0e7210 */
/* 0x004fca0007f3e0ff */
/*02d0*/ IMAD.X R15, R15, 0x1, R19, P1 ; /* 0x000000010f0f7824 */
/* 0x000fca00008e0613 */
/*02e0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0001e8000c101b04 */
/*02f0*/ LDG.E.U8 R16, [R4.64+-0x2] ; /* 0xfffffe0404107981 */
/* 0x000ea4000c1e1100 */
/*0300*/ ISETP.NE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x004fda0003f25270 */
/*0310*/ @P1 LDG.E R19, [R6.64+0x4] ; /* 0x0000040406131981 */
/* 0x000ea8000c1e1900 */
/*0320*/ @P1 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402101981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ PRMT R18, RZ, 0x7610, R18 ; /* 0x00007610ff127816 */
/* 0x000fe40000000012 */
/*0340*/ @P1 IADD3 R16, P2, R19, R16, RZ ; /* 0x0000001013101210 */
/* 0x004fc80007f5e0ff */
/*0350*/ @P1 LEA.HI.X.SX32 R17, R19, R17, 0x1, P2 ; /* 0x0000001113111211 */
/* 0x000fca00010f0eff */
/*0360*/ @P1 STG.E.64 [R2.64+0x8], R16 ; /* 0x0000081002001986 */
/* 0x0003e8000c101b04 */
/*0370*/ @P1 LDG.E.U8 R18, [R4.64+-0x2] ; /* 0xfffffe0404121981 */
/* 0x000ea8000c1e1100 */
/*0380*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x000ee2000c1e1900 */
/*0390*/ LOP3.LUT P1, RZ, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12ff7812 */
/* 0x004fe4000782c0ff */
/*03a0*/ SHF.R.S32.HI R18, RZ, 0x1f, R19 ; /* 0x0000001fff127819 */
/* 0x008fc40000011413 */
/*03b0*/ SEL R19, R19, RZ, P1 ; /* 0x000000ff13137207 */
/* 0x000fe40000800000 */
/*03c0*/ SEL R21, R18, RZ, P1 ; /* 0x000000ff12157207 */
/* 0x000fe40000800000 */
/*03d0*/ IADD3 R14, P1, R19, R14, RZ ; /* 0x0000000e130e7210 */
/* 0x001fca0007f3e0ff */
/*03e0*/ IMAD.X R15, R21, 0x1, R15, P1 ; /* 0x00000001150f7824 */
/* 0x000fca00008e060f */
/*03f0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0001e8000c101b04 */
/*0400*/ LDG.E.U8 R18, [R4.64+-0x1] ; /* 0xffffff0404127981 */
/* 0x000ea4000c1e1100 */
/*0410*/ ISETP.NE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x004fda0003f25270 */
/*0420*/ @P1 LDG.E R19, [R6.64+0x8] ; /* 0x0000080406131981 */
/* 0x000ea8000c1e1900 */
/*0430*/ @P1 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402101981 */
/* 0x002ea2000c1e1b00 */
/*0440*/ PRMT R18, RZ, 0x7610, R18 ; /* 0x00007610ff127816 */
/* 0x000fe40000000012 */
/*0450*/ @P1 IADD3 R16, P2, R19, R16, RZ ; /* 0x0000001013101210 */
/* 0x004fc80007f5e0ff */
/*0460*/ @P1 LEA.HI.X.SX32 R17, R19, R17, 0x1, P2 ; /* 0x0000001113111211 */
/* 0x000fca00010f0eff */
/*0470*/ @P1 STG.E.64 [R2.64+0x8], R16 ; /* 0x0000081002001986 */
/* 0x0003e8000c101b04 */
/*0480*/ @P1 LDG.E.U8 R18, [R4.64+-0x1] ; /* 0xffffff0404121981 */
/* 0x000ea8000c1e1100 */
/*0490*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080408137981 */
/* 0x000ee2000c1e1900 */
/*04a0*/ LOP3.LUT P1, RZ, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12ff7812 */
/* 0x004fe4000782c0ff */
/*04b0*/ SHF.R.S32.HI R18, RZ, 0x1f, R19 ; /* 0x0000001fff127819 */
/* 0x008fc40000011413 */
/*04c0*/ SEL R19, R19, RZ, P1 ; /* 0x000000ff13137207 */
/* 0x000fe40000800000 */
/*04d0*/ SEL R21, R18, RZ, P1 ; /* 0x000000ff12157207 */
/* 0x000fe40000800000 */
/*04e0*/ IADD3 R14, P1, R19, R14, RZ ; /* 0x0000000e130e7210 */
/* 0x001fca0007f3e0ff */
/*04f0*/ IMAD.X R15, R21, 0x1, R15, P1 ; /* 0x00000001150f7824 */
/* 0x000fca00008e060f */
/*0500*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe8000c101b04 */
/*0510*/ LDG.E.U8 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1100 */
/*0520*/ ISETP.NE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x004fda0003f25270 */
/*0530*/ @P1 LDG.E R19, [R6.64+0xc] ; /* 0x00000c0406131981 */
/* 0x000ea8000c1e1900 */
/*0540*/ @P1 LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402101981 */
/* 0x002ea2000c1e1b00 */
/*0550*/ PRMT R18, RZ, 0x7610, R18 ; /* 0x00007610ff127816 */
/* 0x000fe40000000012 */
/*0560*/ @P1 IADD3 R16, P2, R19, R16, RZ ; /* 0x0000001013101210 */
/* 0x004fc80007f5e0ff */
/*0570*/ @P1 LEA.HI.X.SX32 R17, R19, R17, 0x1, P2 ; /* 0x0000001113111211 */
/* 0x000fca00010f0eff */
/*0580*/ @P1 STG.E.64 [R2.64+0x8], R16 ; /* 0x0000081002001986 */
/* 0x0001e8000c101b04 */
/*0590*/ @P1 LDG.E.U8 R18, [R4.64] ; /* 0x0000000404121981 */
/* 0x0002a8000c1e1100 */
/*05a0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe40007ffe0ff */
/*05c0*/ IADD3 R6, P3, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc40007f7e0ff */
/*05d0*/ IADD3 R4, P2, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fe40007f5e0ff */
/*05e0*/ IADD3 R17, P4, R8, 0x10, RZ ; /* 0x0000001008117810 */
/* 0x001fe20007f9e0ff */
/*05f0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0607 */
/*0600*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0620*/ LOP3.LUT P1, RZ, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12ff7812 */
/* 0x004fe4000782c0ff */
/*0630*/ SHF.R.S32.HI R18, RZ, 0x1f, R19 ; /* 0x0000001fff127819 */
/* 0x008fe40000011413 */
/*0640*/ SEL R19, R19, RZ, P1 ; /* 0x000000ff13137207 */
/* 0x000fc40000800000 */
/*0650*/ SEL R21, R18, RZ, P1 ; /* 0x000000ff12157207 */
/* 0x000fe40000800000 */
/*0660*/ IADD3 R14, P1, R19, R14, RZ ; /* 0x0000000e130e7210 */
/* 0x000fca0007f3e0ff */
/*0670*/ IMAD.X R15, R21, 0x1, R15, P1 ; /* 0x00000001150f7824 */
/* 0x000fe200008e060f */
/*0680*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0690*/ IMAD.X R18, RZ, RZ, R9, P4 ; /* 0x000000ffff127224 */
/* 0x000fc600020e0609 */
/*06a0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0001f2000c101b04 */
/*06b0*/ @P1 BRA 0x1b0 ; /* 0xfffffaf000001947 */
/* 0x000fea000383ffff */
/*06c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x186b8 ; /* 0x000186b8ff057424 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD R11, R13, 0x186b8, RZ ; /* 0x000186b80d0b7824 */
/* 0x000fc400078e02ff */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0005 */
/*0710*/ IMAD.WIDE R6, R10, R9, c[0x0][0x170] ; /* 0x00005c000a067625 */
/* 0x000fe200078e0209 */
/*0720*/ IADD3 R4, P0, P1, R12, 0x10, R10 ; /* 0x000000100c047810 */
/* 0x000fc6000791e00a */
/*0730*/ IMAD.WIDE R8, R10, R9, c[0x0][0x168] ; /* 0x00005a000a087625 */
/* 0x000fe200078e0209 */
/*0740*/ SHF.R.S32.HI R10, RZ, 0x1f, R10 ; /* 0x0000001fff0a7819 */
/* 0x000fc6000001140a */
/*0750*/ IMAD.IADD R11, R13, 0x1, R11 ; /* 0x000000010d0b7824 */
/* 0x000fca00078e020b */
/*0760*/ IADD3.X R5, R11, RZ, R10, P0, P1 ; /* 0x000000ff0b057210 */
/* 0x000fca00007e240a */
/*0770*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x001ea4000c1e1100 */
/*0780*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x004fda0003f05270 */
/*0790*/ @P0 LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a0981 */
/* 0x000ea8000c1e1b00 */
/*07a0*/ @P0 LDG.E R13, [R8.64] ; /* 0x00000004080d0981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ PRMT R14, RZ, 0x7610, R14 ; /* 0x00007610ff0e7816 */
/* 0x001fe4000000000e */
/*07c0*/ @P0 IADD3 R12, P1, R13, R10, RZ ; /* 0x0000000a0d0c0210 */
/* 0x004fc80007f3e0ff */
/*07d0*/ @P0 LEA.HI.X.SX32 R13, R13, R11, 0x1, P1 ; /* 0x0000000b0d0d0211 */
/* 0x000fe400008f0eff */
/*07e0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea8000c1e1b00 */
/*07f0*/ @P0 STG.E.64 [R2.64+0x8], R12 ; /* 0x0000080c02000986 */
/* 0x0001e8000c101b04 */
/*0800*/ @P0 LDG.E.U8 R14, [R4.64] ; /* 0x00000004040e0981 */
/* 0x0002e8000c1e1100 */
/*0810*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000962000c1e1900 */
/*0820*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*0830*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f5e0ff */
/*0840*/ IADD3 R4, P3, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007f7e0ff */
/*0850*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc60007f3e0ff */
/*0860*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*0870*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0609 */
/*0880*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0890*/ LOP3.LUT P0, RZ, R14, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0eff7812 */
/* 0x008fe4000780c0ff */
/*08a0*/ SHF.R.S32.HI R14, RZ, 0x1f, R15 ; /* 0x0000001fff0e7819 */
/* 0x020fe4000001140f */
/*08b0*/ SEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7207 */
/* 0x000fe40000000000 */
/*08c0*/ SEL R17, R14, RZ, P0 ; /* 0x000000ff0e117207 */
/* 0x000fc40000000000 */
/*08d0*/ IADD3 R10, P0, R10, R15, RZ ; /* 0x0000000f0a0a7210 */
/* 0x004fca0007f1e0ff */
/*08e0*/ IMAD.X R11, R11, 0x1, R17, P0 ; /* 0x000000010b0b7824 */
/* 0x000fe200000e0611 */
/*08f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05270 */
/*0900*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0001f2000c101b04 */
/*0910*/ @P0 BRA 0x770 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8evaluateP10chromosomePiS1_i
.globl _Z8evaluateP10chromosomePiS1_i
.p2align 8
.type _Z8evaluateP10chromosomePiS1_i,@function
_Z8evaluateP10chromosomePiS1_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_clause 0x2
s_load_b32 s3, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
v_mad_i64_i32 v[0:1], null, v2, 0x186b8, s[4:5]
global_load_b64 v[2:3], v[0:1], off
v_add_co_u32 v4, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, v0, 16
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x0
v_and_b32_e32 v8, 0xffff, v8
v_add_co_u32 v6, vcc_lo, v6, 1
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v8, s3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v2, vcc_lo, v2, v8
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v9, vcc_lo
s_cbranch_scc1 .LBB0_5
.LBB0_3:
global_load_u8 v8, v[6:7], off
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 0, v8
s_cbranch_execz .LBB0_2
global_load_b64 v[9:10], v[4:5], off
s_load_b32 s4, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_store_b64 v[4:5], v[9:10], off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8evaluateP10chromosomePiS1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8evaluateP10chromosomePiS1_i, .Lfunc_end0-_Z8evaluateP10chromosomePiS1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8evaluateP10chromosomePiS1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8evaluateP10chromosomePiS1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003b46c_00000000-6_evaluate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i
.type _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i, @function
_Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8evaluateP10chromosomePiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i, .-_Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i
.globl _Z8evaluateP10chromosomePiS1_i
.type _Z8evaluateP10chromosomePiS1_i, @function
_Z8evaluateP10chromosomePiS1_i:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z8evaluateP10chromosomePiS1_iP10chromosomePiS1_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z8evaluateP10chromosomePiS1_i, .-_Z8evaluateP10chromosomePiS1_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z8evaluateP10chromosomePiS1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8evaluateP10chromosomePiS1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_numofeles, @function
_GLOBAL__sub_I_numofeles:
.LFB2174:
.cfi_startproc
endbr64
leaq chromoele(%rip), %rax
leaq 5001200(%rax), %rdx
.L14:
movq $0, (%rax)
movq $0, 8(%rax)
addq $100024, %rax
cmpq %rdx, %rax
jne .L14
leaq newpopulation(%rip), %rax
leaq 10002400(%rax), %rdx
.L15:
movq $0, (%rax)
movq $0, 8(%rax)
addq $100024, %rax
cmpq %rax, %rdx
jne .L15
movq $0, res(%rip)
movq $0, 8+res(%rip)
movq $0, x(%rip)
movq $0, 8+x(%rip)
movq $0, 100024+x(%rip)
movq $0, 100032+x(%rip)
ret
.cfi_endproc
.LFE2174:
.size _GLOBAL__sub_I_numofeles, .-_GLOBAL__sub_I_numofeles
.section .init_array
.align 8
.quad _GLOBAL__sub_I_numofeles
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl devnumeles
.bss
.align 8
.type devnumeles, @object
.size devnumeles, 8
devnumeles:
.zero 8
.globl devWeight
.align 8
.type devWeight, @object
.size devWeight, 8
devWeight:
.zero 8
.globl devValue
.align 8
.type devValue, @object
.size devValue, 8
devValue:
.zero 8
.globl value
.align 32
.type value, @object
.size value, 400004
value:
.zero 400004
.globl weight
.align 32
.type weight, @object
.size weight, 400004
weight:
.zero 400004
.globl x
.align 32
.type x, @object
.size x, 200048
x:
.zero 200048
.globl res
.align 32
.type res, @object
.size res, 100024
res:
.zero 100024
.globl newpopulation
.align 32
.type newpopulation, @object
.size newpopulation, 10002400
newpopulation:
.zero 10002400
.globl cudaNewpopulation
.align 8
.type cudaNewpopulation, @object
.size cudaNewpopulation, 8
cudaNewpopulation:
.zero 8
.globl cudaChromo
.align 8
.type cudaChromo, @object
.size cudaChromo, 8
cudaChromo:
.zero 8
.globl chromoele
.align 32
.type chromoele, @object
.size chromoele, 5001200
chromoele:
.zero 5001200
.globl capacity
.align 4
.type capacity, @object
.size capacity, 4
capacity:
.zero 4
.globl numofeles
.align 4
.type numofeles, @object
.size numofeles, 4
numofeles:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "evaluate.hip"
.globl _Z23__device_stub__evaluateP10chromosomePiS1_i # -- Begin function _Z23__device_stub__evaluateP10chromosomePiS1_i
.p2align 4, 0x90
.type _Z23__device_stub__evaluateP10chromosomePiS1_i,@function
_Z23__device_stub__evaluateP10chromosomePiS1_i: # @_Z23__device_stub__evaluateP10chromosomePiS1_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8evaluateP10chromosomePiS1_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__evaluateP10chromosomePiS1_i, .Lfunc_end0-_Z23__device_stub__evaluateP10chromosomePiS1_i
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_evaluate.hip
.type _GLOBAL__sub_I_evaluate.hip,@function
_GLOBAL__sub_I_evaluate.hip: # @_GLOBAL__sub_I_evaluate.hip
.cfi_startproc
# %bb.0:
movq $-5001200, %rax # imm = 0xFFB3B010
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movups %xmm0, chromoele+5001200(%rax)
addq $100024, %rax # imm = 0x186B8
jne .LBB1_1
# %bb.2: # %__cxx_global_var_init.exit.preheader
movq $-10002400, %rax # imm = 0xFF676020
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_3: # %__cxx_global_var_init.exit
# =>This Inner Loop Header: Depth=1
movups %xmm0, newpopulation+10002400(%rax)
addq $100024, %rax # imm = 0x186B8
jne .LBB1_3
# %bb.4: # %__cxx_global_var_init.1.exit
xorps %xmm0, %xmm0
movups %xmm0, res(%rip)
movq $-200048, %rax # imm = 0xFFFCF290
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movups %xmm0, x+200048(%rax)
addq $100024, %rax # imm = 0x186B8
jne .LBB1_5
# %bb.6: # %__cxx_global_var_init.3.exit
retq
.Lfunc_end1:
.size _GLOBAL__sub_I_evaluate.hip, .Lfunc_end1-_GLOBAL__sub_I_evaluate.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8evaluateP10chromosomePiS1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type numofeles,@object # @numofeles
.bss
.globl numofeles
.p2align 2, 0x0
numofeles:
.long 0 # 0x0
.size numofeles, 4
.type capacity,@object # @capacity
.globl capacity
.p2align 2, 0x0
capacity:
.long 0 # 0x0
.size capacity, 4
.type chromoele,@object # @chromoele
.globl chromoele
.p2align 4, 0x0
chromoele:
.zero 5001200
.size chromoele, 5001200
.type cudaChromo,@object # @cudaChromo
.globl cudaChromo
.p2align 3, 0x0
cudaChromo:
.quad 0
.size cudaChromo, 8
.type cudaNewpopulation,@object # @cudaNewpopulation
.globl cudaNewpopulation
.p2align 3, 0x0
cudaNewpopulation:
.quad 0
.size cudaNewpopulation, 8
.type newpopulation,@object # @newpopulation
.globl newpopulation
.p2align 4, 0x0
newpopulation:
.zero 10002400
.size newpopulation, 10002400
.type res,@object # @res
.globl res
.p2align 3, 0x0
res:
.zero 100024
.size res, 100024
.type x,@object # @x
.globl x
.p2align 4, 0x0
x:
.zero 200048
.size x, 200048
.type weight,@object # @weight
.globl weight
.p2align 4, 0x0
weight:
.zero 400004
.size weight, 400004
.type value,@object # @value
.globl value
.p2align 4, 0x0
value:
.zero 400004
.size value, 400004
.type devValue,@object # @devValue
.globl devValue
.p2align 3, 0x0
devValue:
.quad 0
.size devValue, 8
.type devWeight,@object # @devWeight
.globl devWeight
.p2align 3, 0x0
devWeight:
.quad 0
.size devWeight, 8
.type devnumeles,@object # @devnumeles
.globl devnumeles
.p2align 3, 0x0
devnumeles:
.quad 0
.size devnumeles, 8
.type _Z8evaluateP10chromosomePiS1_i,@object # @_Z8evaluateP10chromosomePiS1_i
.section .rodata,"a",@progbits
.globl _Z8evaluateP10chromosomePiS1_i
.p2align 3, 0x0
_Z8evaluateP10chromosomePiS1_i:
.quad _Z23__device_stub__evaluateP10chromosomePiS1_i
.size _Z8evaluateP10chromosomePiS1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8evaluateP10chromosomePiS1_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_evaluate.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__evaluateP10chromosomePiS1_i
.addrsig_sym _GLOBAL__sub_I_evaluate.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8evaluateP10chromosomePiS1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/inner_product.h>
#include <thrust/for_each.h>
#include <cstdlib>
#include <vector>
typedef double ScalarType;
int main(void) {
/*
// generate 32M random numbers on the host
thrust::host_vector<int> h_vec(32 << 20);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
// transfer data to the device
thrust::device_vector<int> d_vec= h_vec;
// sort data on the device
thrust::sort(d_vec.begin(), d_vec.end());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << h_vec[0] << ", " << h_vec[1] << ", " << h_vec[2] << std::endl;
*/
std::vector<double> v1(100,1);
std::vector<double> v2(100,2);
std::vector<double> v1pv2(100,1);
std::vector<double> v1mv2(100,2);
for (int i = 0; i < 100; i++)
{
v1pv2[i] = v1[i] + v2[i];
v1mv2[i] = v1[i] - v2[i];
}
std::cout << "v1pv2: " << v1pv2[0] << std::endl;
std::cout << "v1mv2: " << v1mv2[0] << std::endl;
thrust::host_vector<double> h_v1 = v1pv2;
thrust::host_vector<double> h_v2 = v1mv2;
//h_v1 = h_v1 + h_v2;
//h_v2 = h_v1 - h_v2;
//thrust::generate(h_v1.begin(), h_v1.end(), rand);
//thrust::generate(h_v2.begin(), h_v2.end(), rand);
thrust::device_vector<ScalarType> d_v1 = h_v1;
thrust::device_vector<ScalarType> d_v2 = h_v2;
ScalarType start = 0;
//ScalarType expected_thrust = thrust::inner_product(h_v1.begin(), h_v1.end(), h_v2.begin(), start);
ScalarType expected_thrust = thrust::inner_product(d_v1.begin(), d_v1.end(), d_v2.begin(), start);
std::cout << "host dot: " << expected_thrust << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <thrust/inner_product.h>
#include <thrust/for_each.h>
#include <cstdlib>
#include <vector>
typedef double ScalarType;
int main(void) {
/*
// generate 32M random numbers on the host
thrust::host_vector<int> h_vec(32 << 20);
thrust::generate(h_vec.begin(), h_vec.end(), rand);
// transfer data to the device
thrust::device_vector<int> d_vec= h_vec;
// sort data on the device
thrust::sort(d_vec.begin(), d_vec.end());
// transfer data back to host
thrust::copy(d_vec.begin(), d_vec.end(), h_vec.begin());
std::cout << h_vec[0] << ", " << h_vec[1] << ", " << h_vec[2] << std::endl;
*/
std::vector<double> v1(100,1);
std::vector<double> v2(100,2);
std::vector<double> v1pv2(100,1);
std::vector<double> v1mv2(100,2);
for (int i = 0; i < 100; i++)
{
v1pv2[i] = v1[i] + v2[i];
v1mv2[i] = v1[i] - v2[i];
}
std::cout << "v1pv2: " << v1pv2[0] << std::endl;
std::cout << "v1mv2: " << v1mv2[0] << std::endl;
thrust::host_vector<double> h_v1 = v1pv2;
thrust::host_vector<double> h_v2 = v1mv2;
//h_v1 = h_v1 + h_v2;
//h_v2 = h_v1 - h_v2;
//thrust::generate(h_v1.begin(), h_v1.end(), rand);
//thrust::generate(h_v2.begin(), h_v2.end(), rand);
thrust::device_vector<ScalarType> d_v1 = h_v1;
thrust::device_vector<ScalarType> d_v2 = h_v2;
ScalarType start = 0;
//ScalarType expected_thrust = thrust::inner_product(h_v1.begin(), h_v1.end(), h_v2.begin(), start);
ScalarType expected_thrust = thrust::inner_product(d_v1.begin(), d_v1.end(), d_v2.begin(), start);
std::cout << "host dot: " << expected_thrust << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
comp = (+1.3269E34f - -1.9901E36f / (-0.0f + -1.1501E36f / var_1 * -1.9201E12f));
comp = -1.7101E-36f - (var_2 + var_3);
if (comp < var_4 / acosf(var_5 + (var_6 + log10f(sinf(+1.7934E35f / (-1.4872E34f - (var_7 * +1.0960E36f))))))) {
float tmp_1 = var_8 / +1.8982E-42f + (var_9 / var_10);
float tmp_2 = tanhf(+1.2637E-42f * (var_11 * var_12 * cosf(var_13 / var_14)));
comp += tmp_2 - tmp_1 * var_15 * var_16 / (+0.0f - sinf(+1.3280E34f / (var_17 + (-1.0570E-42f / (var_18 - powf((-1.6889E-36f / var_19), -1.2768E-43f - (-1.5121E2f + (var_20 - +1.6499E-37f - (var_21 * var_22)))))))));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000852a8_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
.type _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff, @function
_Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 392(%rsp), %rax
movq %rax, 248(%rsp)
leaq 400(%rsp), %rax
movq %rax, 256(%rsp)
leaq 408(%rsp), %rax
movq %rax, 264(%rsp)
leaq 416(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 312
pushq 40(%rsp)
.cfi_def_cfa_offset 320
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computefffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff, .-_Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
.globl _Z7computefffffffffffffffffffffff
.type _Z7computefffffffffffffffffffffff, @function
_Z7computefffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss 256(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
addq $136, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffffffffffffffffffffff, .-_Z7computefffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $224, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 200(%rsp)
movl $1, 204(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 212(%rsp), %rdx
movl $1, %ecx
movq 200(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 184(%rsp), %xmm0
addq $-128, %rsp
.cfi_def_cfa_offset 368
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 256(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 264(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 272(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 280(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 288(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 296(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
call _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
subq $-128, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
comp = (+1.3269E34f - -1.9901E36f / (-0.0f + -1.1501E36f / var_1 * -1.9201E12f));
comp = -1.7101E-36f - (var_2 + var_3);
if (comp < var_4 / acosf(var_5 + (var_6 + log10f(sinf(+1.7934E35f / (-1.4872E34f - (var_7 * +1.0960E36f))))))) {
float tmp_1 = var_8 / +1.8982E-42f + (var_9 / var_10);
float tmp_2 = tanhf(+1.2637E-42f * (var_11 * var_12 * cosf(var_13 / var_14)));
comp += tmp_2 - tmp_1 * var_15 * var_16 / (+0.0f - sinf(+1.3280E34f / (var_17 + (-1.0570E-42f / (var_18 - powf((-1.6889E-36f / var_19), -1.2768E-43f - (-1.5121E2f + (var_20 - +1.6499E-37f - (var_21 * var_22)))))))));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
comp = (+1.3269E34f - -1.9901E36f / (-0.0f + -1.1501E36f / var_1 * -1.9201E12f));
comp = -1.7101E-36f - (var_2 + var_3);
if (comp < var_4 / acosf(var_5 + (var_6 + log10f(sinf(+1.7934E35f / (-1.4872E34f - (var_7 * +1.0960E36f))))))) {
float tmp_1 = var_8 / +1.8982E-42f + (var_9 / var_10);
float tmp_2 = tanhf(+1.2637E-42f * (var_11 * var_12 * cosf(var_13 / var_14)));
comp += tmp_2 - tmp_1 * var_15 * var_16 / (+0.0f - sinf(+1.3280E34f / (var_17 + (-1.0570E-42f / (var_18 - powf((-1.6889E-36f / var_19), -1.2768E-43f - (-1.5121E2f + (var_20 - +1.6499E-37f - (var_21 * var_22)))))))));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22) {
comp = (+1.3269E34f - -1.9901E36f / (-0.0f + -1.1501E36f / var_1 * -1.9201E12f));
comp = -1.7101E-36f - (var_2 + var_3);
if (comp < var_4 / acosf(var_5 + (var_6 + log10f(sinf(+1.7934E35f / (-1.4872E34f - (var_7 * +1.0960E36f))))))) {
float tmp_1 = var_8 / +1.8982E-42f + (var_9 / var_10);
float tmp_2 = tanhf(+1.2637E-42f * (var_11 * var_12 * cosf(var_13 / var_14)));
comp += tmp_2 - tmp_1 * var_15 * var_16 / (+0.0f - sinf(+1.3280E34f / (var_17 + (-1.0570E-42f / (var_18 - powf((-1.6889E-36f / var_19), -1.2768E-43f - (-1.5121E2f + (var_20 - +1.6499E-37f - (var_21 * var_22)))))))));
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefffffffffffffffffffffff,@function
_Z22__device_stub__computefffffffffffffffffffffff: # @_Z22__device_stub__computefffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 272(%rsp), %rax
movq %rax, 144(%rsp)
leaq 280(%rsp), %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computefffffffffffffffffffffff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $304, %rsp # imm = 0x130
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 40(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 48(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 56(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 64(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 72(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 80(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 88(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 96(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 104(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 112(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 120(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 128(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 136(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 144(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 152(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 160(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 168(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 176(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 184(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 112(%rsp)
movss %xmm9, 104(%rsp)
movss %xmm10, 96(%rsp)
movss %xmm11, 88(%rsp)
movss %xmm12, 80(%rsp)
movss %xmm13, 72(%rsp)
movss %xmm14, 64(%rsp)
movss %xmm15, 56(%rsp)
movss %xmm4, 48(%rsp)
movss %xmm5, 40(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm7, 24(%rsp)
movss 120(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 16(%rsp)
movss 128(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 8(%rsp)
movss 136(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movss 168(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 160(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 152(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 144(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefffffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $304, %rsp # imm = 0x130
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffffffffffffffffffffff,@object # @_Z7computefffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefffffffffffffffffffffff:
.quad _Z22__device_stub__computefffffffffffffffffffffff
.size _Z7computefffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffffffffffffffffffffff"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000852a8_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
.type _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff, @function
_Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 392(%rsp), %rax
movq %rax, 248(%rsp)
leaq 400(%rsp), %rax
movq %rax, 256(%rsp)
leaq 408(%rsp), %rax
movq %rax, 264(%rsp)
leaq 416(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 312
pushq 40(%rsp)
.cfi_def_cfa_offset 320
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computefffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff, .-_Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
.globl _Z7computefffffffffffffffffffffff
.type _Z7computefffffffffffffffffffffff, @function
_Z7computefffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss 256(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
addq $136, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffffffffffffffffffffff, .-_Z7computefffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $224, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 200(%rsp)
movl $1, 204(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 212(%rsp), %rdx
movl $1, %ecx
movq 200(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 184(%rsp), %xmm0
addq $-128, %rsp
.cfi_def_cfa_offset 368
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 256(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 264(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 272(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 280(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 288(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 296(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
call _Z47__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffffffff
subq $-128, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefffffffffffffffffffffff,@function
_Z22__device_stub__computefffffffffffffffffffffff: # @_Z22__device_stub__computefffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 272(%rsp), %rax
movq %rax, 144(%rsp)
leaq 280(%rsp), %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computefffffffffffffffffffffff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $280, %rsp # imm = 0x118
.cfi_adjust_cfa_offset -280
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $304, %rsp # imm = 0x130
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 40(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 48(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 56(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 64(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 72(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 80(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 88(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 96(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 104(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 112(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 120(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 128(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 136(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 144(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 152(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 160(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 168(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 176(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 184(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 112(%rsp)
movss %xmm9, 104(%rsp)
movss %xmm10, 96(%rsp)
movss %xmm11, 88(%rsp)
movss %xmm12, 80(%rsp)
movss %xmm13, 72(%rsp)
movss %xmm14, 64(%rsp)
movss %xmm15, 56(%rsp)
movss %xmm4, 48(%rsp)
movss %xmm5, 40(%rsp)
movss %xmm6, 32(%rsp)
movss %xmm7, 24(%rsp)
movss 120(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 16(%rsp)
movss 128(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 8(%rsp)
movss 136(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movss 168(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 160(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 152(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 144(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefffffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $304, %rsp # imm = 0x130
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffffffffffffffffffffff,@object # @_Z7computefffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefffffffffffffffffffffff:
.quad _Z22__device_stub__computefffffffffffffffffffffff
.size _Z7computefffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffffffffffffffffffffff"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
__device__ double constrain_d_gpu(double val, double min, double max)
{
double tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ float constrain_f_gpu(float val, float min, float max)
{
float tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ int constrain_i_gpu(int val, int min, int max)
{
int tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
__device__ double constrain_d_gpu(double val, double min, double max)
{
double tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ float constrain_f_gpu(float val, float min, float max)
{
float tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ int constrain_i_gpu(int val, int min, int max)
{
int tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
} | .file "tmpxft_000ff7f9_00000000-6_constrain_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15constrain_d_gpuddd
.type _Z15constrain_d_gpuddd, @function
_Z15constrain_d_gpuddd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15constrain_d_gpuddd, .-_Z15constrain_d_gpuddd
.globl _Z15constrain_f_gpufff
.type _Z15constrain_f_gpufff, @function
_Z15constrain_f_gpufff:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z15constrain_f_gpufff, .-_Z15constrain_f_gpufff
.globl _Z15constrain_i_gpuiii
.type _Z15constrain_i_gpuiii, @function
_Z15constrain_i_gpuiii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z15constrain_i_gpuiii, .-_Z15constrain_i_gpuiii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
__device__ double constrain_d_gpu(double val, double min, double max)
{
double tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ float constrain_f_gpu(float val, float min, float max)
{
float tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ int constrain_i_gpu(int val, int min, int max)
{
int tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
} | #include "hip/hip_runtime.h"
__device__ double constrain_d_gpu(double val, double min, double max)
{
double tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ float constrain_f_gpu(float val, float min, float max)
{
float tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ int constrain_i_gpu(int val, int min, int max)
{
int tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
__device__ double constrain_d_gpu(double val, double min, double max)
{
double tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ float constrain_f_gpu(float val, float min, float max)
{
float tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ int constrain_i_gpu(int val, int min, int max)
{
int tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
__device__ double constrain_d_gpu(double val, double min, double max)
{
double tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ float constrain_f_gpu(float val, float min, float max)
{
float tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
}
__device__ int constrain_i_gpu(int val, int min, int max)
{
int tmp = val;
if (tmp <= min) tmp = min; if (tmp >= max) tmp = max;
return tmp;
} | .text
.file "constrain_gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ff7f9_00000000-6_constrain_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15constrain_d_gpuddd
.type _Z15constrain_d_gpuddd, @function
_Z15constrain_d_gpuddd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z15constrain_d_gpuddd, .-_Z15constrain_d_gpuddd
.globl _Z15constrain_f_gpufff
.type _Z15constrain_f_gpufff, @function
_Z15constrain_f_gpufff:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z15constrain_f_gpufff, .-_Z15constrain_f_gpufff
.globl _Z15constrain_i_gpuiii
.type _Z15constrain_i_gpuiii, @function
_Z15constrain_i_gpuiii:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z15constrain_i_gpuiii, .-_Z15constrain_i_gpuiii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "constrain_gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* BC_PointwiseDotproduct.cu
*
* Created on: Feb 6, 2018
* Author: joseph
*/
#ifndef BC_POINTWISEDOTPRODUCT_CU_
#define BC_POINTWISEDOTPRODUCT_CU_
namespace BC {
#ifdef __CUDACC__
#define __BC_gcpu__ __host__ __device__
#define BLACKCAT_GPU_ENABLED
#else
#define __BC_gcpu__
#endif
template<class, class> class Matrix;
template<class, class> class Vector;
template<class, class> class expression;
template<class T, class functor_type>
struct pointwise_accessor : expression<T, pointwise_accessor<T, functor_type>> {
//Evaluates a single row*column operation of two tensors
functor_type lv;
functor_type rv;
T* evaluation;
};
template<class T, class ml>
Vector<T, ml> operator * (const Matrix<T, ml>&, const Vector<T, ml>&) {
}
}
#endif /* BC_POINTWISEDOTPRODUCT_CU_ */ | code for sm_80 |
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