system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
void check_cells(float *rx, float *ry, float *rz, int *head, int *list, int mx, int my, int mz, int natoms, int step, int pstep)
{
int i, icell, ix, iy, iz, icount;
icount = 0;
for(icell=0;icell<(mx+2)*(my+2)*(mz+2);icell++){
ix = icell%(mx+2);
iy = (icell/(mx+2))%(my+2);
iz = icell/((mx+2)*(my+2));
i = head[icell];
if(step==pstep) printf("\nCell number %d at (%d,%d,%d) contains particles:",icell,ix,iy,iz);
while(i>=0){
if(ix>0&&ix<(mx+1)&&iy>0&&iy<(my+1)&&iz>0&&iz<(mz+1)) icount++;
// if(step==pstep) {
// if(rx[i] < -0.5 || rx[i] > 0.5 || ry[i] < -0.5 || ry[i] > 0.5 || rz[i] < -0.5 || rz[i] > 0.5) printf("%d, r = (%f,%f,%f) ",i,rx[i],ry[i],rz[i]);
// }
printf(" (%f,%f,%f);",rx[i],ry[i],rz[i]);
i = list[i];
}
}
if (icount != natoms) printf("\nNumber of particles in cells = %d\n",icount);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
void check_cells(float *rx, float *ry, float *rz, int *head, int *list, int mx, int my, int mz, int natoms, int step, int pstep)
{
int i, icell, ix, iy, iz, icount;
icount = 0;
for(icell=0;icell<(mx+2)*(my+2)*(mz+2);icell++){
ix = icell%(mx+2);
iy = (icell/(mx+2))%(my+2);
iz = icell/((mx+2)*(my+2));
i = head[icell];
if(step==pstep) printf("\nCell number %d at (%d,%d,%d) contains particles:",icell,ix,iy,iz);
while(i>=0){
if(ix>0&&ix<(mx+1)&&iy>0&&iy<(my+1)&&iz>0&&iz<(mz+1)) icount++;
// if(step==pstep) {
// if(rx[i] < -0.5 || rx[i] > 0.5 || ry[i] < -0.5 || ry[i] > 0.5 || rz[i] < -0.5 || rz[i] > 0.5) printf("%d, r = (%f,%f,%f) ",i,rx[i],ry[i],rz[i]);
// }
printf(" (%f,%f,%f);",rx[i],ry[i],rz[i]);
i = list[i];
}
}
if (icount != natoms) printf("\nNumber of particles in cells = %d\n",icount);
} | .file "tmpxft_000c4659_00000000-6_check_cells.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nCell number %d at (%d,%d,%d) contains particles:"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " (%f,%f,%f);"
.section .rodata.str1.8
.align 8
.LC2:
.string "\nNumber of particles in cells = %d\n"
.text
.globl _Z11check_cellsPfS_S_PiS0_iiiiii
.type _Z11check_cellsPfS_S_PiS0_iiiiii, @function
_Z11check_cellsPfS_S_PiS0_iiiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdx, %r12
movq %rcx, 48(%rsp)
movl %r9d, %eax
movl %r9d, 12(%rsp)
addl $2, %eax
movl %eax, 36(%rsp)
movl 128(%rsp), %edx
addl $2, %edx
movl %edx, 40(%rsp)
imull %edx, %eax
movl %eax, %edx
movl %eax, 44(%rsp)
movl 136(%rsp), %eax
addl $2, %eax
imull %edx, %eax
testl %eax, %eax
jle .L11
movq %rdi, %r15
movq %rsi, %r14
movq %r8, %r13
cltq
movq %rax, 56(%rsp)
movq $0, 16(%rsp)
movl $0, 32(%rsp)
jmp .L9
.L15:
movl 28(%rsp), %r9d
movl 24(%rsp), %r8d
movl %ebp, %ecx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L7:
movslq %ebx, %rbx
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
pxor %xmm2, %xmm2
cvtss2sd (%r12,%rbx,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r14,%rbx,4), %xmm1
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl 0(%r13,%rbx,4), %ebx
testl %ebx, %ebx
js .L6
.L8:
testl %ebp, %ebp
jle .L7
cmpl %ebp, 12(%rsp)
jl .L7
movl 24(%rsp), %eax
testl %eax, %eax
jle .L7
cmpl %eax, 128(%rsp)
jl .L7
movl 28(%rsp), %eax
testl %eax, %eax
jle .L7
cmpl %eax, 136(%rsp)
setge %al
cmpb $1, %al
sbbl $-1, 32(%rsp)
jmp .L7
.L6:
addq $1, 16(%rsp)
movq 16(%rsp), %rax
movq 56(%rsp), %rcx
cmpq %rcx, %rax
je .L4
.L9:
movq 16(%rsp), %rcx
movl %ecx, %esi
movl %ecx, %eax
cltd
idivl 36(%rsp)
movl %edx, %ebp
cltd
idivl 40(%rsp)
movl %edx, 24(%rsp)
movl %ecx, %eax
cltd
idivl 44(%rsp)
movl %eax, 28(%rsp)
movq 48(%rsp), %rax
movl (%rax,%rcx,4), %ebx
movl 160(%rsp), %eax
cmpl %eax, 152(%rsp)
je .L15
.L5:
testl %ebx, %ebx
jns .L8
jmp .L6
.L11:
movl $0, 32(%rsp)
.L4:
movl 32(%rsp), %eax
cmpl %eax, 144(%rsp)
jne .L16
.L3:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11check_cellsPfS_S_PiS0_iiiiii, .-_Z11check_cellsPfS_S_PiS0_iiiiii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
void check_cells(float *rx, float *ry, float *rz, int *head, int *list, int mx, int my, int mz, int natoms, int step, int pstep)
{
int i, icell, ix, iy, iz, icount;
icount = 0;
for(icell=0;icell<(mx+2)*(my+2)*(mz+2);icell++){
ix = icell%(mx+2);
iy = (icell/(mx+2))%(my+2);
iz = icell/((mx+2)*(my+2));
i = head[icell];
if(step==pstep) printf("\nCell number %d at (%d,%d,%d) contains particles:",icell,ix,iy,iz);
while(i>=0){
if(ix>0&&ix<(mx+1)&&iy>0&&iy<(my+1)&&iz>0&&iz<(mz+1)) icount++;
// if(step==pstep) {
// if(rx[i] < -0.5 || rx[i] > 0.5 || ry[i] < -0.5 || ry[i] > 0.5 || rz[i] < -0.5 || rz[i] > 0.5) printf("%d, r = (%f,%f,%f) ",i,rx[i],ry[i],rz[i]);
// }
printf(" (%f,%f,%f);",rx[i],ry[i],rz[i]);
i = list[i];
}
}
if (icount != natoms) printf("\nNumber of particles in cells = %d\n",icount);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
void check_cells(float *rx, float *ry, float *rz, int *head, int *list, int mx, int my, int mz, int natoms, int step, int pstep)
{
int i, icell, ix, iy, iz, icount;
icount = 0;
for(icell=0;icell<(mx+2)*(my+2)*(mz+2);icell++){
ix = icell%(mx+2);
iy = (icell/(mx+2))%(my+2);
iz = icell/((mx+2)*(my+2));
i = head[icell];
if(step==pstep) printf("\nCell number %d at (%d,%d,%d) contains particles:",icell,ix,iy,iz);
while(i>=0){
if(ix>0&&ix<(mx+1)&&iy>0&&iy<(my+1)&&iz>0&&iz<(mz+1)) icount++;
// if(step==pstep) {
// if(rx[i] < -0.5 || rx[i] > 0.5 || ry[i] < -0.5 || ry[i] > 0.5 || rz[i] < -0.5 || rz[i] > 0.5) printf("%d, r = (%f,%f,%f) ",i,rx[i],ry[i],rz[i]);
// }
printf(" (%f,%f,%f);",rx[i],ry[i],rz[i]);
i = list[i];
}
}
if (icount != natoms) printf("\nNumber of particles in cells = %d\n",icount);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void check_cells(float *rx, float *ry, float *rz, int *head, int *list, int mx, int my, int mz, int natoms, int step, int pstep)
{
int i, icell, ix, iy, iz, icount;
icount = 0;
for(icell=0;icell<(mx+2)*(my+2)*(mz+2);icell++){
ix = icell%(mx+2);
iy = (icell/(mx+2))%(my+2);
iz = icell/((mx+2)*(my+2));
i = head[icell];
if(step==pstep) printf("\nCell number %d at (%d,%d,%d) contains particles:",icell,ix,iy,iz);
while(i>=0){
if(ix>0&&ix<(mx+1)&&iy>0&&iy<(my+1)&&iz>0&&iz<(mz+1)) icount++;
// if(step==pstep) {
// if(rx[i] < -0.5 || rx[i] > 0.5 || ry[i] < -0.5 || ry[i] > 0.5 || rz[i] < -0.5 || rz[i] > 0.5) printf("%d, r = (%f,%f,%f) ",i,rx[i],ry[i],rz[i]);
// }
printf(" (%f,%f,%f);",rx[i],ry[i],rz[i]);
i = list[i];
}
}
if (icount != natoms) printf("\nNumber of particles in cells = %d\n",icount);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void check_cells(float *rx, float *ry, float *rz, int *head, int *list, int mx, int my, int mz, int natoms, int step, int pstep)
{
int i, icell, ix, iy, iz, icount;
icount = 0;
for(icell=0;icell<(mx+2)*(my+2)*(mz+2);icell++){
ix = icell%(mx+2);
iy = (icell/(mx+2))%(my+2);
iz = icell/((mx+2)*(my+2));
i = head[icell];
if(step==pstep) printf("\nCell number %d at (%d,%d,%d) contains particles:",icell,ix,iy,iz);
while(i>=0){
if(ix>0&&ix<(mx+1)&&iy>0&&iy<(my+1)&&iz>0&&iz<(mz+1)) icount++;
// if(step==pstep) {
// if(rx[i] < -0.5 || rx[i] > 0.5 || ry[i] < -0.5 || ry[i] > 0.5 || rz[i] < -0.5 || rz[i] > 0.5) printf("%d, r = (%f,%f,%f) ",i,rx[i],ry[i],rz[i]);
// }
printf(" (%f,%f,%f);",rx[i],ry[i],rz[i]);
i = list[i];
}
}
if (icount != natoms) printf("\nNumber of particles in cells = %d\n",icount);
} | .text
.file "check_cells.hip"
.globl _Z11check_cellsPfS_S_PiS0_iiiiii # -- Begin function _Z11check_cellsPfS_S_PiS0_iiiiii
.p2align 4, 0x90
.type _Z11check_cellsPfS_S_PiS0_iiiiii,@function
_Z11check_cellsPfS_S_PiS0_iiiiii: # @_Z11check_cellsPfS_S_PiS0_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r9d killed $r9d def $r9
movq %rcx, 104(%rsp) # 8-byte Spill
movl 192(%rsp), %eax
movl %eax, 12(%rsp) # 4-byte Spill
movl 184(%rsp), %ecx
movl 176(%rsp), %r10d
movq %r9, %rax
movq %r9, 88(%rsp) # 8-byte Spill
leal 2(%r9), %eax
movq %r10, 72(%rsp) # 8-byte Spill
leal 2(%r10), %r9d
movl %r9d, 28(%rsp) # 4-byte Spill
movl %eax, 32(%rsp) # 4-byte Spill
imull %eax, %r9d
movq %rcx, 80(%rsp) # 8-byte Spill
leal 2(%rcx), %eax
movl %r9d, 24(%rsp) # 4-byte Spill
imull %r9d, %eax
testl %eax, %eax
jle .LBB0_1
# %bb.2: # %.lr.ph61
movq %rdi, 40(%rsp) # 8-byte Spill
movq %rsi, 48(%rsp) # 8-byte Spill
movq %rdx, 56(%rsp) # 8-byte Spill
movq %r8, 64(%rsp) # 8-byte Spill
movl 208(%rsp), %ecx
movl %ecx, 20(%rsp) # 4-byte Spill
movl 200(%rsp), %ecx
movl %ecx, 16(%rsp) # 4-byte Spill
movl %eax, %eax
movq %rax, 96(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebx, %ebx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_8: # %._crit_edge
# in Loop: Header=BB0_3 Depth=1
movq 112(%rsp), %r14 # 8-byte Reload
incq %r14
cmpq 96(%rsp), %r14 # 8-byte Folded Reload
je .LBB0_9
.LBB0_3: # =>This Loop Header: Depth=1
# Child Loop BB0_7 Depth 2
movl %r14d, %eax
cltd
idivl 32(%rsp) # 4-byte Folded Reload
movl %edx, %ebp
cltd
idivl 28(%rsp) # 4-byte Folded Reload
movl %edx, %r12d
movl %r14d, %eax
cltd
idivl 24(%rsp) # 4-byte Folded Reload
movl %eax, %r13d
movq 104(%rsp), %rax # 8-byte Reload
movl (%rax,%r14,4), %r15d
movl 16(%rsp), %eax # 4-byte Reload
cmpl 20(%rsp), %eax # 4-byte Folded Reload
jne .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=1
movl $.L.str, %edi
movl %r14d, %esi
movl %ebp, %edx
movl %r12d, %ecx
movl %r13d, %r8d
xorl %eax, %eax
callq printf
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
movq %r14, 112(%rsp) # 8-byte Spill
testl %r15d, %r15d
js .LBB0_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB0_3 Depth=1
testl %ebp, %ebp
setne %al
cmpl 88(%rsp), %ebp # 4-byte Folded Reload
setle %cl
testl %r12d, %r12d
setg %dl
andb %cl, %dl
cmpl 72(%rsp), %r12d # 4-byte Folded Reload
setle %cl
testl %r13d, %r13d
setg %sil
cmpl 80(%rsp), %r13d # 4-byte Folded Reload
setle %dil
andb %sil, %dil
andb %cl, %dil
andb %dl, %dil
andb %al, %dil
movzbl %dil, %eax
movl %eax, 36(%rsp) # 4-byte Spill
movq 64(%rsp), %r12 # 8-byte Reload
movq 56(%rsp), %r13 # 8-byte Reload
movq 48(%rsp), %rbp # 8-byte Reload
movq 40(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB0_7: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
addl 36(%rsp), %ebx # 4-byte Folded Reload
movl %r15d, %r15d
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbp,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r13,%r15,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
movl (%r12,%r15,4), %r15d
testl %r15d, %r15d
jns .LBB0_7
jmp .LBB0_8
.LBB0_1:
xorl %ebx, %ebx
.LBB0_9: # %._crit_edge62
cmpl 12(%rsp), %ebx # 4-byte Folded Reload
jne .LBB0_11
# %bb.10:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 176
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11check_cellsPfS_S_PiS0_iiiiii, .Lfunc_end0-_Z11check_cellsPfS_S_PiS0_iiiiii
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nCell number %d at (%d,%d,%d) contains particles:"
.size .L.str, 50
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " (%f,%f,%f)
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNumber of particles in cells = %d\n"
.size .L.str.2, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c4659_00000000-6_check_cells.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nCell number %d at (%d,%d,%d) contains particles:"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " (%f,%f,%f);"
.section .rodata.str1.8
.align 8
.LC2:
.string "\nNumber of particles in cells = %d\n"
.text
.globl _Z11check_cellsPfS_S_PiS0_iiiiii
.type _Z11check_cellsPfS_S_PiS0_iiiiii, @function
_Z11check_cellsPfS_S_PiS0_iiiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdx, %r12
movq %rcx, 48(%rsp)
movl %r9d, %eax
movl %r9d, 12(%rsp)
addl $2, %eax
movl %eax, 36(%rsp)
movl 128(%rsp), %edx
addl $2, %edx
movl %edx, 40(%rsp)
imull %edx, %eax
movl %eax, %edx
movl %eax, 44(%rsp)
movl 136(%rsp), %eax
addl $2, %eax
imull %edx, %eax
testl %eax, %eax
jle .L11
movq %rdi, %r15
movq %rsi, %r14
movq %r8, %r13
cltq
movq %rax, 56(%rsp)
movq $0, 16(%rsp)
movl $0, 32(%rsp)
jmp .L9
.L15:
movl 28(%rsp), %r9d
movl 24(%rsp), %r8d
movl %ebp, %ecx
movl %esi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L7:
movslq %ebx, %rbx
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
pxor %xmm2, %xmm2
cvtss2sd (%r12,%rbx,4), %xmm2
pxor %xmm1, %xmm1
cvtss2sd (%r14,%rbx,4), %xmm1
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl 0(%r13,%rbx,4), %ebx
testl %ebx, %ebx
js .L6
.L8:
testl %ebp, %ebp
jle .L7
cmpl %ebp, 12(%rsp)
jl .L7
movl 24(%rsp), %eax
testl %eax, %eax
jle .L7
cmpl %eax, 128(%rsp)
jl .L7
movl 28(%rsp), %eax
testl %eax, %eax
jle .L7
cmpl %eax, 136(%rsp)
setge %al
cmpb $1, %al
sbbl $-1, 32(%rsp)
jmp .L7
.L6:
addq $1, 16(%rsp)
movq 16(%rsp), %rax
movq 56(%rsp), %rcx
cmpq %rcx, %rax
je .L4
.L9:
movq 16(%rsp), %rcx
movl %ecx, %esi
movl %ecx, %eax
cltd
idivl 36(%rsp)
movl %edx, %ebp
cltd
idivl 40(%rsp)
movl %edx, 24(%rsp)
movl %ecx, %eax
cltd
idivl 44(%rsp)
movl %eax, 28(%rsp)
movq 48(%rsp), %rax
movl (%rax,%rcx,4), %ebx
movl 160(%rsp), %eax
cmpl %eax, 152(%rsp)
je .L15
.L5:
testl %ebx, %ebx
jns .L8
jmp .L6
.L11:
movl $0, 32(%rsp)
.L4:
movl 32(%rsp), %eax
cmpl %eax, 144(%rsp)
jne .L16
.L3:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z11check_cellsPfS_S_PiS0_iiiiii, .-_Z11check_cellsPfS_S_PiS0_iiiiii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check_cells.hip"
.globl _Z11check_cellsPfS_S_PiS0_iiiiii # -- Begin function _Z11check_cellsPfS_S_PiS0_iiiiii
.p2align 4, 0x90
.type _Z11check_cellsPfS_S_PiS0_iiiiii,@function
_Z11check_cellsPfS_S_PiS0_iiiiii: # @_Z11check_cellsPfS_S_PiS0_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r9d killed $r9d def $r9
movq %rcx, 104(%rsp) # 8-byte Spill
movl 192(%rsp), %eax
movl %eax, 12(%rsp) # 4-byte Spill
movl 184(%rsp), %ecx
movl 176(%rsp), %r10d
movq %r9, %rax
movq %r9, 88(%rsp) # 8-byte Spill
leal 2(%r9), %eax
movq %r10, 72(%rsp) # 8-byte Spill
leal 2(%r10), %r9d
movl %r9d, 28(%rsp) # 4-byte Spill
movl %eax, 32(%rsp) # 4-byte Spill
imull %eax, %r9d
movq %rcx, 80(%rsp) # 8-byte Spill
leal 2(%rcx), %eax
movl %r9d, 24(%rsp) # 4-byte Spill
imull %r9d, %eax
testl %eax, %eax
jle .LBB0_1
# %bb.2: # %.lr.ph61
movq %rdi, 40(%rsp) # 8-byte Spill
movq %rsi, 48(%rsp) # 8-byte Spill
movq %rdx, 56(%rsp) # 8-byte Spill
movq %r8, 64(%rsp) # 8-byte Spill
movl 208(%rsp), %ecx
movl %ecx, 20(%rsp) # 4-byte Spill
movl 200(%rsp), %ecx
movl %ecx, 16(%rsp) # 4-byte Spill
movl %eax, %eax
movq %rax, 96(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebx, %ebx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_8: # %._crit_edge
# in Loop: Header=BB0_3 Depth=1
movq 112(%rsp), %r14 # 8-byte Reload
incq %r14
cmpq 96(%rsp), %r14 # 8-byte Folded Reload
je .LBB0_9
.LBB0_3: # =>This Loop Header: Depth=1
# Child Loop BB0_7 Depth 2
movl %r14d, %eax
cltd
idivl 32(%rsp) # 4-byte Folded Reload
movl %edx, %ebp
cltd
idivl 28(%rsp) # 4-byte Folded Reload
movl %edx, %r12d
movl %r14d, %eax
cltd
idivl 24(%rsp) # 4-byte Folded Reload
movl %eax, %r13d
movq 104(%rsp), %rax # 8-byte Reload
movl (%rax,%r14,4), %r15d
movl 16(%rsp), %eax # 4-byte Reload
cmpl 20(%rsp), %eax # 4-byte Folded Reload
jne .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=1
movl $.L.str, %edi
movl %r14d, %esi
movl %ebp, %edx
movl %r12d, %ecx
movl %r13d, %r8d
xorl %eax, %eax
callq printf
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
movq %r14, 112(%rsp) # 8-byte Spill
testl %r15d, %r15d
js .LBB0_8
# %bb.6: # %.lr.ph
# in Loop: Header=BB0_3 Depth=1
testl %ebp, %ebp
setne %al
cmpl 88(%rsp), %ebp # 4-byte Folded Reload
setle %cl
testl %r12d, %r12d
setg %dl
andb %cl, %dl
cmpl 72(%rsp), %r12d # 4-byte Folded Reload
setle %cl
testl %r13d, %r13d
setg %sil
cmpl 80(%rsp), %r13d # 4-byte Folded Reload
setle %dil
andb %sil, %dil
andb %cl, %dil
andb %dl, %dil
andb %al, %dil
movzbl %dil, %eax
movl %eax, 36(%rsp) # 4-byte Spill
movq 64(%rsp), %r12 # 8-byte Reload
movq 56(%rsp), %r13 # 8-byte Reload
movq 48(%rsp), %rbp # 8-byte Reload
movq 40(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB0_7: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
addl 36(%rsp), %ebx # 4-byte Folded Reload
movl %r15d, %r15d
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbp,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r13,%r15,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.1, %edi
movb $3, %al
callq printf
movl (%r12,%r15,4), %r15d
testl %r15d, %r15d
jns .LBB0_7
jmp .LBB0_8
.LBB0_1:
xorl %ebx, %ebx
.LBB0_9: # %._crit_edge62
cmpl 12(%rsp), %ebx # 4-byte Folded Reload
jne .LBB0_11
# %bb.10:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 176
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end0:
.size _Z11check_cellsPfS_S_PiS0_iiiiii, .Lfunc_end0-_Z11check_cellsPfS_S_PiS0_iiiiii
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nCell number %d at (%d,%d,%d) contains particles:"
.size .L.str, 50
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " (%f,%f,%f)
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nNumber of particles in cells = %d\n"
.size .L.str.2, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
__global__ void gpuHistogram(unsigned int* data, unsigned int* bins, unsigned int numElements, unsigned int numBins)
{
extern __shared__ unsigned int privateHistogram[];
int i = 0;
int stride = blockDim.x * gridDim.x;
// This is because we have less threads then we do bins and we need to clear all the bins.
while(i*blockDim.x + threadIdx.x < numBins)
{
privateHistogram[i*blockDim.x + threadIdx.x] = 0;
i++;
}
__syncthreads();
// Normally go through the data.
i = blockDim.x * blockIdx.x + threadIdx.x;
while(i < numElements)
{
atomicAdd(&(privateHistogram[data[i]]), 1);
i += stride;
}
__syncthreads();
// Copy all the data back.
i = 0;
while(i*blockDim.x + threadIdx.x < numBins)
{
atomicAdd(&(bins[i*blockDim.x + threadIdx.x]), privateHistogram[i*blockDim.x + threadIdx.x]);
i++;
}
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins)
{
dim3 gridDim(30,1,1); // 30 SMPs per machine
dim3 blockDim(32,1,1); // 32 threads executing at once.
gpuHistogram<<<gridDim, blockDim, num_bins * sizeof(unsigned int)>>>(input,bins,num_elements,num_bins);
} | code for sm_80
Function : _Z12gpuHistogramPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x100 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x001fe20003f06070 */
/*0050*/ IMAD R3, R0, c[0x0][0x0], R7 ; /* 0x0000000000037a24 */
/* 0x002fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fce0003f46070 */
/*0070*/ @P0 BRA 0xf0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0080*/ MOV R0, R7 ; /* 0x0000000700007202 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fca00078e00ff */
/*00a0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0001e80000004800 */
/*00c0*/ IMAD R0, R2, c[0x0][0x0], R7 ; /* 0x0000000002007a24 */
/* 0x001fca00078e0207 */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f26070 */
/*00e0*/ @!P1 BRA 0xa0 ; /* 0xffffffb000009947 */
/* 0x000fea000383ffff */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ @P2 BRA 0x1d0 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*0130*/ MOV R0, R3 ; /* 0x0000000300007202 */
/* 0x000fe40000000f00 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0170*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*0180*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0190*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26070 */
/*01b0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*01c0*/ @!P1 BRA 0x140 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*01d0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0210*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0230*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x0012a20000004800 */
/*0240*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fe200078e0009 */
/*0260*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0270*/ IMAD R4, R0, c[0x0][0x0], R7 ; /* 0x0000000000047a24 */
/* 0x002fca00078e0207 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fe20003f06070 */
/*0290*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0041d8000c10e184 */
/*02a0*/ @!P0 BRA 0x230 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
__global__ void gpuHistogram(unsigned int* data, unsigned int* bins, unsigned int numElements, unsigned int numBins)
{
extern __shared__ unsigned int privateHistogram[];
int i = 0;
int stride = blockDim.x * gridDim.x;
// This is because we have less threads then we do bins and we need to clear all the bins.
while(i*blockDim.x + threadIdx.x < numBins)
{
privateHistogram[i*blockDim.x + threadIdx.x] = 0;
i++;
}
__syncthreads();
// Normally go through the data.
i = blockDim.x * blockIdx.x + threadIdx.x;
while(i < numElements)
{
atomicAdd(&(privateHistogram[data[i]]), 1);
i += stride;
}
__syncthreads();
// Copy all the data back.
i = 0;
while(i*blockDim.x + threadIdx.x < numBins)
{
atomicAdd(&(bins[i*blockDim.x + threadIdx.x]), privateHistogram[i*blockDim.x + threadIdx.x]);
i++;
}
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins)
{
dim3 gridDim(30,1,1); // 30 SMPs per machine
dim3 blockDim(32,1,1); // 32 threads executing at once.
gpuHistogram<<<gridDim, blockDim, num_bins * sizeof(unsigned int)>>>(input,bins,num_elements,num_bins);
} | .file "tmpxft_0019bd81_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
.type _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj, @function
_Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12gpuHistogramPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj, .-_Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
.globl _Z12gpuHistogramPjS_jj
.type _Z12gpuHistogramPjS_jj, @function
_Z12gpuHistogramPjS_jj:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12gpuHistogramPjS_jj, .-_Z12gpuHistogramPjS_jj
.globl _Z9histogramPjS_jj
.type _Z9histogramPjS_jj, @function
_Z9histogramPjS_jj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r13d
movl %ecx, %ebx
movl $30, 8(%rsp)
movl $1, 12(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl %ecx, %eax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %ecx
movl %r13d, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9histogramPjS_jj, .-_Z9histogramPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12gpuHistogramPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpuHistogramPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
__global__ void gpuHistogram(unsigned int* data, unsigned int* bins, unsigned int numElements, unsigned int numBins)
{
extern __shared__ unsigned int privateHistogram[];
int i = 0;
int stride = blockDim.x * gridDim.x;
// This is because we have less threads then we do bins and we need to clear all the bins.
while(i*blockDim.x + threadIdx.x < numBins)
{
privateHistogram[i*blockDim.x + threadIdx.x] = 0;
i++;
}
__syncthreads();
// Normally go through the data.
i = blockDim.x * blockIdx.x + threadIdx.x;
while(i < numElements)
{
atomicAdd(&(privateHistogram[data[i]]), 1);
i += stride;
}
__syncthreads();
// Copy all the data back.
i = 0;
while(i*blockDim.x + threadIdx.x < numBins)
{
atomicAdd(&(bins[i*blockDim.x + threadIdx.x]), privateHistogram[i*blockDim.x + threadIdx.x]);
i++;
}
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins)
{
dim3 gridDim(30,1,1); // 30 SMPs per machine
dim3 blockDim(32,1,1); // 32 threads executing at once.
gpuHistogram<<<gridDim, blockDim, num_bins * sizeof(unsigned int)>>>(input,bins,num_elements,num_bins);
} | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
__global__ void gpuHistogram(unsigned int* data, unsigned int* bins, unsigned int numElements, unsigned int numBins)
{
extern __shared__ unsigned int privateHistogram[];
int i = 0;
int stride = blockDim.x * gridDim.x;
// This is because we have less threads then we do bins and we need to clear all the bins.
while(i*blockDim.x + threadIdx.x < numBins)
{
privateHistogram[i*blockDim.x + threadIdx.x] = 0;
i++;
}
__syncthreads();
// Normally go through the data.
i = blockDim.x * blockIdx.x + threadIdx.x;
while(i < numElements)
{
atomicAdd(&(privateHistogram[data[i]]), 1);
i += stride;
}
__syncthreads();
// Copy all the data back.
i = 0;
while(i*blockDim.x + threadIdx.x < numBins)
{
atomicAdd(&(bins[i*blockDim.x + threadIdx.x]), privateHistogram[i*blockDim.x + threadIdx.x]);
i++;
}
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins)
{
dim3 gridDim(30,1,1); // 30 SMPs per machine
dim3 blockDim(32,1,1); // 32 threads executing at once.
gpuHistogram<<<gridDim, blockDim, num_bins * sizeof(unsigned int)>>>(input,bins,num_elements,num_bins);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
__global__ void gpuHistogram(unsigned int* data, unsigned int* bins, unsigned int numElements, unsigned int numBins)
{
extern __shared__ unsigned int privateHistogram[];
int i = 0;
int stride = blockDim.x * gridDim.x;
// This is because we have less threads then we do bins and we need to clear all the bins.
while(i*blockDim.x + threadIdx.x < numBins)
{
privateHistogram[i*blockDim.x + threadIdx.x] = 0;
i++;
}
__syncthreads();
// Normally go through the data.
i = blockDim.x * blockIdx.x + threadIdx.x;
while(i < numElements)
{
atomicAdd(&(privateHistogram[data[i]]), 1);
i += stride;
}
__syncthreads();
// Copy all the data back.
i = 0;
while(i*blockDim.x + threadIdx.x < numBins)
{
atomicAdd(&(bins[i*blockDim.x + threadIdx.x]), privateHistogram[i*blockDim.x + threadIdx.x]);
i++;
}
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins)
{
dim3 gridDim(30,1,1); // 30 SMPs per machine
dim3 blockDim(32,1,1); // 32 threads executing at once.
gpuHistogram<<<gridDim, blockDim, num_bins * sizeof(unsigned int)>>>(input,bins,num_elements,num_bins);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpuHistogramPjS_jj
.globl _Z12gpuHistogramPjS_jj
.p2align 8
.type _Z12gpuHistogramPjS_jj,@function
_Z12gpuHistogramPjS_jj:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x14
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s6, 0
s_lshl_b32 s7, s3, 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s3, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, s7, v1
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s10, s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mul_i32 s6, s5, s3
v_mov_b32_e32 v4, 1
s_ashr_i32 s7, s6, 31
s_mov_b32 s5, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_5:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, s2, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
v_cmp_le_u32_e32 vcc_lo, s10, v1
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 2, 0
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v2, v0, 2, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
s_lshl_b32 s5, s3, 2
.LBB0_8:
ds_load_b32 v5, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
v_add_nc_u32_e32 v2, s5, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_or_b32 s2, vcc_lo, s2
global_atomic_add_u32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpuHistogramPjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpuHistogramPjS_jj, .Lfunc_end0-_Z12gpuHistogramPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym privateHistogram
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpuHistogramPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpuHistogramPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
// Define your kernels in this file you may use more than one kernel if you
// need to
__global__ void gpuHistogram(unsigned int* data, unsigned int* bins, unsigned int numElements, unsigned int numBins)
{
extern __shared__ unsigned int privateHistogram[];
int i = 0;
int stride = blockDim.x * gridDim.x;
// This is because we have less threads then we do bins and we need to clear all the bins.
while(i*blockDim.x + threadIdx.x < numBins)
{
privateHistogram[i*blockDim.x + threadIdx.x] = 0;
i++;
}
__syncthreads();
// Normally go through the data.
i = blockDim.x * blockIdx.x + threadIdx.x;
while(i < numElements)
{
atomicAdd(&(privateHistogram[data[i]]), 1);
i += stride;
}
__syncthreads();
// Copy all the data back.
i = 0;
while(i*blockDim.x + threadIdx.x < numBins)
{
atomicAdd(&(bins[i*blockDim.x + threadIdx.x]), privateHistogram[i*blockDim.x + threadIdx.x]);
i++;
}
}
/******************************************************************************
Setup and invoke your kernel(s) in this function. You may also allocate more
GPU memory if you need to
*******************************************************************************/
void histogram(unsigned int* input, unsigned int* bins, unsigned int num_elements, unsigned int num_bins)
{
dim3 gridDim(30,1,1); // 30 SMPs per machine
dim3 blockDim(32,1,1); // 32 threads executing at once.
gpuHistogram<<<gridDim, blockDim, num_bins * sizeof(unsigned int)>>>(input,bins,num_elements,num_bins);
} | .text
.file "kernel.hip"
.globl _Z27__device_stub__gpuHistogramPjS_jj # -- Begin function _Z27__device_stub__gpuHistogramPjS_jj
.p2align 4, 0x90
.type _Z27__device_stub__gpuHistogramPjS_jj,@function
_Z27__device_stub__gpuHistogramPjS_jj: # @_Z27__device_stub__gpuHistogramPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpuHistogramPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__gpuHistogramPjS_jj, .Lfunc_end0-_Z27__device_stub__gpuHistogramPjS_jj
.cfi_endproc
# -- End function
.globl _Z9histogramPjS_jj # -- Begin function _Z9histogramPjS_jj
.p2align 4, 0x90
.type _Z9histogramPjS_jj,@function
_Z9histogramPjS_jj: # @_Z9histogramPjS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r8d
shlq $2, %r8
movabsq $4294967326, %rdi # imm = 0x10000001E
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpuHistogramPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9histogramPjS_jj, .Lfunc_end1-_Z9histogramPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpuHistogramPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpuHistogramPjS_jj,@object # @_Z12gpuHistogramPjS_jj
.section .rodata,"a",@progbits
.globl _Z12gpuHistogramPjS_jj
.p2align 3, 0x0
_Z12gpuHistogramPjS_jj:
.quad _Z27__device_stub__gpuHistogramPjS_jj
.size _Z12gpuHistogramPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpuHistogramPjS_jj"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpuHistogramPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpuHistogramPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12gpuHistogramPjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x100 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x001fe20003f06070 */
/*0050*/ IMAD R3, R0, c[0x0][0x0], R7 ; /* 0x0000000000037a24 */
/* 0x002fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P2, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fce0003f46070 */
/*0070*/ @P0 BRA 0xf0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0080*/ MOV R0, R7 ; /* 0x0000000700007202 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fca00078e00ff */
/*00a0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0001e80000004800 */
/*00c0*/ IMAD R0, R2, c[0x0][0x0], R7 ; /* 0x0000000002007a24 */
/* 0x001fca00078e0207 */
/*00d0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f26070 */
/*00e0*/ @!P1 BRA 0xa0 ; /* 0xffffffb000009947 */
/* 0x000fea000383ffff */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ @P2 BRA 0x1d0 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*0130*/ MOV R0, R3 ; /* 0x0000000300007202 */
/* 0x000fe40000000f00 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0170*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*0180*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0190*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26070 */
/*01b0*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*01c0*/ @!P1 BRA 0x140 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*01d0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0210*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0230*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x0012a20000004800 */
/*0240*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fe200078e0009 */
/*0260*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe60003800000 */
/*0270*/ IMAD R4, R0, c[0x0][0x0], R7 ; /* 0x0000000000047a24 */
/* 0x002fca00078e0207 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fe20003f06070 */
/*0290*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x0041d8000c10e184 */
/*02a0*/ @!P0 BRA 0x230 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12gpuHistogramPjS_jj
.globl _Z12gpuHistogramPjS_jj
.p2align 8
.type _Z12gpuHistogramPjS_jj,@function
_Z12gpuHistogramPjS_jj:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x14
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_lshl_add_u32 v1, v0, 2, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, v0
s_mov_b32 s6, 0
s_lshl_b32 s7, s3, 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s3, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, s7, v1
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s10, s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mul_i32 s6, s5, s3
v_mov_b32_e32 v4, 1
s_ashr_i32 s7, s6, 31
s_mov_b32 s5, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_lshl_b64 s[8:9], s[6:7], 2
.LBB0_5:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s6, v1
v_add_co_u32 v2, s2, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s9, v3, s2
v_cmp_le_u32_e32 vcc_lo, s10, v1
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 2, 0
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v2, v0, 2, 0
v_mov_b32_e32 v1, 0
s_mov_b32 s2, 0
s_lshl_b32 s5, s3, 2
.LBB0_8:
ds_load_b32 v5, v2
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
v_add_nc_u32_e32 v2, s5, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_or_b32 s2, vcc_lo, s2
global_atomic_add_u32 v[3:4], v5, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_8
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12gpuHistogramPjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12gpuHistogramPjS_jj, .Lfunc_end0-_Z12gpuHistogramPjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym privateHistogram
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12gpuHistogramPjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12gpuHistogramPjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019bd81_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
.type _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj, @function
_Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12gpuHistogramPjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj, .-_Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
.globl _Z12gpuHistogramPjS_jj
.type _Z12gpuHistogramPjS_jj, @function
_Z12gpuHistogramPjS_jj:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z12gpuHistogramPjS_jj, .-_Z12gpuHistogramPjS_jj
.globl _Z9histogramPjS_jj
.type _Z9histogramPjS_jj, @function
_Z9histogramPjS_jj:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %r13d
movl %ecx, %ebx
movl $30, 8(%rsp)
movl $1, 12(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl %ecx, %eax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %ecx
movl %r13d, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z36__device_stub__Z12gpuHistogramPjS_jjPjS_jj
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9histogramPjS_jj, .-_Z9histogramPjS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12gpuHistogramPjS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12gpuHistogramPjS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z27__device_stub__gpuHistogramPjS_jj # -- Begin function _Z27__device_stub__gpuHistogramPjS_jj
.p2align 4, 0x90
.type _Z27__device_stub__gpuHistogramPjS_jj,@function
_Z27__device_stub__gpuHistogramPjS_jj: # @_Z27__device_stub__gpuHistogramPjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpuHistogramPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__gpuHistogramPjS_jj, .Lfunc_end0-_Z27__device_stub__gpuHistogramPjS_jj
.cfi_endproc
# -- End function
.globl _Z9histogramPjS_jj # -- Begin function _Z9histogramPjS_jj
.p2align 4, 0x90
.type _Z9histogramPjS_jj,@function
_Z9histogramPjS_jj: # @_Z9histogramPjS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r8d
shlq $2, %r8
movabsq $4294967326, %rdi # imm = 0x10000001E
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12gpuHistogramPjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9histogramPjS_jj, .Lfunc_end1-_Z9histogramPjS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12gpuHistogramPjS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12gpuHistogramPjS_jj,@object # @_Z12gpuHistogramPjS_jj
.section .rodata,"a",@progbits
.globl _Z12gpuHistogramPjS_jj
.p2align 3, 0x0
_Z12gpuHistogramPjS_jj:
.quad _Z27__device_stub__gpuHistogramPjS_jj
.size _Z12gpuHistogramPjS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12gpuHistogramPjS_jj"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__gpuHistogramPjS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12gpuHistogramPjS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime_api.h>
#include <iostream>
// Managed variables may be defined like device variables
__managed__ unsigned int mFoo;
// Print a managed variable
__global__ void PrintFoo()
{
printf("mFoo GPU: %d\n", mFoo);
}
// Print a managed array of integers
__global__ void PrintBar(const int* mBarPtr, unsigned int numEntries)
{
printf("mBar GPU: ");
for (int i = 0; i < numEntries; i++)
printf("%d%s", mBarPtr[i], (i == numEntries - 1) ? "\n" : ", ");
}
int main()
{
std::cout << "==== Sample 13 - Managed Memory ====\n" << std::endl;
/*
Managed memory reduces code complexity by decoupling physical
memory location from address range. The CUDA runtime will take
care of moving the memory to the location where it is needed.
No copies are required, but care must be taken for concurrent
access. To avoid performance degradation, managed memory should
be prefetched.
Expected output:
mFoo GPU: 14
mBar GPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
mBar CPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
CUDA device does (NOT) support concurrent access
mFoo GPU: 42
*/
constexpr unsigned int VALUE = 14;
// We may assign values to managed variables on the CPU
mFoo = VALUE;
// Managed variables can be used without explicit transfer
PrintFoo<<<1,1>>>();
// Wait for printf output
cudaDeviceSynchronize();
// We may also allocate managed memory on demand
int* mBarPtr;
cudaMallocManaged((void**)&mBarPtr, VALUE * sizeof(int));
// Managed memory can be directly initialized on the CPU
for (int i = 0; i < VALUE; i++)
mBarPtr[i] = i;
/*
If we know ahead of time where managed memory will be used
and performance is essential, we can prefetch it to the
required location. This basically replaces memcpy. Note
however, that this action requires support for the
concurrentAccess property. Support for concurrent access
is queried via device properties.
*/
int device;
cudaGetDevice(&device);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, device);
// Report support
std::cout << "\nCUDA device does " << (!prop.concurrentManagedAccess ? "NOT " : "") << "support concurrent access\n";
// If we can, we prefetch ahead of time
if(prop.concurrentManagedAccess)
cudaMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), device);
// Launch kernel with managed memory pointer as parameter
PrintBar<<<1,1>>>(mBarPtr, VALUE);
// We may also prefetch it back to the CPU
if (prop.concurrentManagedAccess)
cudaMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), cudaCpuDeviceId);
// Wait for GPU printing and prefetching to finish
cudaDeviceSynchronize();
std::cout << "mBar CPU: ";
for (int i = 0; i < VALUE; i++)
std::cout << mBarPtr[i] << (i == VALUE - 1 ? "\n" : ", ");
/*
Devices may or may not support concurrent access to variables.
If they don't, then the CPU must ensure that access to managed
memory does not overlap with GPU kernel execution, even if the
GPU does not use the managed memory in question. Modifying
a variable on the CPU before a kernel is fine, because the kernel
will only be launched if the CPU is done with prior instructions.
*/
// Handling access to managed memory, depending on device properties
mFoo = 42;
PrintFoo<<<1, 1>>>();
if (!prop.concurrentManagedAccess)
// CPU access to managed memory and GPU execution may not overlap
cudaDeviceSynchronize();
// Modify on CPU after / during GPU execution
mBarPtr[0] = 20;
// Wait for results of printf
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z8PrintBarPKij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fce000001ff00 */
/*0070*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*0080*/ MOV R11, 0xf0 ; /* 0x000000f0000b7802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R20, 0x70 ; /* 0x0000007000147802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*00b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*00c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00f0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f05270 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R27, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff1b7624 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3 R18, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001127a10 */
/* 0x000fe20007f3e0ff */
/*0130*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e00ff */
/*0140*/ IADD3 R25, R27.reuse, -0x1, RZ ; /* 0xffffffff1b197810 */
/* 0x040fe20007ffe0ff */
/*0150*/ IMAD.X R19, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff137624 */
/* 0x000fe200008e06ff */
/*0160*/ LOP3.LUT R27, R27, 0x3, RZ, 0xc0, !PT ; /* 0x000000031b1b7812 */
/* 0x000fe400078ec0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R25, 0x3, PT ; /* 0x000000031900780c */
/* 0x000fda0003f06070 */
/*0180*/ @!P0 BRA 0x870 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*0190*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*01a0*/ BSSY B6, 0x870 ; /* 0x000006c000067945 */
/* 0x000fe20003800000 */
/*01b0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*01c0*/ IADD3 R22, -R27, c[0x0][0x168], RZ ; /* 0x00005a001b167a10 */
/* 0x000fe20007ffe1ff */
/*01d0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.U32 R28, RZ, RZ, UR4 ; /* 0x00000004ff1c7e24 */
/* 0x000fc4000f8e00ff */
/*0210*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0220*/ LDG.E R0, [R16.64] ; /* 0x0000000410007981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe200078e00ff */
/*0240*/ ISETP.NE.AND P0, PT, R28, -0x1, PT ; /* 0xffffffff1c00780c */
/* 0x000fe20003f05270 */
/*0250*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff027624 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R23, 0x0 ; /* 0x0000000000177802 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; /* 0x01000c00ff047624 */
/* 0x000fe200078e00ff */
/*0280*/ SEL R8, R8, c[0x4][0x28], !P0 ; /* 0x01000a0008087a07 */
/* 0x000fe20004000000 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff057624 */
/* 0x000fe200078e00ff */
/*02a0*/ SEL R9, R2, c[0x4][0x2c], !P0 ; /* 0x01000b0002097a07 */
/* 0x000fe20004000000 */
/*02b0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0012 */
/*02c0*/ LDC.64 R2, c[0x4][R23] ; /* 0x0100000017027b82 */
/* 0x0000620000000a00 */
/*02d0*/ IADD3 R22, R22, -0x4, RZ ; /* 0xfffffffc16167810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*02f0*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001e40000100a00 */
/*0300*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc80003f05270 */
/*0310*/ P2R R24, PR, RZ, 0x1 ; /* 0x00000001ff187803 */
/* 0x000fe20000000000 */
/*0320*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*0330*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*0340*/ MOV R11, 0x3b0 ; /* 0x000003b0000b7802 */
/* 0x000fe40000000f00 */
/*0350*/ MOV R20, 0x330 ; /* 0x0000033000147802 */
/* 0x000fe40000000f00 */
/*0360*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0370*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0380*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0390*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*03a0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*03b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*03c0*/ LDG.E R0, [R16.64+0x4] ; /* 0x0000040410007981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IADD3 R2, R26, 0x1, RZ ; /* 0x000000011a027810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe400078e00ff */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; /* 0x01000c00ff047624 */
/* 0x000fe200078e00ff */
/*0400*/ ISETP.NE.AND P0, PT, R2, R25, PT ; /* 0x000000190200720c */
/* 0x000fe20003f05270 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff027624 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff057624 */
/* 0x000fe200078e00ff */
/*0430*/ SEL R8, R8, c[0x4][0x28], !P0 ; /* 0x01000a0008087a07 */
/* 0x000fe20004000000 */
/*0440*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0012 */
/*0450*/ SEL R9, R2, c[0x4][0x2c], !P0 ; /* 0x01000b0002097a07 */
/* 0x000fe20004000000 */
/*0460*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*0470*/ LDC.64 R2, c[0x4][R23] ; /* 0x0100000017027b82 */
/* 0x0000660000000a00 */
/*0480*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001e80000100a00 */
/*0490*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e40000100800 */
/*04a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*04b0*/ MOV R11, 0x520 ; /* 0x00000520000b7802 */
/* 0x000fc40000000f00 */
/*04c0*/ MOV R20, 0x4a0 ; /* 0x000004a000147802 */
/* 0x000fe40000000f00 */
/*04d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*04e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*04f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0500*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0510*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0520*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0530*/ LDG.E R0, [R16.64+0x8] ; /* 0x0000080410007981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R2, R26, 0x2, RZ ; /* 0x000000021a027810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe400078e00ff */
/*0560*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; /* 0x01000c00ff047624 */
/* 0x000fe200078e00ff */
/*0570*/ ISETP.NE.AND P0, PT, R2, R25, PT ; /* 0x000000190200720c */
/* 0x000fe20003f05270 */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff027624 */
/* 0x000fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff057624 */
/* 0x000fe200078e00ff */
/*05a0*/ SEL R8, R8, c[0x4][0x28], !P0 ; /* 0x01000a0008087a07 */
/* 0x000fe20004000000 */
/*05b0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0012 */
/*05c0*/ SEL R9, R2, c[0x4][0x2c], !P0 ; /* 0x01000b0002097a07 */
/* 0x000fe20004000000 */
/*05d0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*05e0*/ LDC.64 R2, c[0x4][R23] ; /* 0x0100000017027b82 */
/* 0x0000660000000a00 */
/*05f0*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001e80000100a00 */
/*0600*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e40000100800 */
/*0610*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*0620*/ MOV R11, 0x690 ; /* 0x00000690000b7802 */
/* 0x000fc40000000f00 */
/*0630*/ MOV R20, 0x610 ; /* 0x0000061000147802 */
/* 0x000fe40000000f00 */
/*0640*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0650*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0660*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0670*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0680*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0690*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*06a0*/ LDG.E R0, [R16.64+0xc] ; /* 0x00000c0410007981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ IADD3 R2, R26, 0x3, RZ ; /* 0x000000031a027810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; /* 0x01000c00ff047624 */
/* 0x000fe200078e00ff */
/*06e0*/ ISETP.NE.AND P0, PT, R2, R25, PT ; /* 0x000000190200720c */
/* 0x000fe20003f05270 */
/*06f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff027624 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff057624 */
/* 0x000fe200078e00ff */
/*0710*/ SEL R8, R8, c[0x4][0x28], !P0 ; /* 0x01000a0008087a07 */
/* 0x000fe20004000000 */
/*0720*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0012 */
/*0730*/ SEL R9, R2, c[0x4][0x2c], !P0 ; /* 0x01000b0002097a07 */
/* 0x000fe20004000000 */
/*0740*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*0750*/ LDC.64 R2, c[0x4][R23] ; /* 0x0100000017027b82 */
/* 0x0000660000000a00 */
/*0760*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001e80000100a00 */
/*0770*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e40000100800 */
/*0780*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*0790*/ MOV R11, 0x800 ; /* 0x00000800000b7802 */
/* 0x000fc40000000f00 */
/*07a0*/ MOV R20, 0x780 ; /* 0x0000078000147802 */
/* 0x000fe40000000f00 */
/*07b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*07c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*07d0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*07e0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*07f0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0800*/ ISETP.NE.AND P6, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe40003fc5270 */
/*0810*/ IADD3 R16, P0, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f1e0ff */
/*0820*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R28, R28, 0x4, RZ ; /* 0x000000041c1c7810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.X R17, RZ, RZ, R17, P0 ; /* 0x000000ffff117224 */
/* 0x000fcc00000e0611 */
/*0850*/ @P6 BRA 0x210 ; /* 0xfffff9b000006947 */
/* 0x000fea000383ffff */
/*0860*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fda0003f05270 */
/*0880*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*08a0*/ IMAD.WIDE R16, R26.reuse, R17, c[0x0][0x160] ; /* 0x000058001a107625 */
/* 0x040fe200078e0211 */
/*08b0*/ IADD3 R26, R26, -c[0x0][0x168], RZ ; /* 0x80005a001a1a7a10 */
/* 0x000fc60007ffe0ff */
/*08c0*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0010 */
/*08d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*08e0*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0011 */
/*08f0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x0000a2000c1e1900 */
/*0900*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff087624 */
/* 0x000fe200078e00ff */
/*0910*/ ISETP.NE.AND P0, PT, R26, -0x1, PT ; /* 0xffffffff1a00780c */
/* 0x000fe20003f05270 */
/*0920*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff037624 */
/* 0x000fe200078e00ff */
/*0930*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0940*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x30] ; /* 0x01000c00ff047624 */
/* 0x000fe200078e00ff */
/*0950*/ SEL R8, R8, c[0x4][0x28], !P0 ; /* 0x01000a0008087a07 */
/* 0x000fe20004000000 */
/*0960*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x34] ; /* 0x01000d00ff057624 */
/* 0x000fe200078e00ff */
/*0970*/ SEL R9, R3, c[0x4][0x2c], !P0 ; /* 0x01000b0003097a07 */
/* 0x000fe40004000000 */
/*0980*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0990*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x001fc400078e0012 */
/*09a0*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001e20000100a00 */
/*09b0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0013 */
/*09c0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0041e80000100800 */
/*09d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*09e0*/ MOV R11, 0xa50 ; /* 0x00000a50000b7802 */
/* 0x000fe40000000f00 */
/*09f0*/ MOV R20, 0x9d0 ; /* 0x000009d000147802 */
/* 0x000fe40000000f00 */
/*0a00*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a10*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0a20*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0a30*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0a40*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0a50*/ IADD3 R27, R27, -0x1, RZ ; /* 0xffffffff1b1b7810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R16, P1, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fe40007f3e0ff */
/*0a70*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fe40003f05270 */
/*0a80*/ IADD3 R26, R26, 0x1, RZ ; /* 0x000000011a1a7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ IMAD.X R17, RZ, RZ, R17, P1 ; /* 0x000000ffff117224 */
/* 0x000fd400008e0611 */
/*0aa0*/ @P0 BRA 0x8c0 ; /* 0xfffffe1000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ac0*/ BRA 0xac0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8PrintFoov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000660000000a00 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00c0*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0041e80000100800 */
/*00d0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fc60000000000 */
/*00e0*/ MOV R11, 0x150 ; /* 0x00000150000b7802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R20, 0xd0 ; /* 0x000000d000147802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0120*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0130*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0140*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <iostream>
// Managed variables may be defined like device variables
__managed__ unsigned int mFoo;
// Print a managed variable
__global__ void PrintFoo()
{
printf("mFoo GPU: %d\n", mFoo);
}
// Print a managed array of integers
__global__ void PrintBar(const int* mBarPtr, unsigned int numEntries)
{
printf("mBar GPU: ");
for (int i = 0; i < numEntries; i++)
printf("%d%s", mBarPtr[i], (i == numEntries - 1) ? "\n" : ", ");
}
int main()
{
std::cout << "==== Sample 13 - Managed Memory ====\n" << std::endl;
/*
Managed memory reduces code complexity by decoupling physical
memory location from address range. The CUDA runtime will take
care of moving the memory to the location where it is needed.
No copies are required, but care must be taken for concurrent
access. To avoid performance degradation, managed memory should
be prefetched.
Expected output:
mFoo GPU: 14
mBar GPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
mBar CPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
CUDA device does (NOT) support concurrent access
mFoo GPU: 42
*/
constexpr unsigned int VALUE = 14;
// We may assign values to managed variables on the CPU
mFoo = VALUE;
// Managed variables can be used without explicit transfer
PrintFoo<<<1,1>>>();
// Wait for printf output
cudaDeviceSynchronize();
// We may also allocate managed memory on demand
int* mBarPtr;
cudaMallocManaged((void**)&mBarPtr, VALUE * sizeof(int));
// Managed memory can be directly initialized on the CPU
for (int i = 0; i < VALUE; i++)
mBarPtr[i] = i;
/*
If we know ahead of time where managed memory will be used
and performance is essential, we can prefetch it to the
required location. This basically replaces memcpy. Note
however, that this action requires support for the
concurrentAccess property. Support for concurrent access
is queried via device properties.
*/
int device;
cudaGetDevice(&device);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, device);
// Report support
std::cout << "\nCUDA device does " << (!prop.concurrentManagedAccess ? "NOT " : "") << "support concurrent access\n";
// If we can, we prefetch ahead of time
if(prop.concurrentManagedAccess)
cudaMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), device);
// Launch kernel with managed memory pointer as parameter
PrintBar<<<1,1>>>(mBarPtr, VALUE);
// We may also prefetch it back to the CPU
if (prop.concurrentManagedAccess)
cudaMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), cudaCpuDeviceId);
// Wait for GPU printing and prefetching to finish
cudaDeviceSynchronize();
std::cout << "mBar CPU: ";
for (int i = 0; i < VALUE; i++)
std::cout << mBarPtr[i] << (i == VALUE - 1 ? "\n" : ", ");
/*
Devices may or may not support concurrent access to variables.
If they don't, then the CPU must ensure that access to managed
memory does not overlap with GPU kernel execution, even if the
GPU does not use the managed memory in question. Modifying
a variable on the CPU before a kernel is fine, because the kernel
will only be launched if the CPU is done with prior instructions.
*/
// Handling access to managed memory, depending on device properties
mFoo = 42;
PrintFoo<<<1, 1>>>();
if (!prop.concurrentManagedAccess)
// CPU access to managed memory and GPU execution may not overlap
cudaDeviceSynchronize();
// Modify on CPU after / during GPU execution
mBarPtr[0] = 20;
// Wait for results of printf
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00085103_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE1:
.size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8PrintFoovv
.type _Z26__device_stub__Z8PrintFoovv, @function
_Z26__device_stub__Z8PrintFoovv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8PrintFoov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z8PrintFoovv, .-_Z26__device_stub__Z8PrintFoovv
.globl _Z8PrintFoov
.type _Z8PrintFoov, @function
_Z8PrintFoov:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8PrintFoovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8PrintFoov, .-_Z8PrintFoov
.globl _Z29__device_stub__Z8PrintBarPKijPKij
.type _Z29__device_stub__Z8PrintBarPKijPKij, @function
_Z29__device_stub__Z8PrintBarPKijPKij:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8PrintBarPKij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z29__device_stub__Z8PrintBarPKijPKij, .-_Z29__device_stub__Z8PrintBarPKijPKij
.globl _Z8PrintBarPKij
.type _Z8PrintBarPKij, @function
_Z8PrintBarPKij:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8PrintBarPKijPKij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8PrintBarPKij, .-_Z8PrintBarPKij
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "NOT "
.LC1:
.string ""
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "==== Sample 13 - Managed Memory ====\n"
.section .rodata.str1.1
.LC3:
.string "\nCUDA device does "
.LC4:
.string "support concurrent access\n"
.LC5:
.string "mBar CPU: "
.LC6:
.string "\n"
.LC7:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L46
.L27:
movq _ZL4mFoo(%rip), %rax
movl $14, (%rax)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L28:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $56, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L29:
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $14, %rax
jne .L29
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
cmpl $0, 724(%rsp)
leaq .LC1(%rip), %rsi
leaq .LC0(%rip), %rax
cmove %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 724(%rsp)
jne .L48
.L31:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L32:
cmpl $0, 724(%rsp)
jne .L50
.L33:
call cudaDeviceSynchronize@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC7(%rip), %r12
leaq .LC6(%rip), %r13
jmp .L36
.L46:
call _ZL20__nv_init_managed_rtv
jmp .L27
.L47:
call _Z26__device_stub__Z8PrintFoovv
jmp .L28
.L48:
movl $0, %ecx
movl 12(%rsp), %edx
movl $56, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
jmp .L31
.L49:
movl $14, %esi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z8PrintBarPKijPKij
jmp .L32
.L50:
movl $0, %ecx
movl $-1, %edx
movl $56, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
jmp .L33
.L52:
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $14, %rbx
je .L51
.L36:
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
cmpl $13, %ebx
je .L52
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
jmp .L36
.L51:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L53
.L37:
movq _ZL4mFoo(%rip), %rax
movl $42, (%rax)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L38:
cmpl $0, 724(%rsp)
je .L55
.L39:
movq 16(%rsp), %rax
movl $20, (%rax)
call cudaDeviceSynchronize@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call _ZL20__nv_init_managed_rtv
jmp .L37
.L54:
call _Z26__device_stub__Z8PrintFoovv
jmp .L38
.L55:
call cudaDeviceSynchronize@PLT
jmp .L39
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8PrintBarPKij"
.LC9:
.string "_Z8PrintFoov"
.LC10:
.string "mFoo"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8PrintBarPKij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8PrintFoov(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4mFoo(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL4mFoo, @object
.size _ZL4mFoo, 8
_ZL4mFoo:
.zero 8
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <iostream>
// Managed variables may be defined like device variables
__managed__ unsigned int mFoo;
// Print a managed variable
__global__ void PrintFoo()
{
printf("mFoo GPU: %d\n", mFoo);
}
// Print a managed array of integers
__global__ void PrintBar(const int* mBarPtr, unsigned int numEntries)
{
printf("mBar GPU: ");
for (int i = 0; i < numEntries; i++)
printf("%d%s", mBarPtr[i], (i == numEntries - 1) ? "\n" : ", ");
}
int main()
{
std::cout << "==== Sample 13 - Managed Memory ====\n" << std::endl;
/*
Managed memory reduces code complexity by decoupling physical
memory location from address range. The CUDA runtime will take
care of moving the memory to the location where it is needed.
No copies are required, but care must be taken for concurrent
access. To avoid performance degradation, managed memory should
be prefetched.
Expected output:
mFoo GPU: 14
mBar GPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
mBar CPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
CUDA device does (NOT) support concurrent access
mFoo GPU: 42
*/
constexpr unsigned int VALUE = 14;
// We may assign values to managed variables on the CPU
mFoo = VALUE;
// Managed variables can be used without explicit transfer
PrintFoo<<<1,1>>>();
// Wait for printf output
cudaDeviceSynchronize();
// We may also allocate managed memory on demand
int* mBarPtr;
cudaMallocManaged((void**)&mBarPtr, VALUE * sizeof(int));
// Managed memory can be directly initialized on the CPU
for (int i = 0; i < VALUE; i++)
mBarPtr[i] = i;
/*
If we know ahead of time where managed memory will be used
and performance is essential, we can prefetch it to the
required location. This basically replaces memcpy. Note
however, that this action requires support for the
concurrentAccess property. Support for concurrent access
is queried via device properties.
*/
int device;
cudaGetDevice(&device);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, device);
// Report support
std::cout << "\nCUDA device does " << (!prop.concurrentManagedAccess ? "NOT " : "") << "support concurrent access\n";
// If we can, we prefetch ahead of time
if(prop.concurrentManagedAccess)
cudaMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), device);
// Launch kernel with managed memory pointer as parameter
PrintBar<<<1,1>>>(mBarPtr, VALUE);
// We may also prefetch it back to the CPU
if (prop.concurrentManagedAccess)
cudaMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), cudaCpuDeviceId);
// Wait for GPU printing and prefetching to finish
cudaDeviceSynchronize();
std::cout << "mBar CPU: ";
for (int i = 0; i < VALUE; i++)
std::cout << mBarPtr[i] << (i == VALUE - 1 ? "\n" : ", ");
/*
Devices may or may not support concurrent access to variables.
If they don't, then the CPU must ensure that access to managed
memory does not overlap with GPU kernel execution, even if the
GPU does not use the managed memory in question. Modifying
a variable on the CPU before a kernel is fine, because the kernel
will only be launched if the CPU is done with prior instructions.
*/
// Handling access to managed memory, depending on device properties
mFoo = 42;
PrintFoo<<<1, 1>>>();
if (!prop.concurrentManagedAccess)
// CPU access to managed memory and GPU execution may not overlap
cudaDeviceSynchronize();
// Modify on CPU after / during GPU execution
mBarPtr[0] = 20;
// Wait for results of printf
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
// Managed variables may be defined like device variables
__managed__ unsigned int mFoo;
// Print a managed variable
__global__ void PrintFoo()
{
printf("mFoo GPU: %d\n", mFoo);
}
// Print a managed array of integers
__global__ void PrintBar(const int* mBarPtr, unsigned int numEntries)
{
printf("mBar GPU: ");
for (int i = 0; i < numEntries; i++)
printf("%d%s", mBarPtr[i], (i == numEntries - 1) ? "\n" : ", ");
}
int main()
{
std::cout << "==== Sample 13 - Managed Memory ====\n" << std::endl;
/*
Managed memory reduces code complexity by decoupling physical
memory location from address range. The CUDA runtime will take
care of moving the memory to the location where it is needed.
No copies are required, but care must be taken for concurrent
access. To avoid performance degradation, managed memory should
be prefetched.
Expected output:
mFoo GPU: 14
mBar GPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
mBar CPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
CUDA device does (NOT) support concurrent access
mFoo GPU: 42
*/
constexpr unsigned int VALUE = 14;
// We may assign values to managed variables on the CPU
mFoo = VALUE;
// Managed variables can be used without explicit transfer
PrintFoo<<<1,1>>>();
// Wait for printf output
hipDeviceSynchronize();
// We may also allocate managed memory on demand
int* mBarPtr;
hipMallocManaged((void**)&mBarPtr, VALUE * sizeof(int));
// Managed memory can be directly initialized on the CPU
for (int i = 0; i < VALUE; i++)
mBarPtr[i] = i;
/*
If we know ahead of time where managed memory will be used
and performance is essential, we can prefetch it to the
required location. This basically replaces memcpy. Note
however, that this action requires support for the
concurrentAccess property. Support for concurrent access
is queried via device properties.
*/
int device;
hipGetDevice(&device);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, device);
// Report support
std::cout << "\nCUDA device does " << (!prop.concurrentManagedAccess ? "NOT " : "") << "support concurrent access\n";
// If we can, we prefetch ahead of time
if(prop.concurrentManagedAccess)
hipMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), device);
// Launch kernel with managed memory pointer as parameter
PrintBar<<<1,1>>>(mBarPtr, VALUE);
// We may also prefetch it back to the CPU
if (prop.concurrentManagedAccess)
hipMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), hipCpuDeviceId);
// Wait for GPU printing and prefetching to finish
hipDeviceSynchronize();
std::cout << "mBar CPU: ";
for (int i = 0; i < VALUE; i++)
std::cout << mBarPtr[i] << (i == VALUE - 1 ? "\n" : ", ");
/*
Devices may or may not support concurrent access to variables.
If they don't, then the CPU must ensure that access to managed
memory does not overlap with GPU kernel execution, even if the
GPU does not use the managed memory in question. Modifying
a variable on the CPU before a kernel is fine, because the kernel
will only be launched if the CPU is done with prior instructions.
*/
// Handling access to managed memory, depending on device properties
mFoo = 42;
PrintFoo<<<1, 1>>>();
if (!prop.concurrentManagedAccess)
// CPU access to managed memory and GPU execution may not overlap
hipDeviceSynchronize();
// Modify on CPU after / during GPU execution
mBarPtr[0] = 20;
// Wait for results of printf
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
// Managed variables may be defined like device variables
__managed__ unsigned int mFoo;
// Print a managed variable
__global__ void PrintFoo()
{
printf("mFoo GPU: %d\n", mFoo);
}
// Print a managed array of integers
__global__ void PrintBar(const int* mBarPtr, unsigned int numEntries)
{
printf("mBar GPU: ");
for (int i = 0; i < numEntries; i++)
printf("%d%s", mBarPtr[i], (i == numEntries - 1) ? "\n" : ", ");
}
int main()
{
std::cout << "==== Sample 13 - Managed Memory ====\n" << std::endl;
/*
Managed memory reduces code complexity by decoupling physical
memory location from address range. The CUDA runtime will take
care of moving the memory to the location where it is needed.
No copies are required, but care must be taken for concurrent
access. To avoid performance degradation, managed memory should
be prefetched.
Expected output:
mFoo GPU: 14
mBar GPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
mBar CPU: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
CUDA device does (NOT) support concurrent access
mFoo GPU: 42
*/
constexpr unsigned int VALUE = 14;
// We may assign values to managed variables on the CPU
mFoo = VALUE;
// Managed variables can be used without explicit transfer
PrintFoo<<<1,1>>>();
// Wait for printf output
hipDeviceSynchronize();
// We may also allocate managed memory on demand
int* mBarPtr;
hipMallocManaged((void**)&mBarPtr, VALUE * sizeof(int));
// Managed memory can be directly initialized on the CPU
for (int i = 0; i < VALUE; i++)
mBarPtr[i] = i;
/*
If we know ahead of time where managed memory will be used
and performance is essential, we can prefetch it to the
required location. This basically replaces memcpy. Note
however, that this action requires support for the
concurrentAccess property. Support for concurrent access
is queried via device properties.
*/
int device;
hipGetDevice(&device);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, device);
// Report support
std::cout << "\nCUDA device does " << (!prop.concurrentManagedAccess ? "NOT " : "") << "support concurrent access\n";
// If we can, we prefetch ahead of time
if(prop.concurrentManagedAccess)
hipMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), device);
// Launch kernel with managed memory pointer as parameter
PrintBar<<<1,1>>>(mBarPtr, VALUE);
// We may also prefetch it back to the CPU
if (prop.concurrentManagedAccess)
hipMemPrefetchAsync(mBarPtr, VALUE * sizeof(int), hipCpuDeviceId);
// Wait for GPU printing and prefetching to finish
hipDeviceSynchronize();
std::cout << "mBar CPU: ";
for (int i = 0; i < VALUE; i++)
std::cout << mBarPtr[i] << (i == VALUE - 1 ? "\n" : ", ");
/*
Devices may or may not support concurrent access to variables.
If they don't, then the CPU must ensure that access to managed
memory does not overlap with GPU kernel execution, even if the
GPU does not use the managed memory in question. Modifying
a variable on the CPU before a kernel is fine, because the kernel
will only be launched if the CPU is done with prior instructions.
*/
// Handling access to managed memory, depending on device properties
mFoo = 42;
PrintFoo<<<1, 1>>>();
if (!prop.concurrentManagedAccess)
// CPU access to managed memory and GPU execution may not overlap
hipDeviceSynchronize();
// Modify on CPU after / during GPU execution
mBarPtr[0] = 20;
// Wait for results of printf
hipDeviceSynchronize();
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__PrintFoov # -- Begin function _Z23__device_stub__PrintFoov
.p2align 4, 0x90
.type _Z23__device_stub__PrintFoov,@function
_Z23__device_stub__PrintFoov: # @_Z23__device_stub__PrintFoov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8PrintFoov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__PrintFoov, .Lfunc_end0-_Z23__device_stub__PrintFoov
.cfi_endproc
# -- End function
.globl _Z23__device_stub__PrintBarPKij # -- Begin function _Z23__device_stub__PrintBarPKij
.p2align 4, 0x90
.type _Z23__device_stub__PrintBarPKij,@function
_Z23__device_stub__PrintBarPKij: # @_Z23__device_stub__PrintBarPKij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8PrintBarPKij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__PrintBarPKij, .Lfunc_end1-_Z23__device_stub__PrintBarPKij
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movabsq $4294967297, %rbx # imm = 0x100000001
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq mFoo(%rip), %rax
movl $14, (%rax)
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
leaq 112(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z8PrintFoov, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq %rsp, %rdi
movl $56, %esi
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $14, %rax
jne .LBB2_7
# %bb.8:
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 112(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %edx, %edx
cmpl $0, 788(%rsp)
sete %dl
movl $.L.str.2, %eax
movl $.L.str.3, %esi
cmoveq %rax, %rsi
shll $2, %edx
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 788(%rsp)
je .LBB2_10
# %bb.9:
movq (%rsp), %rdi
movl 12(%rsp), %edx
movl $56, %esi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.LBB2_10:
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq (%rsp), %rax
movq %rax, 32(%rsp)
movl $14, 92(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 92(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8PrintBarPKij, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
cmpl $0, 788(%rsp)
je .LBB2_14
# %bb.13:
movq (%rsp), %rdi
movl $56, %esi
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.LBB2_14:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq $-14, %r14
movl $.L.str.6, %r15d
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl 56(%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %edx, %edx
incq %r14
movl $.L.str.7, %esi
cmoveq %r15, %rsi
setne %dl
incq %rdx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testq %r14, %r14
jne .LBB2_15
# %bb.16:
movq mFoo(%rip), %rax
movl $42, (%rax)
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_17
# %bb.18:
cmpl $0, 788(%rsp)
je .LBB2_19
.LBB2_20:
movq (%rsp), %rax
movl $20, (%rax)
callq hipDeviceSynchronize
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 1616
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8PrintFoov, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $0, 788(%rsp)
jne .LBB2_20
.LBB2_19:
callq hipDeviceSynchronize
jmp .LBB2_20
.LBB2_21:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8PrintFoov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8PrintBarPKij, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $mFoo, %esi
movl $mFoo.managed, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r8d
movq %rbx, %rdi
movl $4, %r9d
callq __hipRegisterManagedVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type mFoo.managed,@object # @mFoo.managed
.local mFoo.managed
.comm mFoo.managed,4,4
.type _Z8PrintFoov,@object # @_Z8PrintFoov
.section .rodata,"a",@progbits
.globl _Z8PrintFoov
.p2align 3, 0x0
_Z8PrintFoov:
.quad _Z23__device_stub__PrintFoov
.size _Z8PrintFoov, 8
.type _Z8PrintBarPKij,@object # @_Z8PrintBarPKij
.globl _Z8PrintBarPKij
.p2align 3, 0x0
_Z8PrintBarPKij:
.quad _Z23__device_stub__PrintBarPKij
.size _Z8PrintBarPKij, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "==== Sample 13 - Managed Memory ====\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nCUDA device does "
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "NOT "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.zero 1
.size .L.str.3, 1
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "support concurrent access\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "mBar CPU: "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ", "
.size .L.str.7, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8PrintFoov"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8PrintBarPKij"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mFoo"
.size .L__unnamed_3, 5
.type mFoo,@object # @mFoo
.local mFoo
.comm mFoo,8,8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__PrintFoov
.addrsig_sym _Z23__device_stub__PrintBarPKij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mFoo.managed
.addrsig_sym _Z8PrintFoov
.addrsig_sym _Z8PrintBarPKij
.addrsig_sym _ZSt4cout
.addrsig_sym mFoo
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00085103_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL20__nv_init_managed_rtv, @function
_ZL20__nv_init_managed_rtv:
.LFB1:
.cfi_startproc
movzbl _ZL22__nv_inited_managed_rt(%rip), %eax
testb %al, %al
je .L7
movb %al, _ZL22__nv_inited_managed_rt(%rip)
ret
.L7:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE1:
.size _ZL20__nv_init_managed_rtv, .-_ZL20__nv_init_managed_rtv
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8PrintFoovv
.type _Z26__device_stub__Z8PrintFoovv, @function
_Z26__device_stub__Z8PrintFoovv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8PrintFoov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z8PrintFoovv, .-_Z26__device_stub__Z8PrintFoovv
.globl _Z8PrintFoov
.type _Z8PrintFoov, @function
_Z8PrintFoov:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8PrintFoovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8PrintFoov, .-_Z8PrintFoov
.globl _Z29__device_stub__Z8PrintBarPKijPKij
.type _Z29__device_stub__Z8PrintBarPKijPKij, @function
_Z29__device_stub__Z8PrintBarPKijPKij:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8PrintBarPKij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z29__device_stub__Z8PrintBarPKijPKij, .-_Z29__device_stub__Z8PrintBarPKijPKij
.globl _Z8PrintBarPKij
.type _Z8PrintBarPKij, @function
_Z8PrintBarPKij:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8PrintBarPKijPKij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8PrintBarPKij, .-_Z8PrintBarPKij
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "NOT "
.LC1:
.string ""
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "==== Sample 13 - Managed Memory ====\n"
.section .rodata.str1.1
.LC3:
.string "\nCUDA device does "
.LC4:
.string "support concurrent access\n"
.LC5:
.string "mBar CPU: "
.LC6:
.string "\n"
.LC7:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L46
.L27:
movq _ZL4mFoo(%rip), %rax
movl $14, (%rax)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L28:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $56, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L29:
movq 16(%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $14, %rax
jne .L29
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 48(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
cmpl $0, 724(%rsp)
leaq .LC1(%rip), %rsi
leaq .LC0(%rip), %rax
cmove %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 724(%rsp)
jne .L48
.L31:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L32:
cmpl $0, 724(%rsp)
jne .L50
.L33:
call cudaDeviceSynchronize@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC7(%rip), %r12
leaq .LC6(%rip), %r13
jmp .L36
.L46:
call _ZL20__nv_init_managed_rtv
jmp .L27
.L47:
call _Z26__device_stub__Z8PrintFoovv
jmp .L28
.L48:
movl $0, %ecx
movl 12(%rsp), %edx
movl $56, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
jmp .L31
.L49:
movl $14, %esi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z8PrintBarPKijPKij
jmp .L32
.L50:
movl $0, %ecx
movl $-1, %edx
movl $56, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
jmp .L33
.L52:
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $14, %rbx
je .L51
.L36:
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
cmpl $13, %ebx
je .L52
movl $2, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
jmp .L36
.L51:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L53
.L37:
movq _ZL4mFoo(%rip), %rax
movl $42, (%rax)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L38:
cmpl $0, 724(%rsp)
je .L55
.L39:
movq 16(%rsp), %rax
movl $20, (%rax)
call cudaDeviceSynchronize@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
call _ZL20__nv_init_managed_rtv
jmp .L37
.L54:
call _Z26__device_stub__Z8PrintFoovv
jmp .L38
.L55:
call cudaDeviceSynchronize@PLT
jmp .L39
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z8PrintBarPKij"
.LC9:
.string "_Z8PrintFoov"
.LC10:
.string "mFoo"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8PrintBarPKij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8PrintFoov(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4mFoo(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL4mFoo, @object
.size _ZL4mFoo, 8
_ZL4mFoo:
.zero 8
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__PrintFoov # -- Begin function _Z23__device_stub__PrintFoov
.p2align 4, 0x90
.type _Z23__device_stub__PrintFoov,@function
_Z23__device_stub__PrintFoov: # @_Z23__device_stub__PrintFoov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8PrintFoov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__PrintFoov, .Lfunc_end0-_Z23__device_stub__PrintFoov
.cfi_endproc
# -- End function
.globl _Z23__device_stub__PrintBarPKij # -- Begin function _Z23__device_stub__PrintBarPKij
.p2align 4, 0x90
.type _Z23__device_stub__PrintBarPKij,@function
_Z23__device_stub__PrintBarPKij: # @_Z23__device_stub__PrintBarPKij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8PrintBarPKij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__PrintBarPKij, .Lfunc_end1-_Z23__device_stub__PrintBarPKij
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1616
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $37, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movabsq $4294967297, %rbx # imm = 0x100000001
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq mFoo(%rip), %rax
movl $14, (%rax)
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
leaq 112(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z8PrintFoov, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
movq %rsp, %rdi
movl $56, %esi
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $14, %rax
jne .LBB2_7
# %bb.8:
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 112(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %edx, %edx
cmpl $0, 788(%rsp)
sete %dl
movl $.L.str.2, %eax
movl $.L.str.3, %esi
cmoveq %rax, %rsi
shll $2, %edx
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 788(%rsp)
je .LBB2_10
# %bb.9:
movq (%rsp), %rdi
movl 12(%rsp), %edx
movl $56, %esi
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.LBB2_10:
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq (%rsp), %rax
movq %rax, 32(%rsp)
movl $14, 92(%rsp)
leaq 32(%rsp), %rax
movq %rax, 64(%rsp)
leaq 92(%rsp), %rax
movq %rax, 72(%rsp)
leaq 16(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8PrintBarPKij, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
cmpl $0, 788(%rsp)
je .LBB2_14
# %bb.13:
movq (%rsp), %rdi
movl $56, %esi
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
.LBB2_14:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq $-14, %r14
movl $.L.str.6, %r15d
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl 56(%rax,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
xorl %edx, %edx
incq %r14
movl $.L.str.7, %esi
cmoveq %r15, %rsi
setne %dl
incq %rdx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testq %r14, %r14
jne .LBB2_15
# %bb.16:
movq mFoo(%rip), %rax
movl $42, (%rax)
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_17
# %bb.18:
cmpl $0, 788(%rsp)
je .LBB2_19
.LBB2_20:
movq (%rsp), %rax
movl $20, (%rax)
callq hipDeviceSynchronize
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 1616
leaq 64(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8PrintFoov, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $0, 788(%rsp)
jne .LBB2_20
.LBB2_19:
callq hipDeviceSynchronize
jmp .LBB2_20
.LBB2_21:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8PrintFoov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8PrintBarPKij, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $mFoo, %esi
movl $mFoo.managed, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r8d
movq %rbx, %rdi
movl $4, %r9d
callq __hipRegisterManagedVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type mFoo.managed,@object # @mFoo.managed
.local mFoo.managed
.comm mFoo.managed,4,4
.type _Z8PrintFoov,@object # @_Z8PrintFoov
.section .rodata,"a",@progbits
.globl _Z8PrintFoov
.p2align 3, 0x0
_Z8PrintFoov:
.quad _Z23__device_stub__PrintFoov
.size _Z8PrintFoov, 8
.type _Z8PrintBarPKij,@object # @_Z8PrintBarPKij
.globl _Z8PrintBarPKij
.p2align 3, 0x0
_Z8PrintBarPKij:
.quad _Z23__device_stub__PrintBarPKij
.size _Z8PrintBarPKij, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "==== Sample 13 - Managed Memory ====\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nCUDA device does "
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "NOT "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.zero 1
.size .L.str.3, 1
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "support concurrent access\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "mBar CPU: "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ", "
.size .L.str.7, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8PrintFoov"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8PrintBarPKij"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mFoo"
.size .L__unnamed_3, 5
.type mFoo,@object # @mFoo
.local mFoo
.comm mFoo,8,8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__PrintFoov
.addrsig_sym _Z23__device_stub__PrintBarPKij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mFoo.managed
.addrsig_sym _Z8PrintFoov
.addrsig_sym _Z8PrintBarPKij
.addrsig_sym _ZSt4cout
.addrsig_sym mFoo
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ void clock_block(int kernel_time, int clockRate)
{
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
}
__global__ void superKernel(volatile int *init, int numThreads, int *result)
{
// init and result are arrays of integers where result should end up
// being the result of incrementing all elements of init.
// They have n elements and are (n+1) long. The should wait for the
// first element to be set to zero
int warp_size = 32;
int threadID = (threadIdx.x + threadIdx.y * blockDim.x)%warp_size;
int warpID = (threadIdx.x + threadIdx.y * blockDim.x)/warp_size;
//clock_block(10,706000000);
int count = 1;
while(init[0]==0) count++;
if(threadID<numThreads && warpID==0) result[threadID+1] = count;
//__syncthreads(); //this will need to be a warp wide sync using (PTX barriers)
if(threadID==0) result[0] = count;
} | code for sm_80
Function : _Z11superKernelPViiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fc80000000f00 */
/*0080*/ LOP3.LUT R4, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00047812 */
/* 0x000fe400078ec0ff */
/*0090*/ LDG.E.STRONG.SYS R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea2000c1f5900 */
/*00a0*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fe2000f8e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*00d0*/ @!P0 BRA 0x90 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*00e0*/ LOP3.LUT P0, RZ, R0, 0xffffffe0, RZ, 0xc0, !PT ; /* 0xffffffe000ff7812 */
/* 0x000fe4000780c0ff */
/*00f0*/ ISETP.NE.AND P1, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe40003f25270 */
/*0100*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x168], P0 ; /* 0x00005a0004007a0c */
/* 0x000fda0000706670 */
/*0110*/ @!P0 IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104028810 */
/* 0x000fe40007ffe0ff */
/*0120*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fca0000000f00 */
/*0130*/ @!P0 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002028625 */
/* 0x000fca00078e0003 */
/*0140*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e2000c101906 */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x001fe200078e00ff */
/*0170*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ void clock_block(int kernel_time, int clockRate)
{
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
}
__global__ void superKernel(volatile int *init, int numThreads, int *result)
{
// init and result are arrays of integers where result should end up
// being the result of incrementing all elements of init.
// They have n elements and are (n+1) long. The should wait for the
// first element to be set to zero
int warp_size = 32;
int threadID = (threadIdx.x + threadIdx.y * blockDim.x)%warp_size;
int warpID = (threadIdx.x + threadIdx.y * blockDim.x)/warp_size;
//clock_block(10,706000000);
int count = 1;
while(init[0]==0) count++;
if(threadID<numThreads && warpID==0) result[threadID+1] = count;
//__syncthreads(); //this will need to be a warp wide sync using (PTX barriers)
if(threadID==0) result[0] = count;
} | .file "tmpxft_00100040_00000000-6_incSuperKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11clock_blockii
.type _Z11clock_blockii, @function
_Z11clock_blockii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11clock_blockii, .-_Z11clock_blockii
.globl _Z35__device_stub__Z11superKernelPViiPiPViiPi
.type _Z35__device_stub__Z11superKernelPViiPiPViiPi, @function
_Z35__device_stub__Z11superKernelPViiPiPViiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11superKernelPViiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z11superKernelPViiPiPViiPi, .-_Z35__device_stub__Z11superKernelPViiPiPViiPi
.globl _Z11superKernelPViiPi
.type _Z11superKernelPViiPi, @function
_Z11superKernelPViiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11superKernelPViiPiPViiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11superKernelPViiPi, .-_Z11superKernelPViiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11superKernelPViiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11superKernelPViiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ void clock_block(int kernel_time, int clockRate)
{
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
}
__global__ void superKernel(volatile int *init, int numThreads, int *result)
{
// init and result are arrays of integers where result should end up
// being the result of incrementing all elements of init.
// They have n elements and are (n+1) long. The should wait for the
// first element to be set to zero
int warp_size = 32;
int threadID = (threadIdx.x + threadIdx.y * blockDim.x)%warp_size;
int warpID = (threadIdx.x + threadIdx.y * blockDim.x)/warp_size;
//clock_block(10,706000000);
int count = 1;
while(init[0]==0) count++;
if(threadID<numThreads && warpID==0) result[threadID+1] = count;
//__syncthreads(); //this will need to be a warp wide sync using (PTX barriers)
if(threadID==0) result[0] = count;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void clock_block(int kernel_time, int clockRate)
{
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
}
__global__ void superKernel(volatile int *init, int numThreads, int *result)
{
// init and result are arrays of integers where result should end up
// being the result of incrementing all elements of init.
// They have n elements and are (n+1) long. The should wait for the
// first element to be set to zero
int warp_size = 32;
int threadID = (threadIdx.x + threadIdx.y * blockDim.x)%warp_size;
int warpID = (threadIdx.x + threadIdx.y * blockDim.x)/warp_size;
//clock_block(10,706000000);
int count = 1;
while(init[0]==0) count++;
if(threadID<numThreads && warpID==0) result[threadID+1] = count;
//__syncthreads(); //this will need to be a warp wide sync using (PTX barriers)
if(threadID==0) result[0] = count;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void clock_block(int kernel_time, int clockRate)
{
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
}
__global__ void superKernel(volatile int *init, int numThreads, int *result)
{
// init and result are arrays of integers where result should end up
// being the result of incrementing all elements of init.
// They have n elements and are (n+1) long. The should wait for the
// first element to be set to zero
int warp_size = 32;
int threadID = (threadIdx.x + threadIdx.y * blockDim.x)%warp_size;
int warpID = (threadIdx.x + threadIdx.y * blockDim.x)/warp_size;
//clock_block(10,706000000);
int count = 1;
while(init[0]==0) count++;
if(threadID<numThreads && warpID==0) result[threadID+1] = count;
//__syncthreads(); //this will need to be a warp wide sync using (PTX barriers)
if(threadID==0) result[0] = count;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11superKernelPViiPi
.globl _Z11superKernelPViiPi
.p2align 8
.type _Z11superKernelPViiPi,@function
_Z11superKernelPViiPi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
s_mov_b32 s2, 0
s_mov_b32 s3, 0
.LBB0_1:
flat_load_b32 v3, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_mov_b32_e32 v3, s3
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_and_b32 s0, 0xffff, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v1, v0, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 31, v1
v_cmp_gt_u32_e64 s0, 32, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v1, 2, v0
global_store_b32 v1, v3, s[2:3] offset:4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
global_store_b32 v0, v3, s[2:3]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11superKernelPViiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11superKernelPViiPi, .Lfunc_end0-_Z11superKernelPViiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11superKernelPViiPi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11superKernelPViiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void clock_block(int kernel_time, int clockRate)
{
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
}
__global__ void superKernel(volatile int *init, int numThreads, int *result)
{
// init and result are arrays of integers where result should end up
// being the result of incrementing all elements of init.
// They have n elements and are (n+1) long. The should wait for the
// first element to be set to zero
int warp_size = 32;
int threadID = (threadIdx.x + threadIdx.y * blockDim.x)%warp_size;
int warpID = (threadIdx.x + threadIdx.y * blockDim.x)/warp_size;
//clock_block(10,706000000);
int count = 1;
while(init[0]==0) count++;
if(threadID<numThreads && warpID==0) result[threadID+1] = count;
//__syncthreads(); //this will need to be a warp wide sync using (PTX barriers)
if(threadID==0) result[0] = count;
} | .text
.file "incSuperKernel.hip"
.globl _Z26__device_stub__superKernelPViiPi # -- Begin function _Z26__device_stub__superKernelPViiPi
.p2align 4, 0x90
.type _Z26__device_stub__superKernelPViiPi,@function
_Z26__device_stub__superKernelPViiPi: # @_Z26__device_stub__superKernelPViiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11superKernelPViiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__superKernelPViiPi, .Lfunc_end0-_Z26__device_stub__superKernelPViiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11superKernelPViiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11superKernelPViiPi,@object # @_Z11superKernelPViiPi
.section .rodata,"a",@progbits
.globl _Z11superKernelPViiPi
.p2align 3, 0x0
_Z11superKernelPViiPi:
.quad _Z26__device_stub__superKernelPViiPi
.size _Z11superKernelPViiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11superKernelPViiPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__superKernelPViiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11superKernelPViiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11superKernelPViiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fc80000000f00 */
/*0080*/ LOP3.LUT R4, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00047812 */
/* 0x000fe400078ec0ff */
/*0090*/ LDG.E.STRONG.SYS R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea2000c1f5900 */
/*00a0*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fe2000f8e00ff */
/*00b0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*00c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*00d0*/ @!P0 BRA 0x90 ; /* 0xffffffb000008947 */
/* 0x000fea000383ffff */
/*00e0*/ LOP3.LUT P0, RZ, R0, 0xffffffe0, RZ, 0xc0, !PT ; /* 0xffffffe000ff7812 */
/* 0x000fe4000780c0ff */
/*00f0*/ ISETP.NE.AND P1, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe40003f25270 */
/*0100*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x168], P0 ; /* 0x00005a0004007a0c */
/* 0x000fda0000706670 */
/*0110*/ @!P0 IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104028810 */
/* 0x000fe40007ffe0ff */
/*0120*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fca0000000f00 */
/*0130*/ @!P0 IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002028625 */
/* 0x000fca00078e0003 */
/*0140*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e2000c101906 */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x001fe200078e00ff */
/*0170*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fca0000000f00 */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11superKernelPViiPi
.globl _Z11superKernelPViiPi
.p2align 8
.type _Z11superKernelPViiPi,@function
_Z11superKernelPViiPi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
s_mov_b32 s2, 0
s_mov_b32 s3, 0
.LBB0_1:
flat_load_b32 v3, v[1:2] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
v_mov_b32_e32 v3, s3
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_and_b32 s0, 0xffff, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v1, v0, s0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_and_b32_e32 v0, 31, v1
v_cmp_gt_u32_e64 s0, 32, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s0, vcc_lo
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v1, 2, v0
global_store_b32 v1, v3, s[2:3] offset:4
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
global_store_b32 v0, v3, s[2:3]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11superKernelPViiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11superKernelPViiPi, .Lfunc_end0-_Z11superKernelPViiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11superKernelPViiPi
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11superKernelPViiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00100040_00000000-6_incSuperKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11clock_blockii
.type _Z11clock_blockii, @function
_Z11clock_blockii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z11clock_blockii, .-_Z11clock_blockii
.globl _Z35__device_stub__Z11superKernelPViiPiPViiPi
.type _Z35__device_stub__Z11superKernelPViiPiPViiPi, @function
_Z35__device_stub__Z11superKernelPViiPiPViiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11superKernelPViiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z11superKernelPViiPiPViiPi, .-_Z35__device_stub__Z11superKernelPViiPiPViiPi
.globl _Z11superKernelPViiPi
.type _Z11superKernelPViiPi, @function
_Z11superKernelPViiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11superKernelPViiPiPViiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11superKernelPViiPi, .-_Z11superKernelPViiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11superKernelPViiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11superKernelPViiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "incSuperKernel.hip"
.globl _Z26__device_stub__superKernelPViiPi # -- Begin function _Z26__device_stub__superKernelPViiPi
.p2align 4, 0x90
.type _Z26__device_stub__superKernelPViiPi,@function
_Z26__device_stub__superKernelPViiPi: # @_Z26__device_stub__superKernelPViiPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11superKernelPViiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__superKernelPViiPi, .Lfunc_end0-_Z26__device_stub__superKernelPViiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11superKernelPViiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11superKernelPViiPi,@object # @_Z11superKernelPViiPi
.section .rodata,"a",@progbits
.globl _Z11superKernelPViiPi
.p2align 3, 0x0
_Z11superKernelPViiPi:
.quad _Z26__device_stub__superKernelPViiPi
.size _Z11superKernelPViiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11superKernelPViiPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__superKernelPViiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11superKernelPViiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void index_checker(int *gpu)
{
int index = blockIdx.x*blockDim.x+threadIdx.x;
int value = blockIdx.x*10+threadIdx.x;
gpu[index]=value;
printf("%d, %d, blockIdx=%d, blockDim=%d, threadIdx=%d\n", index, value, blockIdx.x, blockDim.x, threadIdx.x);
return;
}
int main(int argc, char* argv[])
{
int N=20, size=sizeof(int)*N;
int *cpu, *gpu, *cpu_from_gpu;
cpu = (int *)malloc(size);
cpu_from_gpu = (int *)malloc(size);
memset(cpu_from_gpu,0.0,size);
int i,j;
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
int position = j * 10 + i;
int pos = j * 4 + i;
cpu[pos] = position;
printf(",%d", cpu[pos]);
}
printf("\n");
}
cudaMalloc( (void **)&gpu, size);
cudaMemset(gpu, 0.0, size);
dim3 bs(5,1,1);
dim3 ts(4,1,1);
index_checker <<< bs,ts >>> (gpu);
cudaMemcpy(cpu_from_gpu, gpu, size, cudaMemcpyDeviceToHost);
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
printf(",%d", cpu_from_gpu[j*4+i]);
}
printf("\n");
}
cudaFree(gpu);
free(cpu);
free(cpu_from_gpu);
return 0;
} | code for sm_80
Function : _Z13index_checkerPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e620000002500 */
/*0060*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00a0*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0004e20000000a00 */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00d0*/ STL [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0015e20000100800 */
/*00e0*/ IMAD R2, R14, c[0x0][0x0], R12 ; /* 0x000000000e027a24 */
/* 0x002fc600078e020c */
/*00f0*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x0005e20000100a00 */
/*0100*/ IMAD R3, R14, 0xa, R12 ; /* 0x0000000a0e037824 */
/* 0x000fe400078e020c */
/*0110*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fc600078e0209 */
/*0120*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0005e80000100a00 */
/*0130*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0005e4000c101904 */
/*0140*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x00cfe40000000000 */
/*0150*/ MOV R9, 0x1c0 ; /* 0x000001c000097802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01a0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01b0*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void index_checker(int *gpu)
{
int index = blockIdx.x*blockDim.x+threadIdx.x;
int value = blockIdx.x*10+threadIdx.x;
gpu[index]=value;
printf("%d, %d, blockIdx=%d, blockDim=%d, threadIdx=%d\n", index, value, blockIdx.x, blockDim.x, threadIdx.x);
return;
}
int main(int argc, char* argv[])
{
int N=20, size=sizeof(int)*N;
int *cpu, *gpu, *cpu_from_gpu;
cpu = (int *)malloc(size);
cpu_from_gpu = (int *)malloc(size);
memset(cpu_from_gpu,0.0,size);
int i,j;
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
int position = j * 10 + i;
int pos = j * 4 + i;
cpu[pos] = position;
printf(",%d", cpu[pos]);
}
printf("\n");
}
cudaMalloc( (void **)&gpu, size);
cudaMemset(gpu, 0.0, size);
dim3 bs(5,1,1);
dim3 ts(4,1,1);
index_checker <<< bs,ts >>> (gpu);
cudaMemcpy(cpu_from_gpu, gpu, size, cudaMemcpyDeviceToHost);
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
printf(",%d", cpu_from_gpu[j*4+i]);
}
printf("\n");
}
cudaFree(gpu);
free(cpu);
free(cpu_from_gpu);
return 0;
} | .file "tmpxft_000b4c69_00000000-6_cuda_index_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z13index_checkerPiPi
.type _Z33__device_stub__Z13index_checkerPiPi, @function
_Z33__device_stub__Z13index_checkerPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13index_checkerPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z13index_checkerPiPi, .-_Z33__device_stub__Z13index_checkerPiPi
.globl _Z13index_checkerPi
.type _Z13index_checkerPi, @function
_Z13index_checkerPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13index_checkerPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13index_checkerPi, .-_Z13index_checkerPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ",%d"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, %r13
pxor %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L12
.L23:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $10, %ebp
addq $16, %r12
cmpl $50, %ebp
je .L14
.L12:
movl $0, %ebx
.L13:
leal 0(%rbp,%rbx), %edx
movl %edx, (%r12,%rbx,4)
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L13
jmp .L23
.L14:
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $80, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $5, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 16(%r13), %rbp
leaq 96(%r13), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
jmp .L16
.L24:
movq 24(%rsp), %rdi
call _Z33__device_stub__Z13index_checkerPiPi
jmp .L15
.L25:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r15, %rbp
je .L18
.L16:
leaq -16(%rbp), %rbx
.L17:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
jmp .L25
.L18:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13index_checkerPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13index_checkerPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void index_checker(int *gpu)
{
int index = blockIdx.x*blockDim.x+threadIdx.x;
int value = blockIdx.x*10+threadIdx.x;
gpu[index]=value;
printf("%d, %d, blockIdx=%d, blockDim=%d, threadIdx=%d\n", index, value, blockIdx.x, blockDim.x, threadIdx.x);
return;
}
int main(int argc, char* argv[])
{
int N=20, size=sizeof(int)*N;
int *cpu, *gpu, *cpu_from_gpu;
cpu = (int *)malloc(size);
cpu_from_gpu = (int *)malloc(size);
memset(cpu_from_gpu,0.0,size);
int i,j;
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
int position = j * 10 + i;
int pos = j * 4 + i;
cpu[pos] = position;
printf(",%d", cpu[pos]);
}
printf("\n");
}
cudaMalloc( (void **)&gpu, size);
cudaMemset(gpu, 0.0, size);
dim3 bs(5,1,1);
dim3 ts(4,1,1);
index_checker <<< bs,ts >>> (gpu);
cudaMemcpy(cpu_from_gpu, gpu, size, cudaMemcpyDeviceToHost);
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
printf(",%d", cpu_from_gpu[j*4+i]);
}
printf("\n");
}
cudaFree(gpu);
free(cpu);
free(cpu_from_gpu);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void index_checker(int *gpu)
{
int index = blockIdx.x*blockDim.x+threadIdx.x;
int value = blockIdx.x*10+threadIdx.x;
gpu[index]=value;
printf("%d, %d, blockIdx=%d, blockDim=%d, threadIdx=%d\n", index, value, blockIdx.x, blockDim.x, threadIdx.x);
return;
}
int main(int argc, char* argv[])
{
int N=20, size=sizeof(int)*N;
int *cpu, *gpu, *cpu_from_gpu;
cpu = (int *)malloc(size);
cpu_from_gpu = (int *)malloc(size);
memset(cpu_from_gpu,0.0,size);
int i,j;
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
int position = j * 10 + i;
int pos = j * 4 + i;
cpu[pos] = position;
printf(",%d", cpu[pos]);
}
printf("\n");
}
hipMalloc( (void **)&gpu, size);
hipMemset(gpu, 0.0, size);
dim3 bs(5,1,1);
dim3 ts(4,1,1);
index_checker <<< bs,ts >>> (gpu);
hipMemcpy(cpu_from_gpu, gpu, size, hipMemcpyDeviceToHost);
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
printf(",%d", cpu_from_gpu[j*4+i]);
}
printf("\n");
}
hipFree(gpu);
free(cpu);
free(cpu_from_gpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void index_checker(int *gpu)
{
int index = blockIdx.x*blockDim.x+threadIdx.x;
int value = blockIdx.x*10+threadIdx.x;
gpu[index]=value;
printf("%d, %d, blockIdx=%d, blockDim=%d, threadIdx=%d\n", index, value, blockIdx.x, blockDim.x, threadIdx.x);
return;
}
int main(int argc, char* argv[])
{
int N=20, size=sizeof(int)*N;
int *cpu, *gpu, *cpu_from_gpu;
cpu = (int *)malloc(size);
cpu_from_gpu = (int *)malloc(size);
memset(cpu_from_gpu,0.0,size);
int i,j;
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
int position = j * 10 + i;
int pos = j * 4 + i;
cpu[pos] = position;
printf(",%d", cpu[pos]);
}
printf("\n");
}
hipMalloc( (void **)&gpu, size);
hipMemset(gpu, 0.0, size);
dim3 bs(5,1,1);
dim3 ts(4,1,1);
index_checker <<< bs,ts >>> (gpu);
hipMemcpy(cpu_from_gpu, gpu, size, hipMemcpyDeviceToHost);
for(j=0;j<5;j++)
{
for(i=0;i<4;i++)
{
printf(",%d", cpu_from_gpu[j*4+i]);
}
printf("\n");
}
hipFree(gpu);
free(cpu);
free(cpu_from_gpu);
return 0;
} | .text
.file "cuda_index_test.hip"
.globl _Z28__device_stub__index_checkerPi # -- Begin function _Z28__device_stub__index_checkerPi
.p2align 4, 0x90
.type _Z28__device_stub__index_checkerPi,@function
_Z28__device_stub__index_checkerPi: # @_Z28__device_stub__index_checkerPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13index_checkerPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__index_checkerPi, .Lfunc_end0-_Z28__device_stub__index_checkerPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %r14d, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # %.preheader41
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incl %r15d
cmpl $4, %r15d
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
addl $10, %r14d
cmpl $5, %ebp
jne .LBB1_1
# %bb.4:
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $80, %edx
xorl %esi, %esi
callq hipMemset
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13index_checkerPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $80, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $4, %r12
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $16, %r14
cmpq $5, %r15
jne .LBB1_7
# %bb.10:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13index_checkerPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13index_checkerPi,@object # @_Z13index_checkerPi
.section .rodata,"a",@progbits
.globl _Z13index_checkerPi
.p2align 3, 0x0
_Z13index_checkerPi:
.quad _Z28__device_stub__index_checkerPi
.size _Z13index_checkerPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ",%d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13index_checkerPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__index_checkerPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13index_checkerPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b4c69_00000000-6_cuda_index_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z13index_checkerPiPi
.type _Z33__device_stub__Z13index_checkerPiPi, @function
_Z33__device_stub__Z13index_checkerPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13index_checkerPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z13index_checkerPiPi, .-_Z33__device_stub__Z13index_checkerPiPi
.globl _Z13index_checkerPi
.type _Z13index_checkerPi, @function
_Z13index_checkerPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13index_checkerPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13index_checkerPi, .-_Z13index_checkerPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ",%d"
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movl $80, %edi
call malloc@PLT
movq %rax, %r13
pxor %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L12
.L23:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $10, %ebp
addq $16, %r12
cmpl $50, %ebp
je .L14
.L12:
movl $0, %ebx
.L13:
leal 0(%rbp,%rbx), %edx
movl %edx, (%r12,%rbx,4)
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
jne .L13
jmp .L23
.L14:
leaq 24(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
movl $80, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
movl $5, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
movl $2, %ecx
movl $80, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq 16(%r13), %rbp
leaq 96(%r13), %r15
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
jmp .L16
.L24:
movq 24(%rsp), %rdi
call _Z33__device_stub__Z13index_checkerPiPi
jmp .L15
.L25:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq %r15, %rbp
je .L18
.L16:
leaq -16(%rbp), %rbx
.L17:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
jmp .L25
.L18:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13index_checkerPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13index_checkerPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_index_test.hip"
.globl _Z28__device_stub__index_checkerPi # -- Begin function _Z28__device_stub__index_checkerPi
.p2align 4, 0x90
.type _Z28__device_stub__index_checkerPi,@function
_Z28__device_stub__index_checkerPi: # @_Z28__device_stub__index_checkerPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13index_checkerPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__index_checkerPi, .Lfunc_end0-_Z28__device_stub__index_checkerPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $80, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
xorl %r14d, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # %.preheader41
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incl %r15d
cmpl $4, %r15d
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
addl $10, %r14d
cmpl $5, %ebp
jne .LBB1_1
# %bb.4:
leaq 8(%rsp), %rdi
movl $80, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $80, %edx
xorl %esi, %esi
callq hipMemset
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 1(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13index_checkerPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $80, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $4, %r12
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $16, %r14
cmpq $5, %r15
jne .LBB1_7
# %bb.10:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13index_checkerPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13index_checkerPi,@object # @_Z13index_checkerPi
.section .rodata,"a",@progbits
.globl _Z13index_checkerPi
.p2align 3, 0x0
_Z13index_checkerPi:
.quad _Z28__device_stub__index_checkerPi
.size _Z13index_checkerPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ",%d"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13index_checkerPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__index_checkerPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13index_checkerPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kBoundingBoxLogisticGrad( float* mat, int* bbox, int* label, int* seg, float* indices, float* width_offset, float* height_offset, int size, int width, int height, int depth, float scale_width, float scale_height, float* grad) {
const int color = blockIdx.z;
/*
const int numXBlocksPerImage = DIVUP(width, blockDim.x);
const int image_id = blockIdx.x / numXBlocksPerImage;
const int col = (blockIdx.x % numXBlocksPerImage) * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
*/
const int image_id = threadIdx.x;
const int col = blockIdx.x;
const int row = blockIdx.y;
int num_bboxes = 0, num_bboxes_of_this_depth = 0, num_bboxes_of_this_depth_inside = 0;
if (col < width && row < height && image_id < size && color < depth) {
int src_image_id = (int)indices[image_id];
int src_col = (int)(scale_width * col);
int src_row = (int)(scale_height * row);
int start = seg[src_image_id];
int end = seg[src_image_id + 1];
int x1, y1, x2, y2, l, inside;
for (int box_id = start; box_id < end; box_id++) {
l = label[box_id];
x1 = bbox[box_id << 2] - width_offset[image_id];
y1 = bbox[(box_id << 2) + 1] - height_offset[image_id];
x2 = bbox[(box_id << 2) + 2] - width_offset[image_id];
y2 = bbox[(box_id << 2) + 3] - height_offset[image_id];
inside = (src_col >= x1 && src_col <= x2 && src_row >= y1 && src_row <= y2) ? 1:0;
num_bboxes += inside;
num_bboxes_of_this_depth += (l == color) ? 1: 0;
num_bboxes_of_this_depth_inside += (inside == 1 && l == color) ? 1: 0;
}
}
unsigned long i = image_id + size * (col + width * (row + height * color));
__syncthreads();
if (col < width && row < height && image_id < size && color < depth) {
if (num_bboxes > 0) {
grad[i] = (num_bboxes_of_this_depth_inside > 0) ? (mat[i] - 1) : 0;
} else {
grad[i] = (num_bboxes_of_this_depth > 0) ? mat[i] : 0;
}
}
} | code for sm_80
Function : _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xe30 ; /* 0x00000df000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e620000002500 */
/*0060*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fc6000001ff00 */
/*0070*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea80000002100 */
/*0080*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ee20000002700 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x1a0], PT ; /* 0x0000680000007a0c */
/* 0x001fc80003f06270 */
/*00a0*/ ISETP.LT.AND P0, PT, R6, c[0x0][0x19c], !P0 ; /* 0x0000670006007a0c */
/* 0x002fc80004701270 */
/*00b0*/ ISETP.LT.AND P0, PT, R7, c[0x0][0x198], P0 ; /* 0x0000660007007a0c */
/* 0x004fc80000701270 */
/*00c0*/ ISETP.LT.AND P0, PT, R9, c[0x0][0x1a4], P0 ; /* 0x0000690009007a0c */
/* 0x008fda0000701270 */
/*00d0*/ @!P0 BRA 0xe20 ; /* 0x00000d4000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.WIDE R2, R7, R8, c[0x0][0x180] ; /* 0x0000600007027625 */
/* 0x000fcc00078e0208 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0110*/ F2I.TRUNC.NTZ R5, R2 ; /* 0x0000000200057305 */
/* 0x004e24000020f100 */
/*0120*/ IMAD.WIDE R4, R5, R8, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x001fca00078e0208 */
/*0130*/ LDG.E R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea4000c1e1900 */
/*0150*/ ISETP.GT.AND P1, PT, R16, R15, PT ; /* 0x0000000f1000720c */
/* 0x004fda0003f24270 */
/*0160*/ @!P1 BRA 0xe20 ; /* 0x00000cb000009947 */
/* 0x000fea0003800000 */
/*0170*/ SHF.R.S32.HI R2, RZ, 0x1f, R7 ; /* 0x0000001fff027819 */
/* 0x000fe20000011407 */
/*0180*/ IMAD.SHL.U32 R4, R7, 0x4, RZ ; /* 0x0000000407047824 */
/* 0x000fc600078e00ff */
/*0190*/ SHF.L.U64.HI R5, R7, 0x2, R2 ; /* 0x0000000207057819 */
/* 0x000fe40000010202 */
/*01a0*/ IADD3 R2, P1, R4.reuse, c[0x0][0x188], RZ ; /* 0x0000620004027a10 */
/* 0x040fe40007f3e0ff */
/*01b0*/ IADD3 R4, P2, R4, c[0x0][0x190], RZ ; /* 0x0000640004047a10 */
/* 0x000fe40007f5e0ff */
/*01c0*/ IADD3.X R3, R5.reuse, c[0x0][0x18c], RZ, P1, !PT ; /* 0x0000630005037a10 */
/* 0x040fe40000ffe4ff */
/*01d0*/ IADD3.X R5, R5, c[0x0][0x194], RZ, P2, !PT ; /* 0x0000650005057a10 */
/* 0x000fc600017fe4ff */
/*01e0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000168000c1e1900 */
/*01f0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000162000c1e1900 */
/*0200*/ I2F R12, R6 ; /* 0x00000006000c7306 */
/* 0x000e620000201400 */
/*0210*/ LOP3.LUT R17, RZ, R15, RZ, 0x33, !PT ; /* 0x0000000fff117212 */
/* 0x000fe200078e33ff */
/*0220*/ IMAD.IADD R18, R16.reuse, 0x1, -R15 ; /* 0x0000000110127824 */
/* 0x040fe200078e0a0f */
/*0230*/ BSSY B1, 0xb40 ; /* 0x0000090000017945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.IADD R17, R16, 0x1, R17 ; /* 0x0000000110117824 */
/* 0x000fc400078e0211 */
/*0260*/ I2F R14, R0 ; /* 0x00000000000e7306 */
/* 0x000ea60000201400 */
/*0270*/ ISETP.GE.U32.AND P1, PT, R17, 0x3, PT ; /* 0x000000031100780c */
/* 0x000fe20003f26070 */
/*0280*/ FMUL R13, R12, c[0x0][0x1a8] ; /* 0x00006a000c0d7a20 */
/* 0x002fe20000400000 */
/*0290*/ LOP3.LUT R12, R18, 0x3, RZ, 0xc0, !PT ; /* 0x00000003120c7812 */
/* 0x000fe400078ec0ff */
/*02a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*02b0*/ ISETP.NE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f65270 */
/*02c0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e62000020f100 */
/*02d0*/ FMUL R14, R14, c[0x0][0x1ac] ; /* 0x00006b000e0e7a20 */
/* 0x004fce0000400000 */
/*02e0*/ F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e7305 */
/* 0x000ea2000020f100 */
/*02f0*/ @!P1 BRA 0xb30 ; /* 0x0000083000009947 */
/* 0x000fea0003800000 */
/*0300*/ IMAD.WIDE R2, R15.reuse, R8, c[0x0][0x170] ; /* 0x00005c000f027625 */
/* 0x041fe200078e0208 */
/*0310*/ LEA R27, R15, 0xc, 0x2 ; /* 0x0000000c0f1b7811 */
/* 0x000fc600078e10ff */
/*0320*/ IMAD.IADD R16, R12, 0x1, -R16 ; /* 0x000000010c107824 */
/* 0x000fe200078e0a10 */
/*0330*/ IADD3 R4, P1, R2, 0x8, RZ ; /* 0x0000000802047810 */
/* 0x000fe20007f3e0ff */
/*0340*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0603 */
/*0360*/ IADD3 R3, R27, -0xc, RZ ; /* 0xfffffff41b037810 */
/* 0x000fe20007ffe0ff */
/*0370*/ LDG.E R26, [R4.64+-0x8] ; /* 0xfffff804041a7981 */
/* 0x000ee8000c1e1900 */
/*0380*/ IMAD.WIDE R2, R3, R8, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0208 */
/*0390*/ LDG.E R29, [R2.64+0x8] ; /* 0x00000804021d7981 */
/* 0x000f28000c1e1900 */
/*03a0*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x004ea8000c1e1900 */
/*03b0*/ LDG.E R20, [R2.64+0x4] ; /* 0x0000040402147981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R2.64+0xc] ; /* 0x00000c04021c7981 */
/* 0x000ee8000c1e1900 */
/*03d0*/ LDG.E R24, [R2.64+0x18] ; /* 0x0000180402187981 */
/* 0x000ee2000c1e1900 */
/*03e0*/ I2F R17, R29 ; /* 0x0000001d00117306 */
/* 0x010e300000201400 */
/*03f0*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x004eb00000201400 */
/*0400*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x000f220000201400 */
/*0410*/ FADD R17, -R10, R17 ; /* 0x000000110a117221 */
/* 0x021fce0000000100 */
/*0420*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x008e220000201400 */
/*0430*/ FADD R21, -R10, R23 ; /* 0x000000170a157221 */
/* 0x004fce0000000100 */
/*0440*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000ea2000020f100 */
/*0450*/ FADD R25, -R11.reuse, R20 ; /* 0x000000140b197221 */
/* 0x050fe40000000100 */
/*0460*/ LDG.E R20, [R2.64+0x14] ; /* 0x0000140402147981 */
/* 0x000eea000c1e1900 */
/*0470*/ F2I.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000f22000020f100 */
/*0480*/ FADD R28, -R11, R28 ; /* 0x0000001c0b1c7221 */
/* 0x001fce0000000100 */
/*0490*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000e22000020f100 */
/*04a0*/ ISETP.GT.AND P1, PT, R13, R17, PT ; /* 0x000000110d00720c */
/* 0x006fce0003f24270 */
/*04b0*/ F2I.TRUNC.NTZ R23, R28 ; /* 0x0000001c00177305 */
/* 0x000e62000020f100 */
/*04c0*/ ISETP.GE.AND P1, PT, R13, R21, !P1 ; /* 0x000000150d00720c */
/* 0x010fe40004f26270 */
/*04d0*/ LDG.E R21, [R2.64+0x10] ; /* 0x0000100402157981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ ISETP.GE.AND P1, PT, R14.reuse, R25, P1 ; /* 0x000000190e00720c */
/* 0x041fe40000f26270 */
/*04f0*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f24000c1e1900 */
/*0500*/ ISETP.LE.AND P1, PT, R14, R23, P1 ; /* 0x000000170e00720c */
/* 0x002fe40000f23270 */
/*0510*/ IADD3 R17, R22, 0x1, RZ ; /* 0x0000000116117810 */
/* 0x000fd60007ffe0ff */
/*0520*/ @!P1 IMAD.MOV R17, RZ, RZ, R22 ; /* 0x000000ffff119224 */
/* 0x000fe400078e0216 */
/*0530*/ LDG.E R22, [R2.64+0x1c] ; /* 0x00001c0402167981 */
/* 0x000f22000c1e1900 */
/*0540*/ ISETP.NE.AND P2, PT, R26.reuse, R9.reuse, PT ; /* 0x000000091a00720c */
/* 0x0c0fe40003f45270 */
/*0550*/ ISETP.EQ.AND P1, PT, R26, R9, P1 ; /* 0x000000091a00720c */
/* 0x000fe40000f22270 */
/*0560*/ LDG.E R26, [R4.64+-0x4] ; /* 0xfffffc04041a7981 */
/* 0x000f22000c1e1900 */
/*0570*/ IADD3 R23, R18, 0x1, RZ ; /* 0x0000000112177810 */
/* 0x000fd00007ffe0ff */
/*0580*/ @P2 IMAD.MOV R23, RZ, RZ, R18 ; /* 0x000000ffff172224 */
/* 0x000fe200078e0212 */
/*0590*/ IADD3 R18, R19, 0x1, RZ ; /* 0x0000000113127810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ @!P1 IMAD.MOV R18, RZ, RZ, R19 ; /* 0x000000ffff129224 */
/* 0x000fe400078e0213 */
/*05b0*/ LDG.E R19, [R2.64+0x20] ; /* 0x0000200402137981 */
/* 0x000f22000c1e1900 */
/*05c0*/ I2F R29, R24 ; /* 0x00000018001d7306 */
/* 0x000e240000201400 */
/*05d0*/ FADD R28, -R10, R29 ; /* 0x0000001d0a1c7221 */
/* 0x001fcc0000000100 */
/*05e0*/ F2I.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000e24000020f100 */
/*05f0*/ ISETP.GT.AND P1, PT, R13, R28, PT ; /* 0x0000001c0d00720c */
/* 0x001fcc0003f24270 */
/*0600*/ I2F R20, R20 ; /* 0x0000001400147306 */
/* 0x008e300000201400 */
/*0610*/ I2F R21, R21 ; /* 0x0000001500157306 */
/* 0x004e700000201400 */
/*0620*/ I2F R25, R25 ; /* 0x0000001900197306 */
/* 0x010ea20000201400 */
/*0630*/ FADD R29, -R11, R20 ; /* 0x000000140b1d7221 */
/* 0x001fc40000000100 */
/*0640*/ FADD R24, -R10, R21 ; /* 0x000000150a187221 */
/* 0x002fca0000000100 */
/*0650*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e220000201400 */
/*0660*/ FADD R21, -R10, R25 ; /* 0x000000190a157221 */
/* 0x004fe20000000100 */
/*0670*/ ISETP.NE.AND P2, PT, R26, R9, PT ; /* 0x000000091a00720c */
/* 0x000fe20003f45270 */
/*0680*/ LDG.E R25, [R2.64+0x3c] ; /* 0x00003c0402197981 */
/* 0x000eaa000c1e1900 */
/*0690*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e70000020f100 */
/*06a0*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000ee2000020f100 */
/*06b0*/ FADD R28, -R11, R22 ; /* 0x000000160b1c7221 */
/* 0x001fce0000000100 */
/*06c0*/ F2I.TRUNC.NTZ R22, R21 ; /* 0x0000001500167305 */
/* 0x000122000020f100 */
/*06d0*/ ISETP.GE.AND P1, PT, R13, R24, !P1 ; /* 0x000000180d00720c */
/* 0x002fe40004f26270 */
/*06e0*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000ea4000c1e1900 */
/*06f0*/ ISETP.GE.AND P1, PT, R14, R29, P1 ; /* 0x0000001d0e00720c */
/* 0x008fc60000f26270 */
/*0700*/ F2I.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000e62000020f100 */
/*0710*/ LDG.E R29, [R2.64+0x24] ; /* 0x00002404021d7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ IADD3 R20, R23, 0x1, RZ ; /* 0x0000000117147810 */
/* 0x000fc60007ffe0ff */
/*0730*/ LDG.E R21, [R2.64+0x34] ; /* 0x0000340402157981 */
/* 0x0010e2000c1e1900 */
/*0740*/ ISETP.GT.AND P6, PT, R13, R22, PT ; /* 0x000000160d00720c */
/* 0x010fe40003fc4270 */
/*0750*/ I2F R19, R19 ; /* 0x0000001300137306 */
/* 0x000f220000201400 */
/*0760*/ LDG.E R22, [R2.64+0x38] ; /* 0x0000380402167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ @P2 IMAD.MOV R20, RZ, RZ, R23 ; /* 0x000000ffff142224 */
/* 0x000fc600078e0217 */
/*0780*/ LDG.E R23, [R2.64+0x30] ; /* 0x0000300402177981 */
/* 0x000ee2000c1e1900 */
/*0790*/ ISETP.LE.AND P2, PT, R14, R28, P1 ; /* 0x0000001c0e00720c */
/* 0x002fc60000f43270 */
/*07a0*/ LDG.E R28, [R4.64+0x4] ; /* 0x00000404041c7981 */
/* 0x000ee2000c1e1900 */
/*07b0*/ ISETP.EQ.AND P4, PT, R26, R9, P2 ; /* 0x000000091a00720c */
/* 0x000fe20001782270 */
/*07c0*/ FADD R19, -R10, R19 ; /* 0x000000130a137221 */
/* 0x010fc80000000100 */
/*07d0*/ F2I.TRUNC.NTZ R26, R19 ; /* 0x00000013001a7305 */
/* 0x000e64000020f100 */
/*07e0*/ ISETP.GE.AND P6, PT, R13, R26, !P6 ; /* 0x0000001a0d00720c */
/* 0x002fe400077c6270 */
/*07f0*/ LDG.E R26, [R4.64] ; /* 0x00000004041a7981 */
/* 0x000f22000c1e1900 */
/*0800*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe40007ffe0ff */
/*0810*/ IADD3 R27, R27, 0x10, RZ ; /* 0x000000101b1b7810 */
/* 0x000fe20007ffe0ff */
/*0820*/ I2F R25, R25 ; /* 0x0000001900197306 */
/* 0x004ff00000201400 */
/*0830*/ I2F R24, R24 ; /* 0x0000001800187306 */
/* 0x000ff00000201400 */
/*0840*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x008e300000201400 */
/*0850*/ I2F R22, R22 ; /* 0x0000001600167306 */
/* 0x000e700000201400 */
/*0860*/ I2F R23, R23 ; /* 0x0000001700177306 */
/* 0x000ea20000201400 */
/*0870*/ FADD R3, -R11, R29 ; /* 0x0000001d0b037221 */
/* 0x001fc40000000100 */
/*0880*/ FADD R19, -R11, R24 ; /* 0x000000180b137221 */
/* 0x000fca0000000100 */
/*0890*/ I2F R2, R21 ; /* 0x0000001500027306 */
/* 0x000e220000201400 */
/*08a0*/ FADD R24, -R10, R22 ; /* 0x000000160a187221 */
/* 0x002fce0000000100 */
/*08b0*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e62000020f100 */
/*08c0*/ FADD R23, -R10, R23 ; /* 0x000000170a177221 */
/* 0x004fce0000000100 */
/*08d0*/ F2I.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000fe2000020f100 */
/*08e0*/ FADD R2, -R11, R2 ; /* 0x000000020b027221 */
/* 0x001fce0000000100 */
/*08f0*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e22000020f100 */
/*0900*/ FADD R25, -R11, R25 ; /* 0x000000190b197221 */
/* 0x000fce0000000100 */
/*0910*/ F2I.TRUNC.NTZ R29, R23 ; /* 0x00000017001d7305 */
/* 0x000ea2000020f100 */
/*0920*/ ISETP.GE.AND P6, PT, R14, R3, P6 ; /* 0x000000030e00720c */
/* 0x002fce00037c6270 */
/*0930*/ F2I.TRUNC.NTZ R21, R2 ; /* 0x0000000200157305 */
/* 0x000e62000020f100 */
/*0940*/ ISETP.NE.AND P5, PT, R26, R9, PT ; /* 0x000000091a00720c */
/* 0x010fe40003fa5270 */
/*0950*/ IADD3 R3, R17, 0x1, RZ ; /* 0x0000000111037810 */
/* 0x000fe20007ffe0ff */
/*0960*/ @!P2 IMAD.MOV R3, RZ, RZ, R17 ; /* 0x000000ffff03a224 */
/* 0x000fc800078e0211 */
/*0970*/ F2I.TRUNC.NTZ R25, R25 ; /* 0x0000001900197305 */
/* 0x000ee2000020f100 */
/*0980*/ ISETP.GT.AND P1, PT, R13.reuse, R24, PT ; /* 0x000000180d00720c */
/* 0x041fe40003f24270 */
/*0990*/ ISETP.LE.AND P2, PT, R14, R19, P6 ; /* 0x000000130e00720c */
/* 0x000fe40003743270 */
/*09a0*/ ISETP.GE.AND P1, PT, R13, R29, !P1 ; /* 0x0000001d0d00720c */
/* 0x004fe40004f26270 */
/*09b0*/ IADD3 R17, R18, 0x1, RZ ; /* 0x0000000112117810 */
/* 0x000fe20007ffe0ff */
/*09c0*/ @!P4 IMAD.MOV R17, RZ, RZ, R18 ; /* 0x000000ffff11c224 */
/* 0x000fe200078e0212 */
/*09d0*/ ISETP.GE.AND P1, PT, R14, R21, P1 ; /* 0x000000150e00720c */
/* 0x002fe20000f26270 */
/*09e0*/ IMAD.IADD R18, R16, 0x1, R15 ; /* 0x0000000110127824 */
/* 0x000fe200078e020f */
/*09f0*/ IADD3 R2, R20, 0x1, RZ ; /* 0x0000000114027810 */
/* 0x000fe20007ffe0ff */
/*0a00*/ @P5 IMAD.MOV R2, RZ, RZ, R20 ; /* 0x000000ffff025224 */
/* 0x000fe200078e0214 */
/*0a10*/ ISETP.EQ.AND P6, PT, R26, R9, P2 ; /* 0x000000091a00720c */
/* 0x000fc400017c2270 */
/*0a20*/ IADD3 R20, R3, 0x1, RZ ; /* 0x0000000103147810 */
/* 0x000fe20007ffe0ff */
/*0a30*/ @!P2 IMAD.MOV R20, RZ, RZ, R3 ; /* 0x000000ffff14a224 */
/* 0x000fe200078e0203 */
/*0a40*/ ISETP.LE.AND P1, PT, R14, R25, P1 ; /* 0x000000190e00720c */
/* 0x008fe40000f23270 */
/*0a50*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f45270 */
/*0a60*/ ISETP.NE.AND P5, PT, R28.reuse, R9.reuse, PT ; /* 0x000000091c00720c */
/* 0x0c0fe40003fa5270 */
/*0a70*/ ISETP.EQ.AND P4, PT, R28, R9, P1 ; /* 0x000000091c00720c */
/* 0x000fe40000f82270 */
/*0a80*/ IADD3 R21, R17, 0x1, RZ ; /* 0x0000000111157810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ @!P6 IMAD.MOV R21, RZ, RZ, R17 ; /* 0x000000ffff15e224 */
/* 0x000fe200078e0211 */
/*0aa0*/ IADD3 R4, P6, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc40007fde0ff */
/*0ab0*/ IADD3 R22, R20, 0x1, RZ ; /* 0x0000000114167810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ @!P1 IMAD.MOV R22, RZ, RZ, R20 ; /* 0x000000ffff169224 */
/* 0x000fe200078e0214 */
/*0ad0*/ IADD3 R18, R2, 0x1, RZ ; /* 0x0000000102127810 */
/* 0x000fe20007ffe0ff */
/*0ae0*/ IMAD.X R5, RZ, RZ, R5, P6 ; /* 0x000000ffff057224 */
/* 0x000fe200030e0605 */
/*0af0*/ IADD3 R19, R21, 0x1, RZ ; /* 0x0000000115137810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ @P5 IMAD.MOV R18, RZ, RZ, R2 ; /* 0x000000ffff125224 */
/* 0x000fe400078e0202 */
/*0b10*/ @!P4 IMAD.MOV R19, RZ, RZ, R21 ; /* 0x000000ffff13c224 */
/* 0x000fe200078e0215 */
/*0b20*/ @P2 BRA 0x360 ; /* 0xfffff83000002947 */
/* 0x000fea000383ffff */
/*0b30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0b40*/ @!P3 BRA 0xe20 ; /* 0x000002d00000b947 */
/* 0x000fea0003800000 */
/*0b50*/ IMAD.WIDE R2, R15, R8, c[0x0][0x170] ; /* 0x00005c000f027625 */
/* 0x000fc800078e0208 */
/*0b60*/ IMAD.SHL.U32 R15, R15, 0x4, RZ ; /* 0x000000040f0f7824 */
/* 0x000fe400078e00ff */
/*0b70*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0b80*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*0b90*/ IMAD.WIDE R2, R15, R8, c[0x0][0x168] ; /* 0x00005a000f027625 */
/* 0x000fca00078e0208 */
/*0ba0*/ LDG.E R25, [R2.64+0x8] ; /* 0x0000080402197981 */
/* 0x0000e8000c1e1900 */
/*0bb0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000128000c1e1900 */
/*0bc0*/ LDG.E R21, [R2.64+0x4] ; /* 0x0000040402157981 */
/* 0x0040a8000c1e1900 */
/*0bd0*/ LDG.E R27, [R2.64+0xc] ; /* 0x00000c04021b7981 */
/* 0x0000a4000c1e1900 */
/*0be0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*0bf0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0005 */
/*0c00*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x0000a2000c1e1900 */
/*0c10*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe40007ffe0ff */
/*0c20*/ IADD3 R2, R22, 0x1, RZ ; /* 0x0000000116027810 */
/* 0x001fe40007ffe0ff */
/*0c30*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ I2F R25, R25 ; /* 0x0000001900197306 */
/* 0x008e300000201400 */
/*0c50*/ I2F R17, R17 ; /* 0x0000001100117306 */
/* 0x010ef00000201400 */
/*0c60*/ I2F R24, R21 ; /* 0x0000001500187306 */
/* 0x004ea20000201400 */
/*0c70*/ FADD R26, -R10, R25 ; /* 0x000000190a1a7221 */
/* 0x021fce0000000100 */
/*0c80*/ I2F R28, R27 ; /* 0x0000001b001c7306 */
/* 0x000e220000201400 */
/*0c90*/ FADD R20, -R10, R17 ; /* 0x000000110a147221 */
/* 0x008fce0000000100 */
/*0ca0*/ F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000ee2000020f100 */
/*0cb0*/ FADD R24, -R11, R24 ; /* 0x000000180b187221 */
/* 0x004fce0000000100 */
/*0cc0*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000ea2000020f100 */
/*0cd0*/ FADD R28, -R11, R28 ; /* 0x0000001c0b1c7221 */
/* 0x001fce0000000100 */
/*0ce0*/ F2I.TRUNC.NTZ R23, R24 ; /* 0x0000001800177305 */
/* 0x000e22000020f100 */
/*0cf0*/ ISETP.GT.AND P1, PT, R13, R26, PT ; /* 0x0000001a0d00720c */
/* 0x00afce0003f24270 */
/*0d00*/ F2I.TRUNC.NTZ R3, R28 ; /* 0x0000001c00037305 */
/* 0x000e62000020f100 */
/*0d10*/ ISETP.GE.AND P1, PT, R13, R20, !P1 ; /* 0x000000140d00720c */
/* 0x004fc80004f26270 */
/*0d20*/ ISETP.GE.AND P1, PT, R14, R23, P1 ; /* 0x000000170e00720c */
/* 0x001fc80000f26270 */
/*0d30*/ ISETP.LE.AND P1, PT, R14, R3, P1 ; /* 0x000000030e00720c */
/* 0x002fe40000f23270 */
/*0d40*/ ISETP.NE.AND P3, PT, R16.reuse, R9.reuse, PT ; /* 0x000000091000720c */
/* 0x0c0fe40003f65270 */
/*0d50*/ ISETP.EQ.AND P2, PT, R16, R9, P1 ; /* 0x000000091000720c */
/* 0x000fd20000f42270 */
/*0d60*/ @!P1 IMAD.MOV R2, RZ, RZ, R22 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0216 */
/*0d70*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25270 */
/*0d80*/ IADD3 R3, R18, 0x1, RZ ; /* 0x0000000112037810 */
/* 0x000fe20007ffe0ff */
/*0d90*/ @P3 IMAD.MOV R3, RZ, RZ, R18 ; /* 0x000000ffff033224 */
/* 0x000fe200078e0212 */
/*0da0*/ IADD3 R16, R19, 0x1, RZ ; /* 0x0000000113107810 */
/* 0x000fe20007ffe0ff */
/*0db0*/ @!P2 IMAD.MOV R16, RZ, RZ, R19 ; /* 0x000000ffff10a224 */
/* 0x000fe200078e0213 */
/*0dc0*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007f7e0ff */
/*0dd0*/ IMAD.MOV.U32 R18, RZ, RZ, R3 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0003 */
/*0de0*/ IMAD.MOV.U32 R22, RZ, RZ, R2 ; /* 0x000000ffff167224 */
/* 0x000fc400078e0002 */
/*0df0*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*0e00*/ IMAD.MOV.U32 R19, RZ, RZ, R16 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0010 */
/*0e10*/ @P1 BRA 0xb90 ; /* 0xfffffd7000001947 */
/* 0x000fea000383ffff */
/*0e20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e30*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0e40*/ IMAD R9, R9, c[0x0][0x1a0], R0 ; /* 0x0000680009097a24 */
/* 0x000fc800078e0200 */
/*0e50*/ IMAD R6, R9, c[0x0][0x19c], R6 ; /* 0x0000670009067a24 */
/* 0x000fe200078e0206 */
/*0e60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fec0003800000 */
/*0e70*/ ISETP.GT.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f04270 */
/*0e80*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0e90*/ IMAD R6, R6, c[0x0][0x198], R7 ; /* 0x0000660006067a24 */
/* 0x000fc800078e0207 */
/*0ea0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0205 */
/*0eb0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x1b0] ; /* 0x00006c0006047625 */
/* 0x000fe400078e0205 */
/*0ec0*/ @P0 BRA 0xf50 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0ed0*/ ISETP.GE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fe20003f06270 */
/*0ee0*/ BSSY B0, 0xf30 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*0ef0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fd600078e00ff */
/*0f00*/ @!P0 BRA 0xf20 ; /* 0x0000001000008947 */
/* 0x000fea0003800000 */
/*0f10*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000164000c1e1900 */
/*0f20*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f30*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x020fe2000c101904 */
/*0f40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f50*/ ISETP.GE.AND P0, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe20003f06270 */
/*0f60*/ BSSY B0, 0xfc0 ; /* 0x0000005000007945 */
/* 0x000fe20003800000 */
/*0f70*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fd600078e00ff */
/*0f80*/ @!P0 BRA 0xfb0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*0f90*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1900 */
/*0fa0*/ FADD R7, R2, -1 ; /* 0xbf80000002077421 */
/* 0x008fe40000000000 */
/*0fb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0fc0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0fd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fe0*/ BRA 0xfe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kBoundingBoxLogisticGrad( float* mat, int* bbox, int* label, int* seg, float* indices, float* width_offset, float* height_offset, int size, int width, int height, int depth, float scale_width, float scale_height, float* grad) {
const int color = blockIdx.z;
/*
const int numXBlocksPerImage = DIVUP(width, blockDim.x);
const int image_id = blockIdx.x / numXBlocksPerImage;
const int col = (blockIdx.x % numXBlocksPerImage) * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
*/
const int image_id = threadIdx.x;
const int col = blockIdx.x;
const int row = blockIdx.y;
int num_bboxes = 0, num_bboxes_of_this_depth = 0, num_bboxes_of_this_depth_inside = 0;
if (col < width && row < height && image_id < size && color < depth) {
int src_image_id = (int)indices[image_id];
int src_col = (int)(scale_width * col);
int src_row = (int)(scale_height * row);
int start = seg[src_image_id];
int end = seg[src_image_id + 1];
int x1, y1, x2, y2, l, inside;
for (int box_id = start; box_id < end; box_id++) {
l = label[box_id];
x1 = bbox[box_id << 2] - width_offset[image_id];
y1 = bbox[(box_id << 2) + 1] - height_offset[image_id];
x2 = bbox[(box_id << 2) + 2] - width_offset[image_id];
y2 = bbox[(box_id << 2) + 3] - height_offset[image_id];
inside = (src_col >= x1 && src_col <= x2 && src_row >= y1 && src_row <= y2) ? 1:0;
num_bboxes += inside;
num_bboxes_of_this_depth += (l == color) ? 1: 0;
num_bboxes_of_this_depth_inside += (inside == 1 && l == color) ? 1: 0;
}
}
unsigned long i = image_id + size * (col + width * (row + height * color));
__syncthreads();
if (col < width && row < height && image_id < size && color < depth) {
if (num_bboxes > 0) {
grad[i] = (num_bboxes_of_this_depth_inside > 0) ? (mat[i] - 1) : 0;
} else {
grad[i] = (num_bboxes_of_this_depth > 0) ? mat[i] : 0;
}
}
} | .file "tmpxft_00098317_00000000-6_kBoundingBoxLogisticGrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_
.type _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_, @function
_Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 320(%rsp), %rax
movq %rax, 224(%rsp)
leaq 20(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_, .-_Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_
.globl _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.type _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, @function
_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, .-_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kBoundingBoxLogisticGrad( float* mat, int* bbox, int* label, int* seg, float* indices, float* width_offset, float* height_offset, int size, int width, int height, int depth, float scale_width, float scale_height, float* grad) {
const int color = blockIdx.z;
/*
const int numXBlocksPerImage = DIVUP(width, blockDim.x);
const int image_id = blockIdx.x / numXBlocksPerImage;
const int col = (blockIdx.x % numXBlocksPerImage) * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
*/
const int image_id = threadIdx.x;
const int col = blockIdx.x;
const int row = blockIdx.y;
int num_bboxes = 0, num_bboxes_of_this_depth = 0, num_bboxes_of_this_depth_inside = 0;
if (col < width && row < height && image_id < size && color < depth) {
int src_image_id = (int)indices[image_id];
int src_col = (int)(scale_width * col);
int src_row = (int)(scale_height * row);
int start = seg[src_image_id];
int end = seg[src_image_id + 1];
int x1, y1, x2, y2, l, inside;
for (int box_id = start; box_id < end; box_id++) {
l = label[box_id];
x1 = bbox[box_id << 2] - width_offset[image_id];
y1 = bbox[(box_id << 2) + 1] - height_offset[image_id];
x2 = bbox[(box_id << 2) + 2] - width_offset[image_id];
y2 = bbox[(box_id << 2) + 3] - height_offset[image_id];
inside = (src_col >= x1 && src_col <= x2 && src_row >= y1 && src_row <= y2) ? 1:0;
num_bboxes += inside;
num_bboxes_of_this_depth += (l == color) ? 1: 0;
num_bboxes_of_this_depth_inside += (inside == 1 && l == color) ? 1: 0;
}
}
unsigned long i = image_id + size * (col + width * (row + height * color));
__syncthreads();
if (col < width && row < height && image_id < size && color < depth) {
if (num_bboxes > 0) {
grad[i] = (num_bboxes_of_this_depth_inside > 0) ? (mat[i] - 1) : 0;
} else {
grad[i] = (num_bboxes_of_this_depth > 0) ? mat[i] : 0;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kBoundingBoxLogisticGrad( float* mat, int* bbox, int* label, int* seg, float* indices, float* width_offset, float* height_offset, int size, int width, int height, int depth, float scale_width, float scale_height, float* grad) {
const int color = blockIdx.z;
/*
const int numXBlocksPerImage = DIVUP(width, blockDim.x);
const int image_id = blockIdx.x / numXBlocksPerImage;
const int col = (blockIdx.x % numXBlocksPerImage) * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
*/
const int image_id = threadIdx.x;
const int col = blockIdx.x;
const int row = blockIdx.y;
int num_bboxes = 0, num_bboxes_of_this_depth = 0, num_bboxes_of_this_depth_inside = 0;
if (col < width && row < height && image_id < size && color < depth) {
int src_image_id = (int)indices[image_id];
int src_col = (int)(scale_width * col);
int src_row = (int)(scale_height * row);
int start = seg[src_image_id];
int end = seg[src_image_id + 1];
int x1, y1, x2, y2, l, inside;
for (int box_id = start; box_id < end; box_id++) {
l = label[box_id];
x1 = bbox[box_id << 2] - width_offset[image_id];
y1 = bbox[(box_id << 2) + 1] - height_offset[image_id];
x2 = bbox[(box_id << 2) + 2] - width_offset[image_id];
y2 = bbox[(box_id << 2) + 3] - height_offset[image_id];
inside = (src_col >= x1 && src_col <= x2 && src_row >= y1 && src_row <= y2) ? 1:0;
num_bboxes += inside;
num_bboxes_of_this_depth += (l == color) ? 1: 0;
num_bboxes_of_this_depth_inside += (inside == 1 && l == color) ? 1: 0;
}
}
unsigned long i = image_id + size * (col + width * (row + height * color));
__syncthreads();
if (col < width && row < height && image_id < size && color < depth) {
if (num_bboxes > 0) {
grad[i] = (num_bboxes_of_this_depth_inside > 0) ? (mat[i] - 1) : 0;
} else {
grad[i] = (num_bboxes_of_this_depth > 0) ? mat[i] : 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kBoundingBoxLogisticGrad( float* mat, int* bbox, int* label, int* seg, float* indices, float* width_offset, float* height_offset, int size, int width, int height, int depth, float scale_width, float scale_height, float* grad) {
const int color = blockIdx.z;
/*
const int numXBlocksPerImage = DIVUP(width, blockDim.x);
const int image_id = blockIdx.x / numXBlocksPerImage;
const int col = (blockIdx.x % numXBlocksPerImage) * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
*/
const int image_id = threadIdx.x;
const int col = blockIdx.x;
const int row = blockIdx.y;
int num_bboxes = 0, num_bboxes_of_this_depth = 0, num_bboxes_of_this_depth_inside = 0;
if (col < width && row < height && image_id < size && color < depth) {
int src_image_id = (int)indices[image_id];
int src_col = (int)(scale_width * col);
int src_row = (int)(scale_height * row);
int start = seg[src_image_id];
int end = seg[src_image_id + 1];
int x1, y1, x2, y2, l, inside;
for (int box_id = start; box_id < end; box_id++) {
l = label[box_id];
x1 = bbox[box_id << 2] - width_offset[image_id];
y1 = bbox[(box_id << 2) + 1] - height_offset[image_id];
x2 = bbox[(box_id << 2) + 2] - width_offset[image_id];
y2 = bbox[(box_id << 2) + 3] - height_offset[image_id];
inside = (src_col >= x1 && src_col <= x2 && src_row >= y1 && src_row <= y2) ? 1:0;
num_bboxes += inside;
num_bboxes_of_this_depth += (l == color) ? 1: 0;
num_bboxes_of_this_depth_inside += (inside == 1 && l == color) ? 1: 0;
}
}
unsigned long i = image_id + size * (col + width * (row + height * color));
__syncthreads();
if (col < width && row < height && image_id < size && color < depth) {
if (num_bboxes > 0) {
grad[i] = (num_bboxes_of_this_depth_inside > 0) ? (mat[i] - 1) : 0;
} else {
grad[i] = (num_bboxes_of_this_depth > 0) ? mat[i] : 0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.globl _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.p2align 8
.type _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_,@function
_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_:
s_load_b128 s[4:7], s[0:1], 0x38
s_mov_b32 s10, 0
s_mov_b32 s9, 0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s13, s5
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_cselect_b32 s2, -1, 0
s_cmp_lt_i32 s14, s6
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_b32 s2, vcc_lo, s2
s_cmp_lt_i32 s15, s7
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, s3, s2
s_and_saveexec_b32 s12, s7
s_cbranch_execz .LBB0_8
s_load_b128 s[8:11], s[0:1], 0x18
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s3, 0
s_mov_b32 s2, 0
s_mov_b32 s16, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[10:11]
s_mov_b32 s10, 0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v1, v2
s_cbranch_execz .LBB0_7
s_load_b128 s[20:23], s[0:1], 0x28
v_cvt_f32_i32_e32 v3, s13
v_lshlrev_b32_e32 v5, 2, v0
v_cvt_f32_i32_e32 v4, s14
v_dual_mov_b32 v13, 0 :: v_dual_mov_b32 v12, 0
v_mov_b32_e32 v14, 0
s_waitcnt lgkmcnt(0)
global_load_b32 v9, v5, s[20:21]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x48
s_load_b128 s[8:11], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_dual_mul_f32 v6, s2, v3 :: v_dual_mul_f32 v7, s3, v4
v_ashrrev_i32_e32 v4, 31, v1
v_mov_b32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v10, v6
v_cvt_i32_f32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v3, s2, s22, v5
v_add_co_ci_u32_e64 v4, null, s23, 0, s2
v_lshlrev_b32_e32 v5, 2, v1
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
s_mov_b32 s10, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s17
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s15, v6
v_add_nc_u32_e32 v1, 1, v1
v_cndmask_b32_e64 v6, 0, 1, s11
v_add_nc_u32_e32 v5, 4, v5
v_add_co_ci_u32_e64 v13, s2, 0, v13, vcc_lo
s_and_b32 s2, s11, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v1, v2
v_cndmask_b32_e64 v15, 0, 1, s2
v_add_co_u32 v7, s2, v7, 4
v_add_nc_u32_e32 v12, v12, v6
v_add_co_ci_u32_e64 v8, s2, 0, v8, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v14, v14, v15
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_6
.LBB0_4:
v_ashrrev_i32_e32 v6, 31, v5
s_and_not1_b32 s11, s11, exec_lo
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[5:6]
v_add_co_u32 v15, vcc_lo, s8, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
global_load_b32 v15, v[15:16], off
global_load_b32 v6, v[7:8], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v15, v15
v_sub_f32_e32 v15, v15, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v15, v15
v_cmpx_ge_i32_e64 v10, v15
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v15, 3, v5
v_add_nc_u32_e32 v19, 2, v5
v_add_nc_u32_e32 v17, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v16, 31, v15
v_ashrrev_i32_e32 v20, 31, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[19:20], 2, v[19:20]
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v19, vcc_lo, s8, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v20, vcc_lo
v_add_co_u32 v17, vcc_lo, s8, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
s_clause 0x2
global_load_b32 v19, v[19:20], off
global_load_b32 v15, v[15:16], off
global_load_b32 v16, v[17:18], off
global_load_b32 v17, v[3:4], off
s_waitcnt vmcnt(3)
v_cvt_f32_i32_e32 v18, v19
s_waitcnt vmcnt(2)
v_cvt_f32_i32_e32 v15, v15
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v16, v16
v_sub_f32_e32 v18, v18, v9
s_waitcnt vmcnt(0)
v_sub_f32_e32 v15, v15, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v16, v16, v17
v_cvt_i32_f32_e32 v17, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v15, v15
v_cvt_i32_f32_e32 v16, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, v10, v17
v_cmp_le_i32_e64 s2, v11, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e64 s3, v11, v16
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_not1_b32 s3, s11, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s11, s3, s2
s_branch .LBB0_3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s10
v_cmp_ne_u32_e32 vcc_lo, 0, v12
v_cmp_ne_u32_e64 s2, 0, v13
v_cmp_ne_u32_e64 s3, 0, v14
s_and_b32 s10, vcc_lo, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 s2, s2, exec_lo
s_and_b32 s3, s3, exec_lo
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s8, s3, exec_lo
s_and_b32 s9, s2, exec_lo
s_and_b32 s10, s10, exec_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s12
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_18
s_mul_i32 s6, s15, s6
s_load_b64 s[2:3], s[0:1], 0x0
s_add_i32 s6, s6, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s6, s5
s_add_i32 s5, s5, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s5, s4, v[0:1]
s_xor_b32 s4, s10, -1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s5
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v0, 0
s_and_saveexec_b32 s5, s9
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_13:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_17
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_and_saveexec_b32 s5, s8
s_cbranch_execz .LBB0_16
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, -1.0, v0
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_17:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x50
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 88
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, .Lfunc_end0-_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 88
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kBoundingBoxLogisticGrad( float* mat, int* bbox, int* label, int* seg, float* indices, float* width_offset, float* height_offset, int size, int width, int height, int depth, float scale_width, float scale_height, float* grad) {
const int color = blockIdx.z;
/*
const int numXBlocksPerImage = DIVUP(width, blockDim.x);
const int image_id = blockIdx.x / numXBlocksPerImage;
const int col = (blockIdx.x % numXBlocksPerImage) * blockDim.x + threadIdx.x;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
*/
const int image_id = threadIdx.x;
const int col = blockIdx.x;
const int row = blockIdx.y;
int num_bboxes = 0, num_bboxes_of_this_depth = 0, num_bboxes_of_this_depth_inside = 0;
if (col < width && row < height && image_id < size && color < depth) {
int src_image_id = (int)indices[image_id];
int src_col = (int)(scale_width * col);
int src_row = (int)(scale_height * row);
int start = seg[src_image_id];
int end = seg[src_image_id + 1];
int x1, y1, x2, y2, l, inside;
for (int box_id = start; box_id < end; box_id++) {
l = label[box_id];
x1 = bbox[box_id << 2] - width_offset[image_id];
y1 = bbox[(box_id << 2) + 1] - height_offset[image_id];
x2 = bbox[(box_id << 2) + 2] - width_offset[image_id];
y2 = bbox[(box_id << 2) + 3] - height_offset[image_id];
inside = (src_col >= x1 && src_col <= x2 && src_row >= y1 && src_row <= y2) ? 1:0;
num_bboxes += inside;
num_bboxes_of_this_depth += (l == color) ? 1: 0;
num_bboxes_of_this_depth_inside += (inside == 1 && l == color) ? 1: 0;
}
}
unsigned long i = image_id + size * (col + width * (row + height * color));
__syncthreads();
if (col < width && row < height && image_id < size && color < depth) {
if (num_bboxes > 0) {
grad[i] = (num_bboxes_of_this_depth_inside > 0) ? (mat[i] - 1) : 0;
} else {
grad[i] = (num_bboxes_of_this_depth > 0) ? mat[i] : 0;
}
}
} | .text
.file "kBoundingBoxLogisticGrad.hip"
.globl _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_ # -- Begin function _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.p2align 4, 0x90
.type _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_,@function
_Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_: # @_Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, .Lfunc_end0-_Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_,@object # @_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.section .rodata,"a",@progbits
.globl _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.p2align 3, 0x0
_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_:
.quad _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.size _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098317_00000000-6_kBoundingBoxLogisticGrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_
.type _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_, @function
_Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 304(%rsp), %rax
movq %rax, 208(%rsp)
leaq 312(%rsp), %rax
movq %rax, 216(%rsp)
leaq 320(%rsp), %rax
movq %rax, 224(%rsp)
leaq 20(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_, .-_Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_
.globl _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.type _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, @function
_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z66__device_stub__Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_PfPiS0_S0_S_S_S_iiiiffS_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, .-_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kBoundingBoxLogisticGrad.hip"
.globl _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_ # -- Begin function _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.p2align 4, 0x90
.type _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_,@function
_Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_: # @_Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 280(%rsp), %rax
movq %rax, 216(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, .Lfunc_end0-_Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_,@object # @_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.section .rodata,"a",@progbits
.globl _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.p2align 3, 0x0
_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_:
.quad _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.size _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24kBoundingBoxLogisticGradPfPiS0_S0_S_S_S_iiiiffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Just your regular Hello World file
// to be compiled with nvcc rather than gcc
#include <stdio.h>
int main(void) {
printf("Hello World from CPU!\n");
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Just your regular Hello World file
// to be compiled with nvcc rather than gcc
#include <stdio.h>
int main(void) {
printf("Hello World from CPU!\n");
return 0;
} | .file "tmpxft_0003c314_00000000-6_hello1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Just your regular Hello World file
// to be compiled with nvcc rather than gcc
#include <stdio.h>
int main(void) {
printf("Hello World from CPU!\n");
return 0;
} | //Just your regular Hello World file
// to be compiled with nvcc rather than gcc
#include <hip/hip_runtime.h>
#include <stdio.h>
int main(void) {
printf("Hello World from CPU!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Just your regular Hello World file
// to be compiled with nvcc rather than gcc
#include <hip/hip_runtime.h>
#include <stdio.h>
int main(void) {
printf("Hello World from CPU!\n");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Just your regular Hello World file
// to be compiled with nvcc rather than gcc
#include <hip/hip_runtime.h>
#include <stdio.h>
int main(void) {
printf("Hello World from CPU!\n");
return 0;
} | .text
.file "hello1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003c314_00000000-6_hello1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
//Device code
__global__ void addvec (float* a, float* b, float* c, int N)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<N)
c[i] = a[i]+b[i];
}
//Host code
int main()
{
int N = 10;
size_t size = N*sizeof(float);
//Allocate input vectors h_A and h_B in host memory
float* h_a = (float*)malloc(size);
float* h_b = (float*)malloc(size);
float* h_c = (float*)malloc(size);
//Initialize input vectors
int i;
for (i=0;i<N;i++){
h_a[i] = i+1;
}
for (i=0;i<N;i++){
h_b[i] = i+1;
}
//Allocate vectors in device memory
float* d_a;
cudaMalloc(&d_a, size);
float* d_b;
cudaMalloc(&d_b,size);
float* d_c;
cudaMalloc(&d_c,size);
//Copy vectors from host memory to device memory
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
//Invoke kernel
int threads_per_block = 256;
int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;
addvec<<<blocks_per_grid, threads_per_block>>>(d_a, d_b, d_c, N);
//Copy result from device memory to host memory
//h_c contains the result in host memory
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
for (i=0;i<N;i++){
printf("%f \n",h_c[i]);
}
//Free device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//Free host memory
cudaFree(h_a);
cudaFree(h_b);
} | code for sm_80
Function : _Z6addvecPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
//Device code
__global__ void addvec (float* a, float* b, float* c, int N)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<N)
c[i] = a[i]+b[i];
}
//Host code
int main()
{
int N = 10;
size_t size = N*sizeof(float);
//Allocate input vectors h_A and h_B in host memory
float* h_a = (float*)malloc(size);
float* h_b = (float*)malloc(size);
float* h_c = (float*)malloc(size);
//Initialize input vectors
int i;
for (i=0;i<N;i++){
h_a[i] = i+1;
}
for (i=0;i<N;i++){
h_b[i] = i+1;
}
//Allocate vectors in device memory
float* d_a;
cudaMalloc(&d_a, size);
float* d_b;
cudaMalloc(&d_b,size);
float* d_c;
cudaMalloc(&d_c,size);
//Copy vectors from host memory to device memory
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
//Invoke kernel
int threads_per_block = 256;
int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;
addvec<<<blocks_per_grid, threads_per_block>>>(d_a, d_b, d_c, N);
//Copy result from device memory to host memory
//h_c contains the result in host memory
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
for (i=0;i<N;i++){
printf("%f \n",h_c[i]);
}
//Free device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//Free host memory
cudaFree(h_a);
cudaFree(h_b);
} | .file "tmpxft_00098f45_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6addvecPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addvecPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
.globl _Z6addvecPfS_S_i
.type _Z6addvecPfS_S_i, @function
_Z6addvecPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addvecPfS_S_i, .-_Z6addvecPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
addq $1, %rax
cmpq $11, %rax
jne .L12
movl $1, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $11, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
addq $40, %r13
leaq .LC0(%rip), %r14
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6addvecPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addvecPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
//Device code
__global__ void addvec (float* a, float* b, float* c, int N)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<N)
c[i] = a[i]+b[i];
}
//Host code
int main()
{
int N = 10;
size_t size = N*sizeof(float);
//Allocate input vectors h_A and h_B in host memory
float* h_a = (float*)malloc(size);
float* h_b = (float*)malloc(size);
float* h_c = (float*)malloc(size);
//Initialize input vectors
int i;
for (i=0;i<N;i++){
h_a[i] = i+1;
}
for (i=0;i<N;i++){
h_b[i] = i+1;
}
//Allocate vectors in device memory
float* d_a;
cudaMalloc(&d_a, size);
float* d_b;
cudaMalloc(&d_b,size);
float* d_c;
cudaMalloc(&d_c,size);
//Copy vectors from host memory to device memory
cudaMemcpy(d_a, h_a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, size, cudaMemcpyHostToDevice);
//Invoke kernel
int threads_per_block = 256;
int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;
addvec<<<blocks_per_grid, threads_per_block>>>(d_a, d_b, d_c, N);
//Copy result from device memory to host memory
//h_c contains the result in host memory
cudaMemcpy(h_c, d_c, size, cudaMemcpyDeviceToHost);
for (i=0;i<N;i++){
printf("%f \n",h_c[i]);
}
//Free device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//Free host memory
cudaFree(h_a);
cudaFree(h_b);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
//Device code
__global__ void addvec (float* a, float* b, float* c, int N)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<N)
c[i] = a[i]+b[i];
}
//Host code
int main()
{
int N = 10;
size_t size = N*sizeof(float);
//Allocate input vectors h_A and h_B in host memory
float* h_a = (float*)malloc(size);
float* h_b = (float*)malloc(size);
float* h_c = (float*)malloc(size);
//Initialize input vectors
int i;
for (i=0;i<N;i++){
h_a[i] = i+1;
}
for (i=0;i<N;i++){
h_b[i] = i+1;
}
//Allocate vectors in device memory
float* d_a;
hipMalloc(&d_a, size);
float* d_b;
hipMalloc(&d_b,size);
float* d_c;
hipMalloc(&d_c,size);
//Copy vectors from host memory to device memory
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
//Invoke kernel
int threads_per_block = 256;
int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;
addvec<<<blocks_per_grid, threads_per_block>>>(d_a, d_b, d_c, N);
//Copy result from device memory to host memory
//h_c contains the result in host memory
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
for (i=0;i<N;i++){
printf("%f \n",h_c[i]);
}
//Free device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//Free host memory
hipFree(h_a);
hipFree(h_b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//Device code
__global__ void addvec (float* a, float* b, float* c, int N)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<N)
c[i] = a[i]+b[i];
}
//Host code
int main()
{
int N = 10;
size_t size = N*sizeof(float);
//Allocate input vectors h_A and h_B in host memory
float* h_a = (float*)malloc(size);
float* h_b = (float*)malloc(size);
float* h_c = (float*)malloc(size);
//Initialize input vectors
int i;
for (i=0;i<N;i++){
h_a[i] = i+1;
}
for (i=0;i<N;i++){
h_b[i] = i+1;
}
//Allocate vectors in device memory
float* d_a;
hipMalloc(&d_a, size);
float* d_b;
hipMalloc(&d_b,size);
float* d_c;
hipMalloc(&d_c,size);
//Copy vectors from host memory to device memory
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
//Invoke kernel
int threads_per_block = 256;
int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;
addvec<<<blocks_per_grid, threads_per_block>>>(d_a, d_b, d_c, N);
//Copy result from device memory to host memory
//h_c contains the result in host memory
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
for (i=0;i<N;i++){
printf("%f \n",h_c[i]);
}
//Free device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//Free host memory
hipFree(h_a);
hipFree(h_b);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addvecPfS_S_i
.globl _Z6addvecPfS_S_i
.p2align 8
.type _Z6addvecPfS_S_i,@function
_Z6addvecPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addvecPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addvecPfS_S_i, .Lfunc_end0-_Z6addvecPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addvecPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6addvecPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//Device code
__global__ void addvec (float* a, float* b, float* c, int N)
{
int i = blockDim.x*blockIdx.x + threadIdx.x;
if (i<N)
c[i] = a[i]+b[i];
}
//Host code
int main()
{
int N = 10;
size_t size = N*sizeof(float);
//Allocate input vectors h_A and h_B in host memory
float* h_a = (float*)malloc(size);
float* h_b = (float*)malloc(size);
float* h_c = (float*)malloc(size);
//Initialize input vectors
int i;
for (i=0;i<N;i++){
h_a[i] = i+1;
}
for (i=0;i<N;i++){
h_b[i] = i+1;
}
//Allocate vectors in device memory
float* d_a;
hipMalloc(&d_a, size);
float* d_b;
hipMalloc(&d_b,size);
float* d_c;
hipMalloc(&d_c,size);
//Copy vectors from host memory to device memory
hipMemcpy(d_a, h_a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, size, hipMemcpyHostToDevice);
//Invoke kernel
int threads_per_block = 256;
int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;
addvec<<<blocks_per_grid, threads_per_block>>>(d_a, d_b, d_c, N);
//Copy result from device memory to host memory
//h_c contains the result in host memory
hipMemcpy(h_c, d_c, size, hipMemcpyDeviceToHost);
for (i=0;i<N;i++){
printf("%f \n",h_c[i]);
}
//Free device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//Free host memory
hipFree(h_a);
hipFree(h_b);
} | .text
.file "add.hip"
.globl _Z21__device_stub__addvecPfS_S_i # -- Begin function _Z21__device_stub__addvecPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__addvecPfS_S_i,@function
_Z21__device_stub__addvecPfS_S_i: # @_Z21__device_stub__addvecPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addvecPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__addvecPfS_S_i, .Lfunc_end0-_Z21__device_stub__addvecPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_3
# %bb.4:
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addvecPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_7
# %bb.8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addvecPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addvecPfS_S_i,@object # @_Z6addvecPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6addvecPfS_S_i
.p2align 3, 0x0
_Z6addvecPfS_S_i:
.quad _Z21__device_stub__addvecPfS_S_i
.size _Z6addvecPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f \n"
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addvecPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addvecPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addvecPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6addvecPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addvecPfS_S_i
.globl _Z6addvecPfS_S_i
.p2align 8
.type _Z6addvecPfS_S_i,@function
_Z6addvecPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addvecPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addvecPfS_S_i, .Lfunc_end0-_Z6addvecPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addvecPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6addvecPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00098f45_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6addvecPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addvecPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
.globl _Z6addvecPfS_S_i
.type _Z6addvecPfS_S_i, @function
_Z6addvecPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addvecPfS_S_i, .-_Z6addvecPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $1, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%r12,%rax,4)
addq $1, %rax
cmpq $11, %rax
jne .L12
movl $1, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbp,%rax,4)
addq $1, %rax
cmpq $11, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rbx
addq $40, %r13
leaq .LC0(%rip), %r14
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L15
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6addvecPfS_S_iPfS_S_i
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6addvecPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addvecPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z21__device_stub__addvecPfS_S_i # -- Begin function _Z21__device_stub__addvecPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__addvecPfS_S_i,@function
_Z21__device_stub__addvecPfS_S_i: # @_Z21__device_stub__addvecPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addvecPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__addvecPfS_S_i, .Lfunc_end0-_Z21__device_stub__addvecPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
movq %rcx, %rax
cmpq $10, %rcx
jne .LBB1_3
# %bb.4:
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addvecPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB1_7
# %bb.8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addvecPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addvecPfS_S_i,@object # @_Z6addvecPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6addvecPfS_S_i
.p2align 3, 0x0
_Z6addvecPfS_S_i:
.quad _Z21__device_stub__addvecPfS_S_i
.size _Z6addvecPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f \n"
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addvecPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addvecPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addvecPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
int n = Mask_Width/2;
/******************************************************************/
/* Your TODO-1 starts here: */
/* Load the data with halo from N to the shared memory N_ds */
/* remember that you need to load: */
/* + the left halo */
/* + the data */
/* + the right halo */
/******************************************************************/
int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
if(threadIdx.x>=blockDim.x-n)
N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
if(threadIdx.x<n)
N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
__syncthreads();
/***********************/
/*Your TODO-1 ends here*/
/***********************/
/******************************************************************/
/* Your TODO-2 starts here: */
/* Calculate the value coresponding to each thread */
/* The result is saved into the array P */
/* It should be noted that the mask M is already copy to the */
/* constant memory */
/******************************************************************/
float Pvalue = 0;
for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
P[i] = Pvalue;
/***********************/
/*Your TODO-2 ends here*/
/***********************/
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/*******************/
/** READING INPUT **/
/*******************/
/* dimension of mask */
int size_m = 0;
scanf("%d", &size_m);
int full_size_m = size_m*sizeof(float);
float* h_M = (float*)malloc(full_size_m);
for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
/* dimension of array */
int size = 0;
scanf("%d", &size);
int full_size = sizeof(float)*size;
/* Allocate host memory */
float* h_N = (float*)malloc(full_size);
float* h_P = (float*)malloc(full_size);
for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device memory */
/*************************/
float* d_N,*d_P;
cudaMalloc(&d_N, full_size);
cudaMalloc(&d_P, full_size);
/******************************/
/* copy array & mask to device */
/******************************/
cudaMemcpy(d_N,h_N,full_size,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(M,h_M,full_size_m);
/****************/
/** CALL KERNEL */
/****************/
int threadsPerBlock = size;
Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_P, d_P, full_size, cudaMemcpyDeviceToHost);
/*******************************************/
/* Testing output, don't change anything! */
/*******************************************/
test(h_P, size);
free(h_N);
free(h_P);
cudaFree(d_N);
cudaFree(d_P);
return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
int i=0;
for(i=0;i<length;++i){
printf("%.1f ", C[i]);
}
printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z6Conv1DPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e620000002500 */
/*0060*/ BSSY B0, 0x1b0 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0070*/ LEA.HI R2, R10, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c000a027a11 */
/* 0x000fc800078f08ff */
/*0080*/ SHF.R.S32.HI R7, RZ, 0x1, R2 ; /* 0x00000001ff077819 */
/* 0x000fc80000011402 */
/*0090*/ IADD3 R5, -R7, c[0x0][0x0], RZ ; /* 0x0000000007057a10 */
/* 0x000fc80007ffe1ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x001fe20003f06070 */
/*00b0*/ IMAD R3, R9.reuse, R8, -c[0x0][0x0] ; /* 0x8000000009037624 */
/* 0x042fe400078e0208 */
/*00c0*/ IMAD R2, R9, c[0x0][0x0], R0.reuse ; /* 0x0000000009027a24 */
/* 0x100fe400078e0200 */
/*00d0*/ IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103037824 */
/* 0x000fca00078e0200 */
/*00e0*/ LEA R6, R8, R3, 0x1 ; /* 0x0000000308067211 */
/* 0x000fc600078e08ff */
/*00f0*/ @!P0 BRA 0x1a0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0110*/ BSSY B1, 0x190 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0120*/ IADD3 R9, R7, -c[0x0][0x0], R0 ; /* 0x8000000007097a10 */
/* 0x000fe20007ffe000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd400078e00ff */
/*0140*/ @!P0 BRA 0x180 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0160*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e0204 */
/*0170*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000164000c1e1900 */
/*0180*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0190*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0203e40000004800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x003fcc00078e0003 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R9, R7, R0, RZ ; /* 0x0000000007097210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ BSSY B0, 0x2e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fc60003f06070 */
/*0210*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041f40000004800 */
/*0220*/ @P0 BRA 0x2d0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe20003f06270 */
/*0240*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x001fe200078e00ff */
/*0250*/ BSSY B1, 0x2c0 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0270*/ LEA R9, R8, R9, 0x2 ; /* 0x0000000908097211 */
/* 0x000fce00078e10ff */
/*0280*/ @P0 BRA 0x2b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.WIDE R4, R6, R3, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fcc00078e0203 */
/*02a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000164000c1e1900 */
/*02b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02c0*/ STS [R9], R4 ; /* 0x0000000409007388 */
/* 0x0203e40000000800 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f06270 */
/*0300*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fd60000000f00 */
/*0310*/ @!P0 BRA 0xab0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0320*/ IADD3 R4, R10, -0x1, RZ ; /* 0xffffffff0a047810 */
/* 0x003fe20007ffe0ff */
/*0330*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0360*/ LOP3.LUT R4, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a047812 */
/* 0x000fd600078ec0ff */
/*0370*/ @!P0 BRA 0x9e0 ; /* 0x0000066000008947 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R6, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fe20007ffe1ff */
/*0390*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03a0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*03b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*03c0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*03d0*/ LEA R5, R0, 0x8, 0x2 ; /* 0x0000000800057811 */
/* 0x000fd600078e10ff */
/*03e0*/ @!P0 BRA 0x8e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0400*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0410*/ @!P1 BRA 0x710 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0420*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0430*/ LDS R13, [R5+-0x8] ; /* 0xfffff800050d7984 */
/* 0x000e220000000800 */
/*0440*/ ULDC.64 UR8, c[0x3][UR5] ; /* 0x00c0000005087abb */
/* 0x000fe20008000a00 */
/*0450*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0470*/ LDS R10, [R5+-0x4] ; /* 0xfffffc00050a7984 */
/* 0x000e640000000800 */
/*0480*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0490*/ LDS R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000ea80000000800 */
/*04a0*/ LDS R15, [R5+0x4] ; /* 0x00000400050f7984 */
/* 0x000ee80000000800 */
/*04b0*/ LDS R17, [R5+0x8] ; /* 0x0000080005117984 */
/* 0x000f280000000800 */
/*04c0*/ LDS R19, [R5+0xc] ; /* 0x00000c0005137984 */
/* 0x000f680000000800 */
/*04d0*/ LDS R21, [R5+0x10] ; /* 0x0000100005157984 */
/* 0x000f680000000800 */
/*04e0*/ LDS R11, [R5+0x14] ; /* 0x00001400050b7984 */
/* 0x000f680000000800 */
/*04f0*/ LDS R9, [R5+0x18] ; /* 0x0000180005097984 */
/* 0x000f680000000800 */
/*0500*/ LDS R7, [R5+0x1c] ; /* 0x00001c0005077984 */
/* 0x000f620000000800 */
/*0510*/ FFMA R13, R13, UR8, R8 ; /* 0x000000080d0d7c23 */
/* 0x001fc60008000008 */
/*0520*/ LDS R14, [R5+0x28] ; /* 0x00002800050e7984 */
/* 0x000fe20000000800 */
/*0530*/ FFMA R13, R10, UR9, R13 ; /* 0x000000090a0d7c23 */
/* 0x002fc6000800000d */
/*0540*/ LDS R8, [R5+0x20] ; /* 0x0000200005087984 */
/* 0x000e220000000800 */
/*0550*/ ULDC.64 UR8, c[0x3][UR5+0x8] ; /* 0x00c0020005087abb */
/* 0x000fe40008000a00 */
/*0560*/ FFMA R12, R12, UR8, R13 ; /* 0x000000080c0c7c23 */
/* 0x004fe2000800000d */
/*0570*/ LDS R10, [R5+0x24] ; /* 0x00002400050a7984 */
/* 0x000e660000000800 */
/*0580*/ FFMA R12, R15, UR9, R12 ; /* 0x000000090f0c7c23 */
/* 0x008fe2000800000c */
/*0590*/ LDS R16, [R5+0x2c] ; /* 0x00002c0005107984 */
/* 0x000ea20000000800 */
/*05a0*/ ULDC.64 UR8, c[0x3][UR5+0x10] ; /* 0x00c0040005087abb */
/* 0x000fe40008000a00 */
/*05b0*/ FFMA R12, R17, UR8, R12 ; /* 0x00000008110c7c23 */
/* 0x010fe2000800000c */
/*05c0*/ LDS R18, [R5+0x30] ; /* 0x0000300005127984 */
/* 0x000ee60000000800 */
/*05d0*/ FFMA R12, R19, UR9, R12 ; /* 0x00000009130c7c23 */
/* 0x020fe2000800000c */
/*05e0*/ LDS R20, [R5+0x34] ; /* 0x0000340005147984 */
/* 0x0009620000000800 */
/*05f0*/ ULDC.64 UR8, c[0x3][UR5+0x18] ; /* 0x00c0060005087abb */
/* 0x000fc40008000a00 */
/*0600*/ FFMA R12, R21, UR8, R12 ; /* 0x00000008150c7c23 */
/* 0x000fc8000800000c */
/*0610*/ FFMA R12, R11, UR9, R12 ; /* 0x000000090b0c7c23 */
/* 0x000fe2000800000c */
/*0620*/ ULDC.64 UR8, c[0x3][UR5+0x20] ; /* 0x00c0080005087abb */
/* 0x000fe20008000a00 */
/*0630*/ IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005057810 */
/* 0x010fe40007ffe0ff */
/*0640*/ FFMA R12, R9, UR8, R12 ; /* 0x00000008090c7c23 */
/* 0x000fc8000800000c */
/*0650*/ FFMA R7, R7, UR9, R12 ; /* 0x0000000907077c23 */
/* 0x000fe2000800000c */
/*0660*/ ULDC.64 UR8, c[0x3][UR5+0x28] ; /* 0x00c00a0005087abb */
/* 0x000fc60008000a00 */
/*0670*/ FFMA R7, R8, UR8, R7 ; /* 0x0000000808077c23 */
/* 0x001fc80008000007 */
/*0680*/ FFMA R7, R10, UR9, R7 ; /* 0x000000090a077c23 */
/* 0x002fe20008000007 */
/*0690*/ ULDC.64 UR8, c[0x3][UR5+0x30] ; /* 0x00c00c0005087abb */
/* 0x000fc60008000a00 */
/*06a0*/ FFMA R7, R14, UR8, R7 ; /* 0x000000080e077c23 */
/* 0x000fc80008000007 */
/*06b0*/ FFMA R7, R16, UR9, R7 ; /* 0x0000000910077c23 */
/* 0x004fe20008000007 */
/*06c0*/ ULDC.64 UR8, c[0x3][UR5+0x38] ; /* 0x00c00e0005087abb */
/* 0x000fe40008000a00 */
/*06d0*/ UIADD3 UR5, UR5, 0x40, URZ ; /* 0x0000004005057890 */
/* 0x000fe2000fffe03f */
/*06e0*/ FFMA R7, R18, UR8, R7 ; /* 0x0000000812077c23 */
/* 0x008fc80008000007 */
/*06f0*/ FFMA R8, R20, UR9, R7 ; /* 0x0000000914087c23 */
/* 0x020fe20008000007 */
/*0700*/ @P1 BRA 0x430 ; /* 0xfffffd2000001947 */
/* 0x000fea000383ffff */
/*0710*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0720*/ @!P1 BRA 0x8c0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0730*/ LDS R7, [R5+-0x8] ; /* 0xfffff80005077984 */
/* 0x000e220000000800 */
/*0740*/ ULDC.64 UR8, c[0x3][UR5] ; /* 0x00c0000005087abb */
/* 0x000fe20008000a00 */
/*0750*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0760*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0770*/ LDS R10, [R5+-0x4] ; /* 0xfffffc00050a7984 */
/* 0x000e620000000800 */
/*0780*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*0790*/ LDS R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000ea80000000800 */
/*07a0*/ LDS R14, [R5+0x4] ; /* 0x00000400050e7984 */
/* 0x000ee80000000800 */
/*07b0*/ LDS R16, [R5+0x8] ; /* 0x0000080005107984 */
/* 0x000f280000000800 */
/*07c0*/ LDS R18, [R5+0xc] ; /* 0x00000c0005127984 */
/* 0x000f680000000800 */
/*07d0*/ LDS R20, [R5+0x10] ; /* 0x0000100005147984 */
/* 0x000f680000000800 */
/*07e0*/ LDS R22, [R5+0x14] ; /* 0x0000140005167984 */
/* 0x0001640000000800 */
/*07f0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x001fe20007ffe0ff */
/*0800*/ FFMA R7, R7, UR8, R8 ; /* 0x0000000807077c23 */
/* 0x000fc80008000008 */
/*0810*/ FFMA R7, R10, UR9, R7 ; /* 0x000000090a077c23 */
/* 0x002fe20008000007 */
/*0820*/ ULDC.64 UR8, c[0x3][UR5+0x8] ; /* 0x00c0020005087abb */
/* 0x000fc60008000a00 */
/*0830*/ FFMA R7, R12, UR8, R7 ; /* 0x000000080c077c23 */
/* 0x004fc80008000007 */
/*0840*/ FFMA R7, R14, UR9, R7 ; /* 0x000000090e077c23 */
/* 0x008fe20008000007 */
/*0850*/ ULDC.64 UR8, c[0x3][UR5+0x10] ; /* 0x00c0040005087abb */
/* 0x000fc60008000a00 */
/*0860*/ FFMA R7, R16, UR8, R7 ; /* 0x0000000810077c23 */
/* 0x010fc80008000007 */
/*0870*/ FFMA R7, R18, UR9, R7 ; /* 0x0000000912077c23 */
/* 0x020fe20008000007 */
/*0880*/ ULDC.64 UR8, c[0x3][UR5+0x18] ; /* 0x00c0060005087abb */
/* 0x000fe40008000a00 */
/*0890*/ UIADD3 UR5, UR5, 0x20, URZ ; /* 0x0000002005057890 */
/* 0x000fe2000fffe03f */
/*08a0*/ FFMA R7, R20, UR8, R7 ; /* 0x0000000814077c23 */
/* 0x000fc80008000007 */
/*08b0*/ FFMA R8, R22, UR9, R7 ; /* 0x0000000916087c23 */
/* 0x000fe40008000007 */
/*08c0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08d0*/ @!P0 BRA 0x9e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*08e0*/ LDS R7, [R5+-0x8] ; /* 0xfffff80005077984 */
/* 0x000e220000000800 */
/*08f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0900*/ ULDC.64 UR8, c[0x3][UR5] ; /* 0x00c0000005087abb */
/* 0x000fe40008000a00 */
/*0910*/ LDS R10, [R5+-0x4] ; /* 0xfffffc00050a7984 */
/* 0x000e620000000800 */
/*0920*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0930*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0940*/ LDS R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000ea80000000800 */
/*0950*/ LDS R14, [R5+0x4] ; /* 0x00000400050e7984 */
/* 0x0007240000000800 */
/*0960*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x008fe20007ffe0ff */
/*0970*/ FFMA R7, R7, UR8, R8 ; /* 0x0000000807077c23 */
/* 0x001fc80008000008 */
/*0980*/ FFMA R7, R10, UR9, R7 ; /* 0x000000090a077c23 */
/* 0x002fe20008000007 */
/*0990*/ ULDC.64 UR8, c[0x3][UR5+0x8] ; /* 0x00c0020005087abb */
/* 0x000fe40008000a00 */
/*09a0*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*09b0*/ FFMA R7, R12, UR8, R7 ; /* 0x000000080c077c23 */
/* 0x004fc80008000007 */
/*09c0*/ FFMA R8, R14, UR9, R7 ; /* 0x000000090e087c23 */
/* 0x010fe20008000007 */
/*09d0*/ @P0 BRA 0x8e0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*09e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*09f0*/ @!P0 BRA 0xab0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0a00*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe0ff */
/*0a10*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fc6000800063f */
/*0a20*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fce00000006ff */
/*0a30*/ LDS R5, [R0] ; /* 0x0000000000057984 */
/* 0x0000620000000800 */
/*0a40*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ ULDC UR4, c[0x3][UR5] ; /* 0x00c0000005047abb */
/* 0x000fe40008000800 */
/*0a60*/ UIADD3 UR5, UR5, 0x4, URZ ; /* 0x0000000405057890 */
/* 0x000fe2000fffe03f */
/*0a70*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0a80*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0a90*/ FFMA R8, R5, UR4, R8 ; /* 0x0000000405087c23 */
/* 0x002fd40008000008 */
/*0aa0*/ @P0 BRA 0xa30 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0ac0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x000fe2000c101906 */
/*0ad0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
int n = Mask_Width/2;
/******************************************************************/
/* Your TODO-1 starts here: */
/* Load the data with halo from N to the shared memory N_ds */
/* remember that you need to load: */
/* + the left halo */
/* + the data */
/* + the right halo */
/******************************************************************/
int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
if(threadIdx.x>=blockDim.x-n)
N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
if(threadIdx.x<n)
N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
__syncthreads();
/***********************/
/*Your TODO-1 ends here*/
/***********************/
/******************************************************************/
/* Your TODO-2 starts here: */
/* Calculate the value coresponding to each thread */
/* The result is saved into the array P */
/* It should be noted that the mask M is already copy to the */
/* constant memory */
/******************************************************************/
float Pvalue = 0;
for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
P[i] = Pvalue;
/***********************/
/*Your TODO-2 ends here*/
/***********************/
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/*******************/
/** READING INPUT **/
/*******************/
/* dimension of mask */
int size_m = 0;
scanf("%d", &size_m);
int full_size_m = size_m*sizeof(float);
float* h_M = (float*)malloc(full_size_m);
for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
/* dimension of array */
int size = 0;
scanf("%d", &size);
int full_size = sizeof(float)*size;
/* Allocate host memory */
float* h_N = (float*)malloc(full_size);
float* h_P = (float*)malloc(full_size);
for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device memory */
/*************************/
float* d_N,*d_P;
cudaMalloc(&d_N, full_size);
cudaMalloc(&d_P, full_size);
/******************************/
/* copy array & mask to device */
/******************************/
cudaMemcpy(d_N,h_N,full_size,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(M,h_M,full_size_m);
/****************/
/** CALL KERNEL */
/****************/
int threadsPerBlock = size;
Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_P, d_P, full_size, cudaMemcpyDeviceToHost);
/*******************************************/
/* Testing output, don't change anything! */
/*******************************************/
test(h_P, size);
free(h_N);
free(h_P);
cudaFree(d_N);
cudaFree(d_P);
return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
int i=0;
for(i=0;i<length;++i){
printf("%.1f ", C[i]);
}
printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_001980fe_00000000-6_cuda1DCovolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1f "
.LC1:
.string "\n"
.text
.globl _Z4testPfi
.type _Z4testPfi, @function
_Z4testPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4testPfi, .-_Z4testPfi
.section .rodata.str1.1
.LC2:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L11
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
.type _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii, @function
_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Conv1DPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii, .-_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
.globl _Z6Conv1DPfS_ii
.type _Z6Conv1DPfS_ii, @function
_Z6Conv1DPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6Conv1DPfS_ii, .-_Z6Conv1DPfS_ii
.section .rodata.str1.1
.LC3:
.string "%d"
.LC4:
.string "%f"
.LC5:
.string "Kernel Invoking"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, 24(%rsp)
leaq 24(%rsp), %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
movl 24(%rsp), %ebx
leal 0(,%rbx,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L21
movq %rax, %rbp
movl $0, %ebx
leaq .LC4(%rip), %r12
.L22:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 24(%rsp)
jg .L22
.L21:
movl $0, 28(%rsp)
leaq 28(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %ebx
leal 0(,%rbx,4), %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L23
movl $0, %ebx
leaq .LC4(%rip), %r13
.L24:
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 28(%rsp)
jg .L24
.L23:
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
leaq _ZL1M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl 28(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
leaq .LC5(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl 28(%rsp), %esi
movq %r14, %rdi
call _Z4testPfi
movq (%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6Conv1DPfS_ii"
.LC7:
.string "M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Conv1DPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $44, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1M
.comm _ZL1M,44,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
int n = Mask_Width/2;
/******************************************************************/
/* Your TODO-1 starts here: */
/* Load the data with halo from N to the shared memory N_ds */
/* remember that you need to load: */
/* + the left halo */
/* + the data */
/* + the right halo */
/******************************************************************/
int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
if(threadIdx.x>=blockDim.x-n)
N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
if(threadIdx.x<n)
N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
__syncthreads();
/***********************/
/*Your TODO-1 ends here*/
/***********************/
/******************************************************************/
/* Your TODO-2 starts here: */
/* Calculate the value coresponding to each thread */
/* The result is saved into the array P */
/* It should be noted that the mask M is already copy to the */
/* constant memory */
/******************************************************************/
float Pvalue = 0;
for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
P[i] = Pvalue;
/***********************/
/*Your TODO-2 ends here*/
/***********************/
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/*******************/
/** READING INPUT **/
/*******************/
/* dimension of mask */
int size_m = 0;
scanf("%d", &size_m);
int full_size_m = size_m*sizeof(float);
float* h_M = (float*)malloc(full_size_m);
for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
/* dimension of array */
int size = 0;
scanf("%d", &size);
int full_size = sizeof(float)*size;
/* Allocate host memory */
float* h_N = (float*)malloc(full_size);
float* h_P = (float*)malloc(full_size);
for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device memory */
/*************************/
float* d_N,*d_P;
cudaMalloc(&d_N, full_size);
cudaMalloc(&d_P, full_size);
/******************************/
/* copy array & mask to device */
/******************************/
cudaMemcpy(d_N,h_N,full_size,cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(M,h_M,full_size_m);
/****************/
/** CALL KERNEL */
/****************/
int threadsPerBlock = size;
Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
cudaMemcpy(h_P, d_P, full_size, cudaMemcpyDeviceToHost);
/*******************************************/
/* Testing output, don't change anything! */
/*******************************************/
test(h_P, size);
free(h_N);
free(h_P);
cudaFree(d_N);
cudaFree(d_P);
return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
int i=0;
for(i=0;i<length;++i){
printf("%.1f ", C[i]);
}
printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
int n = Mask_Width/2;
/******************************************************************/
/* Your TODO-1 starts here: */
/* Load the data with halo from N to the shared memory N_ds */
/* remember that you need to load: */
/* + the left halo */
/* + the data */
/* + the right halo */
/******************************************************************/
int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
if(threadIdx.x>=blockDim.x-n)
N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
if(threadIdx.x<n)
N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
__syncthreads();
/***********************/
/*Your TODO-1 ends here*/
/***********************/
/******************************************************************/
/* Your TODO-2 starts here: */
/* Calculate the value coresponding to each thread */
/* The result is saved into the array P */
/* It should be noted that the mask M is already copy to the */
/* constant memory */
/******************************************************************/
float Pvalue = 0;
for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
P[i] = Pvalue;
/***********************/
/*Your TODO-2 ends here*/
/***********************/
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/*******************/
/** READING INPUT **/
/*******************/
/* dimension of mask */
int size_m = 0;
scanf("%d", &size_m);
int full_size_m = size_m*sizeof(float);
float* h_M = (float*)malloc(full_size_m);
for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
/* dimension of array */
int size = 0;
scanf("%d", &size);
int full_size = sizeof(float)*size;
/* Allocate host memory */
float* h_N = (float*)malloc(full_size);
float* h_P = (float*)malloc(full_size);
for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device memory */
/*************************/
float* d_N,*d_P;
hipMalloc(&d_N, full_size);
hipMalloc(&d_P, full_size);
/******************************/
/* copy array & mask to device */
/******************************/
hipMemcpy(d_N,h_N,full_size,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,full_size_m);
/****************/
/** CALL KERNEL */
/****************/
int threadsPerBlock = size;
Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_P, d_P, full_size, hipMemcpyDeviceToHost);
/*******************************************/
/* Testing output, don't change anything! */
/*******************************************/
test(h_P, size);
free(h_N);
free(h_P);
hipFree(d_N);
hipFree(d_P);
return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
int i=0;
for(i=0;i<length;++i){
printf("%.1f ", C[i]);
}
printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
int n = Mask_Width/2;
/******************************************************************/
/* Your TODO-1 starts here: */
/* Load the data with halo from N to the shared memory N_ds */
/* remember that you need to load: */
/* + the left halo */
/* + the data */
/* + the right halo */
/******************************************************************/
int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
if(threadIdx.x>=blockDim.x-n)
N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
if(threadIdx.x<n)
N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
__syncthreads();
/***********************/
/*Your TODO-1 ends here*/
/***********************/
/******************************************************************/
/* Your TODO-2 starts here: */
/* Calculate the value coresponding to each thread */
/* The result is saved into the array P */
/* It should be noted that the mask M is already copy to the */
/* constant memory */
/******************************************************************/
float Pvalue = 0;
for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
P[i] = Pvalue;
/***********************/
/*Your TODO-2 ends here*/
/***********************/
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/*******************/
/** READING INPUT **/
/*******************/
/* dimension of mask */
int size_m = 0;
scanf("%d", &size_m);
int full_size_m = size_m*sizeof(float);
float* h_M = (float*)malloc(full_size_m);
for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
/* dimension of array */
int size = 0;
scanf("%d", &size);
int full_size = sizeof(float)*size;
/* Allocate host memory */
float* h_N = (float*)malloc(full_size);
float* h_P = (float*)malloc(full_size);
for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device memory */
/*************************/
float* d_N,*d_P;
hipMalloc(&d_N, full_size);
hipMalloc(&d_P, full_size);
/******************************/
/* copy array & mask to device */
/******************************/
hipMemcpy(d_N,h_N,full_size,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,full_size_m);
/****************/
/** CALL KERNEL */
/****************/
int threadsPerBlock = size;
Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_P, d_P, full_size, hipMemcpyDeviceToHost);
/*******************************************/
/* Testing output, don't change anything! */
/*******************************************/
test(h_P, size);
free(h_N);
free(h_P);
hipFree(d_N);
hipFree(d_P);
return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
int i=0;
for(i=0;i<length;++i){
printf("%.1f ", C[i]);
}
printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6Conv1DPfS_ii
.globl _Z6Conv1DPfS_ii
.p2align 8
.type _Z6Conv1DPfS_ii,@function
_Z6Conv1DPfS_ii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s6, 1
s_sub_i32 s7, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_4
s_add_i32 s8, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s8, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s5, v1
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_lshl_u32 v4, s6, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_8
s_load_b32 s8, s[0:1], 0x14
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_add_lshl_u32 v3, s5, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
v_lshlrev_b32_e32 v2, 2, v0
v_mov_b32_e32 v0, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, M@rel32@lo+4
s_addc_u32 s3, s3, M@rel32@hi+12
.LBB0_10:
ds_load_b32 v3, v2
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
v_add_nc_u32_e32 v2, 4, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v3
s_cbranch_scc0 .LBB0_10
s_branch .LBB0_12
.LBB0_11:
v_mov_b32_e32 v0, 0
.LBB0_12:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6Conv1DPfS_ii
.amdhsa_group_segment_fixed_size 168
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6Conv1DPfS_ii, .Lfunc_end0-_Z6Conv1DPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected M
.type M,@object
.section .bss,"aw",@nobits
.globl M
.p2align 4, 0x0
M:
.zero 44
.size M, 44
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 168
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6Conv1DPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6Conv1DPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 32
#define MAX_MASK_WIDTH 11
/*Declare the constant memory*/
__constant__ float M[MAX_MASK_WIDTH];
/***********************/
/** TODO, write KERNEL */
/***********************/
__global__ void Conv1D(float* N, float* P, int Mask_Width, int Width)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ float N_ds[MAX_TILE_SIZE+MAX_MASK_WIDTH-1];
int n = Mask_Width/2;
/******************************************************************/
/* Your TODO-1 starts here: */
/* Load the data with halo from N to the shared memory N_ds */
/* remember that you need to load: */
/* + the left halo */
/* + the data */
/* + the right halo */
/******************************************************************/
int halo_index_left = (blockIdx.x-1) *blockDim.x + threadIdx.x;
int halo_index_right = (blockIdx.x+1)*blockDim.x + threadIdx.x;
if(threadIdx.x>=blockDim.x-n)
N_ds[threadIdx.x-(blockDim.x-n)] = (halo_index_left <0) ? 0:N[halo_index_left];
N_ds[n+threadIdx.x] = N[blockIdx.x*blockDim.x+threadIdx.x];
if(threadIdx.x<n)
N_ds[n+blockDim.x+threadIdx.x] = (halo_index_right >= Width) ? 0:N[halo_index_right];
__syncthreads();
/***********************/
/*Your TODO-1 ends here*/
/***********************/
/******************************************************************/
/* Your TODO-2 starts here: */
/* Calculate the value coresponding to each thread */
/* The result is saved into the array P */
/* It should be noted that the mask M is already copy to the */
/* constant memory */
/******************************************************************/
float Pvalue = 0;
for(int j=0;j<Mask_Width;j++) Pvalue += N_ds[threadIdx.x+j]*M[j];
P[i] = Pvalue;
/***********************/
/*Your TODO-2 ends here*/
/***********************/
}
/**/
void test(float* C, int length);
void checkCUDAError(const char *msg);
/**/
int main(int argc, char* argv[])
{
int i;
/*******************/
/** READING INPUT **/
/*******************/
/* dimension of mask */
int size_m = 0;
scanf("%d", &size_m);
int full_size_m = size_m*sizeof(float);
float* h_M = (float*)malloc(full_size_m);
for(i=0;i<size_m;++i){ scanf("%f", &h_M[i]);}
/* dimension of array */
int size = 0;
scanf("%d", &size);
int full_size = sizeof(float)*size;
/* Allocate host memory */
float* h_N = (float*)malloc(full_size);
float* h_P = (float*)malloc(full_size);
for(i=0;i<size;++i){ scanf("%f", &h_N[i]);}
/********************/
/** FINISHED INPUT **/
/********************/
/*************************/
/* allocate device memory */
/*************************/
float* d_N,*d_P;
hipMalloc(&d_N, full_size);
hipMalloc(&d_P, full_size);
/******************************/
/* copy array & mask to device */
/******************************/
hipMemcpy(d_N,h_N,full_size,hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(M),h_M,full_size_m);
/****************/
/** CALL KERNEL */
/****************/
int threadsPerBlock = size;
Conv1D<<<1, threadsPerBlock>>>(d_N, d_P,size_m, size);
checkCUDAError("Kernel Invoking");
/**************************/
/* copy result back */
/**************************/
hipMemcpy(h_P, d_P, full_size, hipMemcpyDeviceToHost);
/*******************************************/
/* Testing output, don't change anything! */
/*******************************************/
test(h_P, size);
free(h_N);
free(h_P);
hipFree(d_N);
hipFree(d_P);
return 0;
}
/* to test the input, don't change anything! */
void test(float* C, int length){
int i=0;
for(i=0;i<length;++i){
printf("%.1f ", C[i]);
}
printf("\n");
}
/*function to test CUDA command*/
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.file "cuda1DCovolution.hip"
.globl _Z21__device_stub__Conv1DPfS_ii # -- Begin function _Z21__device_stub__Conv1DPfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__Conv1DPfS_ii,@function
_Z21__device_stub__Conv1DPfS_ii: # @_Z21__device_stub__Conv1DPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Conv1DPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Conv1DPfS_ii, .Lfunc_end0-_Z21__device_stub__Conv1DPfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %ebx
leal (,%rbx,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movq %r15, 40(%rsp) # 8-byte Spill
movl $0, 8(%rsp)
leaq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebx
leal (,%rbx,4), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %ebx, %ebx
jle .LBB1_6
# %bb.4: # %.lr.ph30.preheader
movq %r13, %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph30
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movslq 8(%rsp), %rax
addq $4, %rbp
cmpq %rax, %rbx
jl .LBB1_5
.LBB1_6: # %._crit_edge31
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movl $M, %edi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl 8(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl 12(%rsp), %edx
movl 8(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %edx, 36(%rsp)
movl %esi, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6Conv1DPfS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.9: # %_Z14checkCUDAErrorPKc.exit
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl 8(%rsp), %r15d
testl %r15d, %r15d
jle .LBB1_12
# %bb.10: # %.lr.ph.preheader.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB1_11
.LBB1_12: # %_Z4testPfi.exit
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl _Z4testPfi # -- Begin function _Z4testPfi
.p2align 4, 0x90
.type _Z4testPfi,@function
_Z4testPfi: # @_Z4testPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z4testPfi, .Lfunc_end3-_Z4testPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Conv1DPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $M, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $44, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.local M
.comm M,44,16
.type _Z6Conv1DPfS_ii,@object # @_Z6Conv1DPfS_ii
.section .rodata,"a",@progbits
.globl _Z6Conv1DPfS_ii
.p2align 3, 0x0
_Z6Conv1DPfS_ii:
.quad _Z21__device_stub__Conv1DPfS_ii
.size _Z6Conv1DPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel Invoking"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%.1f "
.size .L.str.3, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6Conv1DPfS_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "M"
.size .L__unnamed_2, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Conv1DPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym _Z6Conv1DPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6Conv1DPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0a7624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R8, c[0x0][0x0] ; /* 0x0000000000087a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e620000002500 */
/*0060*/ BSSY B0, 0x1b0 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0070*/ LEA.HI R2, R10, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c000a027a11 */
/* 0x000fc800078f08ff */
/*0080*/ SHF.R.S32.HI R7, RZ, 0x1, R2 ; /* 0x00000001ff077819 */
/* 0x000fc80000011402 */
/*0090*/ IADD3 R5, -R7, c[0x0][0x0], RZ ; /* 0x0000000007057a10 */
/* 0x000fc80007ffe1ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x001fe20003f06070 */
/*00b0*/ IMAD R3, R9.reuse, R8, -c[0x0][0x0] ; /* 0x8000000009037624 */
/* 0x042fe400078e0208 */
/*00c0*/ IMAD R2, R9, c[0x0][0x0], R0.reuse ; /* 0x0000000009027a24 */
/* 0x100fe400078e0200 */
/*00d0*/ IMAD.IADD R3, R3, 0x1, R0 ; /* 0x0000000103037824 */
/* 0x000fca00078e0200 */
/*00e0*/ LEA R6, R8, R3, 0x1 ; /* 0x0000000308067211 */
/* 0x000fc600078e08ff */
/*00f0*/ @!P0 BRA 0x1a0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0110*/ BSSY B1, 0x190 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0120*/ IADD3 R9, R7, -c[0x0][0x0], R0 ; /* 0x8000000007097a10 */
/* 0x000fe20007ffe000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd400078e00ff */
/*0140*/ @!P0 BRA 0x180 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0150*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0160*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e0204 */
/*0170*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000164000c1e1900 */
/*0180*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0190*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0203e40000004800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x003fcc00078e0003 */
/*01d0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R9, R7, R0, RZ ; /* 0x0000000007097210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ BSSY B0, 0x2e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fc60003f06070 */
/*0210*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041f40000004800 */
/*0220*/ @P0 BRA 0x2d0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x174], PT ; /* 0x00005d0006007a0c */
/* 0x000fe20003f06270 */
/*0240*/ IMAD.SHL.U32 R9, R9, 0x4, RZ ; /* 0x0000000409097824 */
/* 0x001fe200078e00ff */
/*0250*/ BSSY B1, 0x2c0 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0270*/ LEA R9, R8, R9, 0x2 ; /* 0x0000000908097211 */
/* 0x000fce00078e10ff */
/*0280*/ @P0 BRA 0x2b0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.WIDE R4, R6, R3, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fcc00078e0203 */
/*02a0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000164000c1e1900 */
/*02b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02c0*/ STS [R9], R4 ; /* 0x0000000409007388 */
/* 0x0203e40000000800 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe40003f06270 */
/*0300*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fd60000000f00 */
/*0310*/ @!P0 BRA 0xab0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0320*/ IADD3 R4, R10, -0x1, RZ ; /* 0xffffffff0a047810 */
/* 0x003fe20007ffe0ff */
/*0330*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0340*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0360*/ LOP3.LUT R4, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a047812 */
/* 0x000fd600078ec0ff */
/*0370*/ @!P0 BRA 0x9e0 ; /* 0x0000066000008947 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R6, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fe20007ffe1ff */
/*0390*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03a0*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*03b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*03c0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*03d0*/ LEA R5, R0, 0x8, 0x2 ; /* 0x0000000800057811 */
/* 0x000fd600078e10ff */
/*03e0*/ @!P0 BRA 0x8e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0400*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0410*/ @!P1 BRA 0x710 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0420*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0430*/ LDS R13, [R5+-0x8] ; /* 0xfffff800050d7984 */
/* 0x000e220000000800 */
/*0440*/ ULDC.64 UR8, c[0x3][UR5] ; /* 0x00c0000005087abb */
/* 0x000fe20008000a00 */
/*0450*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0470*/ LDS R10, [R5+-0x4] ; /* 0xfffffc00050a7984 */
/* 0x000e640000000800 */
/*0480*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0490*/ LDS R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000ea80000000800 */
/*04a0*/ LDS R15, [R5+0x4] ; /* 0x00000400050f7984 */
/* 0x000ee80000000800 */
/*04b0*/ LDS R17, [R5+0x8] ; /* 0x0000080005117984 */
/* 0x000f280000000800 */
/*04c0*/ LDS R19, [R5+0xc] ; /* 0x00000c0005137984 */
/* 0x000f680000000800 */
/*04d0*/ LDS R21, [R5+0x10] ; /* 0x0000100005157984 */
/* 0x000f680000000800 */
/*04e0*/ LDS R11, [R5+0x14] ; /* 0x00001400050b7984 */
/* 0x000f680000000800 */
/*04f0*/ LDS R9, [R5+0x18] ; /* 0x0000180005097984 */
/* 0x000f680000000800 */
/*0500*/ LDS R7, [R5+0x1c] ; /* 0x00001c0005077984 */
/* 0x000f620000000800 */
/*0510*/ FFMA R13, R13, UR8, R8 ; /* 0x000000080d0d7c23 */
/* 0x001fc60008000008 */
/*0520*/ LDS R14, [R5+0x28] ; /* 0x00002800050e7984 */
/* 0x000fe20000000800 */
/*0530*/ FFMA R13, R10, UR9, R13 ; /* 0x000000090a0d7c23 */
/* 0x002fc6000800000d */
/*0540*/ LDS R8, [R5+0x20] ; /* 0x0000200005087984 */
/* 0x000e220000000800 */
/*0550*/ ULDC.64 UR8, c[0x3][UR5+0x8] ; /* 0x00c0020005087abb */
/* 0x000fe40008000a00 */
/*0560*/ FFMA R12, R12, UR8, R13 ; /* 0x000000080c0c7c23 */
/* 0x004fe2000800000d */
/*0570*/ LDS R10, [R5+0x24] ; /* 0x00002400050a7984 */
/* 0x000e660000000800 */
/*0580*/ FFMA R12, R15, UR9, R12 ; /* 0x000000090f0c7c23 */
/* 0x008fe2000800000c */
/*0590*/ LDS R16, [R5+0x2c] ; /* 0x00002c0005107984 */
/* 0x000ea20000000800 */
/*05a0*/ ULDC.64 UR8, c[0x3][UR5+0x10] ; /* 0x00c0040005087abb */
/* 0x000fe40008000a00 */
/*05b0*/ FFMA R12, R17, UR8, R12 ; /* 0x00000008110c7c23 */
/* 0x010fe2000800000c */
/*05c0*/ LDS R18, [R5+0x30] ; /* 0x0000300005127984 */
/* 0x000ee60000000800 */
/*05d0*/ FFMA R12, R19, UR9, R12 ; /* 0x00000009130c7c23 */
/* 0x020fe2000800000c */
/*05e0*/ LDS R20, [R5+0x34] ; /* 0x0000340005147984 */
/* 0x0009620000000800 */
/*05f0*/ ULDC.64 UR8, c[0x3][UR5+0x18] ; /* 0x00c0060005087abb */
/* 0x000fc40008000a00 */
/*0600*/ FFMA R12, R21, UR8, R12 ; /* 0x00000008150c7c23 */
/* 0x000fc8000800000c */
/*0610*/ FFMA R12, R11, UR9, R12 ; /* 0x000000090b0c7c23 */
/* 0x000fe2000800000c */
/*0620*/ ULDC.64 UR8, c[0x3][UR5+0x20] ; /* 0x00c0080005087abb */
/* 0x000fe20008000a00 */
/*0630*/ IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005057810 */
/* 0x010fe40007ffe0ff */
/*0640*/ FFMA R12, R9, UR8, R12 ; /* 0x00000008090c7c23 */
/* 0x000fc8000800000c */
/*0650*/ FFMA R7, R7, UR9, R12 ; /* 0x0000000907077c23 */
/* 0x000fe2000800000c */
/*0660*/ ULDC.64 UR8, c[0x3][UR5+0x28] ; /* 0x00c00a0005087abb */
/* 0x000fc60008000a00 */
/*0670*/ FFMA R7, R8, UR8, R7 ; /* 0x0000000808077c23 */
/* 0x001fc80008000007 */
/*0680*/ FFMA R7, R10, UR9, R7 ; /* 0x000000090a077c23 */
/* 0x002fe20008000007 */
/*0690*/ ULDC.64 UR8, c[0x3][UR5+0x30] ; /* 0x00c00c0005087abb */
/* 0x000fc60008000a00 */
/*06a0*/ FFMA R7, R14, UR8, R7 ; /* 0x000000080e077c23 */
/* 0x000fc80008000007 */
/*06b0*/ FFMA R7, R16, UR9, R7 ; /* 0x0000000910077c23 */
/* 0x004fe20008000007 */
/*06c0*/ ULDC.64 UR8, c[0x3][UR5+0x38] ; /* 0x00c00e0005087abb */
/* 0x000fe40008000a00 */
/*06d0*/ UIADD3 UR5, UR5, 0x40, URZ ; /* 0x0000004005057890 */
/* 0x000fe2000fffe03f */
/*06e0*/ FFMA R7, R18, UR8, R7 ; /* 0x0000000812077c23 */
/* 0x008fc80008000007 */
/*06f0*/ FFMA R8, R20, UR9, R7 ; /* 0x0000000914087c23 */
/* 0x020fe20008000007 */
/*0700*/ @P1 BRA 0x430 ; /* 0xfffffd2000001947 */
/* 0x000fea000383ffff */
/*0710*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0720*/ @!P1 BRA 0x8c0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0730*/ LDS R7, [R5+-0x8] ; /* 0xfffff80005077984 */
/* 0x000e220000000800 */
/*0740*/ ULDC.64 UR8, c[0x3][UR5] ; /* 0x00c0000005087abb */
/* 0x000fe20008000a00 */
/*0750*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0760*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0770*/ LDS R10, [R5+-0x4] ; /* 0xfffffc00050a7984 */
/* 0x000e620000000800 */
/*0780*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*0790*/ LDS R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000ea80000000800 */
/*07a0*/ LDS R14, [R5+0x4] ; /* 0x00000400050e7984 */
/* 0x000ee80000000800 */
/*07b0*/ LDS R16, [R5+0x8] ; /* 0x0000080005107984 */
/* 0x000f280000000800 */
/*07c0*/ LDS R18, [R5+0xc] ; /* 0x00000c0005127984 */
/* 0x000f680000000800 */
/*07d0*/ LDS R20, [R5+0x10] ; /* 0x0000100005147984 */
/* 0x000f680000000800 */
/*07e0*/ LDS R22, [R5+0x14] ; /* 0x0000140005167984 */
/* 0x0001640000000800 */
/*07f0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x001fe20007ffe0ff */
/*0800*/ FFMA R7, R7, UR8, R8 ; /* 0x0000000807077c23 */
/* 0x000fc80008000008 */
/*0810*/ FFMA R7, R10, UR9, R7 ; /* 0x000000090a077c23 */
/* 0x002fe20008000007 */
/*0820*/ ULDC.64 UR8, c[0x3][UR5+0x8] ; /* 0x00c0020005087abb */
/* 0x000fc60008000a00 */
/*0830*/ FFMA R7, R12, UR8, R7 ; /* 0x000000080c077c23 */
/* 0x004fc80008000007 */
/*0840*/ FFMA R7, R14, UR9, R7 ; /* 0x000000090e077c23 */
/* 0x008fe20008000007 */
/*0850*/ ULDC.64 UR8, c[0x3][UR5+0x10] ; /* 0x00c0040005087abb */
/* 0x000fc60008000a00 */
/*0860*/ FFMA R7, R16, UR8, R7 ; /* 0x0000000810077c23 */
/* 0x010fc80008000007 */
/*0870*/ FFMA R7, R18, UR9, R7 ; /* 0x0000000912077c23 */
/* 0x020fe20008000007 */
/*0880*/ ULDC.64 UR8, c[0x3][UR5+0x18] ; /* 0x00c0060005087abb */
/* 0x000fe40008000a00 */
/*0890*/ UIADD3 UR5, UR5, 0x20, URZ ; /* 0x0000002005057890 */
/* 0x000fe2000fffe03f */
/*08a0*/ FFMA R7, R20, UR8, R7 ; /* 0x0000000814077c23 */
/* 0x000fc80008000007 */
/*08b0*/ FFMA R8, R22, UR9, R7 ; /* 0x0000000916087c23 */
/* 0x000fe40008000007 */
/*08c0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08d0*/ @!P0 BRA 0x9e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*08e0*/ LDS R7, [R5+-0x8] ; /* 0xfffff80005077984 */
/* 0x000e220000000800 */
/*08f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0900*/ ULDC.64 UR8, c[0x3][UR5] ; /* 0x00c0000005087abb */
/* 0x000fe40008000a00 */
/*0910*/ LDS R10, [R5+-0x4] ; /* 0xfffffc00050a7984 */
/* 0x000e620000000800 */
/*0920*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0930*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0940*/ LDS R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000ea80000000800 */
/*0950*/ LDS R14, [R5+0x4] ; /* 0x00000400050e7984 */
/* 0x0007240000000800 */
/*0960*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x008fe20007ffe0ff */
/*0970*/ FFMA R7, R7, UR8, R8 ; /* 0x0000000807077c23 */
/* 0x001fc80008000008 */
/*0980*/ FFMA R7, R10, UR9, R7 ; /* 0x000000090a077c23 */
/* 0x002fe20008000007 */
/*0990*/ ULDC.64 UR8, c[0x3][UR5+0x8] ; /* 0x00c0020005087abb */
/* 0x000fe40008000a00 */
/*09a0*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe2000fffe03f */
/*09b0*/ FFMA R7, R12, UR8, R7 ; /* 0x000000080c077c23 */
/* 0x004fc80008000007 */
/*09c0*/ FFMA R8, R14, UR9, R7 ; /* 0x000000090e087c23 */
/* 0x010fe20008000007 */
/*09d0*/ @P0 BRA 0x8e0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*09e0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*09f0*/ @!P0 BRA 0xab0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0a00*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fe2000fffe0ff */
/*0a10*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fc6000800063f */
/*0a20*/ SHF.L.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007819 */
/* 0x000fce00000006ff */
/*0a30*/ LDS R5, [R0] ; /* 0x0000000000057984 */
/* 0x0000620000000800 */
/*0a40*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ ULDC UR4, c[0x3][UR5] ; /* 0x00c0000005047abb */
/* 0x000fe40008000800 */
/*0a60*/ UIADD3 UR5, UR5, 0x4, URZ ; /* 0x0000000405057890 */
/* 0x000fe2000fffe03f */
/*0a70*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0a80*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0a90*/ FFMA R8, R5, UR4, R8 ; /* 0x0000000405087c23 */
/* 0x002fd40008000008 */
/*0aa0*/ @P0 BRA 0xa30 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0ac0*/ STG.E [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x000fe2000c101906 */
/*0ad0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6Conv1DPfS_ii
.globl _Z6Conv1DPfS_ii
.p2align 8
.type _Z6Conv1DPfS_ii,@function
_Z6Conv1DPfS_ii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s6, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s6, s6, 1
s_sub_i32 s7, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s7, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_4
s_add_i32 s8, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s8, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s8, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s5, v1
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_lshl_u32 v4, s6, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB0_8
s_load_b32 s8, s[0:1], 0x14
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_7
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_add_lshl_u32 v3, s5, v0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_lt_i32 s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
v_lshlrev_b32_e32 v2, 2, v0
v_mov_b32_e32 v0, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, M@rel32@lo+4
s_addc_u32 s3, s3, M@rel32@hi+12
.LBB0_10:
ds_load_b32 v3, v2
s_load_b32 s5, s[2:3], 0x0
s_add_i32 s4, s4, -1
v_add_nc_u32_e32 v2, 4, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s5, v3
s_cbranch_scc0 .LBB0_10
s_branch .LBB0_12
.LBB0_11:
v_mov_b32_e32 v0, 0
.LBB0_12:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6Conv1DPfS_ii
.amdhsa_group_segment_fixed_size 168
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6Conv1DPfS_ii, .Lfunc_end0-_Z6Conv1DPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected M
.type M,@object
.section .bss,"aw",@nobits
.globl M
.p2align 4, 0x0
M:
.zero 44
.size M, 44
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym M
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 168
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6Conv1DPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6Conv1DPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001980fe_00000000-6_cuda1DCovolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1f "
.LC1:
.string "\n"
.text
.globl _Z4testPfi
.type _Z4testPfi, @function
_Z4testPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L4
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z4testPfi, .-_Z4testPfi
.section .rodata.str1.1
.LC2:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L11
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
.type _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii, @function
_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6Conv1DPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii, .-_Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
.globl _Z6Conv1DPfS_ii
.type _Z6Conv1DPfS_ii, @function
_Z6Conv1DPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6Conv1DPfS_ii, .-_Z6Conv1DPfS_ii
.section .rodata.str1.1
.LC3:
.string "%d"
.LC4:
.string "%f"
.LC5:
.string "Kernel Invoking"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, 24(%rsp)
leaq 24(%rsp), %rsi
leaq .LC3(%rip), %rdi
call __isoc23_scanf@PLT
movl 24(%rsp), %ebx
leal 0(,%rbx,4), %r15d
movslq %r15d, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L21
movq %rax, %rbp
movl $0, %ebx
leaq .LC4(%rip), %r12
.L22:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 24(%rsp)
jg .L22
.L21:
movl $0, 28(%rsp)
leaq 28(%rsp), %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 28(%rsp), %ebx
leal 0(,%rbx,4), %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L23
movl $0, %ebx
leaq .LC4(%rip), %r13
.L24:
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 28(%rsp)
jg .L24
.L23:
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
leaq _ZL1M(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl 28(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L25:
leaq .LC5(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movq %r12, %rdx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl 28(%rsp), %esi
movq %r14, %rdi
call _Z4testPfi
movq (%rsp), %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl 28(%rsp), %ecx
movl 24(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z29__device_stub__Z6Conv1DPfS_iiPfS_ii
jmp .L25
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6Conv1DPfS_ii"
.LC7:
.string "M"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6Conv1DPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $44, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1M(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1M
.comm _ZL1M,44,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda1DCovolution.hip"
.globl _Z21__device_stub__Conv1DPfS_ii # -- Begin function _Z21__device_stub__Conv1DPfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__Conv1DPfS_ii,@function
_Z21__device_stub__Conv1DPfS_ii: # @_Z21__device_stub__Conv1DPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6Conv1DPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__Conv1DPfS_ii, .Lfunc_end0-_Z21__device_stub__Conv1DPfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 12(%rsp), %ebx
leal (,%rbx,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movq %r15, 40(%rsp) # 8-byte Spill
movl $0, 8(%rsp)
leaq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebx
leal (,%rbx,4), %eax
movslq %eax, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %ebx, %ebx
jle .LBB1_6
# %bb.4: # %.lr.ph30.preheader
movq %r13, %rbp
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph30
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbp, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %rbx
movslq 8(%rsp), %rax
addq $4, %rbp
cmpq %rax, %rbx
jl .LBB1_5
.LBB1_6: # %._crit_edge31
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movl $M, %edi
movq 40(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl 8(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movl 12(%rsp), %edx
movl 8(%rsp), %esi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %edx, 36(%rsp)
movl %esi, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6Conv1DPfS_ii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.9: # %_Z14checkCUDAErrorPKc.exit
movq 16(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl 8(%rsp), %r15d
testl %r15d, %r15d
jle .LBB1_12
# %bb.10: # %.lr.ph.preheader.i
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r15
jne .LBB1_11
.LBB1_12: # %_Z4testPfi.exit
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movl $.L.str.2, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB2_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14checkCUDAErrorPKc, .Lfunc_end2-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl _Z4testPfi # -- Begin function _Z4testPfi
.p2align 4, 0x90
.type _Z4testPfi,@function
_Z4testPfi: # @_Z4testPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z4testPfi, .Lfunc_end3-_Z4testPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6Conv1DPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $M, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $44, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type M,@object # @M
.local M
.comm M,44,16
.type _Z6Conv1DPfS_ii,@object # @_Z6Conv1DPfS_ii
.section .rodata,"a",@progbits
.globl _Z6Conv1DPfS_ii
.p2align 3, 0x0
_Z6Conv1DPfS_ii:
.quad _Z21__device_stub__Conv1DPfS_ii
.size _Z6Conv1DPfS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel Invoking"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%.1f "
.size .L.str.3, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6Conv1DPfS_ii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "M"
.size .L__unnamed_2, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__Conv1DPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym M
.addrsig_sym _Z6Conv1DPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecmul(float *A, float* B, float *C, int size)
{
// Row and Column indexes:
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
// Are they bellow the maximum?
if (col < size && row < size) {
float result = 0;
for(int ix=0;ix<size;ix++) {
result += A[row*size+ix]*B[ix*size+col];
}
C[row*size+col] = result;
}
} | code for sm_80
Function : _Z6vecmulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecmul(float *A, float* B, float *C, int size)
{
// Row and Column indexes:
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
// Are they bellow the maximum?
if (col < size && row < size) {
float result = 0;
for(int ix=0;ix<size;ix++) {
result += A[row*size+ix]*B[ix*size+col];
}
C[row*size+col] = result;
}
} | .file "tmpxft_0005eb65_00000000-6_vecmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecmulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i
.globl _Z6vecmulPfS_S_i
.type _Z6vecmulPfS_S_i, @function
_Z6vecmulPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecmulPfS_S_i, .-_Z6vecmulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecmulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecmulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecmul(float *A, float* B, float *C, int size)
{
// Row and Column indexes:
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
// Are they bellow the maximum?
if (col < size && row < size) {
float result = 0;
for(int ix=0;ix<size;ix++) {
result += A[row*size+ix]*B[ix*size+col];
}
C[row*size+col] = result;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecmul(float *A, float* B, float *C, int size)
{
// Row and Column indexes:
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
// Are they bellow the maximum?
if (col < size && row < size) {
float result = 0;
for(int ix=0;ix<size;ix++) {
result += A[row*size+ix]*B[ix*size+col];
}
C[row*size+col] = result;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecmul(float *A, float* B, float *C, int size)
{
// Row and Column indexes:
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
// Are they bellow the maximum?
if (col < size && row < size) {
float result = 0;
for(int ix=0;ix<size;ix++) {
result += A[row*size+ix]*B[ix*size+col];
}
C[row*size+col] = result;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecmulPfS_S_i
.globl _Z6vecmulPfS_S_i
.p2align 8
.type _Z6vecmulPfS_S_i,@function
_Z6vecmulPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecmulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecmulPfS_S_i, .Lfunc_end0-_Z6vecmulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecmulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecmulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecmul(float *A, float* B, float *C, int size)
{
// Row and Column indexes:
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
// Are they bellow the maximum?
if (col < size && row < size) {
float result = 0;
for(int ix=0;ix<size;ix++) {
result += A[row*size+ix]*B[ix*size+col];
}
C[row*size+col] = result;
}
} | .text
.file "vecmul.hip"
.globl _Z21__device_stub__vecmulPfS_S_i # -- Begin function _Z21__device_stub__vecmulPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecmulPfS_S_i,@function
_Z21__device_stub__vecmulPfS_S_i: # @_Z21__device_stub__vecmulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecmulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecmulPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecmulPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecmulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecmulPfS_S_i,@object # @_Z6vecmulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecmulPfS_S_i
.p2align 3, 0x0
_Z6vecmulPfS_S_i:
.quad _Z21__device_stub__vecmulPfS_S_i
.size _Z6vecmulPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecmulPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecmulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecmulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecmulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecmulPfS_S_i
.globl _Z6vecmulPfS_S_i
.p2align 8
.type _Z6vecmulPfS_S_i,@function
_Z6vecmulPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecmulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecmulPfS_S_i, .Lfunc_end0-_Z6vecmulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecmulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecmulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005eb65_00000000-6_vecmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecmulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i
.globl _Z6vecmulPfS_S_i
.type _Z6vecmulPfS_S_i, @function
_Z6vecmulPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecmulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecmulPfS_S_i, .-_Z6vecmulPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecmulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecmulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecmul.hip"
.globl _Z21__device_stub__vecmulPfS_S_i # -- Begin function _Z21__device_stub__vecmulPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecmulPfS_S_i,@function
_Z21__device_stub__vecmulPfS_S_i: # @_Z21__device_stub__vecmulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecmulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecmulPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecmulPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecmulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecmulPfS_S_i,@object # @_Z6vecmulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecmulPfS_S_i
.p2align 3, 0x0
_Z6vecmulPfS_S_i:
.quad _Z21__device_stub__vecmulPfS_S_i
.size _Z6vecmulPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecmulPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecmulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecmulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
__global__ void calcPReLUKernel(const float *input, float *output, const float *weights,
int width, int height, int channels)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x >= width || y >= height) {
return;
}
output[y * width + x] = input[y * width + x] > 0 ? input[y * width + x] : input[y * width + x] * weights[y % channels];
}
void calcPReLU(const float *input, float *output, const float* weights, int batchSize, int channels,
int width, int height, cudaStream_t stream)
{
dim3 grids((width * height + 31) / 32, (batchSize * channels + 31) / 32);
dim3 blocks(32, 32);
calcPReLUKernel<<<grids, blocks, 0, stream>>>(input, output, weights, width * height, channels * batchSize, channels);
} | code for sm_80
Function : _Z15calcPReLUKernelPKfPfS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R7, c[0x0][0x178], R0 ; /* 0x00005e0007007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e020b */
/*00e0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0100*/ BSSY B0, 0x2e0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0110*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078210ff */
/*0120*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fe400008f1403 */
/*0130*/ FSETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x004fda0003f04000 */
/*0140*/ @P0 BRA 0x2d0 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0150*/ IABS R13, c[0x0][0x180] ; /* 0x00006000000d7a13 */
/* 0x000fe40000000000 */
/*0160*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*0170*/ I2F.RP R0, R13 ; /* 0x0000000d00007306 */
/* 0x000e300000209400 */
/*0180*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*01c0*/ IADD3 R6, RZ, -R5, RZ ; /* 0x80000005ff067210 */
/* 0x002fca0007ffe0ff */
/*01d0*/ IMAD R15, R6, R13, RZ ; /* 0x0000000d060f7224 */
/* 0x000fe200078e02ff */
/*01e0*/ IABS R6, R7 ; /* 0x0000000700067213 */
/* 0x000fc60000000000 */
/*01f0*/ IMAD.HI.U32 R5, R5, R15, R4 ; /* 0x0000000f05057227 */
/* 0x000fcc00078e0004 */
/*0200*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0220*/ IMAD R0, R13, R5, R6 ; /* 0x000000050d007224 */
/* 0x000fca00078e0206 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fda0003f04070 */
/*0240*/ @!P0 IADD3 R0, R0, -R13, RZ ; /* 0x8000000d00008210 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f05270 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fda0003f24070 */
/*0270*/ @!P1 IMAD.IADD R0, R0, 0x1, -R13 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a0d */
/*0280*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0290*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff008a12 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fcc00078e020b */
/*02b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FMUL R9, R9, R4 ; /* 0x0000000409097220 */
/* 0x004fe40000400000 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
__global__ void calcPReLUKernel(const float *input, float *output, const float *weights,
int width, int height, int channels)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x >= width || y >= height) {
return;
}
output[y * width + x] = input[y * width + x] > 0 ? input[y * width + x] : input[y * width + x] * weights[y % channels];
}
void calcPReLU(const float *input, float *output, const float* weights, int batchSize, int channels,
int width, int height, cudaStream_t stream)
{
dim3 grids((width * height + 31) / 32, (batchSize * channels + 31) / 32);
dim3 blocks(32, 32);
calcPReLUKernel<<<grids, blocks, 0, stream>>>(input, output, weights, width * height, channels * batchSize, channels);
} | .file "tmpxft_0004ce9d_00000000-6_calcprelu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
.type _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii, @function
_Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15calcPReLUKernelPKfPfS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii, .-_Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
.globl _Z15calcPReLUKernelPKfPfS0_iii
.type _Z15calcPReLUKernelPKfPfS0_iii, @function
_Z15calcPReLUKernelPKfPfS0_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15calcPReLUKernelPKfPfS0_iii, .-_Z15calcPReLUKernelPKfPfS0_iii
.globl _Z9calcPReLUPKfPfS0_iiiiP11CUstream_st
.type _Z9calcPReLUPKfPfS0_iiiiP11CUstream_st, @function
_Z9calcPReLUPKfPfS0_iiiiP11CUstream_st:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movl %r8d, %r12d
imull %r8d, %ecx
movl %ecx, %ebp
movl %r9d, %ebx
imull 96(%rsp), %ebx
leal 62(%rbx), %eax
movl %ebx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 8(%rsp)
leal 62(%rcx), %eax
movl %ecx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 12(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movq 104(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %r9d
movl %ebp, %r8d
movl %ebx, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9calcPReLUPKfPfS0_iiiiP11CUstream_st, .-_Z9calcPReLUPKfPfS0_iiiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15calcPReLUKernelPKfPfS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calcPReLUKernelPKfPfS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
__global__ void calcPReLUKernel(const float *input, float *output, const float *weights,
int width, int height, int channels)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x >= width || y >= height) {
return;
}
output[y * width + x] = input[y * width + x] > 0 ? input[y * width + x] : input[y * width + x] * weights[y % channels];
}
void calcPReLU(const float *input, float *output, const float* weights, int batchSize, int channels,
int width, int height, cudaStream_t stream)
{
dim3 grids((width * height + 31) / 32, (batchSize * channels + 31) / 32);
dim3 blocks(32, 32);
calcPReLUKernel<<<grids, blocks, 0, stream>>>(input, output, weights, width * height, channels * batchSize, channels);
} | #include <hip/hip_runtime.h>
__global__ void calcPReLUKernel(const float *input, float *output, const float *weights,
int width, int height, int channels)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x >= width || y >= height) {
return;
}
output[y * width + x] = input[y * width + x] > 0 ? input[y * width + x] : input[y * width + x] * weights[y % channels];
}
void calcPReLU(const float *input, float *output, const float* weights, int batchSize, int channels,
int width, int height, hipStream_t stream)
{
dim3 grids((width * height + 31) / 32, (batchSize * channels + 31) / 32);
dim3 blocks(32, 32);
calcPReLUKernel<<<grids, blocks, 0, stream>>>(input, output, weights, width * height, channels * batchSize, channels);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void calcPReLUKernel(const float *input, float *output, const float *weights,
int width, int height, int channels)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x >= width || y >= height) {
return;
}
output[y * width + x] = input[y * width + x] > 0 ? input[y * width + x] : input[y * width + x] * weights[y % channels];
}
void calcPReLU(const float *input, float *output, const float* weights, int batchSize, int channels,
int width, int height, hipStream_t stream)
{
dim3 grids((width * height + 31) / 32, (batchSize * channels + 31) / 32);
dim3 blocks(32, 32);
calcPReLUKernel<<<grids, blocks, 0, stream>>>(input, output, weights, width * height, channels * batchSize, channels);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calcPReLUKernelPKfPfS0_iii
.globl _Z15calcPReLUKernelPKfPfS0_iii
.p2align 8
.type _Z15calcPReLUKernelPKfPfS0_iii,@function
_Z15calcPReLUKernelPKfPfS0_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f32_e32 0, v3
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[0:1], 0x20
v_ashrrev_i32_e32 v6, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v6
v_xor_b32_e32 v2, v2, v6
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_xor_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s3
s_sub_i32 s4, 0, s3
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s4, v4
s_load_b64 s[4:5], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v2, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calcPReLUKernelPKfPfS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calcPReLUKernelPKfPfS0_iii, .Lfunc_end0-_Z15calcPReLUKernelPKfPfS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calcPReLUKernelPKfPfS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calcPReLUKernelPKfPfS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void calcPReLUKernel(const float *input, float *output, const float *weights,
int width, int height, int channels)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if (x >= width || y >= height) {
return;
}
output[y * width + x] = input[y * width + x] > 0 ? input[y * width + x] : input[y * width + x] * weights[y % channels];
}
void calcPReLU(const float *input, float *output, const float* weights, int batchSize, int channels,
int width, int height, hipStream_t stream)
{
dim3 grids((width * height + 31) / 32, (batchSize * channels + 31) / 32);
dim3 blocks(32, 32);
calcPReLUKernel<<<grids, blocks, 0, stream>>>(input, output, weights, width * height, channels * batchSize, channels);
} | .text
.file "calcprelu.hip"
.globl _Z30__device_stub__calcPReLUKernelPKfPfS0_iii # -- Begin function _Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.p2align 4, 0x90
.type _Z30__device_stub__calcPReLUKernelPKfPfS0_iii,@function
_Z30__device_stub__calcPReLUKernelPKfPfS0_iii: # @_Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15calcPReLUKernelPKfPfS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__calcPReLUKernelPKfPfS0_iii, .Lfunc_end0-_Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.cfi_endproc
# -- End function
.globl _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t # -- Begin function _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t
.p2align 4, 0x90
.type _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t,@function
_Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t: # @_Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %r8d, %ebx
movl %ecx, %r15d
movq %rdx, %r12
movq %rsi, %r13
imull 208(%rsp), %r14d
leal 31(%r14), %eax
leal 62(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
movq %rdi, %rbp
sarl $5, %ecx
imull %r8d, %r15d
leal 31(%r15), %eax
leal 62(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
movq 216(%rsp), %r9
sarl $5, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbp, 88(%rsp)
movq %r13, 80(%rsp)
movq %r12, 72(%rsp)
movl %r14d, 20(%rsp)
movl %r15d, 16(%rsp)
movl %ebx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15calcPReLUKernelPKfPfS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t, .Lfunc_end1-_Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calcPReLUKernelPKfPfS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calcPReLUKernelPKfPfS0_iii,@object # @_Z15calcPReLUKernelPKfPfS0_iii
.section .rodata,"a",@progbits
.globl _Z15calcPReLUKernelPKfPfS0_iii
.p2align 3, 0x0
_Z15calcPReLUKernelPKfPfS0_iii:
.quad _Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.size _Z15calcPReLUKernelPKfPfS0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15calcPReLUKernelPKfPfS0_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15calcPReLUKernelPKfPfS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15calcPReLUKernelPKfPfS0_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R7, c[0x0][0x178], R0 ; /* 0x00005e0007007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e020b */
/*00e0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0100*/ BSSY B0, 0x2e0 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0110*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078210ff */
/*0120*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fe400008f1403 */
/*0130*/ FSETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x004fda0003f04000 */
/*0140*/ @P0 BRA 0x2d0 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*0150*/ IABS R13, c[0x0][0x180] ; /* 0x00006000000d7a13 */
/* 0x000fe40000000000 */
/*0160*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*0170*/ I2F.RP R0, R13 ; /* 0x0000000d00007306 */
/* 0x000e300000209400 */
/*0180*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0190*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*01a0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*01c0*/ IADD3 R6, RZ, -R5, RZ ; /* 0x80000005ff067210 */
/* 0x002fca0007ffe0ff */
/*01d0*/ IMAD R15, R6, R13, RZ ; /* 0x0000000d060f7224 */
/* 0x000fe200078e02ff */
/*01e0*/ IABS R6, R7 ; /* 0x0000000700067213 */
/* 0x000fc60000000000 */
/*01f0*/ IMAD.HI.U32 R5, R5, R15, R4 ; /* 0x0000000f05057227 */
/* 0x000fcc00078e0004 */
/*0200*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0220*/ IMAD R0, R13, R5, R6 ; /* 0x000000050d007224 */
/* 0x000fca00078e0206 */
/*0230*/ ISETP.GT.U32.AND P0, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fda0003f04070 */
/*0240*/ @!P0 IADD3 R0, R0, -R13, RZ ; /* 0x8000000d00008210 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f05270 */
/*0260*/ ISETP.GT.U32.AND P1, PT, R13, R0, PT ; /* 0x000000000d00720c */
/* 0x000fda0003f24070 */
/*0270*/ @!P1 IMAD.IADD R0, R0, 0x1, -R13 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a0d */
/*0280*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*0290*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff008a12 */
/* 0x000fca00078e33ff */
/*02a0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fcc00078e020b */
/*02b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FMUL R9, R9, R4 ; /* 0x0000000409097220 */
/* 0x004fe40000400000 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calcPReLUKernelPKfPfS0_iii
.globl _Z15calcPReLUKernelPKfPfS0_iii
.p2align 8
.type _Z15calcPReLUKernelPKfPfS0_iii,@function
_Z15calcPReLUKernelPKfPfS0_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s2, exec_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f32_e32 0, v3
s_cbranch_execz .LBB0_3
s_load_b32 s3, s[0:1], 0x20
v_ashrrev_i32_e32 v6, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v6
v_xor_b32_e32 v2, v2, v6
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_xor_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v4, s3
s_sub_i32 s4, 0, s3
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s4, v4
s_load_b64 s[4:5], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v2, v4
v_mul_lo_u32 v4, v4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_xor_b32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v2, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calcPReLUKernelPKfPfS0_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calcPReLUKernelPKfPfS0_iii, .Lfunc_end0-_Z15calcPReLUKernelPKfPfS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calcPReLUKernelPKfPfS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calcPReLUKernelPKfPfS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004ce9d_00000000-6_calcprelu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
.type _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii, @function
_Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15calcPReLUKernelPKfPfS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii, .-_Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
.globl _Z15calcPReLUKernelPKfPfS0_iii
.type _Z15calcPReLUKernelPKfPfS0_iii, @function
_Z15calcPReLUKernelPKfPfS0_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15calcPReLUKernelPKfPfS0_iii, .-_Z15calcPReLUKernelPKfPfS0_iii
.globl _Z9calcPReLUPKfPfS0_iiiiP11CUstream_st
.type _Z9calcPReLUPKfPfS0_iiiiP11CUstream_st, @function
_Z9calcPReLUPKfPfS0_iiiiP11CUstream_st:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movl %r8d, %r12d
imull %r8d, %ecx
movl %ecx, %ebp
movl %r9d, %ebx
imull 96(%rsp), %ebx
leal 62(%rbx), %eax
movl %ebx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 8(%rsp)
leal 62(%rcx), %eax
movl %ecx, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 12(%rsp)
movl $32, 20(%rsp)
movl $32, 24(%rsp)
movq 104(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %r12d, %r9d
movl %ebp, %r8d
movl %ebx, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq %r13, %rdi
call _Z44__device_stub__Z15calcPReLUKernelPKfPfS0_iiiPKfPfS0_iii
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z9calcPReLUPKfPfS0_iiiiP11CUstream_st, .-_Z9calcPReLUPKfPfS0_iiiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15calcPReLUKernelPKfPfS0_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calcPReLUKernelPKfPfS0_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calcprelu.hip"
.globl _Z30__device_stub__calcPReLUKernelPKfPfS0_iii # -- Begin function _Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.p2align 4, 0x90
.type _Z30__device_stub__calcPReLUKernelPKfPfS0_iii,@function
_Z30__device_stub__calcPReLUKernelPKfPfS0_iii: # @_Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15calcPReLUKernelPKfPfS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__calcPReLUKernelPKfPfS0_iii, .Lfunc_end0-_Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.cfi_endproc
# -- End function
.globl _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t # -- Begin function _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t
.p2align 4, 0x90
.type _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t,@function
_Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t: # @_Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r14d
movl %r8d, %ebx
movl %ecx, %r15d
movq %rdx, %r12
movq %rsi, %r13
imull 208(%rsp), %r14d
leal 31(%r14), %eax
leal 62(%r14), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
movq %rdi, %rbp
sarl $5, %ecx
imull %r8d, %r15d
leal 31(%r15), %eax
leal 62(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
movq 216(%rsp), %r9
sarl $5, %edi
shlq $32, %rdi
orq %rcx, %rdi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbp, 88(%rsp)
movq %r13, 80(%rsp)
movq %r12, 72(%rsp)
movl %r14d, 20(%rsp)
movl %r15d, 16(%rsp)
movl %ebx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15calcPReLUKernelPKfPfS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t, .Lfunc_end1-_Z9calcPReLUPKfPfS0_iiiiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calcPReLUKernelPKfPfS0_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calcPReLUKernelPKfPfS0_iii,@object # @_Z15calcPReLUKernelPKfPfS0_iii
.section .rodata,"a",@progbits
.globl _Z15calcPReLUKernelPKfPfS0_iii
.p2align 3, 0x0
_Z15calcPReLUKernelPKfPfS0_iii:
.quad _Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.size _Z15calcPReLUKernelPKfPfS0_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15calcPReLUKernelPKfPfS0_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calcPReLUKernelPKfPfS0_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15calcPReLUKernelPKfPfS0_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<algorithm>
#include<omp.h>
#include<chrono>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/generate.h>
#include <thrust/set_operations.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include "general.cuh"
//using namespace std;
using ::std::cout;
using ::std::endl;
void basicSort(int * col1, int * col2, int c1, int c2){
int cnt = 0;
std::sort(col1, col1 + c1);
std::sort(col2, col2 + c2);
int i = 0;
int j = 0;
for(; i < c1 && j < c2;){
if (col1[i] < col2[j]){
i += 1;
}
else if (col1[i] > col2[j]){
j += 1;
} else {
i += 1;
j += 1;
cnt += 1;
}
}
cout << cnt << endl;
}
__global__ void partitionKernelSort(int * c1, int * c2,int n1, int n2, int partitions, int blocks, CustomContainer * containers1, CustomContainer * containers2){
int blockSize1 = n1 / blocks;
int p;
int idx = blockSize1 * blockIdx.x + threadIdx.x;
for (int i = idx; i < blockSize1 * (blockIdx.x + 1) && i < n1; i += blockDim.x){
p = c1[i] % partitions;
containers1->push_back(p, 0, c1[i]);
}
int blockSize2 = n2 / blocks;
idx = blockSize2 * blockIdx.x + threadIdx.x;
for (int i = idx; i < blockSize2 * (blockIdx.x + 1) && i < n2; i += blockDim.x){
p = c2[i] % partitions;
containers2->push_back(p, 0, c2[i]);
}
}
void sortParallel(int * c1, int * c2, int n1, int n2, int partitions){
// cudaEvent_t start, stop;
// cudaEventCreate(&start);
// cudaEventCreate(&stop);
float milliseconds = 0;
// cudaEventRecord(start);
thrust::device_vector<int> dCol1(c1, c1 + n1);
thrust::device_vector<int> dCol2(c2, c2 + n2);
thrust::sort(dCol1.begin(), dCol1.end());
thrust::sort(dCol2.begin(), dCol2.end());
thrust::device_vector<int> result(n1);
// int * result = 0;
// cudaMalloc(&result, sizeof(int) * n1);
thrust::device_vector<int>::iterator last = thrust::set_intersection(dCol1.begin(), dCol1.end(), dCol2.begin(), dCol2.end(), result.begin());
//cudaThreadSynchronize();
int match = thrust::distance(result.begin(), last);
// cudaEventRecord(stop);
// cudaEventSynchronize(stop);
// cudaEventElapsedTime(&milliseconds, start, stop);
cout << "Matched - " << match << endl;
}
void partitionedSortParallel(int * c1, int * c2, int n1, int n2, int partitions) {
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
thrust::device_vector<int> dCol1(c1, c1 + n1);
thrust::device_vector<int> dCol2(c2, c2 + n2);
int blocks = 80;
int blockSize = n1/1;
CustomContainer * containers1 = new CustomContainer(2 * n1/partitions, partitions, 1, NULL);
CustomContainer * containers2 = new CustomContainer(2 * n2/partitions, partitions, 1, NULL);
CustomContainer * deviceContainers1 = 0;
CustomContainer * deviceContainers2 = 0;
cudaMalloc(&deviceContainers1, sizeof(CustomContainer));
cudaMalloc(&deviceContainers2, sizeof(CustomContainer));
cudaMemcpy(&deviceContainers1->container, &containers1->container, sizeof(int *), cudaMemcpyHostToDevice);
cudaMemcpy(&deviceContainers1->meta, &containers1->meta, sizeof(int *), cudaMemcpyHostToDevice);
cudaMemcpy(&deviceContainers1->head, &containers1->head, sizeof(int *), cudaMemcpyHostToDevice);
cudaMemcpy(&deviceContainers2->container, &containers2->container, sizeof(int *), cudaMemcpyHostToDevice);
cudaMemcpy(&deviceContainers2->meta, &containers2->meta, sizeof(int *), cudaMemcpyHostToDevice);
cudaMemcpy(&deviceContainers2->head, &containers2->head, sizeof(int *), cudaMemcpyHostToDevice);
int * finalCount = 0;
cudaMalloc(&finalCount, sizeof(int)*partitions);
try{
partitionKernelSort<<<blocks, 256>>>(thrust::raw_pointer_cast(dCol1.data()),thrust::raw_pointer_cast(dCol2.data()),n1,n2, partitions, blocks, deviceContainers1, deviceContainers2);
} catch (thrust::system_error e){
std::cout << "Error: " << e.what() << std::endl;
}
cudaThreadSynchronize();
thrust::device_vector<int> result(n1);
thrust::device_vector<int>::iterator first = result.begin();
thrust::device_vector<int>::iterator last_temp = first;
for(int p = 0; p < partitions; p++){
int * col1 = containers1->getPartition(p);
int * col2 = containers2->getPartition(p);
int n1 = containers1->getPartitionSize(p);
int n2 = containers2->getPartitionSize(p);
thrust::device_vector<int> dCol1(col1, col1+n1);
thrust::device_vector<int> dCol2(col2, col2 +n2);
thrust::sort(dCol1.begin(), dCol1.end());
thrust::sort(dCol2.begin(), dCol2.end());
thrust::device_vector<int>::iterator last = thrust::set_intersection(dCol1.begin(), dCol1.end(), dCol2.begin(), dCol2.end(), last_temp);
last_temp = last;
}
//cudaThreadSynchronize();
cudaEventRecord(stop);
float milliseconds = 0;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milliseconds, start, stop);
cout << "Time elapsed: " << milliseconds << std::endl;
cout << "Matched - " << thrust::distance(result.begin(), last_temp) << endl;
} | #include <hip/hip_runtime.h>
void basicSort(int * col1, int * col2, int c1, int c2);
void partitionedSortSerial(int * c1, int * c2, int n1, int n2, int partitions);
void partitionedSortParallel(int * c1, int * c2, int n1, int n2, int partitions);
void sortParallel(int * c1, int * c2, int n1, int n2, int partitions); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void basicSort(int * col1, int * col2, int c1, int c2);
void partitionedSortSerial(int * c1, int * c2, int n1, int n2, int partitions);
void partitionedSortParallel(int * c1, int * c2, int n1, int n2, int partitions);
void sortParallel(int * c1, int * c2, int n1, int n2, int partitions); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void basicSort(int * col1, int * col2, int c1, int c2);
void partitionedSortSerial(int * c1, int * c2, int n1, int n2, int partitions);
void partitionedSortParallel(int * c1, int * c2, int n1, int n2, int partitions);
void sortParallel(int * c1, int * c2, int n1, int n2, int partitions); | .text
.file "sort_approach.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<sys/time.h>
#define A 10000
#define B 10000
#define k 10000
struct timeval start, stop,start1,stop1,start2,stop2;
__global__ void matrix_mul(int *a, int *b, int *c){
int row = (blockIdx.y*blockDim.y + threadIdx.y);
int col = (blockIdx.x*blockDim.x + threadIdx.x);
int temp=0;
for(int i = 0;i < k;i++){
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp;
}
void random_int(int *a, int b){
for(int i=0;i<b;i++){
a[i] = rand()%100;
}
}
int main(void){
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int matrix_size= A* B * sizeof(int);
cudaMalloc((void **)&d_a,matrix_size);
cudaMalloc((void **)&d_b,matrix_size);
cudaMalloc((void **)&d_c,matrix_size);
a=(int*)malloc(matrix_size);
random_int(a,A);
b=(int*)malloc(matrix_size);
random_int(b,B);
c=(int*)malloc(matrix_size);
gettimeofday(&start1,NULL);
cudaMemcpy(d_a,a,matrix_size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,matrix_size,cudaMemcpyHostToDevice);
gettimeofday(&stop1,NULL);
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
dim3 threadsPerBlock = dim3(16,16,1);
gettimeofday(&start,NULL);
matrix_mul<<<threadBlocks,threadsPerBlock>>>(d_a,d_b,d_c);
gettimeofday(&stop,NULL);
printf("GPU Execution time of kernel without memory Transfer: %lu us\n", (stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6);
float kernelTime=(stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6;
gettimeofday(&start2,NULL);
cudaMemcpy(c, d_c, matrix_size, cudaMemcpyDeviceToHost);
gettimeofday(&stop2,NULL);
float htod=(stop1.tv_sec-start1.tv_sec)+ (stop1.tv_usec-start1.tv_usec) * 1e-6;
float dtoh=(stop2.tv_sec-start2.tv_sec)+ (stop2.tv_usec-start2.tv_usec) * 1e-6;
float totaltime=htod+dtoh+kernelTime;
printf("GPU Execution Time of kernel with memory Transfer: %lu us\n",totaltime);
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z10matrix_mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x001fe200078e0200 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fc600000001ff */
/*00b0*/ IMAD R7, R7, 0x2710, RZ ; /* 0x0000271007077824 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x002fca00078e0205 */
/*00d0*/ IMAD.WIDE R2, R7, R0, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0200 */
/*00e0*/ IADD3 R2, P0, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R3, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff037210 */
/* 0x000fc800007fe4ff */
/*0100*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0110*/ LDG.E R15, [R2.64+-0x20] ; /* 0xffffe004020f7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0130*/ LDG.E R17, [R2.64+-0x1c] ; /* 0xffffe40402117981 */
/* 0x000ee4000c1e1900 */
/*0140*/ IMAD.WIDE R4, R6, 0x4, R4 ; /* 0x0000000406047825 */
/* 0x000fe400078e0204 */
/*0150*/ LDG.E R19, [R2.64+-0x18] ; /* 0xffffe80402137981 */
/* 0x000f28000c1e1900 */
/*0160*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R18, [R4.64+0x9c40] ; /* 0x009c400404127981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R20, [R4.64+0x13880] ; /* 0x0138800404147981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R22, [R2.64+-0x14] ; /* 0xffffec0402167981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R4.64+0x1d4c0] ; /* 0x01d4c00404157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R23, [R2.64+-0x10] ; /* 0xfffff00402177981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R24, [R4.64+0x27100] ; /* 0x0271000404187981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R9, [R2.64+-0xc] ; /* 0xfffff40402097981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R10, [R4.64+0x30d40] ; /* 0x030d4004040a7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff804020b7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R12, [R4.64+0x3a980] ; /* 0x03a98004040c7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R2.64+-0x4] ; /* 0xfffffc04020d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R4.64+0x445c0] ; /* 0x0445c004040e7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R26, [R2.64+0x1c] ; /* 0x00001c04021a7981 */
/* 0x000162000c1e1900 */
/*0240*/ IMAD R25, R16, R15, R25 ; /* 0x0000000f10197224 */
/* 0x004fc600078e0219 */
/*0250*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R16, [R4.64+0x4e200] ; /* 0x04e2000404107981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x008fc600078e0219 */
/*0280*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x0000e2000c1e1900 */
/*0290*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x010fc600078e0219 */
/*02a0*/ LDG.E R18, [R4.64+0x57e40] ; /* 0x057e400404127981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000122000c1e1900 */
/*02c0*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*02d0*/ LDG.E R19, [R4.64+0x61a80] ; /* 0x061a800404137981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x000fc600078e0219 */
/*0300*/ LDG.E R21, [R4.64+0x6b6c0] ; /* 0x06b6c00404157981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000162000c1e1900 */
/*0320*/ IMAD R25, R10, R9, R25 ; /* 0x000000090a197224 */
/* 0x000fc600078e0219 */
/*0330*/ LDG.E R23, [R4.64+0x75300] ; /* 0x0753000404177981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000162000c1e1900 */
/*0350*/ IMAD R27, R12, R11, R25 ; /* 0x0000000b0c1b7224 */
/* 0x000fc600078e0219 */
/*0360*/ LDG.E R9, [R4.64+0x7ef40] ; /* 0x07ef400404097981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000168000c1e1900 */
/*0380*/ LDG.E R12, [R4.64+0x88b80] ; /* 0x088b8004040c7981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R25, [R4.64+0x927c0] ; /* 0x0927c00404197981 */
/* 0x000f62000c1e1900 */
/*03a0*/ IMAD R13, R14, R13, R27 ; /* 0x0000000d0e0d7224 */
/* 0x000fe200078e021b */
/*03b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R8, 0x2710, PT ; /* 0x000027100800780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x9c400, URZ ; /* 0x0009c40006067890 */
/* 0x000fe2000ff1e03f */
/*03e0*/ IADD3 R2, P1, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fc60007f3e0ff */
/*03f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0400*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*0410*/ IMAD R13, R16, R15, R13 ; /* 0x0000000f100d7224 */
/* 0x004fc800078e020d */
/*0420*/ IMAD R13, R18, R17, R13 ; /* 0x00000011120d7224 */
/* 0x008fc800078e020d */
/*0430*/ IMAD R13, R19, R20, R13 ; /* 0x00000014130d7224 */
/* 0x010fc800078e020d */
/*0440*/ IMAD R13, R21, R22, R13 ; /* 0x00000016150d7224 */
/* 0x020fc800078e020d */
/*0450*/ IMAD R13, R23, R24, R13 ; /* 0x00000018170d7224 */
/* 0x000fc800078e020d */
/*0460*/ IMAD R9, R9, R10, R13 ; /* 0x0000000a09097224 */
/* 0x000fc800078e020d */
/*0470*/ IMAD R9, R12, R11, R9 ; /* 0x0000000b0c097224 */
/* 0x000fc800078e0209 */
/*0480*/ IMAD R25, R25, R26, R9 ; /* 0x0000001a19197224 */
/* 0x000fe200078e0209 */
/*0490*/ @P0 BRA 0x100 ; /* 0xfffffc6000000947 */
/* 0x000fea000383ffff */
/*04a0*/ IADD3 R3, R6, R7, RZ ; /* 0x0000000706037210 */
/* 0x000fca0007ffe0ff */
/*04b0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0200 */
/*04c0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<sys/time.h>
#define A 10000
#define B 10000
#define k 10000
struct timeval start, stop,start1,stop1,start2,stop2;
__global__ void matrix_mul(int *a, int *b, int *c){
int row = (blockIdx.y*blockDim.y + threadIdx.y);
int col = (blockIdx.x*blockDim.x + threadIdx.x);
int temp=0;
for(int i = 0;i < k;i++){
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp;
}
void random_int(int *a, int b){
for(int i=0;i<b;i++){
a[i] = rand()%100;
}
}
int main(void){
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int matrix_size= A* B * sizeof(int);
cudaMalloc((void **)&d_a,matrix_size);
cudaMalloc((void **)&d_b,matrix_size);
cudaMalloc((void **)&d_c,matrix_size);
a=(int*)malloc(matrix_size);
random_int(a,A);
b=(int*)malloc(matrix_size);
random_int(b,B);
c=(int*)malloc(matrix_size);
gettimeofday(&start1,NULL);
cudaMemcpy(d_a,a,matrix_size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,matrix_size,cudaMemcpyHostToDevice);
gettimeofday(&stop1,NULL);
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
dim3 threadsPerBlock = dim3(16,16,1);
gettimeofday(&start,NULL);
matrix_mul<<<threadBlocks,threadsPerBlock>>>(d_a,d_b,d_c);
gettimeofday(&stop,NULL);
printf("GPU Execution time of kernel without memory Transfer: %lu us\n", (stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6);
float kernelTime=(stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6;
gettimeofday(&start2,NULL);
cudaMemcpy(c, d_c, matrix_size, cudaMemcpyDeviceToHost);
gettimeofday(&stop2,NULL);
float htod=(stop1.tv_sec-start1.tv_sec)+ (stop1.tv_usec-start1.tv_usec) * 1e-6;
float dtoh=(stop2.tv_sec-start2.tv_sec)+ (stop2.tv_usec-start2.tv_usec) * 1e-6;
float totaltime=htod+dtoh+kernelTime;
printf("GPU Execution Time of kernel with memory Transfer: %lu us\n",totaltime);
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | .file "tmpxft_00080c52_00000000-6_Matrix_mul_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10random_intPii
.type _Z10random_intPii, @function
_Z10random_intPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10random_intPii, .-_Z10random_intPii
.globl _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
.type _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_, @function
_Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_, .-_Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
.globl _Z10matrix_mulPiS_S_
.type _Z10matrix_mulPiS_S_, @function
_Z10matrix_mulPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10matrix_mulPiS_S_, .-_Z10matrix_mulPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU Execution time of kernel without memory Transfer: %lu us\n"
.align 8
.LC2:
.string "GPU Execution Time of kernel with memory Transfer: %lu us\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $10000, %esi
movq %rax, %rdi
call _Z10random_intPii
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $10000, %esi
movq %rax, %rdi
call _Z10random_intPii
movl $400000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %esi
leaq start1(%rip), %rdi
call gettimeofday@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
leaq stop1(%rip), %rdi
call gettimeofday@PLT
movl $625, 48(%rsp)
movl $625, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
leaq start(%rip), %rdi
call gettimeofday@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
leaq stop(%rip), %rdi
call gettimeofday@PLT
movq 8+stop(%rip), %rax
subq 8+start(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq stop(%rip), %rax
subq start(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8+stop(%rip), %rax
subq 8+start(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq stop(%rip), %rax
subq start(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
pxor %xmm3, %xmm3
cvtsd2ss %xmm0, %xmm3
movss %xmm3, 12(%rsp)
movl $0, %esi
leaq start2(%rip), %rdi
call gettimeofday@PLT
movl $2, %ecx
movl $400000000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
leaq stop2(%rip), %rdi
call gettimeofday@PLT
movq 8+stop1(%rip), %rax
subq 8+start1(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq stop1(%rip), %rax
subq start1(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8+stop2(%rip), %rax
subq 8+start2(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC0(%rip), %xmm1
movq stop2(%rip), %rax
subq start2(%rip), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
addss %xmm1, %xmm0
addss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z10matrix_mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl stop2
.bss
.align 16
.type stop2, @object
.size stop2, 16
stop2:
.zero 16
.globl start2
.align 16
.type start2, @object
.size start2, 16
start2:
.zero 16
.globl stop1
.align 16
.type stop1, @object
.size stop1, 16
stop1:
.zero 16
.globl start1
.align 16
.type start1, @object
.size start1, 16
start1:
.zero 16
.globl stop
.align 16
.type stop, @object
.size stop, 16
stop:
.zero 16
.globl start
.align 16
.type start, @object
.size start, 16
start:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<sys/time.h>
#define A 10000
#define B 10000
#define k 10000
struct timeval start, stop,start1,stop1,start2,stop2;
__global__ void matrix_mul(int *a, int *b, int *c){
int row = (blockIdx.y*blockDim.y + threadIdx.y);
int col = (blockIdx.x*blockDim.x + threadIdx.x);
int temp=0;
for(int i = 0;i < k;i++){
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp;
}
void random_int(int *a, int b){
for(int i=0;i<b;i++){
a[i] = rand()%100;
}
}
int main(void){
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int matrix_size= A* B * sizeof(int);
cudaMalloc((void **)&d_a,matrix_size);
cudaMalloc((void **)&d_b,matrix_size);
cudaMalloc((void **)&d_c,matrix_size);
a=(int*)malloc(matrix_size);
random_int(a,A);
b=(int*)malloc(matrix_size);
random_int(b,B);
c=(int*)malloc(matrix_size);
gettimeofday(&start1,NULL);
cudaMemcpy(d_a,a,matrix_size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,matrix_size,cudaMemcpyHostToDevice);
gettimeofday(&stop1,NULL);
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
dim3 threadsPerBlock = dim3(16,16,1);
gettimeofday(&start,NULL);
matrix_mul<<<threadBlocks,threadsPerBlock>>>(d_a,d_b,d_c);
gettimeofday(&stop,NULL);
printf("GPU Execution time of kernel without memory Transfer: %lu us\n", (stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6);
float kernelTime=(stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6;
gettimeofday(&start2,NULL);
cudaMemcpy(c, d_c, matrix_size, cudaMemcpyDeviceToHost);
gettimeofday(&stop2,NULL);
float htod=(stop1.tv_sec-start1.tv_sec)+ (stop1.tv_usec-start1.tv_usec) * 1e-6;
float dtoh=(stop2.tv_sec-start2.tv_sec)+ (stop2.tv_usec-start2.tv_usec) * 1e-6;
float totaltime=htod+dtoh+kernelTime;
printf("GPU Execution Time of kernel with memory Transfer: %lu us\n",totaltime);
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<sys/time.h>
#define A 10000
#define B 10000
#define k 10000
struct timeval start, stop,start1,stop1,start2,stop2;
__global__ void matrix_mul(int *a, int *b, int *c){
int row = (blockIdx.y*blockDim.y + threadIdx.y);
int col = (blockIdx.x*blockDim.x + threadIdx.x);
int temp=0;
for(int i = 0;i < k;i++){
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp;
}
void random_int(int *a, int b){
for(int i=0;i<b;i++){
a[i] = rand()%100;
}
}
int main(void){
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int matrix_size= A* B * sizeof(int);
hipMalloc((void **)&d_a,matrix_size);
hipMalloc((void **)&d_b,matrix_size);
hipMalloc((void **)&d_c,matrix_size);
a=(int*)malloc(matrix_size);
random_int(a,A);
b=(int*)malloc(matrix_size);
random_int(b,B);
c=(int*)malloc(matrix_size);
gettimeofday(&start1,NULL);
hipMemcpy(d_a,a,matrix_size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,matrix_size,hipMemcpyHostToDevice);
gettimeofday(&stop1,NULL);
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
dim3 threadsPerBlock = dim3(16,16,1);
gettimeofday(&start,NULL);
matrix_mul<<<threadBlocks,threadsPerBlock>>>(d_a,d_b,d_c);
gettimeofday(&stop,NULL);
printf("GPU Execution time of kernel without memory Transfer: %lu us\n", (stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6);
float kernelTime=(stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6;
gettimeofday(&start2,NULL);
hipMemcpy(c, d_c, matrix_size, hipMemcpyDeviceToHost);
gettimeofday(&stop2,NULL);
float htod=(stop1.tv_sec-start1.tv_sec)+ (stop1.tv_usec-start1.tv_usec) * 1e-6;
float dtoh=(stop2.tv_sec-start2.tv_sec)+ (stop2.tv_usec-start2.tv_usec) * 1e-6;
float totaltime=htod+dtoh+kernelTime;
printf("GPU Execution Time of kernel with memory Transfer: %lu us\n",totaltime);
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<sys/time.h>
#define A 10000
#define B 10000
#define k 10000
struct timeval start, stop,start1,stop1,start2,stop2;
__global__ void matrix_mul(int *a, int *b, int *c){
int row = (blockIdx.y*blockDim.y + threadIdx.y);
int col = (blockIdx.x*blockDim.x + threadIdx.x);
int temp=0;
for(int i = 0;i < k;i++){
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp;
}
void random_int(int *a, int b){
for(int i=0;i<b;i++){
a[i] = rand()%100;
}
}
int main(void){
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int matrix_size= A* B * sizeof(int);
hipMalloc((void **)&d_a,matrix_size);
hipMalloc((void **)&d_b,matrix_size);
hipMalloc((void **)&d_c,matrix_size);
a=(int*)malloc(matrix_size);
random_int(a,A);
b=(int*)malloc(matrix_size);
random_int(b,B);
c=(int*)malloc(matrix_size);
gettimeofday(&start1,NULL);
hipMemcpy(d_a,a,matrix_size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,matrix_size,hipMemcpyHostToDevice);
gettimeofday(&stop1,NULL);
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
dim3 threadsPerBlock = dim3(16,16,1);
gettimeofday(&start,NULL);
matrix_mul<<<threadBlocks,threadsPerBlock>>>(d_a,d_b,d_c);
gettimeofday(&stop,NULL);
printf("GPU Execution time of kernel without memory Transfer: %lu us\n", (stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6);
float kernelTime=(stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6;
gettimeofday(&start2,NULL);
hipMemcpy(c, d_c, matrix_size, hipMemcpyDeviceToHost);
gettimeofday(&stop2,NULL);
float htod=(stop1.tv_sec-start1.tv_sec)+ (stop1.tv_usec-start1.tv_usec) * 1e-6;
float dtoh=(stop2.tv_sec-start2.tv_sec)+ (stop2.tv_usec-start2.tv_usec) * 1e-6;
float totaltime=htod+dtoh+kernelTime;
printf("GPU Execution Time of kernel with memory Transfer: %lu us\n",totaltime);
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_mulPiS_S_
.globl _Z10matrix_mulPiS_S_
.p2align 8
.type _Z10matrix_mulPiS_S_,@function
_Z10matrix_mulPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, 0x2710
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_u32 s2, 0x9c40
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v9, v8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_add_nc_u32 v3, 0x2710, v3
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 0x2710, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_mulPiS_S_, .Lfunc_end0-_Z10matrix_mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<sys/time.h>
#define A 10000
#define B 10000
#define k 10000
struct timeval start, stop,start1,stop1,start2,stop2;
__global__ void matrix_mul(int *a, int *b, int *c){
int row = (blockIdx.y*blockDim.y + threadIdx.y);
int col = (blockIdx.x*blockDim.x + threadIdx.x);
int temp=0;
for(int i = 0;i < k;i++){
temp += a[row * k + i] * b[i * k + col]; //add and multiply
}
c[row * k + col] = temp;
}
void random_int(int *a, int b){
for(int i=0;i<b;i++){
a[i] = rand()%100;
}
}
int main(void){
int *a,*b,*c;
int *d_a,*d_b,*d_c;
int matrix_size= A* B * sizeof(int);
hipMalloc((void **)&d_a,matrix_size);
hipMalloc((void **)&d_b,matrix_size);
hipMalloc((void **)&d_c,matrix_size);
a=(int*)malloc(matrix_size);
random_int(a,A);
b=(int*)malloc(matrix_size);
random_int(b,B);
c=(int*)malloc(matrix_size);
gettimeofday(&start1,NULL);
hipMemcpy(d_a,a,matrix_size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,matrix_size,hipMemcpyHostToDevice);
gettimeofday(&stop1,NULL);
dim3 threadBlocks = dim3((int) std::ceil( (double) k/16 ),(int) std::ceil ( (double) k/16),1);
dim3 threadsPerBlock = dim3(16,16,1);
gettimeofday(&start,NULL);
matrix_mul<<<threadBlocks,threadsPerBlock>>>(d_a,d_b,d_c);
gettimeofday(&stop,NULL);
printf("GPU Execution time of kernel without memory Transfer: %lu us\n", (stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6);
float kernelTime=(stop.tv_sec-start.tv_sec)+ (stop.tv_usec-start.tv_usec) * 1e-6;
gettimeofday(&start2,NULL);
hipMemcpy(c, d_c, matrix_size, hipMemcpyDeviceToHost);
gettimeofday(&stop2,NULL);
float htod=(stop1.tv_sec-start1.tv_sec)+ (stop1.tv_usec-start1.tv_usec) * 1e-6;
float dtoh=(stop2.tv_sec-start2.tv_sec)+ (stop2.tv_usec-start2.tv_usec) * 1e-6;
float totaltime=htod+dtoh+kernelTime;
printf("GPU Execution Time of kernel with memory Transfer: %lu us\n",totaltime);
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "Matrix_mul_naive.hip"
.globl _Z25__device_stub__matrix_mulPiS_S_ # -- Begin function _Z25__device_stub__matrix_mulPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__matrix_mulPiS_S_,@function
_Z25__device_stub__matrix_mulPiS_S_: # @_Z25__device_stub__matrix_mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPiS_S_, .Lfunc_end0-_Z25__device_stub__matrix_mulPiS_S_
.cfi_endproc
# -- End function
.globl _Z10random_intPii # -- Begin function _Z10random_intPii
.p2align 4, 0x90
.type _Z10random_intPii,@function
_Z10random_intPii: # @_Z10random_intPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10random_intPii, .Lfunc_end1-_Z10random_intPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB2_1
# %bb.2: # %_Z10random_intPii.exit
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $10000, %r15 # imm = 0x2710
jne .LBB2_3
# %bb.4: # %_Z10random_intPii.exit30
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r15
movl $start1, %edi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $stop1, %edi
xorl %esi, %esi
callq gettimeofday
movl $start, %edi
xorl %esi, %esi
callq gettimeofday
movabsq $2684354560625, %rdi # imm = 0x27100000271
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10matrix_mulPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movl $stop, %edi
xorl %esi, %esi
callq gettimeofday
movq stop(%rip), %rax
subq start(%rip), %rax
cvtsi2sd %rax, %xmm1
movq stop+8(%rip), %rax
subq start+8(%rip), %rax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq stop(%rip), %rax
subq start(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq stop+8(%rip), %rax
subq start+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 36(%rsp) # 4-byte Spill
movl $start2, %edi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $stop2, %edi
xorl %esi, %esi
callq gettimeofday
movq stop1(%rip), %rax
subq start1(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq stop1+8(%rip), %rax
subq start1+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq stop2(%rip), %rax
subq start2(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movq stop2+8(%rip), %rax
subq start2+8(%rip), %rax
cvtsi2sd %rax, %xmm2
mulsd %xmm3, %xmm2
addsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
addss %xmm0, %xmm1
addss 36(%rsp), %xmm1 # 4-byte Folded Reload
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.zero 16
.size start, 16
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.zero 16
.size stop, 16
.type start1,@object # @start1
.globl start1
.p2align 3, 0x0
start1:
.zero 16
.size start1, 16
.type stop1,@object # @stop1
.globl stop1
.p2align 3, 0x0
stop1:
.zero 16
.size stop1, 16
.type start2,@object # @start2
.globl start2
.p2align 3, 0x0
start2:
.zero 16
.size start2, 16
.type stop2,@object # @stop2
.globl stop2
.p2align 3, 0x0
stop2:
.zero 16
.size stop2, 16
.type _Z10matrix_mulPiS_S_,@object # @_Z10matrix_mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPiS_S_
.p2align 3, 0x0
_Z10matrix_mulPiS_S_:
.quad _Z25__device_stub__matrix_mulPiS_S_
.size _Z10matrix_mulPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Execution time of kernel without memory Transfer: %lu us\n"
.size .L.str, 62
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Execution Time of kernel with memory Transfer: %lu us\n"
.size .L.str.1, 59
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_mulPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym start
.addrsig_sym stop
.addrsig_sym start1
.addrsig_sym stop1
.addrsig_sym start2
.addrsig_sym stop2
.addrsig_sym _Z10matrix_mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrix_mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x001fe200078e0200 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fc600000001ff */
/*00b0*/ IMAD R7, R7, 0x2710, RZ ; /* 0x0000271007077824 */
/* 0x000fe400078e02ff */
/*00c0*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x002fca00078e0205 */
/*00d0*/ IMAD.WIDE R2, R7, R0, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0200 */
/*00e0*/ IADD3 R2, P0, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fc80007f1e0ff */
/*00f0*/ IADD3.X R3, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff037210 */
/* 0x000fc800007fe4ff */
/*0100*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0110*/ LDG.E R15, [R2.64+-0x20] ; /* 0xffffe004020f7981 */
/* 0x000ea2000c1e1900 */
/*0120*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0130*/ LDG.E R17, [R2.64+-0x1c] ; /* 0xffffe40402117981 */
/* 0x000ee4000c1e1900 */
/*0140*/ IMAD.WIDE R4, R6, 0x4, R4 ; /* 0x0000000406047825 */
/* 0x000fe400078e0204 */
/*0150*/ LDG.E R19, [R2.64+-0x18] ; /* 0xffffe80402137981 */
/* 0x000f28000c1e1900 */
/*0160*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R18, [R4.64+0x9c40] ; /* 0x009c400404127981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R20, [R4.64+0x13880] ; /* 0x0138800404147981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R22, [R2.64+-0x14] ; /* 0xffffec0402167981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R21, [R4.64+0x1d4c0] ; /* 0x01d4c00404157981 */
/* 0x000f68000c1e1900 */
/*01b0*/ LDG.E R23, [R2.64+-0x10] ; /* 0xfffff00402177981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R24, [R4.64+0x27100] ; /* 0x0271000404187981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R9, [R2.64+-0xc] ; /* 0xfffff40402097981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R10, [R4.64+0x30d40] ; /* 0x030d4004040a7981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R11, [R2.64+-0x8] ; /* 0xfffff804020b7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R12, [R4.64+0x3a980] ; /* 0x03a98004040c7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R13, [R2.64+-0x4] ; /* 0xfffffc04020d7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R14, [R4.64+0x445c0] ; /* 0x0445c004040e7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R26, [R2.64+0x1c] ; /* 0x00001c04021a7981 */
/* 0x000162000c1e1900 */
/*0240*/ IMAD R25, R16, R15, R25 ; /* 0x0000000f10197224 */
/* 0x004fc600078e0219 */
/*0250*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R16, [R4.64+0x4e200] ; /* 0x04e2000404107981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x008fc600078e0219 */
/*0280*/ LDG.E R17, [R2.64+0x4] ; /* 0x0000040402117981 */
/* 0x0000e2000c1e1900 */
/*0290*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x010fc600078e0219 */
/*02a0*/ LDG.E R18, [R4.64+0x57e40] ; /* 0x057e400404127981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000122000c1e1900 */
/*02c0*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*02d0*/ LDG.E R19, [R4.64+0x61a80] ; /* 0x061a800404137981 */
/* 0x000f28000c1e1900 */
/*02e0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000162000c1e1900 */
/*02f0*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x000fc600078e0219 */
/*0300*/ LDG.E R21, [R4.64+0x6b6c0] ; /* 0x06b6c00404157981 */
/* 0x000f68000c1e1900 */
/*0310*/ LDG.E R24, [R2.64+0x10] ; /* 0x0000100402187981 */
/* 0x000162000c1e1900 */
/*0320*/ IMAD R25, R10, R9, R25 ; /* 0x000000090a197224 */
/* 0x000fc600078e0219 */
/*0330*/ LDG.E R23, [R4.64+0x75300] ; /* 0x0753000404177981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000162000c1e1900 */
/*0350*/ IMAD R27, R12, R11, R25 ; /* 0x0000000b0c1b7224 */
/* 0x000fc600078e0219 */
/*0360*/ LDG.E R9, [R4.64+0x7ef40] ; /* 0x07ef400404097981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000168000c1e1900 */
/*0380*/ LDG.E R12, [R4.64+0x88b80] ; /* 0x088b8004040c7981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R25, [R4.64+0x927c0] ; /* 0x0927c00404197981 */
/* 0x000f62000c1e1900 */
/*03a0*/ IMAD R13, R14, R13, R27 ; /* 0x0000000d0e0d7224 */
/* 0x000fe200078e021b */
/*03b0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03c0*/ ISETP.NE.AND P0, PT, R8, 0x2710, PT ; /* 0x000027100800780c */
/* 0x000fe20003f05270 */
/*03d0*/ UIADD3 UR6, UP0, UR6, 0x9c400, URZ ; /* 0x0009c40006067890 */
/* 0x000fe2000ff1e03f */
/*03e0*/ IADD3 R2, P1, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fc60007f3e0ff */
/*03f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0400*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*0410*/ IMAD R13, R16, R15, R13 ; /* 0x0000000f100d7224 */
/* 0x004fc800078e020d */
/*0420*/ IMAD R13, R18, R17, R13 ; /* 0x00000011120d7224 */
/* 0x008fc800078e020d */
/*0430*/ IMAD R13, R19, R20, R13 ; /* 0x00000014130d7224 */
/* 0x010fc800078e020d */
/*0440*/ IMAD R13, R21, R22, R13 ; /* 0x00000016150d7224 */
/* 0x020fc800078e020d */
/*0450*/ IMAD R13, R23, R24, R13 ; /* 0x00000018170d7224 */
/* 0x000fc800078e020d */
/*0460*/ IMAD R9, R9, R10, R13 ; /* 0x0000000a09097224 */
/* 0x000fc800078e020d */
/*0470*/ IMAD R9, R12, R11, R9 ; /* 0x0000000b0c097224 */
/* 0x000fc800078e0209 */
/*0480*/ IMAD R25, R25, R26, R9 ; /* 0x0000001a19197224 */
/* 0x000fe200078e0209 */
/*0490*/ @P0 BRA 0x100 ; /* 0xfffffc6000000947 */
/* 0x000fea000383ffff */
/*04a0*/ IADD3 R3, R6, R7, RZ ; /* 0x0000000706037210 */
/* 0x000fca0007ffe0ff */
/*04b0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0200 */
/*04c0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrix_mulPiS_S_
.globl _Z10matrix_mulPiS_S_
.p2align 8
.type _Z10matrix_mulPiS_S_,@function
_Z10matrix_mulPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, 0x2710
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[0:1]
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_mov_b32_e32 v3, v2
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v8, vcc_lo, v6, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_u32 s2, 0x9c40
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v9, v8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v4 :: v_dual_add_nc_u32 v3, 0x2710, v3
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 0x2710, v[2:3]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrix_mulPiS_S_, .Lfunc_end0-_Z10matrix_mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00080c52_00000000-6_Matrix_mul_naive.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10random_intPii
.type _Z10random_intPii, @function
_Z10random_intPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z10random_intPii, .-_Z10random_intPii
.globl _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
.type _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_, @function
_Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_, .-_Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
.globl _Z10matrix_mulPiS_S_
.type _Z10matrix_mulPiS_S_, @function
_Z10matrix_mulPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z10matrix_mulPiS_S_, .-_Z10matrix_mulPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "GPU Execution time of kernel without memory Transfer: %lu us\n"
.align 8
.LC2:
.string "GPU Execution Time of kernel with memory Transfer: %lu us\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $10000, %esi
movq %rax, %rdi
call _Z10random_intPii
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $10000, %esi
movq %rax, %rdi
call _Z10random_intPii
movl $400000000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %esi
leaq start1(%rip), %rdi
call gettimeofday@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
leaq stop1(%rip), %rdi
call gettimeofday@PLT
movl $625, 48(%rsp)
movl $625, 52(%rsp)
movl $1, 56(%rsp)
movl $16, 60(%rsp)
movl $16, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
leaq start(%rip), %rdi
call gettimeofday@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
leaq stop(%rip), %rdi
call gettimeofday@PLT
movq 8+stop(%rip), %rax
subq 8+start(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq stop(%rip), %rax
subq start(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8+stop(%rip), %rax
subq 8+start(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq stop(%rip), %rax
subq start(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
pxor %xmm3, %xmm3
cvtsd2ss %xmm0, %xmm3
movss %xmm3, 12(%rsp)
movl $0, %esi
leaq start2(%rip), %rdi
call gettimeofday@PLT
movl $2, %ecx
movl $400000000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
leaq stop2(%rip), %rdi
call gettimeofday@PLT
movq 8+stop1(%rip), %rax
subq 8+start1(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC0(%rip), %xmm0
movq stop1(%rip), %rax
subq start1(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 8+stop2(%rip), %rax
subq 8+start2(%rip), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
mulsd .LC0(%rip), %xmm1
movq stop2(%rip), %rax
subq start2(%rip), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
addss %xmm1, %xmm0
addss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10matrix_mulPiS_S_PiS_S_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "_Z10matrix_mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_mulPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl stop2
.bss
.align 16
.type stop2, @object
.size stop2, 16
stop2:
.zero 16
.globl start2
.align 16
.type start2, @object
.size start2, 16
start2:
.zero 16
.globl stop1
.align 16
.type stop1, @object
.size stop1, 16
stop1:
.zero 16
.globl start1
.align 16
.type start1, @object
.size start1, 16
start1:
.zero 16
.globl stop
.align 16
.type stop, @object
.size stop, 16
stop:
.zero 16
.globl start
.align 16
.type start, @object
.size start, 16
start:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Matrix_mul_naive.hip"
.globl _Z25__device_stub__matrix_mulPiS_S_ # -- Begin function _Z25__device_stub__matrix_mulPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__matrix_mulPiS_S_,@function
_Z25__device_stub__matrix_mulPiS_S_: # @_Z25__device_stub__matrix_mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__matrix_mulPiS_S_, .Lfunc_end0-_Z25__device_stub__matrix_mulPiS_S_
.cfi_endproc
# -- End function
.globl _Z10random_intPii # -- Begin function _Z10random_intPii
.p2align 4, 0x90
.type _Z10random_intPii,@function
_Z10random_intPii: # @_Z10random_intPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10random_intPii, .Lfunc_end1-_Z10random_intPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB2_1
# %bb.2: # %_Z10random_intPii.exit
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r15,4)
incq %r15
cmpq $10000, %r15 # imm = 0x2710
jne .LBB2_3
# %bb.4: # %_Z10random_intPii.exit30
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r15
movl $start1, %edi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $stop1, %edi
xorl %esi, %esi
callq gettimeofday
movl $start, %edi
xorl %esi, %esi
callq gettimeofday
movabsq $2684354560625, %rdi # imm = 0x27100000271
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10matrix_mulPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movl $stop, %edi
xorl %esi, %esi
callq gettimeofday
movq stop(%rip), %rax
subq start(%rip), %rax
cvtsi2sd %rax, %xmm1
movq stop+8(%rip), %rax
subq start+8(%rip), %rax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq stop(%rip), %rax
subq start(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq stop+8(%rip), %rax
subq start+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, 36(%rsp) # 4-byte Spill
movl $start2, %edi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $stop2, %edi
xorl %esi, %esi
callq gettimeofday
movq stop1(%rip), %rax
subq start1(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movq stop1+8(%rip), %rax
subq start1+8(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movsd .LCPI2_0(%rip), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm3, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq stop2(%rip), %rax
subq start2(%rip), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movq stop2+8(%rip), %rax
subq start2+8(%rip), %rax
cvtsi2sd %rax, %xmm2
mulsd %xmm3, %xmm2
addsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
addss %xmm0, %xmm1
addss 36(%rsp), %xmm1 # 4-byte Folded Reload
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.zero 16
.size start, 16
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.zero 16
.size stop, 16
.type start1,@object # @start1
.globl start1
.p2align 3, 0x0
start1:
.zero 16
.size start1, 16
.type stop1,@object # @stop1
.globl stop1
.p2align 3, 0x0
stop1:
.zero 16
.size stop1, 16
.type start2,@object # @start2
.globl start2
.p2align 3, 0x0
start2:
.zero 16
.size start2, 16
.type stop2,@object # @stop2
.globl stop2
.p2align 3, 0x0
stop2:
.zero 16
.size stop2, 16
.type _Z10matrix_mulPiS_S_,@object # @_Z10matrix_mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z10matrix_mulPiS_S_
.p2align 3, 0x0
_Z10matrix_mulPiS_S_:
.quad _Z25__device_stub__matrix_mulPiS_S_
.size _Z10matrix_mulPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Execution time of kernel without memory Transfer: %lu us\n"
.size .L.str, 62
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Execution Time of kernel with memory Transfer: %lu us\n"
.size .L.str.1, 59
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrix_mulPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrix_mulPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym start
.addrsig_sym stop
.addrsig_sym start1
.addrsig_sym stop1
.addrsig_sym start2
.addrsig_sym stop2
.addrsig_sym _Z10matrix_mulPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
void sum_arrays_on_host( const int N, double *A, double *B, double *C )
{
for( int idx = 0; idx < N; idx++ ) {
C[idx] = A[idx] + B[idx];
}
}
void initial_data( int Ndata, double *dat )
{
// Generate different seed for random number
time_t t;
srand( (unsigned int) time(&t) );
for( int i = 0; i < Ndata; i++ ) {
dat[i] = (double)( rand() & 0xFF )/10.0f;
}
}
void print_data( int Ndata, double *A )
{
for( int i = 0; i < Ndata; i++ ) {
printf("%8d %18.10f\n", i, A[i]);
}
}
int main( int argc, char **argv)
{
int Ndata = 10;
size_t Nbytes = Ndata * sizeof(double);
double *h_A, *h_B, *h_C;
h_A = (double*) malloc(Nbytes);
h_B = (double*) malloc(Nbytes);
h_C = (double*) malloc(Nbytes);
initial_data( Ndata, h_A );
initial_data( Ndata, h_B );
sum_arrays_on_host( Ndata, h_A, h_B, h_C );
for( int i = 0; i < Ndata; i++ ) {
printf("%3d %18.10f %18.10f %18.10f\n", i, h_A[i], h_B[i], h_C[i]);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
void sum_arrays_on_host( const int N, double *A, double *B, double *C )
{
for( int idx = 0; idx < N; idx++ ) {
C[idx] = A[idx] + B[idx];
}
}
void initial_data( int Ndata, double *dat )
{
// Generate different seed for random number
time_t t;
srand( (unsigned int) time(&t) );
for( int i = 0; i < Ndata; i++ ) {
dat[i] = (double)( rand() & 0xFF )/10.0f;
}
}
void print_data( int Ndata, double *A )
{
for( int i = 0; i < Ndata; i++ ) {
printf("%8d %18.10f\n", i, A[i]);
}
}
int main( int argc, char **argv)
{
int Ndata = 10;
size_t Nbytes = Ndata * sizeof(double);
double *h_A, *h_B, *h_C;
h_A = (double*) malloc(Nbytes);
h_B = (double*) malloc(Nbytes);
h_C = (double*) malloc(Nbytes);
initial_data( Ndata, h_A );
initial_data( Ndata, h_B );
sum_arrays_on_host( Ndata, h_A, h_B, h_C );
for( int i = 0; i < Ndata; i++ ) {
printf("%3d %18.10f %18.10f %18.10f\n", i, h_A[i], h_B[i], h_C[i]);
}
return 0;
} | .file "tmpxft_000c8785_00000000-6_03_sum_arrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18sum_arrays_on_hostiPdS_S_
.type _Z18sum_arrays_on_hostiPdS_S_, @function
_Z18sum_arrays_on_hostiPdS_S_:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
salq $3, %rdi
movl $0, %eax
.L5:
movsd (%rsi,%rax), %xmm0
addsd (%rdx,%rax), %xmm0
movsd %xmm0, (%rcx,%rax)
addq $8, %rax
cmpq %rdi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z18sum_arrays_on_hostiPdS_S_, .-_Z18sum_arrays_on_hostiPdS_S_
.globl _Z12initial_dataiPd
.type _Z12initial_dataiPd, @function
_Z12initial_dataiPd:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L7
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,8), %rbp
.L9:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L9
.L7:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12initial_dataiPd, .-_Z12initial_dataiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%8d %18.10f\n"
.text
.globl _Z10print_dataiPd
.type _Z10print_dataiPd, @function
_Z10print_dataiPd:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L19
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movslq %edi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L16:
movsd (%r12,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L16
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2059:
.size _Z10print_dataiPd, .-_Z10print_dataiPd
.section .rodata.str1.1
.LC2:
.string "%3d %18.10f %18.10f %18.10f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $80, %edi
call malloc@PLT
movq %rax, %r12
movl $80, %edi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rsi
movl $10, %edi
call _Z12initial_dataiPd
movq %r12, %rsi
movl $10, %edi
call _Z12initial_dataiPd
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl $10, %edi
call _Z18sum_arrays_on_hostiPdS_S_
movl $0, %ebx
leaq .LC2(%rip), %r14
.L23:
movsd 0(%rbp,%rbx,8), %xmm0
movsd 0(%r13,%rbx,8), %xmm2
movsd (%r12,%rbx,8), %xmm1
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L23
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1076101120
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
void sum_arrays_on_host( const int N, double *A, double *B, double *C )
{
for( int idx = 0; idx < N; idx++ ) {
C[idx] = A[idx] + B[idx];
}
}
void initial_data( int Ndata, double *dat )
{
// Generate different seed for random number
time_t t;
srand( (unsigned int) time(&t) );
for( int i = 0; i < Ndata; i++ ) {
dat[i] = (double)( rand() & 0xFF )/10.0f;
}
}
void print_data( int Ndata, double *A )
{
for( int i = 0; i < Ndata; i++ ) {
printf("%8d %18.10f\n", i, A[i]);
}
}
int main( int argc, char **argv)
{
int Ndata = 10;
size_t Nbytes = Ndata * sizeof(double);
double *h_A, *h_B, *h_C;
h_A = (double*) malloc(Nbytes);
h_B = (double*) malloc(Nbytes);
h_C = (double*) malloc(Nbytes);
initial_data( Ndata, h_A );
initial_data( Ndata, h_B );
sum_arrays_on_host( Ndata, h_A, h_B, h_C );
for( int i = 0; i < Ndata; i++ ) {
printf("%3d %18.10f %18.10f %18.10f\n", i, h_A[i], h_B[i], h_C[i]);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
void sum_arrays_on_host( const int N, double *A, double *B, double *C )
{
for( int idx = 0; idx < N; idx++ ) {
C[idx] = A[idx] + B[idx];
}
}
void initial_data( int Ndata, double *dat )
{
// Generate different seed for random number
time_t t;
srand( (unsigned int) time(&t) );
for( int i = 0; i < Ndata; i++ ) {
dat[i] = (double)( rand() & 0xFF )/10.0f;
}
}
void print_data( int Ndata, double *A )
{
for( int i = 0; i < Ndata; i++ ) {
printf("%8d %18.10f\n", i, A[i]);
}
}
int main( int argc, char **argv)
{
int Ndata = 10;
size_t Nbytes = Ndata * sizeof(double);
double *h_A, *h_B, *h_C;
h_A = (double*) malloc(Nbytes);
h_B = (double*) malloc(Nbytes);
h_C = (double*) malloc(Nbytes);
initial_data( Ndata, h_A );
initial_data( Ndata, h_B );
sum_arrays_on_host( Ndata, h_A, h_B, h_C );
for( int i = 0; i < Ndata; i++ ) {
printf("%3d %18.10f %18.10f %18.10f\n", i, h_A[i], h_B[i], h_C[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
void sum_arrays_on_host( const int N, double *A, double *B, double *C )
{
for( int idx = 0; idx < N; idx++ ) {
C[idx] = A[idx] + B[idx];
}
}
void initial_data( int Ndata, double *dat )
{
// Generate different seed for random number
time_t t;
srand( (unsigned int) time(&t) );
for( int i = 0; i < Ndata; i++ ) {
dat[i] = (double)( rand() & 0xFF )/10.0f;
}
}
void print_data( int Ndata, double *A )
{
for( int i = 0; i < Ndata; i++ ) {
printf("%8d %18.10f\n", i, A[i]);
}
}
int main( int argc, char **argv)
{
int Ndata = 10;
size_t Nbytes = Ndata * sizeof(double);
double *h_A, *h_B, *h_C;
h_A = (double*) malloc(Nbytes);
h_B = (double*) malloc(Nbytes);
h_C = (double*) malloc(Nbytes);
initial_data( Ndata, h_A );
initial_data( Ndata, h_B );
sum_arrays_on_host( Ndata, h_A, h_B, h_C );
for( int i = 0; i < Ndata; i++ ) {
printf("%3d %18.10f %18.10f %18.10f\n", i, h_A[i], h_B[i], h_C[i]);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
void sum_arrays_on_host( const int N, double *A, double *B, double *C )
{
for( int idx = 0; idx < N; idx++ ) {
C[idx] = A[idx] + B[idx];
}
}
void initial_data( int Ndata, double *dat )
{
// Generate different seed for random number
time_t t;
srand( (unsigned int) time(&t) );
for( int i = 0; i < Ndata; i++ ) {
dat[i] = (double)( rand() & 0xFF )/10.0f;
}
}
void print_data( int Ndata, double *A )
{
for( int i = 0; i < Ndata; i++ ) {
printf("%8d %18.10f\n", i, A[i]);
}
}
int main( int argc, char **argv)
{
int Ndata = 10;
size_t Nbytes = Ndata * sizeof(double);
double *h_A, *h_B, *h_C;
h_A = (double*) malloc(Nbytes);
h_B = (double*) malloc(Nbytes);
h_C = (double*) malloc(Nbytes);
initial_data( Ndata, h_A );
initial_data( Ndata, h_B );
sum_arrays_on_host( Ndata, h_A, h_B, h_C );
for( int i = 0; i < Ndata; i++ ) {
printf("%3d %18.10f %18.10f %18.10f\n", i, h_A[i], h_B[i], h_C[i]);
}
return 0;
} | .text
.file "03_sum_arrays.hip"
.globl _Z18sum_arrays_on_hostiPdS_S_ # -- Begin function _Z18sum_arrays_on_hostiPdS_S_
.p2align 4, 0x90
.type _Z18sum_arrays_on_hostiPdS_S_,@function
_Z18sum_arrays_on_hostiPdS_S_: # @_Z18sum_arrays_on_hostiPdS_S_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rdx,%rdi,8), %xmm0
movsd %xmm0, (%rcx,%rdi,8)
incq %rdi
cmpq %rdi, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z18sum_arrays_on_hostiPdS_S_, .Lfunc_end0-_Z18sum_arrays_on_hostiPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12initial_dataiPd
.LCPI1_0:
.quad 0x4024000000000000 # double 10
.text
.globl _Z12initial_dataiPd
.p2align 4, 0x90
.type _Z12initial_dataiPd,@function
_Z12initial_dataiPd: # @_Z12initial_dataiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12initial_dataiPd, .Lfunc_end1-_Z12initial_dataiPd
.cfi_endproc
# -- End function
.globl _Z10print_dataiPd # -- Begin function _Z10print_dataiPd
.p2align 4, 0x90
.type _Z10print_dataiPd,@function
_Z10print_dataiPd: # @_Z10print_dataiPd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10print_dataiPd, .Lfunc_end2-_Z10print_dataiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4024000000000000 # double 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edi
callq malloc
movq %rax, %r14
movl $80, %edi
callq malloc
movq %rax, %r15
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r12,8)
incq %r12
cmpq $10, %r12
jne .LBB3_1
# %bb.2: # %_Z12initial_dataiPd.exit
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i21
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%r14,%r12,8)
incq %r12
cmpq $10, %r12
jne .LBB3_3
# %bb.4: # %_Z12initial_dataiPd.exit25
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%r15,%rax,8)
incq %rax
cmpq $10, %rax
jne .LBB3_5
# %bb.6: # %_Z18sum_arrays_on_hostiPdS_S_.exit.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # %_Z18sum_arrays_on_hostiPdS_S_.exit
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r15,%r12,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movl %r12d, %esi
movb $3, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB3_7
# %bb.8:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%8d %18.10f\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%3d %18.10f %18.10f %18.10f\n"
.size .L.str.1, 29
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c8785_00000000-6_03_sum_arrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18sum_arrays_on_hostiPdS_S_
.type _Z18sum_arrays_on_hostiPdS_S_, @function
_Z18sum_arrays_on_hostiPdS_S_:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
salq $3, %rdi
movl $0, %eax
.L5:
movsd (%rsi,%rax), %xmm0
addsd (%rdx,%rax), %xmm0
movsd %xmm0, (%rcx,%rax)
addq $8, %rax
cmpq %rdi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z18sum_arrays_on_hostiPdS_S_, .-_Z18sum_arrays_on_hostiPdS_S_
.globl _Z12initial_dataiPd
.type _Z12initial_dataiPd, @function
_Z12initial_dataiPd:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L7
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,8), %rbp
.L9:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L9
.L7:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12initial_dataiPd, .-_Z12initial_dataiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%8d %18.10f\n"
.text
.globl _Z10print_dataiPd
.type _Z10print_dataiPd, @function
_Z10print_dataiPd:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L19
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movslq %edi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L16:
movsd (%r12,%rbx,8), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L16
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2059:
.size _Z10print_dataiPd, .-_Z10print_dataiPd
.section .rodata.str1.1
.LC2:
.string "%3d %18.10f %18.10f %18.10f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $80, %edi
call malloc@PLT
movq %rax, %r12
movl $80, %edi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rsi
movl $10, %edi
call _Z12initial_dataiPd
movq %r12, %rsi
movl $10, %edi
call _Z12initial_dataiPd
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl $10, %edi
call _Z18sum_arrays_on_hostiPdS_S_
movl $0, %ebx
leaq .LC2(%rip), %r14
.L23:
movsd 0(%rbp,%rbx,8), %xmm0
movsd 0(%r13,%rbx,8), %xmm2
movsd (%r12,%rbx,8), %xmm1
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L23
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1076101120
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "03_sum_arrays.hip"
.globl _Z18sum_arrays_on_hostiPdS_S_ # -- Begin function _Z18sum_arrays_on_hostiPdS_S_
.p2align 4, 0x90
.type _Z18sum_arrays_on_hostiPdS_S_,@function
_Z18sum_arrays_on_hostiPdS_S_: # @_Z18sum_arrays_on_hostiPdS_S_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rsi,%rdi,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rdx,%rdi,8), %xmm0
movsd %xmm0, (%rcx,%rdi,8)
incq %rdi
cmpq %rdi, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z18sum_arrays_on_hostiPdS_S_, .Lfunc_end0-_Z18sum_arrays_on_hostiPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12initial_dataiPd
.LCPI1_0:
.quad 0x4024000000000000 # double 10
.text
.globl _Z12initial_dataiPd
.p2align 4, 0x90
.type _Z12initial_dataiPd,@function
_Z12initial_dataiPd: # @_Z12initial_dataiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12initial_dataiPd, .Lfunc_end1-_Z12initial_dataiPd
.cfi_endproc
# -- End function
.globl _Z10print_dataiPd # -- Begin function _Z10print_dataiPd
.p2align 4, 0x90
.type _Z10print_dataiPd,@function
_Z10print_dataiPd: # @_Z10print_dataiPd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z10print_dataiPd, .Lfunc_end2-_Z10print_dataiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4024000000000000 # double 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edi
callq malloc
movq %rax, %r14
movl $80, %edi
callq malloc
movq %rax, %r15
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%rbx,%r12,8)
incq %r12
cmpq $10, %r12
jne .LBB3_1
# %bb.2: # %_Z12initial_dataiPd.exit
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i21
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, (%r14,%r12,8)
incq %r12
cmpq $10, %r12
jne .LBB3_3
# %bb.4: # %_Z12initial_dataiPd.exit25
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i26
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%rax,8), %xmm0
movsd %xmm0, (%r15,%rax,8)
incq %rax
cmpq $10, %rax
jne .LBB3_5
# %bb.6: # %_Z18sum_arrays_on_hostiPdS_S_.exit.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # %_Z18sum_arrays_on_hostiPdS_S_.exit
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r14,%r12,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r15,%r12,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.1, %edi
movl %r12d, %esi
movb $3, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB3_7
# %bb.8:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%8d %18.10f\n"
.size .L.str, 13
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%3d %18.10f %18.10f %18.10f\n"
.size .L.str.1, 29
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Thumbnail_ushort2(cudaTextureObject_t ushort2_tex, int *histogram, int src_width, int src_height)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (y < src_height && x < src_width)
{
ushort2 pixel = tex2D<ushort2>(ushort2_tex, x, y);
atomicAdd(&histogram[(pixel.x + 128) >> 8], 1);
atomicAdd(&histogram[256 + (pixel.y + 128) >> 8], 1);
}
} | code for sm_80
Function : _Z17Thumbnail_ushort2yPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R6, R0 ; /* 0x0000000000067306 */
/* 0x000fe20000201400 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x3e000000 ; /* 0xc2000000ff087424 */
/* 0x000fce00078e00ff */
/*00c0*/ I2F R7, R2 ; /* 0x0000000200077306 */
/* 0x000e240000201400 */
/*00d0*/ TEX.SCR.LL RZ, R6, R6, R8, 0x0, 0x58, 2D, 0x3 ; /* 0x3000580806067b60 */
/* 0x001f4200019e03ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0110*/ LOP3.LUT R3, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06037812 */
/* 0x020fe400078ec0ff */
/*0120*/ LOP3.LUT R4, R7, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff07047812 */
/* 0x000fe400078ec0ff */
/*0130*/ IADD3 R3, R3, 0x80, RZ ; /* 0x0000008003037810 */
/* 0x000fe40007ffe0ff */
/*0140*/ IADD3 R4, R4, 0x180, RZ ; /* 0x0000018004047810 */
/* 0x000fe40007ffe0ff */
/*0150*/ SHF.R.U32.HI R3, RZ, 0x8, R3 ; /* 0x00000008ff037819 */
/* 0x000fc40000011603 */
/*0160*/ SHF.R.U32.HI R4, RZ, 0x8, R4 ; /* 0x00000008ff047819 */
/* 0x000fc60000011604 */
/*0170*/ IMAD.WIDE.U32 R2, R3, R5, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0005 */
/*0180*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe8000c10e184 */
/*01a0*/ RED.E.ADD.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x000fe2000c10e184 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Thumbnail_ushort2(cudaTextureObject_t ushort2_tex, int *histogram, int src_width, int src_height)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (y < src_height && x < src_width)
{
ushort2 pixel = tex2D<ushort2>(ushort2_tex, x, y);
atomicAdd(&histogram[(pixel.x + 128) >> 8], 1);
atomicAdd(&histogram[256 + (pixel.y + 128) >> 8], 1);
}
} | .file "tmpxft_00145eac_00000000-6_Thumbnail_ushort2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii
.type _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii, @function
_Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17Thumbnail_ushort2yPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii, .-_Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii
.globl _Z17Thumbnail_ushort2yPiii
.type _Z17Thumbnail_ushort2yPiii, @function
_Z17Thumbnail_ushort2yPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17Thumbnail_ushort2yPiii, .-_Z17Thumbnail_ushort2yPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17Thumbnail_ushort2yPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17Thumbnail_ushort2yPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Thumbnail_ushort2(cudaTextureObject_t ushort2_tex, int *histogram, int src_width, int src_height)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (y < src_height && x < src_width)
{
ushort2 pixel = tex2D<ushort2>(ushort2_tex, x, y);
atomicAdd(&histogram[(pixel.x + 128) >> 8], 1);
atomicAdd(&histogram[256 + (pixel.y + 128) >> 8], 1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Thumbnail_ushort2(hipTextureObject_t ushort2_tex, int *histogram, int src_width, int src_height)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (y < src_height && x < src_width)
{
ushort2 pixel = tex2D<ushort2>(ushort2_tex, x, y);
atomicAdd(&histogram[(pixel.x + 128) >> 8], 1);
atomicAdd(&histogram[256 + (pixel.y + 128) >> 8], 1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Thumbnail_ushort2(hipTextureObject_t ushort2_tex, int *histogram, int src_width, int src_height)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (y < src_height && x < src_width)
{
ushort2 pixel = tex2D<ushort2>(ushort2_tex, x, y);
atomicAdd(&histogram[(pixel.x + 128) >> 8], 1);
atomicAdd(&histogram[256 + (pixel.y + 128) >> 8], 1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17Thumbnail_ushort2P13__hip_texturePiii
.globl _Z17Thumbnail_ushort2P13__hip_texturePiii
.p2align 8
.type _Z17Thumbnail_ushort2P13__hip_texturePiii,@function
_Z17Thumbnail_ushort2P13__hip_texturePiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s5, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_cvt_f32_i32_e32 v1, v2
v_cvt_f32_i32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_clause 0x5
s_load_b32 s0, s[4:5], 0x38
s_load_b32 s1, s[4:5], 0x30
s_load_b32 s2, s[4:5], 0x8
s_load_b32 s3, s[4:5], 0x28
s_load_b128 s[16:19], s[4:5], 0x30
s_load_b256 s[8:15], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s1, 15
v_cvt_f32_u32_e32 v3, s3
s_cselect_b32 s0, -1, 0
s_bfe_u32 s1, s2, 0xe000e
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, 1
v_cndmask_b32_e64 v3, 1.0, v3, s0
v_cvt_f32_u32_e32 v2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v3
v_cndmask_b32_e64 v2, 1.0, v2, s0
v_mul_f32_e32 v3, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v4, v2
v_mul_f32_e32 v2, v2, v1
v_floor_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_floor_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, v5, v3 :: v_dual_mul_f32 v2, v4, v2
v_dual_cndmask_b32 v0, v0, v3 :: v_dual_cndmask_b32 v1, v1, v2
v_mov_b32_e32 v2, 1
image_sample_lz v[0:1], v[0:1], s[8:15], s[16:19] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_perm_b32 v0, v1, v0, 0x5040100
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, 0xff80, v0
v_lshrrev_b32_e32 v0, 16, v0
v_add_nc_u32_e32 v1, 0x80, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, 0x180, v0
v_lshrrev_b32_e32 v1, 6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v0, 6, v0
v_and_b32_e32 v1, 0x7fc, v1
s_delay_alu instid0(VALU_DEP_2)
v_and_b32_e32 v0, 0x7fc, v0
s_clause 0x1
global_atomic_add_u32 v1, v2, s[6:7]
global_atomic_add_u32 v0, v2, s[6:7]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Thumbnail_ushort2P13__hip_texturePiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17Thumbnail_ushort2P13__hip_texturePiii, .Lfunc_end0-_Z17Thumbnail_ushort2P13__hip_texturePiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Thumbnail_ushort2P13__hip_texturePiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z17Thumbnail_ushort2P13__hip_texturePiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Thumbnail_ushort2(hipTextureObject_t ushort2_tex, int *histogram, int src_width, int src_height)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if (y < src_height && x < src_width)
{
ushort2 pixel = tex2D<ushort2>(ushort2_tex, x, y);
atomicAdd(&histogram[(pixel.x + 128) >> 8], 1);
atomicAdd(&histogram[256 + (pixel.y + 128) >> 8], 1);
}
} | .text
.file "Thumbnail_ushort2.hip"
.globl _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii # -- Begin function _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.p2align 4, 0x90
.type _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii,@function
_Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii: # @_Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17Thumbnail_ushort2P13__hip_texturePiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii, .Lfunc_end0-_Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17Thumbnail_ushort2P13__hip_texturePiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17Thumbnail_ushort2P13__hip_texturePiii,@object # @_Z17Thumbnail_ushort2P13__hip_texturePiii
.section .rodata,"a",@progbits
.globl _Z17Thumbnail_ushort2P13__hip_texturePiii
.p2align 3, 0x0
_Z17Thumbnail_ushort2P13__hip_texturePiii:
.quad _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.size _Z17Thumbnail_ushort2P13__hip_texturePiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17Thumbnail_ushort2P13__hip_texturePiii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17Thumbnail_ushort2P13__hip_texturePiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17Thumbnail_ushort2yPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R6, R0 ; /* 0x0000000000067306 */
/* 0x000fe20000201400 */
/*00b0*/ IMAD.MOV.U32 R8, RZ, RZ, -0x3e000000 ; /* 0xc2000000ff087424 */
/* 0x000fce00078e00ff */
/*00c0*/ I2F R7, R2 ; /* 0x0000000200077306 */
/* 0x000e240000201400 */
/*00d0*/ TEX.SCR.LL RZ, R6, R6, R8, 0x0, 0x58, 2D, 0x3 ; /* 0x3000580806067b60 */
/* 0x001f4200019e03ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0110*/ LOP3.LUT R3, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06037812 */
/* 0x020fe400078ec0ff */
/*0120*/ LOP3.LUT R4, R7, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff07047812 */
/* 0x000fe400078ec0ff */
/*0130*/ IADD3 R3, R3, 0x80, RZ ; /* 0x0000008003037810 */
/* 0x000fe40007ffe0ff */
/*0140*/ IADD3 R4, R4, 0x180, RZ ; /* 0x0000018004047810 */
/* 0x000fe40007ffe0ff */
/*0150*/ SHF.R.U32.HI R3, RZ, 0x8, R3 ; /* 0x00000008ff037819 */
/* 0x000fc40000011603 */
/*0160*/ SHF.R.U32.HI R4, RZ, 0x8, R4 ; /* 0x00000008ff047819 */
/* 0x000fc60000011604 */
/*0170*/ IMAD.WIDE.U32 R2, R3, R5, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0005 */
/*0180*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x000fe8000c10e184 */
/*01a0*/ RED.E.ADD.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x000fe2000c10e184 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17Thumbnail_ushort2P13__hip_texturePiii
.globl _Z17Thumbnail_ushort2P13__hip_texturePiii
.p2align 8
.type _Z17Thumbnail_ushort2P13__hip_texturePiii,@function
_Z17Thumbnail_ushort2P13__hip_texturePiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s5, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_cvt_f32_i32_e32 v1, v2
v_cvt_f32_i32_e32 v0, v0
s_waitcnt lgkmcnt(0)
s_clause 0x5
s_load_b32 s0, s[4:5], 0x38
s_load_b32 s1, s[4:5], 0x30
s_load_b32 s2, s[4:5], 0x8
s_load_b32 s3, s[4:5], 0x28
s_load_b128 s[16:19], s[4:5], 0x30
s_load_b256 s[8:15], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s1, 15
v_cvt_f32_u32_e32 v3, s3
s_cselect_b32 s0, -1, 0
s_bfe_u32 s1, s2, 0xe000e
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, 1
v_cndmask_b32_e64 v3, 1.0, v3, s0
v_cvt_f32_u32_e32 v2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v3
v_cndmask_b32_e64 v2, 1.0, v2, s0
v_mul_f32_e32 v3, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v4, v2
v_mul_f32_e32 v2, v2, v1
v_floor_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_floor_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, v5, v3 :: v_dual_mul_f32 v2, v4, v2
v_dual_cndmask_b32 v0, v0, v3 :: v_dual_cndmask_b32 v1, v1, v2
v_mov_b32_e32 v2, 1
image_sample_lz v[0:1], v[0:1], s[8:15], s[16:19] dmask:0x3 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_perm_b32 v0, v1, v0, 0x5040100
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, 0xff80, v0
v_lshrrev_b32_e32 v0, 16, v0
v_add_nc_u32_e32 v1, 0x80, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, 0x180, v0
v_lshrrev_b32_e32 v1, 6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v0, 6, v0
v_and_b32_e32 v1, 0x7fc, v1
s_delay_alu instid0(VALU_DEP_2)
v_and_b32_e32 v0, 0x7fc, v0
s_clause 0x1
global_atomic_add_u32 v1, v2, s[6:7]
global_atomic_add_u32 v0, v2, s[6:7]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Thumbnail_ushort2P13__hip_texturePiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17Thumbnail_ushort2P13__hip_texturePiii, .Lfunc_end0-_Z17Thumbnail_ushort2P13__hip_texturePiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Thumbnail_ushort2P13__hip_texturePiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z17Thumbnail_ushort2P13__hip_texturePiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00145eac_00000000-6_Thumbnail_ushort2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii
.type _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii, @function
_Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17Thumbnail_ushort2yPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii, .-_Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii
.globl _Z17Thumbnail_ushort2yPiii
.type _Z17Thumbnail_ushort2yPiii, @function
_Z17Thumbnail_ushort2yPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17Thumbnail_ushort2yPiiiyPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17Thumbnail_ushort2yPiii, .-_Z17Thumbnail_ushort2yPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17Thumbnail_ushort2yPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17Thumbnail_ushort2yPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Thumbnail_ushort2.hip"
.globl _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii # -- Begin function _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.p2align 4, 0x90
.type _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii,@function
_Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii: # @_Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17Thumbnail_ushort2P13__hip_texturePiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii, .Lfunc_end0-_Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17Thumbnail_ushort2P13__hip_texturePiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17Thumbnail_ushort2P13__hip_texturePiii,@object # @_Z17Thumbnail_ushort2P13__hip_texturePiii
.section .rodata,"a",@progbits
.globl _Z17Thumbnail_ushort2P13__hip_texturePiii
.p2align 3, 0x0
_Z17Thumbnail_ushort2P13__hip_texturePiii:
.quad _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.size _Z17Thumbnail_ushort2P13__hip_texturePiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17Thumbnail_ushort2P13__hip_texturePiii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__Thumbnail_ushort2P13__hip_texturePiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17Thumbnail_ushort2P13__hip_texturePiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// GPU¸¦ À§ÇÑ Ä¿³Î ÇÁ·Î±×·¥(NVCC°¡ ÄÄÆÄÀÏÇÔ)
__global__ void addKernel(int* c, const int * a, const int * b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// GPU¸¦ À§ÇÑ Ä¿³Î ÇÁ·Î±×·¥(NVCC°¡ ÄÄÆÄÀÏÇÔ)
__global__ void addKernel(int* c, const int * a, const int * b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | .file "tmpxft_00118b84_00000000-6_addKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// GPU¸¦ À§ÇÑ Ä¿³Î ÇÁ·Î±×·¥(NVCC°¡ ÄÄÆÄÀÏÇÔ)
__global__ void addKernel(int* c, const int * a, const int * b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
// GPU¸¦ À§ÇÑ Ä¿³Î ÇÁ·Î±×·¥(NVCC°¡ ÄÄÆÄÀÏÇÔ)
__global__ void addKernel(int* c, const int * a, const int * b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// GPU¸¦ À§ÇÑ Ä¿³Î ÇÁ·Î±×·¥(NVCC°¡ ÄÄÆÄÀÏÇÔ)
__global__ void addKernel(int* c, const int * a, const int * b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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