system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// GPU¸¦ À§ÇÑ Ä¿³Î ÇÁ·Î±×·¥(NVCC°¡ ÄÄÆÄÀÏÇÔ)
__global__ void addKernel(int* c, const int * a, const int * b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | .text
.file "addKernel.hip"
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118b84_00000000-6_addKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addKernel.hip"
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
// Kernel wykonywane na "CUDA device"
__host__ __device__ float f(float x){
return exp(x*x)*cos(x);
}
__global__ void oblicz_fx(float h, float a, float *w)
{
// rozmiar bloku równy 64
__shared__ float y[64];
int i = blockIdx.x * blockDim.x + threadIdx.x;
y[threadIdx.x] = f(a+(i+1)*h);
__syncthreads();
if(threadIdx.x%2==0) y[threadIdx.x]+=y[threadIdx.x+1];
__syncthreads();
if(threadIdx.x%4==0) y[threadIdx.x]+=y[threadIdx.x+2];
__syncthreads();
if(threadIdx.x%8==0) y[threadIdx.x]+=y[threadIdx.x+4];
__syncthreads();
if(threadIdx.x%16==0) y[threadIdx.x]+=y[threadIdx.x+8];
__syncthreads();
if(threadIdx.x%32==0) y[threadIdx.x]+=y[threadIdx.x+16];
__syncthreads();
if(threadIdx.x==0) {
y[threadIdx.x]+=y[threadIdx.x+32];
w[blockIdx.x]=y[threadIdx.x];
}
/*
if(threadIdx.x==0){
float x=0;
for(int i=0;i<blockDim.x;i++)
x+=y[i];
w[blockIdx.x]=x;
}
*/
}
// program wykonywany na "host computer"
int main(void)
{
float *w_h, *w_d; // wskazniki do tablic na host i device
const int N = 4*65536+1; // liczba elementow tablicy
float a=0.0;
float b=1.0;
float h=(b-a)/N;
int bsize=64;
int gsize=(N-1)/bsize;
size_t size = gsize * sizeof(float);
w_h = (float *)malloc(size); // alokacja tablicy na host
cudaMalloc((void **) &w_d, size); // alokacja tablicy na device
// wykonanie obliczen na device
oblicz_fx <<< gsize, bsize >>> (h,a,w_d);
// skopiowanie wynikow z pamieci karty do pomieci hosta
cudaMemcpy(w_h, w_d, sizeof(float)*gsize, cudaMemcpyDeviceToHost);
// Print results
float sum=0.5*(f(a)+f(b));
for (int i=0; i<gsize; i++)
sum+=w_h[i];
sum*=h;
printf("calka=%f\n", sum);
// zwolnienie pamieci
free(w_h);
cudaFree(w_d);
} | code for sm_80
Function : _Z9oblicz_fxffPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x7e0 ; /* 0x0000079000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0200 */
/*0070*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc80007ffe0ff */
/*0080*/ I2F R2, R4 ; /* 0x0000000400027306 */
/* 0x000e240000201400 */
/*0090*/ FFMA R2, R2, R5, c[0x0][0x164] ; /* 0x0000590002027623 */
/* 0x001fc80000000005 */
/*00a0*/ FMUL R5, R2.reuse, 0.63661974668502807617 ; /* 0x3f22f98302057820 */
/* 0x040fe20000400000 */
/*00b0*/ FSETP.GE.AND P0, PT, |R2|, 105615, PT ; /* 0x47ce47800200780b */
/* 0x000fca0003f06200 */
/*00c0*/ F2I.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e300000203100 */
/*00d0*/ I2F R7, R5 ; /* 0x0000000500077306 */
/* 0x001e240000201400 */
/*00e0*/ FFMA R6, R7, -1.5707962512969970703, R2 ; /* 0xbfc90fda07067823 */
/* 0x001fc80000000002 */
/*00f0*/ FFMA R6, R7, -7.5497894158615963534e-08, R6 ; /* 0xb3a2216807067823 */
/* 0x000fc80000000006 */
/*0100*/ FFMA R10, R7, -5.3903029534742383927e-15, R6 ; /* 0xa7c234c5070a7823 */
/* 0x000fe20000000006 */
/*0110*/ @!P0 BRA 0x7d0 ; /* 0x000006b000008947 */
/* 0x000fea0003800000 */
/*0120*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f0d200 */
/*0130*/ @!P0 BRA 0x7b0 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fe20000011602 */
/*0150*/ IMAD.SHL.U32 R6, R2, 0x100, RZ ; /* 0x0000010002067824 */
/* 0x000fe200078e00ff */
/*0160*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R5, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04057812 */
/* 0x000fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R11, R6, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000060b7812 */
/* 0x000fe200078efcff */
/*01b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01c0*/ IADD3 R5, R5, -0x80, RZ ; /* 0xffffff8005057810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ SHF.R.U32.HI R12, RZ, 0x5, R5 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011605 */
/*01f0*/ IMAD.U32 R6, RZ, RZ, UR8 ; /* 0x00000008ff067e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R7, RZ, RZ, UR9 ; /* 0x00000009ff077e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0240*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0250*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0260*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0270*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0280*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0290*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*02a0*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02b0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R8, R6, R11, RZ ; /* 0x0000000b06087225 */
/* 0x004fca00078e00ff */
/*02d0*/ IADD3 R8, P6, R8, R4, RZ ; /* 0x0000000408087210 */
/* 0x000fc80007fde0ff */
/*02e0*/ IADD3.X R4, R9, UR4, RZ, P6, !PT ; /* 0x0000000409047c10 */
/* 0x000fe2000b7fe4ff */
/*02f0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R8.reuse ; /* 0x000000ffff0a0224 */
/* 0x100fe200078e0008 */
/*0300*/ ISETP.NE.AND P6, PT, R13, 0x6, PT ; /* 0x000000060d00780c */
/* 0x000fe20003fc5270 */
/*0310*/ @P5 IMAD.MOV.U32 R15, RZ, RZ, R8.reuse ; /* 0x000000ffff0f5224 */
/* 0x100fe200078e0008 */
/*0320*/ @P3 MOV R17, R8 ; /* 0x0000000800113202 */
/* 0x000fe20000000f00 */
/*0330*/ @P4 IMAD.MOV.U32 R16, RZ, RZ, R8.reuse ; /* 0x000000ffff104224 */
/* 0x100fe400078e0008 */
/*0340*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R8.reuse ; /* 0x000000ffff122224 */
/* 0x100fe400078e0008 */
/*0350*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e1224 */
/* 0x000fcc00078e0008 */
/*0360*/ @P6 BRA 0x1f0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R6, -R12, 0x6, RZ ; /* 0x000000060c067810 */
/* 0x000fe20007ffe1ff */
/*0380*/ BSSY B1, 0x6a0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*0390*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03b0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03c0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03d0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03e0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03f0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R10.reuse ; /* 0x000000ffff070224 */
/* 0x100fe200078e000a */
/*0400*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0410*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff083224 */
/* 0x000fe200078e000a */
/*0420*/ @P3 MOV R7, R15 ; /* 0x0000000f00073202 */
/* 0x000fe20000000f00 */
/*0430*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R15 ; /* 0x000000ffff084224 */
/* 0x000fe200078e000f */
/*0440*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0450*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R16.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e0010 */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff082224 */
/* 0x000fe200078e0010 */
/*0480*/ @P1 MOV R8, R17 ; /* 0x0000001100081202 */
/* 0x000fe20000000f00 */
/*0490*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff072224 */
/* 0x000fc400078e0011 */
/*04a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0012 */
/*04b0*/ LOP3.LUT P1, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fe2000782c0ff */
/*04c0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fe400078e000e */
/*04d0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff080224 */
/* 0x000fe400078e0012 */
/*04e0*/ @P3 MOV R7, R4 ; /* 0x0000000400073202 */
/* 0x000fe20000000f00 */
/*04f0*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff083224 */
/* 0x000fe400078e000e */
/*0500*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff084224 */
/* 0x000fe400078e0004 */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0007 */
/*0520*/ @!P1 BRA 0x690 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0530*/ IADD3 R12, -R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe1ff */
/*0540*/ IADD3 R7, -R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fe40007ffe1ff */
/*0550*/ SHF.L.U32 R9, R8, R6, RZ ; /* 0x0000000608097219 */
/* 0x000fe200000006ff */
/*0560*/ IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0c7824 */
/* 0x000fca00078e00ff */
/*0570*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x4, PT ; /* 0x000000040c00780c */
/* 0x040fe40003f22270 */
/*0580*/ ISETP.EQ.AND P2, PT, R12.reuse, 0x8, PT ; /* 0x000000080c00780c */
/* 0x040fe40003f42270 */
/*0590*/ ISETP.EQ.AND P0, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f02270 */
/*05a0*/ ISETP.EQ.AND P3, PT, R12.reuse, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x040fe40003f62270 */
/*05b0*/ ISETP.EQ.AND P0, PT, R12, 0x10, PT ; /* 0x000000100c00780c */
/* 0x000fca0003f02270 */
/*05c0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e000f */
/*05d0*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x14, PT ; /* 0x000000140c00780c */
/* 0x040fe40003f22270 */
/*05e0*/ @P2 MOV R10, R16 ; /* 0x00000010000a2202 */
/* 0x000fe40000000f00 */
/*05f0*/ ISETP.EQ.AND P2, PT, R12, 0x18, PT ; /* 0x000000180c00780c */
/* 0x000fe20003f42270 */
/*0600*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e0011 */
/*0610*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a0224 */
/* 0x000fcc00078e0012 */
/*0620*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fc800078e000e */
/*0630*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0004 */
/*0640*/ SHF.L.U32 R4, R5, R6, RZ ; /* 0x0000000605047219 */
/* 0x000fe400000006ff */
/*0650*/ SHF.R.U32.HI R5, RZ, R7.reuse, R8 ; /* 0x00000007ff057219 */
/* 0x080fe40000011608 */
/*0660*/ SHF.R.U32.HI R10, RZ, R7, R10 ; /* 0x00000007ff0a7219 */
/* 0x000fe4000001160a */
/*0670*/ IADD3 R5, R5, R4, RZ ; /* 0x0000000405057210 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.IADD R8, R10, 0x1, R9 ; /* 0x000000010a087824 */
/* 0x000fe400078e0209 */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U32.HI R9, R8.reuse, 0x2, R5 ; /* 0x0000000208097819 */
/* 0x040fe20000010605 */
/*06b0*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fe200078e00ff */
/*06c0*/ LOP3.LUT P1, R4, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002047812 */
/* 0x000fe4000782c0ff */
/*06d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*06e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*06f0*/ LEA.HI R5, R5, R10, RZ, 0x2 ; /* 0x0000000a05057211 */
/* 0x000fd600078f10ff */
/*0700*/ @P0 LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff090212 */
/* 0x000fe400078e33ff */
/*0710*/ @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff080212 */
/* 0x000fe400078e33ff */
/*0720*/ @P0 LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000004040812 */
/* 0x000fe400078e3cff */
/*0730*/ I2F.F64.S64 R6, R8 ; /* 0x0000000800067312 */
/* 0x000e240000301c00 */
/*0740*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a05 */
/*0760*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0004 */
/*0770*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0780*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000301000 */
/*0790*/ FSEL R10, R6, -R6, !P0 ; /* 0x80000006060a7208 */
/* 0x001fe20004000000 */
/*07a0*/ BRA 0x7d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07b0*/ FMUL R10, RZ, R2 ; /* 0x00000002ff0a7220 */
/* 0x000fe20000400000 */
/*07c0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe400078e00ff */
/*0800*/ FMUL R4, R2, R2 ; /* 0x0000000202047220 */
/* 0x000fe20000400000 */
/*0810*/ LOP3.LUT P1, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe2000782c0ff */
/*0820*/ IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff077424 */
/* 0x000fe200078e00ff */
/*0830*/ LOP3.LUT P0, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fe2000780c0ff */
/*0840*/ FFMA.SAT R2, R4, R5, 0.5 ; /* 0x3f00000004027423 */
/* 0x000fc40000002005 */
/*0850*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff087424 */
/* 0x000fe400078e00ff */
/*0860*/ FFMA.RM R6, R2, R7, 12582913 ; /* 0x4b40000102067423 */
/* 0x000fe40000004007 */
/*0870*/ FMUL R11, R10.reuse, R10 ; /* 0x0000000a0a0b7220 */
/* 0x040fe20000400000 */
/*0880*/ FSEL R10, R10, 1, !P1 ; /* 0x3f8000000a0a7808 */
/* 0x000fe20004800000 */
/*0890*/ FADD R5, R6, -12583039 ; /* 0xcb40007f06057421 */
/* 0x000fe40000000000 */
/*08a0*/ @P1 MOV R7, 0x37cbac00 ; /* 0x37cbac0000071802 */
/* 0x000fe20000000f00 */
/*08b0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fe400078e00ff */
/*08c0*/ FFMA R5, R4, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b04057823 */
/* 0x000fc40000000805 */
/*08d0*/ @P1 FFMA R2, R11, R7, -0.0013887860113754868507 ; /* 0xbab607ed0b021423 */
/* 0x000fe40000000007 */
/*08e0*/ FFMA R4, R4, 1.925963033500011079e-08, R5 ; /* 0x32a5706004047823 */
/* 0x000fe20000000005 */
/*08f0*/ FSEL R5, R8, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb08057808 */
/* 0x000fe20004800000 */
/*0900*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff077424 */
/* 0x000fe200078e00ff */
/*0910*/ LOP3.LUT R8, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100087812 */
/* 0x000fc600078ec0ff */
/*0920*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e220000000800 */
/*0930*/ FFMA R2, R11, R2, R5 ; /* 0x000000020b027223 */
/* 0x000fe20000000005 */
/*0940*/ FSEL R5, -R7, -0.4999999701976776123, !P1 ; /* 0xbeffffff07057808 */
/* 0x000fe20004800100 */
/*0950*/ IMAD.SHL.U32 R7, R6, 0x800000, RZ ; /* 0x0080000006077824 */
/* 0x000fe200078e00ff */
/*0960*/ ISETP.NE.U32.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc60003f25070 */
/*0970*/ FFMA R5, R11.reuse, R2, R5 ; /* 0x000000020b057223 */
/* 0x040fe40000000005 */
/*0980*/ FFMA R2, R11, R10, RZ ; /* 0x0000000a0b027223 */
/* 0x000fc800000000ff */
/*0990*/ FFMA R2, R5, R2, R10 ; /* 0x0000000205027223 */
/* 0x000fe4000000000a */
/*09a0*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x001fe40000400000 */
/*09b0*/ @P0 FFMA R2, R2, -1, RZ ; /* 0xbf80000002020823 */
/* 0x000fe200000000ff */
/*09c0*/ LOP3.LUT P0, RZ, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300ff7812 */
/* 0x000fc6000780c0ff */
/*09d0*/ FMUL R7, R7, R2 ; /* 0x0000000207077220 */
/* 0x000fca0000400000 */
/*09e0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x000fe80000004800 */
/*09f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a00*/ @P1 LDS R2, [R0.X4] ; /* 0x0000000000021984 */
/* 0x000fe80000004800 */
/*0a10*/ @P1 LDS R5, [R0.X4+0x4] ; /* 0x0000040000051984 */
/* 0x000e240000004800 */
/*0a20*/ @P1 FADD R5, R2, R5 ; /* 0x0000000502051221 */
/* 0x001fca0000000000 */
/*0a30*/ @P1 STS [R0.X4], R5 ; /* 0x0000000500001388 */
/* 0x000fe80000004800 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a50*/ LOP3.LUT P1, RZ, R0, 0x7, RZ, 0xc0, !PT ; /* 0x0000000700ff7812 */
/* 0x000fca000782c0ff */
/*0a60*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0a70*/ @!P0 LDS R9, [R0.X4+0x8] ; /* 0x0000080000098984 */
/* 0x000e240000004800 */
/*0a80*/ @!P0 FADD R9, R2, R9 ; /* 0x0000000902098221 */
/* 0x001fca0000000000 */
/*0a90*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x000fe80000004800 */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ab0*/ LOP3.LUT P0, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fca000780c0ff */
/*0ac0*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*0ad0*/ @!P1 LDS R7, [R0.X4+0x10] ; /* 0x0000100000079984 */
/* 0x000e240000004800 */
/*0ae0*/ @!P1 FADD R7, R2, R7 ; /* 0x0000000702079221 */
/* 0x001fca0000000000 */
/*0af0*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x000fe80000004800 */
/*0b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b10*/ LOP3.LUT P1, RZ, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00ff7812 */
/* 0x000fca000782c0ff */
/*0b20*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0b30*/ @!P0 LDS R5, [R0.X4+0x20] ; /* 0x0000200000058984 */
/* 0x000e240000004800 */
/*0b40*/ @!P0 FADD R5, R2, R5 ; /* 0x0000000502058221 */
/* 0x001fca0000000000 */
/*0b50*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x000fe80000004800 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*0b80*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*0b90*/ @!P1 LDS R9, [R0.X4+0x40] ; /* 0x0000400000099984 */
/* 0x000e240000004800 */
/*0ba0*/ @!P1 FADD R9, R2, R9 ; /* 0x0000000902099221 */
/* 0x001fca0000000000 */
/*0bb0*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x0001e80000004800 */
/*0bc0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bd0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0be0*/ LDS R0, [0x80] ; /* 0x00008000ff007984 */
/* 0x001fe20000000800 */
/*0bf0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0c00*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0c10*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0002 */
/*0c20*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x001fca0000000000 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101906 */
/*0c40*/ STS [RZ], R5 ; /* 0x00000005ff007388 */
/* 0x000fe20000000800 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
// Kernel wykonywane na "CUDA device"
__host__ __device__ float f(float x){
return exp(x*x)*cos(x);
}
__global__ void oblicz_fx(float h, float a, float *w)
{
// rozmiar bloku równy 64
__shared__ float y[64];
int i = blockIdx.x * blockDim.x + threadIdx.x;
y[threadIdx.x] = f(a+(i+1)*h);
__syncthreads();
if(threadIdx.x%2==0) y[threadIdx.x]+=y[threadIdx.x+1];
__syncthreads();
if(threadIdx.x%4==0) y[threadIdx.x]+=y[threadIdx.x+2];
__syncthreads();
if(threadIdx.x%8==0) y[threadIdx.x]+=y[threadIdx.x+4];
__syncthreads();
if(threadIdx.x%16==0) y[threadIdx.x]+=y[threadIdx.x+8];
__syncthreads();
if(threadIdx.x%32==0) y[threadIdx.x]+=y[threadIdx.x+16];
__syncthreads();
if(threadIdx.x==0) {
y[threadIdx.x]+=y[threadIdx.x+32];
w[blockIdx.x]=y[threadIdx.x];
}
/*
if(threadIdx.x==0){
float x=0;
for(int i=0;i<blockDim.x;i++)
x+=y[i];
w[blockIdx.x]=x;
}
*/
}
// program wykonywany na "host computer"
int main(void)
{
float *w_h, *w_d; // wskazniki do tablic na host i device
const int N = 4*65536+1; // liczba elementow tablicy
float a=0.0;
float b=1.0;
float h=(b-a)/N;
int bsize=64;
int gsize=(N-1)/bsize;
size_t size = gsize * sizeof(float);
w_h = (float *)malloc(size); // alokacja tablicy na host
cudaMalloc((void **) &w_d, size); // alokacja tablicy na device
// wykonanie obliczen na device
oblicz_fx <<< gsize, bsize >>> (h,a,w_d);
// skopiowanie wynikow z pamieci karty do pomieci hosta
cudaMemcpy(w_h, w_d, sizeof(float)*gsize, cudaMemcpyDeviceToHost);
// Print results
float sum=0.5*(f(a)+f(b));
for (int i=0; i<gsize; i++)
sum+=w_h[i];
sum*=h;
printf("calka=%f\n", sum);
// zwolnienie pamieci
free(w_h);
cudaFree(w_d);
} | .file "tmpxft_0010bd7f_00000000-6_071_calka_redukcja.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps %xmm0, %xmm1
movss %xmm0, 12(%rsp)
mulss %xmm0, %xmm1
movaps %xmm1, %xmm0
call expf@PLT
movss %xmm0, 8(%rsp)
movss 12(%rsp), %xmm0
call cosf@PLT
mulss 8(%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z1ff, .-_Z1ff
.globl _Z30__device_stub__Z9oblicz_fxffPfffPf
.type _Z30__device_stub__Z9oblicz_fxffPfffPf, @function
_Z30__device_stub__Z9oblicz_fxffPfffPf:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9oblicz_fxffPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9oblicz_fxffPfffPf, .-_Z30__device_stub__Z9oblicz_fxffPfffPf
.globl _Z9oblicz_fxffPf
.type _Z9oblicz_fxffPf, @function
_Z9oblicz_fxffPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9oblicz_fxffPfffPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9oblicz_fxffPf, .-_Z9oblicz_fxffPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "calka=%f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16384, %edi
call malloc@PLT
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movl $16384, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
call _Z1ff
movss %xmm0, 12(%rsp)
movss .LC2(%rip), %xmm0
call _Z1ff
addss 12(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movq %rbx, %rax
leaq 16384(%rbx), %rdx
.L15:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L15
mulss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdi
pxor %xmm1, %xmm1
movss .LC1(%rip), %xmm0
call _Z30__device_stub__Z9oblicz_fxffPfffPf
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9oblicz_fxffPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9oblicz_fxffPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 914358208
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
// Kernel wykonywane na "CUDA device"
__host__ __device__ float f(float x){
return exp(x*x)*cos(x);
}
__global__ void oblicz_fx(float h, float a, float *w)
{
// rozmiar bloku równy 64
__shared__ float y[64];
int i = blockIdx.x * blockDim.x + threadIdx.x;
y[threadIdx.x] = f(a+(i+1)*h);
__syncthreads();
if(threadIdx.x%2==0) y[threadIdx.x]+=y[threadIdx.x+1];
__syncthreads();
if(threadIdx.x%4==0) y[threadIdx.x]+=y[threadIdx.x+2];
__syncthreads();
if(threadIdx.x%8==0) y[threadIdx.x]+=y[threadIdx.x+4];
__syncthreads();
if(threadIdx.x%16==0) y[threadIdx.x]+=y[threadIdx.x+8];
__syncthreads();
if(threadIdx.x%32==0) y[threadIdx.x]+=y[threadIdx.x+16];
__syncthreads();
if(threadIdx.x==0) {
y[threadIdx.x]+=y[threadIdx.x+32];
w[blockIdx.x]=y[threadIdx.x];
}
/*
if(threadIdx.x==0){
float x=0;
for(int i=0;i<blockDim.x;i++)
x+=y[i];
w[blockIdx.x]=x;
}
*/
}
// program wykonywany na "host computer"
int main(void)
{
float *w_h, *w_d; // wskazniki do tablic na host i device
const int N = 4*65536+1; // liczba elementow tablicy
float a=0.0;
float b=1.0;
float h=(b-a)/N;
int bsize=64;
int gsize=(N-1)/bsize;
size_t size = gsize * sizeof(float);
w_h = (float *)malloc(size); // alokacja tablicy na host
cudaMalloc((void **) &w_d, size); // alokacja tablicy na device
// wykonanie obliczen na device
oblicz_fx <<< gsize, bsize >>> (h,a,w_d);
// skopiowanie wynikow z pamieci karty do pomieci hosta
cudaMemcpy(w_h, w_d, sizeof(float)*gsize, cudaMemcpyDeviceToHost);
// Print results
float sum=0.5*(f(a)+f(b));
for (int i=0; i<gsize; i++)
sum+=w_h[i];
sum*=h;
printf("calka=%f\n", sum);
// zwolnienie pamieci
free(w_h);
cudaFree(w_d);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
// Kernel wykonywane na "CUDA device"
__host__ __device__ float f(float x){
return exp(x*x)*cos(x);
}
__global__ void oblicz_fx(float h, float a, float *w)
{
// rozmiar bloku równy 64
__shared__ float y[64];
int i = blockIdx.x * blockDim.x + threadIdx.x;
y[threadIdx.x] = f(a+(i+1)*h);
__syncthreads();
if(threadIdx.x%2==0) y[threadIdx.x]+=y[threadIdx.x+1];
__syncthreads();
if(threadIdx.x%4==0) y[threadIdx.x]+=y[threadIdx.x+2];
__syncthreads();
if(threadIdx.x%8==0) y[threadIdx.x]+=y[threadIdx.x+4];
__syncthreads();
if(threadIdx.x%16==0) y[threadIdx.x]+=y[threadIdx.x+8];
__syncthreads();
if(threadIdx.x%32==0) y[threadIdx.x]+=y[threadIdx.x+16];
__syncthreads();
if(threadIdx.x==0) {
y[threadIdx.x]+=y[threadIdx.x+32];
w[blockIdx.x]=y[threadIdx.x];
}
/*
if(threadIdx.x==0){
float x=0;
for(int i=0;i<blockDim.x;i++)
x+=y[i];
w[blockIdx.x]=x;
}
*/
}
// program wykonywany na "host computer"
int main(void)
{
float *w_h, *w_d; // wskazniki do tablic na host i device
const int N = 4*65536+1; // liczba elementow tablicy
float a=0.0;
float b=1.0;
float h=(b-a)/N;
int bsize=64;
int gsize=(N-1)/bsize;
size_t size = gsize * sizeof(float);
w_h = (float *)malloc(size); // alokacja tablicy na host
hipMalloc((void **) &w_d, size); // alokacja tablicy na device
// wykonanie obliczen na device
oblicz_fx <<< gsize, bsize >>> (h,a,w_d);
// skopiowanie wynikow z pamieci karty do pomieci hosta
hipMemcpy(w_h, w_d, sizeof(float)*gsize, hipMemcpyDeviceToHost);
// Print results
float sum=0.5*(f(a)+f(b));
for (int i=0; i<gsize; i++)
sum+=w_h[i];
sum*=h;
printf("calka=%f\n", sum);
// zwolnienie pamieci
free(w_h);
hipFree(w_d);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// Kernel wykonywane na "CUDA device"
__host__ __device__ float f(float x){
return exp(x*x)*cos(x);
}
__global__ void oblicz_fx(float h, float a, float *w)
{
// rozmiar bloku równy 64
__shared__ float y[64];
int i = blockIdx.x * blockDim.x + threadIdx.x;
y[threadIdx.x] = f(a+(i+1)*h);
__syncthreads();
if(threadIdx.x%2==0) y[threadIdx.x]+=y[threadIdx.x+1];
__syncthreads();
if(threadIdx.x%4==0) y[threadIdx.x]+=y[threadIdx.x+2];
__syncthreads();
if(threadIdx.x%8==0) y[threadIdx.x]+=y[threadIdx.x+4];
__syncthreads();
if(threadIdx.x%16==0) y[threadIdx.x]+=y[threadIdx.x+8];
__syncthreads();
if(threadIdx.x%32==0) y[threadIdx.x]+=y[threadIdx.x+16];
__syncthreads();
if(threadIdx.x==0) {
y[threadIdx.x]+=y[threadIdx.x+32];
w[blockIdx.x]=y[threadIdx.x];
}
/*
if(threadIdx.x==0){
float x=0;
for(int i=0;i<blockDim.x;i++)
x+=y[i];
w[blockIdx.x]=x;
}
*/
}
// program wykonywany na "host computer"
int main(void)
{
float *w_h, *w_d; // wskazniki do tablic na host i device
const int N = 4*65536+1; // liczba elementow tablicy
float a=0.0;
float b=1.0;
float h=(b-a)/N;
int bsize=64;
int gsize=(N-1)/bsize;
size_t size = gsize * sizeof(float);
w_h = (float *)malloc(size); // alokacja tablicy na host
hipMalloc((void **) &w_d, size); // alokacja tablicy na device
// wykonanie obliczen na device
oblicz_fx <<< gsize, bsize >>> (h,a,w_d);
// skopiowanie wynikow z pamieci karty do pomieci hosta
hipMemcpy(w_h, w_d, sizeof(float)*gsize, hipMemcpyDeviceToHost);
// Print results
float sum=0.5*(f(a)+f(b));
for (int i=0; i<gsize; i++)
sum+=w_h[i];
sum*=h;
printf("calka=%f\n", sum);
// zwolnienie pamieci
free(w_h);
hipFree(w_d);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9oblicz_fxffPf
.globl _Z9oblicz_fxffPf
.p2align 8
.type _Z9oblicz_fxffPf,@function
_Z9oblicz_fxffPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s5
v_add3_u32 v1, v0, s5, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_fma_f32 v1, v1, s2, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v1|
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v9, 0x7fffffff, v1
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v12, v9, s2, 0x800000
v_lshrrev_b32_e32 v9, 23, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v12, 0xfe5163ab, 0
v_add_nc_u32_e32 v10, 0xffffff88, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v10
v_mad_u64_u32 v[5:6], null, v12, 0x3c439041, v[3:4]
v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v6
v_add_nc_u32_e32 v11, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v12, 0xdb629599, v[3:4]
v_cmp_lt_u32_e64 s2, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, 0, 0xffffffe0, s2
v_dual_mov_b32 v3, v7 :: v_dual_cndmask_b32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, v13, v11
v_mad_u64_u32 v[7:8], null, v12, 0xf534ddc0, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v13
v_mov_b32_e32 v3, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v7, v5, vcc_lo
v_mad_u64_u32 v[8:9], null, v12, 0xfc2757d1, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, v5, v2, s2
v_mov_b32_e32 v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v12, 0x4e441529, v[3:4]
v_mov_b32_e32 v3, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, 0xa2f9836e, v[3:4]
v_cndmask_b32_e64 v3, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v4, v9, v7 :: v_dual_add_nc_u32 v3, v3, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v10, v10, v8 :: v_dual_cndmask_b32 v9, v11, v9
v_cndmask_b32_e32 v8, v8, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, v10, v4, s2
v_cndmask_b32_e64 v9, v9, v10, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v4, v4, v8, s2
v_sub_nc_u32_e32 v10, 32, v3
v_cndmask_b32_e64 v8, v8, v5, s2
v_cndmask_b32_e64 v9, v9, v7, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v4, s3
v_cndmask_b32_e64 v4, v4, v8, s3
v_cndmask_b32_e64 v2, v8, v2, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v9, v7, v10
v_alignbit_b32 v6, v7, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v3, v11, v9, vcc_lo
v_alignbit_b32 v9, v4, v2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v6, v7, vcc_lo
v_bfe_u32 v6, v3, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v9, v4, vcc_lo
v_alignbit_b32 v7, v3, v5, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v8, 0, v6
v_alignbit_b32 v5, v5, v4, 30
v_alignbit_b32 v2, v4, v2, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v8
v_xor_b32_e32 v4, v5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v8
v_clz_i32_u32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v9, 32, v9
v_sub_nc_u32_e32 v5, 31, v9
v_lshlrev_b32_e32 v11, 23, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v7, v7, v4, v5
v_alignbit_b32 v2, v4, v2, v5
v_lshrrev_b32_e32 v5, 29, v3
v_alignbit_b32 v4, v7, v2, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 31, v5
v_lshrrev_b32_e32 v7, 9, v7
v_clz_i32_u32_e32 v8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v10, 0.5, v5
v_min_u32_e32 v8, 32, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v10, v11
v_sub_nc_u32_e32 v12, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v2, v4, v2, v12
v_or_b32_e32 v4, v7, v10
v_add_lshl_u32 v7, v8, v9, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v2, 9, v2
v_mul_f32_e32 v8, 0x3fc90fda, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v7
v_fma_f32 v7, v4, 0x3fc90fda, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x33000000, v2
v_fmamk_f32 v4, v4, 0x33a22168, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v2, v5
v_fmac_f32_e32 v4, 0x3fc90fda, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v8, v4
v_lshrrev_b32_e32 v3, 30, v3
v_add_nc_u32_e32 v3, v6, v3
.LBB0_2:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v2, 0x3f22f983, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v3, v2
v_fma_f32 v2, v3, 0xbfc90fda, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v3, 0xb3a22168, v2
v_fmamk_f32 v2, v3, 0xa7c234c4, v2
v_cvt_i32_f32_e32 v3, v3
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v2, v2
s_mov_b32 s2, 0xb94c1982
v_mul_f32_e32 v4, v1, v1
s_mov_b32 s3, 0x37d75334
v_fmaak_f32 v9, s2, v6, 0x3c0881c4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v6, v9, 0xbe2aaa9d
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_rndne_f32_e32 v7, v5
v_fma_f32 v8, v4, 0x3fb8aa3b, -v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v5, v5, v7 :: v_dual_fmamk_f32 v8, v4, 0x32a5705f, v8
v_fmaak_f32 v10, s3, v6, 0xbab64f3b
v_cvt_i32_f32_e32 v7, v7
v_dual_add_f32 v5, v5, v8 :: v_dual_mul_f32 v8, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v7
v_fmaak_f32 v10, v6, v10, 0x3d2aabf7
v_dual_fmaak_f32 v9, v6, v10, 0xbf000004 :: v_dual_and_b32 v10, 1, v3
v_dual_fmac_f32 v2, v2, v8 :: v_dual_lshlrev_b32 v3, 30, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v6, v6, v9, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v3, 0x80000000, v3
v_cndmask_b32_e64 v2, -v2, v6, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v3, v2
v_cndmask_b32_e32 v3, 0, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x1f8
v_dual_cndmask_b32 v2, 0x7fc00000, v2 :: v_dual_lshlrev_b32 v1, 2, v0
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, 0x7f800000, v3 :: v_dual_and_b32 v4, 1, v0
v_mul_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_6
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 3, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 7, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 15, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 31, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_16
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, 0
ds_load_b32 v2, v1
ds_load_b32 v3, v0 offset:128
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
global_store_b32 v0, v2, s[0:1]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9oblicz_fxffPf
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9oblicz_fxffPf, .Lfunc_end0-_Z9oblicz_fxffPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9oblicz_fxffPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9oblicz_fxffPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// Kernel wykonywane na "CUDA device"
__host__ __device__ float f(float x){
return exp(x*x)*cos(x);
}
__global__ void oblicz_fx(float h, float a, float *w)
{
// rozmiar bloku równy 64
__shared__ float y[64];
int i = blockIdx.x * blockDim.x + threadIdx.x;
y[threadIdx.x] = f(a+(i+1)*h);
__syncthreads();
if(threadIdx.x%2==0) y[threadIdx.x]+=y[threadIdx.x+1];
__syncthreads();
if(threadIdx.x%4==0) y[threadIdx.x]+=y[threadIdx.x+2];
__syncthreads();
if(threadIdx.x%8==0) y[threadIdx.x]+=y[threadIdx.x+4];
__syncthreads();
if(threadIdx.x%16==0) y[threadIdx.x]+=y[threadIdx.x+8];
__syncthreads();
if(threadIdx.x%32==0) y[threadIdx.x]+=y[threadIdx.x+16];
__syncthreads();
if(threadIdx.x==0) {
y[threadIdx.x]+=y[threadIdx.x+32];
w[blockIdx.x]=y[threadIdx.x];
}
/*
if(threadIdx.x==0){
float x=0;
for(int i=0;i<blockDim.x;i++)
x+=y[i];
w[blockIdx.x]=x;
}
*/
}
// program wykonywany na "host computer"
int main(void)
{
float *w_h, *w_d; // wskazniki do tablic na host i device
const int N = 4*65536+1; // liczba elementow tablicy
float a=0.0;
float b=1.0;
float h=(b-a)/N;
int bsize=64;
int gsize=(N-1)/bsize;
size_t size = gsize * sizeof(float);
w_h = (float *)malloc(size); // alokacja tablicy na host
hipMalloc((void **) &w_d, size); // alokacja tablicy na device
// wykonanie obliczen na device
oblicz_fx <<< gsize, bsize >>> (h,a,w_d);
// skopiowanie wynikow z pamieci karty do pomieci hosta
hipMemcpy(w_h, w_d, sizeof(float)*gsize, hipMemcpyDeviceToHost);
// Print results
float sum=0.5*(f(a)+f(b));
for (int i=0; i<gsize; i++)
sum+=w_h[i];
sum*=h;
printf("calka=%f\n", sum);
// zwolnienie pamieci
free(w_h);
hipFree(w_d);
} | .text
.file "071_calka_redukcja.hip"
.globl _Z1ff # -- Begin function _Z1ff
.p2align 4, 0x90
.type _Z1ff,@function
_Z1ff: # @_Z1ff
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 12(%rsp) # 4-byte Spill
movaps %xmm0, %xmm1
mulss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
callq exp
movsd %xmm0, 16(%rsp) # 8-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z1ff, .Lfunc_end0-_Z1ff
.cfi_endproc
# -- End function
.globl _Z24__device_stub__oblicz_fxffPf # -- Begin function _Z24__device_stub__oblicz_fxffPf
.p2align 4, 0x90
.type _Z24__device_stub__oblicz_fxffPf,@function
_Z24__device_stub__oblicz_fxffPf: # @_Z24__device_stub__oblicz_fxffPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %rdi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9oblicz_fxffPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__oblicz_fxffPf, .Lfunc_end1-_Z24__device_stub__oblicz_fxffPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f9dff15 # float 1.23434699
.LCPI2_1:
.long 0x367fffc0 # float 3.81468271E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movabsq $4294967360, %rdx # imm = 0x100000040
leaq 4032(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movl $914358208, 20(%rsp) # imm = 0x367FFFC0
movl $0, 16(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9oblicz_fxffPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB2_3
# %bb.4:
mulss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9oblicz_fxffPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9oblicz_fxffPf,@object # @_Z9oblicz_fxffPf
.section .rodata,"a",@progbits
.globl _Z9oblicz_fxffPf
.p2align 3, 0x0
_Z9oblicz_fxffPf:
.quad _Z24__device_stub__oblicz_fxffPf
.size _Z9oblicz_fxffPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "calka=%f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9oblicz_fxffPf"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__oblicz_fxffPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9oblicz_fxffPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9oblicz_fxffPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x7e0 ; /* 0x0000079000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0200 */
/*0070*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc80007ffe0ff */
/*0080*/ I2F R2, R4 ; /* 0x0000000400027306 */
/* 0x000e240000201400 */
/*0090*/ FFMA R2, R2, R5, c[0x0][0x164] ; /* 0x0000590002027623 */
/* 0x001fc80000000005 */
/*00a0*/ FMUL R5, R2.reuse, 0.63661974668502807617 ; /* 0x3f22f98302057820 */
/* 0x040fe20000400000 */
/*00b0*/ FSETP.GE.AND P0, PT, |R2|, 105615, PT ; /* 0x47ce47800200780b */
/* 0x000fca0003f06200 */
/*00c0*/ F2I.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e300000203100 */
/*00d0*/ I2F R7, R5 ; /* 0x0000000500077306 */
/* 0x001e240000201400 */
/*00e0*/ FFMA R6, R7, -1.5707962512969970703, R2 ; /* 0xbfc90fda07067823 */
/* 0x001fc80000000002 */
/*00f0*/ FFMA R6, R7, -7.5497894158615963534e-08, R6 ; /* 0xb3a2216807067823 */
/* 0x000fc80000000006 */
/*0100*/ FFMA R10, R7, -5.3903029534742383927e-15, R6 ; /* 0xa7c234c5070a7823 */
/* 0x000fe20000000006 */
/*0110*/ @!P0 BRA 0x7d0 ; /* 0x000006b000008947 */
/* 0x000fea0003800000 */
/*0120*/ FSETP.NEU.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f0d200 */
/*0130*/ @!P0 BRA 0x7b0 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fe20000011602 */
/*0150*/ IMAD.SHL.U32 R6, R2, 0x100, RZ ; /* 0x0000010002067824 */
/* 0x000fe200078e00ff */
/*0160*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R5, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04057812 */
/* 0x000fe200078ec0ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R11, R6, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000060b7812 */
/* 0x000fe200078efcff */
/*01b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01c0*/ IADD3 R5, R5, -0x80, RZ ; /* 0xffffff8005057810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fc60000000a00 */
/*01e0*/ SHF.R.U32.HI R12, RZ, 0x5, R5 ; /* 0x00000005ff0c7819 */
/* 0x000fe40000011605 */
/*01f0*/ IMAD.U32 R6, RZ, RZ, UR8 ; /* 0x00000008ff067e24 */
/* 0x000fe4000f8e00ff */
/*0200*/ IMAD.U32 R7, RZ, RZ, UR9 ; /* 0x00000009ff077e24 */
/* 0x000fca000f8e00ff */
/*0210*/ LDG.E.CONSTANT R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e9900 */
/*0220*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*0230*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fe2000ff1e03f */
/*0240*/ ISETP.EQ.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f02270 */
/*0250*/ ISETP.EQ.AND P5, PT, R19.reuse, 0x4, PT ; /* 0x000000041300780c */
/* 0x040fe20003fa2270 */
/*0260*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0270*/ ISETP.EQ.AND P4, PT, R19.reuse, 0x8, PT ; /* 0x000000081300780c */
/* 0x040fe40003f82270 */
/*0280*/ ISETP.EQ.AND P3, PT, R19.reuse, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x040fe40003f62270 */
/*0290*/ ISETP.EQ.AND P2, PT, R19, 0x10, PT ; /* 0x000000101300780c */
/* 0x000fc40003f42270 */
/*02a0*/ ISETP.EQ.AND P1, PT, R19.reuse, 0x14, PT ; /* 0x000000141300780c */
/* 0x040fe40003f22270 */
/*02b0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.WIDE.U32 R8, R6, R11, RZ ; /* 0x0000000b06087225 */
/* 0x004fca00078e00ff */
/*02d0*/ IADD3 R8, P6, R8, R4, RZ ; /* 0x0000000408087210 */
/* 0x000fc80007fde0ff */
/*02e0*/ IADD3.X R4, R9, UR4, RZ, P6, !PT ; /* 0x0000000409047c10 */
/* 0x000fe2000b7fe4ff */
/*02f0*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R8.reuse ; /* 0x000000ffff0a0224 */
/* 0x100fe200078e0008 */
/*0300*/ ISETP.NE.AND P6, PT, R13, 0x6, PT ; /* 0x000000060d00780c */
/* 0x000fe20003fc5270 */
/*0310*/ @P5 IMAD.MOV.U32 R15, RZ, RZ, R8.reuse ; /* 0x000000ffff0f5224 */
/* 0x100fe200078e0008 */
/*0320*/ @P3 MOV R17, R8 ; /* 0x0000000800113202 */
/* 0x000fe20000000f00 */
/*0330*/ @P4 IMAD.MOV.U32 R16, RZ, RZ, R8.reuse ; /* 0x000000ffff104224 */
/* 0x100fe400078e0008 */
/*0340*/ @P2 IMAD.MOV.U32 R18, RZ, RZ, R8.reuse ; /* 0x000000ffff122224 */
/* 0x100fe400078e0008 */
/*0350*/ @P1 IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e1224 */
/* 0x000fcc00078e0008 */
/*0360*/ @P6 BRA 0x1f0 ; /* 0xfffffe8000006947 */
/* 0x000fea000383ffff */
/*0370*/ IADD3 R6, -R12, 0x6, RZ ; /* 0x000000060c067810 */
/* 0x000fe20007ffe1ff */
/*0380*/ BSSY B1, 0x6a0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*0390*/ IMAD.SHL.U32 R6, R6, 0x4, RZ ; /* 0x0000000406067824 */
/* 0x000fca00078e00ff */
/*03a0*/ ISETP.EQ.AND P0, PT, R6.reuse, RZ, PT ; /* 0x000000ff0600720c */
/* 0x040fe40003f02270 */
/*03b0*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x4, PT ; /* 0x000000040600780c */
/* 0x040fe40003f62270 */
/*03c0*/ ISETP.EQ.AND P4, PT, R6.reuse, 0x8, PT ; /* 0x000000080600780c */
/* 0x040fe40003f82270 */
/*03d0*/ ISETP.EQ.AND P2, PT, R6.reuse, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x040fe40003f42270 */
/*03e0*/ ISETP.EQ.AND P1, PT, R6, 0x10, PT ; /* 0x000000100600780c */
/* 0x000fca0003f22270 */
/*03f0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R10.reuse ; /* 0x000000ffff070224 */
/* 0x100fe200078e000a */
/*0400*/ ISETP.EQ.AND P0, PT, R6.reuse, 0x14, PT ; /* 0x000000140600780c */
/* 0x040fe20003f02270 */
/*0410*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff083224 */
/* 0x000fe200078e000a */
/*0420*/ @P3 MOV R7, R15 ; /* 0x0000000f00073202 */
/* 0x000fe20000000f00 */
/*0430*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R15 ; /* 0x000000ffff084224 */
/* 0x000fe200078e000f */
/*0440*/ ISETP.EQ.AND P3, PT, R6.reuse, 0x18, PT ; /* 0x000000180600780c */
/* 0x040fe20003f62270 */
/*0450*/ @P4 IMAD.MOV.U32 R7, RZ, RZ, R16.reuse ; /* 0x000000ffff074224 */
/* 0x100fe200078e0010 */
/*0460*/ ISETP.EQ.AND P4, PT, R6, 0x1c, PT ; /* 0x0000001c0600780c */
/* 0x000fe20003f82270 */
/*0470*/ @P2 IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff082224 */
/* 0x000fe200078e0010 */
/*0480*/ @P1 MOV R8, R17 ; /* 0x0000001100081202 */
/* 0x000fe20000000f00 */
/*0490*/ @P2 IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff072224 */
/* 0x000fc400078e0011 */
/*04a0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff071224 */
/* 0x000fe200078e0012 */
/*04b0*/ LOP3.LUT P1, R6, R5, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f05067812 */
/* 0x000fe2000782c0ff */
/*04c0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, R14 ; /* 0x000000ffff070224 */
/* 0x000fe400078e000e */
/*04d0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff080224 */
/* 0x000fe400078e0012 */
/*04e0*/ @P3 MOV R7, R4 ; /* 0x0000000400073202 */
/* 0x000fe20000000f00 */
/*04f0*/ @P3 IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff083224 */
/* 0x000fe400078e000e */
/*0500*/ @P4 IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff084224 */
/* 0x000fe400078e0004 */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fc600078e0007 */
/*0520*/ @!P1 BRA 0x690 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0530*/ IADD3 R12, -R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe1ff */
/*0540*/ IADD3 R7, -R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fe40007ffe1ff */
/*0550*/ SHF.L.U32 R9, R8, R6, RZ ; /* 0x0000000608097219 */
/* 0x000fe200000006ff */
/*0560*/ IMAD.SHL.U32 R12, R12, 0x4, RZ ; /* 0x000000040c0c7824 */
/* 0x000fca00078e00ff */
/*0570*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x4, PT ; /* 0x000000040c00780c */
/* 0x040fe40003f22270 */
/*0580*/ ISETP.EQ.AND P2, PT, R12.reuse, 0x8, PT ; /* 0x000000080c00780c */
/* 0x040fe40003f42270 */
/*0590*/ ISETP.EQ.AND P0, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f02270 */
/*05a0*/ ISETP.EQ.AND P3, PT, R12.reuse, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x040fe40003f62270 */
/*05b0*/ ISETP.EQ.AND P0, PT, R12, 0x10, PT ; /* 0x000000100c00780c */
/* 0x000fca0003f02270 */
/*05c0*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R15 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e000f */
/*05d0*/ ISETP.EQ.AND P1, PT, R12.reuse, 0x14, PT ; /* 0x000000140c00780c */
/* 0x040fe40003f22270 */
/*05e0*/ @P2 MOV R10, R16 ; /* 0x00000010000a2202 */
/* 0x000fe40000000f00 */
/*05f0*/ ISETP.EQ.AND P2, PT, R12, 0x18, PT ; /* 0x000000180c00780c */
/* 0x000fe20003f42270 */
/*0600*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R17 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e0011 */
/*0610*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, R18 ; /* 0x000000ffff0a0224 */
/* 0x000fcc00078e0012 */
/*0620*/ @P1 IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a1224 */
/* 0x000fc800078e000e */
/*0630*/ @P2 IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a2224 */
/* 0x000fe200078e0004 */
/*0640*/ SHF.L.U32 R4, R5, R6, RZ ; /* 0x0000000605047219 */
/* 0x000fe400000006ff */
/*0650*/ SHF.R.U32.HI R5, RZ, R7.reuse, R8 ; /* 0x00000007ff057219 */
/* 0x080fe40000011608 */
/*0660*/ SHF.R.U32.HI R10, RZ, R7, R10 ; /* 0x00000007ff0a7219 */
/* 0x000fe4000001160a */
/*0670*/ IADD3 R5, R5, R4, RZ ; /* 0x0000000405057210 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.IADD R8, R10, 0x1, R9 ; /* 0x000000010a087824 */
/* 0x000fe400078e0209 */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ SHF.L.U32.HI R9, R8.reuse, 0x2, R5 ; /* 0x0000000208097819 */
/* 0x040fe20000010605 */
/*06b0*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fe200078e00ff */
/*06c0*/ LOP3.LUT P1, R4, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002047812 */
/* 0x000fe4000782c0ff */
/*06d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*06e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*06f0*/ LEA.HI R5, R5, R10, RZ, 0x2 ; /* 0x0000000a05057211 */
/* 0x000fd600078f10ff */
/*0700*/ @P0 LOP3.LUT R9, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff090212 */
/* 0x000fe400078e33ff */
/*0710*/ @P0 LOP3.LUT R8, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff080212 */
/* 0x000fe400078e33ff */
/*0720*/ @P0 LOP3.LUT R4, R4, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000004040812 */
/* 0x000fe400078e3cff */
/*0730*/ I2F.F64.S64 R6, R8 ; /* 0x0000000800067312 */
/* 0x000e240000301c00 */
/*0740*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0750*/ IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a05 */
/*0760*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0004 */
/*0770*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0780*/ F2F.F32.F64 R6, R6 ; /* 0x0000000600067310 */
/* 0x001e240000301000 */
/*0790*/ FSEL R10, R6, -R6, !P0 ; /* 0x80000006060a7208 */
/* 0x001fe20004000000 */
/*07a0*/ BRA 0x7d0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*07b0*/ FMUL R10, RZ, R2 ; /* 0x00000002ff0a7220 */
/* 0x000fe20000400000 */
/*07c0*/ MOV R5, RZ ; /* 0x000000ff00057202 */
/* 0x000fe40000000f00 */
/*07d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07e0*/ IADD3 R9, R5, 0x1, RZ ; /* 0x0000000105097810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff057424 */
/* 0x000fe400078e00ff */
/*0800*/ FMUL R4, R2, R2 ; /* 0x0000000202047220 */
/* 0x000fe20000400000 */
/*0810*/ LOP3.LUT P1, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe2000782c0ff */
/*0820*/ IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff077424 */
/* 0x000fe200078e00ff */
/*0830*/ LOP3.LUT P0, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fe2000780c0ff */
/*0840*/ FFMA.SAT R2, R4, R5, 0.5 ; /* 0x3f00000004027423 */
/* 0x000fc40000002005 */
/*0850*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff087424 */
/* 0x000fe400078e00ff */
/*0860*/ FFMA.RM R6, R2, R7, 12582913 ; /* 0x4b40000102067423 */
/* 0x000fe40000004007 */
/*0870*/ FMUL R11, R10.reuse, R10 ; /* 0x0000000a0a0b7220 */
/* 0x040fe20000400000 */
/*0880*/ FSEL R10, R10, 1, !P1 ; /* 0x3f8000000a0a7808 */
/* 0x000fe20004800000 */
/*0890*/ FADD R5, R6, -12583039 ; /* 0xcb40007f06057421 */
/* 0x000fe40000000000 */
/*08a0*/ @P1 MOV R7, 0x37cbac00 ; /* 0x37cbac0000071802 */
/* 0x000fe20000000f00 */
/*08b0*/ IMAD.MOV.U32 R2, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff027424 */
/* 0x000fe400078e00ff */
/*08c0*/ FFMA R5, R4, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b04057823 */
/* 0x000fc40000000805 */
/*08d0*/ @P1 FFMA R2, R11, R7, -0.0013887860113754868507 ; /* 0xbab607ed0b021423 */
/* 0x000fe40000000007 */
/*08e0*/ FFMA R4, R4, 1.925963033500011079e-08, R5 ; /* 0x32a5706004047823 */
/* 0x000fe20000000005 */
/*08f0*/ FSEL R5, R8, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb08057808 */
/* 0x000fe20004800000 */
/*0900*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff077424 */
/* 0x000fe200078e00ff */
/*0910*/ LOP3.LUT R8, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100087812 */
/* 0x000fc600078ec0ff */
/*0920*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e220000000800 */
/*0930*/ FFMA R2, R11, R2, R5 ; /* 0x000000020b027223 */
/* 0x000fe20000000005 */
/*0940*/ FSEL R5, -R7, -0.4999999701976776123, !P1 ; /* 0xbeffffff07057808 */
/* 0x000fe20004800100 */
/*0950*/ IMAD.SHL.U32 R7, R6, 0x800000, RZ ; /* 0x0080000006077824 */
/* 0x000fe200078e00ff */
/*0960*/ ISETP.NE.U32.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc60003f25070 */
/*0970*/ FFMA R5, R11.reuse, R2, R5 ; /* 0x000000020b057223 */
/* 0x040fe40000000005 */
/*0980*/ FFMA R2, R11, R10, RZ ; /* 0x0000000a0b027223 */
/* 0x000fc800000000ff */
/*0990*/ FFMA R2, R5, R2, R10 ; /* 0x0000000205027223 */
/* 0x000fe4000000000a */
/*09a0*/ FMUL R7, R4, R7 ; /* 0x0000000704077220 */
/* 0x001fe40000400000 */
/*09b0*/ @P0 FFMA R2, R2, -1, RZ ; /* 0xbf80000002020823 */
/* 0x000fe200000000ff */
/*09c0*/ LOP3.LUT P0, RZ, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300ff7812 */
/* 0x000fc6000780c0ff */
/*09d0*/ FMUL R7, R7, R2 ; /* 0x0000000207077220 */
/* 0x000fca0000400000 */
/*09e0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x000fe80000004800 */
/*09f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a00*/ @P1 LDS R2, [R0.X4] ; /* 0x0000000000021984 */
/* 0x000fe80000004800 */
/*0a10*/ @P1 LDS R5, [R0.X4+0x4] ; /* 0x0000040000051984 */
/* 0x000e240000004800 */
/*0a20*/ @P1 FADD R5, R2, R5 ; /* 0x0000000502051221 */
/* 0x001fca0000000000 */
/*0a30*/ @P1 STS [R0.X4], R5 ; /* 0x0000000500001388 */
/* 0x000fe80000004800 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a50*/ LOP3.LUT P1, RZ, R0, 0x7, RZ, 0xc0, !PT ; /* 0x0000000700ff7812 */
/* 0x000fca000782c0ff */
/*0a60*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0a70*/ @!P0 LDS R9, [R0.X4+0x8] ; /* 0x0000080000098984 */
/* 0x000e240000004800 */
/*0a80*/ @!P0 FADD R9, R2, R9 ; /* 0x0000000902098221 */
/* 0x001fca0000000000 */
/*0a90*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x000fe80000004800 */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ab0*/ LOP3.LUT P0, RZ, R0, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f00ff7812 */
/* 0x000fca000780c0ff */
/*0ac0*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*0ad0*/ @!P1 LDS R7, [R0.X4+0x10] ; /* 0x0000100000079984 */
/* 0x000e240000004800 */
/*0ae0*/ @!P1 FADD R7, R2, R7 ; /* 0x0000000702079221 */
/* 0x001fca0000000000 */
/*0af0*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x000fe80000004800 */
/*0b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b10*/ LOP3.LUT P1, RZ, R0, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f00ff7812 */
/* 0x000fca000782c0ff */
/*0b20*/ @!P0 LDS R2, [R0.X4] ; /* 0x0000000000028984 */
/* 0x000fe80000004800 */
/*0b30*/ @!P0 LDS R5, [R0.X4+0x20] ; /* 0x0000200000058984 */
/* 0x000e240000004800 */
/*0b40*/ @!P0 FADD R5, R2, R5 ; /* 0x0000000502058221 */
/* 0x001fca0000000000 */
/*0b50*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x000fe80000004800 */
/*0b60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*0b80*/ @!P1 LDS R2, [R0.X4] ; /* 0x0000000000029984 */
/* 0x000fe80000004800 */
/*0b90*/ @!P1 LDS R9, [R0.X4+0x40] ; /* 0x0000400000099984 */
/* 0x000e240000004800 */
/*0ba0*/ @!P1 FADD R9, R2, R9 ; /* 0x0000000902099221 */
/* 0x001fca0000000000 */
/*0bb0*/ @!P1 STS [R0.X4], R9 ; /* 0x0000000900009388 */
/* 0x0001e80000004800 */
/*0bc0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bd0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0be0*/ LDS R0, [0x80] ; /* 0x00008000ff007984 */
/* 0x001fe20000000800 */
/*0bf0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0c00*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0c10*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0002 */
/*0c20*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x001fca0000000000 */
/*0c30*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101906 */
/*0c40*/ STS [RZ], R5 ; /* 0x00000005ff007388 */
/* 0x000fe20000000800 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9oblicz_fxffPf
.globl _Z9oblicz_fxffPf
.p2align 8
.type _Z9oblicz_fxffPf,@function
_Z9oblicz_fxffPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s5
v_add3_u32 v1, v0, s5, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_fma_f32 v1, v1, s2, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v1|
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v4, 0 :: v_dual_and_b32 v9, 0x7fffffff, v1
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v12, v9, s2, 0x800000
v_lshrrev_b32_e32 v9, 23, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v12, 0xfe5163ab, 0
v_add_nc_u32_e32 v10, 0xffffff88, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v10
v_mad_u64_u32 v[5:6], null, v12, 0x3c439041, v[3:4]
v_cndmask_b32_e64 v11, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v3, v6
v_add_nc_u32_e32 v11, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v12, 0xdb629599, v[3:4]
v_cmp_lt_u32_e64 s2, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, 0, 0xffffffe0, s2
v_dual_mov_b32 v3, v7 :: v_dual_cndmask_b32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, v13, v11
v_mad_u64_u32 v[7:8], null, v12, 0xf534ddc0, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v13
v_mov_b32_e32 v3, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v7, v5, vcc_lo
v_mad_u64_u32 v[8:9], null, v12, 0xfc2757d1, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, v5, v2, s2
v_mov_b32_e32 v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v12, 0x4e441529, v[3:4]
v_mov_b32_e32 v3, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v12, 0xa2f9836e, v[3:4]
v_cndmask_b32_e64 v3, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v4, v9, v7 :: v_dual_add_nc_u32 v3, v3, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v10, v10, v8 :: v_dual_cndmask_b32 v9, v11, v9
v_cndmask_b32_e32 v8, v8, v6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, v10, v4, s2
v_cndmask_b32_e64 v9, v9, v10, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v4, v4, v8, s2
v_sub_nc_u32_e32 v10, 32, v3
v_cndmask_b32_e64 v8, v8, v5, s2
v_cndmask_b32_e64 v9, v9, v7, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v4, s3
v_cndmask_b32_e64 v4, v4, v8, s3
v_cndmask_b32_e64 v2, v8, v2, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v11, v9, v7, v10
v_alignbit_b32 v6, v7, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v3, v11, v9, vcc_lo
v_alignbit_b32 v9, v4, v2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v6, v7, vcc_lo
v_bfe_u32 v6, v3, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v9, v4, vcc_lo
v_alignbit_b32 v7, v3, v5, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v8, 0, v6
v_alignbit_b32 v5, v5, v4, 30
v_alignbit_b32 v2, v4, v2, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v8
v_xor_b32_e32 v4, v5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v8
v_clz_i32_u32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v9, 32, v9
v_sub_nc_u32_e32 v5, 31, v9
v_lshlrev_b32_e32 v11, 23, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v7, v7, v4, v5
v_alignbit_b32 v2, v4, v2, v5
v_lshrrev_b32_e32 v5, 29, v3
v_alignbit_b32 v4, v7, v2, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 31, v5
v_lshrrev_b32_e32 v7, 9, v7
v_clz_i32_u32_e32 v8, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v10, 0.5, v5
v_min_u32_e32 v8, 32, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v10, v11
v_sub_nc_u32_e32 v12, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v2, v4, v2, v12
v_or_b32_e32 v4, v7, v10
v_add_lshl_u32 v7, v8, v9, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v2, 9, v2
v_mul_f32_e32 v8, 0x3fc90fda, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v7
v_fma_f32 v7, v4, 0x3fc90fda, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, 0x33000000, v2
v_fmamk_f32 v4, v4, 0x33a22168, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v2, v2, v5
v_fmac_f32_e32 v4, 0x3fc90fda, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v8, v4
v_lshrrev_b32_e32 v3, 30, v3
v_add_nc_u32_e32 v3, v6, v3
.LBB0_2:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v2, 0x3f22f983, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v3, v2
v_fma_f32 v2, v3, 0xbfc90fda, |v1|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v3, 0xb3a22168, v2
v_fmamk_f32 v2, v3, 0xa7c234c4, v2
v_cvt_i32_f32_e32 v3, v3
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, v2, v2
s_mov_b32 s2, 0xb94c1982
v_mul_f32_e32 v4, v1, v1
s_mov_b32 s3, 0x37d75334
v_fmaak_f32 v9, s2, v6, 0x3c0881c4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v9, v6, v9, 0xbe2aaa9d
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_rndne_f32_e32 v7, v5
v_fma_f32 v8, v4, 0x3fb8aa3b, -v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v5, v5, v7 :: v_dual_fmamk_f32 v8, v4, 0x32a5705f, v8
v_fmaak_f32 v10, s3, v6, 0xbab64f3b
v_cvt_i32_f32_e32 v7, v7
v_dual_add_f32 v5, v5, v8 :: v_dual_mul_f32 v8, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v7
v_fmaak_f32 v10, v6, v10, 0x3d2aabf7
v_dual_fmaak_f32 v9, v6, v10, 0xbf000004 :: v_dual_and_b32 v10, 1, v3
v_dual_fmac_f32 v2, v2, v8 :: v_dual_lshlrev_b32 v3, 30, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v6, v6, v9, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v3, 0x80000000, v3
v_cndmask_b32_e64 v2, -v2, v6, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v3, v2
v_cndmask_b32_e32 v3, 0, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x1f8
v_dual_cndmask_b32 v2, 0x7fc00000, v2 :: v_dual_lshlrev_b32 v1, 2, v0
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, 0x7f800000, v3 :: v_dual_and_b32 v4, 1, v0
v_mul_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_6
ds_load_2addr_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 3, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:8
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 7, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:16
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 15, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_12
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:32
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
v_and_b32_e32 v2, 31, v0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_14
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v2, v2 offset:64
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_16
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s5, 0
ds_load_b32 v2, v1
ds_load_b32 v3, v0 offset:128
s_lshl_b64 s[2:3], s[4:5], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
global_store_b32 v0, v2, s[0:1]
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9oblicz_fxffPf
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9oblicz_fxffPf, .Lfunc_end0-_Z9oblicz_fxffPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9oblicz_fxffPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9oblicz_fxffPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010bd7f_00000000-6_071_calka_redukcja.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movaps %xmm0, %xmm1
movss %xmm0, 12(%rsp)
mulss %xmm0, %xmm1
movaps %xmm1, %xmm0
call expf@PLT
movss %xmm0, 8(%rsp)
movss 12(%rsp), %xmm0
call cosf@PLT
mulss 8(%rsp), %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z1ff, .-_Z1ff
.globl _Z30__device_stub__Z9oblicz_fxffPfffPf
.type _Z30__device_stub__Z9oblicz_fxffPfffPf, @function
_Z30__device_stub__Z9oblicz_fxffPfffPf:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %rdi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9oblicz_fxffPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9oblicz_fxffPfffPf, .-_Z30__device_stub__Z9oblicz_fxffPfffPf
.globl _Z9oblicz_fxffPf
.type _Z9oblicz_fxffPf, @function
_Z9oblicz_fxffPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9oblicz_fxffPfffPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9oblicz_fxffPf, .-_Z9oblicz_fxffPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "calka=%f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $16384, %edi
call malloc@PLT
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movl $16384, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
call _Z1ff
movss %xmm0, 12(%rsp)
movss .LC2(%rip), %xmm0
call _Z1ff
addss 12(%rsp), %xmm0
mulss .LC3(%rip), %xmm0
movq %rbx, %rax
leaq 16384(%rbx), %rdx
.L15:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L15
mulss .LC1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdi
pxor %xmm1, %xmm1
movss .LC1(%rip), %xmm0
call _Z30__device_stub__Z9oblicz_fxffPfffPf
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z9oblicz_fxffPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9oblicz_fxffPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 914358208
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "071_calka_redukcja.hip"
.globl _Z1ff # -- Begin function _Z1ff
.p2align 4, 0x90
.type _Z1ff,@function
_Z1ff: # @_Z1ff
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 12(%rsp) # 4-byte Spill
movaps %xmm0, %xmm1
mulss %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
callq exp
movsd %xmm0, 16(%rsp) # 8-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
callq cos
mulsd 16(%rsp), %xmm0 # 8-byte Folded Reload
cvtsd2ss %xmm0, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z1ff, .Lfunc_end0-_Z1ff
.cfi_endproc
# -- End function
.globl _Z24__device_stub__oblicz_fxffPf # -- Begin function _Z24__device_stub__oblicz_fxffPf
.p2align 4, 0x90
.type _Z24__device_stub__oblicz_fxffPf,@function
_Z24__device_stub__oblicz_fxffPf: # @_Z24__device_stub__oblicz_fxffPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movss %xmm1, (%rsp)
movq %rdi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9oblicz_fxffPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__oblicz_fxffPf, .Lfunc_end1-_Z24__device_stub__oblicz_fxffPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f9dff15 # float 1.23434699
.LCPI2_1:
.long 0x367fffc0 # float 3.81468271E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
movabsq $4294967360, %rdx # imm = 0x100000040
leaq 4032(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movl $914358208, 20(%rsp) # imm = 0x367FFFC0
movl $0, 16(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9oblicz_fxffPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $4096, %rax # imm = 0x1000
jne .LBB2_3
# %bb.4:
mulss .LCPI2_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9oblicz_fxffPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9oblicz_fxffPf,@object # @_Z9oblicz_fxffPf
.section .rodata,"a",@progbits
.globl _Z9oblicz_fxffPf
.p2align 3, 0x0
_Z9oblicz_fxffPf:
.quad _Z24__device_stub__oblicz_fxffPf
.size _Z9oblicz_fxffPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "calka=%f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9oblicz_fxffPf"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__oblicz_fxffPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9oblicz_fxffPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Solve-2 by SnipGhost 22.03.2017
*/
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 8
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ float f(const int x, const int y, const int t)
{
if (t > 256) return 0;
if (x == 0 && y == 0) return 5000;
if (x*x+y*y <= 10) return 4000;
else return 0;
}
__global__ void kernel_simulate(const float *z, float *b, const int t,
const int xsize, const int ysize,
const float Hx, const float Hy, const float Ht)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
unsigned idl = idy * xsize + idx;
float top = 0, bottom = 0, left = 0, right = 0;
if (idx+1 < xsize) right = z[idl+1];
if (idx-1 >= 0) left = z[idl-1];
if (idy+1 < ysize) bottom = z[idl+xsize];
if (idy-1 >= 0) top = z[idl-xsize];
float dx = (right - 2*z[idl] + left) / (Hx * Hx);
float dy = (bottom - 2*z[idl] + top) / (Hy * Hy);
b[idl] += (5*(dx+dy) + f(idx-xsize/2, idy-ysize/2, t)) * Ht;
}
void initialize(float *d, int size, float init = 0)
{
for (int i = 0; i < size; ++i)
d[i] = init;
}
void save_data(FILE *file, float *d, int xsize, int ysize, int t)
{
if (!file)
printf("File output error\n");
else
for (int i = 0; i < xsize*ysize; ++i)
fprintf(file, "%4d %4d %20.14f %4d\n", i/xsize, i%xsize, d[i], t);
}
int main(void)
{
const float Hx = 1;
const float Hy = 1;
const float Ht = 0.05;
const int XNODES = 64;
const int YNODES = 64;
const int TICKS = 800;
const int numBytes = sizeof(float) * XNODES * YNODES;
FILE *file = fopen("out","w");
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(XNODES/BLOCK_SIZE, YNODES/BLOCK_SIZE);
float *data_dev, *buff_dev, *data_host;
data_host = (float*)malloc(numBytes);
initialize(data_host, XNODES*YNODES);
CUDA_CHECK_RETURN(cudaMalloc((void**)&data_dev, numBytes));
CUDA_CHECK_RETURN(cudaMalloc((void**)&buff_dev, numBytes));
CUDA_CHECK_RETURN(cudaMemcpy(data_dev, data_host, numBytes, cudaMemcpyHostToDevice));
for (int t = 0; t < TICKS; ++t)
{
kernel_simulate <<< blocks, threads >>> (data_dev, buff_dev, t, XNODES, YNODES, Hx, Hy, Ht);
CUDA_CHECK_RETURN(cudaGetLastError());
CUDA_CHECK_RETURN(cudaMemcpy(data_dev, buff_dev, numBytes, cudaMemcpyDeviceToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(data_host, buff_dev, numBytes, cudaMemcpyDeviceToHost));
save_data(file, data_host, XNODES, YNODES, t);
}
CUDA_CHECK_RETURN(cudaFree((void*)data_dev));
CUDA_CHECK_RETURN(cudaFree((void*)buff_dev));
CUDA_CHECK_RETURN(cudaDeviceReset());
free(data_host);
fclose(file);
return 0;
} | code for sm_80
Function : _Z15kernel_simulatePKfPfiiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0040*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*00b0*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f26270 */
/*00c0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*00d0*/ IMAD R2, R3, c[0x0][0x174], R0 ; /* 0x00005d0003027a24 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE.U32 R10, R2.reuse, R17.reuse, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x0c0fe400078e0011 */
/*00f0*/ @P0 IADD3 R8, R2.reuse, -0x1, RZ ; /* 0xffffffff02080810 */
/* 0x040fe40007ffe0ff */
/*0100*/ @!P1 IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102069810 */
/* 0x000fe20007ffe0ff */
/*0110*/ LDG.E R16, [R10.64] ; /* 0x0000000a0a107981 */
/* 0x0000a8000c1e1900 */
/*0120*/ @!P1 IMAD.WIDE.U32 R6, R6, R17, c[0x0][0x160] ; /* 0x0000580006069625 */
/* 0x000fc800078e0011 */
/*0130*/ @P0 IMAD.WIDE.U32 R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008080625 */
/* 0x000fe200078e0011 */
/*0140*/ @!P1 LDG.E R13, [R6.64] ; /* 0x0000000a060d9981 */
/* 0x0002e2000c1e1900 */
/*0150*/ ISETP.GE.AND P2, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc60003f46270 */
/*0160*/ @P0 LDG.E R12, [R8.64] ; /* 0x0000000a080c0981 */
/* 0x0008e2000c1e1900 */
/*0170*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fc80007ffe0ff */
/*0180*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fca0003f26270 */
/*0190*/ @P2 IADD3 R15, R2, -c[0x0][0x174], RZ ; /* 0x80005d00020f2a10 */
/* 0x000fe20007ffe0ff */
/*01a0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc8000001ff00 */
/*01b0*/ @P2 IMAD.WIDE.U32 R10, R15, R17, c[0x0][0x160] ; /* 0x000058000f0a2625 */
/* 0x001fca00078e0011 */
/*01c0*/ @P2 LDG.E R4, [R10.64] ; /* 0x0000000a0a042981 */
/* 0x000162000c1e1900 */
/*01d0*/ @!P1 IADD3 R14, R2, c[0x0][0x174], RZ ; /* 0x00005d00020e9a10 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P1 IMAD.WIDE.U32 R6, R14, R17, c[0x0][0x160] ; /* 0x000058000e069625 */
/* 0x002fc800078e0011 */
/*01f0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0e7624 */
/* 0x000fe200078e00ff */
/*0200*/ @!P1 LDG.E R5, [R6.64] ; /* 0x0000000a06059981 */
/* 0x000366000c1e1900 */
/*0210*/ FMUL R14, R14, c[0x0][0x17c] ; /* 0x00005f000e0e7a20 */
/* 0x000fc80000400000 */
/*0220*/ MUFU.RCP R9, R14 ; /* 0x0000000e00097308 */
/* 0x010f220000001000 */
/*0230*/ BSSY B0, 0x320 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0240*/ FADD R8, R16, R16 ; /* 0x0000001010087221 */
/* 0x004fc80000000000 */
/*0250*/ FADD R13, -R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fc80000000100 */
/*0260*/ FADD R13, R13, R12 ; /* 0x0000000c0d0d7221 */
/* 0x000fe40000000000 */
/*0270*/ FFMA R16, -R14, R9, 1 ; /* 0x3f8000000e107423 */
/* 0x010fe40000000109 */
/*0280*/ FCHK P0, R13, R14 ; /* 0x0000000e0d007302 */
/* 0x000ea40000000000 */
/*0290*/ FFMA R16, R9, R16, R9 ; /* 0x0000001009107223 */
/* 0x000fc80000000009 */
/*02a0*/ FFMA R9, R13, R16, RZ ; /* 0x000000100d097223 */
/* 0x000fc800000000ff */
/*02b0*/ FFMA R6, -R14, R9, R13 ; /* 0x000000090e067223 */
/* 0x002fc8000000010d */
/*02c0*/ FFMA R6, R16, R6, R9 ; /* 0x0000000610067223 */
/* 0x000fe20000000009 */
/*02d0*/ @!P0 BRA 0x310 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*02e0*/ MOV R10, 0x300 ; /* 0x00000300000a7802 */
/* 0x001fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x610 ; /* 0x0000031000007944 */
/* 0x020fea0003c00000 */
/*0300*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0007 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff077624 */
/* 0x000fe200078e00ff */
/*0330*/ BSSY B0, 0x440 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0340*/ FADD R5, -R8, R5 ; /* 0x0000000508057221 */
/* 0x020fe40000000100 */
/*0350*/ FMUL R7, R7, c[0x0][0x180] ; /* 0x0000600007077a20 */
/* 0x000fe40000400000 */
/*0360*/ FADD R13, R5, R4 ; /* 0x00000004050d7221 */
/* 0x000fe40000000000 */
/*0370*/ MUFU.RCP R10, R7 ; /* 0x00000007000a7308 */
/* 0x000e300000001000 */
/*0380*/ FCHK P0, R13, R7 ; /* 0x000000070d007302 */
/* 0x000e620000000000 */
/*0390*/ FFMA R9, -R7, R10, 1 ; /* 0x3f80000007097423 */
/* 0x001fc8000000010a */
/*03a0*/ FFMA R9, R10, R9, R10 ; /* 0x000000090a097223 */
/* 0x000fc8000000000a */
/*03b0*/ FFMA R4, R13, R9, RZ ; /* 0x000000090d047223 */
/* 0x000fc800000000ff */
/*03c0*/ FFMA R5, -R7, R4, R13 ; /* 0x0000000407057223 */
/* 0x000fc8000000010d */
/*03d0*/ FFMA R9, R9, R5, R4 ; /* 0x0000000509097223 */
/* 0x000fe20000000004 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0007 */
/*0400*/ MOV R10, 0x420 ; /* 0x00000420000a7802 */
/* 0x000fe40000000f00 */
/*0410*/ CALL.REL.NOINC 0x610 ; /* 0x000001f000007944 */
/* 0x000fea0003c00000 */
/*0420*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0450*/ LEA.HI.X R5, R2, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f14ff */
/*0460*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000162000c1e1900 */
/*0470*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0480*/ UMOV UR8, 0x2 ; /* 0x0000000200087882 */
/* 0x000fe20000000000 */
/*0490*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x000fe20000000000 */
/*04a0*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*04b0*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe20000000800 */
/*04c0*/ ISETP.GT.AND P0, PT, R2, 0x100, PT ; /* 0x000001000200780c */
/* 0x000fe20003f04270 */
/*04d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*04e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*04f0*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fc40008000000 */
/*0500*/ UIMAD.WIDE.U32 UR4, UR8, UR5, UR4 ; /* 0x00000005080472a5 */
/* 0x000fe4000f8e0004 */
/*0510*/ UIMAD.WIDE.U32 UR6, UR8, UR7, UR6 ; /* 0x00000007080672a5 */
/* 0x000fe4000f8e0006 */
/*0520*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011405 */
/*0530*/ USHF.R.S32.HI UR7, URZ, 0x1, UR7 ; /* 0x000000013f077899 */
/* 0x000fc80008011407 */
/*0540*/ IADD3 R0, R0, -UR5, RZ ; /* 0x8000000500007c10 */
/* 0x000fe4000fffe0ff */
/*0550*/ IADD3 R3, R3, -UR7, RZ ; /* 0x8000000703037c10 */
/* 0x000fe2000fffe0ff */
/*0560*/ @P0 BRA 0x5d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT P0, RZ, R3, R0, RZ, 0xfc, !PT ; /* 0x0000000003ff7212 */
/* 0x001fe2000780fcff */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, 0x459c4000 ; /* 0x459c4000ff027424 */
/* 0x000fd800078e00ff */
/*0590*/ @P0 IMAD R0, R0, R0, RZ ; /* 0x0000000000000224 */
/* 0x000fc800078e02ff */
/*05a0*/ @P0 IMAD R0, R3, R3, R0 ; /* 0x0000000303000224 */
/* 0x000fca00078e0200 */
/*05b0*/ @P0 ISETP.GE.U32.AND P1, PT, R0, 0xb, PT ; /* 0x0000000b0000080c */
/* 0x000fc80003f26070 */
/*05c0*/ @P0 FSEL R2, RZ, 4000, P1 ; /* 0x457a0000ff020808 */
/* 0x000fca0000800000 */
/*05d0*/ FFMA R2, R9, 5, R2 ; /* 0x40a0000009027823 */
/* 0x001fc80000000002 */
/*05e0*/ FFMA R7, R2, c[0x0][0x184], R7 ; /* 0x0000610002077a23 */
/* 0x020fca0000000007 */
/*05f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c10190a */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ SHF.R.U32.HI R11, RZ, 0x17, R14.reuse ; /* 0x00000017ff0b7819 */
/* 0x100fe2000001160e */
/*0620*/ BSSY B1, 0xc70 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0630*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0640*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000e */
/*0650*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0660*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe200078ec0ff */
/*0670*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0680*/ IADD3 R17, R11, -0x1, RZ ; /* 0xffffffff0b117810 */
/* 0x000fe40007ffe0ff */
/*0690*/ IADD3 R16, R15, -0x1, RZ ; /* 0xffffffff0f107810 */
/* 0x000fc40007ffe0ff */
/*06a0*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fc80003f04070 */
/*06b0*/ ISETP.GT.U32.OR P0, PT, R16, 0xfd, P0 ; /* 0x000000fd1000780c */
/* 0x000fda0000704470 */
/*06c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*06d0*/ @!P0 BRA 0x850 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*06e0*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*06f0*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fc80003f3c200 */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0710*/ @P0 BRA 0xc50 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0720*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c807 */
/*0730*/ @!P0 BRA 0xc30 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.NEU.FTZ.AND P2, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f5d200 */
/*0750*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3d200 */
/*0760*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0770*/ @!P1 BRA !P2, 0xc30 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0780*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0790*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07a0*/ @P1 BRA 0xc10 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*07c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*07d0*/ @P0 BRA 0xbe0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f06270 */
/*07f0*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0800*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0810*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0820*/ @!P0 FFMA R7, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d078823 */
/* 0x000fe400000000ff */
/*0830*/ @!P1 FFMA R12, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0c9823 */
/* 0x000fe200000000ff */
/*0840*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0850*/ LEA R13, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0d7811 */
/* 0x000fe200078eb8ff */
/*0860*/ BSSY B2, 0xbd0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0870*/ IMAD.IADD R13, R12, 0x1, -R13 ; /* 0x000000010c0d7824 */
/* 0x000fe200078e0a0d */
/*0880*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*0890*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x000e220000001000 */
/*08a0*/ FADD.FTZ R16, -R13, -RZ ; /* 0x800000ff0d107221 */
/* 0x000fe40000010100 */
/*08b0*/ IMAD R7, R12.reuse, -0x800000, R7 ; /* 0xff8000000c077824 */
/* 0x040fe200078e0207 */
/*08c0*/ IADD3 R12, R12, 0x7f, -R11 ; /* 0x0000007f0c0c7810 */
/* 0x000fca0007ffe80b */
/*08d0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0209 */
/*08e0*/ FFMA R15, R14, R16, 1 ; /* 0x3f8000000e0f7423 */
/* 0x001fc80000000010 */
/*08f0*/ FFMA R18, R14, R15, R14 ; /* 0x0000000f0e127223 */
/* 0x000fc8000000000e */
/*0900*/ FFMA R14, R7, R18, RZ ; /* 0x00000012070e7223 */
/* 0x000fc800000000ff */
/*0910*/ FFMA R15, R16, R14, R7 ; /* 0x0000000e100f7223 */
/* 0x000fc80000000007 */
/*0920*/ FFMA R15, R18, R15, R14 ; /* 0x0000000f120f7223 */
/* 0x000fc8000000000e */
/*0930*/ FFMA R16, R16, R15, R7 ; /* 0x0000000f10107223 */
/* 0x000fc80000000007 */
/*0940*/ FFMA R7, R18, R16, R15 ; /* 0x0000001012077223 */
/* 0x000fca000000000f */
/*0950*/ SHF.R.U32.HI R11, RZ, 0x17, R7 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011607 */
/*0960*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*0970*/ IMAD.IADD R13, R11, 0x1, R12 ; /* 0x000000010b0d7824 */
/* 0x000fca00078e020c */
/*0980*/ IADD3 R9, R13, -0x1, RZ ; /* 0xffffffff0d097810 */
/* 0x000fc80007ffe0ff */
/*0990*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*09a0*/ @!P0 BRA 0xbb0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*09c0*/ @P0 BRA 0xb80 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*09e0*/ @P0 BRA 0xbc0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a00*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0a10*/ @!P0 BRA 0xbc0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a20*/ FFMA.RZ R9, R18.reuse, R16.reuse, R15.reuse ; /* 0x0000001012097223 */
/* 0x1c0fe2000000c00f */
/*0a30*/ IADD3 R14, R13.reuse, 0x20, RZ ; /* 0x000000200d0e7810 */
/* 0x040fe20007ffe0ff */
/*0a40*/ FFMA.RM R12, R18.reuse, R16.reuse, R15.reuse ; /* 0x00000010120c7223 */
/* 0x1c0fe2000000400f */
/*0a50*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0a60*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*0a70*/ FFMA.RP R9, R18, R16, R15 ; /* 0x0000001012097223 */
/* 0x000fe2000000800f */
/*0a80*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0a90*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0d */
/*0aa0*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0ab0*/ FSETP.NEU.FTZ.AND P0, PT, R9, R12, PT ; /* 0x0000000c0900720b */
/* 0x000fc40003f1d000 */
/*0ac0*/ SHF.L.U32 R14, R11, R14, RZ ; /* 0x0000000e0b0e7219 */
/* 0x000fe400000006ff */
/*0ad0*/ SEL R12, R13, RZ, P2 ; /* 0x000000ff0d0c7207 */
/* 0x000fe40001000000 */
/*0ae0*/ ISETP.NE.AND P1, PT, R14, RZ, P1 ; /* 0x000000ff0e00720c */
/* 0x000fe40000f25270 */
/*0af0*/ SHF.R.U32.HI R12, RZ, R12, R11 ; /* 0x0000000cff0c7219 */
/* 0x000fe4000001160b */
/*0b00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b10*/ SHF.R.U32.HI R14, RZ, 0x1, R12 ; /* 0x00000001ff0e7819 */
/* 0x000fc4000001160c */
/*0b20*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0b30*/ LOP3.LUT R9, R9, 0x1, R14, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80e */
/*0b40*/ LOP3.LUT R9, R9, R12, RZ, 0xc0, !PT ; /* 0x0000000c09097212 */
/* 0x000fca00078ec0ff */
/*0b50*/ IMAD.IADD R14, R14, 0x1, R9 ; /* 0x000000010e0e7824 */
/* 0x000fca00078e0209 */
/*0b60*/ LOP3.LUT R7, R14, R7, RZ, 0xfc, !PT ; /* 0x000000070e077212 */
/* 0x000fe200078efcff */
/*0b70*/ BRA 0xbc0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b80*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0b90*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0bc0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xc60 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fc800078e4807 */
/*0bf0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fe200078e4807 */
/*0c20*/ BRA 0xc60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c30*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0c40*/ BRA 0xc60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c50*/ FADD.FTZ R7, R13, R14 ; /* 0x0000000e0d077221 */
/* 0x000fe40000010000 */
/*0c60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0c80*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff3700a007950 */
/* 0x000fea0003c3ffff */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Solve-2 by SnipGhost 22.03.2017
*/
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 8
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ float f(const int x, const int y, const int t)
{
if (t > 256) return 0;
if (x == 0 && y == 0) return 5000;
if (x*x+y*y <= 10) return 4000;
else return 0;
}
__global__ void kernel_simulate(const float *z, float *b, const int t,
const int xsize, const int ysize,
const float Hx, const float Hy, const float Ht)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
unsigned idl = idy * xsize + idx;
float top = 0, bottom = 0, left = 0, right = 0;
if (idx+1 < xsize) right = z[idl+1];
if (idx-1 >= 0) left = z[idl-1];
if (idy+1 < ysize) bottom = z[idl+xsize];
if (idy-1 >= 0) top = z[idl-xsize];
float dx = (right - 2*z[idl] + left) / (Hx * Hx);
float dy = (bottom - 2*z[idl] + top) / (Hy * Hy);
b[idl] += (5*(dx+dy) + f(idx-xsize/2, idy-ysize/2, t)) * Ht;
}
void initialize(float *d, int size, float init = 0)
{
for (int i = 0; i < size; ++i)
d[i] = init;
}
void save_data(FILE *file, float *d, int xsize, int ysize, int t)
{
if (!file)
printf("File output error\n");
else
for (int i = 0; i < xsize*ysize; ++i)
fprintf(file, "%4d %4d %20.14f %4d\n", i/xsize, i%xsize, d[i], t);
}
int main(void)
{
const float Hx = 1;
const float Hy = 1;
const float Ht = 0.05;
const int XNODES = 64;
const int YNODES = 64;
const int TICKS = 800;
const int numBytes = sizeof(float) * XNODES * YNODES;
FILE *file = fopen("out","w");
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(XNODES/BLOCK_SIZE, YNODES/BLOCK_SIZE);
float *data_dev, *buff_dev, *data_host;
data_host = (float*)malloc(numBytes);
initialize(data_host, XNODES*YNODES);
CUDA_CHECK_RETURN(cudaMalloc((void**)&data_dev, numBytes));
CUDA_CHECK_RETURN(cudaMalloc((void**)&buff_dev, numBytes));
CUDA_CHECK_RETURN(cudaMemcpy(data_dev, data_host, numBytes, cudaMemcpyHostToDevice));
for (int t = 0; t < TICKS; ++t)
{
kernel_simulate <<< blocks, threads >>> (data_dev, buff_dev, t, XNODES, YNODES, Hx, Hy, Ht);
CUDA_CHECK_RETURN(cudaGetLastError());
CUDA_CHECK_RETURN(cudaMemcpy(data_dev, buff_dev, numBytes, cudaMemcpyDeviceToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(data_host, buff_dev, numBytes, cudaMemcpyDeviceToHost));
save_data(file, data_host, XNODES, YNODES, t);
}
CUDA_CHECK_RETURN(cudaFree((void*)data_dev));
CUDA_CHECK_RETURN(cudaFree((void*)buff_dev));
CUDA_CHECK_RETURN(cudaDeviceReset());
free(data_host);
fclose(file);
return 0;
} | .file "tmpxft_0003df6e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fiii
.type _Z1fiii, @function
_Z1fiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1fiii, .-_Z1fiii
.globl _Z10initializePfif
.type _Z10initializePfif, @function
_Z10initializePfif:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L5
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L7:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z10initializePfif, .-_Z10initializePfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "File output error\n"
.LC1:
.string "%4d %4d %20.14f %4d\n"
.text
.globl _Z9save_dataP8_IO_FILEPfiii
.type _Z9save_dataP8_IO_FILEPfiii, @function
_Z9save_dataP8_IO_FILEPfiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %r8d, 12(%rsp)
testq %rdi, %rdi
je .L10
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebp
imull %edx, %ecx
movslq %ecx, %r15
movl $0, %ebx
leaq .LC1(%rip), %r14
testl %ecx, %ecx
jle .L9
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movl %ebx, %eax
cltd
idivl %ebp
movl %edx, %r8d
movl %eax, %ecx
movl 12(%rsp), %r9d
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %r15, %rbx
jne .L13
.L9:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2059:
.size _Z9save_dataP8_IO_FILEPfiii, .-_Z9save_dataP8_IO_FILEPfiii
.globl _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
.type _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff, @function
_Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kernel_simulatePKfPfiiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff, .-_Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
.globl _Z15kernel_simulatePKfPfiiifff
.type _Z15kernel_simulatePKfPfiiifff, @function
_Z15kernel_simulatePKfPfiiifff:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15kernel_simulatePKfPfiiifff, .-_Z15kernel_simulatePKfPfiiifff
.section .rodata.str1.1
.LC2:
.string "w"
.LC3:
.string "out"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SnipGhost/cuda-tech-park/master/SZ2/main.cu"
.align 8
.LC6:
.string "Error %s at line %d in file %s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $8, 16(%rsp)
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 28(%rsp)
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
pxor %xmm0, %xmm0
movl $4096, %esi
movq %rax, %rdi
call _Z10initializePfif
movq %rsp, %rdi
movl $16384, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 8(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
movl $0, %ebx
jmp .L28
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $81, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $82, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $83, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L43
movl $3, %ecx
movl $16384, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
movl $2, %ecx
movl $16384, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L45
movl %ebx, %r8d
movl $64, %ecx
movl $64, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9save_dataP8_IO_FILEPfiii
addl $1, %ebx
cmpl $800, %ebx
je .L46
.L28:
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movss .LC7(%rip), %xmm2
movss .LC8(%rip), %xmm1
movaps %xmm1, %xmm0
movl $64, %r8d
movl $64, %ecx
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
jmp .L29
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $88, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $89, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $90, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L47
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L48
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L49
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $94, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $95, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $96, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z15kernel_simulatePKfPfiiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_simulatePKfPfiiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1028443341
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Solve-2 by SnipGhost 22.03.2017
*/
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 8
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ float f(const int x, const int y, const int t)
{
if (t > 256) return 0;
if (x == 0 && y == 0) return 5000;
if (x*x+y*y <= 10) return 4000;
else return 0;
}
__global__ void kernel_simulate(const float *z, float *b, const int t,
const int xsize, const int ysize,
const float Hx, const float Hy, const float Ht)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
unsigned idl = idy * xsize + idx;
float top = 0, bottom = 0, left = 0, right = 0;
if (idx+1 < xsize) right = z[idl+1];
if (idx-1 >= 0) left = z[idl-1];
if (idy+1 < ysize) bottom = z[idl+xsize];
if (idy-1 >= 0) top = z[idl-xsize];
float dx = (right - 2*z[idl] + left) / (Hx * Hx);
float dy = (bottom - 2*z[idl] + top) / (Hy * Hy);
b[idl] += (5*(dx+dy) + f(idx-xsize/2, idy-ysize/2, t)) * Ht;
}
void initialize(float *d, int size, float init = 0)
{
for (int i = 0; i < size; ++i)
d[i] = init;
}
void save_data(FILE *file, float *d, int xsize, int ysize, int t)
{
if (!file)
printf("File output error\n");
else
for (int i = 0; i < xsize*ysize; ++i)
fprintf(file, "%4d %4d %20.14f %4d\n", i/xsize, i%xsize, d[i], t);
}
int main(void)
{
const float Hx = 1;
const float Hy = 1;
const float Ht = 0.05;
const int XNODES = 64;
const int YNODES = 64;
const int TICKS = 800;
const int numBytes = sizeof(float) * XNODES * YNODES;
FILE *file = fopen("out","w");
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(XNODES/BLOCK_SIZE, YNODES/BLOCK_SIZE);
float *data_dev, *buff_dev, *data_host;
data_host = (float*)malloc(numBytes);
initialize(data_host, XNODES*YNODES);
CUDA_CHECK_RETURN(cudaMalloc((void**)&data_dev, numBytes));
CUDA_CHECK_RETURN(cudaMalloc((void**)&buff_dev, numBytes));
CUDA_CHECK_RETURN(cudaMemcpy(data_dev, data_host, numBytes, cudaMemcpyHostToDevice));
for (int t = 0; t < TICKS; ++t)
{
kernel_simulate <<< blocks, threads >>> (data_dev, buff_dev, t, XNODES, YNODES, Hx, Hy, Ht);
CUDA_CHECK_RETURN(cudaGetLastError());
CUDA_CHECK_RETURN(cudaMemcpy(data_dev, buff_dev, numBytes, cudaMemcpyDeviceToDevice));
CUDA_CHECK_RETURN(cudaMemcpy(data_host, buff_dev, numBytes, cudaMemcpyDeviceToHost));
save_data(file, data_host, XNODES, YNODES, t);
}
CUDA_CHECK_RETURN(cudaFree((void*)data_dev));
CUDA_CHECK_RETURN(cudaFree((void*)buff_dev));
CUDA_CHECK_RETURN(cudaDeviceReset());
free(data_host);
fclose(file);
return 0;
} | /*
* Solve-2 by SnipGhost 22.03.2017
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 8
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ float f(const int x, const int y, const int t)
{
if (t > 256) return 0;
if (x == 0 && y == 0) return 5000;
if (x*x+y*y <= 10) return 4000;
else return 0;
}
__global__ void kernel_simulate(const float *z, float *b, const int t,
const int xsize, const int ysize,
const float Hx, const float Hy, const float Ht)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
unsigned idl = idy * xsize + idx;
float top = 0, bottom = 0, left = 0, right = 0;
if (idx+1 < xsize) right = z[idl+1];
if (idx-1 >= 0) left = z[idl-1];
if (idy+1 < ysize) bottom = z[idl+xsize];
if (idy-1 >= 0) top = z[idl-xsize];
float dx = (right - 2*z[idl] + left) / (Hx * Hx);
float dy = (bottom - 2*z[idl] + top) / (Hy * Hy);
b[idl] += (5*(dx+dy) + f(idx-xsize/2, idy-ysize/2, t)) * Ht;
}
void initialize(float *d, int size, float init = 0)
{
for (int i = 0; i < size; ++i)
d[i] = init;
}
void save_data(FILE *file, float *d, int xsize, int ysize, int t)
{
if (!file)
printf("File output error\n");
else
for (int i = 0; i < xsize*ysize; ++i)
fprintf(file, "%4d %4d %20.14f %4d\n", i/xsize, i%xsize, d[i], t);
}
int main(void)
{
const float Hx = 1;
const float Hy = 1;
const float Ht = 0.05;
const int XNODES = 64;
const int YNODES = 64;
const int TICKS = 800;
const int numBytes = sizeof(float) * XNODES * YNODES;
FILE *file = fopen("out","w");
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(XNODES/BLOCK_SIZE, YNODES/BLOCK_SIZE);
float *data_dev, *buff_dev, *data_host;
data_host = (float*)malloc(numBytes);
initialize(data_host, XNODES*YNODES);
CUDA_CHECK_RETURN(hipMalloc((void**)&data_dev, numBytes));
CUDA_CHECK_RETURN(hipMalloc((void**)&buff_dev, numBytes));
CUDA_CHECK_RETURN(hipMemcpy(data_dev, data_host, numBytes, hipMemcpyHostToDevice));
for (int t = 0; t < TICKS; ++t)
{
kernel_simulate <<< blocks, threads >>> (data_dev, buff_dev, t, XNODES, YNODES, Hx, Hy, Ht);
CUDA_CHECK_RETURN(hipGetLastError());
CUDA_CHECK_RETURN(hipMemcpy(data_dev, buff_dev, numBytes, hipMemcpyDeviceToDevice));
CUDA_CHECK_RETURN(hipMemcpy(data_host, buff_dev, numBytes, hipMemcpyDeviceToHost));
save_data(file, data_host, XNODES, YNODES, t);
}
CUDA_CHECK_RETURN(hipFree((void*)data_dev));
CUDA_CHECK_RETURN(hipFree((void*)buff_dev));
CUDA_CHECK_RETURN(hipDeviceReset());
free(data_host);
fclose(file);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Solve-2 by SnipGhost 22.03.2017
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 8
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ float f(const int x, const int y, const int t)
{
if (t > 256) return 0;
if (x == 0 && y == 0) return 5000;
if (x*x+y*y <= 10) return 4000;
else return 0;
}
__global__ void kernel_simulate(const float *z, float *b, const int t,
const int xsize, const int ysize,
const float Hx, const float Hy, const float Ht)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
unsigned idl = idy * xsize + idx;
float top = 0, bottom = 0, left = 0, right = 0;
if (idx+1 < xsize) right = z[idl+1];
if (idx-1 >= 0) left = z[idl-1];
if (idy+1 < ysize) bottom = z[idl+xsize];
if (idy-1 >= 0) top = z[idl-xsize];
float dx = (right - 2*z[idl] + left) / (Hx * Hx);
float dy = (bottom - 2*z[idl] + top) / (Hy * Hy);
b[idl] += (5*(dx+dy) + f(idx-xsize/2, idy-ysize/2, t)) * Ht;
}
void initialize(float *d, int size, float init = 0)
{
for (int i = 0; i < size; ++i)
d[i] = init;
}
void save_data(FILE *file, float *d, int xsize, int ysize, int t)
{
if (!file)
printf("File output error\n");
else
for (int i = 0; i < xsize*ysize; ++i)
fprintf(file, "%4d %4d %20.14f %4d\n", i/xsize, i%xsize, d[i], t);
}
int main(void)
{
const float Hx = 1;
const float Hy = 1;
const float Ht = 0.05;
const int XNODES = 64;
const int YNODES = 64;
const int TICKS = 800;
const int numBytes = sizeof(float) * XNODES * YNODES;
FILE *file = fopen("out","w");
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(XNODES/BLOCK_SIZE, YNODES/BLOCK_SIZE);
float *data_dev, *buff_dev, *data_host;
data_host = (float*)malloc(numBytes);
initialize(data_host, XNODES*YNODES);
CUDA_CHECK_RETURN(hipMalloc((void**)&data_dev, numBytes));
CUDA_CHECK_RETURN(hipMalloc((void**)&buff_dev, numBytes));
CUDA_CHECK_RETURN(hipMemcpy(data_dev, data_host, numBytes, hipMemcpyHostToDevice));
for (int t = 0; t < TICKS; ++t)
{
kernel_simulate <<< blocks, threads >>> (data_dev, buff_dev, t, XNODES, YNODES, Hx, Hy, Ht);
CUDA_CHECK_RETURN(hipGetLastError());
CUDA_CHECK_RETURN(hipMemcpy(data_dev, buff_dev, numBytes, hipMemcpyDeviceToDevice));
CUDA_CHECK_RETURN(hipMemcpy(data_host, buff_dev, numBytes, hipMemcpyDeviceToHost));
save_data(file, data_host, XNODES, YNODES, t);
}
CUDA_CHECK_RETURN(hipFree((void*)data_dev));
CUDA_CHECK_RETURN(hipFree((void*)buff_dev));
CUDA_CHECK_RETURN(hipDeviceReset());
free(data_host);
fclose(file);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kernel_simulatePKfPfiiifff
.globl _Z15kernel_simulatePKfPfiiifff
.p2align 8
.type _Z15kernel_simulatePKfPfiiifff,@function
_Z15kernel_simulatePKfPfiiifff:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x14
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_lshr_b32 s5, s5, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v2
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s4, v4
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, 1, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v7, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB0_4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, -1, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v6, v[4:5], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_load_b32 s5, s[0:1], 0x18
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v1, 1, v3
v_mov_b32_e32 v9, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v9, v[4:5], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB0_8
v_subrev_nc_u32_e32 v4, s4, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v8, v[4:5], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v10, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v5, vcc_lo
s_load_b32 s2, s[0:1], 0x10
global_load_b32 v0, v[10:11], off
s_waitcnt lgkmcnt(0)
s_cmpk_gt_i32 s2, 0x100
s_cbranch_scc1 .LBB0_12
s_lshr_b32 s2, s4, 31
s_lshr_b32 s3, s5, 31
s_add_i32 s4, s4, s2
s_add_i32 s5, s5, s3
s_ashr_i32 s2, s4, 1
s_ashr_i32 s3, s5, 1
v_subrev_nc_u32_e32 v10, s2, v2
v_subrev_nc_u32_e32 v2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v1, v2, v10
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_mov_b32_e32 v1, 0x459c4000
s_and_saveexec_b32 s2, vcc_lo
v_mul_lo_u32 v1, v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v2, v2, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, 11, v10
v_cndmask_b32_e64 v1, 0, 0x457a0000, vcc_lo
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x1c
s_load_b32 s1, s[0:1], 0x24
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v9, -2.0, v0
v_fmac_f32_e32 v7, -2.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, v6, v7
v_add_f32_e32 v6, v8, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
v_mul_f32_e64 v5, s4, s4
v_mul_f32_e64 v7, s5, s5
global_load_b32 v4, v[2:3], off
v_div_scale_f32 v8, null, v5, v5, v0
v_div_scale_f32 v9, null, v7, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v8, v10, 1.0
v_fma_f32 v13, -v9, v11, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v10, v12, v10
v_div_scale_f32 v12, vcc_lo, v0, v5, v0
v_fmac_f32_e32 v11, v13, v11
v_div_scale_f32 v13, s0, v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v12, v10 :: v_dual_mul_f32 v15, v13, v11
v_fma_f32 v16, -v8, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, -v9, v15, v13
v_dual_fmac_f32 v14, v16, v10 :: v_dual_fmac_f32 v15, v17, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v8, v14, v12
v_fma_f32 v9, -v9, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v8, v8, v10, v14
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v9, v9, v11, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v0, v8, v5, v0
v_div_fixup_f32 v5, v9, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
v_fmamk_f32 v0, v0, 0x40a00000, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s1, v0
global_store_b32 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernel_simulatePKfPfiiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kernel_simulatePKfPfiiifff, .Lfunc_end0-_Z15kernel_simulatePKfPfiiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernel_simulatePKfPfiiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kernel_simulatePKfPfiiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Solve-2 by SnipGhost 22.03.2017
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 8
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
__device__ float f(const int x, const int y, const int t)
{
if (t > 256) return 0;
if (x == 0 && y == 0) return 5000;
if (x*x+y*y <= 10) return 4000;
else return 0;
}
__global__ void kernel_simulate(const float *z, float *b, const int t,
const int xsize, const int ysize,
const float Hx, const float Hy, const float Ht)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
unsigned idl = idy * xsize + idx;
float top = 0, bottom = 0, left = 0, right = 0;
if (idx+1 < xsize) right = z[idl+1];
if (idx-1 >= 0) left = z[idl-1];
if (idy+1 < ysize) bottom = z[idl+xsize];
if (idy-1 >= 0) top = z[idl-xsize];
float dx = (right - 2*z[idl] + left) / (Hx * Hx);
float dy = (bottom - 2*z[idl] + top) / (Hy * Hy);
b[idl] += (5*(dx+dy) + f(idx-xsize/2, idy-ysize/2, t)) * Ht;
}
void initialize(float *d, int size, float init = 0)
{
for (int i = 0; i < size; ++i)
d[i] = init;
}
void save_data(FILE *file, float *d, int xsize, int ysize, int t)
{
if (!file)
printf("File output error\n");
else
for (int i = 0; i < xsize*ysize; ++i)
fprintf(file, "%4d %4d %20.14f %4d\n", i/xsize, i%xsize, d[i], t);
}
int main(void)
{
const float Hx = 1;
const float Hy = 1;
const float Ht = 0.05;
const int XNODES = 64;
const int YNODES = 64;
const int TICKS = 800;
const int numBytes = sizeof(float) * XNODES * YNODES;
FILE *file = fopen("out","w");
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
dim3 blocks(XNODES/BLOCK_SIZE, YNODES/BLOCK_SIZE);
float *data_dev, *buff_dev, *data_host;
data_host = (float*)malloc(numBytes);
initialize(data_host, XNODES*YNODES);
CUDA_CHECK_RETURN(hipMalloc((void**)&data_dev, numBytes));
CUDA_CHECK_RETURN(hipMalloc((void**)&buff_dev, numBytes));
CUDA_CHECK_RETURN(hipMemcpy(data_dev, data_host, numBytes, hipMemcpyHostToDevice));
for (int t = 0; t < TICKS; ++t)
{
kernel_simulate <<< blocks, threads >>> (data_dev, buff_dev, t, XNODES, YNODES, Hx, Hy, Ht);
CUDA_CHECK_RETURN(hipGetLastError());
CUDA_CHECK_RETURN(hipMemcpy(data_dev, buff_dev, numBytes, hipMemcpyDeviceToDevice));
CUDA_CHECK_RETURN(hipMemcpy(data_host, buff_dev, numBytes, hipMemcpyDeviceToHost));
save_data(file, data_host, XNODES, YNODES, t);
}
CUDA_CHECK_RETURN(hipFree((void*)data_dev));
CUDA_CHECK_RETURN(hipFree((void*)buff_dev));
CUDA_CHECK_RETURN(hipDeviceReset());
free(data_host);
fclose(file);
return 0;
} | .text
.file "main.hip"
.globl _Z30__device_stub__kernel_simulatePKfPfiiifff # -- Begin function _Z30__device_stub__kernel_simulatePKfPfiiifff
.p2align 4, 0x90
.type _Z30__device_stub__kernel_simulatePKfPfiiifff,@function
_Z30__device_stub__kernel_simulatePKfPfiiifff: # @_Z30__device_stub__kernel_simulatePKfPfiiifff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kernel_simulatePKfPfiiifff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z30__device_stub__kernel_simulatePKfPfiiifff, .Lfunc_end0-_Z30__device_stub__kernel_simulatePKfPfiiifff
.cfi_endproc
# -- End function
.globl _Z10initializePfif # -- Begin function _Z10initializePfif
.p2align 4, 0x90
.type _Z10initializePfif,@function
_Z10initializePfif: # @_Z10initializePfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10initializePfif, .Lfunc_end1-_Z10initializePfif
.cfi_endproc
# -- End function
.globl _Z9save_dataP8_IO_FILEPfiii # -- Begin function _Z9save_dataP8_IO_FILEPfiii
.p2align 4, 0x90
.type _Z9save_dataP8_IO_FILEPfiii,@function
_Z9save_dataP8_IO_FILEPfiii: # @_Z9save_dataP8_IO_FILEPfiii
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB2_5
# %bb.1: # %.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
imull %edx, %ecx
testl %ecx, %ecx
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl %r8d, %ebx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
movl %edx, %ecx
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %esi
movq %r15, %rdi
movl %eax, %edx
movl %ebx, %r8d
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r13
jne .LBB2_3
.LBB2_4: # %.loopexit
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z9save_dataP8_IO_FILEPfiii, .Lfunc_end2-_Z9save_dataP8_IO_FILEPfiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z10initializePfif.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
movq 16(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_11
# %bb.6: # %.preheader
xorl %r15d, %r15d
movabsq $34359738376, %r12 # imm = 0x800000008
leaq 112(%rsp), %r13
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_27: # in Loop: Header=BB3_7 Depth=1
movl $.Lstr, %edi
callq puts@PLT
.LBB3_19: # %_Z9save_dataP8_IO_FILEPfiii.exit
# in Loop: Header=BB3_7 Depth=1
incl %r15d
cmpl $800, %r15d # imm = 0x320
je .LBB3_20
.LBB3_7: # =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r15d, 44(%rsp)
movl $64, 40(%rsp)
movl $64, 36(%rsp)
movl $1065353216, 32(%rsp) # imm = 0x3F800000
movl $1065353216, 28(%rsp) # imm = 0x3F800000
movl $1028443341, 24(%rsp) # imm = 0x3D4CCCCD
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z15kernel_simulatePKfPfiiifff, %edi
movq %r13, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB3_10
# %bb.12: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movl $3, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_13
# %bb.14: # in Loop: Header=BB3_7 Depth=1
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_7 Depth=1
testq %rbx, %rbx
je .LBB3_27
# %bb.17: # %.lr.ph.i52.preheader
# in Loop: Header=BB3_7 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_18: # %.lr.ph.i52
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
leal 63(%rbp), %edx
testl %ebp, %ebp
cmovnsl %ebp, %edx
movl %edx, %eax
andl $-64, %eax
movl %ebp, %ecx
subl %eax, %ecx
sarl $6, %edx
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %esi
movq %rbx, %rdi
movl %r15d, %r8d
movb $1, %al
callq fprintf
incq %rbp
cmpq $4096, %rbp # imm = 0x1000
jne .LBB3_18
jmp .LBB3_19
.LBB3_20:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_21
# %bb.22:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_23
# %bb.24:
callq hipDeviceReset
testl %eax, %eax
jne .LBB3_25
# %bb.26:
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %ecx
jmp .LBB3_2
.LBB3_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $91, %ecx
jmp .LBB3_2
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %ecx
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %ecx
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %ecx
jmp .LBB3_2
.LBB3_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %ecx
jmp .LBB3_2
.LBB3_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %ecx
jmp .LBB3_2
.LBB3_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %ecx
jmp .LBB3_2
.LBB3_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $98, %ecx
jmp .LBB3_2
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_simulatePKfPfiiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kernel_simulatePKfPfiiifff,@object # @_Z15kernel_simulatePKfPfiiifff
.section .rodata,"a",@progbits
.globl _Z15kernel_simulatePKfPfiiifff
.p2align 3, 0x0
_Z15kernel_simulatePKfPfiiifff:
.quad _Z30__device_stub__kernel_simulatePKfPfiiifff
.size _Z15kernel_simulatePKfPfiiifff, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%4d %4d %20.14f %4d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "out"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SnipGhost/cuda-tech-park/master/SZ2/main.hip"
.size .L.str.5, 102
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15kernel_simulatePKfPfiiifff"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "File output error"
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kernel_simulatePKfPfiiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kernel_simulatePKfPfiiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15kernel_simulatePKfPfiiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0040*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*00b0*/ ISETP.GE.AND P1, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f26270 */
/*00c0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*00d0*/ IMAD R2, R3, c[0x0][0x174], R0 ; /* 0x00005d0003027a24 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE.U32 R10, R2.reuse, R17.reuse, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x0c0fe400078e0011 */
/*00f0*/ @P0 IADD3 R8, R2.reuse, -0x1, RZ ; /* 0xffffffff02080810 */
/* 0x040fe40007ffe0ff */
/*0100*/ @!P1 IADD3 R6, R2, 0x1, RZ ; /* 0x0000000102069810 */
/* 0x000fe20007ffe0ff */
/*0110*/ LDG.E R16, [R10.64] ; /* 0x0000000a0a107981 */
/* 0x0000a8000c1e1900 */
/*0120*/ @!P1 IMAD.WIDE.U32 R6, R6, R17, c[0x0][0x160] ; /* 0x0000580006069625 */
/* 0x000fc800078e0011 */
/*0130*/ @P0 IMAD.WIDE.U32 R8, R8, R17, c[0x0][0x160] ; /* 0x0000580008080625 */
/* 0x000fe200078e0011 */
/*0140*/ @!P1 LDG.E R13, [R6.64] ; /* 0x0000000a060d9981 */
/* 0x0002e2000c1e1900 */
/*0150*/ ISETP.GE.AND P2, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fc60003f46270 */
/*0160*/ @P0 LDG.E R12, [R8.64] ; /* 0x0000000a080c0981 */
/* 0x0008e2000c1e1900 */
/*0170*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x000fc80007ffe0ff */
/*0180*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fca0003f26270 */
/*0190*/ @P2 IADD3 R15, R2, -c[0x0][0x174], RZ ; /* 0x80005d00020f2a10 */
/* 0x000fe20007ffe0ff */
/*01a0*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fc8000001ff00 */
/*01b0*/ @P2 IMAD.WIDE.U32 R10, R15, R17, c[0x0][0x160] ; /* 0x000058000f0a2625 */
/* 0x001fca00078e0011 */
/*01c0*/ @P2 LDG.E R4, [R10.64] ; /* 0x0000000a0a042981 */
/* 0x000162000c1e1900 */
/*01d0*/ @!P1 IADD3 R14, R2, c[0x0][0x174], RZ ; /* 0x00005d00020e9a10 */
/* 0x000fca0007ffe0ff */
/*01e0*/ @!P1 IMAD.WIDE.U32 R6, R14, R17, c[0x0][0x160] ; /* 0x000058000e069625 */
/* 0x002fc800078e0011 */
/*01f0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0e7624 */
/* 0x000fe200078e00ff */
/*0200*/ @!P1 LDG.E R5, [R6.64] ; /* 0x0000000a06059981 */
/* 0x000366000c1e1900 */
/*0210*/ FMUL R14, R14, c[0x0][0x17c] ; /* 0x00005f000e0e7a20 */
/* 0x000fc80000400000 */
/*0220*/ MUFU.RCP R9, R14 ; /* 0x0000000e00097308 */
/* 0x010f220000001000 */
/*0230*/ BSSY B0, 0x320 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0240*/ FADD R8, R16, R16 ; /* 0x0000001010087221 */
/* 0x004fc80000000000 */
/*0250*/ FADD R13, -R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fc80000000100 */
/*0260*/ FADD R13, R13, R12 ; /* 0x0000000c0d0d7221 */
/* 0x000fe40000000000 */
/*0270*/ FFMA R16, -R14, R9, 1 ; /* 0x3f8000000e107423 */
/* 0x010fe40000000109 */
/*0280*/ FCHK P0, R13, R14 ; /* 0x0000000e0d007302 */
/* 0x000ea40000000000 */
/*0290*/ FFMA R16, R9, R16, R9 ; /* 0x0000001009107223 */
/* 0x000fc80000000009 */
/*02a0*/ FFMA R9, R13, R16, RZ ; /* 0x000000100d097223 */
/* 0x000fc800000000ff */
/*02b0*/ FFMA R6, -R14, R9, R13 ; /* 0x000000090e067223 */
/* 0x002fc8000000010d */
/*02c0*/ FFMA R6, R16, R6, R9 ; /* 0x0000000610067223 */
/* 0x000fe20000000009 */
/*02d0*/ @!P0 BRA 0x310 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*02e0*/ MOV R10, 0x300 ; /* 0x00000300000a7802 */
/* 0x001fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x610 ; /* 0x0000031000007944 */
/* 0x020fea0003c00000 */
/*0300*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0007 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0320*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff077624 */
/* 0x000fe200078e00ff */
/*0330*/ BSSY B0, 0x440 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0340*/ FADD R5, -R8, R5 ; /* 0x0000000508057221 */
/* 0x020fe40000000100 */
/*0350*/ FMUL R7, R7, c[0x0][0x180] ; /* 0x0000600007077a20 */
/* 0x000fe40000400000 */
/*0360*/ FADD R13, R5, R4 ; /* 0x00000004050d7221 */
/* 0x000fe40000000000 */
/*0370*/ MUFU.RCP R10, R7 ; /* 0x00000007000a7308 */
/* 0x000e300000001000 */
/*0380*/ FCHK P0, R13, R7 ; /* 0x000000070d007302 */
/* 0x000e620000000000 */
/*0390*/ FFMA R9, -R7, R10, 1 ; /* 0x3f80000007097423 */
/* 0x001fc8000000010a */
/*03a0*/ FFMA R9, R10, R9, R10 ; /* 0x000000090a097223 */
/* 0x000fc8000000000a */
/*03b0*/ FFMA R4, R13, R9, RZ ; /* 0x000000090d047223 */
/* 0x000fc800000000ff */
/*03c0*/ FFMA R5, -R7, R4, R13 ; /* 0x0000000407057223 */
/* 0x000fc8000000010d */
/*03d0*/ FFMA R9, R9, R5, R4 ; /* 0x0000000509097223 */
/* 0x000fe20000000004 */
/*03e0*/ @!P0 BRA 0x430 ; /* 0x0000004000008947 */
/* 0x002fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0007 */
/*0400*/ MOV R10, 0x420 ; /* 0x00000420000a7802 */
/* 0x000fe40000000f00 */
/*0410*/ CALL.REL.NOINC 0x610 ; /* 0x000001f000007944 */
/* 0x000fea0003c00000 */
/*0420*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0007 */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0450*/ LEA.HI.X R5, R2, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f14ff */
/*0460*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000162000c1e1900 */
/*0470*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0480*/ UMOV UR8, 0x2 ; /* 0x0000000200087882 */
/* 0x000fe20000000000 */
/*0490*/ FADD R9, R9, R6 ; /* 0x0000000609097221 */
/* 0x000fe20000000000 */
/*04a0*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*04b0*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe20000000800 */
/*04c0*/ ISETP.GT.AND P0, PT, R2, 0x100, PT ; /* 0x000001000200780c */
/* 0x000fe20003f04270 */
/*04d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*04e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*04f0*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fc40008000000 */
/*0500*/ UIMAD.WIDE.U32 UR4, UR8, UR5, UR4 ; /* 0x00000005080472a5 */
/* 0x000fe4000f8e0004 */
/*0510*/ UIMAD.WIDE.U32 UR6, UR8, UR7, UR6 ; /* 0x00000007080672a5 */
/* 0x000fe4000f8e0006 */
/*0520*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011405 */
/*0530*/ USHF.R.S32.HI UR7, URZ, 0x1, UR7 ; /* 0x000000013f077899 */
/* 0x000fc80008011407 */
/*0540*/ IADD3 R0, R0, -UR5, RZ ; /* 0x8000000500007c10 */
/* 0x000fe4000fffe0ff */
/*0550*/ IADD3 R3, R3, -UR7, RZ ; /* 0x8000000703037c10 */
/* 0x000fe2000fffe0ff */
/*0560*/ @P0 BRA 0x5d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT P0, RZ, R3, R0, RZ, 0xfc, !PT ; /* 0x0000000003ff7212 */
/* 0x001fe2000780fcff */
/*0580*/ IMAD.MOV.U32 R2, RZ, RZ, 0x459c4000 ; /* 0x459c4000ff027424 */
/* 0x000fd800078e00ff */
/*0590*/ @P0 IMAD R0, R0, R0, RZ ; /* 0x0000000000000224 */
/* 0x000fc800078e02ff */
/*05a0*/ @P0 IMAD R0, R3, R3, R0 ; /* 0x0000000303000224 */
/* 0x000fca00078e0200 */
/*05b0*/ @P0 ISETP.GE.U32.AND P1, PT, R0, 0xb, PT ; /* 0x0000000b0000080c */
/* 0x000fc80003f26070 */
/*05c0*/ @P0 FSEL R2, RZ, 4000, P1 ; /* 0x457a0000ff020808 */
/* 0x000fca0000800000 */
/*05d0*/ FFMA R2, R9, 5, R2 ; /* 0x40a0000009027823 */
/* 0x001fc80000000002 */
/*05e0*/ FFMA R7, R2, c[0x0][0x184], R7 ; /* 0x0000610002077a23 */
/* 0x020fca0000000007 */
/*05f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c10190a */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ SHF.R.U32.HI R11, RZ, 0x17, R14.reuse ; /* 0x00000017ff0b7819 */
/* 0x100fe2000001160e */
/*0620*/ BSSY B1, 0xc70 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0630*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0640*/ IMAD.MOV.U32 R12, RZ, RZ, R14 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e000e */
/*0650*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fe400078ec0ff */
/*0660*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe200078ec0ff */
/*0670*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0680*/ IADD3 R17, R11, -0x1, RZ ; /* 0xffffffff0b117810 */
/* 0x000fe40007ffe0ff */
/*0690*/ IADD3 R16, R15, -0x1, RZ ; /* 0xffffffff0f107810 */
/* 0x000fc40007ffe0ff */
/*06a0*/ ISETP.GT.U32.AND P0, PT, R17, 0xfd, PT ; /* 0x000000fd1100780c */
/* 0x000fc80003f04070 */
/*06b0*/ ISETP.GT.U32.OR P0, PT, R16, 0xfd, P0 ; /* 0x000000fd1000780c */
/* 0x000fda0000704470 */
/*06c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*06d0*/ @!P0 BRA 0x850 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*06e0*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*06f0*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fc80003f3c200 */
/*0700*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0710*/ @P0 BRA 0xc50 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0720*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c807 */
/*0730*/ @!P0 BRA 0xc30 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0740*/ FSETP.NEU.FTZ.AND P2, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f5d200 */
/*0750*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3d200 */
/*0760*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0770*/ @!P1 BRA !P2, 0xc30 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0780*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0790*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*07a0*/ @P1 BRA 0xc10 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*07c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*07d0*/ @P0 BRA 0xbe0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f06270 */
/*07f0*/ ISETP.GE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fd60003f26270 */
/*0800*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0810*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0820*/ @!P0 FFMA R7, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d078823 */
/* 0x000fe400000000ff */
/*0830*/ @!P1 FFMA R12, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0c9823 */
/* 0x000fe200000000ff */
/*0840*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0850*/ LEA R13, R11, 0xc0800000, 0x17 ; /* 0xc08000000b0d7811 */
/* 0x000fe200078eb8ff */
/*0860*/ BSSY B2, 0xbd0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0870*/ IMAD.IADD R13, R12, 0x1, -R13 ; /* 0x000000010c0d7824 */
/* 0x000fe200078e0a0d */
/*0880*/ IADD3 R12, R15, -0x7f, RZ ; /* 0xffffff810f0c7810 */
/* 0x000fc60007ffe0ff */
/*0890*/ MUFU.RCP R14, R13 ; /* 0x0000000d000e7308 */
/* 0x000e220000001000 */
/*08a0*/ FADD.FTZ R16, -R13, -RZ ; /* 0x800000ff0d107221 */
/* 0x000fe40000010100 */
/*08b0*/ IMAD R7, R12.reuse, -0x800000, R7 ; /* 0xff8000000c077824 */
/* 0x040fe200078e0207 */
/*08c0*/ IADD3 R12, R12, 0x7f, -R11 ; /* 0x0000007f0c0c7810 */
/* 0x000fca0007ffe80b */
/*08d0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0209 */
/*08e0*/ FFMA R15, R14, R16, 1 ; /* 0x3f8000000e0f7423 */
/* 0x001fc80000000010 */
/*08f0*/ FFMA R18, R14, R15, R14 ; /* 0x0000000f0e127223 */
/* 0x000fc8000000000e */
/*0900*/ FFMA R14, R7, R18, RZ ; /* 0x00000012070e7223 */
/* 0x000fc800000000ff */
/*0910*/ FFMA R15, R16, R14, R7 ; /* 0x0000000e100f7223 */
/* 0x000fc80000000007 */
/*0920*/ FFMA R15, R18, R15, R14 ; /* 0x0000000f120f7223 */
/* 0x000fc8000000000e */
/*0930*/ FFMA R16, R16, R15, R7 ; /* 0x0000000f10107223 */
/* 0x000fc80000000007 */
/*0940*/ FFMA R7, R18, R16, R15 ; /* 0x0000001012077223 */
/* 0x000fca000000000f */
/*0950*/ SHF.R.U32.HI R11, RZ, 0x17, R7 ; /* 0x00000017ff0b7819 */
/* 0x000fc80000011607 */
/*0960*/ LOP3.LUT R11, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0b0b7812 */
/* 0x000fca00078ec0ff */
/*0970*/ IMAD.IADD R13, R11, 0x1, R12 ; /* 0x000000010b0d7824 */
/* 0x000fca00078e020c */
/*0980*/ IADD3 R9, R13, -0x1, RZ ; /* 0xffffffff0d097810 */
/* 0x000fc80007ffe0ff */
/*0990*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*09a0*/ @!P0 BRA 0xbb0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.GT.AND P0, PT, R13, 0xfe, PT ; /* 0x000000fe0d00780c */
/* 0x000fda0003f04270 */
/*09c0*/ @P0 BRA 0xb80 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*09d0*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fda0003f06270 */
/*09e0*/ @P0 BRA 0xbc0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*09f0*/ ISETP.GE.AND P0, PT, R13, -0x18, PT ; /* 0xffffffe80d00780c */
/* 0x000fe40003f06270 */
/*0a00*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0a10*/ @!P0 BRA 0xbc0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a20*/ FFMA.RZ R9, R18.reuse, R16.reuse, R15.reuse ; /* 0x0000001012097223 */
/* 0x1c0fe2000000c00f */
/*0a30*/ IADD3 R14, R13.reuse, 0x20, RZ ; /* 0x000000200d0e7810 */
/* 0x040fe20007ffe0ff */
/*0a40*/ FFMA.RM R12, R18.reuse, R16.reuse, R15.reuse ; /* 0x00000010120c7223 */
/* 0x1c0fe2000000400f */
/*0a50*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*0a60*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*0a70*/ FFMA.RP R9, R18, R16, R15 ; /* 0x0000001012097223 */
/* 0x000fe2000000800f */
/*0a80*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f25270 */
/*0a90*/ IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0d */
/*0aa0*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0ab0*/ FSETP.NEU.FTZ.AND P0, PT, R9, R12, PT ; /* 0x0000000c0900720b */
/* 0x000fc40003f1d000 */
/*0ac0*/ SHF.L.U32 R14, R11, R14, RZ ; /* 0x0000000e0b0e7219 */
/* 0x000fe400000006ff */
/*0ad0*/ SEL R12, R13, RZ, P2 ; /* 0x000000ff0d0c7207 */
/* 0x000fe40001000000 */
/*0ae0*/ ISETP.NE.AND P1, PT, R14, RZ, P1 ; /* 0x000000ff0e00720c */
/* 0x000fe40000f25270 */
/*0af0*/ SHF.R.U32.HI R12, RZ, R12, R11 ; /* 0x0000000cff0c7219 */
/* 0x000fe4000001160b */
/*0b00*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b10*/ SHF.R.U32.HI R14, RZ, 0x1, R12 ; /* 0x00000001ff0e7819 */
/* 0x000fc4000001160c */
/*0b20*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0b30*/ LOP3.LUT R9, R9, 0x1, R14, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80e */
/*0b40*/ LOP3.LUT R9, R9, R12, RZ, 0xc0, !PT ; /* 0x0000000c09097212 */
/* 0x000fca00078ec0ff */
/*0b50*/ IMAD.IADD R14, R14, 0x1, R9 ; /* 0x000000010e0e7824 */
/* 0x000fca00078e0209 */
/*0b60*/ LOP3.LUT R7, R14, R7, RZ, 0xfc, !PT ; /* 0x000000070e077212 */
/* 0x000fe200078efcff */
/*0b70*/ BRA 0xbc0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0b80*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0b90*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0bc0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xc60 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fc800078e4807 */
/*0bf0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc60 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c10*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fe200078e4807 */
/*0c20*/ BRA 0xc60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c30*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*0c40*/ BRA 0xc60 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c50*/ FADD.FTZ R7, R13, R14 ; /* 0x0000000e0d077221 */
/* 0x000fe40000010000 */
/*0c60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c70*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*0c80*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff3700a007950 */
/* 0x000fea0003c3ffff */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15kernel_simulatePKfPfiiifff
.globl _Z15kernel_simulatePKfPfiiifff
.p2align 8
.type _Z15kernel_simulatePKfPfiiifff,@function
_Z15kernel_simulatePKfPfiiifff:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x14
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_lshr_b32 s5, s5, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v2
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s4, v4
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, 1, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v7, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s5, exec_lo
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB0_4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, -1, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v6, v[4:5], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_load_b32 s5, s[0:1], 0x18
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v1, 1, v3
v_mov_b32_e32 v9, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v9, v[4:5], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB0_8
v_subrev_nc_u32_e32 v4, s4, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v8, v[4:5], off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_add_co_u32 v10, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v5, vcc_lo
s_load_b32 s2, s[0:1], 0x10
global_load_b32 v0, v[10:11], off
s_waitcnt lgkmcnt(0)
s_cmpk_gt_i32 s2, 0x100
s_cbranch_scc1 .LBB0_12
s_lshr_b32 s2, s4, 31
s_lshr_b32 s3, s5, 31
s_add_i32 s4, s4, s2
s_add_i32 s5, s5, s3
s_ashr_i32 s2, s4, 1
s_ashr_i32 s3, s5, 1
v_subrev_nc_u32_e32 v10, s2, v2
v_subrev_nc_u32_e32 v2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v1, v2, v10
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_mov_b32_e32 v1, 0x459c4000
s_and_saveexec_b32 s2, vcc_lo
v_mul_lo_u32 v1, v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v2, v2, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, 11, v10
v_cndmask_b32_e64 v1, 0, 0x457a0000, vcc_lo
s_or_b32 exec_lo, exec_lo, s2
.LBB0_12:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b64 s[4:5], s[0:1], 0x1c
s_load_b32 s1, s[0:1], 0x24
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v9, -2.0, v0
v_fmac_f32_e32 v7, -2.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, v6, v7
v_add_f32_e32 v6, v8, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
v_mul_f32_e64 v5, s4, s4
v_mul_f32_e64 v7, s5, s5
global_load_b32 v4, v[2:3], off
v_div_scale_f32 v8, null, v5, v5, v0
v_div_scale_f32 v9, null, v7, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v8, v10, 1.0
v_fma_f32 v13, -v9, v11, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v10, v12, v10
v_div_scale_f32 v12, vcc_lo, v0, v5, v0
v_fmac_f32_e32 v11, v13, v11
v_div_scale_f32 v13, s0, v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v12, v10 :: v_dual_mul_f32 v15, v13, v11
v_fma_f32 v16, -v8, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v17, -v9, v15, v13
v_dual_fmac_f32 v14, v16, v10 :: v_dual_fmac_f32 v15, v17, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v8, v14, v12
v_fma_f32 v9, -v9, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v8, v8, v10, v14
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v9, v9, v11, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v0, v8, v5, v0
v_div_fixup_f32 v5, v9, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
v_fmamk_f32 v0, v0, 0x40a00000, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, s1, v0
global_store_b32 v[2:3], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernel_simulatePKfPfiiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15kernel_simulatePKfPfiiifff, .Lfunc_end0-_Z15kernel_simulatePKfPfiiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernel_simulatePKfPfiiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15kernel_simulatePKfPfiiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003df6e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fiii
.type _Z1fiii, @function
_Z1fiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1fiii, .-_Z1fiii
.globl _Z10initializePfif
.type _Z10initializePfif, @function
_Z10initializePfif:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L5
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
.L7:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L7
.L5:
ret
.cfi_endproc
.LFE2058:
.size _Z10initializePfif, .-_Z10initializePfif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "File output error\n"
.LC1:
.string "%4d %4d %20.14f %4d\n"
.text
.globl _Z9save_dataP8_IO_FILEPfiii
.type _Z9save_dataP8_IO_FILEPfiii, @function
_Z9save_dataP8_IO_FILEPfiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %r8d, 12(%rsp)
testq %rdi, %rdi
je .L10
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebp
imull %edx, %ecx
movslq %ecx, %r15
movl $0, %ebx
leaq .LC1(%rip), %r14
testl %ecx, %ecx
jle .L9
.L13:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movl %ebx, %eax
cltd
idivl %ebp
movl %edx, %r8d
movl %eax, %ecx
movl 12(%rsp), %r9d
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %r15, %rbx
jne .L13
.L9:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2059:
.size _Z9save_dataP8_IO_FILEPfiii, .-_Z9save_dataP8_IO_FILEPfiii
.globl _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
.type _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff, @function
_Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff:
.LFB2085:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kernel_simulatePKfPfiiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff, .-_Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
.globl _Z15kernel_simulatePKfPfiiifff
.type _Z15kernel_simulatePKfPfiiifff, @function
_Z15kernel_simulatePKfPfiiifff:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15kernel_simulatePKfPfiiifff, .-_Z15kernel_simulatePKfPfiiifff
.section .rodata.str1.1
.LC2:
.string "w"
.LC3:
.string "out"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SnipGhost/cuda-tech-park/master/SZ2/main.cu"
.align 8
.LC6:
.string "Error %s at line %d in file %s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl $8, 16(%rsp)
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 28(%rsp)
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, %edi
call malloc@PLT
movq %rax, %rbp
pxor %xmm0, %xmm0
movl $4096, %esi
movq %rax, %rdi
call _Z10initializePfif
movq %rsp, %rdi
movl $16384, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 8(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movl $1, %ecx
movl $16384, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L42
movl $0, %ebx
jmp .L28
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $81, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $82, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $83, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L43
movl $3, %ecx
movl $16384, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
movl $2, %ecx
movl $16384, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L45
movl %ebx, %r8d
movl $64, %ecx
movl $64, %edx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9save_dataP8_IO_FILEPfiii
addl $1, %ebx
cmpl $800, %ebx
je .L46
.L28:
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movss .LC7(%rip), %xmm2
movss .LC8(%rip), %xmm1
movaps %xmm1, %xmm0
movl $64, %r8d
movl $64, %ecx
movl %ebx, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z44__device_stub__Z15kernel_simulatePKfPfiiifffPKfPfiiifff
jmp .L29
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $88, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $89, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $90, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movq (%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L47
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L48
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L49
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L50
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $94, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $95, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %r9
movl $96, %r8d
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z15kernel_simulatePKfPfiiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_simulatePKfPfiiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 1028443341
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z30__device_stub__kernel_simulatePKfPfiiifff # -- Begin function _Z30__device_stub__kernel_simulatePKfPfiiifff
.p2align 4, 0x90
.type _Z30__device_stub__kernel_simulatePKfPfiiifff,@function
_Z30__device_stub__kernel_simulatePKfPfiiifff: # @_Z30__device_stub__kernel_simulatePKfPfiiifff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kernel_simulatePKfPfiiifff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z30__device_stub__kernel_simulatePKfPfiiifff, .Lfunc_end0-_Z30__device_stub__kernel_simulatePKfPfiiifff
.cfi_endproc
# -- End function
.globl _Z10initializePfif # -- Begin function _Z10initializePfif
.p2align 4, 0x90
.type _Z10initializePfif,@function
_Z10initializePfif: # @_Z10initializePfif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z10initializePfif, .Lfunc_end1-_Z10initializePfif
.cfi_endproc
# -- End function
.globl _Z9save_dataP8_IO_FILEPfiii # -- Begin function _Z9save_dataP8_IO_FILEPfiii
.p2align 4, 0x90
.type _Z9save_dataP8_IO_FILEPfiii,@function
_Z9save_dataP8_IO_FILEPfiii: # @_Z9save_dataP8_IO_FILEPfiii
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB2_5
# %bb.1: # %.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
imull %edx, %ecx
testl %ecx, %ecx
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl %r8d, %ebx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r13d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
cltd
idivl %ebp
movl %edx, %ecx
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %esi
movq %r15, %rdi
movl %eax, %edx
movl %ebx, %r8d
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r13
jne .LBB2_3
.LBB2_4: # %.loopexit
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z9save_dataP8_IO_FILEPfiii, .Lfunc_end2-_Z9save_dataP8_IO_FILEPfiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z10initializePfif.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
movl $16384, %edi # imm = 0x4000
callq malloc
movq %rax, %r14
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
movq 16(%rsp), %rdi
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_11
# %bb.6: # %.preheader
xorl %r15d, %r15d
movabsq $34359738376, %r12 # imm = 0x800000008
leaq 112(%rsp), %r13
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_27: # in Loop: Header=BB3_7 Depth=1
movl $.Lstr, %edi
callq puts@PLT
.LBB3_19: # %_Z9save_dataP8_IO_FILEPfiii.exit
# in Loop: Header=BB3_7 Depth=1
incl %r15d
cmpl $800, %r15d # imm = 0x320
je .LBB3_20
.LBB3_7: # =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %r15d, 44(%rsp)
movl $64, 40(%rsp)
movl $64, 36(%rsp)
movl $1065353216, 32(%rsp) # imm = 0x3F800000
movl $1065353216, 28(%rsp) # imm = 0x3F800000
movl $1028443341, 24(%rsp) # imm = 0x3D4CCCCD
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z15kernel_simulatePKfPfiiifff, %edi
movq %r13, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB3_10
# %bb.12: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movl $3, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_13
# %bb.14: # in Loop: Header=BB3_7 Depth=1
movq 8(%rsp), %rsi
movl $16384, %edx # imm = 0x4000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.16: # in Loop: Header=BB3_7 Depth=1
testq %rbx, %rbx
je .LBB3_27
# %bb.17: # %.lr.ph.i52.preheader
# in Loop: Header=BB3_7 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_18: # %.lr.ph.i52
# Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
leal 63(%rbp), %edx
testl %ebp, %ebp
cmovnsl %ebp, %edx
movl %edx, %eax
andl $-64, %eax
movl %ebp, %ecx
subl %eax, %ecx
sarl $6, %edx
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %esi
movq %rbx, %rdi
movl %r15d, %r8d
movb $1, %al
callq fprintf
incq %rbp
cmpq $4096, %rbp # imm = 0x1000
jne .LBB3_18
jmp .LBB3_19
.LBB3_20:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_21
# %bb.22:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB3_23
# %bb.24:
callq hipDeviceReset
testl %eax, %eax
jne .LBB3_25
# %bb.26:
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %ecx
jmp .LBB3_2
.LBB3_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $91, %ecx
jmp .LBB3_2
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %ecx
.LBB3_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $83, %ecx
jmp .LBB3_2
.LBB3_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $84, %ecx
jmp .LBB3_2
.LBB3_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $85, %ecx
jmp .LBB3_2
.LBB3_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %ecx
jmp .LBB3_2
.LBB3_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %ecx
jmp .LBB3_2
.LBB3_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $98, %ecx
jmp .LBB3_2
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_simulatePKfPfiiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15kernel_simulatePKfPfiiifff,@object # @_Z15kernel_simulatePKfPfiiifff
.section .rodata,"a",@progbits
.globl _Z15kernel_simulatePKfPfiiifff
.p2align 3, 0x0
_Z15kernel_simulatePKfPfiiifff:
.quad _Z30__device_stub__kernel_simulatePKfPfiiifff
.size _Z15kernel_simulatePKfPfiiifff, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%4d %4d %20.14f %4d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "out"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error %s at line %d in file %s\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SnipGhost/cuda-tech-park/master/SZ2/main.hip"
.size .L.str.5, 102
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15kernel_simulatePKfPfiiifff"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "File output error"
.size .Lstr, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__kernel_simulatePKfPfiiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15kernel_simulatePKfPfiiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*-----------
*
* clock.cu
*
* This is the source file of a kernel to measure time for each block.
*
* This kernel is from CUDA samples. clock.cu
*
* streamsOptBenchmark/clock.cu
*
* By Hao Li
*
*------------
*/
// This kernel computes a standard parallel reduction and evaluates the
// time it takes to do that for each block. The timing results are stored
// in device memory.
__global__ static void clockTimedReduction(const float *input, float *output, clock_t *timer)
{
for(int l = 0; l < 100000; l++)
{
// __shared__ float shared[2 * blockDim.x];
extern __shared__ float shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
if (tid == 0) timer[bid] = clock();
// Copy input.
shared[tid] = input[tid];
shared[tid + blockDim.x] = input[tid + blockDim.x];
// Perform reduction to find minimum.
for (int d = blockDim.x; d > 0; d /= 2)
{
__syncthreads();
if (tid < d)
{
float f0 = shared[tid];
float f1 = shared[tid + d];
if (f1 < f0)
{
shared[tid] = f1;
}
}
}
// Write result.
if (tid == 0) output[bid] = shared[0];
__syncthreads();
if (tid == 0) timer[bid+gridDim.x] = clock();
}
}
// int main(int argc, char **argv)
// {
// printf("CUDA Clock sample\n");
// // This will pick the best possible CUDA capable device
// int dev = findCudaDevice(argc, (const char **)argv);
// float *dinput = NULL;
// float *doutput = NULL;
// clock_t *dtimer = NULL;
// clock_t timer[NUM_BLOCKS * 2];
// float input[NUM_THREADS * 2];
// for (int i = 0; i < NUM_THREADS * 2; i++)
// {
// input[i] = (float)i;
// }
// checkCudaErrors(cudaMalloc((void **)&dinput, sizeof(float) * NUM_THREADS * 2));
// checkCudaErrors(cudaMalloc((void **)&doutput, sizeof(float) * NUM_BLOCKS));
// checkCudaErrors(cudaMalloc((void **)&dtimer, sizeof(clock_t) * NUM_BLOCKS * 2));
// checkCudaErrors(cudaMemcpy(dinput, input, sizeof(float) * NUM_THREADS * 2, cudaMemcpyHostToDevice));
// clockTimedReduction<<<NUM_BLOCKS, NUM_THREADS, sizeof(float) * 2 *NUM_THREADS>>>(dinput, doutput, dtimer);
// checkCudaErrors(cudaMemcpy(timer, dtimer, sizeof(clock_t) * NUM_BLOCKS * 2, cudaMemcpyDeviceToHost));
// checkCudaErrors(cudaFree(dinput));
// checkCudaErrors(cudaFree(doutput));
// checkCudaErrors(cudaFree(dtimer));
// // Compute the difference between the last block end and the first block start.
// clock_t minStart = timer[0];
// clock_t maxEnd = timer[NUM_BLOCKS];
// for (int i = 1; i < NUM_BLOCKS; i++)
// {
// minStart = timer[i] < minStart ? timer[i] : minStart;
// maxEnd = timer[NUM_BLOCKS+i] > maxEnd ? timer[NUM_BLOCKS+i] : maxEnd;
// }
// printf("Total clocks = %d\n", (int)(maxEnd - minStart));
// // cudaDeviceReset causes the driver to clean up all state. While
// // not mandatory in normal operation, it is good practice. It is also
// // needed to ensure correct operation when the application is being
// // profiled. Calling cudaDeviceReset causes all profile data to be
// // flushed before the application exits
// cudaDeviceReset();
// return EXIT_SUCCESS;
// } | code for sm_80
Function : _Z19clockTimedReductionPKfPfPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0060*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R10, R0.reuse, c[0x0][0x0], RZ ; /* 0x00000000000a7a10 */
/* 0x041fe20007ffe0ff */
/*0080*/ IMAD.SHL.U32 R12, R0, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020d */
/*00a0*/ IADD3 R8, R4, c[0x0][0xc], RZ ; /* 0x0000030004087a10 */
/* 0x002fc60007ffe0ff */
/*00b0*/ IMAD.WIDE R6, R4, R9, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fc800078e0209 */
/*00c0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*00d0*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e000d */
/*00e0*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc800078e0009 */
/*00f0*/ IMAD R13, R13, c[0x0][0x0], R12 ; /* 0x000000000d0d7a24 */
/* 0x000fe400078e020c */
/*0100*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R18, 0x186a0, PT ; /* 0x000186a01200780c */
/* 0x001fd60003f26070 */
/*0130*/ @!P0 CS2R R14, SR_CLOCKLO ; /* 0x00000000000e8805 */
/* 0x000fca0000015000 */
/*0140*/ @!P0 STG.E.64 [R6.64], R14 ; /* 0x0000000e06008986 */
/* 0x0001e8000c101b04 */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee2000c1e1900 */
/*0170*/ MOV R19, c[0x0][0x0] ; /* 0x0000000000137a02 */
/* 0x000fc80000000f00 */
/*0180*/ ISETP.GE.AND P2, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe20003f46270 */
/*0190*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0041e80000004800 */
/*01a0*/ STS [R13], R16 ; /* 0x000000100d007388 */
/* 0x0081f00000000800 */
/*01b0*/ @!P2 BRA 0x2a0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x001fc800078e00ff */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GE.AND P2, PT, R0, R15, PT ; /* 0x0000000f0000720c */
/* 0x000fca0003f46270 */
/*01f0*/ BSSY B0, 0x270 ; /* 0x0000007000007945 */
/* 0x000ff00003800000 */
/*0200*/ @P2 BRA 0x260 ; /* 0x0000005000002947 */
/* 0x001fea0003800000 */
/*0210*/ LEA R16, R15, R12, 0x2 ; /* 0x0000000c0f107211 */
/* 0x000fe200078e10ff */
/*0220*/ LDS R14, [R0.X4] ; /* 0x00000000000e7984 */
/* 0x000fe80000004800 */
/*0230*/ LDS R17, [R16] ; /* 0x0000000010117984 */
/* 0x000e240000000800 */
/*0240*/ FSETP.GEU.AND P2, PT, R17, R14, PT ; /* 0x0000000e1100720b */
/* 0x001fda0003f4e000 */
/*0250*/ @!P2 STS [R0.X4], R17 ; /* 0x000000110000a388 */
/* 0x0001e40000004800 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ SHF.R.U32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f7819 */
/* 0x000fc8000001160f */
/*0280*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fda0003f45270 */
/*0290*/ @P2 BRA 0x1d0 ; /* 0xffffff3000002947 */
/* 0x000fea000383ffff */
/*02a0*/ @!P0 LDS R15, [RZ] ; /* 0x00000000ff0f8984 */
/* 0x001e220000000800 */
/*02b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*02c0*/ @!P0 STG.E [R4.64], R15 ; /* 0x0000000f04008986 */
/* 0x0011e8000c101904 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ @!P0 CS2R R14, SR_CLOCKLO ; /* 0x00000000000e8805 */
/* 0x001fca0000015000 */
/*02f0*/ @!P0 STG.E.64 [R8.64], R14 ; /* 0x0000000e08008986 */
/* 0x0001e2000c101b04 */
/*0300*/ @!P1 BRA 0x100 ; /* 0xfffffdf000009947 */
/* 0x000fea000383ffff */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*-----------
*
* clock.cu
*
* This is the source file of a kernel to measure time for each block.
*
* This kernel is from CUDA samples. clock.cu
*
* streamsOptBenchmark/clock.cu
*
* By Hao Li
*
*------------
*/
// This kernel computes a standard parallel reduction and evaluates the
// time it takes to do that for each block. The timing results are stored
// in device memory.
__global__ static void clockTimedReduction(const float *input, float *output, clock_t *timer)
{
for(int l = 0; l < 100000; l++)
{
// __shared__ float shared[2 * blockDim.x];
extern __shared__ float shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
if (tid == 0) timer[bid] = clock();
// Copy input.
shared[tid] = input[tid];
shared[tid + blockDim.x] = input[tid + blockDim.x];
// Perform reduction to find minimum.
for (int d = blockDim.x; d > 0; d /= 2)
{
__syncthreads();
if (tid < d)
{
float f0 = shared[tid];
float f1 = shared[tid + d];
if (f1 < f0)
{
shared[tid] = f1;
}
}
}
// Write result.
if (tid == 0) output[bid] = shared[0];
__syncthreads();
if (tid == 0) timer[bid+gridDim.x] = clock();
}
}
// int main(int argc, char **argv)
// {
// printf("CUDA Clock sample\n");
// // This will pick the best possible CUDA capable device
// int dev = findCudaDevice(argc, (const char **)argv);
// float *dinput = NULL;
// float *doutput = NULL;
// clock_t *dtimer = NULL;
// clock_t timer[NUM_BLOCKS * 2];
// float input[NUM_THREADS * 2];
// for (int i = 0; i < NUM_THREADS * 2; i++)
// {
// input[i] = (float)i;
// }
// checkCudaErrors(cudaMalloc((void **)&dinput, sizeof(float) * NUM_THREADS * 2));
// checkCudaErrors(cudaMalloc((void **)&doutput, sizeof(float) * NUM_BLOCKS));
// checkCudaErrors(cudaMalloc((void **)&dtimer, sizeof(clock_t) * NUM_BLOCKS * 2));
// checkCudaErrors(cudaMemcpy(dinput, input, sizeof(float) * NUM_THREADS * 2, cudaMemcpyHostToDevice));
// clockTimedReduction<<<NUM_BLOCKS, NUM_THREADS, sizeof(float) * 2 *NUM_THREADS>>>(dinput, doutput, dtimer);
// checkCudaErrors(cudaMemcpy(timer, dtimer, sizeof(clock_t) * NUM_BLOCKS * 2, cudaMemcpyDeviceToHost));
// checkCudaErrors(cudaFree(dinput));
// checkCudaErrors(cudaFree(doutput));
// checkCudaErrors(cudaFree(dtimer));
// // Compute the difference between the last block end and the first block start.
// clock_t minStart = timer[0];
// clock_t maxEnd = timer[NUM_BLOCKS];
// for (int i = 1; i < NUM_BLOCKS; i++)
// {
// minStart = timer[i] < minStart ? timer[i] : minStart;
// maxEnd = timer[NUM_BLOCKS+i] > maxEnd ? timer[NUM_BLOCKS+i] : maxEnd;
// }
// printf("Total clocks = %d\n", (int)(maxEnd - minStart));
// // cudaDeviceReset causes the driver to clean up all state. While
// // not mandatory in normal operation, it is good practice. It is also
// // needed to ensure correct operation when the application is being
// // profiled. Calling cudaDeviceReset causes all profile data to be
// // flushed before the application exits
// cudaDeviceReset();
// return EXIT_SUCCESS;
// } | .file "tmpxft_000760cf_00000000-6_clock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL19clockTimedReductionPKfPfPl, @function
_ZL19clockTimedReductionPKfPfPl:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL19clockTimedReductionPKfPfPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL19clockTimedReductionPKfPfPl, .-_ZL19clockTimedReductionPKfPfPl
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19clockTimedReductionPKfPfPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19clockTimedReductionPKfPfPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*-----------
*
* clock.cu
*
* This is the source file of a kernel to measure time for each block.
*
* This kernel is from CUDA samples. clock.cu
*
* streamsOptBenchmark/clock.cu
*
* By Hao Li
*
*------------
*/
// This kernel computes a standard parallel reduction and evaluates the
// time it takes to do that for each block. The timing results are stored
// in device memory.
__global__ static void clockTimedReduction(const float *input, float *output, clock_t *timer)
{
for(int l = 0; l < 100000; l++)
{
// __shared__ float shared[2 * blockDim.x];
extern __shared__ float shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
if (tid == 0) timer[bid] = clock();
// Copy input.
shared[tid] = input[tid];
shared[tid + blockDim.x] = input[tid + blockDim.x];
// Perform reduction to find minimum.
for (int d = blockDim.x; d > 0; d /= 2)
{
__syncthreads();
if (tid < d)
{
float f0 = shared[tid];
float f1 = shared[tid + d];
if (f1 < f0)
{
shared[tid] = f1;
}
}
}
// Write result.
if (tid == 0) output[bid] = shared[0];
__syncthreads();
if (tid == 0) timer[bid+gridDim.x] = clock();
}
}
// int main(int argc, char **argv)
// {
// printf("CUDA Clock sample\n");
// // This will pick the best possible CUDA capable device
// int dev = findCudaDevice(argc, (const char **)argv);
// float *dinput = NULL;
// float *doutput = NULL;
// clock_t *dtimer = NULL;
// clock_t timer[NUM_BLOCKS * 2];
// float input[NUM_THREADS * 2];
// for (int i = 0; i < NUM_THREADS * 2; i++)
// {
// input[i] = (float)i;
// }
// checkCudaErrors(cudaMalloc((void **)&dinput, sizeof(float) * NUM_THREADS * 2));
// checkCudaErrors(cudaMalloc((void **)&doutput, sizeof(float) * NUM_BLOCKS));
// checkCudaErrors(cudaMalloc((void **)&dtimer, sizeof(clock_t) * NUM_BLOCKS * 2));
// checkCudaErrors(cudaMemcpy(dinput, input, sizeof(float) * NUM_THREADS * 2, cudaMemcpyHostToDevice));
// clockTimedReduction<<<NUM_BLOCKS, NUM_THREADS, sizeof(float) * 2 *NUM_THREADS>>>(dinput, doutput, dtimer);
// checkCudaErrors(cudaMemcpy(timer, dtimer, sizeof(clock_t) * NUM_BLOCKS * 2, cudaMemcpyDeviceToHost));
// checkCudaErrors(cudaFree(dinput));
// checkCudaErrors(cudaFree(doutput));
// checkCudaErrors(cudaFree(dtimer));
// // Compute the difference between the last block end and the first block start.
// clock_t minStart = timer[0];
// clock_t maxEnd = timer[NUM_BLOCKS];
// for (int i = 1; i < NUM_BLOCKS; i++)
// {
// minStart = timer[i] < minStart ? timer[i] : minStart;
// maxEnd = timer[NUM_BLOCKS+i] > maxEnd ? timer[NUM_BLOCKS+i] : maxEnd;
// }
// printf("Total clocks = %d\n", (int)(maxEnd - minStart));
// // cudaDeviceReset causes the driver to clean up all state. While
// // not mandatory in normal operation, it is good practice. It is also
// // needed to ensure correct operation when the application is being
// // profiled. Calling cudaDeviceReset causes all profile data to be
// // flushed before the application exits
// cudaDeviceReset();
// return EXIT_SUCCESS;
// } | #include <hip/hip_runtime.h>
/*-----------
*
* clock.cu
*
* This is the source file of a kernel to measure time for each block.
*
* This kernel is from CUDA samples. clock.cu
*
* streamsOptBenchmark/clock.cu
*
* By Hao Li
*
*------------
*/
// This kernel computes a standard parallel reduction and evaluates the
// time it takes to do that for each block. The timing results are stored
// in device memory.
__global__ static void clockTimedReduction(const float *input, float *output, clock_t *timer)
{
for(int l = 0; l < 100000; l++)
{
// __shared__ float shared[2 * blockDim.x];
extern __shared__ float shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
if (tid == 0) timer[bid] = clock();
// Copy input.
shared[tid] = input[tid];
shared[tid + blockDim.x] = input[tid + blockDim.x];
// Perform reduction to find minimum.
for (int d = blockDim.x; d > 0; d /= 2)
{
__syncthreads();
if (tid < d)
{
float f0 = shared[tid];
float f1 = shared[tid + d];
if (f1 < f0)
{
shared[tid] = f1;
}
}
}
// Write result.
if (tid == 0) output[bid] = shared[0];
__syncthreads();
if (tid == 0) timer[bid+gridDim.x] = clock();
}
}
// int main(int argc, char **argv)
// {
// printf("CUDA Clock sample\n");
// // This will pick the best possible CUDA capable device
// int dev = findCudaDevice(argc, (const char **)argv);
// float *dinput = NULL;
// float *doutput = NULL;
// clock_t *dtimer = NULL;
// clock_t timer[NUM_BLOCKS * 2];
// float input[NUM_THREADS * 2];
// for (int i = 0; i < NUM_THREADS * 2; i++)
// {
// input[i] = (float)i;
// }
// checkCudaErrors(cudaMalloc((void **)&dinput, sizeof(float) * NUM_THREADS * 2));
// checkCudaErrors(cudaMalloc((void **)&doutput, sizeof(float) * NUM_BLOCKS));
// checkCudaErrors(cudaMalloc((void **)&dtimer, sizeof(clock_t) * NUM_BLOCKS * 2));
// checkCudaErrors(cudaMemcpy(dinput, input, sizeof(float) * NUM_THREADS * 2, cudaMemcpyHostToDevice));
// clockTimedReduction<<<NUM_BLOCKS, NUM_THREADS, sizeof(float) * 2 *NUM_THREADS>>>(dinput, doutput, dtimer);
// checkCudaErrors(cudaMemcpy(timer, dtimer, sizeof(clock_t) * NUM_BLOCKS * 2, cudaMemcpyDeviceToHost));
// checkCudaErrors(cudaFree(dinput));
// checkCudaErrors(cudaFree(doutput));
// checkCudaErrors(cudaFree(dtimer));
// // Compute the difference between the last block end and the first block start.
// clock_t minStart = timer[0];
// clock_t maxEnd = timer[NUM_BLOCKS];
// for (int i = 1; i < NUM_BLOCKS; i++)
// {
// minStart = timer[i] < minStart ? timer[i] : minStart;
// maxEnd = timer[NUM_BLOCKS+i] > maxEnd ? timer[NUM_BLOCKS+i] : maxEnd;
// }
// printf("Total clocks = %d\n", (int)(maxEnd - minStart));
// // cudaDeviceReset causes the driver to clean up all state. While
// // not mandatory in normal operation, it is good practice. It is also
// // needed to ensure correct operation when the application is being
// // profiled. Calling cudaDeviceReset causes all profile data to be
// // flushed before the application exits
// cudaDeviceReset();
// return EXIT_SUCCESS;
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*-----------
*
* clock.cu
*
* This is the source file of a kernel to measure time for each block.
*
* This kernel is from CUDA samples. clock.cu
*
* streamsOptBenchmark/clock.cu
*
* By Hao Li
*
*------------
*/
// This kernel computes a standard parallel reduction and evaluates the
// time it takes to do that for each block. The timing results are stored
// in device memory.
__global__ static void clockTimedReduction(const float *input, float *output, clock_t *timer)
{
for(int l = 0; l < 100000; l++)
{
// __shared__ float shared[2 * blockDim.x];
extern __shared__ float shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
if (tid == 0) timer[bid] = clock();
// Copy input.
shared[tid] = input[tid];
shared[tid + blockDim.x] = input[tid + blockDim.x];
// Perform reduction to find minimum.
for (int d = blockDim.x; d > 0; d /= 2)
{
__syncthreads();
if (tid < d)
{
float f0 = shared[tid];
float f1 = shared[tid + d];
if (f1 < f0)
{
shared[tid] = f1;
}
}
}
// Write result.
if (tid == 0) output[bid] = shared[0];
__syncthreads();
if (tid == 0) timer[bid+gridDim.x] = clock();
}
}
// int main(int argc, char **argv)
// {
// printf("CUDA Clock sample\n");
// // This will pick the best possible CUDA capable device
// int dev = findCudaDevice(argc, (const char **)argv);
// float *dinput = NULL;
// float *doutput = NULL;
// clock_t *dtimer = NULL;
// clock_t timer[NUM_BLOCKS * 2];
// float input[NUM_THREADS * 2];
// for (int i = 0; i < NUM_THREADS * 2; i++)
// {
// input[i] = (float)i;
// }
// checkCudaErrors(cudaMalloc((void **)&dinput, sizeof(float) * NUM_THREADS * 2));
// checkCudaErrors(cudaMalloc((void **)&doutput, sizeof(float) * NUM_BLOCKS));
// checkCudaErrors(cudaMalloc((void **)&dtimer, sizeof(clock_t) * NUM_BLOCKS * 2));
// checkCudaErrors(cudaMemcpy(dinput, input, sizeof(float) * NUM_THREADS * 2, cudaMemcpyHostToDevice));
// clockTimedReduction<<<NUM_BLOCKS, NUM_THREADS, sizeof(float) * 2 *NUM_THREADS>>>(dinput, doutput, dtimer);
// checkCudaErrors(cudaMemcpy(timer, dtimer, sizeof(clock_t) * NUM_BLOCKS * 2, cudaMemcpyDeviceToHost));
// checkCudaErrors(cudaFree(dinput));
// checkCudaErrors(cudaFree(doutput));
// checkCudaErrors(cudaFree(dtimer));
// // Compute the difference between the last block end and the first block start.
// clock_t minStart = timer[0];
// clock_t maxEnd = timer[NUM_BLOCKS];
// for (int i = 1; i < NUM_BLOCKS; i++)
// {
// minStart = timer[i] < minStart ? timer[i] : minStart;
// maxEnd = timer[NUM_BLOCKS+i] > maxEnd ? timer[NUM_BLOCKS+i] : maxEnd;
// }
// printf("Total clocks = %d\n", (int)(maxEnd - minStart));
// // cudaDeviceReset causes the driver to clean up all state. While
// // not mandatory in normal operation, it is good practice. It is also
// // needed to ensure correct operation when the application is being
// // profiled. Calling cudaDeviceReset causes all profile data to be
// // flushed before the application exits
// cudaDeviceReset();
// return EXIT_SUCCESS;
// } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL19clockTimedReductionPKfPfPl,"axG",@progbits,_ZL19clockTimedReductionPKfPfPl,comdat
.globl _ZL19clockTimedReductionPKfPfPl
.p2align 8
.type _ZL19clockTimedReductionPKfPfPl,@function
_ZL19clockTimedReductionPKfPfPl:
s_mov_b32 s12, s15
s_clause 0x3
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x10
s_load_b32 s11, s[0:1], 0x18
v_lshlrev_b32_e32 v1, 2, v0
v_mov_b32_e32 v5, 0
s_mov_b32 s3, 0
v_cmp_eq_u32_e64 s0, 0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v6, 0, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
v_add_co_u32 v1, s2, s4, v1
s_cmp_lg_u32 s1, 0
v_add_lshl_u32 v7, v0, s1, 2
s_cselect_b32 s10, -1, 0
s_ashr_i32 s13, s12, 31
v_add_co_ci_u32_e64 v2, null, s5, 0, s2
s_lshl_b64 s[8:9], s[12:13], 3
v_add_co_u32 v3, s2, s4, v7
s_add_u32 s8, s14, s8
s_addc_u32 s9, s15, s9
s_lshl_b64 s[16:17], s[12:13], 2
v_add_co_ci_u32_e64 v4, null, s5, 0, s2
s_add_u32 s4, s6, s16
s_addc_u32 s5, s7, s17
s_add_i32 s2, s11, s12
v_add_nc_u32_e32 v7, 0, v7
s_lshl_b64 s[6:7], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s14, s6
s_addc_u32 s7, s15, s7
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0x186a0
s_cbranch_scc1 .LBB0_13
.LBB0_2:
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_4
s_getreg_b32 s11, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, s11
global_store_b64 v5, v[8:9], s[8:9]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
global_load_b32 v8, v[1:2], off
global_load_b32 v9, v[3:4], off
s_mov_b32 s2, s1
s_and_not1_b32 vcc_lo, exec_lo, s10
s_waitcnt vmcnt(1)
ds_store_b32 v6, v8
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
s_cbranch_vccz .LBB0_10
.LBB0_5:
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v8, 0
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
global_store_b32 v5, v8, s[4:5]
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_1
s_getreg_b32 s11, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, s11
global_store_b64 v5, v[8:9], s[6:7]
s_branch .LBB0_1
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s11
s_lshr_b32 s11, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s11
s_cbranch_scc1 .LBB0_5
.LBB0_10:
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v8, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v9, v6
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v8, v9
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
ds_store_b32 v6, v8
s_branch .LBB0_9
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL19clockTimedReductionPKfPfPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL19clockTimedReductionPKfPfPl,"axG",@progbits,_ZL19clockTimedReductionPKfPfPl,comdat
.Lfunc_end0:
.size _ZL19clockTimedReductionPKfPfPl, .Lfunc_end0-_ZL19clockTimedReductionPKfPfPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL19clockTimedReductionPKfPfPl
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _ZL19clockTimedReductionPKfPfPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*-----------
*
* clock.cu
*
* This is the source file of a kernel to measure time for each block.
*
* This kernel is from CUDA samples. clock.cu
*
* streamsOptBenchmark/clock.cu
*
* By Hao Li
*
*------------
*/
// This kernel computes a standard parallel reduction and evaluates the
// time it takes to do that for each block. The timing results are stored
// in device memory.
__global__ static void clockTimedReduction(const float *input, float *output, clock_t *timer)
{
for(int l = 0; l < 100000; l++)
{
// __shared__ float shared[2 * blockDim.x];
extern __shared__ float shared[];
const int tid = threadIdx.x;
const int bid = blockIdx.x;
if (tid == 0) timer[bid] = clock();
// Copy input.
shared[tid] = input[tid];
shared[tid + blockDim.x] = input[tid + blockDim.x];
// Perform reduction to find minimum.
for (int d = blockDim.x; d > 0; d /= 2)
{
__syncthreads();
if (tid < d)
{
float f0 = shared[tid];
float f1 = shared[tid + d];
if (f1 < f0)
{
shared[tid] = f1;
}
}
}
// Write result.
if (tid == 0) output[bid] = shared[0];
__syncthreads();
if (tid == 0) timer[bid+gridDim.x] = clock();
}
}
// int main(int argc, char **argv)
// {
// printf("CUDA Clock sample\n");
// // This will pick the best possible CUDA capable device
// int dev = findCudaDevice(argc, (const char **)argv);
// float *dinput = NULL;
// float *doutput = NULL;
// clock_t *dtimer = NULL;
// clock_t timer[NUM_BLOCKS * 2];
// float input[NUM_THREADS * 2];
// for (int i = 0; i < NUM_THREADS * 2; i++)
// {
// input[i] = (float)i;
// }
// checkCudaErrors(cudaMalloc((void **)&dinput, sizeof(float) * NUM_THREADS * 2));
// checkCudaErrors(cudaMalloc((void **)&doutput, sizeof(float) * NUM_BLOCKS));
// checkCudaErrors(cudaMalloc((void **)&dtimer, sizeof(clock_t) * NUM_BLOCKS * 2));
// checkCudaErrors(cudaMemcpy(dinput, input, sizeof(float) * NUM_THREADS * 2, cudaMemcpyHostToDevice));
// clockTimedReduction<<<NUM_BLOCKS, NUM_THREADS, sizeof(float) * 2 *NUM_THREADS>>>(dinput, doutput, dtimer);
// checkCudaErrors(cudaMemcpy(timer, dtimer, sizeof(clock_t) * NUM_BLOCKS * 2, cudaMemcpyDeviceToHost));
// checkCudaErrors(cudaFree(dinput));
// checkCudaErrors(cudaFree(doutput));
// checkCudaErrors(cudaFree(dtimer));
// // Compute the difference between the last block end and the first block start.
// clock_t minStart = timer[0];
// clock_t maxEnd = timer[NUM_BLOCKS];
// for (int i = 1; i < NUM_BLOCKS; i++)
// {
// minStart = timer[i] < minStart ? timer[i] : minStart;
// maxEnd = timer[NUM_BLOCKS+i] > maxEnd ? timer[NUM_BLOCKS+i] : maxEnd;
// }
// printf("Total clocks = %d\n", (int)(maxEnd - minStart));
// // cudaDeviceReset causes the driver to clean up all state. While
// // not mandatory in normal operation, it is good practice. It is also
// // needed to ensure correct operation when the application is being
// // profiled. Calling cudaDeviceReset causes all profile data to be
// // flushed before the application exits
// cudaDeviceReset();
// return EXIT_SUCCESS;
// } | .text
.file "clock.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19clockTimedReductionPKfPfPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0060*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*0070*/ IADD3 R10, R0.reuse, c[0x0][0x0], RZ ; /* 0x00000000000a7a10 */
/* 0x041fe20007ffe0ff */
/*0080*/ IMAD.SHL.U32 R12, R0, 0x4, RZ ; /* 0x00000004000c7824 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020d */
/*00a0*/ IADD3 R8, R4, c[0x0][0xc], RZ ; /* 0x0000030004087a10 */
/* 0x002fc60007ffe0ff */
/*00b0*/ IMAD.WIDE R6, R4, R9, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fc800078e0209 */
/*00c0*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020d */
/*00d0*/ IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e000d */
/*00e0*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc800078e0009 */
/*00f0*/ IMAD R13, R13, c[0x0][0x0], R12 ; /* 0x000000000d0d7a24 */
/* 0x000fe400078e020c */
/*0100*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R18, 0x186a0, PT ; /* 0x000186a01200780c */
/* 0x001fd60003f26070 */
/*0130*/ @!P0 CS2R R14, SR_CLOCKLO ; /* 0x00000000000e8805 */
/* 0x000fca0000015000 */
/*0140*/ @!P0 STG.E.64 [R6.64], R14 ; /* 0x0000000e06008986 */
/* 0x0001e8000c101b04 */
/*0150*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee2000c1e1900 */
/*0170*/ MOV R19, c[0x0][0x0] ; /* 0x0000000000137a02 */
/* 0x000fc80000000f00 */
/*0180*/ ISETP.GE.AND P2, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe20003f46270 */
/*0190*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0041e80000004800 */
/*01a0*/ STS [R13], R16 ; /* 0x000000100d007388 */
/* 0x0081f00000000800 */
/*01b0*/ @!P2 BRA 0x2a0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0f7624 */
/* 0x001fc800078e00ff */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ ISETP.GE.AND P2, PT, R0, R15, PT ; /* 0x0000000f0000720c */
/* 0x000fca0003f46270 */
/*01f0*/ BSSY B0, 0x270 ; /* 0x0000007000007945 */
/* 0x000ff00003800000 */
/*0200*/ @P2 BRA 0x260 ; /* 0x0000005000002947 */
/* 0x001fea0003800000 */
/*0210*/ LEA R16, R15, R12, 0x2 ; /* 0x0000000c0f107211 */
/* 0x000fe200078e10ff */
/*0220*/ LDS R14, [R0.X4] ; /* 0x00000000000e7984 */
/* 0x000fe80000004800 */
/*0230*/ LDS R17, [R16] ; /* 0x0000000010117984 */
/* 0x000e240000000800 */
/*0240*/ FSETP.GEU.AND P2, PT, R17, R14, PT ; /* 0x0000000e1100720b */
/* 0x001fda0003f4e000 */
/*0250*/ @!P2 STS [R0.X4], R17 ; /* 0x000000110000a388 */
/* 0x0001e40000004800 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ SHF.R.U32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f7819 */
/* 0x000fc8000001160f */
/*0280*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fda0003f45270 */
/*0290*/ @P2 BRA 0x1d0 ; /* 0xffffff3000002947 */
/* 0x000fea000383ffff */
/*02a0*/ @!P0 LDS R15, [RZ] ; /* 0x00000000ff0f8984 */
/* 0x001e220000000800 */
/*02b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe60003800000 */
/*02c0*/ @!P0 STG.E [R4.64], R15 ; /* 0x0000000f04008986 */
/* 0x0011e8000c101904 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02e0*/ @!P0 CS2R R14, SR_CLOCKLO ; /* 0x00000000000e8805 */
/* 0x001fca0000015000 */
/*02f0*/ @!P0 STG.E.64 [R8.64], R14 ; /* 0x0000000e08008986 */
/* 0x0001e2000c101b04 */
/*0300*/ @!P1 BRA 0x100 ; /* 0xfffffdf000009947 */
/* 0x000fea000383ffff */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL19clockTimedReductionPKfPfPl,"axG",@progbits,_ZL19clockTimedReductionPKfPfPl,comdat
.globl _ZL19clockTimedReductionPKfPfPl
.p2align 8
.type _ZL19clockTimedReductionPKfPfPl,@function
_ZL19clockTimedReductionPKfPfPl:
s_mov_b32 s12, s15
s_clause 0x3
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x10
s_load_b32 s11, s[0:1], 0x18
v_lshlrev_b32_e32 v1, 2, v0
v_mov_b32_e32 v5, 0
s_mov_b32 s3, 0
v_cmp_eq_u32_e64 s0, 0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v6, 0, v1
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s2, 0xffff
v_add_co_u32 v1, s2, s4, v1
s_cmp_lg_u32 s1, 0
v_add_lshl_u32 v7, v0, s1, 2
s_cselect_b32 s10, -1, 0
s_ashr_i32 s13, s12, 31
v_add_co_ci_u32_e64 v2, null, s5, 0, s2
s_lshl_b64 s[8:9], s[12:13], 3
v_add_co_u32 v3, s2, s4, v7
s_add_u32 s8, s14, s8
s_addc_u32 s9, s15, s9
s_lshl_b64 s[16:17], s[12:13], 2
v_add_co_ci_u32_e64 v4, null, s5, 0, s2
s_add_u32 s4, s6, s16
s_addc_u32 s5, s7, s17
s_add_i32 s2, s11, s12
v_add_nc_u32_e32 v7, 0, v7
s_lshl_b64 s[6:7], s[2:3], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s14, s6
s_addc_u32 s7, s15, s7
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0x186a0
s_cbranch_scc1 .LBB0_13
.LBB0_2:
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_4
s_getreg_b32 s11, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, s11
global_store_b64 v5, v[8:9], s[8:9]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_clause 0x1
global_load_b32 v8, v[1:2], off
global_load_b32 v9, v[3:4], off
s_mov_b32 s2, s1
s_and_not1_b32 vcc_lo, exec_lo, s10
s_waitcnt vmcnt(1)
ds_store_b32 v6, v8
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
s_cbranch_vccz .LBB0_10
.LBB0_5:
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v8, 0
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
global_store_b32 v5, v8, s[4:5]
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_1
s_getreg_b32 s11, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, s11
global_store_b64 v5, v[8:9], s[6:7]
s_branch .LBB0_1
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s11
s_lshr_b32 s11, s2, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s11
s_cbranch_scc1 .LBB0_5
.LBB0_10:
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v8, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v9, v6
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v8, v9
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_9
ds_store_b32 v6, v8
s_branch .LBB0_9
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL19clockTimedReductionPKfPfPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL19clockTimedReductionPKfPfPl,"axG",@progbits,_ZL19clockTimedReductionPKfPfPl,comdat
.Lfunc_end0:
.size _ZL19clockTimedReductionPKfPfPl, .Lfunc_end0-_ZL19clockTimedReductionPKfPfPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL19clockTimedReductionPKfPfPl
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _ZL19clockTimedReductionPKfPfPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000760cf_00000000-6_clock.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL19clockTimedReductionPKfPfPl, @function
_ZL19clockTimedReductionPKfPfPl:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL19clockTimedReductionPKfPfPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL19clockTimedReductionPKfPfPl, .-_ZL19clockTimedReductionPKfPfPl
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19clockTimedReductionPKfPfPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19clockTimedReductionPKfPfPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "clock.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void meanMatrix(double *dMatrix, double *dMean, int dSize, int *d_mutex){
__shared__ double cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
double temp = 0;
while (tid < dSize) {
temp += dMatrix[tid];
tid += blockDim.x * gridDim.x;
}
// set the cache values
cache[cacheIndex] = temp;
// synchronize threads in this block
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if(cacheIndex == 0){
while(atomicCAS(d_mutex,0,1) != 0); //lock
*dMean += cache[0];
atomicExch(d_mutex, 0); //unlock
*dMean = dMean[0]/dSize;
}
} | code for sm_80
Function : _Z10meanMatrixPdS_iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0040*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0209 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0090*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x001fc800078e00ff */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0205 */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x0060580000000002 */
/*0110*/ @!P0 BRA 0xa0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0140*/ STS.64 [R9.X8], R2 ; /* 0x0000000209007388 */
/* 0x0023e20000008a00 */
/*0150*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0180*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0190*/ @!P1 BRA 0x280 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.SHL.U32 R0, R9, 0x8, RZ ; /* 0x0000000809007824 */
/* 0x002fe400078e00ff */
/*01b0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fca000f8e00ff */
/*01c0*/ ISETP.GE.AND P1, PT, R9, R7, PT ; /* 0x000000070900720c */
/* 0x000fda0003f26270 */
/*01d0*/ @!P1 IMAD R4, R7.reuse, 0x8, R0 ; /* 0x0000000807049824 */
/* 0x041fe200078e0200 */
/*01e0*/ @!P1 LDS.64 R2, [R9.X8] ; /* 0x0000000009029984 */
/* 0x000fea0000008a00 */
/*01f0*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0200*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x0010640000000004 */
/*0210*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x001fc40007ffe0ff */
/*0220*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc600078f08ff */
/*0230*/ @!P1 STS.64 [R9.X8], R2 ; /* 0x0000000209009388 */
/* 0x0021e80000008a00 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0260*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fd60000011407 */
/*0270*/ @P1 BRA 0x1c0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x002fea0003800000 */
/*0290*/ BSSY B0, 0x330 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x001fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*02e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*02f0*/ ATOMG.E.CAS.STRONG.GPU PT, R0, [R4], R2, R3 ; /* 0x00000002040073a9 */
/* 0x000ea400001ee103 */
/*0300*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0310*/ @P0 BRA 0x2d0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0340*/ LDS.64 R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x000e220000000a00 */
/*0350*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0360*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000e22000c1e1b00 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*0380*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x001e0e0000000008 */
/*0390*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b06 */
/*03a0*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R4.64], RZ ; /* 0x000000ff04ff79a8 */
/* 0x000368000c1ee1c6 */
/*03b0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000e22000c1e1b00 */
/*03c0*/ I2F.F64 R8, c[0x0][0x170] ; /* 0x00005c0000087b12 */
/* 0x000eb00000201c00 */
/*03d0*/ MUFU.RCP64H R13, R9 ; /* 0x00000009000d7308 */
/* 0x004ea40000001800 */
/*03e0*/ DFMA R14, -R8, R12, 1 ; /* 0x3ff00000080e742b */
/* 0x004e8c000000010c */
/*03f0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x004e8c000000000e */
/*0400*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x004e8c000000000c */
/*0410*/ DFMA R12, -R8, R14, 1 ; /* 0x3ff00000080c742b */
/* 0x004e8c000000010e */
/*0420*/ DFMA R12, R14, R12, R14 ; /* 0x0000000c0e0c722b */
/* 0x004e0c000000000e */
/*0430*/ DMUL R10, R6, R12 ; /* 0x0000000c060a7228 */
/* 0x001e620000000000 */
/*0440*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0450*/ DFMA R4, -R8, R10, R6 ; /* 0x0000000a0804722b */
/* 0x002e0c0000000106 */
/*0460*/ DFMA R4, R12, R4, R10 ; /* 0x000000040c04722b */
/* 0x001e14000000000a */
/*0470*/ FFMA R0, RZ, R9, R5 ; /* 0x00000009ff007223 */
/* 0x001fca0000000005 */
/*0480*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0490*/ @P0 BRA P1, 0x4e0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*04a0*/ MOV R0, 0x4c0 ; /* 0x000004c000007802 */
/* 0x000fe40000000f00 */
/*04b0*/ CALL.REL.NOINC 0x500 ; /* 0x0000004000007944 */
/* 0x020fea0003c00000 */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000f */
/*04e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0510*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0520*/ LOP3.LUT R4, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x040fe200078ec0ff */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0f7424 */
/* 0x000fe200078e00ff */
/*0540*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x000fe400078ec0ff */
/*0550*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0560*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0570*/ LOP3.LUT R14, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070e7812 */
/* 0x000fc800078ec0ff */
/*0580*/ ISETP.GE.U32.AND P1, PT, R14, R16, PT ; /* 0x000000100e00720c */
/* 0x000fe20003f26070 */
/*0590*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e060000000000 */
/*05a0*/ SEL R17, R15, 0x63400000, !P1 ; /* 0x634000000f117807 */
/* 0x000fe40004800000 */
/*05b0*/ FSETP.GEU.AND P1, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x000fe20003f2e200 */
/*05c0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x001e280000001800 */
/*05d0*/ @!P0 LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005108812 */
/* 0x000fe200078ec0ff */
/*05e0*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000804 */
/*05f0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0600*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0610*/ DFMA R10, R12, -R4, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000804 */
/*0620*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*0630*/ LOP3.LUT R11, R17, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff110b7812 */
/* 0x001fe200078ef807 */
/*0640*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000e */
/*0650*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0660*/ @P1 BRA 0x6f0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0670*/ LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009117812 */
/* 0x002fe200078ec0ff */
/*0680*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R14, R17, PT ; /* 0x000000110e00720c */
/* 0x000fc80003f06070 */
/*06a0*/ SEL R17, R15, 0x63400000, !P0 ; /* 0x634000000f117807 */
/* 0x000fc80004000000 */
/*06b0*/ LOP3.LUT R17, R17, 0x80000000, R7, 0xf8, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ef807 */
/*06c0*/ LOP3.LUT R19, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000011137812 */
/* 0x000fcc00078efcff */
/*06d0*/ DFMA R10, R10, 2, -R18 ; /* 0x400000000a0a782b */
/* 0x000e140000000812 */
/*06e0*/ LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b117812 */
/* 0x001fc800078ec0ff */
/*06f0*/ IADD3 R20, R17, -0x1, RZ ; /* 0xffffffff11147810 */
/* 0x002fe20007ffe0ff */
/*0700*/ DMUL R18, R12, R10 ; /* 0x0000000a0c127228 */
/* 0x000e220000000000 */
/*0710*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0730*/ DFMA R20, R18, -R4, R10 ; /* 0x800000041214722b */
/* 0x001e22000000000a */
/*0740*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0750*/ DFMA R12, R12, R20, R18 ; /* 0x000000140c0c722b */
/* 0x0010500000000012 */
/*0760*/ @P0 BRA 0x930 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0770*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*0780*/ ISETP.GE.U32.AND P0, PT, R14.reuse, R7, PT ; /* 0x000000070e00720c */
/* 0x040fe20003f06070 */
/*0790*/ IMAD.IADD R6, R14, 0x1, -R7 ; /* 0x000000010e067824 */
/* 0x000fc600078e0a07 */
/*07a0*/ SEL R15, R15, 0x63400000, !P0 ; /* 0x634000000f0f7807 */
/* 0x000fe40004000000 */
/*07b0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*07c0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*07d0*/ IMAD.IADD R16, R6, 0x1, -R15 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0f */
/*07e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*07f0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0800*/ DMUL R14, R12, R6 ; /* 0x000000060c0e7228 */
/* 0x000e140000000000 */
/*0810*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0820*/ @P0 BRA 0xa80 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0830*/ DFMA R4, R12, -R4, R10 ; /* 0x800000040c04722b */
/* 0x000e22000000000a */
/*0840*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0850*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0860*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0870*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0880*/ @!P0 BRA 0xa80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*08a0*/ DMUL.RP R6, R12, R6 ; /* 0x000000060c067228 */
/* 0x000e220000008000 */
/*08b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*08c0*/ DFMA R4, R14, -R4, R12 ; /* 0x800000040e04722b */
/* 0x000e46000000000c */
/*08d0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*08e0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*08f0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0900*/ FSEL R14, R6, R14, !P0 ; /* 0x0000000e060e7208 */
/* 0x000fe40004000000 */
/*0910*/ FSEL R15, R9, R15, !P0 ; /* 0x0000000f090f7208 */
/* 0x000fe20004000000 */
/*0920*/ BRA 0xa80 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0930*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0940*/ @P0 BRA 0xa60 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0950*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0960*/ @P0 BRA 0xa30 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0970*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0980*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0990*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*09a0*/ @!P0 BRA 0xa80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*09c0*/ LOP3.LUT R15, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070f7812 */
/* 0x000fe400078e4809 */
/*09d0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*09e0*/ @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f040812 */
/* 0x000fe200078efcff */
/*09f0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*0a00*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0a10*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0004 */
/*0a20*/ BRA 0xa80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a30*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0a40*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0a50*/ BRA 0xa80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT R15, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070f7812 */
/* 0x000fe200078efcff */
/*0a70*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0006 */
/*0a80*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0aa0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff55004007950 */
/* 0x000fea0003c3ffff */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void meanMatrix(double *dMatrix, double *dMean, int dSize, int *d_mutex){
__shared__ double cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
double temp = 0;
while (tid < dSize) {
temp += dMatrix[tid];
tid += blockDim.x * gridDim.x;
}
// set the cache values
cache[cacheIndex] = temp;
// synchronize threads in this block
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if(cacheIndex == 0){
while(atomicCAS(d_mutex,0,1) != 0); //lock
*dMean += cache[0];
atomicExch(d_mutex, 0); //unlock
*dMean = dMean[0]/dSize;
}
} | .file "tmpxft_001485a7_00000000-6_meanMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi
.type _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi, @function
_Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10meanMatrixPdS_iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi, .-_Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi
.globl _Z10meanMatrixPdS_iPi
.type _Z10meanMatrixPdS_iPi, @function
_Z10meanMatrixPdS_iPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10meanMatrixPdS_iPi, .-_Z10meanMatrixPdS_iPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10meanMatrixPdS_iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10meanMatrixPdS_iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void meanMatrix(double *dMatrix, double *dMean, int dSize, int *d_mutex){
__shared__ double cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
double temp = 0;
while (tid < dSize) {
temp += dMatrix[tid];
tid += blockDim.x * gridDim.x;
}
// set the cache values
cache[cacheIndex] = temp;
// synchronize threads in this block
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if(cacheIndex == 0){
while(atomicCAS(d_mutex,0,1) != 0); //lock
*dMean += cache[0];
atomicExch(d_mutex, 0); //unlock
*dMean = dMean[0]/dSize;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void meanMatrix(double *dMatrix, double *dMean, int dSize, int *d_mutex){
__shared__ double cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
double temp = 0;
while (tid < dSize) {
temp += dMatrix[tid];
tid += blockDim.x * gridDim.x;
}
// set the cache values
cache[cacheIndex] = temp;
// synchronize threads in this block
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if(cacheIndex == 0){
while(atomicCAS(d_mutex,0,1) != 0); //lock
*dMean += cache[0];
atomicExch(d_mutex, 0); //unlock
*dMean = dMean[0]/dSize;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void meanMatrix(double *dMatrix, double *dMean, int dSize, int *d_mutex){
__shared__ double cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
double temp = 0;
while (tid < dSize) {
temp += dMatrix[tid];
tid += blockDim.x * gridDim.x;
}
// set the cache values
cache[cacheIndex] = temp;
// synchronize threads in this block
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if(cacheIndex == 0){
while(atomicCAS(d_mutex,0,1) != 0); //lock
*dMean += cache[0];
atomicExch(d_mutex, 0); //unlock
*dMean = dMean[0]/dSize;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10meanMatrixPdS_iPi
.globl _Z10meanMatrixPdS_iPi
.p2align 8
.type _Z10meanMatrixPdS_iPi,@function
_Z10meanMatrixPdS_iPi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_cmpx_gt_i32_e64 s4, v3
s_cbranch_execz .LBB0_4
s_load_b32 s8, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s5
.LBB0_2:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[3:4]
v_add_nc_u32_e32 v3, s8, v3
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s4, v3
global_load_b64 v[4:5], v[4:5], off
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
v_add_f64 v[1:2], v[1:2], v[4:5]
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v3, 3, v0
s_cmp_lt_u32 s5, 2
ds_store_b64 v3, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_11
.LBB0_5:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x18
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_7:
s_waitcnt lgkmcnt(0)
global_atomic_cmpswap_b32 v3, v2, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v12, 0
ds_load_b64 v[2:3], v12
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v12, s[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
v_cvt_f64_i32_e32 v[2:3], s4
global_store_b64 v12, v[0:1], s[0:1]
global_atomic_swap_b32 v12, v12, s[2:3]
global_load_b64 v[0:1], v12, s[0:1]
s_waitcnt vmcnt(0)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
global_store_b64 v12, v[0:1], s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_gt_u32 s5, 3
s_mov_b32 s5, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_11:
s_lshr_b32 s2, s5, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_10
v_add_lshl_u32 v1, s2, v0, 3
ds_load_b64 v[1:2], v1
ds_load_b64 v[4:5], v3
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[4:5]
ds_store_b64 v3, v[1:2]
s_branch .LBB0_10
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10meanMatrixPdS_iPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10meanMatrixPdS_iPi, .Lfunc_end0-_Z10meanMatrixPdS_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10meanMatrixPdS_iPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10meanMatrixPdS_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void meanMatrix(double *dMatrix, double *dMean, int dSize, int *d_mutex){
__shared__ double cache[threadsPerBlock];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int cacheIndex = threadIdx.x;
double temp = 0;
while (tid < dSize) {
temp += dMatrix[tid];
tid += blockDim.x * gridDim.x;
}
// set the cache values
cache[cacheIndex] = temp;
// synchronize threads in this block
__syncthreads();
int i = blockDim.x/2;
while (i != 0) {
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if(cacheIndex == 0){
while(atomicCAS(d_mutex,0,1) != 0); //lock
*dMean += cache[0];
atomicExch(d_mutex, 0); //unlock
*dMean = dMean[0]/dSize;
}
} | .text
.file "meanMatrix.hip"
.globl _Z25__device_stub__meanMatrixPdS_iPi # -- Begin function _Z25__device_stub__meanMatrixPdS_iPi
.p2align 4, 0x90
.type _Z25__device_stub__meanMatrixPdS_iPi,@function
_Z25__device_stub__meanMatrixPdS_iPi: # @_Z25__device_stub__meanMatrixPdS_iPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10meanMatrixPdS_iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__meanMatrixPdS_iPi, .Lfunc_end0-_Z25__device_stub__meanMatrixPdS_iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10meanMatrixPdS_iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10meanMatrixPdS_iPi,@object # @_Z10meanMatrixPdS_iPi
.section .rodata,"a",@progbits
.globl _Z10meanMatrixPdS_iPi
.p2align 3, 0x0
_Z10meanMatrixPdS_iPi:
.quad _Z25__device_stub__meanMatrixPdS_iPi
.size _Z10meanMatrixPdS_iPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10meanMatrixPdS_iPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__meanMatrixPdS_iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10meanMatrixPdS_iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10meanMatrixPdS_iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0040*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0209 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x120 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0090*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x001fc800078e00ff */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0205 */
/*00c0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x0060580000000002 */
/*0110*/ @!P0 BRA 0xa0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0140*/ STS.64 [R9.X8], R2 ; /* 0x0000000209007388 */
/* 0x0023e20000008a00 */
/*0150*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0180*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0190*/ @!P1 BRA 0x280 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.SHL.U32 R0, R9, 0x8, RZ ; /* 0x0000000809007824 */
/* 0x002fe400078e00ff */
/*01b0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fca000f8e00ff */
/*01c0*/ ISETP.GE.AND P1, PT, R9, R7, PT ; /* 0x000000070900720c */
/* 0x000fda0003f26270 */
/*01d0*/ @!P1 IMAD R4, R7.reuse, 0x8, R0 ; /* 0x0000000807049824 */
/* 0x041fe200078e0200 */
/*01e0*/ @!P1 LDS.64 R2, [R9.X8] ; /* 0x0000000009029984 */
/* 0x000fea0000008a00 */
/*01f0*/ @!P1 LDS.64 R4, [R4] ; /* 0x0000000004049984 */
/* 0x000e240000000a00 */
/*0200*/ @!P1 DADD R2, R2, R4 ; /* 0x0000000002029229 */
/* 0x0010640000000004 */
/*0210*/ IADD3 R5, R7, 0x1, RZ ; /* 0x0000000107057810 */
/* 0x001fc40007ffe0ff */
/*0220*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc600078f08ff */
/*0230*/ @!P1 STS.64 [R9.X8], R2 ; /* 0x0000000209009388 */
/* 0x0021e80000008a00 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0260*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fd60000011407 */
/*0270*/ @P1 BRA 0x1c0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x002fea0003800000 */
/*0290*/ BSSY B0, 0x330 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x001fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*02e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*02f0*/ ATOMG.E.CAS.STRONG.GPU PT, R0, [R4], R2, R3 ; /* 0x00000002040073a9 */
/* 0x000ea400001ee103 */
/*0300*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0310*/ @P0 BRA 0x2d0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0340*/ LDS.64 R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x000e220000000a00 */
/*0350*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fca00078e00ff */
/*0360*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000e22000c1e1b00 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1 ; /* 0x00000001ff0c7424 */
/* 0x000fe200078e00ff */
/*0380*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x001e0e0000000008 */
/*0390*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0011e8000c101b06 */
/*03a0*/ ATOMG.E.EXCH.STRONG.GPU PT, RZ, [R4.64], RZ ; /* 0x000000ff04ff79a8 */
/* 0x000368000c1ee1c6 */
/*03b0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000e22000c1e1b00 */
/*03c0*/ I2F.F64 R8, c[0x0][0x170] ; /* 0x00005c0000087b12 */
/* 0x000eb00000201c00 */
/*03d0*/ MUFU.RCP64H R13, R9 ; /* 0x00000009000d7308 */
/* 0x004ea40000001800 */
/*03e0*/ DFMA R14, -R8, R12, 1 ; /* 0x3ff00000080e742b */
/* 0x004e8c000000010c */
/*03f0*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x004e8c000000000e */
/*0400*/ DFMA R14, R12, R14, R12 ; /* 0x0000000e0c0e722b */
/* 0x004e8c000000000c */
/*0410*/ DFMA R12, -R8, R14, 1 ; /* 0x3ff00000080c742b */
/* 0x004e8c000000010e */
/*0420*/ DFMA R12, R14, R12, R14 ; /* 0x0000000c0e0c722b */
/* 0x004e0c000000000e */
/*0430*/ DMUL R10, R6, R12 ; /* 0x0000000c060a7228 */
/* 0x001e620000000000 */
/*0440*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fca0003f2e200 */
/*0450*/ DFMA R4, -R8, R10, R6 ; /* 0x0000000a0804722b */
/* 0x002e0c0000000106 */
/*0460*/ DFMA R4, R12, R4, R10 ; /* 0x000000040c04722b */
/* 0x001e14000000000a */
/*0470*/ FFMA R0, RZ, R9, R5 ; /* 0x00000009ff007223 */
/* 0x001fca0000000005 */
/*0480*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0490*/ @P0 BRA P1, 0x4e0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*04a0*/ MOV R0, 0x4c0 ; /* 0x000004c000007802 */
/* 0x000fe40000000f00 */
/*04b0*/ CALL.REL.NOINC 0x500 ; /* 0x0000004000007944 */
/* 0x020fea0003c00000 */
/*04c0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fca00078e000f */
/*04e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b06 */
/*04f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0500*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0510*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0520*/ LOP3.LUT R4, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x040fe200078ec0ff */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0f7424 */
/* 0x000fe200078e00ff */
/*0540*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x000fe400078ec0ff */
/*0550*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0560*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0570*/ LOP3.LUT R14, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070e7812 */
/* 0x000fc800078ec0ff */
/*0580*/ ISETP.GE.U32.AND P1, PT, R14, R16, PT ; /* 0x000000100e00720c */
/* 0x000fe20003f26070 */
/*0590*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e060000000000 */
/*05a0*/ SEL R17, R15, 0x63400000, !P1 ; /* 0x634000000f117807 */
/* 0x000fe40004800000 */
/*05b0*/ FSETP.GEU.AND P1, PT, |R7|, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x000fe20003f2e200 */
/*05c0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x001e280000001800 */
/*05d0*/ @!P0 LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005108812 */
/* 0x000fe200078ec0ff */
/*05e0*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000804 */
/*05f0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0600*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x001e0c000000000a */
/*0610*/ DFMA R10, R12, -R4, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e0c0000000804 */
/*0620*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*0630*/ LOP3.LUT R11, R17, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff110b7812 */
/* 0x001fe200078ef807 */
/*0640*/ IMAD.MOV.U32 R17, RZ, RZ, R14 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000e */
/*0650*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*0660*/ @P1 BRA 0x6f0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0670*/ LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009117812 */
/* 0x002fe200078ec0ff */
/*0680*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R14, R17, PT ; /* 0x000000110e00720c */
/* 0x000fc80003f06070 */
/*06a0*/ SEL R17, R15, 0x63400000, !P0 ; /* 0x634000000f117807 */
/* 0x000fc80004000000 */
/*06b0*/ LOP3.LUT R17, R17, 0x80000000, R7, 0xf8, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ef807 */
/*06c0*/ LOP3.LUT R19, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000011137812 */
/* 0x000fcc00078efcff */
/*06d0*/ DFMA R10, R10, 2, -R18 ; /* 0x400000000a0a782b */
/* 0x000e140000000812 */
/*06e0*/ LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b117812 */
/* 0x001fc800078ec0ff */
/*06f0*/ IADD3 R20, R17, -0x1, RZ ; /* 0xffffffff11147810 */
/* 0x002fe20007ffe0ff */
/*0700*/ DMUL R18, R12, R10 ; /* 0x0000000a0c127228 */
/* 0x000e220000000000 */
/*0710*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0730*/ DFMA R20, R18, -R4, R10 ; /* 0x800000041214722b */
/* 0x001e22000000000a */
/*0740*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0750*/ DFMA R12, R12, R20, R18 ; /* 0x000000140c0c722b */
/* 0x0010500000000012 */
/*0760*/ @P0 BRA 0x930 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0770*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x003fc800078ec0ff */
/*0780*/ ISETP.GE.U32.AND P0, PT, R14.reuse, R7, PT ; /* 0x000000070e00720c */
/* 0x040fe20003f06070 */
/*0790*/ IMAD.IADD R6, R14, 0x1, -R7 ; /* 0x000000010e067824 */
/* 0x000fc600078e0a07 */
/*07a0*/ SEL R15, R15, 0x63400000, !P0 ; /* 0x634000000f0f7807 */
/* 0x000fe40004000000 */
/*07b0*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*07c0*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*07d0*/ IMAD.IADD R16, R6, 0x1, -R15 ; /* 0x0000000106107824 */
/* 0x000fe400078e0a0f */
/*07e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*07f0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0800*/ DMUL R14, R12, R6 ; /* 0x000000060c0e7228 */
/* 0x000e140000000000 */
/*0810*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0820*/ @P0 BRA 0xa80 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0830*/ DFMA R4, R12, -R4, R10 ; /* 0x800000040c04722b */
/* 0x000e22000000000a */
/*0840*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0850*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0860*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0870*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fce00078efcff */
/*0880*/ @!P0 BRA 0xa80 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0890*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*08a0*/ DMUL.RP R6, R12, R6 ; /* 0x000000060c067228 */
/* 0x000e220000008000 */
/*08b0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*08c0*/ DFMA R4, R14, -R4, R12 ; /* 0x800000040e04722b */
/* 0x000e46000000000c */
/*08d0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*08e0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*08f0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0900*/ FSEL R14, R6, R14, !P0 ; /* 0x0000000e060e7208 */
/* 0x000fe40004000000 */
/*0910*/ FSEL R15, R9, R15, !P0 ; /* 0x0000000f090f7208 */
/* 0x000fe20004000000 */
/*0920*/ BRA 0xa80 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0930*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0940*/ @P0 BRA 0xa60 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0950*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0960*/ @P0 BRA 0xa30 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0970*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0980*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0990*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*09a0*/ @!P0 BRA 0xa80 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09b0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*09c0*/ LOP3.LUT R15, R7, 0x80000000, R9, 0x48, !PT ; /* 0x80000000070f7812 */
/* 0x000fe400078e4809 */
/*09d0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*09e0*/ @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f040812 */
/* 0x000fe200078efcff */
/*09f0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*0a00*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0a10*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0004 */
/*0a20*/ BRA 0xa80 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a30*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0a40*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0a50*/ BRA 0xa80 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0a60*/ LOP3.LUT R15, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070f7812 */
/* 0x000fe200078efcff */
/*0a70*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0006 */
/*0a80*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0a90*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0aa0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff55004007950 */
/* 0x000fea0003c3ffff */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10meanMatrixPdS_iPi
.globl _Z10meanMatrixPdS_iPi
.p2align 8
.type _Z10meanMatrixPdS_iPi,@function
_Z10meanMatrixPdS_iPi:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_cmpx_gt_i32_e64 s4, v3
s_cbranch_execz .LBB0_4
s_load_b32 s8, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s5
.LBB0_2:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[3:4]
v_add_nc_u32_e32 v3, s8, v3
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s4, v3
global_load_b64 v[4:5], v[4:5], off
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
v_add_f64 v[1:2], v[1:2], v[4:5]
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s7
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v3, 3, v0
s_cmp_lt_u32 s5, 2
ds_store_b64 v3, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_11
.LBB0_5:
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x18
v_dual_mov_b32 v0, 1 :: v_dual_mov_b32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_7:
s_waitcnt lgkmcnt(0)
global_atomic_cmpswap_b32 v3, v2, v[0:1], s[2:3] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v12, 0
ds_load_b64 v[2:3], v12
s_waitcnt lgkmcnt(0)
global_load_b64 v[0:1], v12, s[0:1]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
v_cvt_f64_i32_e32 v[2:3], s4
global_store_b64 v12, v[0:1], s[0:1]
global_atomic_swap_b32 v12, v12, s[2:3]
global_load_b64 v[0:1], v12, s[0:1]
s_waitcnt vmcnt(0)
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_div_fixup_f64 v[0:1], v[4:5], v[2:3], v[0:1]
global_store_b64 v12, v[0:1], s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_gt_u32 s5, 3
s_mov_b32 s5, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_11:
s_lshr_b32 s2, s5, 1
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_10
v_add_lshl_u32 v1, s2, v0, 3
ds_load_b64 v[1:2], v1
ds_load_b64 v[4:5], v3
s_waitcnt lgkmcnt(0)
v_add_f64 v[1:2], v[1:2], v[4:5]
ds_store_b64 v3, v[1:2]
s_branch .LBB0_10
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10meanMatrixPdS_iPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10meanMatrixPdS_iPi, .Lfunc_end0-_Z10meanMatrixPdS_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10meanMatrixPdS_iPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10meanMatrixPdS_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001485a7_00000000-6_meanMatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi
.type _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi, @function
_Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10meanMatrixPdS_iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi, .-_Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi
.globl _Z10meanMatrixPdS_iPi
.type _Z10meanMatrixPdS_iPi, @function
_Z10meanMatrixPdS_iPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10meanMatrixPdS_iPiPdS_iPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10meanMatrixPdS_iPi, .-_Z10meanMatrixPdS_iPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10meanMatrixPdS_iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10meanMatrixPdS_iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "meanMatrix.hip"
.globl _Z25__device_stub__meanMatrixPdS_iPi # -- Begin function _Z25__device_stub__meanMatrixPdS_iPi
.p2align 4, 0x90
.type _Z25__device_stub__meanMatrixPdS_iPi,@function
_Z25__device_stub__meanMatrixPdS_iPi: # @_Z25__device_stub__meanMatrixPdS_iPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10meanMatrixPdS_iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__meanMatrixPdS_iPi, .Lfunc_end0-_Z25__device_stub__meanMatrixPdS_iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10meanMatrixPdS_iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10meanMatrixPdS_iPi,@object # @_Z10meanMatrixPdS_iPi
.section .rodata,"a",@progbits
.globl _Z10meanMatrixPdS_iPi
.p2align 3, 0x0
_Z10meanMatrixPdS_iPi:
.quad _Z25__device_stub__meanMatrixPdS_iPi
.size _Z10meanMatrixPdS_iPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10meanMatrixPdS_iPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__meanMatrixPdS_iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10meanMatrixPdS_iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <curand.h>
#include <curand_kernel.h>
#define TPB 512
/** Need to use this function instead of atomicAdd for double precision. Computation done in single precision(float) for now**/
__device__ double atomicAdd_double(double* address, double val)
{
unsigned long long int* address_as_ull =
(unsigned long long int*)address;
unsigned long long int old = *address_as_ull, assumed;
do {
assumed = old;
old = atomicCAS(address_as_ull, assumed,
__double_as_longlong(val +
__longlong_as_double(assumed)));
} while (assumed != old);
return __longlong_as_double(old);
}
__global__ void trap(float *out, int N) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
temp[threadIdx.x] = sin(M_PI*(float)index/((float)N-1));
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/(N-1);
atomicAdd(out, sum);
}
return;
}
__global__ void mc(float *out, int N, int seed) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
curandState_t state;
curand_init(blockIdx.x + seed,
threadIdx.x,
0,
&state);
temp[threadIdx.x] = sin(curand_uniform(&state)*M_PI);
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/N;
atomicAdd(out, sum);
}
return;
}
int main(int argc, char** argv){
int num_points = atoi(argv[2]);
int num_blocks = (num_points+TPB-1)/TPB;
if(argv[1][0]=='T'){
clock_t begin = clock();
float* integral;
float* d_integral;
cudaMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
trap<<<num_blocks,TPB>>>(d_integral, num_points);
cudaMemcpy(integral, d_integral, sizeof(float), cudaMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
cudaFree(d_integral);
}
else if(argv[1][0]=='M'){
clock_t begin = clock();
float* integral;
float* d_integral;
cudaMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
mc<<<num_blocks,TPB>>>(d_integral, num_points, time(NULL));
cudaMemcpy(integral, d_integral, sizeof(float), cudaMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
cudaFree(d_integral);
}
return 0;
} | .file "tmpxft_000ff7e3_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16atomicAdd_doublePdd
.type _Z16atomicAdd_doublePdd, @function
_Z16atomicAdd_doublePdd:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z16atomicAdd_doublePdd, .-_Z16atomicAdd_doublePdd
.globl _Z24__device_stub__Z4trapPfiPfi
.type _Z24__device_stub__Z4trapPfiPfi, @function
_Z24__device_stub__Z4trapPfiPfi:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4trapPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z24__device_stub__Z4trapPfiPfi, .-_Z24__device_stub__Z4trapPfiPfi
.globl _Z4trapPfi
.type _Z4trapPfi, @function
_Z4trapPfi:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4trapPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z4trapPfi, .-_Z4trapPfi
.globl _Z23__device_stub__Z2mcPfiiPfii
.type _Z23__device_stub__Z2mcPfiiPfii, @function
_Z23__device_stub__Z2mcPfiiPfii:
.LFB2299:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2mcPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z23__device_stub__Z2mcPfiiPfii, .-_Z23__device_stub__Z2mcPfiiPfii
.globl _Z2mcPfii
.type _Z2mcPfii, @function
_Z2mcPfii:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2mcPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z2mcPfii, .-_Z2mcPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n"
.align 8
.LC3:
.string "Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
leal 1022(%rax), %edx
addl $511, %eax
cmovs %edx, %eax
sarl $9, %eax
movl %eax, %r12d
movq 8(%rbx), %rax
movzbl (%rax), %eax
cmpb $84, %al
je .L38
cmpb $77, %al
je .L39
.L27:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call clock@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L23:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r13, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
divsd .LC0(%rip), %xmm2
movss (%rbx), %xmm1
comiss .LC1(%rip), %xmm1
jbe .L35
movaps %xmm1, %xmm0
subss .LC1(%rip), %xmm0
.L26:
cvtss2sd %xmm0, %xmm0
movl %ebp, %ecx
movl %r12d, %edx
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L27
.L41:
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4trapPfiPfi
jmp .L23
.L35:
movss .LC1(%rip), %xmm0
subss %xmm1, %xmm0
jmp .L26
.L39:
call clock@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L28:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r13, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
divsd .LC0(%rip), %xmm2
movss (%rbx), %xmm1
comiss .LC1(%rip), %xmm1
jbe .L36
movaps %xmm1, %xmm0
subss .LC1(%rip), %xmm0
.L31:
cvtss2sd %xmm0, %xmm0
movl %ebp, %ecx
movl %r12d, %edx
cvtss2sd %xmm1, %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L27
.L42:
movl $0, %edi
call time@PLT
movl %eax, %edx
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z23__device_stub__Z2mcPfiiPfii
jmp .L28
.L36:
movss .LC1(%rip), %xmm0
subss %xmm1, %xmm0
jmp .L31
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z2mcPfii"
.LC5:
.string "_Z4trapPfi"
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z2mcPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4trapPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <curand.h>
#include <curand_kernel.h>
#define TPB 512
/** Need to use this function instead of atomicAdd for double precision. Computation done in single precision(float) for now**/
__device__ double atomicAdd_double(double* address, double val)
{
unsigned long long int* address_as_ull =
(unsigned long long int*)address;
unsigned long long int old = *address_as_ull, assumed;
do {
assumed = old;
old = atomicCAS(address_as_ull, assumed,
__double_as_longlong(val +
__longlong_as_double(assumed)));
} while (assumed != old);
return __longlong_as_double(old);
}
__global__ void trap(float *out, int N) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
temp[threadIdx.x] = sin(M_PI*(float)index/((float)N-1));
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/(N-1);
atomicAdd(out, sum);
}
return;
}
__global__ void mc(float *out, int N, int seed) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
curandState_t state;
curand_init(blockIdx.x + seed,
threadIdx.x,
0,
&state);
temp[threadIdx.x] = sin(curand_uniform(&state)*M_PI);
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/N;
atomicAdd(out, sum);
}
return;
}
int main(int argc, char** argv){
int num_points = atoi(argv[2]);
int num_blocks = (num_points+TPB-1)/TPB;
if(argv[1][0]=='T'){
clock_t begin = clock();
float* integral;
float* d_integral;
cudaMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
trap<<<num_blocks,TPB>>>(d_integral, num_points);
cudaMemcpy(integral, d_integral, sizeof(float), cudaMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
cudaFree(d_integral);
}
else if(argv[1][0]=='M'){
clock_t begin = clock();
float* integral;
float* d_integral;
cudaMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
mc<<<num_blocks,TPB>>>(d_integral, num_points, time(NULL));
cudaMemcpy(integral, d_integral, sizeof(float), cudaMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
cudaFree(d_integral);
}
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define TPB 512
/** Need to use this function instead of atomicAdd for double precision. Computation done in single precision(float) for now**/
__device__ double atomicAdd_double(double* address, double val)
{
unsigned long long int* address_as_ull =
(unsigned long long int*)address;
unsigned long long int old = *address_as_ull, assumed;
do {
assumed = old;
old = atomicCAS(address_as_ull, assumed,
__double_as_longlong(val +
__longlong_as_double(assumed)));
} while (assumed != old);
return __longlong_as_double(old);
}
__global__ void trap(float *out, int N) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
temp[threadIdx.x] = sin(M_PI*(float)index/((float)N-1));
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/(N-1);
atomicAdd(out, sum);
}
return;
}
__global__ void mc(float *out, int N, int seed) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
hiprandState_t state;
hiprand_init(blockIdx.x + seed,
threadIdx.x,
0,
&state);
temp[threadIdx.x] = sin(hiprand_uniform(&state)*M_PI);
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/N;
atomicAdd(out, sum);
}
return;
}
int main(int argc, char** argv){
int num_points = atoi(argv[2]);
int num_blocks = (num_points+TPB-1)/TPB;
if(argv[1][0]=='T'){
clock_t begin = clock();
float* integral;
float* d_integral;
hipMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
trap<<<num_blocks,TPB>>>(d_integral, num_points);
hipMemcpy(integral, d_integral, sizeof(float), hipMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
hipFree(d_integral);
}
else if(argv[1][0]=='M'){
clock_t begin = clock();
float* integral;
float* d_integral;
hipMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
mc<<<num_blocks,TPB>>>(d_integral, num_points, time(NULL));
hipMemcpy(integral, d_integral, sizeof(float), hipMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
hipFree(d_integral);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<math.h>
#include<time.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define TPB 512
/** Need to use this function instead of atomicAdd for double precision. Computation done in single precision(float) for now**/
__device__ double atomicAdd_double(double* address, double val)
{
unsigned long long int* address_as_ull =
(unsigned long long int*)address;
unsigned long long int old = *address_as_ull, assumed;
do {
assumed = old;
old = atomicCAS(address_as_ull, assumed,
__double_as_longlong(val +
__longlong_as_double(assumed)));
} while (assumed != old);
return __longlong_as_double(old);
}
__global__ void trap(float *out, int N) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
temp[threadIdx.x] = sin(M_PI*(float)index/((float)N-1));
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/(N-1);
atomicAdd(out, sum);
}
return;
}
__global__ void mc(float *out, int N, int seed) {
__shared__ float temp[TPB];
temp[threadIdx.x] = 0;
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index>=N){
}
else{
hiprandState_t state;
hiprand_init(blockIdx.x + seed,
threadIdx.x,
0,
&state);
temp[threadIdx.x] = sin(hiprand_uniform(&state)*M_PI);
}
__syncthreads();
if(threadIdx.x == 0){
float sum = 0;
for(int i = 0; i<TPB; i++){
sum += temp[i];
}
sum = sum*M_PI/N;
atomicAdd(out, sum);
}
return;
}
int main(int argc, char** argv){
int num_points = atoi(argv[2]);
int num_blocks = (num_points+TPB-1)/TPB;
if(argv[1][0]=='T'){
clock_t begin = clock();
float* integral;
float* d_integral;
hipMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
trap<<<num_blocks,TPB>>>(d_integral, num_points);
hipMemcpy(integral, d_integral, sizeof(float), hipMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
hipFree(d_integral);
}
else if(argv[1][0]=='M'){
clock_t begin = clock();
float* integral;
float* d_integral;
hipMalloc((void**)&d_integral, sizeof(float));
integral = (float *)malloc(sizeof(float));
mc<<<num_blocks,TPB>>>(d_integral, num_points, time(NULL));
hipMemcpy(integral, d_integral, sizeof(float), hipMemcpyDeviceToHost);
clock_t end = clock();
double time_spent = (double)(end-begin)/CLOCKS_PER_SEC;
float error = *integral > 2.0 ? *integral - 2.0 : 2.0 - *integral;
printf("Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n",error, *integral, num_blocks, num_points, time_spent);
free(integral);
hipFree(d_integral);
}
return 0;
} | .text
.file "main.hip"
.globl _Z19__device_stub__trapPfi # -- Begin function _Z19__device_stub__trapPfi
.p2align 4, 0x90
.type _Z19__device_stub__trapPfi,@function
_Z19__device_stub__trapPfi: # @_Z19__device_stub__trapPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4trapPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__trapPfi, .Lfunc_end0-_Z19__device_stub__trapPfi
.cfi_endproc
# -- End function
.globl _Z17__device_stub__mcPfii # -- Begin function _Z17__device_stub__mcPfii
.p2align 4, 0x90
.type _Z17__device_stub__mcPfii,@function
_Z17__device_stub__mcPfii: # @_Z17__device_stub__mcPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2mcPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z17__device_stub__mcPfii, .Lfunc_end1-_Z17__device_stub__mcPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_2:
.quad 0xc000000000000000 # double -2
.LCPI2_3:
.quad 0x4000000000000000 # double 2
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x40000000 # float 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 16(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
addl $511, %eax # imm = 0x1FF
leal 1022(%rbx), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $9, %ebp
movq 8(%r14), %rax
movzbl (%rax), %eax
cmpl $77, %eax
je .LBB2_8
# %bb.1:
cmpl $84, %eax
jne .LBB2_15
# %bb.2:
callq clock
movq %rax, %r15
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $4, %edi
callq malloc
movq %rax, %r14
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4trapPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm2
divsd .LCPI2_0(%rip), %xmm2
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
ucomiss .LCPI2_1(%rip), %xmm0
ja .LBB2_5
# %bb.6:
movsd .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm1, %xmm0
jmp .LBB2_7
.LBB2_8:
callq clock
movq %rax, %r15
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $4, %edi
callq malloc
movq %rax, %r14
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %r12
xorl %edi, %edi
callq time
movq %r12, 64(%rsp)
movl %ebx, 12(%rsp)
movl %eax, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2mcPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq (%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm2
divsd .LCPI2_0(%rip), %xmm2
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
ucomiss .LCPI2_1(%rip), %xmm0
ja .LBB2_11
# %bb.12:
movsd .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm1, %xmm0
jmp .LBB2_13
.LBB2_5:
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
addsd %xmm1, %xmm0
.LBB2_7:
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
jmp .LBB2_14
.LBB2_11:
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
addsd %xmm1, %xmm0
.LBB2_13:
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
.LBB2_14:
movl %ebp, %esi
movl %ebx, %edx
movb $3, %al
callq printf
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB2_15:
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4trapPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2mcPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4trapPfi,@object # @_Z4trapPfi
.section .rodata,"a",@progbits
.globl _Z4trapPfi
.p2align 3, 0x0
_Z4trapPfi:
.quad _Z19__device_stub__trapPfi
.size _Z4trapPfi, 8
.type _Z2mcPfii,@object # @_Z2mcPfii
.globl _Z2mcPfii
.p2align 3, 0x0
_Z2mcPfii:
.quad _Z17__device_stub__mcPfii
.size _Z2mcPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n"
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4trapPfi"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2mcPfii"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__trapPfi
.addrsig_sym _Z17__device_stub__mcPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4trapPfi
.addrsig_sym _Z2mcPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ff7e3_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16atomicAdd_doublePdd
.type _Z16atomicAdd_doublePdd, @function
_Z16atomicAdd_doublePdd:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z16atomicAdd_doublePdd, .-_Z16atomicAdd_doublePdd
.globl _Z24__device_stub__Z4trapPfiPfi
.type _Z24__device_stub__Z4trapPfiPfi, @function
_Z24__device_stub__Z4trapPfiPfi:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4trapPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z24__device_stub__Z4trapPfiPfi, .-_Z24__device_stub__Z4trapPfiPfi
.globl _Z4trapPfi
.type _Z4trapPfi, @function
_Z4trapPfi:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4trapPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z4trapPfi, .-_Z4trapPfi
.globl _Z23__device_stub__Z2mcPfiiPfii
.type _Z23__device_stub__Z2mcPfiiPfii, @function
_Z23__device_stub__Z2mcPfiiPfii:
.LFB2299:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2mcPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z23__device_stub__Z2mcPfiiPfii, .-_Z23__device_stub__Z2mcPfiiPfii
.globl _Z2mcPfii
.type _Z2mcPfii, @function
_Z2mcPfii:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2mcPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z2mcPfii, .-_Z2mcPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n"
.align 8
.LC3:
.string "Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
leal 1022(%rax), %edx
addl $511, %eax
cmovs %edx, %eax
sarl $9, %eax
movl %eax, %r12d
movq 8(%rbx), %rax
movzbl (%rax), %eax
cmpb $84, %al
je .L38
cmpb $77, %al
je .L39
.L27:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call clock@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L23:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r13, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
divsd .LC0(%rip), %xmm2
movss (%rbx), %xmm1
comiss .LC1(%rip), %xmm1
jbe .L35
movaps %xmm1, %xmm0
subss .LC1(%rip), %xmm0
.L26:
cvtss2sd %xmm0, %xmm0
movl %ebp, %ecx
movl %r12d, %edx
cvtss2sd %xmm1, %xmm1
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L27
.L41:
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4trapPfiPfi
jmp .L23
.L35:
movss .LC1(%rip), %xmm0
subss %xmm1, %xmm0
jmp .L26
.L39:
call clock@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L28:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r13, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
divsd .LC0(%rip), %xmm2
movss (%rbx), %xmm1
comiss .LC1(%rip), %xmm1
jbe .L36
movaps %xmm1, %xmm0
subss .LC1(%rip), %xmm0
.L31:
cvtss2sd %xmm0, %xmm0
movl %ebp, %ecx
movl %r12d, %edx
cvtss2sd %xmm1, %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L27
.L42:
movl $0, %edi
call time@PLT
movl %eax, %edx
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z23__device_stub__Z2mcPfiiPfii
jmp .L28
.L36:
movss .LC1(%rip), %xmm0
subss %xmm1, %xmm0
jmp .L31
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z2mcPfii"
.LC5:
.string "_Z4trapPfi"
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z2mcPfii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4trapPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z19__device_stub__trapPfi # -- Begin function _Z19__device_stub__trapPfi
.p2align 4, 0x90
.type _Z19__device_stub__trapPfi,@function
_Z19__device_stub__trapPfi: # @_Z19__device_stub__trapPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4trapPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__trapPfi, .Lfunc_end0-_Z19__device_stub__trapPfi
.cfi_endproc
# -- End function
.globl _Z17__device_stub__mcPfii # -- Begin function _Z17__device_stub__mcPfii
.p2align 4, 0x90
.type _Z17__device_stub__mcPfii,@function
_Z17__device_stub__mcPfii: # @_Z17__device_stub__mcPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2mcPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z17__device_stub__mcPfii, .Lfunc_end1-_Z17__device_stub__mcPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_2:
.quad 0xc000000000000000 # double -2
.LCPI2_3:
.quad 0x4000000000000000 # double 2
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x40000000 # float 2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 16(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
addl $511, %eax # imm = 0x1FF
leal 1022(%rbx), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
sarl $9, %ebp
movq 8(%r14), %rax
movzbl (%rax), %eax
cmpl $77, %eax
je .LBB2_8
# %bb.1:
cmpl $84, %eax
jne .LBB2_15
# %bb.2:
callq clock
movq %rax, %r15
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $4, %edi
callq malloc
movq %rax, %r14
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4trapPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm2
divsd .LCPI2_0(%rip), %xmm2
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
ucomiss .LCPI2_1(%rip), %xmm0
ja .LBB2_5
# %bb.6:
movsd .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm1, %xmm0
jmp .LBB2_7
.LBB2_8:
callq clock
movq %rax, %r15
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $4, %edi
callq malloc
movq %rax, %r14
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq (%rsp), %r12
xorl %edi, %edi
callq time
movq %r12, 64(%rsp)
movl %ebx, 12(%rsp)
movl %eax, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2mcPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq (%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r15, %rax
cvtsi2sd %rax, %xmm2
divsd .LCPI2_0(%rip), %xmm2
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm1
ucomiss .LCPI2_1(%rip), %xmm0
ja .LBB2_11
# %bb.12:
movsd .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm1, %xmm0
jmp .LBB2_13
.LBB2_5:
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
addsd %xmm1, %xmm0
.LBB2_7:
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
jmp .LBB2_14
.LBB2_11:
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
addsd %xmm1, %xmm0
.LBB2_13:
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
.LBB2_14:
movl %ebp, %esi
movl %ebx, %edx
movb $3, %al
callq printf
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB2_15:
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4trapPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2mcPfii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4trapPfi,@object # @_Z4trapPfi
.section .rodata,"a",@progbits
.globl _Z4trapPfi
.p2align 3, 0x0
_Z4trapPfi:
.quad _Z19__device_stub__trapPfi
.size _Z4trapPfi, 8
.type _Z2mcPfii,@object # @_Z2mcPfii
.globl _Z2mcPfii
.p2align 3, 0x0
_Z2mcPfii:
.quad _Z17__device_stub__mcPfii
.size _Z2mcPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Trapezoidal, %.12f, %.12f,%d, %d,%.12f\n"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Monte-Carlo, %.12f, %.12f,%d, %d,%.12f\n"
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4trapPfi"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2mcPfii"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__trapPfi
.addrsig_sym _Z17__device_stub__mcPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4trapPfi
.addrsig_sym _Z2mcPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convert(double* A,double* C)
{
int idx = BLOCK*blockIdx.x + threadIdx.x;
int i;
int stride = BLOCK * THREAD;
for(i=idx;i<SIZE;i+=stride)
A[i] = C[SIZE-i-1];
} | code for sm_80
Function : _Z7convertPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R5, 0x100, R2 ; /* 0x0000010005037824 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x270f, PT ; /* 0x0000270f0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMNMX R0, R3, -0x1d8f0, !PT ; /* 0xfffe271003007817 */
/* 0x000fe20007800200 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x270 ; /* 0x000001e000007945 */
/* 0x000fe40003800000 */
/*0090*/ IADD3 R0, -R2, 0x1ffff, R0 ; /* 0x0001ffff02007810 */
/* 0x000fca0007ffe100 */
/*00a0*/ IMAD R4, R5, -0x100, R0 ; /* 0xffffff0005047824 */
/* 0x000fca00078e0200 */
/*00b0*/ LEA.HI R0, R4.reuse, 0x1, RZ, 0xf ; /* 0x0000000104007811 */
/* 0x040fe400078f78ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x60000, PT ; /* 0x000600000400780c */
/* 0x000fe40003f06070 */
/*00d0*/ LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fda000782c0ff */
/*00e0*/ @!P1 BRA 0x260 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, -R2, 0x270f, RZ ; /* 0x0000270f02027810 */
/* 0x000fe20007ffe1ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD R2, R5, -0x100, R2 ; /* 0xffffff0005027824 */
/* 0x000fe400078e0202 */
/*0120*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0130*/ IMAD.WIDE R6, R2, R6, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0206 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0005 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0002 */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0009 */
/*01a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*01c0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R11.reuse ; /* 0x000000ffff077224 */
/* 0x100fe200078e000b */
/*01e0*/ IADD3 R8, P2, R8, 0x100000, RZ ; /* 0x0010000008087810 */
/* 0x000fe40007f5e0ff */
/*01f0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0200*/ IADD3 R2, P3, R2, -0x100000, RZ ; /* 0xfff0000002027810 */
/* 0x000fe20007f7e0ff */
/*0210*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0220*/ IADD3 R3, R3, 0x20000, RZ ; /* 0x0002000003037810 */
/* 0x000fc40007ffe0ff */
/*0230*/ IADD3.X R9, R9, -0x1, RZ, P3, !PT ; /* 0xffffffff09097810 */
/* 0x000fe20001ffe4ff */
/*0240*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0041ec000c101b04 */
/*0250*/ @P1 BRA 0x180 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R0, R3.reuse, -0x80000, RZ ; /* 0xfff8000003007810 */
/* 0x040fe20007ffe0ff */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x001fe200078e00ff */
/*02a0*/ BSSY B0, 0x610 ; /* 0x0000036000007945 */
/* 0x000fe40003800000 */
/*02b0*/ IADD3 R4, -R0, -0x7d8f0, RZ ; /* 0xfff8271000047810 */
/* 0x000fe20007ffe1ff */
/*02c0*/ IMAD.WIDE R6, R3, R5, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc600078e0205 */
/*02d0*/ ISETP.GT.AND P1, PT, R4, 0x180000, PT ; /* 0x001800000400780c */
/* 0x000fe40003f24270 */
/*02e0*/ IADD3 R2, P0, R6, 0x200000, RZ ; /* 0x0020000006027810 */
/* 0x000fe40007f1e0ff */
/*02f0*/ IADD3 R4, -R3, 0x270f, RZ ; /* 0x0000270f03047810 */
/* 0x000fc60007ffe1ff */
/*0300*/ IMAD.X R3, RZ, RZ, R7, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0607 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0320*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0330*/ @!P1 BRA 0x600 ; /* 0x000002c000009947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0350*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x010ea8000c1e1b00 */
/*0360*/ STG.E.64 [R2.64+-0x200000], R6 ; /* 0xe000000602007986 */
/* 0x0041e8000c101b04 */
/*0370*/ LDG.E.64 R8, [R4.64+-0x100000] ; /* 0xf000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0380*/ STG.E.64 [R2.64+-0x100000], R8 ; /* 0xf000000802007986 */
/* 0x0043e8000c101b04 */
/*0390*/ LDG.E.64 R10, [R4.64+-0x200000] ; /* 0xe0000004040a7981 */
/* 0x000ea8000c1e1b00 */
/*03a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*03b0*/ LDG.E.64 R12, [R4.64+-0x300000] ; /* 0xd0000004040c7981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ STG.E.64 [R2.64+0x100000], R12 ; /* 0x1000000c02007986 */
/* 0x0087e8000c101b04 */
/*03d0*/ LDG.E.64 R14, [R4.64+-0x400000] ; /* 0xc0000004040e7981 */
/* 0x000f28000c1e1b00 */
/*03e0*/ STG.E.64 [R2.64+0x200000], R14 ; /* 0x2000000e02007986 */
/* 0x0109e8000c101b04 */
/*03f0*/ LDG.E.64 R16, [R4.64+-0x500000] ; /* 0xb000000404107981 */
/* 0x000f68000c1e1b00 */
/*0400*/ STG.E.64 [R2.64+0x300000], R16 ; /* 0x3000001002007986 */
/* 0x020fe8000c101b04 */
/*0410*/ LDG.E.64 R6, [R4.64+-0x600000] ; /* 0xa000000404067981 */
/* 0x001f68000c1e1b00 */
/*0420*/ STG.E.64 [R2.64+0x400000], R6 ; /* 0x4000000602007986 */
/* 0x0201e8000c101b04 */
/*0430*/ LDG.E.64 R8, [R4.64+-0x700000] ; /* 0x9000000404087981 */
/* 0x002f62000c1e1b00 */
/*0440*/ IADD3 R18, P1, R4, -0x1000000, RZ ; /* 0xff00000004127810 */
/* 0x000fc60007f3e0ff */
/*0450*/ STG.E.64 [R2.64+0x500000], R8 ; /* 0x5000000802007986 */
/* 0x0203e8000c101b04 */
/*0460*/ LDG.E.64 R10, [R4.64+-0x800000] ; /* 0x80000004040a7981 */
/* 0x004ea2000c1e1b00 */
/*0470*/ IADD3.X R19, R5, -0x1, RZ, P1, !PT ; /* 0xffffffff05137810 */
/* 0x000fc60000ffe4ff */
/*0480*/ STG.E.64 [R2.64+0x600000], R10 ; /* 0x6000000a02007986 */
/* 0x0045e8000c101b04 */
/*0490*/ LDG.E.64 R12, [R18.64+0x700000] ; /* 0x70000004120c7981 */
/* 0x008ee2000c1e1b00 */
/*04a0*/ IADD3 R20, P1, R2, 0x1000000, RZ ; /* 0x0100000002147810 */
/* 0x000fc60007f3e0ff */
/*04b0*/ STG.E.64 [R2.64+0x700000], R12 ; /* 0x7000000c02007986 */
/* 0x0087e8000c101b04 */
/*04c0*/ LDG.E.64 R14, [R18.64+0x600000] ; /* 0x60000004120e7981 */
/* 0x010f22000c1e1b00 */
/*04d0*/ IMAD.X R21, RZ, RZ, R3, P1 ; /* 0x000000ffff157224 */
/* 0x000fca00008e0603 */
/*04e0*/ STG.E.64 [R20.64+-0x800000], R14 ; /* 0x8000000e14007986 */
/* 0x0109e8000c101b04 */
/*04f0*/ LDG.E.64 R6, [R18.64+0x500000] ; /* 0x5000000412067981 */
/* 0x001f68000c1e1b00 */
/*0500*/ STG.E.64 [R20.64+-0x700000], R6 ; /* 0x9000000614007986 */
/* 0x0209e8000c101b04 */
/*0510*/ LDG.E.64 R8, [R18.64+0x400000] ; /* 0x4000000412087981 */
/* 0x002f68000c1e1b00 */
/*0520*/ STG.E.64 [R20.64+-0x600000], R8 ; /* 0xa000000814007986 */
/* 0x0209e8000c101b04 */
/*0530*/ LDG.E.64 R10, [R18.64+0x300000] ; /* 0x30000004120a7981 */
/* 0x004ea8000c1e1b00 */
/*0540*/ STG.E.64 [R20.64+-0x500000], R10 ; /* 0xb000000a14007986 */
/* 0x0049e8000c101b04 */
/*0550*/ LDG.E.64 R12, [R18.64+0x200000] ; /* 0x20000004120c7981 */
/* 0x008ea8000c1e1b00 */
/*0560*/ STG.E.64 [R20.64+-0x400000], R12 ; /* 0xc000000c14007986 */
/* 0x0049e8000c101b04 */
/*0570*/ LDG.E.64 R16, [R18.64+0x100000] ; /* 0x1000000412107981 */
/* 0x000ea2000c1e1b00 */
/*0580*/ IADD3 R0, R0, 0x200000, RZ ; /* 0x0020000000007810 */
/* 0x000fc40007ffe0ff */
/*0590*/ IADD3 R2, P3, R2, 0x1000000, RZ ; /* 0x0100000002027810 */
/* 0x000fe40007f7e0ff */
/*05a0*/ ISETP.GE.AND P1, PT, R0, -0x1fd8f0, PT ; /* 0xffe027100000780c */
/* 0x000fe40003f26270 */
/*05b0*/ IADD3 R4, P2, R4, -0x1000000, RZ ; /* 0xff00000004047810 */
/* 0x000fe20007f5e0ff */
/*05c0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fc600018e0603 */
/*05d0*/ IADD3.X R5, R5, -0x1, RZ, P2, !PT ; /* 0xffffffff05057810 */
/* 0x000fe200017fe4ff */
/*05e0*/ STG.E.64 [R20.64+-0x300000], R16 ; /* 0xd000001014007986 */
/* 0x0049ec000c101b04 */
/*05f0*/ @!P1 BRA 0x350 ; /* 0xfffffd5000009947 */
/* 0x000fea000383ffff */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R6, -R0, -0x7d8f0, RZ ; /* 0xfff8271000067810 */
/* 0x010fe20007ffe1ff */
/*0620*/ BSSY B0, 0x800 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*0630*/ ISETP.GT.AND P1, PT, R6, 0x80000, PT ; /* 0x000800000600780c */
/* 0x000fda0003f24270 */
/*0640*/ @!P1 BRA 0x7f0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0660*/ STG.E.64 [R2.64+-0x200000], R6 ; /* 0xe000000602007986 */
/* 0x0041e8000c101b04 */
/*0670*/ LDG.E.64 R8, [R4.64+-0x100000] ; /* 0xf000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0680*/ STG.E.64 [R2.64+-0x100000], R8 ; /* 0xf000000802007986 */
/* 0x004fe8000c101b04 */
/*0690*/ LDG.E.64 R10, [R4.64+-0x200000] ; /* 0xe0000004040a7981 */
/* 0x000ea8000c1e1b00 */
/*06a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0043e8000c101b04 */
/*06b0*/ LDG.E.64 R12, [R4.64+-0x300000] ; /* 0xd0000004040c7981 */
/* 0x000ea8000c1e1b00 */
/*06c0*/ STG.E.64 [R2.64+0x100000], R12 ; /* 0x1000000c02007986 */
/* 0x004fe8000c101b04 */
/*06d0*/ LDG.E.64 R14, [R4.64+-0x400000] ; /* 0xc0000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*06e0*/ STG.E.64 [R2.64+0x200000], R14 ; /* 0x2000000e02007986 */
/* 0x004fe8000c101b04 */
/*06f0*/ LDG.E.64 R16, [R4.64+-0x500000] ; /* 0xb000000404107981 */
/* 0x000ea8000c1e1b00 */
/*0700*/ STG.E.64 [R2.64+0x300000], R16 ; /* 0x3000001002007986 */
/* 0x004fe8000c101b04 */
/*0710*/ LDG.E.64 R6, [R4.64+-0x600000] ; /* 0xa000000404067981 */
/* 0x001ea2000c1e1b00 */
/*0720*/ IADD3 R18, P1, R4, -0x800000, RZ ; /* 0xff80000004127810 */
/* 0x000fc40007f3e0ff */
/*0730*/ IADD3 R10, P2, R2, 0x800000, RZ ; /* 0x00800000020a7810 */
/* 0x002fe20007f5e0ff */
/*0740*/ STG.E.64 [R2.64+0x400000], R6 ; /* 0x4000000602007986 */
/* 0x004fe8000c101b04 */
/*0750*/ LDG.E.64 R8, [R4.64+-0x700000] ; /* 0x9000000404087981 */
/* 0x0000a2000c1e1b00 */
/*0760*/ IADD3.X R19, R5, -0x1, RZ, P1, !PT ; /* 0xffffffff05137810 */
/* 0x000fe20000ffe4ff */
/*0770*/ IMAD.X R11, RZ, RZ, R3, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e0603 */
/*0780*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0790*/ IADD3 R0, R0, 0x100000, RZ ; /* 0x0010000000007810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x001fc400078e0012 */
/*07b0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*07c0*/ STG.E.64 [R2.64+0x500000], R8 ; /* 0x5000000802007986 */
/* 0x0041e4000c101b04 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000a */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.LT.OR P0, PT, R0, -0x7d8f0, P0 ; /* 0xfff827100000780c */
/* 0x000fda0000701670 */
/*0810*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0820*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0830*/ STG.E.64 [R2.64+-0x200000], R6 ; /* 0xe000000602007986 */
/* 0x004fe8000c101b04 */
/*0840*/ LDG.E.64 R8, [R4.64+-0x100000] ; /* 0xf000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0850*/ STG.E.64 [R2.64+-0x100000], R8 ; /* 0xf000000802007986 */
/* 0x004fe8000c101b04 */
/*0860*/ LDG.E.64 R10, [R4.64+-0x200000] ; /* 0xe0000004040a7981 */
/* 0x000ea8000c1e1b00 */
/*0870*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x004fe8000c101b04 */
/*0880*/ LDG.E.64 R12, [R4.64+-0x300000] ; /* 0xd0000004040c7981 */
/* 0x000ea8000c1e1b00 */
/*0890*/ STG.E.64 [R2.64+0x100000], R12 ; /* 0x1000000c02007986 */
/* 0x004fe2000c101b04 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convert(double* A,double* C)
{
int idx = BLOCK*blockIdx.x + threadIdx.x;
int i;
int stride = BLOCK * THREAD;
for(i=idx;i<SIZE;i+=stride)
A[i] = C[SIZE-i-1];
} | .file "tmpxft_00117db5_00000000-6_convert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7convertPdS_PdS_
.type _Z28__device_stub__Z7convertPdS_PdS_, @function
_Z28__device_stub__Z7convertPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7convertPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7convertPdS_PdS_, .-_Z28__device_stub__Z7convertPdS_PdS_
.globl _Z7convertPdS_
.type _Z7convertPdS_, @function
_Z7convertPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7convertPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7convertPdS_, .-_Z7convertPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7convertPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7convertPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convert(double* A,double* C)
{
int idx = BLOCK*blockIdx.x + threadIdx.x;
int i;
int stride = BLOCK * THREAD;
for(i=idx;i<SIZE;i+=stride)
A[i] = C[SIZE-i-1];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convert(double* A,double* C)
{
int idx = BLOCK*blockIdx.x + threadIdx.x;
int i;
int stride = BLOCK * THREAD;
for(i=idx;i<SIZE;i+=stride)
A[i] = C[SIZE-i-1];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convert(double* A,double* C)
{
int idx = BLOCK*blockIdx.x + threadIdx.x;
int i;
int stride = BLOCK * THREAD;
for(i=idx;i<SIZE;i+=stride)
A[i] = C[SIZE-i-1];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7convertPdS_
.globl _Z7convertPdS_
.p2align 8
.type _Z7convertPdS_,@function
_Z7convertPdS_:
s_lshl_b32 s2, s15, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s2, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x2710, v2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, 0xfffe0000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_sub_nc_u32_e32 v2, 0x270f, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, 0x20000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[2:3]
v_add_nc_u32_e32 v2, 0xfffe0000, v2
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0xfffe270f, v4
global_load_b64 v[5:6], v[5:6], off
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[5:6], off
v_add_co_u32 v0, s0, v0, 0x100000
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7convertPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7convertPdS_, .Lfunc_end0-_Z7convertPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7convertPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7convertPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convert(double* A,double* C)
{
int idx = BLOCK*blockIdx.x + threadIdx.x;
int i;
int stride = BLOCK * THREAD;
for(i=idx;i<SIZE;i+=stride)
A[i] = C[SIZE-i-1];
} | .text
.file "convert.hip"
.globl _Z22__device_stub__convertPdS_ # -- Begin function _Z22__device_stub__convertPdS_
.p2align 4, 0x90
.type _Z22__device_stub__convertPdS_,@function
_Z22__device_stub__convertPdS_: # @_Z22__device_stub__convertPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7convertPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__convertPdS_, .Lfunc_end0-_Z22__device_stub__convertPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7convertPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7convertPdS_,@object # @_Z7convertPdS_
.section .rodata,"a",@progbits
.globl _Z7convertPdS_
.p2align 3, 0x0
_Z7convertPdS_:
.quad _Z22__device_stub__convertPdS_
.size _Z7convertPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7convertPdS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__convertPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7convertPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7convertPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R5, 0x100, R2 ; /* 0x0000010005037824 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x270f, PT ; /* 0x0000270f0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMNMX R0, R3, -0x1d8f0, !PT ; /* 0xfffe271003007817 */
/* 0x000fe20007800200 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x270 ; /* 0x000001e000007945 */
/* 0x000fe40003800000 */
/*0090*/ IADD3 R0, -R2, 0x1ffff, R0 ; /* 0x0001ffff02007810 */
/* 0x000fca0007ffe100 */
/*00a0*/ IMAD R4, R5, -0x100, R0 ; /* 0xffffff0005047824 */
/* 0x000fca00078e0200 */
/*00b0*/ LEA.HI R0, R4.reuse, 0x1, RZ, 0xf ; /* 0x0000000104007811 */
/* 0x040fe400078f78ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x60000, PT ; /* 0x000600000400780c */
/* 0x000fe40003f06070 */
/*00d0*/ LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fda000782c0ff */
/*00e0*/ @!P1 BRA 0x260 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, -R2, 0x270f, RZ ; /* 0x0000270f02027810 */
/* 0x000fe20007ffe1ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x8 ; /* 0x00000008ff067424 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD R2, R5, -0x100, R2 ; /* 0xffffff0005027824 */
/* 0x000fe400078e0202 */
/*0120*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0130*/ IMAD.WIDE R6, R2, R6, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0206 */
/*0140*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0005 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*0170*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0180*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0002 */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0009 */
/*01a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*01c0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, R11.reuse ; /* 0x000000ffff077224 */
/* 0x100fe200078e000b */
/*01e0*/ IADD3 R8, P2, R8, 0x100000, RZ ; /* 0x0010000008087810 */
/* 0x000fe40007f5e0ff */
/*01f0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f25270 */
/*0200*/ IADD3 R2, P3, R2, -0x100000, RZ ; /* 0xfff0000002027810 */
/* 0x000fe20007f7e0ff */
/*0210*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0220*/ IADD3 R3, R3, 0x20000, RZ ; /* 0x0002000003037810 */
/* 0x000fc40007ffe0ff */
/*0230*/ IADD3.X R9, R9, -0x1, RZ, P3, !PT ; /* 0xffffffff09097810 */
/* 0x000fe20001ffe4ff */
/*0240*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0041ec000c101b04 */
/*0250*/ @P1 BRA 0x180 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R0, R3.reuse, -0x80000, RZ ; /* 0xfff8000003007810 */
/* 0x040fe20007ffe0ff */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x001fe200078e00ff */
/*02a0*/ BSSY B0, 0x610 ; /* 0x0000036000007945 */
/* 0x000fe40003800000 */
/*02b0*/ IADD3 R4, -R0, -0x7d8f0, RZ ; /* 0xfff8271000047810 */
/* 0x000fe20007ffe1ff */
/*02c0*/ IMAD.WIDE R6, R3, R5, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc600078e0205 */
/*02d0*/ ISETP.GT.AND P1, PT, R4, 0x180000, PT ; /* 0x001800000400780c */
/* 0x000fe40003f24270 */
/*02e0*/ IADD3 R2, P0, R6, 0x200000, RZ ; /* 0x0020000006027810 */
/* 0x000fe40007f1e0ff */
/*02f0*/ IADD3 R4, -R3, 0x270f, RZ ; /* 0x0000270f03047810 */
/* 0x000fc60007ffe1ff */
/*0300*/ IMAD.X R3, RZ, RZ, R7, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0607 */
/*0310*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0320*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0330*/ @!P1 BRA 0x600 ; /* 0x000002c000009947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0e170 */
/*0350*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x010ea8000c1e1b00 */
/*0360*/ STG.E.64 [R2.64+-0x200000], R6 ; /* 0xe000000602007986 */
/* 0x0041e8000c101b04 */
/*0370*/ LDG.E.64 R8, [R4.64+-0x100000] ; /* 0xf000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0380*/ STG.E.64 [R2.64+-0x100000], R8 ; /* 0xf000000802007986 */
/* 0x0043e8000c101b04 */
/*0390*/ LDG.E.64 R10, [R4.64+-0x200000] ; /* 0xe0000004040a7981 */
/* 0x000ea8000c1e1b00 */
/*03a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0045e8000c101b04 */
/*03b0*/ LDG.E.64 R12, [R4.64+-0x300000] ; /* 0xd0000004040c7981 */
/* 0x000ee8000c1e1b00 */
/*03c0*/ STG.E.64 [R2.64+0x100000], R12 ; /* 0x1000000c02007986 */
/* 0x0087e8000c101b04 */
/*03d0*/ LDG.E.64 R14, [R4.64+-0x400000] ; /* 0xc0000004040e7981 */
/* 0x000f28000c1e1b00 */
/*03e0*/ STG.E.64 [R2.64+0x200000], R14 ; /* 0x2000000e02007986 */
/* 0x0109e8000c101b04 */
/*03f0*/ LDG.E.64 R16, [R4.64+-0x500000] ; /* 0xb000000404107981 */
/* 0x000f68000c1e1b00 */
/*0400*/ STG.E.64 [R2.64+0x300000], R16 ; /* 0x3000001002007986 */
/* 0x020fe8000c101b04 */
/*0410*/ LDG.E.64 R6, [R4.64+-0x600000] ; /* 0xa000000404067981 */
/* 0x001f68000c1e1b00 */
/*0420*/ STG.E.64 [R2.64+0x400000], R6 ; /* 0x4000000602007986 */
/* 0x0201e8000c101b04 */
/*0430*/ LDG.E.64 R8, [R4.64+-0x700000] ; /* 0x9000000404087981 */
/* 0x002f62000c1e1b00 */
/*0440*/ IADD3 R18, P1, R4, -0x1000000, RZ ; /* 0xff00000004127810 */
/* 0x000fc60007f3e0ff */
/*0450*/ STG.E.64 [R2.64+0x500000], R8 ; /* 0x5000000802007986 */
/* 0x0203e8000c101b04 */
/*0460*/ LDG.E.64 R10, [R4.64+-0x800000] ; /* 0x80000004040a7981 */
/* 0x004ea2000c1e1b00 */
/*0470*/ IADD3.X R19, R5, -0x1, RZ, P1, !PT ; /* 0xffffffff05137810 */
/* 0x000fc60000ffe4ff */
/*0480*/ STG.E.64 [R2.64+0x600000], R10 ; /* 0x6000000a02007986 */
/* 0x0045e8000c101b04 */
/*0490*/ LDG.E.64 R12, [R18.64+0x700000] ; /* 0x70000004120c7981 */
/* 0x008ee2000c1e1b00 */
/*04a0*/ IADD3 R20, P1, R2, 0x1000000, RZ ; /* 0x0100000002147810 */
/* 0x000fc60007f3e0ff */
/*04b0*/ STG.E.64 [R2.64+0x700000], R12 ; /* 0x7000000c02007986 */
/* 0x0087e8000c101b04 */
/*04c0*/ LDG.E.64 R14, [R18.64+0x600000] ; /* 0x60000004120e7981 */
/* 0x010f22000c1e1b00 */
/*04d0*/ IMAD.X R21, RZ, RZ, R3, P1 ; /* 0x000000ffff157224 */
/* 0x000fca00008e0603 */
/*04e0*/ STG.E.64 [R20.64+-0x800000], R14 ; /* 0x8000000e14007986 */
/* 0x0109e8000c101b04 */
/*04f0*/ LDG.E.64 R6, [R18.64+0x500000] ; /* 0x5000000412067981 */
/* 0x001f68000c1e1b00 */
/*0500*/ STG.E.64 [R20.64+-0x700000], R6 ; /* 0x9000000614007986 */
/* 0x0209e8000c101b04 */
/*0510*/ LDG.E.64 R8, [R18.64+0x400000] ; /* 0x4000000412087981 */
/* 0x002f68000c1e1b00 */
/*0520*/ STG.E.64 [R20.64+-0x600000], R8 ; /* 0xa000000814007986 */
/* 0x0209e8000c101b04 */
/*0530*/ LDG.E.64 R10, [R18.64+0x300000] ; /* 0x30000004120a7981 */
/* 0x004ea8000c1e1b00 */
/*0540*/ STG.E.64 [R20.64+-0x500000], R10 ; /* 0xb000000a14007986 */
/* 0x0049e8000c101b04 */
/*0550*/ LDG.E.64 R12, [R18.64+0x200000] ; /* 0x20000004120c7981 */
/* 0x008ea8000c1e1b00 */
/*0560*/ STG.E.64 [R20.64+-0x400000], R12 ; /* 0xc000000c14007986 */
/* 0x0049e8000c101b04 */
/*0570*/ LDG.E.64 R16, [R18.64+0x100000] ; /* 0x1000000412107981 */
/* 0x000ea2000c1e1b00 */
/*0580*/ IADD3 R0, R0, 0x200000, RZ ; /* 0x0020000000007810 */
/* 0x000fc40007ffe0ff */
/*0590*/ IADD3 R2, P3, R2, 0x1000000, RZ ; /* 0x0100000002027810 */
/* 0x000fe40007f7e0ff */
/*05a0*/ ISETP.GE.AND P1, PT, R0, -0x1fd8f0, PT ; /* 0xffe027100000780c */
/* 0x000fe40003f26270 */
/*05b0*/ IADD3 R4, P2, R4, -0x1000000, RZ ; /* 0xff00000004047810 */
/* 0x000fe20007f5e0ff */
/*05c0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fc600018e0603 */
/*05d0*/ IADD3.X R5, R5, -0x1, RZ, P2, !PT ; /* 0xffffffff05057810 */
/* 0x000fe200017fe4ff */
/*05e0*/ STG.E.64 [R20.64+-0x300000], R16 ; /* 0xd000001014007986 */
/* 0x0049ec000c101b04 */
/*05f0*/ @!P1 BRA 0x350 ; /* 0xfffffd5000009947 */
/* 0x000fea000383ffff */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ IADD3 R6, -R0, -0x7d8f0, RZ ; /* 0xfff8271000067810 */
/* 0x010fe20007ffe1ff */
/*0620*/ BSSY B0, 0x800 ; /* 0x000001d000007945 */
/* 0x000fe60003800000 */
/*0630*/ ISETP.GT.AND P1, PT, R6, 0x80000, PT ; /* 0x000800000600780c */
/* 0x000fda0003f24270 */
/*0640*/ @!P1 BRA 0x7f0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0660*/ STG.E.64 [R2.64+-0x200000], R6 ; /* 0xe000000602007986 */
/* 0x0041e8000c101b04 */
/*0670*/ LDG.E.64 R8, [R4.64+-0x100000] ; /* 0xf000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0680*/ STG.E.64 [R2.64+-0x100000], R8 ; /* 0xf000000802007986 */
/* 0x004fe8000c101b04 */
/*0690*/ LDG.E.64 R10, [R4.64+-0x200000] ; /* 0xe0000004040a7981 */
/* 0x000ea8000c1e1b00 */
/*06a0*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0043e8000c101b04 */
/*06b0*/ LDG.E.64 R12, [R4.64+-0x300000] ; /* 0xd0000004040c7981 */
/* 0x000ea8000c1e1b00 */
/*06c0*/ STG.E.64 [R2.64+0x100000], R12 ; /* 0x1000000c02007986 */
/* 0x004fe8000c101b04 */
/*06d0*/ LDG.E.64 R14, [R4.64+-0x400000] ; /* 0xc0000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*06e0*/ STG.E.64 [R2.64+0x200000], R14 ; /* 0x2000000e02007986 */
/* 0x004fe8000c101b04 */
/*06f0*/ LDG.E.64 R16, [R4.64+-0x500000] ; /* 0xb000000404107981 */
/* 0x000ea8000c1e1b00 */
/*0700*/ STG.E.64 [R2.64+0x300000], R16 ; /* 0x3000001002007986 */
/* 0x004fe8000c101b04 */
/*0710*/ LDG.E.64 R6, [R4.64+-0x600000] ; /* 0xa000000404067981 */
/* 0x001ea2000c1e1b00 */
/*0720*/ IADD3 R18, P1, R4, -0x800000, RZ ; /* 0xff80000004127810 */
/* 0x000fc40007f3e0ff */
/*0730*/ IADD3 R10, P2, R2, 0x800000, RZ ; /* 0x00800000020a7810 */
/* 0x002fe20007f5e0ff */
/*0740*/ STG.E.64 [R2.64+0x400000], R6 ; /* 0x4000000602007986 */
/* 0x004fe8000c101b04 */
/*0750*/ LDG.E.64 R8, [R4.64+-0x700000] ; /* 0x9000000404087981 */
/* 0x0000a2000c1e1b00 */
/*0760*/ IADD3.X R19, R5, -0x1, RZ, P1, !PT ; /* 0xffffffff05137810 */
/* 0x000fe20000ffe4ff */
/*0770*/ IMAD.X R11, RZ, RZ, R3, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e0603 */
/*0780*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0790*/ IADD3 R0, R0, 0x100000, RZ ; /* 0x0010000000007810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x001fc400078e0012 */
/*07b0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*07c0*/ STG.E.64 [R2.64+0x500000], R8 ; /* 0x5000000802007986 */
/* 0x0041e4000c101b04 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000a */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.LT.OR P0, PT, R0, -0x7d8f0, P0 ; /* 0xfff827100000780c */
/* 0x000fda0000701670 */
/*0810*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0820*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0830*/ STG.E.64 [R2.64+-0x200000], R6 ; /* 0xe000000602007986 */
/* 0x004fe8000c101b04 */
/*0840*/ LDG.E.64 R8, [R4.64+-0x100000] ; /* 0xf000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0850*/ STG.E.64 [R2.64+-0x100000], R8 ; /* 0xf000000802007986 */
/* 0x004fe8000c101b04 */
/*0860*/ LDG.E.64 R10, [R4.64+-0x200000] ; /* 0xe0000004040a7981 */
/* 0x000ea8000c1e1b00 */
/*0870*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x004fe8000c101b04 */
/*0880*/ LDG.E.64 R12, [R4.64+-0x300000] ; /* 0xd0000004040c7981 */
/* 0x000ea8000c1e1b00 */
/*0890*/ STG.E.64 [R2.64+0x100000], R12 ; /* 0x1000000c02007986 */
/* 0x004fe2000c101b04 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7convertPdS_
.globl _Z7convertPdS_
.p2align 8
.type _Z7convertPdS_,@function
_Z7convertPdS_:
s_lshl_b32 s2, s15, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s2, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x2710, v2
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, 0xfffe0000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_sub_nc_u32_e32 v2, 0x270f, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v4, 0x20000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[2:3]
v_add_nc_u32_e32 v2, 0xfffe0000, v2
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0xfffe270f, v4
global_load_b64 v[5:6], v[5:6], off
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[5:6], off
v_add_co_u32 v0, s0, v0, 0x100000
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7convertPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7convertPdS_, .Lfunc_end0-_Z7convertPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7convertPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7convertPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00117db5_00000000-6_convert.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7convertPdS_PdS_
.type _Z28__device_stub__Z7convertPdS_PdS_, @function
_Z28__device_stub__Z7convertPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7convertPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7convertPdS_PdS_, .-_Z28__device_stub__Z7convertPdS_PdS_
.globl _Z7convertPdS_
.type _Z7convertPdS_, @function
_Z7convertPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7convertPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7convertPdS_, .-_Z7convertPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7convertPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7convertPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convert.hip"
.globl _Z22__device_stub__convertPdS_ # -- Begin function _Z22__device_stub__convertPdS_
.p2align 4, 0x90
.type _Z22__device_stub__convertPdS_,@function
_Z22__device_stub__convertPdS_: # @_Z22__device_stub__convertPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7convertPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__convertPdS_, .Lfunc_end0-_Z22__device_stub__convertPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7convertPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7convertPdS_,@object # @_Z7convertPdS_
.section .rodata,"a",@progbits
.globl _Z7convertPdS_
.p2align 3, 0x0
_Z7convertPdS_:
.quad _Z22__device_stub__convertPdS_
.size _Z7convertPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7convertPdS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__convertPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7convertPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define SIZE 10
int main(int argc , char **argv){
int * p;
cudaError_t err;
// Should be cudaMalloc((void**)&p,SIZE*sizeof(int))
err=cudaMalloc((void**)&p,SIZE);
if( err != cudaSuccess)
{
printf("CUDA error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaFree(p);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define SIZE 10
int main(int argc , char **argv){
int * p;
cudaError_t err;
// Should be cudaMalloc((void**)&p,SIZE*sizeof(int))
err=cudaMalloc((void**)&p,SIZE);
if( err != cudaSuccess)
{
printf("CUDA error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaFree(p);
return 0;
} | .file "tmpxft_0017ffcb_00000000-6_m6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $10, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L7
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define SIZE 10
int main(int argc , char **argv){
int * p;
cudaError_t err;
// Should be cudaMalloc((void**)&p,SIZE*sizeof(int))
err=cudaMalloc((void**)&p,SIZE);
if( err != cudaSuccess)
{
printf("CUDA error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaFree(p);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
int main(int argc , char **argv){
int * p;
hipError_t err;
// Should be cudaMalloc((void**)&p,SIZE*sizeof(int))
err=hipMalloc((void**)&p,SIZE);
if( err != hipSuccess)
{
printf("CUDA error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipFree(p);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
int main(int argc , char **argv){
int * p;
hipError_t err;
// Should be cudaMalloc((void**)&p,SIZE*sizeof(int))
err=hipMalloc((void**)&p,SIZE);
if( err != hipSuccess)
{
printf("CUDA error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipFree(p);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE 10
int main(int argc , char **argv){
int * p;
hipError_t err;
// Should be cudaMalloc((void**)&p,SIZE*sizeof(int))
err=hipMalloc((void**)&p,SIZE);
if( err != hipSuccess)
{
printf("CUDA error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipFree(p);
return 0;
} | .text
.file "m6.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $10, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017ffcb_00000000-6_m6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $10, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L7
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "m6.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $10, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdlib.h>
#include <fstream>
#include <string>
#include <cmath>
#include <climits>
#include <iostream>
#include <chrono>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
using namespace std;
#define MAX_THREAD_PER_BLOCK 512
#define DEBUG_PRINT
/*
PARALLEL NN - VERSION 2
*/
typedef unsigned short int usint;
const usint num_dimensions = 16;
const usint numPointsTest = 1000;
const usint numPointsTrain = 19000;
const usint streamCount = 4;
struct Coordinates {
usint points[num_dimensions];
};
__device__ float getDistance(const Coordinates & coord1, const Coordinates & coord2) {
float square_sum = 0;
for (int i = 0; i < num_dimensions; i++) {
const int c1 = coord1.points[i];
const int c2 = coord2.points[i];
square_sum += (c1 - c2)*(c1 - c2);
}
return sqrt(square_sum);
}
__global__ void nearestNeighbor(Coordinates * trainCoords, Coordinates * testCoords, const usint sizeTest, const usint sizeTrain, usint * nearestNeighbors) {
const usint threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (threadId < sizeTest) { // DEBUG
usint nearestNeighbor = 0;
usint nearestDistance = USHRT_MAX;
for (int trainCoordInd = 0; trainCoordInd < sizeTrain; trainCoordInd++) {
float currentDistance = getDistance(trainCoords[trainCoordInd], testCoords[threadId]);
if (currentDistance < nearestDistance) {
nearestNeighbor = trainCoordInd;
nearestDistance = currentDistance;
}
}
nearestNeighbors[threadId] = nearestNeighbor;
}
}
bool checkError(const cudaError_t & error, const char * msg = "") {
if (error != cudaSuccess) {
printf("CUDA ERROR: %s\n", msg);
cout << error << endl;
exit(1);
}
return true;
}
int main() {
// 1 - INITIALIZE READ STREAMS
const char * testFile = "test.txt";
const char * trainFile = "train.txt";
FILE * test_is = fopen(testFile, "r"), * train_is = fopen(trainFile, "r");
if (!test_is) {
cerr << "Cannot open " << testFile << endl;
exit(1);
}
if (!train_is) {
cerr << "Cannot open " << trainFile << endl;
exit(1);
}
cudaSetDevice(0); // initialize CUDA context
cout << "\t--------------------\n";
chrono::high_resolution_clock::time_point begin = chrono::high_resolution_clock::now(), temp, end;
// 2 - SET EXECUTION PARAMETERS
cudaStream_t streams[streamCount]; // create four CUDA streams
cudaError_t cudaError;
usint numThreadsPerBlock = numPointsTest;
usint numBlocks = 1;
if (numPointsTest > MAX_THREAD_PER_BLOCK) {
numBlocks = std::ceil(static_cast<double>(numPointsTest) / MAX_THREAD_PER_BLOCK);
numThreadsPerBlock = MAX_THREAD_PER_BLOCK;
}
numThreadsPerBlock /= streamCount;
cout << "Kernels will be called with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each\n";
// 3 - READ TRAIN COORDINATES FROM FILE STREAMS
// device pointers
Coordinates * d_testCoordinates[streamCount], *d_trainCoordinates;
usint * d_nearestNeighbors[streamCount];
// host pointers
Coordinates * h_testCoordinates[streamCount], *h_trainCoordinates;
usint * h_nearestNeighbors[streamCount];
cudaError = cudaMallocHost((void**)&h_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(cudaError, "cudamallochost - h_trainCoordinates");
// read train points to host
for (int i = 0; i < numPointsTrain; i++) {
fscanf(train_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", &h_trainCoordinates[i].points[0], &h_trainCoordinates[i].points[1], &h_trainCoordinates[i].points[2],
&h_trainCoordinates[i].points[3], &h_trainCoordinates[i].points[4], &h_trainCoordinates[i].points[5], &h_trainCoordinates[i].points[6], &h_trainCoordinates[i].points[7],
&h_trainCoordinates[i].points[8], &h_trainCoordinates[i].points[9], &h_trainCoordinates[i].points[10], &h_trainCoordinates[i].points[11], &h_trainCoordinates[i].points[12],
&h_trainCoordinates[i].points[13], &h_trainCoordinates[i].points[14], &h_trainCoordinates[i].points[15]);
}
cout << "done reading training coordinates to host pinned memory" << endl;
// copy train coordinates to device
cudaError = cudaMalloc((void**)&d_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(cudaError, "cudaMalloc - d_trainCoordinates");
cudaError = cudaMemcpy(d_trainCoordinates, h_trainCoordinates, numPointsTrain * sizeof(Coordinates), cudaMemcpyHostToDevice);
checkError(cudaError, "cudaMemcpyAsync - d_trainCoordinates");
chrono::high_resolution_clock::time_point kernel_start = chrono::high_resolution_clock::now();
for (usint stream = 0; stream < streamCount; stream++) {
// 1 - create stream
cudaStreamCreate(&streams[stream]);
// 2 - Host memory - allocate memory on host for results and test coordinates
cudaError = cudaMallocHost((void**)&h_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(cudaError, "cudamallochost - h_nearestneighbors");
cudaError = cudaMallocHost((void**)&h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(cudaError, "cudamallochost - h_testCoordinates");
// 3 - Host memory - read test points
for (int i = 0; i < numPointsTest / streamCount; i++) {
fscanf(test_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", &h_testCoordinates[stream][i].points[0], &h_testCoordinates[stream][i].points[1], &h_testCoordinates[stream][i].points[2],
&h_testCoordinates[stream][i].points[3], &h_testCoordinates[stream][i].points[4], &h_testCoordinates[stream][i].points[5], &h_testCoordinates[stream][i].points[6], &h_testCoordinates[stream][i].points[7],
&h_testCoordinates[stream][i].points[8], &h_testCoordinates[stream][i].points[9], &h_testCoordinates[stream][i].points[10], &h_testCoordinates[stream][i].points[11], &h_testCoordinates[stream][i].points[12],
&h_testCoordinates[stream][i].points[13], &h_testCoordinates[stream][i].points[14], &h_testCoordinates[stream][i].points[15]);
}
// 4 - Device memory - allocate space for test coordiantes and result array for this stream to write its results to
cudaError = cudaMalloc((void**)&d_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(cudaError, "cudaMalloc - d_testCoordiantes");
cudaError = cudaMalloc((void**)&d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(cudaError, "cudaMalloc - d_nearestNeighbors");
// 5 - copy test coordinates to device in async
temp = chrono::high_resolution_clock::now();
cudaError = cudaMemcpyAsync(d_testCoordinates[stream], h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), cudaMemcpyHostToDevice, streams[stream]);
checkError(cudaError, "cudaMemcpy - d_testCoordinates");
end = chrono::high_resolution_clock::now();
cout << "data copied to device memory [" << chrono::duration_cast<chrono::milliseconds>(end - temp).count() << " ms]\n"
<< "executing kernel with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each" << endl;
// 6 - Inovke kernel for current stream
usint *& currentResultArray = d_nearestNeighbors[stream];
nearestNeighbor<<< numBlocks, numThreadsPerBlock, 0, streams[stream] >>>(d_trainCoordinates, d_testCoordinates[stream], numPointsTest / streamCount, numPointsTrain, currentResultArray);
cudaError = cudaMemcpyAsync(h_nearestNeighbors[stream], d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), cudaMemcpyDeviceToHost, streams[stream]);
checkError(cudaError, "cudaMemcpy - h_nearestNeighbors");
}
// Wait for GPU to terminate and fetch results
cudaError = cudaGetLastError();
checkError(cudaError, "before deviceSync() error!");
cudaDeviceSynchronize();
end = chrono::high_resolution_clock::now();
cout << "Computation + read test data: " << chrono::duration_cast<chrono::milliseconds>(end - kernel_start).count() << " ms\n";
cout << "\t--------------------\n";
end = chrono::high_resolution_clock::now();
ofstream os("output.txt");
for (int stream = 0; stream < streamCount; stream++) {
for (int i = 0; i < numPointsTest / streamCount; i++) {
os << h_nearestNeighbors[stream][i] << endl;
}
}
end = chrono::high_resolution_clock::now();
cout << "\t--------------------\nTotal time: " << chrono::duration_cast<chrono::milliseconds>(end - begin).count() << " ms\nterminating\n";
return 0;
} | code for sm_80
Function : _Z15nearestNeighborP11CoordinatesS0_ttPt
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR4, 0xffff ; /* 0x0000ffff00047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0xc0, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8ec03f */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ LOP3.LUT R0, R0, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff00007812 */
/* 0x000fc800078ec0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.U16 UR6, c[0x0][0x172] ; /* 0x00005c8000067ab9 */
/* 0x000fe40000000400 */
/*00b0*/ UPRMT UR4, UR6, 0x9910, URZ ; /* 0x0000991006047896 */
/* 0x000fcc000800003f */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00e0*/ @!P0 BRA 0x930 ; /* 0x0000084000008947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff037435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0110*/ LDG.E.U16 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000168000c1e1500 */
/*0120*/ LDG.E.U16 R7, [R2.64+0x2] ; /* 0x0000020402077981 */
/* 0x000168000c1e1500 */
/*0130*/ LDG.E.U16 R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000168000c1e1500 */
/*0140*/ LDG.E.U16 R9, [R2.64+0x6] ; /* 0x0000060402097981 */
/* 0x000168000c1e1500 */
/*0150*/ LDG.E.U16 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000168000c1e1500 */
/*0160*/ LDG.E.U16 R11, [R2.64+0xa] ; /* 0x00000a04020b7981 */
/* 0x000168000c1e1500 */
/*0170*/ LDG.E.U16 R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000168000c1e1500 */
/*0180*/ LDG.E.U16 R13, [R2.64+0xe] ; /* 0x00000e04020d7981 */
/* 0x000168000c1e1500 */
/*0190*/ LDG.E.U16 R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000168000c1e1500 */
/*01a0*/ LDG.E.U16 R15, [R2.64+0x12] ; /* 0x00001204020f7981 */
/* 0x000168000c1e1500 */
/*01b0*/ LDG.E.U16 R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000168000c1e1500 */
/*01c0*/ LDG.E.U16 R17, [R2.64+0x16] ; /* 0x0000160402117981 */
/* 0x000168000c1e1500 */
/*01d0*/ LDG.E.U16 R18, [R2.64+0x18] ; /* 0x0000180402127981 */
/* 0x000168000c1e1500 */
/*01e0*/ LDG.E.U16 R19, [R2.64+0x1a] ; /* 0x00001a0402137981 */
/* 0x000168000c1e1500 */
/*01f0*/ LDG.E.U16 R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000168000c1e1500 */
/*0200*/ LDG.E.U16 R21, [R2.64+0x1e] ; /* 0x00001e0402157981 */
/* 0x000162000c1e1500 */
/*0210*/ MOV R24, 0xffff ; /* 0x0000ffff00187802 */
/* 0x000fe20000000f00 */
/*0220*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0230*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fc40000000f00 */
/*0240*/ PRMT R24, RZ, 0x5410, R24 ; /* 0x00005410ff187816 */
/* 0x000fe40000000018 */
/*0250*/ MOV R26, c[0x0][0x164] ; /* 0x00005900001a7a02 */
/* 0x000fe40000000f00 */
/*0260*/ PRMT R22, RZ, 0x7610, R22 ; /* 0x00007610ff167816 */
/* 0x000fe40000000016 */
/*0270*/ MOV R2, R5 ; /* 0x0000000500027202 */
/* 0x001fe40000000f00 */
/*0280*/ MOV R3, R26 ; /* 0x0000001a00037202 */
/* 0x000fca0000000f00 */
/*0290*/ LDG.E.U16 R26, [R2.64+0x2] ; /* 0x00000204021a7981 */
/* 0x000ea8000c1e1500 */
/*02a0*/ LDG.E.U16 R25, [R2.64] ; /* 0x0000000402197981 */
/* 0x000ee8000c1e1500 */
/*02b0*/ LDG.E.U16 R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000f28000c1e1500 */
/*02c0*/ LDG.E.U16 R4, [R2.64+0x6] ; /* 0x0000060402047981 */
/* 0x000f22000c1e1500 */
/*02d0*/ IMAD.IADD R26, R26, 0x1, -R7 ; /* 0x000000011a1a7824 */
/* 0x024fe200078e0a07 */
/*02e0*/ IADD3 R25, -R6, R25, RZ ; /* 0x0000001906197210 */
/* 0x008fc60007ffe1ff */
/*02f0*/ IMAD R28, R26, R26, RZ ; /* 0x0000001a1a1c7224 */
/* 0x000fe200078e02ff */
/*0300*/ IADD3 R26, -R8, R5, RZ ; /* 0x00000005081a7210 */
/* 0x010fe20007ffe1ff */
/*0310*/ IMAD R27, R25, R25, RZ ; /* 0x00000019191b7224 */
/* 0x000fe200078e02ff */
/*0320*/ LDG.E.U16 R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea6000c1e1500 */
/*0330*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000fe20000201400 */
/*0340*/ IMAD R29, R26, R26, RZ ; /* 0x0000001a1a1d7224 */
/* 0x000fce00078e02ff */
/*0350*/ I2F R25, R27 ; /* 0x0000001b00197306 */
/* 0x000e220000201400 */
/*0360*/ IADD3 R4, -R9, R4, RZ ; /* 0x0000000409047210 */
/* 0x000fce0007ffe1ff */
/*0370*/ I2F R26, R29 ; /* 0x0000001d001a7306 */
/* 0x000e620000201400 */
/*0380*/ IMAD R4, R4, R4, RZ ; /* 0x0000000404047224 */
/* 0x000fe400078e02ff */
/*0390*/ FADD R25, R25, R28 ; /* 0x0000001c19197221 */
/* 0x001fca0000000000 */
/*03a0*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e220000201400 */
/*03b0*/ FADD R25, R25, R26 ; /* 0x0000001a19197221 */
/* 0x002fe40000000000 */
/*03c0*/ LDG.E.U16 R26, [R2.64+0xa] ; /* 0x00000a04021a7981 */
/* 0x000ee4000c1e1500 */
/*03d0*/ FADD R27, R25, R4 ; /* 0x00000004191b7221 */
/* 0x001fe40000000000 */
/*03e0*/ LDG.E.U16 R25, [R2.64+0xc] ; /* 0x00000c0402197981 */
/* 0x000f28000c1e1500 */
/*03f0*/ LDG.E.U16 R4, [R2.64+0xe] ; /* 0x00000e0402047981 */
/* 0x000f22000c1e1500 */
/*0400*/ IADD3 R5, -R10, R5, RZ ; /* 0x000000050a057210 */
/* 0x004fca0007ffe1ff */
/*0410*/ IMAD R28, R5, R5, RZ ; /* 0x00000005051c7224 */
/* 0x000fe400078e02ff */
/*0420*/ LDG.E.U16 R5, [R2.64+0x10] ; /* 0x0000100402057981 */
/* 0x000ea8000c1e1500 */
/*0430*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000e220000201400 */
/*0440*/ IADD3 R26, -R11, R26, RZ ; /* 0x0000001a0b1a7210 */
/* 0x008fca0007ffe1ff */
/*0450*/ IMAD R29, R26, R26, RZ ; /* 0x0000001a1a1d7224 */
/* 0x000fc800078e02ff */
/*0460*/ I2F R26, R29 ; /* 0x0000001d001a7306 */
/* 0x000e620000201400 */
/*0470*/ IADD3 R25, -R12, R25, RZ ; /* 0x000000190c197210 */
/* 0x010fe20007ffe1ff */
/*0480*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x001fc80000000000 */
/*0490*/ IMAD R25, R25, R25, RZ ; /* 0x0000001919197224 */
/* 0x000fe400078e02ff */
/*04a0*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x002fe40000000000 */
/*04b0*/ I2F R26, R25 ; /* 0x00000019001a7306 */
/* 0x0000620000201400 */
/*04c0*/ IADD3 R4, -R13, R4, RZ ; /* 0x000000040d047210 */
/* 0x000fe20007ffe1ff */
/*04d0*/ LDG.E.U16 R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x001ee2000c1e1500 */
/*04e0*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x002fc60000000000 */
/*04f0*/ LDG.E.U16 R26, [R2.64+0x12] ; /* 0x00001204021a7981 */
/* 0x000f22000c1e1500 */
/*0500*/ IMAD R28, R4, R4, RZ ; /* 0x00000004041c7224 */
/* 0x000fc600078e02ff */
/*0510*/ LDG.E.U16 R4, [R2.64+0x16] ; /* 0x0000160402047981 */
/* 0x000f26000c1e1500 */
/*0520*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000e240000201400 */
/*0530*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x001fe40000000000 */
/*0540*/ IMAD.IADD R5, R5, 0x1, -R14 ; /* 0x0000000105057824 */
/* 0x004fc800078e0a0e */
/*0550*/ IMAD R29, R5, R5, RZ ; /* 0x00000005051d7224 */
/* 0x000fe400078e02ff */
/*0560*/ LDG.E.U16 R5, [R2.64+0x18] ; /* 0x0000180402057981 */
/* 0x000ea8000c1e1500 */
/*0570*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e240000201400 */
/*0580*/ FADD R27, R27, R29 ; /* 0x0000001d1b1b7221 */
/* 0x001fe20000000000 */
/*0590*/ IADD3 R25, -R16, R25, RZ ; /* 0x0000001910197210 */
/* 0x008fe40007ffe1ff */
/*05a0*/ IADD3 R26, -R15, R26, RZ ; /* 0x0000001a0f1a7210 */
/* 0x010fc60007ffe1ff */
/*05b0*/ IMAD R28, R25, R25, RZ ; /* 0x00000019191c7224 */
/* 0x000fe400078e02ff */
/*05c0*/ LDG.E.U16 R25, [R2.64+0x1c] ; /* 0x00001c0402197981 */
/* 0x000ee2000c1e1500 */
/*05d0*/ IMAD R26, R26, R26, RZ ; /* 0x0000001a1a1a7224 */
/* 0x000fe200078e02ff */
/*05e0*/ IADD3 R4, -R17, R4, RZ ; /* 0x0000000411047210 */
/* 0x000fe40007ffe1ff */
/*05f0*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000fe60000201400 */
/*0600*/ IMAD R29, R4, R4, RZ ; /* 0x00000004041d7224 */
/* 0x000fca00078e02ff */
/*0610*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e300000201400 */
/*0620*/ I2F R4, R29 ; /* 0x0000001d00047306 */
/* 0x000e620000201400 */
/*0630*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x001fe40000000000 */
/*0640*/ LDG.E.U16 R26, [R2.64+0x1a] ; /* 0x00001a04021a7981 */
/* 0x000f24000c1e1500 */
/*0650*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x000fc80000000000 */
/*0660*/ FADD R27, R27, R4 ; /* 0x000000041b1b7221 */
/* 0x002fe40000000000 */
/*0670*/ LDG.E.U16 R4, [R2.64+0x1e] ; /* 0x00001e0402047981 */
/* 0x000f22000c1e1500 */
/*0680*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fe20007ffe0ff */
/*0690*/ BSSY B0, 0x880 ; /* 0x000001e000007945 */
/* 0x000fe60003800000 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R23, UR6, PT ; /* 0x0000000617007c0c */
/* 0x000fe4000bf06070 */
/*06b0*/ IADD3 R5, -R18, R5, RZ ; /* 0x0000000512057210 */
/* 0x004fca0007ffe1ff */
/*06c0*/ IMAD R5, R5, R5, RZ ; /* 0x0000000505057224 */
/* 0x000fcc00078e02ff */
/*06d0*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e240000201400 */
/*06e0*/ FADD R27, R27, R5 ; /* 0x000000051b1b7221 */
/* 0x001fe20000000000 */
/*06f0*/ IADD3 R25, -R20, R25, RZ ; /* 0x0000001914197210 */
/* 0x008fe40007ffe1ff */
/*0700*/ IADD3 R26, -R19, R26, RZ ; /* 0x0000001a131a7210 */
/* 0x010fca0007ffe1ff */
/*0710*/ IMAD R26, R26, R26, RZ ; /* 0x0000001a1a1a7224 */
/* 0x000fe200078e02ff */
/*0720*/ IADD3 R28, -R21, R4, RZ ; /* 0x00000004151c7210 */
/* 0x000fe20007ffe1ff */
/*0730*/ IMAD R4, R25, R25, RZ ; /* 0x0000001919047224 */
/* 0x000fc800078e02ff */
/*0740*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e220000201400 */
/*0750*/ IMAD R28, R28, R28, RZ ; /* 0x0000001c1c1c7224 */
/* 0x000fce00078e02ff */
/*0760*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e700000201400 */
/*0770*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000ea20000201400 */
/*0780*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x001fc80000000000 */
/*0790*/ FADD R27, R27, R4 ; /* 0x000000041b1b7221 */
/* 0x002fc80000000000 */
/*07a0*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x004fca0000000000 */
/*07b0*/ IADD3 R5, R27, -0xd000000, RZ ; /* 0xf30000001b057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ MUFU.RSQ R26, R27 ; /* 0x0000001b001a7308 */
/* 0x0000660000001400 */
/*07d0*/ ISETP.GT.U32.AND P1, PT, R5, 0x727fffff, PT ; /* 0x727fffff0500780c */
/* 0x000fda0003f24070 */
/*07e0*/ @!P1 BRA 0x830 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*07f0*/ MOV R4, 0x810 ; /* 0x0000081000047802 */
/* 0x003fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0x980 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, R25 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0019 */
/*0820*/ BRA 0x870 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0830*/ FMUL.FTZ R4, R27, R26 ; /* 0x0000001a1b047220 */
/* 0x003fe40000410000 */
/*0840*/ FMUL.FTZ R25, R26, 0.5 ; /* 0x3f0000001a197820 */
/* 0x000fe40000410000 */
/*0850*/ FFMA R5, -R4, R4, R27 ; /* 0x0000000404057223 */
/* 0x000fc8000000011b */
/*0860*/ FFMA R4, R5, R25, R4 ; /* 0x0000001905047223 */
/* 0x000fe40000000004 */
/*0870*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0880*/ I2F.U16 R5, R24.H1 ; /* 0x1000001800057306 */
/* 0x000e240000101000 */
/*0890*/ FSETP.GEU.AND P1, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x001fe40003f2e000 */
/*08a0*/ IADD3 R5, P2, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x000fe40007f5e0ff */
/*08b0*/ IADD3 R2, R22, 0x1, RZ ; /* 0x0000000116027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3.X R26, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff1a7210 */
/* 0x000fce00017fe4ff */
/*08d0*/ @!P1 F2I.U32.TRUNC.NTZ R4, R4 ; /* 0x0000000400049305 */
/* 0x000e24000020f000 */
/*08e0*/ @!P1 PRMT R24, R24, 0x5410, R4 ; /* 0x0000541018189816 */
/* 0x001fc80000000004 */
/*08f0*/ @!P1 PRMT R24, R22, 0x7610, R24 ; /* 0x0000761016189816 */
/* 0x000fe40000000018 */
/*0900*/ PRMT R22, R2, 0x7610, R22 ; /* 0x0000761002167816 */
/* 0x000fe20000000016 */
/*0910*/ @!P0 BRA 0x270 ; /* 0xfffff95000008947 */
/* 0x000fea000383ffff */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ PRMT R24, RZ, 0x7610, R24 ; /* 0x00007610ff187816 */
/* 0x000fe40000000018 */
/*0940*/ MOV R3, 0x2 ; /* 0x0000000200037802 */
/* 0x000fca0000000f00 */
/*0950*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0003 */
/*0960*/ STG.E.U16 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101504 */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT P1, RZ, R27, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1bff7812 */
/* 0x000fda000782c0ff */
/*0990*/ @!P1 MOV R25, R27 ; /* 0x0000001b00199202 */
/* 0x000fe20000000f00 */
/*09a0*/ @!P1 BRA 0xac0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*09b0*/ FSETP.GEU.FTZ.AND P1, PT, R27, RZ, PT ; /* 0x000000ff1b00720b */
/* 0x000fe40003f3e000 */
/*09c0*/ MOV R5, R27 ; /* 0x0000001b00057202 */
/* 0x000fd60000000f00 */
/*09d0*/ @!P1 MOV R25, 0x7fffffff ; /* 0x7fffffff00199802 */
/* 0x000fe20000000f00 */
/*09e0*/ @!P1 BRA 0xac0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*09f0*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f3c200 */
/*0a00*/ @P1 FADD.FTZ R25, R5, 1 ; /* 0x3f80000005191421 */
/* 0x000fe20000010000 */
/*0a10*/ @P1 BRA 0xac0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f3d200 */
/*0a30*/ @P1 FFMA R27, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f800000051b1823 */
/* 0x000fc800000000ff */
/*0a40*/ @P1 MUFU.RSQ R26, R27 ; /* 0x0000001b001a1308 */
/* 0x000e240000001400 */
/*0a50*/ @P1 FMUL.FTZ R25, R27, R26 ; /* 0x0000001a1b191220 */
/* 0x001fe40000410000 */
/*0a60*/ @P1 FMUL.FTZ R26, R26, 0.5 ; /* 0x3f0000001a1a1820 */
/* 0x000fe40000410000 */
/*0a70*/ @P1 FADD.FTZ R28, -R25, -RZ ; /* 0x800000ff191c1221 */
/* 0x000fc80000010100 */
/*0a80*/ @P1 FFMA R28, R25, R28, R27 ; /* 0x0000001c191c1223 */
/* 0x000fc8000000001b */
/*0a90*/ @P1 FFMA R26, R28, R26, R25 ; /* 0x0000001a1c1a1223 */
/* 0x000fe20000000019 */
/*0aa0*/ @!P1 MOV R25, R5 ; /* 0x0000000500199202 */
/* 0x000fc60000000f00 */
/*0ab0*/ @P1 FMUL.FTZ R25, R26, 2.3283064365386962891e-10 ; /* 0x2f8000001a191820 */
/* 0x000fe40000410000 */
/*0ac0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fcc00000001ff */
/*0ad0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff52004007950 */
/* 0x000fea0003c3ffff */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdlib.h>
#include <fstream>
#include <string>
#include <cmath>
#include <climits>
#include <iostream>
#include <chrono>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
using namespace std;
#define MAX_THREAD_PER_BLOCK 512
#define DEBUG_PRINT
/*
PARALLEL NN - VERSION 2
*/
typedef unsigned short int usint;
const usint num_dimensions = 16;
const usint numPointsTest = 1000;
const usint numPointsTrain = 19000;
const usint streamCount = 4;
struct Coordinates {
usint points[num_dimensions];
};
__device__ float getDistance(const Coordinates & coord1, const Coordinates & coord2) {
float square_sum = 0;
for (int i = 0; i < num_dimensions; i++) {
const int c1 = coord1.points[i];
const int c2 = coord2.points[i];
square_sum += (c1 - c2)*(c1 - c2);
}
return sqrt(square_sum);
}
__global__ void nearestNeighbor(Coordinates * trainCoords, Coordinates * testCoords, const usint sizeTest, const usint sizeTrain, usint * nearestNeighbors) {
const usint threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (threadId < sizeTest) { // DEBUG
usint nearestNeighbor = 0;
usint nearestDistance = USHRT_MAX;
for (int trainCoordInd = 0; trainCoordInd < sizeTrain; trainCoordInd++) {
float currentDistance = getDistance(trainCoords[trainCoordInd], testCoords[threadId]);
if (currentDistance < nearestDistance) {
nearestNeighbor = trainCoordInd;
nearestDistance = currentDistance;
}
}
nearestNeighbors[threadId] = nearestNeighbor;
}
}
bool checkError(const cudaError_t & error, const char * msg = "") {
if (error != cudaSuccess) {
printf("CUDA ERROR: %s\n", msg);
cout << error << endl;
exit(1);
}
return true;
}
int main() {
// 1 - INITIALIZE READ STREAMS
const char * testFile = "test.txt";
const char * trainFile = "train.txt";
FILE * test_is = fopen(testFile, "r"), * train_is = fopen(trainFile, "r");
if (!test_is) {
cerr << "Cannot open " << testFile << endl;
exit(1);
}
if (!train_is) {
cerr << "Cannot open " << trainFile << endl;
exit(1);
}
cudaSetDevice(0); // initialize CUDA context
cout << "\t--------------------\n";
chrono::high_resolution_clock::time_point begin = chrono::high_resolution_clock::now(), temp, end;
// 2 - SET EXECUTION PARAMETERS
cudaStream_t streams[streamCount]; // create four CUDA streams
cudaError_t cudaError;
usint numThreadsPerBlock = numPointsTest;
usint numBlocks = 1;
if (numPointsTest > MAX_THREAD_PER_BLOCK) {
numBlocks = std::ceil(static_cast<double>(numPointsTest) / MAX_THREAD_PER_BLOCK);
numThreadsPerBlock = MAX_THREAD_PER_BLOCK;
}
numThreadsPerBlock /= streamCount;
cout << "Kernels will be called with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each\n";
// 3 - READ TRAIN COORDINATES FROM FILE STREAMS
// device pointers
Coordinates * d_testCoordinates[streamCount], *d_trainCoordinates;
usint * d_nearestNeighbors[streamCount];
// host pointers
Coordinates * h_testCoordinates[streamCount], *h_trainCoordinates;
usint * h_nearestNeighbors[streamCount];
cudaError = cudaMallocHost((void**)&h_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(cudaError, "cudamallochost - h_trainCoordinates");
// read train points to host
for (int i = 0; i < numPointsTrain; i++) {
fscanf(train_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", &h_trainCoordinates[i].points[0], &h_trainCoordinates[i].points[1], &h_trainCoordinates[i].points[2],
&h_trainCoordinates[i].points[3], &h_trainCoordinates[i].points[4], &h_trainCoordinates[i].points[5], &h_trainCoordinates[i].points[6], &h_trainCoordinates[i].points[7],
&h_trainCoordinates[i].points[8], &h_trainCoordinates[i].points[9], &h_trainCoordinates[i].points[10], &h_trainCoordinates[i].points[11], &h_trainCoordinates[i].points[12],
&h_trainCoordinates[i].points[13], &h_trainCoordinates[i].points[14], &h_trainCoordinates[i].points[15]);
}
cout << "done reading training coordinates to host pinned memory" << endl;
// copy train coordinates to device
cudaError = cudaMalloc((void**)&d_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(cudaError, "cudaMalloc - d_trainCoordinates");
cudaError = cudaMemcpy(d_trainCoordinates, h_trainCoordinates, numPointsTrain * sizeof(Coordinates), cudaMemcpyHostToDevice);
checkError(cudaError, "cudaMemcpyAsync - d_trainCoordinates");
chrono::high_resolution_clock::time_point kernel_start = chrono::high_resolution_clock::now();
for (usint stream = 0; stream < streamCount; stream++) {
// 1 - create stream
cudaStreamCreate(&streams[stream]);
// 2 - Host memory - allocate memory on host for results and test coordinates
cudaError = cudaMallocHost((void**)&h_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(cudaError, "cudamallochost - h_nearestneighbors");
cudaError = cudaMallocHost((void**)&h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(cudaError, "cudamallochost - h_testCoordinates");
// 3 - Host memory - read test points
for (int i = 0; i < numPointsTest / streamCount; i++) {
fscanf(test_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", &h_testCoordinates[stream][i].points[0], &h_testCoordinates[stream][i].points[1], &h_testCoordinates[stream][i].points[2],
&h_testCoordinates[stream][i].points[3], &h_testCoordinates[stream][i].points[4], &h_testCoordinates[stream][i].points[5], &h_testCoordinates[stream][i].points[6], &h_testCoordinates[stream][i].points[7],
&h_testCoordinates[stream][i].points[8], &h_testCoordinates[stream][i].points[9], &h_testCoordinates[stream][i].points[10], &h_testCoordinates[stream][i].points[11], &h_testCoordinates[stream][i].points[12],
&h_testCoordinates[stream][i].points[13], &h_testCoordinates[stream][i].points[14], &h_testCoordinates[stream][i].points[15]);
}
// 4 - Device memory - allocate space for test coordiantes and result array for this stream to write its results to
cudaError = cudaMalloc((void**)&d_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(cudaError, "cudaMalloc - d_testCoordiantes");
cudaError = cudaMalloc((void**)&d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(cudaError, "cudaMalloc - d_nearestNeighbors");
// 5 - copy test coordinates to device in async
temp = chrono::high_resolution_clock::now();
cudaError = cudaMemcpyAsync(d_testCoordinates[stream], h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), cudaMemcpyHostToDevice, streams[stream]);
checkError(cudaError, "cudaMemcpy - d_testCoordinates");
end = chrono::high_resolution_clock::now();
cout << "data copied to device memory [" << chrono::duration_cast<chrono::milliseconds>(end - temp).count() << " ms]\n"
<< "executing kernel with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each" << endl;
// 6 - Inovke kernel for current stream
usint *& currentResultArray = d_nearestNeighbors[stream];
nearestNeighbor<<< numBlocks, numThreadsPerBlock, 0, streams[stream] >>>(d_trainCoordinates, d_testCoordinates[stream], numPointsTest / streamCount, numPointsTrain, currentResultArray);
cudaError = cudaMemcpyAsync(h_nearestNeighbors[stream], d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), cudaMemcpyDeviceToHost, streams[stream]);
checkError(cudaError, "cudaMemcpy - h_nearestNeighbors");
}
// Wait for GPU to terminate and fetch results
cudaError = cudaGetLastError();
checkError(cudaError, "before deviceSync() error!");
cudaDeviceSynchronize();
end = chrono::high_resolution_clock::now();
cout << "Computation + read test data: " << chrono::duration_cast<chrono::milliseconds>(end - kernel_start).count() << " ms\n";
cout << "\t--------------------\n";
end = chrono::high_resolution_clock::now();
ofstream os("output.txt");
for (int stream = 0; stream < streamCount; stream++) {
for (int i = 0; i < numPointsTest / streamCount; i++) {
os << h_nearestNeighbors[stream][i] << endl;
}
}
end = chrono::high_resolution_clock::now();
cout << "\t--------------------\nTotal time: " << chrono::duration_cast<chrono::milliseconds>(end - begin).count() << " ms\nterminating\n";
return 0;
} | .file "tmpxft_0017d951_00000000-6_source2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3910:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3910:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11getDistanceRK11CoordinatesS1_
.type _Z11getDistanceRK11CoordinatesS1_, @function
_Z11getDistanceRK11CoordinatesS1_:
.LFB3899:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3899:
.size _Z11getDistanceRK11CoordinatesS1_, .-_Z11getDistanceRK11CoordinatesS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA ERROR: %s\n"
.text
.globl _Z10checkErrorRK9cudaErrorPKc
.type _Z10checkErrorRK9cudaErrorPKc, @function
_Z10checkErrorRK9cudaErrorPKc:
.LFB3900:
.cfi_startproc
endbr64
cmpl $0, (%rdi)
jne .L10
movl $1, %eax
ret
.L10:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3900:
.size _Z10checkErrorRK9cudaErrorPKc, .-_Z10checkErrorRK9cudaErrorPKc
.globl _Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt
.type _Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt, @function
_Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt:
.LFB3932:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %r8, (%rsp)
movw %dx, 12(%rsp)
movw %cx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15nearestNeighborP11CoordinatesS0_ttPt(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3932:
.size _Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt, .-_Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt
.globl _Z15nearestNeighborP11CoordinatesS0_ttPt
.type _Z15nearestNeighborP11CoordinatesS0_ttPt, @function
_Z15nearestNeighborP11CoordinatesS0_ttPt:
.LFB3933:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzwl %cx, %ecx
movzwl %dx, %edx
call _Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3933:
.size _Z15nearestNeighborP11CoordinatesS0_ttPt, .-_Z15nearestNeighborP11CoordinatesS0_ttPt
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z15nearestNeighborP11CoordinatesS0_ttPt"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3935:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15nearestNeighborP11CoordinatesS0_ttPt(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3935:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "test.txt"
.LC4:
.string "train.txt"
.LC5:
.string "Cannot open "
.LC6:
.string "\t--------------------\n"
.LC7:
.string "Kernels will be called with "
.LC8:
.string " blocks with "
.LC9:
.string " threads each\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "cudamallochost - h_trainCoordinates"
.align 8
.LC11:
.string "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n"
.align 8
.LC12:
.string "done reading training coordinates to host pinned memory"
.align 8
.LC13:
.string "cudaMalloc - d_trainCoordinates"
.align 8
.LC14:
.string "cudaMemcpyAsync - d_trainCoordinates"
.align 8
.LC15:
.string "cudamallochost - h_nearestneighbors"
.align 8
.LC16:
.string "cudamallochost - h_testCoordinates"
.align 8
.LC17:
.string "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d"
.align 8
.LC18:
.string "cudaMalloc - d_testCoordiantes"
.align 8
.LC19:
.string "cudaMalloc - d_nearestNeighbors"
.align 8
.LC20:
.string "cudaMemcpy - d_testCoordinates"
.align 8
.LC21:
.string "data copied to device memory ["
.section .rodata.str1.1
.LC22:
.string " ms]\n"
.LC23:
.string "executing kernel with "
.LC24:
.string " threads each"
.section .rodata.str1.8
.align 8
.LC25:
.string "cudaMemcpy - h_nearestNeighbors"
.section .rodata.str1.1
.LC26:
.string "before deviceSync() error!"
.section .rodata.str1.8
.align 8
.LC27:
.string "Computation + read test data: "
.section .rodata.str1.1
.LC28:
.string " ms\n"
.LC29:
.string "output.txt"
.section .rodata.str1.8
.align 8
.LC30:
.string "\t--------------------\nTotal time: "
.section .rodata.str1.1
.LC31:
.string " ms\nterminating\n"
.text
.globl main
.type main, @function
main:
.LFB3901:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3901
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $856, %rsp
.cfi_def_cfa_offset 912
movq %fs:40, %rax
movq %rax, 840(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
.LEHB0:
call fopen@PLT
movq %rax, %r14
movq %rbx, %rsi
leaq .LC4(%rip), %rdi
call fopen@PLT
testq %r14, %r14
je .L49
movq %rax, %rbp
testq %rax, %rax
je .L50
movl $0, %edi
call cudaSetDevice@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 88(%rsp)
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $2, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $128, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 128(%rsp), %rdi
movl $608000, %esi
call cudaMallocHost@PLT
movl %eax, 116(%rsp)
leaq 116(%rsp), %rdi
leaq .LC10(%rip), %rsi
call _Z10checkErrorRK9cudaErrorPKc
movl $0, %ebx
leaq .LC11(%rip), %r12
.L24:
movq %rbx, %rdx
addq 128(%rsp), %rdx
leaq 2(%rdx), %rcx
leaq 30(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 920
leaq 28(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 928
leaq 26(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 936
leaq 24(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 944
leaq 22(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 952
leaq 20(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 960
leaq 18(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 968
leaq 16(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 976
leaq 14(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 984
leaq 12(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 992
leaq 10(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 1000
leaq 8(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 1008
leaq 6(%rdx), %r9
leaq 4(%rdx), %r8
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $32, %rbx
addq $96, %rsp
.cfi_def_cfa_offset 912
cmpq $608000, %rbx
jne .L24
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 120(%rsp), %rdi
movl $608000, %esi
call cudaMalloc@PLT
movl %eax, 116(%rsp)
leaq 116(%rsp), %rbx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _Z10checkErrorRK9cudaErrorPKc
movl $1, %ecx
movl $608000, %edx
movq 128(%rsp), %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, 116(%rsp)
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _Z10checkErrorRK9cudaErrorPKc
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
leaq 160(%rsp), %rax
movq %rax, 40(%rsp)
leaq 288(%rsp), %r13
leaq 256(%rsp), %rax
movq %rax, 8(%rsp)
leaq 224(%rsp), %rax
movq %rax, 32(%rsp)
leaq 192(%rsp), %rbp
movq %r13, 80(%rsp)
movq %r13, 48(%rsp)
leaq .LC17(%rip), %r15
movq %r13, 96(%rsp)
movq %r12, 104(%rsp)
movq %rbx, %r13
jmp .L31
.L49:
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L50:
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L54:
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L51
call _ZSt16__throw_bad_castv@PLT
.L51:
call __stack_chk_fail@PLT
.L55:
movzbl 67(%r12), %eax
.L29:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $128, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $2, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movq 16(%rsp), %rax
movq (%rax), %r9
movl $0, %r8d
movq 148(%rsp), %rdx
movl $1, %ecx
movq 136(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L30:
movq 24(%rsp), %rax
movq (%rax), %rsi
movq 56(%rsp), %rax
movq (%rax), %rdi
movq 16(%rsp), %rax
movq (%rax), %r8
movl $2, %ecx
movl $500, %edx
call cudaMemcpyAsync@PLT
movl %eax, 116(%rsp)
leaq .LC25(%rip), %rsi
movq %r13, %rdi
call _Z10checkErrorRK9cudaErrorPKc
addq $8, 40(%rsp)
addq $8, 48(%rsp)
addq $8, 8(%rsp)
movq 8(%rsp), %rax
addq $8, 32(%rsp)
addq $8, %rbp
cmpq %rax, 80(%rsp)
je .L53
.L31:
movq 40(%rsp), %rdi
movq %rdi, 16(%rsp)
call cudaStreamCreate@PLT
movq 48(%rsp), %rdi
movq %rdi, 56(%rsp)
movl $500, %esi
call cudaMallocHost@PLT
movl %eax, 116(%rsp)
leaq .LC15(%rip), %rsi
movq %r13, %rdi
call _Z10checkErrorRK9cudaErrorPKc
movq 8(%rsp), %rdi
movq %rdi, %rbx
movl $8000, %esi
call cudaMallocHost@PLT
movl %eax, 116(%rsp)
leaq .LC16(%rip), %rsi
movq %r13, %rdi
call _Z10checkErrorRK9cudaErrorPKc
movl $0, %r12d
.L25:
movq %r12, %rdx
addq (%rbx), %rdx
leaq 2(%rdx), %rcx
leaq 30(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 920
leaq 28(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 928
leaq 26(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 936
leaq 24(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 944
leaq 22(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 952
leaq 20(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 960
leaq 18(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 968
leaq 16(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 976
leaq 14(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 984
leaq 12(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 992
leaq 10(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 1000
leaq 8(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 1008
leaq 6(%rdx), %r9
leaq 4(%rdx), %r8
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $32, %r12
addq $96, %rsp
.cfi_def_cfa_offset 912
cmpq $8000, %r12
jne .L25
movq %rbp, 72(%rsp)
movl $8000, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
movl %eax, 116(%rsp)
leaq .LC18(%rip), %rsi
movq %r13, %rdi
call _Z10checkErrorRK9cudaErrorPKc
movq 32(%rsp), %rdi
movq %rdi, 24(%rsp)
movl $500, %esi
call cudaMalloc@PLT
movl %eax, 116(%rsp)
leaq .LC19(%rip), %rsi
movq %r13, %rdi
call _Z10checkErrorRK9cudaErrorPKc
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 64(%rsp)
movq (%rbx), %rsi
movq 0(%rbp), %rdi
movq 16(%rsp), %rcx
movq (%rcx), %r8
movl $1, %ecx
movl $8000, %edx
call cudaMemcpyAsync@PLT
movl %eax, 116(%rsp)
leaq .LC20(%rip), %rsi
movq %r13, %rdi
call _Z10checkErrorRK9cudaErrorPKc
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $30, %edx
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 64(%rsp), %rax
subq %rax, %rbx
movabsq $4835703278458516699, %rdx
movq %rbx, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %rbx
movq %rdx, %rsi
subq %rbx, %rsi
movq %r12, %rdi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rbx
movl $5, %edx
leaq .LC22(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $22, %edx
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $2, %esi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movl $13, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $128, %esi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movl $13, %edx
leaq .LC24(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L54
cmpb $0, 56(%r12)
jne .L55
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L29
.L52:
movq 72(%rsp), %rax
movq (%rax), %rsi
movq 24(%rsp), %rax
movq (%rax), %r8
movl $19000, %ecx
movl $250, %edx
movq 120(%rsp), %rdi
call _Z54__device_stub__Z15nearestNeighborP11CoordinatesS0_ttPtP11CoordinatesS0_ttPt
jmp .L30
.L53:
movq 96(%rsp), %r13
movq 104(%rsp), %r12
call cudaGetLastError@PLT
movl %eax, 116(%rsp)
leaq 116(%rsp), %rdi
leaq .LC26(%rip), %rsi
call _Z10checkErrorRK9cudaErrorPKc
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
leaq .LC27(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rcx
subq %r12, %rcx
movabsq $4835703278458516699, %rdx
movq %rcx, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC28(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
leaq 320(%rsp), %rdi
movl $16, %edx
leaq .LC29(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 32(%r13), %r15
leaq 320(%rsp), %r14
jmp .L32
.L60:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L56
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
.LEHB1:
call _ZNSo3putEc@PLT
jmp .L57
.L56:
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L42:
endbr64
movq %rax, %rbx
leaq 320(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 840(%rsp), %rax
subq %fs:40, %rax
je .L40
call __stack_chk_fail@PLT
.L58:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L57:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $2, %r12
cmpq $500, %r12
je .L59
.L37:
movq 0(%r13), %rax
movzwl (%rax,%r12), %esi
movq %r14, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
jmp .L60
.L59:
addq $8, %r13
cmpq %r15, %r13
je .L38
.L32:
movl $0, %r12d
jmp .L37
.L38:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC30(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rcx
movq 88(%rsp), %rax
subq %rax, %rcx
movabsq $4835703278458516699, %rdx
movq %rcx, %rax
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC31(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE1:
leaq 320(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L61
movl $0, %eax
addq $856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3901:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3901:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3901-.LLSDACSB3901
.LLSDACSB3901:
.uleb128 .LEHB0-.LFB3901
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3901
.uleb128 .LEHE1-.LEHB1
.uleb128 .L42-.LFB3901
.uleb128 0
.uleb128 .LEHB2-.LFB3901
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3901:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdlib.h>
#include <fstream>
#include <string>
#include <cmath>
#include <climits>
#include <iostream>
#include <chrono>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
using namespace std;
#define MAX_THREAD_PER_BLOCK 512
#define DEBUG_PRINT
/*
PARALLEL NN - VERSION 2
*/
typedef unsigned short int usint;
const usint num_dimensions = 16;
const usint numPointsTest = 1000;
const usint numPointsTrain = 19000;
const usint streamCount = 4;
struct Coordinates {
usint points[num_dimensions];
};
__device__ float getDistance(const Coordinates & coord1, const Coordinates & coord2) {
float square_sum = 0;
for (int i = 0; i < num_dimensions; i++) {
const int c1 = coord1.points[i];
const int c2 = coord2.points[i];
square_sum += (c1 - c2)*(c1 - c2);
}
return sqrt(square_sum);
}
__global__ void nearestNeighbor(Coordinates * trainCoords, Coordinates * testCoords, const usint sizeTest, const usint sizeTrain, usint * nearestNeighbors) {
const usint threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (threadId < sizeTest) { // DEBUG
usint nearestNeighbor = 0;
usint nearestDistance = USHRT_MAX;
for (int trainCoordInd = 0; trainCoordInd < sizeTrain; trainCoordInd++) {
float currentDistance = getDistance(trainCoords[trainCoordInd], testCoords[threadId]);
if (currentDistance < nearestDistance) {
nearestNeighbor = trainCoordInd;
nearestDistance = currentDistance;
}
}
nearestNeighbors[threadId] = nearestNeighbor;
}
}
bool checkError(const cudaError_t & error, const char * msg = "") {
if (error != cudaSuccess) {
printf("CUDA ERROR: %s\n", msg);
cout << error << endl;
exit(1);
}
return true;
}
int main() {
// 1 - INITIALIZE READ STREAMS
const char * testFile = "test.txt";
const char * trainFile = "train.txt";
FILE * test_is = fopen(testFile, "r"), * train_is = fopen(trainFile, "r");
if (!test_is) {
cerr << "Cannot open " << testFile << endl;
exit(1);
}
if (!train_is) {
cerr << "Cannot open " << trainFile << endl;
exit(1);
}
cudaSetDevice(0); // initialize CUDA context
cout << "\t--------------------\n";
chrono::high_resolution_clock::time_point begin = chrono::high_resolution_clock::now(), temp, end;
// 2 - SET EXECUTION PARAMETERS
cudaStream_t streams[streamCount]; // create four CUDA streams
cudaError_t cudaError;
usint numThreadsPerBlock = numPointsTest;
usint numBlocks = 1;
if (numPointsTest > MAX_THREAD_PER_BLOCK) {
numBlocks = std::ceil(static_cast<double>(numPointsTest) / MAX_THREAD_PER_BLOCK);
numThreadsPerBlock = MAX_THREAD_PER_BLOCK;
}
numThreadsPerBlock /= streamCount;
cout << "Kernels will be called with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each\n";
// 3 - READ TRAIN COORDINATES FROM FILE STREAMS
// device pointers
Coordinates * d_testCoordinates[streamCount], *d_trainCoordinates;
usint * d_nearestNeighbors[streamCount];
// host pointers
Coordinates * h_testCoordinates[streamCount], *h_trainCoordinates;
usint * h_nearestNeighbors[streamCount];
cudaError = cudaMallocHost((void**)&h_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(cudaError, "cudamallochost - h_trainCoordinates");
// read train points to host
for (int i = 0; i < numPointsTrain; i++) {
fscanf(train_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", &h_trainCoordinates[i].points[0], &h_trainCoordinates[i].points[1], &h_trainCoordinates[i].points[2],
&h_trainCoordinates[i].points[3], &h_trainCoordinates[i].points[4], &h_trainCoordinates[i].points[5], &h_trainCoordinates[i].points[6], &h_trainCoordinates[i].points[7],
&h_trainCoordinates[i].points[8], &h_trainCoordinates[i].points[9], &h_trainCoordinates[i].points[10], &h_trainCoordinates[i].points[11], &h_trainCoordinates[i].points[12],
&h_trainCoordinates[i].points[13], &h_trainCoordinates[i].points[14], &h_trainCoordinates[i].points[15]);
}
cout << "done reading training coordinates to host pinned memory" << endl;
// copy train coordinates to device
cudaError = cudaMalloc((void**)&d_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(cudaError, "cudaMalloc - d_trainCoordinates");
cudaError = cudaMemcpy(d_trainCoordinates, h_trainCoordinates, numPointsTrain * sizeof(Coordinates), cudaMemcpyHostToDevice);
checkError(cudaError, "cudaMemcpyAsync - d_trainCoordinates");
chrono::high_resolution_clock::time_point kernel_start = chrono::high_resolution_clock::now();
for (usint stream = 0; stream < streamCount; stream++) {
// 1 - create stream
cudaStreamCreate(&streams[stream]);
// 2 - Host memory - allocate memory on host for results and test coordinates
cudaError = cudaMallocHost((void**)&h_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(cudaError, "cudamallochost - h_nearestneighbors");
cudaError = cudaMallocHost((void**)&h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(cudaError, "cudamallochost - h_testCoordinates");
// 3 - Host memory - read test points
for (int i = 0; i < numPointsTest / streamCount; i++) {
fscanf(test_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", &h_testCoordinates[stream][i].points[0], &h_testCoordinates[stream][i].points[1], &h_testCoordinates[stream][i].points[2],
&h_testCoordinates[stream][i].points[3], &h_testCoordinates[stream][i].points[4], &h_testCoordinates[stream][i].points[5], &h_testCoordinates[stream][i].points[6], &h_testCoordinates[stream][i].points[7],
&h_testCoordinates[stream][i].points[8], &h_testCoordinates[stream][i].points[9], &h_testCoordinates[stream][i].points[10], &h_testCoordinates[stream][i].points[11], &h_testCoordinates[stream][i].points[12],
&h_testCoordinates[stream][i].points[13], &h_testCoordinates[stream][i].points[14], &h_testCoordinates[stream][i].points[15]);
}
// 4 - Device memory - allocate space for test coordiantes and result array for this stream to write its results to
cudaError = cudaMalloc((void**)&d_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(cudaError, "cudaMalloc - d_testCoordiantes");
cudaError = cudaMalloc((void**)&d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(cudaError, "cudaMalloc - d_nearestNeighbors");
// 5 - copy test coordinates to device in async
temp = chrono::high_resolution_clock::now();
cudaError = cudaMemcpyAsync(d_testCoordinates[stream], h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), cudaMemcpyHostToDevice, streams[stream]);
checkError(cudaError, "cudaMemcpy - d_testCoordinates");
end = chrono::high_resolution_clock::now();
cout << "data copied to device memory [" << chrono::duration_cast<chrono::milliseconds>(end - temp).count() << " ms]\n"
<< "executing kernel with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each" << endl;
// 6 - Inovke kernel for current stream
usint *& currentResultArray = d_nearestNeighbors[stream];
nearestNeighbor<<< numBlocks, numThreadsPerBlock, 0, streams[stream] >>>(d_trainCoordinates, d_testCoordinates[stream], numPointsTest / streamCount, numPointsTrain, currentResultArray);
cudaError = cudaMemcpyAsync(h_nearestNeighbors[stream], d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), cudaMemcpyDeviceToHost, streams[stream]);
checkError(cudaError, "cudaMemcpy - h_nearestNeighbors");
}
// Wait for GPU to terminate and fetch results
cudaError = cudaGetLastError();
checkError(cudaError, "before deviceSync() error!");
cudaDeviceSynchronize();
end = chrono::high_resolution_clock::now();
cout << "Computation + read test data: " << chrono::duration_cast<chrono::milliseconds>(end - kernel_start).count() << " ms\n";
cout << "\t--------------------\n";
end = chrono::high_resolution_clock::now();
ofstream os("output.txt");
for (int stream = 0; stream < streamCount; stream++) {
for (int i = 0; i < numPointsTest / streamCount; i++) {
os << h_nearestNeighbors[stream][i] << endl;
}
}
end = chrono::high_resolution_clock::now();
cout << "\t--------------------\nTotal time: " << chrono::duration_cast<chrono::milliseconds>(end - begin).count() << " ms\nterminating\n";
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <fstream>
#include <string>
#include <cmath>
#include <climits>
#include <iostream>
#include <chrono>
using namespace std;
#define MAX_THREAD_PER_BLOCK 512
#define DEBUG_PRINT
/*
PARALLEL NN - VERSION 2
*/
typedef unsigned short int usint;
const usint num_dimensions = 16;
const usint numPointsTest = 1000;
const usint numPointsTrain = 19000;
const usint streamCount = 4;
struct Coordinates {
usint points[num_dimensions];
};
__device__ float getDistance(const Coordinates & coord1, const Coordinates & coord2) {
float square_sum = 0;
for (int i = 0; i < num_dimensions; i++) {
const int c1 = coord1.points[i];
const int c2 = coord2.points[i];
square_sum += (c1 - c2)*(c1 - c2);
}
return sqrt(square_sum);
}
__global__ void nearestNeighbor(Coordinates * trainCoords, Coordinates * testCoords, const usint sizeTest, const usint sizeTrain, usint * nearestNeighbors) {
const usint threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (threadId < sizeTest) { // DEBUG
usint nearestNeighbor = 0;
usint nearestDistance = USHRT_MAX;
for (int trainCoordInd = 0; trainCoordInd < sizeTrain; trainCoordInd++) {
float currentDistance = getDistance(trainCoords[trainCoordInd], testCoords[threadId]);
if (currentDistance < nearestDistance) {
nearestNeighbor = trainCoordInd;
nearestDistance = currentDistance;
}
}
nearestNeighbors[threadId] = nearestNeighbor;
}
}
bool checkError(const hipError_t & error, const char * msg = "") {
if (error != hipSuccess) {
printf("CUDA ERROR: %s\n", msg);
cout << error << endl;
exit(1);
}
return true;
}
int main() {
// 1 - INITIALIZE READ STREAMS
const char * testFile = "test.txt";
const char * trainFile = "train.txt";
FILE * test_is = fopen(testFile, "r"), * train_is = fopen(trainFile, "r");
if (!test_is) {
cerr << "Cannot open " << testFile << endl;
exit(1);
}
if (!train_is) {
cerr << "Cannot open " << trainFile << endl;
exit(1);
}
hipSetDevice(0); // initialize CUDA context
cout << "\t--------------------\n";
chrono::high_resolution_clock::time_point begin = chrono::high_resolution_clock::now(), temp, end;
// 2 - SET EXECUTION PARAMETERS
hipStream_t streams[streamCount]; // create four CUDA streams
hipError_t hipError_t;
usint numThreadsPerBlock = numPointsTest;
usint numBlocks = 1;
if (numPointsTest > MAX_THREAD_PER_BLOCK) {
numBlocks = std::ceil(static_cast<double>(numPointsTest) / MAX_THREAD_PER_BLOCK);
numThreadsPerBlock = MAX_THREAD_PER_BLOCK;
}
numThreadsPerBlock /= streamCount;
cout << "Kernels will be called with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each\n";
// 3 - READ TRAIN COORDINATES FROM FILE STREAMS
// device pointers
Coordinates * d_testCoordinates[streamCount], *d_trainCoordinates;
usint * d_nearestNeighbors[streamCount];
// host pointers
Coordinates * h_testCoordinates[streamCount], *h_trainCoordinates;
usint * h_nearestNeighbors[streamCount];
hipError_t = hipHostMalloc((void**)&h_trainCoordinates, numPointsTrain * sizeof(Coordinates), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_trainCoordinates");
// read train points to host
for (int i = 0; i < numPointsTrain; i++) {
fscanf(train_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", &h_trainCoordinates[i].points[0], &h_trainCoordinates[i].points[1], &h_trainCoordinates[i].points[2],
&h_trainCoordinates[i].points[3], &h_trainCoordinates[i].points[4], &h_trainCoordinates[i].points[5], &h_trainCoordinates[i].points[6], &h_trainCoordinates[i].points[7],
&h_trainCoordinates[i].points[8], &h_trainCoordinates[i].points[9], &h_trainCoordinates[i].points[10], &h_trainCoordinates[i].points[11], &h_trainCoordinates[i].points[12],
&h_trainCoordinates[i].points[13], &h_trainCoordinates[i].points[14], &h_trainCoordinates[i].points[15]);
}
cout << "done reading training coordinates to host pinned memory" << endl;
// copy train coordinates to device
hipError_t = hipMalloc((void**)&d_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(hipError_t, "hipMalloc - d_trainCoordinates");
hipError_t = hipMemcpy(d_trainCoordinates, h_trainCoordinates, numPointsTrain * sizeof(Coordinates), hipMemcpyHostToDevice);
checkError(hipError_t, "hipMemcpyAsync - d_trainCoordinates");
chrono::high_resolution_clock::time_point kernel_start = chrono::high_resolution_clock::now();
for (usint stream = 0; stream < streamCount; stream++) {
// 1 - create stream
hipStreamCreate(&streams[stream]);
// 2 - Host memory - allocate memory on host for results and test coordinates
hipError_t = hipHostMalloc((void**)&h_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_nearestneighbors");
hipError_t = hipHostMalloc((void**)&h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_testCoordinates");
// 3 - Host memory - read test points
for (int i = 0; i < numPointsTest / streamCount; i++) {
fscanf(test_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", &h_testCoordinates[stream][i].points[0], &h_testCoordinates[stream][i].points[1], &h_testCoordinates[stream][i].points[2],
&h_testCoordinates[stream][i].points[3], &h_testCoordinates[stream][i].points[4], &h_testCoordinates[stream][i].points[5], &h_testCoordinates[stream][i].points[6], &h_testCoordinates[stream][i].points[7],
&h_testCoordinates[stream][i].points[8], &h_testCoordinates[stream][i].points[9], &h_testCoordinates[stream][i].points[10], &h_testCoordinates[stream][i].points[11], &h_testCoordinates[stream][i].points[12],
&h_testCoordinates[stream][i].points[13], &h_testCoordinates[stream][i].points[14], &h_testCoordinates[stream][i].points[15]);
}
// 4 - Device memory - allocate space for test coordiantes and result array for this stream to write its results to
hipError_t = hipMalloc((void**)&d_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(hipError_t, "hipMalloc - d_testCoordiantes");
hipError_t = hipMalloc((void**)&d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(hipError_t, "hipMalloc - d_nearestNeighbors");
// 5 - copy test coordinates to device in async
temp = chrono::high_resolution_clock::now();
hipError_t = hipMemcpyAsync(d_testCoordinates[stream], h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), hipMemcpyHostToDevice, streams[stream]);
checkError(hipError_t, "hipMemcpy - d_testCoordinates");
end = chrono::high_resolution_clock::now();
cout << "data copied to device memory [" << chrono::duration_cast<chrono::milliseconds>(end - temp).count() << " ms]\n"
<< "executing kernel with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each" << endl;
// 6 - Inovke kernel for current stream
usint *& currentResultArray = d_nearestNeighbors[stream];
nearestNeighbor<<< numBlocks, numThreadsPerBlock, 0, streams[stream] >>>(d_trainCoordinates, d_testCoordinates[stream], numPointsTest / streamCount, numPointsTrain, currentResultArray);
hipError_t = hipMemcpyAsync(h_nearestNeighbors[stream], d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), hipMemcpyDeviceToHost, streams[stream]);
checkError(hipError_t, "hipMemcpy - h_nearestNeighbors");
}
// Wait for GPU to terminate and fetch results
hipError_t = hipGetLastError();
checkError(hipError_t, "before deviceSync() error!");
hipDeviceSynchronize();
end = chrono::high_resolution_clock::now();
cout << "Computation + read test data: " << chrono::duration_cast<chrono::milliseconds>(end - kernel_start).count() << " ms\n";
cout << "\t--------------------\n";
end = chrono::high_resolution_clock::now();
ofstream os("output.txt");
for (int stream = 0; stream < streamCount; stream++) {
for (int i = 0; i < numPointsTest / streamCount; i++) {
os << h_nearestNeighbors[stream][i] << endl;
}
}
end = chrono::high_resolution_clock::now();
cout << "\t--------------------\nTotal time: " << chrono::duration_cast<chrono::milliseconds>(end - begin).count() << " ms\nterminating\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <fstream>
#include <string>
#include <cmath>
#include <climits>
#include <iostream>
#include <chrono>
using namespace std;
#define MAX_THREAD_PER_BLOCK 512
#define DEBUG_PRINT
/*
PARALLEL NN - VERSION 2
*/
typedef unsigned short int usint;
const usint num_dimensions = 16;
const usint numPointsTest = 1000;
const usint numPointsTrain = 19000;
const usint streamCount = 4;
struct Coordinates {
usint points[num_dimensions];
};
__device__ float getDistance(const Coordinates & coord1, const Coordinates & coord2) {
float square_sum = 0;
for (int i = 0; i < num_dimensions; i++) {
const int c1 = coord1.points[i];
const int c2 = coord2.points[i];
square_sum += (c1 - c2)*(c1 - c2);
}
return sqrt(square_sum);
}
__global__ void nearestNeighbor(Coordinates * trainCoords, Coordinates * testCoords, const usint sizeTest, const usint sizeTrain, usint * nearestNeighbors) {
const usint threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (threadId < sizeTest) { // DEBUG
usint nearestNeighbor = 0;
usint nearestDistance = USHRT_MAX;
for (int trainCoordInd = 0; trainCoordInd < sizeTrain; trainCoordInd++) {
float currentDistance = getDistance(trainCoords[trainCoordInd], testCoords[threadId]);
if (currentDistance < nearestDistance) {
nearestNeighbor = trainCoordInd;
nearestDistance = currentDistance;
}
}
nearestNeighbors[threadId] = nearestNeighbor;
}
}
bool checkError(const hipError_t & error, const char * msg = "") {
if (error != hipSuccess) {
printf("CUDA ERROR: %s\n", msg);
cout << error << endl;
exit(1);
}
return true;
}
int main() {
// 1 - INITIALIZE READ STREAMS
const char * testFile = "test.txt";
const char * trainFile = "train.txt";
FILE * test_is = fopen(testFile, "r"), * train_is = fopen(trainFile, "r");
if (!test_is) {
cerr << "Cannot open " << testFile << endl;
exit(1);
}
if (!train_is) {
cerr << "Cannot open " << trainFile << endl;
exit(1);
}
hipSetDevice(0); // initialize CUDA context
cout << "\t--------------------\n";
chrono::high_resolution_clock::time_point begin = chrono::high_resolution_clock::now(), temp, end;
// 2 - SET EXECUTION PARAMETERS
hipStream_t streams[streamCount]; // create four CUDA streams
hipError_t hipError_t;
usint numThreadsPerBlock = numPointsTest;
usint numBlocks = 1;
if (numPointsTest > MAX_THREAD_PER_BLOCK) {
numBlocks = std::ceil(static_cast<double>(numPointsTest) / MAX_THREAD_PER_BLOCK);
numThreadsPerBlock = MAX_THREAD_PER_BLOCK;
}
numThreadsPerBlock /= streamCount;
cout << "Kernels will be called with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each\n";
// 3 - READ TRAIN COORDINATES FROM FILE STREAMS
// device pointers
Coordinates * d_testCoordinates[streamCount], *d_trainCoordinates;
usint * d_nearestNeighbors[streamCount];
// host pointers
Coordinates * h_testCoordinates[streamCount], *h_trainCoordinates;
usint * h_nearestNeighbors[streamCount];
hipError_t = hipHostMalloc((void**)&h_trainCoordinates, numPointsTrain * sizeof(Coordinates), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_trainCoordinates");
// read train points to host
for (int i = 0; i < numPointsTrain; i++) {
fscanf(train_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", &h_trainCoordinates[i].points[0], &h_trainCoordinates[i].points[1], &h_trainCoordinates[i].points[2],
&h_trainCoordinates[i].points[3], &h_trainCoordinates[i].points[4], &h_trainCoordinates[i].points[5], &h_trainCoordinates[i].points[6], &h_trainCoordinates[i].points[7],
&h_trainCoordinates[i].points[8], &h_trainCoordinates[i].points[9], &h_trainCoordinates[i].points[10], &h_trainCoordinates[i].points[11], &h_trainCoordinates[i].points[12],
&h_trainCoordinates[i].points[13], &h_trainCoordinates[i].points[14], &h_trainCoordinates[i].points[15]);
}
cout << "done reading training coordinates to host pinned memory" << endl;
// copy train coordinates to device
hipError_t = hipMalloc((void**)&d_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(hipError_t, "hipMalloc - d_trainCoordinates");
hipError_t = hipMemcpy(d_trainCoordinates, h_trainCoordinates, numPointsTrain * sizeof(Coordinates), hipMemcpyHostToDevice);
checkError(hipError_t, "hipMemcpyAsync - d_trainCoordinates");
chrono::high_resolution_clock::time_point kernel_start = chrono::high_resolution_clock::now();
for (usint stream = 0; stream < streamCount; stream++) {
// 1 - create stream
hipStreamCreate(&streams[stream]);
// 2 - Host memory - allocate memory on host for results and test coordinates
hipError_t = hipHostMalloc((void**)&h_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_nearestneighbors");
hipError_t = hipHostMalloc((void**)&h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_testCoordinates");
// 3 - Host memory - read test points
for (int i = 0; i < numPointsTest / streamCount; i++) {
fscanf(test_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", &h_testCoordinates[stream][i].points[0], &h_testCoordinates[stream][i].points[1], &h_testCoordinates[stream][i].points[2],
&h_testCoordinates[stream][i].points[3], &h_testCoordinates[stream][i].points[4], &h_testCoordinates[stream][i].points[5], &h_testCoordinates[stream][i].points[6], &h_testCoordinates[stream][i].points[7],
&h_testCoordinates[stream][i].points[8], &h_testCoordinates[stream][i].points[9], &h_testCoordinates[stream][i].points[10], &h_testCoordinates[stream][i].points[11], &h_testCoordinates[stream][i].points[12],
&h_testCoordinates[stream][i].points[13], &h_testCoordinates[stream][i].points[14], &h_testCoordinates[stream][i].points[15]);
}
// 4 - Device memory - allocate space for test coordiantes and result array for this stream to write its results to
hipError_t = hipMalloc((void**)&d_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(hipError_t, "hipMalloc - d_testCoordiantes");
hipError_t = hipMalloc((void**)&d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(hipError_t, "hipMalloc - d_nearestNeighbors");
// 5 - copy test coordinates to device in async
temp = chrono::high_resolution_clock::now();
hipError_t = hipMemcpyAsync(d_testCoordinates[stream], h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), hipMemcpyHostToDevice, streams[stream]);
checkError(hipError_t, "hipMemcpy - d_testCoordinates");
end = chrono::high_resolution_clock::now();
cout << "data copied to device memory [" << chrono::duration_cast<chrono::milliseconds>(end - temp).count() << " ms]\n"
<< "executing kernel with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each" << endl;
// 6 - Inovke kernel for current stream
usint *& currentResultArray = d_nearestNeighbors[stream];
nearestNeighbor<<< numBlocks, numThreadsPerBlock, 0, streams[stream] >>>(d_trainCoordinates, d_testCoordinates[stream], numPointsTest / streamCount, numPointsTrain, currentResultArray);
hipError_t = hipMemcpyAsync(h_nearestNeighbors[stream], d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), hipMemcpyDeviceToHost, streams[stream]);
checkError(hipError_t, "hipMemcpy - h_nearestNeighbors");
}
// Wait for GPU to terminate and fetch results
hipError_t = hipGetLastError();
checkError(hipError_t, "before deviceSync() error!");
hipDeviceSynchronize();
end = chrono::high_resolution_clock::now();
cout << "Computation + read test data: " << chrono::duration_cast<chrono::milliseconds>(end - kernel_start).count() << " ms\n";
cout << "\t--------------------\n";
end = chrono::high_resolution_clock::now();
ofstream os("output.txt");
for (int stream = 0; stream < streamCount; stream++) {
for (int i = 0; i < numPointsTest / streamCount; i++) {
os << h_nearestNeighbors[stream][i] << endl;
}
}
end = chrono::high_resolution_clock::now();
cout << "\t--------------------\nTotal time: " << chrono::duration_cast<chrono::milliseconds>(end - begin).count() << " ms\nterminating\n";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15nearestNeighborP11CoordinatesS0_ttPt
.globl _Z15nearestNeighborP11CoordinatesS0_ttPt
.p2align 8
.type _Z15nearestNeighborP11CoordinatesS0_ttPt,@function
_Z15nearestNeighborP11CoordinatesS0_ttPt:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0xffff, v1
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_8
s_lshr_b32 s2, s2, 16
s_mov_b32 s8, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 5, v0
v_mov_b32_e32 v3, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s3, s6, v1
v_add_co_ci_u32_e64 v5, null, s7, 0, s3
v_mov_b32_e32 v1, 0
s_and_b32 s6, 0xffff, s2
.LBB0_3:
v_mov_b32_e32 v6, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v4, s2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v5, vcc_lo
s_add_u32 s10, s4, s2
s_addc_u32 s11, s5, s3
global_load_u16 v9, v2, s[10:11]
global_load_u16 v7, v[7:8], off
s_add_u32 s2, s2, 2
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 32
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v7, v7, v7
v_cvt_f32_i32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, 0x4f800000, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v9, 1, v7
v_fma_f32 v10, -v8, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v9, v7, v6
v_cmp_ge_f32_e64 s2, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v8, s2
v_cmp_lt_f32_e64 s2, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v9, s2
v_mul_f32_e32 v8, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v7, v7, v8 :: v_dual_and_b32 v8, 0xffff, v3
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v7, v8
v_cvt_u32_f32_e32 v8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e32 vcc_lo, v6, v7
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_cndmask_b32_e64 v1, v1, s8, vcc_lo
s_add_i32 s8, s8, 1
s_add_u32 s4, s4, 32
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, s6
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v1, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
global_store_b16 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15nearestNeighborP11CoordinatesS0_ttPt
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15nearestNeighborP11CoordinatesS0_ttPt, .Lfunc_end0-_Z15nearestNeighborP11CoordinatesS0_ttPt
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 2
.value_kind: by_value
- .offset: 18
.size: 2
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15nearestNeighborP11CoordinatesS0_ttPt
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15nearestNeighborP11CoordinatesS0_ttPt.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <fstream>
#include <string>
#include <cmath>
#include <climits>
#include <iostream>
#include <chrono>
using namespace std;
#define MAX_THREAD_PER_BLOCK 512
#define DEBUG_PRINT
/*
PARALLEL NN - VERSION 2
*/
typedef unsigned short int usint;
const usint num_dimensions = 16;
const usint numPointsTest = 1000;
const usint numPointsTrain = 19000;
const usint streamCount = 4;
struct Coordinates {
usint points[num_dimensions];
};
__device__ float getDistance(const Coordinates & coord1, const Coordinates & coord2) {
float square_sum = 0;
for (int i = 0; i < num_dimensions; i++) {
const int c1 = coord1.points[i];
const int c2 = coord2.points[i];
square_sum += (c1 - c2)*(c1 - c2);
}
return sqrt(square_sum);
}
__global__ void nearestNeighbor(Coordinates * trainCoords, Coordinates * testCoords, const usint sizeTest, const usint sizeTrain, usint * nearestNeighbors) {
const usint threadId = blockIdx.x*blockDim.x + threadIdx.x;
if (threadId < sizeTest) { // DEBUG
usint nearestNeighbor = 0;
usint nearestDistance = USHRT_MAX;
for (int trainCoordInd = 0; trainCoordInd < sizeTrain; trainCoordInd++) {
float currentDistance = getDistance(trainCoords[trainCoordInd], testCoords[threadId]);
if (currentDistance < nearestDistance) {
nearestNeighbor = trainCoordInd;
nearestDistance = currentDistance;
}
}
nearestNeighbors[threadId] = nearestNeighbor;
}
}
bool checkError(const hipError_t & error, const char * msg = "") {
if (error != hipSuccess) {
printf("CUDA ERROR: %s\n", msg);
cout << error << endl;
exit(1);
}
return true;
}
int main() {
// 1 - INITIALIZE READ STREAMS
const char * testFile = "test.txt";
const char * trainFile = "train.txt";
FILE * test_is = fopen(testFile, "r"), * train_is = fopen(trainFile, "r");
if (!test_is) {
cerr << "Cannot open " << testFile << endl;
exit(1);
}
if (!train_is) {
cerr << "Cannot open " << trainFile << endl;
exit(1);
}
hipSetDevice(0); // initialize CUDA context
cout << "\t--------------------\n";
chrono::high_resolution_clock::time_point begin = chrono::high_resolution_clock::now(), temp, end;
// 2 - SET EXECUTION PARAMETERS
hipStream_t streams[streamCount]; // create four CUDA streams
hipError_t hipError_t;
usint numThreadsPerBlock = numPointsTest;
usint numBlocks = 1;
if (numPointsTest > MAX_THREAD_PER_BLOCK) {
numBlocks = std::ceil(static_cast<double>(numPointsTest) / MAX_THREAD_PER_BLOCK);
numThreadsPerBlock = MAX_THREAD_PER_BLOCK;
}
numThreadsPerBlock /= streamCount;
cout << "Kernels will be called with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each\n";
// 3 - READ TRAIN COORDINATES FROM FILE STREAMS
// device pointers
Coordinates * d_testCoordinates[streamCount], *d_trainCoordinates;
usint * d_nearestNeighbors[streamCount];
// host pointers
Coordinates * h_testCoordinates[streamCount], *h_trainCoordinates;
usint * h_nearestNeighbors[streamCount];
hipError_t = hipHostMalloc((void**)&h_trainCoordinates, numPointsTrain * sizeof(Coordinates), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_trainCoordinates");
// read train points to host
for (int i = 0; i < numPointsTrain; i++) {
fscanf(train_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n", &h_trainCoordinates[i].points[0], &h_trainCoordinates[i].points[1], &h_trainCoordinates[i].points[2],
&h_trainCoordinates[i].points[3], &h_trainCoordinates[i].points[4], &h_trainCoordinates[i].points[5], &h_trainCoordinates[i].points[6], &h_trainCoordinates[i].points[7],
&h_trainCoordinates[i].points[8], &h_trainCoordinates[i].points[9], &h_trainCoordinates[i].points[10], &h_trainCoordinates[i].points[11], &h_trainCoordinates[i].points[12],
&h_trainCoordinates[i].points[13], &h_trainCoordinates[i].points[14], &h_trainCoordinates[i].points[15]);
}
cout << "done reading training coordinates to host pinned memory" << endl;
// copy train coordinates to device
hipError_t = hipMalloc((void**)&d_trainCoordinates, numPointsTrain * sizeof(Coordinates));
checkError(hipError_t, "hipMalloc - d_trainCoordinates");
hipError_t = hipMemcpy(d_trainCoordinates, h_trainCoordinates, numPointsTrain * sizeof(Coordinates), hipMemcpyHostToDevice);
checkError(hipError_t, "hipMemcpyAsync - d_trainCoordinates");
chrono::high_resolution_clock::time_point kernel_start = chrono::high_resolution_clock::now();
for (usint stream = 0; stream < streamCount; stream++) {
// 1 - create stream
hipStreamCreate(&streams[stream]);
// 2 - Host memory - allocate memory on host for results and test coordinates
hipError_t = hipHostMalloc((void**)&h_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_nearestneighbors");
hipError_t = hipHostMalloc((void**)&h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), hipHostMallocDefault);
checkError(hipError_t, "cudamallochost - h_testCoordinates");
// 3 - Host memory - read test points
for (int i = 0; i < numPointsTest / streamCount; i++) {
fscanf(test_is, "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d", &h_testCoordinates[stream][i].points[0], &h_testCoordinates[stream][i].points[1], &h_testCoordinates[stream][i].points[2],
&h_testCoordinates[stream][i].points[3], &h_testCoordinates[stream][i].points[4], &h_testCoordinates[stream][i].points[5], &h_testCoordinates[stream][i].points[6], &h_testCoordinates[stream][i].points[7],
&h_testCoordinates[stream][i].points[8], &h_testCoordinates[stream][i].points[9], &h_testCoordinates[stream][i].points[10], &h_testCoordinates[stream][i].points[11], &h_testCoordinates[stream][i].points[12],
&h_testCoordinates[stream][i].points[13], &h_testCoordinates[stream][i].points[14], &h_testCoordinates[stream][i].points[15]);
}
// 4 - Device memory - allocate space for test coordiantes and result array for this stream to write its results to
hipError_t = hipMalloc((void**)&d_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates));
checkError(hipError_t, "hipMalloc - d_testCoordiantes");
hipError_t = hipMalloc((void**)&d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint));
checkError(hipError_t, "hipMalloc - d_nearestNeighbors");
// 5 - copy test coordinates to device in async
temp = chrono::high_resolution_clock::now();
hipError_t = hipMemcpyAsync(d_testCoordinates[stream], h_testCoordinates[stream], (numPointsTest / streamCount) * sizeof(Coordinates), hipMemcpyHostToDevice, streams[stream]);
checkError(hipError_t, "hipMemcpy - d_testCoordinates");
end = chrono::high_resolution_clock::now();
cout << "data copied to device memory [" << chrono::duration_cast<chrono::milliseconds>(end - temp).count() << " ms]\n"
<< "executing kernel with " << numBlocks << " blocks with " << numThreadsPerBlock << " threads each" << endl;
// 6 - Inovke kernel for current stream
usint *& currentResultArray = d_nearestNeighbors[stream];
nearestNeighbor<<< numBlocks, numThreadsPerBlock, 0, streams[stream] >>>(d_trainCoordinates, d_testCoordinates[stream], numPointsTest / streamCount, numPointsTrain, currentResultArray);
hipError_t = hipMemcpyAsync(h_nearestNeighbors[stream], d_nearestNeighbors[stream], (numPointsTest / streamCount) * sizeof(usint), hipMemcpyDeviceToHost, streams[stream]);
checkError(hipError_t, "hipMemcpy - h_nearestNeighbors");
}
// Wait for GPU to terminate and fetch results
hipError_t = hipGetLastError();
checkError(hipError_t, "before deviceSync() error!");
hipDeviceSynchronize();
end = chrono::high_resolution_clock::now();
cout << "Computation + read test data: " << chrono::duration_cast<chrono::milliseconds>(end - kernel_start).count() << " ms\n";
cout << "\t--------------------\n";
end = chrono::high_resolution_clock::now();
ofstream os("output.txt");
for (int stream = 0; stream < streamCount; stream++) {
for (int i = 0; i < numPointsTest / streamCount; i++) {
os << h_nearestNeighbors[stream][i] << endl;
}
}
end = chrono::high_resolution_clock::now();
cout << "\t--------------------\nTotal time: " << chrono::duration_cast<chrono::milliseconds>(end - begin).count() << " ms\nterminating\n";
return 0;
} | .text
.file "source2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt # -- Begin function _Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt
.p2align 4, 0x90
.type _Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt,@function
_Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt: # @_Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movw %dx, 6(%rsp)
movw %cx, 4(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 6(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15nearestNeighborP11CoordinatesS0_ttPt, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt, .Lfunc_end0-_Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt
.cfi_endproc
# -- End function
.globl _Z10checkErrorRK10hipError_tPKc # -- Begin function _Z10checkErrorRK10hipError_tPKc
.p2align 4, 0x90
.type _Z10checkErrorRK10hipError_tPKc,@function
_Z10checkErrorRK10hipError_tPKc: # @_Z10checkErrorRK10hipError_tPKc
.cfi_startproc
# %bb.0:
cmpl $0, (%rdi)
jne .LBB1_2
# %bb.1:
movb $1, %al
retq
.LBB1_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z10checkErrorRK10hipError_tPKc, .Lfunc_end1-_Z10checkErrorRK10hipError_tPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $872, %rsp # imm = 0x368
.cfi_def_cfa_offset 928
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
testq %rbx, %rbx
je .LBB2_1
# %bb.4:
movq %rax, %r14
testq %rax, %rax
je .LBB2_5
# %bb.6:
movq %rbx, 112(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq hipSetDevice
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 72(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $2, %esi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $128, %esi
movq %r15, %rdi
callq _ZNSo9_M_insertImEERSoT_
.cfi_escape 0x2e, 0x00
movl $.L.str.8, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
movl $608000, %esi # imm = 0x94700
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.7: # %_Z10checkErrorRK10hipError_tPKc.exit.preheader
movl $30, %r15d
.p2align 4, 0x90
.LBB2_8: # %_Z10checkErrorRK10hipError_tPKc.exit
# =>This Inner Loop Header: Depth=1
movq 56(%rsp), %rax
leaq (%rax,%r15), %rbp
leaq (%rax,%r15), %rdx
addq $-30, %rdx
leaq -28(%rax,%r15), %rcx
leaq -26(%rax,%r15), %r8
leaq -24(%rax,%r15), %r9
leaq -22(%rax,%r15), %rsi
movq %rsi, 48(%rsp) # 8-byte Spill
leaq -20(%rax,%r15), %rsi
movq %rsi, 40(%rsp) # 8-byte Spill
leaq -18(%rax,%r15), %rsi
movq %rsi, 32(%rsp) # 8-byte Spill
leaq -16(%rax,%r15), %rsi
movq %rsi, 24(%rsp) # 8-byte Spill
leaq -14(%rax,%r15), %rsi
movq %rsi, 16(%rsp) # 8-byte Spill
leaq -12(%rax,%r15), %rsi
movq %rsi, 8(%rsp) # 8-byte Spill
leaq -10(%rax,%r15), %r11
leaq -8(%rax,%r15), %r12
leaq -6(%rax,%r15), %r13
leaq -4(%rax,%r15), %rbx
leaq -2(%rax,%r15), %r10
.cfi_escape 0x2e, 0x60
movl $.L.str.10, %esi
movq %r14, %rdi
xorl %eax, %eax
pushq %rbp
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
pushq %rbx
.cfi_adjust_cfa_offset 8
pushq %r13
.cfi_adjust_cfa_offset 8
pushq %r12
.cfi_adjust_cfa_offset 8
pushq %r11
.cfi_adjust_cfa_offset 8
pushq 56(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 72(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 88(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 104(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 120(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 136(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
callq __isoc23_fscanf
addq $96, %rsp
.cfi_adjust_cfa_offset -96
addq $32, %r15
cmpq $608030, %r15 # imm = 0x9471E
jne .LBB2_8
# %bb.9:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $55, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_65
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_14
# %bb.11:
movzbl 67(%rbx), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
movl $608000, %esi # imm = 0x94700
callq hipMalloc
testl %eax, %eax
jne .LBB2_16
# %bb.17: # %_Z10checkErrorRK10hipError_tPKc.exit111
movq 64(%rsp), %rdi
movq 56(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $608000, %edx # imm = 0x94700
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_18
# %bb.22: # %_Z10checkErrorRK10hipError_tPKc.exit113
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_23: # =>This Loop Header: Depth=1
# Child Loop BB2_27 Depth 2
leaq (%rsp,%r14,8), %rbx
addq $320, %rbx # imm = 0x140
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq hipStreamCreate
leaq (%rsp,%r14,8), %r15
addq $192, %r15
.cfi_escape 0x2e, 0x00
movl $500, %esi # imm = 0x1F4
movq %r15, %rdi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB2_24
# %bb.25: # %_Z10checkErrorRK10hipError_tPKc.exit117
# in Loop: Header=BB2_23 Depth=1
movq %r15, 88(%rsp) # 8-byte Spill
movq %rbx, 96(%rsp) # 8-byte Spill
movq %r14, 104(%rsp) # 8-byte Spill
leaq (%rsp,%r14,8), %r12
addq $224, %r12
.cfi_escape 0x2e, 0x00
movl $8000, %esi # imm = 0x1F40
movq %r12, %rdi
xorl %edx, %edx
callq hipHostMalloc
testl %eax, %eax
jne .LBB2_67
# %bb.26: # %_Z10checkErrorRK10hipError_tPKc.exit119.preheader
# in Loop: Header=BB2_23 Depth=1
movl $30, %ebx
movq %r12, 8(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_27: # %_Z10checkErrorRK10hipError_tPKc.exit119
# Parent Loop BB2_23 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12), %rax
leaq (%rax,%rbx), %r14
leaq (%rax,%rbx), %rdx
addq $-30, %rdx
leaq -28(%rax,%rbx), %rcx
leaq -26(%rax,%rbx), %r8
leaq -24(%rax,%rbx), %r9
leaq -22(%rax,%rbx), %rsi
movq %rsi, 48(%rsp) # 8-byte Spill
leaq -20(%rax,%rbx), %rsi
movq %rsi, 40(%rsp) # 8-byte Spill
leaq -18(%rax,%rbx), %rsi
movq %rsi, 32(%rsp) # 8-byte Spill
leaq -16(%rax,%rbx), %rsi
movq %rsi, 24(%rsp) # 8-byte Spill
leaq -14(%rax,%rbx), %rsi
movq %rsi, 16(%rsp) # 8-byte Spill
leaq -12(%rax,%rbx), %r12
leaq -10(%rax,%rbx), %r10
leaq -8(%rax,%rbx), %r11
leaq -6(%rax,%rbx), %r15
leaq -4(%rax,%rbx), %r13
leaq -2(%rax,%rbx), %rbp
.cfi_escape 0x2e, 0x60
movl $.L.str.16, %esi
movq 112(%rsp), %rdi # 8-byte Reload
xorl %eax, %eax
pushq %r14
.cfi_adjust_cfa_offset 8
pushq %rbp
.cfi_adjust_cfa_offset 8
pushq %r13
.cfi_adjust_cfa_offset 8
pushq %r15
.cfi_adjust_cfa_offset 8
pushq %r11
.cfi_adjust_cfa_offset 8
pushq %r10
.cfi_adjust_cfa_offset 8
pushq %r12
movq 64(%rsp), %r12 # 8-byte Reload
.cfi_adjust_cfa_offset 8
pushq 72(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 88(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 104(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 120(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq 136(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
callq __isoc23_fscanf
addq $96, %rsp
.cfi_adjust_cfa_offset -96
addq $32, %rbx
cmpq $8030, %rbx # imm = 0x1F5E
jne .LBB2_27
# %bb.28: # in Loop: Header=BB2_23 Depth=1
movq 104(%rsp), %r14 # 8-byte Reload
leaq (%rsp,%r14,8), %r13
addq $288, %r13 # imm = 0x120
.cfi_escape 0x2e, 0x00
movl $8000, %esi # imm = 0x1F40
movq %r13, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB2_29
# %bb.30: # %_Z10checkErrorRK10hipError_tPKc.exit121
# in Loop: Header=BB2_23 Depth=1
leaq (%rsp,%r14,8), %r15
addq $256, %r15 # imm = 0x100
.cfi_escape 0x2e, 0x00
movl $500, %esi # imm = 0x1F4
movq %r15, %rdi
callq hipMalloc
testl %eax, %eax
movq 96(%rsp), %rbp # 8-byte Reload
jne .LBB2_31
# %bb.32: # %_Z10checkErrorRK10hipError_tPKc.exit123
# in Loop: Header=BB2_23 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
movq (%r13), %rdi
movq (%r12), %rsi
movq (%rbp), %r8
.cfi_escape 0x2e, 0x00
movl $8000, %edx # imm = 0x1F40
movl $1, %ecx
callq hipMemcpyAsync
testl %eax, %eax
jne .LBB2_33
# %bb.34: # %_Z10checkErrorRK10hipError_tPKc.exit125
# in Loop: Header=BB2_23 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %rbx, %r12
movq %r12, %rax
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.21, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $.L.str.22, %esi
movl $22, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $2, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $128, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.23, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .LBB2_66
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i134
# in Loop: Header=BB2_23 Depth=1
cmpb $0, 56(%rbx)
je .LBB2_37
# %bb.36: # in Loop: Header=BB2_23 Depth=1
movzbl 67(%rbx), %eax
jmp .LBB2_38
.p2align 4, 0x90
.LBB2_37: # in Loop: Header=BB2_23 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit137
# in Loop: Header=BB2_23 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rbp), %r9
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 126(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_40
# %bb.39: # in Loop: Header=BB2_23 Depth=1
movq 64(%rsp), %rax
movq (%r13), %rcx
movq (%r15), %rdx
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movw $250, 6(%rsp)
movw $19000, 4(%rsp) # imm = 0x4A38
movq %rdx, 168(%rsp)
leaq 184(%rsp), %rax
movq %rax, 352(%rsp)
leaq 176(%rsp), %rax
movq %rax, 360(%rsp)
leaq 6(%rsp), %rax
movq %rax, 368(%rsp)
leaq 4(%rsp), %rax
movq %rax, 376(%rsp)
leaq 168(%rsp), %rax
movq %rax, 384(%rsp)
.cfi_escape 0x2e, 0x00
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
.cfi_escape 0x2e, 0x10
movl $_Z15nearestNeighborP11CoordinatesS0_ttPt, %edi
leaq 352(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_40: # %_Z10checkErrorRK10hipError_tPKc.exit129
# in Loop: Header=BB2_23 Depth=1
movq 88(%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
movq (%r15), %rsi
movq (%rbp), %r8
.cfi_escape 0x2e, 0x00
movl $500, %edx # imm = 0x1F4
movl $2, %ecx
callq hipMemcpyAsync
testl %eax, %eax
jne .LBB2_41
# %bb.19: # in Loop: Header=BB2_23 Depth=1
incq %r14
cmpq $4, %r14
jne .LBB2_23
# %bb.20:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
testl %eax, %eax
jne .LBB2_21
# %bb.42: # %_Z10checkErrorRK10hipError_tPKc.exit115
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.26, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq 80(%rsp), %rbx # 8-byte Folded Reload
movq %rbx, %rax
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.cfi_escape 0x2e, 0x00
movl $.L.str.27, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
.cfi_escape 0x2e, 0x00
leaq 352(%rsp), %rbx
movl $.L.str.28, %esi
movq %rbx, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_43: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_44 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_44: # Parent Loop BB2_43 Depth=1
# => This Inner Loop Header: Depth=2
movq 192(%rsp,%r12,8), %rax
movzwl (%rax,%r13,2), %esi
.Ltmp0:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp1:
# %bb.45: # %_ZNSolsEt.exit
# in Loop: Header=BB2_44 Depth=2
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_46
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i139
# in Loop: Header=BB2_44 Depth=2
cmpb $0, 56(%r15)
je .LBB2_55
# %bb.54: # in Loop: Header=BB2_44 Depth=2
movzbl 67(%r15), %eax
jmp .LBB2_57
.p2align 4, 0x90
.LBB2_55: # in Loop: Header=BB2_44 Depth=2
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp3:
# %bb.56: # %.noexc142
# in Loop: Header=BB2_44 Depth=2
movq (%r15), %rax
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp5:
.LBB2_57: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB2_44 Depth=2
.Ltmp6:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp7:
# %bb.58: # %.noexc144
# in Loop: Header=BB2_44 Depth=2
.Ltmp8:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp9:
# %bb.59: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB2_44 Depth=2
incq %r13
cmpq $250, %r13
jne .LBB2_44
# %bb.47: # in Loop: Header=BB2_43 Depth=1
incq %r12
cmpq $4, %r12
jne .LBB2_43
# %bb.48:
.cfi_escape 0x2e, 0x00
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
.Ltmp11:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.29, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp12:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
subq 72(%rsp), %rbx # 8-byte Folded Reload
movq %rbx, %rax
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $18, %rdx
addq %rdx, %rsi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
.Ltmp15:
# %bb.50: # %_ZNSolsEl.exit
.Ltmp16:
.cfi_escape 0x2e, 0x00
movl $.L.str.30, %esi
movl $16, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.51: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit132
.cfi_escape 0x2e, 0x00
leaq 352(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $872, %rsp # imm = 0x368
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_46:
.cfi_def_cfa_offset 928
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp20:
# %bb.52: # %.noexc
.LBB2_66:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_41:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.24, %esi
jmp .LBB2_13
.LBB2_33:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.19, %esi
jmp .LBB2_13
.LBB2_31:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.18, %esi
jmp .LBB2_13
.LBB2_29:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.17, %esi
jmp .LBB2_13
.LBB2_67:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.15, %esi
jmp .LBB2_13
.LBB2_24:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.14, %esi
.LBB2_13:
movl %eax, %ebx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
.cfi_escape 0x2e, 0x00
.LBB2_3:
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.cfi_escape 0x2e, 0x00
movl $1, %edi
callq exit
.LBB2_1:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
jmp .LBB2_2
.LBB2_5:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cerr, %edi
movl $.L.str.4, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %esi
.LBB2_2:
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
.cfi_escape 0x2e, 0x00
jmp .LBB2_3
.LBB2_12:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.9, %esi
jmp .LBB2_13
.LBB2_65:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_16:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.12, %esi
jmp .LBB2_13
.LBB2_18:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.13, %esi
jmp .LBB2_13
.LBB2_21:
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.25, %esi
jmp .LBB2_13
.LBB2_62:
.Ltmp13:
jmp .LBB2_64
.LBB2_63:
.Ltmp18:
jmp .LBB2_64
.LBB2_61: # %.loopexit.split-lp
.Ltmp21:
jmp .LBB2_64
.LBB2_60: # %.loopexit
.Ltmp10:
.LBB2_64:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 352(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp9-.Ltmp0 # Call between .Ltmp0 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp17-.Ltmp14 # Call between .Ltmp14 and .Ltmp17
.uleb128 .Ltmp18-.Lfunc_begin0 # jumps to .Ltmp18
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp19 # Call between .Ltmp19 and .Ltmp20
.uleb128 .Ltmp21-.Lfunc_begin0 # jumps to .Ltmp21
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end2-.Ltmp20 # Call between .Ltmp20 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15nearestNeighborP11CoordinatesS0_ttPt, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15nearestNeighborP11CoordinatesS0_ttPt,@object # @_Z15nearestNeighborP11CoordinatesS0_ttPt
.section .rodata,"a",@progbits
.globl _Z15nearestNeighborP11CoordinatesS0_ttPt
.p2align 3, 0x0
_Z15nearestNeighborP11CoordinatesS0_ttPt:
.quad _Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt
.size _Z15nearestNeighborP11CoordinatesS0_ttPt, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA ERROR: %s\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "test.txt"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "train.txt"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cannot open "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\t--------------------\n"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Kernels will be called with "
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " blocks with "
.size .L.str.7, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " threads each\n"
.size .L.str.8, 15
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cudamallochost - h_trainCoordinates"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d\n"
.size .L.str.10, 64
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "done reading training coordinates to host pinned memory"
.size .L.str.11, 56
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "hipMalloc - d_trainCoordinates"
.size .L.str.12, 31
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpyAsync - d_trainCoordinates"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "cudamallochost - h_nearestneighbors"
.size .L.str.14, 36
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "cudamallochost - h_testCoordinates"
.size .L.str.15, 35
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d"
.size .L.str.16, 63
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "hipMalloc - d_testCoordiantes"
.size .L.str.17, 30
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "hipMalloc - d_nearestNeighbors"
.size .L.str.18, 31
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "hipMemcpy - d_testCoordinates"
.size .L.str.19, 30
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "data copied to device memory ["
.size .L.str.20, 31
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " ms]\n"
.size .L.str.21, 6
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "executing kernel with "
.size .L.str.22, 23
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz " threads each"
.size .L.str.23, 14
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "hipMemcpy - h_nearestNeighbors"
.size .L.str.24, 31
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "before deviceSync() error!"
.size .L.str.25, 27
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Computation + read test data: "
.size .L.str.26, 31
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz " ms\n"
.size .L.str.27, 5
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "output.txt"
.size .L.str.28, 11
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "\t--------------------\nTotal time: "
.size .L.str.29, 35
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz " ms\nterminating\n"
.size .L.str.30, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15nearestNeighborP11CoordinatesS0_ttPt"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__nearestNeighborP11CoordinatesS0_ttPt
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z15nearestNeighborP11CoordinatesS0_ttPt
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15nearestNeighborP11CoordinatesS0_ttPt
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR4, 0xffff ; /* 0x0000ffff00047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0xc0, !UPT ; /* 0x0000000504047292 */
/* 0x000fe2000f8ec03f */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ LOP3.LUT R0, R0, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff00007812 */
/* 0x000fc800078ec0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.U16 UR6, c[0x0][0x172] ; /* 0x00005c8000067ab9 */
/* 0x000fe40000000400 */
/*00b0*/ UPRMT UR4, UR6, 0x9910, URZ ; /* 0x0000991006047896 */
/* 0x000fcc000800003f */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*00e0*/ @!P0 BRA 0x930 ; /* 0x0000084000008947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff037435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0110*/ LDG.E.U16 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000168000c1e1500 */
/*0120*/ LDG.E.U16 R7, [R2.64+0x2] ; /* 0x0000020402077981 */
/* 0x000168000c1e1500 */
/*0130*/ LDG.E.U16 R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000168000c1e1500 */
/*0140*/ LDG.E.U16 R9, [R2.64+0x6] ; /* 0x0000060402097981 */
/* 0x000168000c1e1500 */
/*0150*/ LDG.E.U16 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000168000c1e1500 */
/*0160*/ LDG.E.U16 R11, [R2.64+0xa] ; /* 0x00000a04020b7981 */
/* 0x000168000c1e1500 */
/*0170*/ LDG.E.U16 R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000168000c1e1500 */
/*0180*/ LDG.E.U16 R13, [R2.64+0xe] ; /* 0x00000e04020d7981 */
/* 0x000168000c1e1500 */
/*0190*/ LDG.E.U16 R14, [R2.64+0x10] ; /* 0x00001004020e7981 */
/* 0x000168000c1e1500 */
/*01a0*/ LDG.E.U16 R15, [R2.64+0x12] ; /* 0x00001204020f7981 */
/* 0x000168000c1e1500 */
/*01b0*/ LDG.E.U16 R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000168000c1e1500 */
/*01c0*/ LDG.E.U16 R17, [R2.64+0x16] ; /* 0x0000160402117981 */
/* 0x000168000c1e1500 */
/*01d0*/ LDG.E.U16 R18, [R2.64+0x18] ; /* 0x0000180402127981 */
/* 0x000168000c1e1500 */
/*01e0*/ LDG.E.U16 R19, [R2.64+0x1a] ; /* 0x00001a0402137981 */
/* 0x000168000c1e1500 */
/*01f0*/ LDG.E.U16 R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000168000c1e1500 */
/*0200*/ LDG.E.U16 R21, [R2.64+0x1e] ; /* 0x00001e0402157981 */
/* 0x000162000c1e1500 */
/*0210*/ MOV R24, 0xffff ; /* 0x0000ffff00187802 */
/* 0x000fe20000000f00 */
/*0220*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0230*/ MOV R5, c[0x0][0x160] ; /* 0x0000580000057a02 */
/* 0x000fc40000000f00 */
/*0240*/ PRMT R24, RZ, 0x5410, R24 ; /* 0x00005410ff187816 */
/* 0x000fe40000000018 */
/*0250*/ MOV R26, c[0x0][0x164] ; /* 0x00005900001a7a02 */
/* 0x000fe40000000f00 */
/*0260*/ PRMT R22, RZ, 0x7610, R22 ; /* 0x00007610ff167816 */
/* 0x000fe40000000016 */
/*0270*/ MOV R2, R5 ; /* 0x0000000500027202 */
/* 0x001fe40000000f00 */
/*0280*/ MOV R3, R26 ; /* 0x0000001a00037202 */
/* 0x000fca0000000f00 */
/*0290*/ LDG.E.U16 R26, [R2.64+0x2] ; /* 0x00000204021a7981 */
/* 0x000ea8000c1e1500 */
/*02a0*/ LDG.E.U16 R25, [R2.64] ; /* 0x0000000402197981 */
/* 0x000ee8000c1e1500 */
/*02b0*/ LDG.E.U16 R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000f28000c1e1500 */
/*02c0*/ LDG.E.U16 R4, [R2.64+0x6] ; /* 0x0000060402047981 */
/* 0x000f22000c1e1500 */
/*02d0*/ IMAD.IADD R26, R26, 0x1, -R7 ; /* 0x000000011a1a7824 */
/* 0x024fe200078e0a07 */
/*02e0*/ IADD3 R25, -R6, R25, RZ ; /* 0x0000001906197210 */
/* 0x008fc60007ffe1ff */
/*02f0*/ IMAD R28, R26, R26, RZ ; /* 0x0000001a1a1c7224 */
/* 0x000fe200078e02ff */
/*0300*/ IADD3 R26, -R8, R5, RZ ; /* 0x00000005081a7210 */
/* 0x010fe20007ffe1ff */
/*0310*/ IMAD R27, R25, R25, RZ ; /* 0x00000019191b7224 */
/* 0x000fe200078e02ff */
/*0320*/ LDG.E.U16 R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000ea6000c1e1500 */
/*0330*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000fe20000201400 */
/*0340*/ IMAD R29, R26, R26, RZ ; /* 0x0000001a1a1d7224 */
/* 0x000fce00078e02ff */
/*0350*/ I2F R25, R27 ; /* 0x0000001b00197306 */
/* 0x000e220000201400 */
/*0360*/ IADD3 R4, -R9, R4, RZ ; /* 0x0000000409047210 */
/* 0x000fce0007ffe1ff */
/*0370*/ I2F R26, R29 ; /* 0x0000001d001a7306 */
/* 0x000e620000201400 */
/*0380*/ IMAD R4, R4, R4, RZ ; /* 0x0000000404047224 */
/* 0x000fe400078e02ff */
/*0390*/ FADD R25, R25, R28 ; /* 0x0000001c19197221 */
/* 0x001fca0000000000 */
/*03a0*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e220000201400 */
/*03b0*/ FADD R25, R25, R26 ; /* 0x0000001a19197221 */
/* 0x002fe40000000000 */
/*03c0*/ LDG.E.U16 R26, [R2.64+0xa] ; /* 0x00000a04021a7981 */
/* 0x000ee4000c1e1500 */
/*03d0*/ FADD R27, R25, R4 ; /* 0x00000004191b7221 */
/* 0x001fe40000000000 */
/*03e0*/ LDG.E.U16 R25, [R2.64+0xc] ; /* 0x00000c0402197981 */
/* 0x000f28000c1e1500 */
/*03f0*/ LDG.E.U16 R4, [R2.64+0xe] ; /* 0x00000e0402047981 */
/* 0x000f22000c1e1500 */
/*0400*/ IADD3 R5, -R10, R5, RZ ; /* 0x000000050a057210 */
/* 0x004fca0007ffe1ff */
/*0410*/ IMAD R28, R5, R5, RZ ; /* 0x00000005051c7224 */
/* 0x000fe400078e02ff */
/*0420*/ LDG.E.U16 R5, [R2.64+0x10] ; /* 0x0000100402057981 */
/* 0x000ea8000c1e1500 */
/*0430*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000e220000201400 */
/*0440*/ IADD3 R26, -R11, R26, RZ ; /* 0x0000001a0b1a7210 */
/* 0x008fca0007ffe1ff */
/*0450*/ IMAD R29, R26, R26, RZ ; /* 0x0000001a1a1d7224 */
/* 0x000fc800078e02ff */
/*0460*/ I2F R26, R29 ; /* 0x0000001d001a7306 */
/* 0x000e620000201400 */
/*0470*/ IADD3 R25, -R12, R25, RZ ; /* 0x000000190c197210 */
/* 0x010fe20007ffe1ff */
/*0480*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x001fc80000000000 */
/*0490*/ IMAD R25, R25, R25, RZ ; /* 0x0000001919197224 */
/* 0x000fe400078e02ff */
/*04a0*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x002fe40000000000 */
/*04b0*/ I2F R26, R25 ; /* 0x00000019001a7306 */
/* 0x0000620000201400 */
/*04c0*/ IADD3 R4, -R13, R4, RZ ; /* 0x000000040d047210 */
/* 0x000fe20007ffe1ff */
/*04d0*/ LDG.E.U16 R25, [R2.64+0x14] ; /* 0x0000140402197981 */
/* 0x001ee2000c1e1500 */
/*04e0*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x002fc60000000000 */
/*04f0*/ LDG.E.U16 R26, [R2.64+0x12] ; /* 0x00001204021a7981 */
/* 0x000f22000c1e1500 */
/*0500*/ IMAD R28, R4, R4, RZ ; /* 0x00000004041c7224 */
/* 0x000fc600078e02ff */
/*0510*/ LDG.E.U16 R4, [R2.64+0x16] ; /* 0x0000160402047981 */
/* 0x000f26000c1e1500 */
/*0520*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000e240000201400 */
/*0530*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x001fe40000000000 */
/*0540*/ IMAD.IADD R5, R5, 0x1, -R14 ; /* 0x0000000105057824 */
/* 0x004fc800078e0a0e */
/*0550*/ IMAD R29, R5, R5, RZ ; /* 0x00000005051d7224 */
/* 0x000fe400078e02ff */
/*0560*/ LDG.E.U16 R5, [R2.64+0x18] ; /* 0x0000180402057981 */
/* 0x000ea8000c1e1500 */
/*0570*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x000e240000201400 */
/*0580*/ FADD R27, R27, R29 ; /* 0x0000001d1b1b7221 */
/* 0x001fe20000000000 */
/*0590*/ IADD3 R25, -R16, R25, RZ ; /* 0x0000001910197210 */
/* 0x008fe40007ffe1ff */
/*05a0*/ IADD3 R26, -R15, R26, RZ ; /* 0x0000001a0f1a7210 */
/* 0x010fc60007ffe1ff */
/*05b0*/ IMAD R28, R25, R25, RZ ; /* 0x00000019191c7224 */
/* 0x000fe400078e02ff */
/*05c0*/ LDG.E.U16 R25, [R2.64+0x1c] ; /* 0x00001c0402197981 */
/* 0x000ee2000c1e1500 */
/*05d0*/ IMAD R26, R26, R26, RZ ; /* 0x0000001a1a1a7224 */
/* 0x000fe200078e02ff */
/*05e0*/ IADD3 R4, -R17, R4, RZ ; /* 0x0000000411047210 */
/* 0x000fe40007ffe1ff */
/*05f0*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000fe60000201400 */
/*0600*/ IMAD R29, R4, R4, RZ ; /* 0x00000004041d7224 */
/* 0x000fca00078e02ff */
/*0610*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e300000201400 */
/*0620*/ I2F R4, R29 ; /* 0x0000001d00047306 */
/* 0x000e620000201400 */
/*0630*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x001fe40000000000 */
/*0640*/ LDG.E.U16 R26, [R2.64+0x1a] ; /* 0x00001a04021a7981 */
/* 0x000f24000c1e1500 */
/*0650*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x000fc80000000000 */
/*0660*/ FADD R27, R27, R4 ; /* 0x000000041b1b7221 */
/* 0x002fe40000000000 */
/*0670*/ LDG.E.U16 R4, [R2.64+0x1e] ; /* 0x00001e0402047981 */
/* 0x000f22000c1e1500 */
/*0680*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fe20007ffe0ff */
/*0690*/ BSSY B0, 0x880 ; /* 0x000001e000007945 */
/* 0x000fe60003800000 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R23, UR6, PT ; /* 0x0000000617007c0c */
/* 0x000fe4000bf06070 */
/*06b0*/ IADD3 R5, -R18, R5, RZ ; /* 0x0000000512057210 */
/* 0x004fca0007ffe1ff */
/*06c0*/ IMAD R5, R5, R5, RZ ; /* 0x0000000505057224 */
/* 0x000fcc00078e02ff */
/*06d0*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e240000201400 */
/*06e0*/ FADD R27, R27, R5 ; /* 0x000000051b1b7221 */
/* 0x001fe20000000000 */
/*06f0*/ IADD3 R25, -R20, R25, RZ ; /* 0x0000001914197210 */
/* 0x008fe40007ffe1ff */
/*0700*/ IADD3 R26, -R19, R26, RZ ; /* 0x0000001a131a7210 */
/* 0x010fca0007ffe1ff */
/*0710*/ IMAD R26, R26, R26, RZ ; /* 0x0000001a1a1a7224 */
/* 0x000fe200078e02ff */
/*0720*/ IADD3 R28, -R21, R4, RZ ; /* 0x00000004151c7210 */
/* 0x000fe20007ffe1ff */
/*0730*/ IMAD R4, R25, R25, RZ ; /* 0x0000001919047224 */
/* 0x000fc800078e02ff */
/*0740*/ I2F R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000e220000201400 */
/*0750*/ IMAD R28, R28, R28, RZ ; /* 0x0000001c1c1c7224 */
/* 0x000fce00078e02ff */
/*0760*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e700000201400 */
/*0770*/ I2F R28, R28 ; /* 0x0000001c001c7306 */
/* 0x000ea20000201400 */
/*0780*/ FADD R27, R27, R26 ; /* 0x0000001a1b1b7221 */
/* 0x001fc80000000000 */
/*0790*/ FADD R27, R27, R4 ; /* 0x000000041b1b7221 */
/* 0x002fc80000000000 */
/*07a0*/ FADD R27, R27, R28 ; /* 0x0000001c1b1b7221 */
/* 0x004fca0000000000 */
/*07b0*/ IADD3 R5, R27, -0xd000000, RZ ; /* 0xf30000001b057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ MUFU.RSQ R26, R27 ; /* 0x0000001b001a7308 */
/* 0x0000660000001400 */
/*07d0*/ ISETP.GT.U32.AND P1, PT, R5, 0x727fffff, PT ; /* 0x727fffff0500780c */
/* 0x000fda0003f24070 */
/*07e0*/ @!P1 BRA 0x830 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*07f0*/ MOV R4, 0x810 ; /* 0x0000081000047802 */
/* 0x003fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0x980 ; /* 0x0000017000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R4, RZ, RZ, R25 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0019 */
/*0820*/ BRA 0x870 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0830*/ FMUL.FTZ R4, R27, R26 ; /* 0x0000001a1b047220 */
/* 0x003fe40000410000 */
/*0840*/ FMUL.FTZ R25, R26, 0.5 ; /* 0x3f0000001a197820 */
/* 0x000fe40000410000 */
/*0850*/ FFMA R5, -R4, R4, R27 ; /* 0x0000000404057223 */
/* 0x000fc8000000011b */
/*0860*/ FFMA R4, R5, R25, R4 ; /* 0x0000001905047223 */
/* 0x000fe40000000004 */
/*0870*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0880*/ I2F.U16 R5, R24.H1 ; /* 0x1000001800057306 */
/* 0x000e240000101000 */
/*0890*/ FSETP.GEU.AND P1, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x001fe40003f2e000 */
/*08a0*/ IADD3 R5, P2, R2, 0x20, RZ ; /* 0x0000002002057810 */
/* 0x000fe40007f5e0ff */
/*08b0*/ IADD3 R2, R22, 0x1, RZ ; /* 0x0000000116027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3.X R26, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff1a7210 */
/* 0x000fce00017fe4ff */
/*08d0*/ @!P1 F2I.U32.TRUNC.NTZ R4, R4 ; /* 0x0000000400049305 */
/* 0x000e24000020f000 */
/*08e0*/ @!P1 PRMT R24, R24, 0x5410, R4 ; /* 0x0000541018189816 */
/* 0x001fc80000000004 */
/*08f0*/ @!P1 PRMT R24, R22, 0x7610, R24 ; /* 0x0000761016189816 */
/* 0x000fe40000000018 */
/*0900*/ PRMT R22, R2, 0x7610, R22 ; /* 0x0000761002167816 */
/* 0x000fe20000000016 */
/*0910*/ @!P0 BRA 0x270 ; /* 0xfffff95000008947 */
/* 0x000fea000383ffff */
/*0920*/ BRA 0x940 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0930*/ PRMT R24, RZ, 0x7610, R24 ; /* 0x00007610ff187816 */
/* 0x000fe40000000018 */
/*0940*/ MOV R3, 0x2 ; /* 0x0000000200037802 */
/* 0x000fca0000000f00 */
/*0950*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0003 */
/*0960*/ STG.E.U16 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101504 */
/*0970*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT P1, RZ, R27, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff1bff7812 */
/* 0x000fda000782c0ff */
/*0990*/ @!P1 MOV R25, R27 ; /* 0x0000001b00199202 */
/* 0x000fe20000000f00 */
/*09a0*/ @!P1 BRA 0xac0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*09b0*/ FSETP.GEU.FTZ.AND P1, PT, R27, RZ, PT ; /* 0x000000ff1b00720b */
/* 0x000fe40003f3e000 */
/*09c0*/ MOV R5, R27 ; /* 0x0000001b00057202 */
/* 0x000fd60000000f00 */
/*09d0*/ @!P1 MOV R25, 0x7fffffff ; /* 0x7fffffff00199802 */
/* 0x000fe20000000f00 */
/*09e0*/ @!P1 BRA 0xac0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*09f0*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f3c200 */
/*0a00*/ @P1 FADD.FTZ R25, R5, 1 ; /* 0x3f80000005191421 */
/* 0x000fe20000010000 */
/*0a10*/ @P1 BRA 0xac0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fda0003f3d200 */
/*0a30*/ @P1 FFMA R27, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f800000051b1823 */
/* 0x000fc800000000ff */
/*0a40*/ @P1 MUFU.RSQ R26, R27 ; /* 0x0000001b001a1308 */
/* 0x000e240000001400 */
/*0a50*/ @P1 FMUL.FTZ R25, R27, R26 ; /* 0x0000001a1b191220 */
/* 0x001fe40000410000 */
/*0a60*/ @P1 FMUL.FTZ R26, R26, 0.5 ; /* 0x3f0000001a1a1820 */
/* 0x000fe40000410000 */
/*0a70*/ @P1 FADD.FTZ R28, -R25, -RZ ; /* 0x800000ff191c1221 */
/* 0x000fc80000010100 */
/*0a80*/ @P1 FFMA R28, R25, R28, R27 ; /* 0x0000001c191c1223 */
/* 0x000fc8000000001b */
/*0a90*/ @P1 FFMA R26, R28, R26, R25 ; /* 0x0000001a1c1a1223 */
/* 0x000fe20000000019 */
/*0aa0*/ @!P1 MOV R25, R5 ; /* 0x0000000500199202 */
/* 0x000fc60000000f00 */
/*0ab0*/ @P1 FMUL.FTZ R25, R26, 2.3283064365386962891e-10 ; /* 0x2f8000001a191820 */
/* 0x000fe40000410000 */
/*0ac0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fcc00000001ff */
/*0ad0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff52004007950 */
/* 0x000fea0003c3ffff */
/*0ae0*/ BRA 0xae0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15nearestNeighborP11CoordinatesS0_ttPt
.globl _Z15nearestNeighborP11CoordinatesS0_ttPt
.p2align 8
.type _Z15nearestNeighborP11CoordinatesS0_ttPt,@function
_Z15nearestNeighborP11CoordinatesS0_ttPt:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v0, 0xffff, v1
v_cmp_gt_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_8
s_lshr_b32 s2, s2, 16
s_mov_b32 s8, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 5, v0
v_mov_b32_e32 v3, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s3, s6, v1
v_add_co_ci_u32_e64 v5, null, s7, 0, s3
v_mov_b32_e32 v1, 0
s_and_b32 s6, 0xffff, s2
.LBB0_3:
v_mov_b32_e32 v6, 0
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v4, s2
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v5, vcc_lo
s_add_u32 s10, s4, s2
s_addc_u32 s11, s5, s3
global_load_u16 v9, v2, s[10:11]
global_load_u16 v7, v[7:8], off
s_add_u32 s2, s2, 2
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 32
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_i32_i24_e32 v7, v7, v7
v_cvt_f32_i32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, 0x4f800000, v6
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v9, 1, v7
v_fma_f32 v10, -v8, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v9, v7, v6
v_cmp_ge_f32_e64 s2, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v8, s2
v_cmp_lt_f32_e64 s2, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v9, s2
v_mul_f32_e32 v8, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v7, v7, v8 :: v_dual_and_b32 v8, 0xffff, v3
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
v_cndmask_b32_e32 v6, v7, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v7, v8
v_cvt_u32_f32_e32 v8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_f32_e32 vcc_lo, v6, v7
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_cndmask_b32_e64 v1, v1, s8, vcc_lo
s_add_i32 s8, s8, 1
s_add_u32 s4, s4, 32
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, s6
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v1, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x18
v_lshlrev_b32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
global_store_b16 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15nearestNeighborP11CoordinatesS0_ttPt
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15nearestNeighborP11CoordinatesS0_ttPt, .Lfunc_end0-_Z15nearestNeighborP11CoordinatesS0_ttPt
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 2
.value_kind: by_value
- .offset: 18
.size: 2
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15nearestNeighborP11CoordinatesS0_ttPt
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15nearestNeighborP11CoordinatesS0_ttPt.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
// Kernel function to add the elements of two arrays
__global__ void add(int n, int *x, int *y, int a)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid<n) x[tid] = a*x[tid] + y[tid];
}
int main(void)
{
int dNum = 1<<20;
int *x, *y;
// memory size for each array
size_t memSize = sizeof(int)*dNum;
// unified memory allocation
cudaMallocManaged(&x, memSize);
cudaMallocManaged(&y, memSize);
// initialization in CPU
for(int i=0; i<dNum; i++) { x[i] = 1; y[i] = 2; }
// grid configuration (dNum = numBlocks * numThreads)
int numThreads = 512;
int numBlocks = (dNum + numThreads-1) / numThreads;
// Run kernel on the device
add<<<numBlocks, numThreads>>>(dNum, x, y, 2);
// explicit barrier
cudaDeviceSynchronize();
for(int i=0; i<dNum; i++) if(x[i]!=4) printf("Error!\n");
// Free memory
cudaFree(x); cudaFree(y);
return 0;
} | code for sm_80
Function : _Z3addiPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMAD R7, R0, c[0x0][0x178], R5 ; /* 0x00005e0000077a24 */
/* 0x004fca00078e0205 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
// Kernel function to add the elements of two arrays
__global__ void add(int n, int *x, int *y, int a)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid<n) x[tid] = a*x[tid] + y[tid];
}
int main(void)
{
int dNum = 1<<20;
int *x, *y;
// memory size for each array
size_t memSize = sizeof(int)*dNum;
// unified memory allocation
cudaMallocManaged(&x, memSize);
cudaMallocManaged(&y, memSize);
// initialization in CPU
for(int i=0; i<dNum; i++) { x[i] = 1; y[i] = 2; }
// grid configuration (dNum = numBlocks * numThreads)
int numThreads = 512;
int numBlocks = (dNum + numThreads-1) / numThreads;
// Run kernel on the device
add<<<numBlocks, numThreads>>>(dNum, x, y, 2);
// explicit barrier
cudaDeviceSynchronize();
for(int i=0; i<dNum; i++) if(x[i]!=4) printf("Error!\n");
// Free memory
cudaFree(x); cudaFree(y);
return 0;
} | .file "tmpxft_0002a302_00000000-6_saxpy_unified_mem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addiPiS_iiPiS_i
.type _Z26__device_stub__Z3addiPiS_iiPiS_i, @function
_Z26__device_stub__Z3addiPiS_iiPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addiPiS_iiPiS_i, .-_Z26__device_stub__Z3addiPiS_iiPiS_i
.globl _Z3addiPiS_i
.type _Z3addiPiS_i, @function
_Z3addiPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addiPiS_iiPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPiS_i, .-_Z3addiPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq (%rsp), %rdx
movl $1, (%rdx,%rax)
movq 8(%rsp), %rdx
movl $2, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2048, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
jmp .L15
.L20:
movl $2, %ecx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z3addiPiS_iiPiS_i
jmp .L13
.L14:
addq $4, %rbx
cmpq $4194304, %rbx
je .L21
.L15:
movq (%rsp), %rax
cmpl $4, (%rax,%rbx)
je .L14
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
// Kernel function to add the elements of two arrays
__global__ void add(int n, int *x, int *y, int a)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid<n) x[tid] = a*x[tid] + y[tid];
}
int main(void)
{
int dNum = 1<<20;
int *x, *y;
// memory size for each array
size_t memSize = sizeof(int)*dNum;
// unified memory allocation
cudaMallocManaged(&x, memSize);
cudaMallocManaged(&y, memSize);
// initialization in CPU
for(int i=0; i<dNum; i++) { x[i] = 1; y[i] = 2; }
// grid configuration (dNum = numBlocks * numThreads)
int numThreads = 512;
int numBlocks = (dNum + numThreads-1) / numThreads;
// Run kernel on the device
add<<<numBlocks, numThreads>>>(dNum, x, y, 2);
// explicit barrier
cudaDeviceSynchronize();
for(int i=0; i<dNum; i++) if(x[i]!=4) printf("Error!\n");
// Free memory
cudaFree(x); cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
// Kernel function to add the elements of two arrays
__global__ void add(int n, int *x, int *y, int a)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid<n) x[tid] = a*x[tid] + y[tid];
}
int main(void)
{
int dNum = 1<<20;
int *x, *y;
// memory size for each array
size_t memSize = sizeof(int)*dNum;
// unified memory allocation
hipMallocManaged(&x, memSize);
hipMallocManaged(&y, memSize);
// initialization in CPU
for(int i=0; i<dNum; i++) { x[i] = 1; y[i] = 2; }
// grid configuration (dNum = numBlocks * numThreads)
int numThreads = 512;
int numBlocks = (dNum + numThreads-1) / numThreads;
// Run kernel on the device
add<<<numBlocks, numThreads>>>(dNum, x, y, 2);
// explicit barrier
hipDeviceSynchronize();
for(int i=0; i<dNum; i++) if(x[i]!=4) printf("Error!\n");
// Free memory
hipFree(x); hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
// Kernel function to add the elements of two arrays
__global__ void add(int n, int *x, int *y, int a)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid<n) x[tid] = a*x[tid] + y[tid];
}
int main(void)
{
int dNum = 1<<20;
int *x, *y;
// memory size for each array
size_t memSize = sizeof(int)*dNum;
// unified memory allocation
hipMallocManaged(&x, memSize);
hipMallocManaged(&y, memSize);
// initialization in CPU
for(int i=0; i<dNum; i++) { x[i] = 1; y[i] = 2; }
// grid configuration (dNum = numBlocks * numThreads)
int numThreads = 512;
int numBlocks = (dNum + numThreads-1) / numThreads;
// Run kernel on the device
add<<<numBlocks, numThreads>>>(dNum, x, y, 2);
// explicit barrier
hipDeviceSynchronize();
for(int i=0; i<dNum; i++) if(x[i]!=4) printf("Error!\n");
// Free memory
hipFree(x); hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPiS_i
.globl _Z3addiPiS_i
.p2align 8
.type _Z3addiPiS_i,@function
_Z3addiPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s0, v[0:1]
global_store_b32 v[2:3], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPiS_i, .Lfunc_end0-_Z3addiPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
// Kernel function to add the elements of two arrays
__global__ void add(int n, int *x, int *y, int a)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
if(tid<n) x[tid] = a*x[tid] + y[tid];
}
int main(void)
{
int dNum = 1<<20;
int *x, *y;
// memory size for each array
size_t memSize = sizeof(int)*dNum;
// unified memory allocation
hipMallocManaged(&x, memSize);
hipMallocManaged(&y, memSize);
// initialization in CPU
for(int i=0; i<dNum; i++) { x[i] = 1; y[i] = 2; }
// grid configuration (dNum = numBlocks * numThreads)
int numThreads = 512;
int numBlocks = (dNum + numThreads-1) / numThreads;
// Run kernel on the device
add<<<numBlocks, numThreads>>>(dNum, x, y, 2);
// explicit barrier
hipDeviceSynchronize();
for(int i=0; i<dNum; i++) if(x[i]!=4) printf("Error!\n");
// Free memory
hipFree(x); hipFree(y);
return 0;
} | .text
.file "saxpy_unified_mem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPiS_i # -- Begin function _Z18__device_stub__addiPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__addiPiS_i,@function
_Z18__device_stub__addiPiS_i: # @_Z18__device_stub__addiPiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPiS_i, .Lfunc_end0-_Z18__device_stub__addiPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rax,%rcx,4)
movl $2, (%rdx,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1536(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $2, 24(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
cmpl $4, (%rax,%rbx,4)
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB1_7
.LBB1_8:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPiS_i,@object # @_Z3addiPiS_i
.section .rodata,"a",@progbits
.globl _Z3addiPiS_i
.p2align 3, 0x0
_Z3addiPiS_i:
.quad _Z18__device_stub__addiPiS_i
.size _Z3addiPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiPiS_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error!"
.size .Lstr, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMAD R7, R0, c[0x0][0x178], R5 ; /* 0x00005e0000077a24 */
/* 0x004fca00078e0205 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPiS_i
.globl _Z3addiPiS_i
.p2align 8
.type _Z3addiPiS_i,@function
_Z3addiPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v6, s0, v[0:1]
global_store_b32 v[2:3], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPiS_i, .Lfunc_end0-_Z3addiPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002a302_00000000-6_saxpy_unified_mem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addiPiS_iiPiS_i
.type _Z26__device_stub__Z3addiPiS_iiPiS_i, @function
_Z26__device_stub__Z3addiPiS_iiPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3addiPiS_iiPiS_i, .-_Z26__device_stub__Z3addiPiS_iiPiS_i
.globl _Z3addiPiS_i
.type _Z3addiPiS_i, @function
_Z3addiPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addiPiS_iiPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPiS_i, .-_Z3addiPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq (%rsp), %rdx
movl $1, (%rdx,%rax)
movq 8(%rsp), %rdx
movl $2, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $512, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2048, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
jmp .L15
.L20:
movl $2, %ecx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z3addiPiS_iiPiS_i
jmp .L13
.L14:
addq $4, %rbx
cmpq $4194304, %rbx
je .L21
.L15:
movq (%rsp), %rax
cmpl $4, (%rax,%rbx)
je .L14
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_unified_mem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPiS_i # -- Begin function _Z18__device_stub__addiPiS_i
.p2align 4, 0x90
.type _Z18__device_stub__addiPiS_i,@function
_Z18__device_stub__addiPiS_i: # @_Z18__device_stub__addiPiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPiS_i, .Lfunc_end0-_Z18__device_stub__addiPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rax,%rcx,4)
movl $2, (%rdx,%rcx,4)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1536(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $2, 24(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %rbx
cmpq $1048576, %rbx # imm = 0x100000
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
cmpl $4, (%rax,%rbx,4)
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $.Lstr, %edi
callq puts@PLT
jmp .LBB1_7
.LBB1_8:
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPiS_i,@object # @_Z3addiPiS_i
.section .rodata,"a",@progbits
.globl _Z3addiPiS_i
.p2align 3, 0x0
_Z3addiPiS_i:
.quad _Z18__device_stub__addiPiS_i
.size _Z3addiPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiPiS_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error!"
.size .Lstr, 7
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <iomanip>
#include <cstring>
#include <cmath>
#include <stdlib.h>
#include <sys/time.h>
using namespace std;
//-----------------------DO NOT CHANGE NAMES, ONLY MODIFY VALUES--------------------------------------------
//Final Value that will be compared for correctness
//You need to create the function prototypes and definitions as per your design, but you need to present final results in this array
//-----------------------------Structures for correctness check-------------------
char **fourbit_sorted_suffixes_student;
//--------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
//-----------------------DO NOT CHANGE AT ALL--------------------------------------------
int read_count = 0;
int read_length = 0;
//This array is the default result
char **fourbit_sorted_suffixes_original;
//Read file to get reads
char** inputReads(char *file_path, int *read_count, int *length){
FILE *read_file = fopen(file_path, "r");
int ch, lines=0;
char **reads;
do
{
ch = fgetc(read_file);
if (ch == '\n')
lines++;
} while (ch != EOF);
rewind(read_file);
reads=(char**)malloc(lines*sizeof(char*));
*read_count = lines;
int i = 0;
size_t len = 0;
for(i = 0; i < lines; i++)
{
reads[i] = NULL;
len = 0;
getline(&reads[i], &len, read_file);
}
fclose(read_file);
int j=0;
while(reads[0][j]!='\n')
j++;
*length = j+1;
for(i=0;i<lines;i++)
reads[i][j]='$';
return reads;
}
//Check correctness of values
int checker(){
int correct = 1;
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++){
if(fourbit_sorted_suffixes_student[i][j] != fourbit_sorted_suffixes_original[i][j])
correct = 0;
}
}
return correct;
}
//Rotate 4-bit encoded read by 1 character (4-bit)
char* rotateRead(char *read, int byte_length){
char prev_4bit = (read[0] & 0x0F) << 4;
read[0] = (read[0] >> 4) & 0x0F;
for(int i=1;i<byte_length;i++){
char this_char = ((read[i] >> 4) & 0x0F) | prev_4bit;
prev_4bit = (read[i] & 0x0F) << 4;
read[i] = this_char;
}
read[0]=read[0] | prev_4bit;
char *rotated_read = (char*)malloc(byte_length*sizeof(char));
for(int i=0;i<byte_length;i++)
rotated_read[i] = read[i];
return rotated_read;
}
//Generate Sufixes for a 4-bit encoded read
char** generateSuffixes(char *read, int byte_length){
char **suffixes=(char**)malloc(byte_length*2*sizeof(char*));
for(int i=0;i<byte_length*2;i++){
suffixes[i] = rotateRead(read, byte_length);
}
return suffixes;
}
//Comparator for 4-bit encoded Suffixes
int compSuffixes(char *suffix1, char *suffix2, int byte_length){
int ret = 0;
for(int i=0;i<byte_length;i++){
if(suffix1[i]>suffix2[i])
return 1;
else if(suffix1[i]<suffix2[i])
return -1;
}
return ret;
}
char* fourbitEncodeRead(char *read, int length){
int byte_length = length/2;
char *fourbit_read = (char*)calloc(byte_length,sizeof(char));
for(int i=0;i<length;i++){
char this_char = read[i];
char fourbit_char;
if(this_char == '$')
fourbit_char = 0x00;
else if(this_char == 'A')
fourbit_char = 0x01;
else if(this_char == 'C')
fourbit_char = 0x02;
else if(this_char == 'G')
fourbit_char = 0x03;
else
fourbit_char = 0x04;
fourbit_char = i%2==0 ? fourbit_char << 4 : fourbit_char;
fourbit_read[i/2] = fourbit_read[i/2] | fourbit_char;
}
return fourbit_read;
}
void sort_fourbit_suffixes(char **suffixes, int suffix_count, int byte_length){
char *temp=(char*)malloc(byte_length*sizeof(char));
for(int i=0;i<suffix_count-1;i++){
for(int j=0;j<suffix_count-i-1;j++){
if(compSuffixes(suffixes[j], suffixes[j+1], byte_length)>0){
memcpy(temp, suffixes[j], byte_length*sizeof(char));
memcpy(suffixes[j], suffixes[j+1], byte_length*sizeof(char));
memcpy(suffixes[j+1], temp, byte_length*sizeof(char));
}
}
}
}
//Default Pipeline. You need to implement CUDA function corresponding to everything inside this function
void pipeline(char **reads, int read_length, int read_count){
fourbit_sorted_suffixes_original = (char**)malloc(read_length*read_count*sizeof(char*));
for(int i=0;i<read_count;i++){
char **suffixes_for_read = generateSuffixes(fourbitEncodeRead(reads[i], read_length), read_length/2);
sort_fourbit_suffixes(suffixes_for_read, read_length, read_length/2);
for(int j=0;j<read_length;j++){
fourbit_sorted_suffixes_original[i*read_length+j] = suffixes_for_read[j];
}
}
//--------------For debug purpose--------------
/*
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++)
printf("%x\t",fourbit_sorted_suffixes_original[i][j]);
printf("\n");
}*/
//---------------------------------------------
}
//Merge all sorted suffixes in overall sorted order
void mergeAllSorted4bitSuffixes(char** suffixes, int read_count, int read_length){
}
//-----------------------DO NOT CHANGE--------------------------------------------
int main(int argc, char *argv[]){
char **reads = inputReads(argv[1], &read_count, &read_length);//Input reads from file
//-----------Default implementation----------------
//-----------Time capture start--------------------
struct timeval TimeValue_Start;
struct timeval TimeValue_Final;
struct timezone TimeZone_Start;
struct timezone TimeZone_Final;
long time_start, time_end;
double time_overhead_default, time_overhead_student;
gettimeofday(&TimeValue_Start, &TimeZone_Start);
pipeline(reads, read_length, read_count);
mergeAllSorted4bitSuffixes(fourbit_sorted_suffixes_original, read_count, read_length);
gettimeofday(&TimeValue_Final, &TimeZone_Final);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_default = (time_end - time_start)/1000000.0;
cout<<time_overhead_default<<endl;
//------------Time capture end----------------------
//--------------------------------------------------
//-----------Your implementations------------------
gettimeofday(&TimeValue_Start, &TimeZone_Start);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
//-----------Call your functions here--------------------
//-----------Call your functions here--------------------
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_student = (time_end - time_start)/1000000.0;
//--------------------------------------------------
//---------------Correction check and speedup calculation----------------------
float speedup=0.0;
//if(checker()==1)
// speedup = time_overhead_default/time_overhead_student;
cout<<"Speedup="<<speedup<<endl;
//-----------------------------------------------------------------------------
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <iomanip>
#include <cstring>
#include <cmath>
#include <stdlib.h>
#include <sys/time.h>
using namespace std;
//-----------------------DO NOT CHANGE NAMES, ONLY MODIFY VALUES--------------------------------------------
//Final Value that will be compared for correctness
//You need to create the function prototypes and definitions as per your design, but you need to present final results in this array
//-----------------------------Structures for correctness check-------------------
char **fourbit_sorted_suffixes_student;
//--------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
//-----------------------DO NOT CHANGE AT ALL--------------------------------------------
int read_count = 0;
int read_length = 0;
//This array is the default result
char **fourbit_sorted_suffixes_original;
//Read file to get reads
char** inputReads(char *file_path, int *read_count, int *length){
FILE *read_file = fopen(file_path, "r");
int ch, lines=0;
char **reads;
do
{
ch = fgetc(read_file);
if (ch == '\n')
lines++;
} while (ch != EOF);
rewind(read_file);
reads=(char**)malloc(lines*sizeof(char*));
*read_count = lines;
int i = 0;
size_t len = 0;
for(i = 0; i < lines; i++)
{
reads[i] = NULL;
len = 0;
getline(&reads[i], &len, read_file);
}
fclose(read_file);
int j=0;
while(reads[0][j]!='\n')
j++;
*length = j+1;
for(i=0;i<lines;i++)
reads[i][j]='$';
return reads;
}
//Check correctness of values
int checker(){
int correct = 1;
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++){
if(fourbit_sorted_suffixes_student[i][j] != fourbit_sorted_suffixes_original[i][j])
correct = 0;
}
}
return correct;
}
//Rotate 4-bit encoded read by 1 character (4-bit)
char* rotateRead(char *read, int byte_length){
char prev_4bit = (read[0] & 0x0F) << 4;
read[0] = (read[0] >> 4) & 0x0F;
for(int i=1;i<byte_length;i++){
char this_char = ((read[i] >> 4) & 0x0F) | prev_4bit;
prev_4bit = (read[i] & 0x0F) << 4;
read[i] = this_char;
}
read[0]=read[0] | prev_4bit;
char *rotated_read = (char*)malloc(byte_length*sizeof(char));
for(int i=0;i<byte_length;i++)
rotated_read[i] = read[i];
return rotated_read;
}
//Generate Sufixes for a 4-bit encoded read
char** generateSuffixes(char *read, int byte_length){
char **suffixes=(char**)malloc(byte_length*2*sizeof(char*));
for(int i=0;i<byte_length*2;i++){
suffixes[i] = rotateRead(read, byte_length);
}
return suffixes;
}
//Comparator for 4-bit encoded Suffixes
int compSuffixes(char *suffix1, char *suffix2, int byte_length){
int ret = 0;
for(int i=0;i<byte_length;i++){
if(suffix1[i]>suffix2[i])
return 1;
else if(suffix1[i]<suffix2[i])
return -1;
}
return ret;
}
char* fourbitEncodeRead(char *read, int length){
int byte_length = length/2;
char *fourbit_read = (char*)calloc(byte_length,sizeof(char));
for(int i=0;i<length;i++){
char this_char = read[i];
char fourbit_char;
if(this_char == '$')
fourbit_char = 0x00;
else if(this_char == 'A')
fourbit_char = 0x01;
else if(this_char == 'C')
fourbit_char = 0x02;
else if(this_char == 'G')
fourbit_char = 0x03;
else
fourbit_char = 0x04;
fourbit_char = i%2==0 ? fourbit_char << 4 : fourbit_char;
fourbit_read[i/2] = fourbit_read[i/2] | fourbit_char;
}
return fourbit_read;
}
void sort_fourbit_suffixes(char **suffixes, int suffix_count, int byte_length){
char *temp=(char*)malloc(byte_length*sizeof(char));
for(int i=0;i<suffix_count-1;i++){
for(int j=0;j<suffix_count-i-1;j++){
if(compSuffixes(suffixes[j], suffixes[j+1], byte_length)>0){
memcpy(temp, suffixes[j], byte_length*sizeof(char));
memcpy(suffixes[j], suffixes[j+1], byte_length*sizeof(char));
memcpy(suffixes[j+1], temp, byte_length*sizeof(char));
}
}
}
}
//Default Pipeline. You need to implement CUDA function corresponding to everything inside this function
void pipeline(char **reads, int read_length, int read_count){
fourbit_sorted_suffixes_original = (char**)malloc(read_length*read_count*sizeof(char*));
for(int i=0;i<read_count;i++){
char **suffixes_for_read = generateSuffixes(fourbitEncodeRead(reads[i], read_length), read_length/2);
sort_fourbit_suffixes(suffixes_for_read, read_length, read_length/2);
for(int j=0;j<read_length;j++){
fourbit_sorted_suffixes_original[i*read_length+j] = suffixes_for_read[j];
}
}
//--------------For debug purpose--------------
/*
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++)
printf("%x\t",fourbit_sorted_suffixes_original[i][j]);
printf("\n");
}*/
//---------------------------------------------
}
//Merge all sorted suffixes in overall sorted order
void mergeAllSorted4bitSuffixes(char** suffixes, int read_count, int read_length){
}
//-----------------------DO NOT CHANGE--------------------------------------------
int main(int argc, char *argv[]){
char **reads = inputReads(argv[1], &read_count, &read_length);//Input reads from file
//-----------Default implementation----------------
//-----------Time capture start--------------------
struct timeval TimeValue_Start;
struct timeval TimeValue_Final;
struct timezone TimeZone_Start;
struct timezone TimeZone_Final;
long time_start, time_end;
double time_overhead_default, time_overhead_student;
gettimeofday(&TimeValue_Start, &TimeZone_Start);
pipeline(reads, read_length, read_count);
mergeAllSorted4bitSuffixes(fourbit_sorted_suffixes_original, read_count, read_length);
gettimeofday(&TimeValue_Final, &TimeZone_Final);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_default = (time_end - time_start)/1000000.0;
cout<<time_overhead_default<<endl;
//------------Time capture end----------------------
//--------------------------------------------------
//-----------Your implementations------------------
gettimeofday(&TimeValue_Start, &TimeZone_Start);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
//-----------Call your functions here--------------------
//-----------Call your functions here--------------------
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_student = (time_end - time_start)/1000000.0;
//--------------------------------------------------
//---------------Correction check and speedup calculation----------------------
float speedup=0.0;
//if(checker()==1)
// speedup = time_overhead_default/time_overhead_student;
cout<<"Speedup="<<speedup<<endl;
//-----------------------------------------------------------------------------
return 0;
} | .file "tmpxft_00006cde_00000000-6_FMIndex.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4051:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4051:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.text
.globl _Z10inputReadsPcPiS0_
.type _Z10inputReadsPcPiS0_, @function
_Z10inputReadsPcPiS0_:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbx
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %r12d
jmp .L7
.L23:
addl $1, %r12d
.L7:
movq %rbp, %rdi
call fgetc@PLT
cmpl $10, %eax
je .L23
cmpl $-1, %eax
jne .L7
movq %rbp, %rdi
call rewind@PLT
movslq %r12d, %rax
leaq 0(,%rax,8), %r14
movq %r14, 8(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
movl %r12d, (%rbx)
movq $0, 16(%rsp)
testl %r12d, %r12d
jle .L8
movq %rax, %rbx
addq %rax, %r14
leaq 16(%rsp), %r13
.L9:
movq $0, (%rbx)
movq $0, 16(%rsp)
movq %rbp, %rcx
movl $10, %edx
movq %r13, %rsi
movq %rbx, %rdi
call __getdelim@PLT
addq $8, %rbx
cmpq %r14, %rbx
jne .L9
movq %rbp, %rdi
call fclose@PLT
movq (%r15), %rcx
cmpb $10, (%rcx)
je .L10
.L14:
movl $1, %eax
.L11:
movq %rax, %rdx
addq $1, %rax
cmpb $10, -1(%rcx,%rax)
jne .L11
leal 1(%rdx), %eax
movq (%rsp), %rsi
movl %eax, (%rsi)
testl %r12d, %r12d
jle .L3
.L16:
movq %r15, %rax
movq 8(%rsp), %rsi
addq %r15, %rsi
.L13:
movq (%rax), %rcx
movb $36, (%rcx,%rdx)
addq $8, %rax
cmpq %rsi, %rax
jne .L13
.L3:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L24
movq %r15, %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movq %rbp, %rdi
call fclose@PLT
movq (%r15), %rcx
cmpb $10, (%rcx)
jne .L14
movq (%rsp), %rax
movl $1, (%rax)
jmp .L3
.L10:
movq (%rsp), %rax
movl $1, (%rax)
movl $0, %edx
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.size _Z10inputReadsPcPiS0_, .-_Z10inputReadsPcPiS0_
.globl _Z7checkerv
.type _Z7checkerv, @function
_Z7checkerv:
.LFB4040:
.cfi_startproc
endbr64
movl read_length(%rip), %r11d
movl %r11d, %eax
imull read_count(%rip), %eax
testl %eax, %eax
jle .L32
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %r11d, %edi
shrl $31, %edi
addl %r11d, %edi
sarl %edi
movq fourbit_sorted_suffixes_student(%rip), %rbp
movq fourbit_sorted_suffixes_original(%rip), %rbx
cltq
leaq 0(,%rax,8), %r10
movl $0, %r9d
movl $1, %edx
movl $0, %r8d
jmp .L27
.L30:
movq 0(%rbp,%r9), %rsi
movq (%rbx,%r9), %rcx
movl $0, %eax
.L29:
movzbl (%rcx,%rax), %r14d
cmpb %r14b, (%rsi,%rax)
cmovne %r8d, %edx
addq $1, %rax
cmpl %eax, %edi
jg .L29
.L31:
addq $8, %r9
cmpq %r10, %r9
je .L25
.L27:
cmpl $1, %r11d
jg .L30
jmp .L31
.L32:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 14
movl $1, %edx
movl %edx, %eax
ret
.L25:
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
.cfi_offset 6, -24
.cfi_offset 14, -16
movl %edx, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4040:
.size _Z7checkerv, .-_Z7checkerv
.globl _Z10rotateReadPci
.type _Z10rotateReadPci, @function
_Z10rotateReadPci:
.LFB4041:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
movzbl (%rdi), %eax
movl %eax, %esi
sall $4, %esi
shrb $4, %al
movb %al, (%rdi)
cmpl $1, %ebp
jle .L40
leaq 1(%rdi), %rax
leal -2(%rbp), %edx
leaq 2(%rdi,%rdx), %rdi
.L41:
movzbl (%rax), %ecx
movl %ecx, %edx
shrb $4, %dl
orl %esi, %edx
movl %ecx, %esi
sall $4, %esi
movb %dl, (%rax)
addq $1, %rax
cmpq %rdi, %rax
jne .L41
orb %sil, (%rbx)
movslq %ebp, %r12
movq %r12, %rdi
call malloc@PLT
.L45:
movl $0, %edx
.L44:
movzbl (%rbx,%rdx), %ecx
movb %cl, (%rax,%rdx)
addq $1, %rdx
cmpq %rdx, %r12
jne .L44
.L39:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
orb %sil, (%rdi)
movslq %ebp, %r12
movq %r12, %rdi
call malloc@PLT
testl %ebp, %ebp
jle .L39
jmp .L45
.cfi_endproc
.LFE4041:
.size _Z10rotateReadPci, .-_Z10rotateReadPci
.globl _Z16generateSuffixesPci
.type _Z16generateSuffixesPci, @function
_Z16generateSuffixesPci:
.LFB4042:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebp
leal (%rsi,%rsi), %ebx
movslq %ebx, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L50
movq %rax, %rbx
leal -1(%rbp,%rbp), %eax
leaq 8(%r14,%rax,8), %r13
.L52:
movl %ebp, %esi
movq %r12, %rdi
call _Z10rotateReadPci
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L52
.L50:
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _Z16generateSuffixesPci, .-_Z16generateSuffixesPci
.globl _Z12compSuffixesPcS_i
.type _Z12compSuffixesPcS_i, @function
_Z12compSuffixesPcS_i:
.LFB4043:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L58
movslq %edx, %rdx
movl $0, %eax
.L57:
movzbl (%rdi,%rax), %r8d
movzbl (%rsi,%rax), %ecx
cmpb %cl, %r8b
jg .L59
jl .L60
addq $1, %rax
cmpq %rdx, %rax
jne .L57
movl $0, %eax
ret
.L58:
movl $0, %eax
ret
.L59:
movl $1, %eax
ret
.L60:
movl $-1, %eax
ret
.cfi_endproc
.LFE4043:
.size _Z12compSuffixesPcS_i, .-_Z12compSuffixesPcS_i
.globl _Z17fourbitEncodeReadPci
.type _Z17fourbitEncodeReadPci, @function
_Z17fourbitEncodeReadPci:
.LFB4044:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
movl %esi, %edi
shrl $31, %edi
addl %esi, %edi
sarl %edi
movslq %edi, %rdi
movl $1, %esi
call calloc@PLT
movq %rax, %rdi
testl %ebp, %ebp
jle .L62
movslq %ebp, %r8
movl $0, %ecx
movl $2, %r10d
movl $0, %r9d
jmp .L67
.L65:
cmpb $71, %al
setne %dl
addl $3, %edx
.L64:
movl %edx, %eax
sall $4, %eax
testb $1, %sil
cmove %eax, %edx
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
cltq
orb %dl, (%rdi,%rax)
addq $1, %rcx
cmpq %r8, %rcx
je .L62
.L67:
movl %ecx, %esi
movzbl (%rbx,%rcx), %eax
cmpb $67, %al
je .L68
jg .L65
movl %r9d, %edx
cmpb $36, %al
je .L64
cmpb $65, %al
setne %dl
leal 1(%rdx,%rdx,2), %edx
jmp .L64
.L68:
movl %r10d, %edx
jmp .L64
.L62:
movq %rdi, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4044:
.size _Z17fourbitEncodeReadPci, .-_Z17fourbitEncodeReadPci
.globl _Z21sort_fourbit_suffixesPPcii
.type _Z21sort_fourbit_suffixesPPcii, @function
_Z21sort_fourbit_suffixesPPcii:
.LFB4045:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %edx, %r15d
movslq %edx, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, (%rsp)
cmpl $1, %ebx
jle .L74
movl %ebx, 12(%rsp)
leaq 16(%r14), %rax
movq %rax, 24(%rsp)
jmp .L76
.L77:
addq $8, %rbx
cmpq %r14, %rbx
je .L84
.L78:
movq (%rbx), %r12
movq -8(%rbx), %rbp
movl %r15d, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z12compSuffixesPcS_i
testl %eax, %eax
jle .L77
movq %r13, %rcx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call __memcpy_chk@PLT
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call memcpy@PLT
movq (%rbx), %rdi
movq %r13, %rdx
movq (%rsp), %rsi
call memcpy@PLT
jmp .L77
.L84:
subl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl $1, %eax
je .L74
.L76:
cmpl $1, 12(%rsp)
jle .L85
movq 16(%rsp), %rax
leaq 8(%rax), %rbx
movl 12(%rsp), %eax
leal -2(%rax), %eax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,8), %r14
jmp .L78
.L85:
subl $1, 12(%rsp)
jmp .L76
.L74:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _Z21sort_fourbit_suffixesPPcii, .-_Z21sort_fourbit_suffixesPPcii
.globl _Z8pipelinePPcii
.type _Z8pipelinePPcii, @function
_Z8pipelinePPcii:
.LFB4046:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %ebx
movl %esi, %edi
imull %edx, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, fourbit_sorted_suffixes_original(%rip)
testl %ebx, %ebx
jle .L86
movl %ebp, %r14d
shrl $31, %r14d
addl %ebp, %r14d
sarl %r14d
movq %r13, %r12
movslq %ebx, %rbx
leaq 0(%r13,%rbx,8), %r15
movl $0, %r13d
movslq %ebp, %rax
movq %rax, 8(%rsp)
.L90:
movq (%r12), %rdi
movl %ebp, %esi
call _Z17fourbitEncodeReadPci
movq %rax, %rdi
movl %r14d, %esi
call _Z16generateSuffixesPci
movq %rax, %rbx
movl %r14d, %edx
movl %ebp, %esi
movq %rax, %rdi
call _Z21sort_fourbit_suffixesPPcii
testl %ebp, %ebp
jle .L88
movslq %r13d, %rdx
leaq 0(,%rdx,8), %rax
movq 8(%rsp), %rsi
addq %rdx, %rsi
salq $3, %rsi
negq %rdx
leaq (%rbx,%rdx,8), %rdi
.L89:
movq (%rdi,%rax), %rcx
movq fourbit_sorted_suffixes_original(%rip), %rdx
movq %rcx, (%rdx,%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L89
.L88:
addq $8, %r12
addl %ebp, %r13d
cmpq %r15, %r12
jne .L90
.L86:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4046:
.size _Z8pipelinePPcii, .-_Z8pipelinePPcii
.globl _Z26mergeAllSorted4bitSuffixesPPcii
.type _Z26mergeAllSorted4bitSuffixesPPcii, @function
_Z26mergeAllSorted4bitSuffixesPPcii:
.LFB4047:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE4047:
.size _Z26mergeAllSorted4bitSuffixesPPcii, .-_Z26mergeAllSorted4bitSuffixesPPcii
.section .rodata.str1.1
.LC2:
.string "Speedup="
.text
.globl main
.type main, @function
main:
.LFB4048:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq read_length(%rip), %rdx
leaq read_count(%rip), %rsi
call _Z10inputReadsPcPiS0_
movq %rax, %r12
movq %rsp, %rbp
leaq 16(%rsp), %rbx
movq %rbp, %rsi
movq %rbx, %rdi
call gettimeofday@PLT
movl read_count(%rip), %edx
movl read_length(%rip), %esi
movq %r12, %rdi
call _Z8pipelinePPcii
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
call gettimeofday@PLT
imulq $1000000, 32(%rsp), %rax
addq 40(%rsp), %rax
imulq $1000000, 16(%rsp), %rdx
addq 24(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call gettimeofday@PLT
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L98
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4048:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4074:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl fourbit_sorted_suffixes_original
.bss
.align 8
.type fourbit_sorted_suffixes_original, @object
.size fourbit_sorted_suffixes_original, 8
fourbit_sorted_suffixes_original:
.zero 8
.globl read_length
.align 4
.type read_length, @object
.size read_length, 4
read_length:
.zero 4
.globl read_count
.align 4
.type read_count, @object
.size read_count, 4
read_count:
.zero 4
.globl fourbit_sorted_suffixes_student
.align 8
.type fourbit_sorted_suffixes_student, @object
.size fourbit_sorted_suffixes_student, 8
fourbit_sorted_suffixes_student:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <iomanip>
#include <cstring>
#include <cmath>
#include <stdlib.h>
#include <sys/time.h>
using namespace std;
//-----------------------DO NOT CHANGE NAMES, ONLY MODIFY VALUES--------------------------------------------
//Final Value that will be compared for correctness
//You need to create the function prototypes and definitions as per your design, but you need to present final results in this array
//-----------------------------Structures for correctness check-------------------
char **fourbit_sorted_suffixes_student;
//--------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
//-----------------------DO NOT CHANGE AT ALL--------------------------------------------
int read_count = 0;
int read_length = 0;
//This array is the default result
char **fourbit_sorted_suffixes_original;
//Read file to get reads
char** inputReads(char *file_path, int *read_count, int *length){
FILE *read_file = fopen(file_path, "r");
int ch, lines=0;
char **reads;
do
{
ch = fgetc(read_file);
if (ch == '\n')
lines++;
} while (ch != EOF);
rewind(read_file);
reads=(char**)malloc(lines*sizeof(char*));
*read_count = lines;
int i = 0;
size_t len = 0;
for(i = 0; i < lines; i++)
{
reads[i] = NULL;
len = 0;
getline(&reads[i], &len, read_file);
}
fclose(read_file);
int j=0;
while(reads[0][j]!='\n')
j++;
*length = j+1;
for(i=0;i<lines;i++)
reads[i][j]='$';
return reads;
}
//Check correctness of values
int checker(){
int correct = 1;
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++){
if(fourbit_sorted_suffixes_student[i][j] != fourbit_sorted_suffixes_original[i][j])
correct = 0;
}
}
return correct;
}
//Rotate 4-bit encoded read by 1 character (4-bit)
char* rotateRead(char *read, int byte_length){
char prev_4bit = (read[0] & 0x0F) << 4;
read[0] = (read[0] >> 4) & 0x0F;
for(int i=1;i<byte_length;i++){
char this_char = ((read[i] >> 4) & 0x0F) | prev_4bit;
prev_4bit = (read[i] & 0x0F) << 4;
read[i] = this_char;
}
read[0]=read[0] | prev_4bit;
char *rotated_read = (char*)malloc(byte_length*sizeof(char));
for(int i=0;i<byte_length;i++)
rotated_read[i] = read[i];
return rotated_read;
}
//Generate Sufixes for a 4-bit encoded read
char** generateSuffixes(char *read, int byte_length){
char **suffixes=(char**)malloc(byte_length*2*sizeof(char*));
for(int i=0;i<byte_length*2;i++){
suffixes[i] = rotateRead(read, byte_length);
}
return suffixes;
}
//Comparator for 4-bit encoded Suffixes
int compSuffixes(char *suffix1, char *suffix2, int byte_length){
int ret = 0;
for(int i=0;i<byte_length;i++){
if(suffix1[i]>suffix2[i])
return 1;
else if(suffix1[i]<suffix2[i])
return -1;
}
return ret;
}
char* fourbitEncodeRead(char *read, int length){
int byte_length = length/2;
char *fourbit_read = (char*)calloc(byte_length,sizeof(char));
for(int i=0;i<length;i++){
char this_char = read[i];
char fourbit_char;
if(this_char == '$')
fourbit_char = 0x00;
else if(this_char == 'A')
fourbit_char = 0x01;
else if(this_char == 'C')
fourbit_char = 0x02;
else if(this_char == 'G')
fourbit_char = 0x03;
else
fourbit_char = 0x04;
fourbit_char = i%2==0 ? fourbit_char << 4 : fourbit_char;
fourbit_read[i/2] = fourbit_read[i/2] | fourbit_char;
}
return fourbit_read;
}
void sort_fourbit_suffixes(char **suffixes, int suffix_count, int byte_length){
char *temp=(char*)malloc(byte_length*sizeof(char));
for(int i=0;i<suffix_count-1;i++){
for(int j=0;j<suffix_count-i-1;j++){
if(compSuffixes(suffixes[j], suffixes[j+1], byte_length)>0){
memcpy(temp, suffixes[j], byte_length*sizeof(char));
memcpy(suffixes[j], suffixes[j+1], byte_length*sizeof(char));
memcpy(suffixes[j+1], temp, byte_length*sizeof(char));
}
}
}
}
//Default Pipeline. You need to implement CUDA function corresponding to everything inside this function
void pipeline(char **reads, int read_length, int read_count){
fourbit_sorted_suffixes_original = (char**)malloc(read_length*read_count*sizeof(char*));
for(int i=0;i<read_count;i++){
char **suffixes_for_read = generateSuffixes(fourbitEncodeRead(reads[i], read_length), read_length/2);
sort_fourbit_suffixes(suffixes_for_read, read_length, read_length/2);
for(int j=0;j<read_length;j++){
fourbit_sorted_suffixes_original[i*read_length+j] = suffixes_for_read[j];
}
}
//--------------For debug purpose--------------
/*
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++)
printf("%x\t",fourbit_sorted_suffixes_original[i][j]);
printf("\n");
}*/
//---------------------------------------------
}
//Merge all sorted suffixes in overall sorted order
void mergeAllSorted4bitSuffixes(char** suffixes, int read_count, int read_length){
}
//-----------------------DO NOT CHANGE--------------------------------------------
int main(int argc, char *argv[]){
char **reads = inputReads(argv[1], &read_count, &read_length);//Input reads from file
//-----------Default implementation----------------
//-----------Time capture start--------------------
struct timeval TimeValue_Start;
struct timeval TimeValue_Final;
struct timezone TimeZone_Start;
struct timezone TimeZone_Final;
long time_start, time_end;
double time_overhead_default, time_overhead_student;
gettimeofday(&TimeValue_Start, &TimeZone_Start);
pipeline(reads, read_length, read_count);
mergeAllSorted4bitSuffixes(fourbit_sorted_suffixes_original, read_count, read_length);
gettimeofday(&TimeValue_Final, &TimeZone_Final);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_default = (time_end - time_start)/1000000.0;
cout<<time_overhead_default<<endl;
//------------Time capture end----------------------
//--------------------------------------------------
//-----------Your implementations------------------
gettimeofday(&TimeValue_Start, &TimeZone_Start);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
//-----------Call your functions here--------------------
//-----------Call your functions here--------------------
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_student = (time_end - time_start)/1000000.0;
//--------------------------------------------------
//---------------Correction check and speedup calculation----------------------
float speedup=0.0;
//if(checker()==1)
// speedup = time_overhead_default/time_overhead_student;
cout<<"Speedup="<<speedup<<endl;
//-----------------------------------------------------------------------------
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <cstring>
#include <cmath>
#include <stdlib.h>
#include <sys/time.h>
using namespace std;
//-----------------------DO NOT CHANGE NAMES, ONLY MODIFY VALUES--------------------------------------------
//Final Value that will be compared for correctness
//You need to create the function prototypes and definitions as per your design, but you need to present final results in this array
//-----------------------------Structures for correctness check-------------------
char **fourbit_sorted_suffixes_student;
//--------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
//-----------------------DO NOT CHANGE AT ALL--------------------------------------------
int read_count = 0;
int read_length = 0;
//This array is the default result
char **fourbit_sorted_suffixes_original;
//Read file to get reads
char** inputReads(char *file_path, int *read_count, int *length){
FILE *read_file = fopen(file_path, "r");
int ch, lines=0;
char **reads;
do
{
ch = fgetc(read_file);
if (ch == '\n')
lines++;
} while (ch != EOF);
rewind(read_file);
reads=(char**)malloc(lines*sizeof(char*));
*read_count = lines;
int i = 0;
size_t len = 0;
for(i = 0; i < lines; i++)
{
reads[i] = NULL;
len = 0;
getline(&reads[i], &len, read_file);
}
fclose(read_file);
int j=0;
while(reads[0][j]!='\n')
j++;
*length = j+1;
for(i=0;i<lines;i++)
reads[i][j]='$';
return reads;
}
//Check correctness of values
int checker(){
int correct = 1;
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++){
if(fourbit_sorted_suffixes_student[i][j] != fourbit_sorted_suffixes_original[i][j])
correct = 0;
}
}
return correct;
}
//Rotate 4-bit encoded read by 1 character (4-bit)
char* rotateRead(char *read, int byte_length){
char prev_4bit = (read[0] & 0x0F) << 4;
read[0] = (read[0] >> 4) & 0x0F;
for(int i=1;i<byte_length;i++){
char this_char = ((read[i] >> 4) & 0x0F) | prev_4bit;
prev_4bit = (read[i] & 0x0F) << 4;
read[i] = this_char;
}
read[0]=read[0] | prev_4bit;
char *rotated_read = (char*)malloc(byte_length*sizeof(char));
for(int i=0;i<byte_length;i++)
rotated_read[i] = read[i];
return rotated_read;
}
//Generate Sufixes for a 4-bit encoded read
char** generateSuffixes(char *read, int byte_length){
char **suffixes=(char**)malloc(byte_length*2*sizeof(char*));
for(int i=0;i<byte_length*2;i++){
suffixes[i] = rotateRead(read, byte_length);
}
return suffixes;
}
//Comparator for 4-bit encoded Suffixes
int compSuffixes(char *suffix1, char *suffix2, int byte_length){
int ret = 0;
for(int i=0;i<byte_length;i++){
if(suffix1[i]>suffix2[i])
return 1;
else if(suffix1[i]<suffix2[i])
return -1;
}
return ret;
}
char* fourbitEncodeRead(char *read, int length){
int byte_length = length/2;
char *fourbit_read = (char*)calloc(byte_length,sizeof(char));
for(int i=0;i<length;i++){
char this_char = read[i];
char fourbit_char;
if(this_char == '$')
fourbit_char = 0x00;
else if(this_char == 'A')
fourbit_char = 0x01;
else if(this_char == 'C')
fourbit_char = 0x02;
else if(this_char == 'G')
fourbit_char = 0x03;
else
fourbit_char = 0x04;
fourbit_char = i%2==0 ? fourbit_char << 4 : fourbit_char;
fourbit_read[i/2] = fourbit_read[i/2] | fourbit_char;
}
return fourbit_read;
}
void sort_fourbit_suffixes(char **suffixes, int suffix_count, int byte_length){
char *temp=(char*)malloc(byte_length*sizeof(char));
for(int i=0;i<suffix_count-1;i++){
for(int j=0;j<suffix_count-i-1;j++){
if(compSuffixes(suffixes[j], suffixes[j+1], byte_length)>0){
memcpy(temp, suffixes[j], byte_length*sizeof(char));
memcpy(suffixes[j], suffixes[j+1], byte_length*sizeof(char));
memcpy(suffixes[j+1], temp, byte_length*sizeof(char));
}
}
}
}
//Default Pipeline. You need to implement CUDA function corresponding to everything inside this function
void pipeline(char **reads, int read_length, int read_count){
fourbit_sorted_suffixes_original = (char**)malloc(read_length*read_count*sizeof(char*));
for(int i=0;i<read_count;i++){
char **suffixes_for_read = generateSuffixes(fourbitEncodeRead(reads[i], read_length), read_length/2);
sort_fourbit_suffixes(suffixes_for_read, read_length, read_length/2);
for(int j=0;j<read_length;j++){
fourbit_sorted_suffixes_original[i*read_length+j] = suffixes_for_read[j];
}
}
//--------------For debug purpose--------------
/*
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++)
printf("%x\t",fourbit_sorted_suffixes_original[i][j]);
printf("\n");
}*/
//---------------------------------------------
}
//Merge all sorted suffixes in overall sorted order
void mergeAllSorted4bitSuffixes(char** suffixes, int read_count, int read_length){
}
//-----------------------DO NOT CHANGE--------------------------------------------
int main(int argc, char *argv[]){
char **reads = inputReads(argv[1], &read_count, &read_length);//Input reads from file
//-----------Default implementation----------------
//-----------Time capture start--------------------
struct timeval TimeValue_Start;
struct timeval TimeValue_Final;
struct timezone TimeZone_Start;
struct timezone TimeZone_Final;
long time_start, time_end;
double time_overhead_default, time_overhead_student;
gettimeofday(&TimeValue_Start, &TimeZone_Start);
pipeline(reads, read_length, read_count);
mergeAllSorted4bitSuffixes(fourbit_sorted_suffixes_original, read_count, read_length);
gettimeofday(&TimeValue_Final, &TimeZone_Final);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_default = (time_end - time_start)/1000000.0;
cout<<time_overhead_default<<endl;
//------------Time capture end----------------------
//--------------------------------------------------
//-----------Your implementations------------------
gettimeofday(&TimeValue_Start, &TimeZone_Start);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
//-----------Call your functions here--------------------
//-----------Call your functions here--------------------
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_student = (time_end - time_start)/1000000.0;
//--------------------------------------------------
//---------------Correction check and speedup calculation----------------------
float speedup=0.0;
//if(checker()==1)
// speedup = time_overhead_default/time_overhead_student;
cout<<"Speedup="<<speedup<<endl;
//-----------------------------------------------------------------------------
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <cstring>
#include <cmath>
#include <stdlib.h>
#include <sys/time.h>
using namespace std;
//-----------------------DO NOT CHANGE NAMES, ONLY MODIFY VALUES--------------------------------------------
//Final Value that will be compared for correctness
//You need to create the function prototypes and definitions as per your design, but you need to present final results in this array
//-----------------------------Structures for correctness check-------------------
char **fourbit_sorted_suffixes_student;
//--------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
//-----------------------DO NOT CHANGE AT ALL--------------------------------------------
int read_count = 0;
int read_length = 0;
//This array is the default result
char **fourbit_sorted_suffixes_original;
//Read file to get reads
char** inputReads(char *file_path, int *read_count, int *length){
FILE *read_file = fopen(file_path, "r");
int ch, lines=0;
char **reads;
do
{
ch = fgetc(read_file);
if (ch == '\n')
lines++;
} while (ch != EOF);
rewind(read_file);
reads=(char**)malloc(lines*sizeof(char*));
*read_count = lines;
int i = 0;
size_t len = 0;
for(i = 0; i < lines; i++)
{
reads[i] = NULL;
len = 0;
getline(&reads[i], &len, read_file);
}
fclose(read_file);
int j=0;
while(reads[0][j]!='\n')
j++;
*length = j+1;
for(i=0;i<lines;i++)
reads[i][j]='$';
return reads;
}
//Check correctness of values
int checker(){
int correct = 1;
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++){
if(fourbit_sorted_suffixes_student[i][j] != fourbit_sorted_suffixes_original[i][j])
correct = 0;
}
}
return correct;
}
//Rotate 4-bit encoded read by 1 character (4-bit)
char* rotateRead(char *read, int byte_length){
char prev_4bit = (read[0] & 0x0F) << 4;
read[0] = (read[0] >> 4) & 0x0F;
for(int i=1;i<byte_length;i++){
char this_char = ((read[i] >> 4) & 0x0F) | prev_4bit;
prev_4bit = (read[i] & 0x0F) << 4;
read[i] = this_char;
}
read[0]=read[0] | prev_4bit;
char *rotated_read = (char*)malloc(byte_length*sizeof(char));
for(int i=0;i<byte_length;i++)
rotated_read[i] = read[i];
return rotated_read;
}
//Generate Sufixes for a 4-bit encoded read
char** generateSuffixes(char *read, int byte_length){
char **suffixes=(char**)malloc(byte_length*2*sizeof(char*));
for(int i=0;i<byte_length*2;i++){
suffixes[i] = rotateRead(read, byte_length);
}
return suffixes;
}
//Comparator for 4-bit encoded Suffixes
int compSuffixes(char *suffix1, char *suffix2, int byte_length){
int ret = 0;
for(int i=0;i<byte_length;i++){
if(suffix1[i]>suffix2[i])
return 1;
else if(suffix1[i]<suffix2[i])
return -1;
}
return ret;
}
char* fourbitEncodeRead(char *read, int length){
int byte_length = length/2;
char *fourbit_read = (char*)calloc(byte_length,sizeof(char));
for(int i=0;i<length;i++){
char this_char = read[i];
char fourbit_char;
if(this_char == '$')
fourbit_char = 0x00;
else if(this_char == 'A')
fourbit_char = 0x01;
else if(this_char == 'C')
fourbit_char = 0x02;
else if(this_char == 'G')
fourbit_char = 0x03;
else
fourbit_char = 0x04;
fourbit_char = i%2==0 ? fourbit_char << 4 : fourbit_char;
fourbit_read[i/2] = fourbit_read[i/2] | fourbit_char;
}
return fourbit_read;
}
void sort_fourbit_suffixes(char **suffixes, int suffix_count, int byte_length){
char *temp=(char*)malloc(byte_length*sizeof(char));
for(int i=0;i<suffix_count-1;i++){
for(int j=0;j<suffix_count-i-1;j++){
if(compSuffixes(suffixes[j], suffixes[j+1], byte_length)>0){
memcpy(temp, suffixes[j], byte_length*sizeof(char));
memcpy(suffixes[j], suffixes[j+1], byte_length*sizeof(char));
memcpy(suffixes[j+1], temp, byte_length*sizeof(char));
}
}
}
}
//Default Pipeline. You need to implement CUDA function corresponding to everything inside this function
void pipeline(char **reads, int read_length, int read_count){
fourbit_sorted_suffixes_original = (char**)malloc(read_length*read_count*sizeof(char*));
for(int i=0;i<read_count;i++){
char **suffixes_for_read = generateSuffixes(fourbitEncodeRead(reads[i], read_length), read_length/2);
sort_fourbit_suffixes(suffixes_for_read, read_length, read_length/2);
for(int j=0;j<read_length;j++){
fourbit_sorted_suffixes_original[i*read_length+j] = suffixes_for_read[j];
}
}
//--------------For debug purpose--------------
/*
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++)
printf("%x\t",fourbit_sorted_suffixes_original[i][j]);
printf("\n");
}*/
//---------------------------------------------
}
//Merge all sorted suffixes in overall sorted order
void mergeAllSorted4bitSuffixes(char** suffixes, int read_count, int read_length){
}
//-----------------------DO NOT CHANGE--------------------------------------------
int main(int argc, char *argv[]){
char **reads = inputReads(argv[1], &read_count, &read_length);//Input reads from file
//-----------Default implementation----------------
//-----------Time capture start--------------------
struct timeval TimeValue_Start;
struct timeval TimeValue_Final;
struct timezone TimeZone_Start;
struct timezone TimeZone_Final;
long time_start, time_end;
double time_overhead_default, time_overhead_student;
gettimeofday(&TimeValue_Start, &TimeZone_Start);
pipeline(reads, read_length, read_count);
mergeAllSorted4bitSuffixes(fourbit_sorted_suffixes_original, read_count, read_length);
gettimeofday(&TimeValue_Final, &TimeZone_Final);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_default = (time_end - time_start)/1000000.0;
cout<<time_overhead_default<<endl;
//------------Time capture end----------------------
//--------------------------------------------------
//-----------Your implementations------------------
gettimeofday(&TimeValue_Start, &TimeZone_Start);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
//-----------Call your functions here--------------------
//-----------Call your functions here--------------------
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_student = (time_end - time_start)/1000000.0;
//--------------------------------------------------
//---------------Correction check and speedup calculation----------------------
float speedup=0.0;
//if(checker()==1)
// speedup = time_overhead_default/time_overhead_student;
cout<<"Speedup="<<speedup<<endl;
//-----------------------------------------------------------------------------
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <iomanip>
#include <cstring>
#include <cmath>
#include <stdlib.h>
#include <sys/time.h>
using namespace std;
//-----------------------DO NOT CHANGE NAMES, ONLY MODIFY VALUES--------------------------------------------
//Final Value that will be compared for correctness
//You need to create the function prototypes and definitions as per your design, but you need to present final results in this array
//-----------------------------Structures for correctness check-------------------
char **fourbit_sorted_suffixes_student;
//--------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------------
//-----------------------DO NOT CHANGE AT ALL--------------------------------------------
int read_count = 0;
int read_length = 0;
//This array is the default result
char **fourbit_sorted_suffixes_original;
//Read file to get reads
char** inputReads(char *file_path, int *read_count, int *length){
FILE *read_file = fopen(file_path, "r");
int ch, lines=0;
char **reads;
do
{
ch = fgetc(read_file);
if (ch == '\n')
lines++;
} while (ch != EOF);
rewind(read_file);
reads=(char**)malloc(lines*sizeof(char*));
*read_count = lines;
int i = 0;
size_t len = 0;
for(i = 0; i < lines; i++)
{
reads[i] = NULL;
len = 0;
getline(&reads[i], &len, read_file);
}
fclose(read_file);
int j=0;
while(reads[0][j]!='\n')
j++;
*length = j+1;
for(i=0;i<lines;i++)
reads[i][j]='$';
return reads;
}
//Check correctness of values
int checker(){
int correct = 1;
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++){
if(fourbit_sorted_suffixes_student[i][j] != fourbit_sorted_suffixes_original[i][j])
correct = 0;
}
}
return correct;
}
//Rotate 4-bit encoded read by 1 character (4-bit)
char* rotateRead(char *read, int byte_length){
char prev_4bit = (read[0] & 0x0F) << 4;
read[0] = (read[0] >> 4) & 0x0F;
for(int i=1;i<byte_length;i++){
char this_char = ((read[i] >> 4) & 0x0F) | prev_4bit;
prev_4bit = (read[i] & 0x0F) << 4;
read[i] = this_char;
}
read[0]=read[0] | prev_4bit;
char *rotated_read = (char*)malloc(byte_length*sizeof(char));
for(int i=0;i<byte_length;i++)
rotated_read[i] = read[i];
return rotated_read;
}
//Generate Sufixes for a 4-bit encoded read
char** generateSuffixes(char *read, int byte_length){
char **suffixes=(char**)malloc(byte_length*2*sizeof(char*));
for(int i=0;i<byte_length*2;i++){
suffixes[i] = rotateRead(read, byte_length);
}
return suffixes;
}
//Comparator for 4-bit encoded Suffixes
int compSuffixes(char *suffix1, char *suffix2, int byte_length){
int ret = 0;
for(int i=0;i<byte_length;i++){
if(suffix1[i]>suffix2[i])
return 1;
else if(suffix1[i]<suffix2[i])
return -1;
}
return ret;
}
char* fourbitEncodeRead(char *read, int length){
int byte_length = length/2;
char *fourbit_read = (char*)calloc(byte_length,sizeof(char));
for(int i=0;i<length;i++){
char this_char = read[i];
char fourbit_char;
if(this_char == '$')
fourbit_char = 0x00;
else if(this_char == 'A')
fourbit_char = 0x01;
else if(this_char == 'C')
fourbit_char = 0x02;
else if(this_char == 'G')
fourbit_char = 0x03;
else
fourbit_char = 0x04;
fourbit_char = i%2==0 ? fourbit_char << 4 : fourbit_char;
fourbit_read[i/2] = fourbit_read[i/2] | fourbit_char;
}
return fourbit_read;
}
void sort_fourbit_suffixes(char **suffixes, int suffix_count, int byte_length){
char *temp=(char*)malloc(byte_length*sizeof(char));
for(int i=0;i<suffix_count-1;i++){
for(int j=0;j<suffix_count-i-1;j++){
if(compSuffixes(suffixes[j], suffixes[j+1], byte_length)>0){
memcpy(temp, suffixes[j], byte_length*sizeof(char));
memcpy(suffixes[j], suffixes[j+1], byte_length*sizeof(char));
memcpy(suffixes[j+1], temp, byte_length*sizeof(char));
}
}
}
}
//Default Pipeline. You need to implement CUDA function corresponding to everything inside this function
void pipeline(char **reads, int read_length, int read_count){
fourbit_sorted_suffixes_original = (char**)malloc(read_length*read_count*sizeof(char*));
for(int i=0;i<read_count;i++){
char **suffixes_for_read = generateSuffixes(fourbitEncodeRead(reads[i], read_length), read_length/2);
sort_fourbit_suffixes(suffixes_for_read, read_length, read_length/2);
for(int j=0;j<read_length;j++){
fourbit_sorted_suffixes_original[i*read_length+j] = suffixes_for_read[j];
}
}
//--------------For debug purpose--------------
/*
for(int i=0;i<read_count*read_length;i++){
for(int j=0;j<read_length/2;j++)
printf("%x\t",fourbit_sorted_suffixes_original[i][j]);
printf("\n");
}*/
//---------------------------------------------
}
//Merge all sorted suffixes in overall sorted order
void mergeAllSorted4bitSuffixes(char** suffixes, int read_count, int read_length){
}
//-----------------------DO NOT CHANGE--------------------------------------------
int main(int argc, char *argv[]){
char **reads = inputReads(argv[1], &read_count, &read_length);//Input reads from file
//-----------Default implementation----------------
//-----------Time capture start--------------------
struct timeval TimeValue_Start;
struct timeval TimeValue_Final;
struct timezone TimeZone_Start;
struct timezone TimeZone_Final;
long time_start, time_end;
double time_overhead_default, time_overhead_student;
gettimeofday(&TimeValue_Start, &TimeZone_Start);
pipeline(reads, read_length, read_count);
mergeAllSorted4bitSuffixes(fourbit_sorted_suffixes_original, read_count, read_length);
gettimeofday(&TimeValue_Final, &TimeZone_Final);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_default = (time_end - time_start)/1000000.0;
cout<<time_overhead_default<<endl;
//------------Time capture end----------------------
//--------------------------------------------------
//-----------Your implementations------------------
gettimeofday(&TimeValue_Start, &TimeZone_Start);
time_start = TimeValue_Start.tv_sec * 1000000 + TimeValue_Start.tv_usec;
//-----------Call your functions here--------------------
//-----------Call your functions here--------------------
time_end = TimeValue_Final.tv_sec * 1000000 + TimeValue_Final.tv_usec;
time_overhead_student = (time_end - time_start)/1000000.0;
//--------------------------------------------------
//---------------Correction check and speedup calculation----------------------
float speedup=0.0;
//if(checker()==1)
// speedup = time_overhead_default/time_overhead_student;
cout<<"Speedup="<<speedup<<endl;
//-----------------------------------------------------------------------------
return 0;
} | .text
.file "FMIndex.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10inputReadsPcPiS0_ # -- Begin function _Z10inputReadsPcPiS0_
.p2align 4, 0x90
.type _Z10inputReadsPcPiS0_,@function
_Z10inputReadsPcPiS0_: # @_Z10inputReadsPcPiS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, %rbx
movl $.L.str, %esi
callq fopen
movq %rax, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq fgetc
xorl %ecx, %ecx
cmpl $10, %eax
sete %cl
addl %ecx, %ebp
cmpl $-1, %eax
jne .LBB0_1
# %bb.2:
movq %r15, %rdi
callq rewind
movl %ebp, %r12d
leaq (,%r12,8), %rdi
callq malloc
movq %rax, %r14
movl %ebp, (%rbx)
movq $0, 8(%rsp)
testl %ebp, %ebp
je .LBB0_5
# %bb.3: # %.lr.ph.preheader
movq %r12, %rbx
movq %r14, %r13
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq $0, (%r13)
movq $0, 8(%rsp)
movq %r13, %rdi
leaq 8(%rsp), %rsi
movl $10, %edx
movq %r15, %rcx
callq __getdelim
addq $8, %r13
decq %rbx
jne .LBB0_4
.LBB0_5: # %._crit_edge
movq %r15, %rdi
callq fclose
movq (%r14), %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
cmpb $10, (%rcx,%rax)
leaq 1(%rax), %rax
jne .LBB0_6
# %bb.7:
movq 16(%rsp), %rcx # 8-byte Reload
movl %eax, (%rcx)
testl %ebp, %ebp
je .LBB0_10
# %bb.8: # %.lr.ph36.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_9: # %.lr.ph36
# =>This Inner Loop Header: Depth=1
movq (%r14,%rcx,8), %rdx
movb $36, -1(%rdx,%rax)
incq %rcx
cmpq %rcx, %r12
jne .LBB0_9
.LBB0_10: # %._crit_edge37
movq %r14, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10inputReadsPcPiS0_, .Lfunc_end0-_Z10inputReadsPcPiS0_
.cfi_endproc
# -- End function
.globl _Z7checkerv # -- Begin function _Z7checkerv
.p2align 4, 0x90
.type _Z7checkerv,@function
_Z7checkerv: # @_Z7checkerv
.cfi_startproc
# %bb.0:
movl read_length(%rip), %ecx
movl read_count(%rip), %eax
imull %ecx, %eax
testl %eax, %eax
jle .LBB1_1
# %bb.3: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
movq fourbit_sorted_suffixes_student(%rip), %rsi
movq fourbit_sorted_suffixes_original(%rip), %rdi
movl %eax, %r8d
movl $1, %eax
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB1_8
.LBB1_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
cmpl $2, %ecx
jl .LBB1_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movq (%rsi,%r10,8), %r11
movq (%rdi,%r10,8), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r11,%r14), %ebp
cmpb (%rbx,%r14), %bpl
cmovnel %r9d, %eax
incq %r14
cmpq %r14, %rdx
jne .LBB1_6
jmp .LBB1_7
.LBB1_8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
retq
.LBB1_1:
movl $1, %eax
retq
.Lfunc_end1:
.size _Z7checkerv, .Lfunc_end1-_Z7checkerv
.cfi_endproc
# -- End function
.globl _Z10rotateReadPci # -- Begin function _Z10rotateReadPci
.p2align 4, 0x90
.type _Z10rotateReadPci,@function
_Z10rotateReadPci: # @_Z10rotateReadPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movzbl (%rdi), %ecx
movl %ecx, %eax
shrb $4, %al
movb %al, (%rdi)
shlb $4, %cl
movl %esi, %r14d
cmpl $2, %esi
jl .LBB2_1
# %bb.5: # %.lr.ph.preheader
movl $1, %edx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rdx), %esi
movl %esi, %edi
shrb $4, %dil
orb %cl, %dil
movb %dil, (%rbx,%rdx)
incq %rdx
shlb $4, %sil
movl %esi, %ecx
cmpq %rdx, %r14
jne .LBB2_6
jmp .LBB2_2
.LBB2_1:
movl %ecx, %esi
.LBB2_2: # %._crit_edge
orb %al, %sil
movb %sil, (%rbx)
movslq %ebp, %rdi
callq malloc
testl %ebp, %ebp
jle .LBB2_4
# %bb.3: # %.lr.ph33.preheader
movq %rax, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movq %rax, %rbx
callq memcpy@PLT
movq %rbx, %rax
.LBB2_4: # %._crit_edge34
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10rotateReadPci, .Lfunc_end2-_Z10rotateReadPci
.cfi_endproc
# -- End function
.globl _Z16generateSuffixesPci # -- Begin function _Z16generateSuffixesPci
.p2align 4, 0x90
.type _Z16generateSuffixesPci,@function
_Z16generateSuffixesPci: # @_Z16generateSuffixesPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r15d
movq %rdi, %r14
leal (%r15,%r15), %ebx
movslq %ebx, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r15, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB3_5
# %bb.1: # %.lr.ph
movl 8(%rsp), %r12d # 4-byte Reload
movzbl (%r14), %eax
cmpl $2, %ebx
movl $1, %ebp
cmovgel %ebx, %ebp
xorl %ebx, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_2 Depth=1
movl %eax, %r15d
.LBB3_4: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
orb %cl, %r15b
movb %r15b, (%r14)
movq %r12, %rdi
callq malloc
movq %rax, %r13
movq %rax, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memcpy@PLT
movq 16(%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbx,8)
incq %rbx
movl %r15d, %eax
cmpq %rbp, %rbx
je .LBB3_5
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
movl %eax, %ecx
shrb $4, %cl
shlb $4, %al
movb %cl, (%r14)
cmpl $1, 8(%rsp) # 4-byte Folded Reload
je .LBB3_3
# %bb.6: # %.lr.ph.i.preheader
# in Loop: Header=BB3_2 Depth=1
movl $1, %edx
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r14,%rdx), %r15d
movl %r15d, %esi
shrb $4, %sil
orb %al, %sil
movb %sil, (%r14,%rdx)
incq %rdx
shlb $4, %r15b
movl %r15d, %eax
cmpq %rdx, %r12
jne .LBB3_7
jmp .LBB3_4
.LBB3_5: # %._crit_edge
movq 16(%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16generateSuffixesPci, .Lfunc_end3-_Z16generateSuffixesPci
.cfi_endproc
# -- End function
.globl _Z12compSuffixesPcS_i # -- Begin function _Z12compSuffixesPcS_i
.p2align 4, 0x90
.type _Z12compSuffixesPcS_i,@function
_Z12compSuffixesPcS_i: # @_Z12compSuffixesPcS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rsi,%rcx), %edx
cmpb %dl, (%rdi,%rcx)
jg .LBB4_7
# %bb.3: # in Loop: Header=BB4_2 Depth=1
jl .LBB4_8
# %bb.4: # in Loop: Header=BB4_2 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_6:
xorl %eax, %eax
retq
.LBB4_7:
movl $1, %eax
retq
.LBB4_8:
movl $-1, %eax
retq
.Lfunc_end4:
.size _Z12compSuffixesPcS_i, .Lfunc_end4-_Z12compSuffixesPcS_i
.cfi_endproc
# -- End function
.globl _Z17fourbitEncodeReadPci # -- Begin function _Z17fourbitEncodeReadPci
.p2align 4, 0x90
.type _Z17fourbitEncodeReadPci,@function
_Z17fourbitEncodeReadPci: # @_Z17fourbitEncodeReadPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
movslq %eax, %rdi
movl $1, %esi
callq calloc
testl %ebp, %ebp
jle .LBB5_9
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
xorl %edx, %edx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_2 Depth=1
movl $2, %esi
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
movl %esi, %edi
shll $4, %edi
movl %edx, %r8d
shrl %r8d
testb $1, %dl
cmovnel %esi, %edi
orb %dil, (%rax,%r8)
incq %rdx
cmpq %rdx, %rcx
je .LBB5_9
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rdx), %edi
addl $-36, %edi
cmpl $35, %edi
ja .LBB5_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
xorl %esi, %esi
jmpq *.LJTI5_0(,%rdi,8)
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movl $1, %esi
jmp .LBB5_8
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
movl $3, %esi
jmp .LBB5_8
.LBB5_7: # in Loop: Header=BB5_2 Depth=1
movl $4, %esi
jmp .LBB5_8
.LBB5_9: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z17fourbitEncodeReadPci, .Lfunc_end5-_Z17fourbitEncodeReadPci
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI5_0:
.quad .LBB5_8
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_4
.quad .LBB5_7
.quad .LBB5_5
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_6
# -- End function
.text
.globl _Z21sort_fourbit_suffixesPPcii # -- Begin function _Z21sort_fourbit_suffixesPPcii
.p2align 4, 0x90
.type _Z21sort_fourbit_suffixesPPcii,@function
_Z21sort_fourbit_suffixesPPcii: # @_Z21sort_fourbit_suffixesPPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r14d
movq %rdi, 32(%rsp) # 8-byte Spill
movslq %edx, %rdi
movq %rdi, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movq %r14, 24(%rsp) # 8-byte Spill
cmpl $2, %r14d
jl .LBB6_10
# %bb.1: # %.preheader.lr.ph
movl %ebx, %esi
movq 24(%rsp), %rax # 8-byte Reload
decl %eax
movl %ebx, %r13d
decq %r13
xorl %ecx, %ecx
movl %eax, 16(%rsp) # 4-byte Spill
movl %eax, 12(%rsp) # 4-byte Spill
movl %ebx, 20(%rsp) # 4-byte Spill
movq 48(%rsp), %r12 # 8-byte Reload
movq 56(%rsp), %r15 # 8-byte Reload
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_9: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
movq 40(%rsp), %rcx # 8-byte Reload
incl %ecx
decl 12(%rsp) # 4-byte Folded Spill
cmpl 16(%rsp), %ecx # 4-byte Folded Reload
je .LBB6_10
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
# Child Loop BB6_6 Depth 3
movq %rcx, 40(%rsp) # 8-byte Spill
movl %ecx, %eax
subl 24(%rsp), %eax # 4-byte Folded Reload
cmpl $-2, %eax
jg .LBB6_9
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB6_2 Depth=1
movl 12(%rsp), %edi # 4-byte Reload
xorl %ebx, %ebx
movq %rdi, 64(%rsp) # 8-byte Spill
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_11: # %_Z12compSuffixesPcS_i.exit
# in Loop: Header=BB6_4 Depth=2
movq %r12, %rdi
movq %rbp, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq %rbp, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq 32(%rsp), %rax # 8-byte Reload
movq (%rax,%rbx,8), %rdi
movq %r12, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq 64(%rsp), %rdi # 8-byte Reload
movl 20(%rsp), %esi # 4-byte Reload
.LBB6_12: # %.critedge
# in Loop: Header=BB6_4 Depth=2
cmpq %rdi, %rbx
je .LBB6_9
.LBB6_4: # %.lr.ph
# Parent Loop BB6_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_6 Depth 3
movq %rbx, %rax
incq %rbx
testl %esi, %esi
jle .LBB6_12
# %bb.5: # %.lr.ph.i.preheader
# in Loop: Header=BB6_4 Depth=2
movq 32(%rsp), %rcx # 8-byte Reload
movq (%rcx,%rax,8), %rbp
movq 8(%rcx,%rax,8), %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_6: # %.lr.ph.i
# Parent Loop BB6_2 Depth=1
# Parent Loop BB6_4 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%rbp,%rax), %ecx
movzbl (%r14,%rax), %edx
cmpb %dl, %cl
jg .LBB6_11
# %bb.7: # in Loop: Header=BB6_6 Depth=3
jl .LBB6_12
# %bb.8: # in Loop: Header=BB6_6 Depth=3
leaq 1(%rax), %rcx
cmpq %rax, %r13
movq %rcx, %rax
jne .LBB6_6
jmp .LBB6_12
.LBB6_10: # %._crit_edge28
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z21sort_fourbit_suffixesPPcii, .Lfunc_end6-_Z21sort_fourbit_suffixesPPcii
.cfi_endproc
# -- End function
.globl _Z8pipelinePPcii # -- Begin function _Z8pipelinePPcii
.p2align 4, 0x90
.type _Z8pipelinePPcii,@function
_Z8pipelinePPcii: # @_Z8pipelinePPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %ebx
movq %rdi, 72(%rsp) # 8-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, fourbit_sorted_suffixes_original(%rip)
testl %ebp, %ebp
jle .LBB7_25
# %bb.1: # %.lr.ph34
movq %rbx, %rsi
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
movl %eax, %ecx
sarl %ecx
andl $-2, %eax
cltq
movl %esi, %edx
andl $2147483646, %edx # imm = 0x7FFFFFFE
movl %edx, 16(%rsp) # 4-byte Spill
cmpl $2, %eax
movl $1, %edx
cmovgel %eax, %edx
movq %rdx, 96(%rsp) # 8-byte Spill
leaq (,%rax,8), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movslq %ecx, %rax
movq %rax, 32(%rsp) # 8-byte Spill
leal -1(%rbx), %edx
movl %edx, (%rsp) # 4-byte Spill
movl %ebp, %edx
movq %rdx, 56(%rsp) # 8-byte Spill
movl %esi, %r8d
movq %rcx, 24(%rsp) # 8-byte Spill
leaq -1(%rcx), %rbx
xorl %r9d, %r9d
xorl %ecx, %ecx
movq %rsi, 40(%rsp) # 8-byte Spill
movq %r8, 48(%rsp) # 8-byte Spill
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_24: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movq 80(%rsp), %rcx # 8-byte Reload
incq %rcx
addl %esi, %r9d
cmpq 56(%rsp), %rcx # 8-byte Folded Reload
je .LBB7_25
.LBB7_2: # =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
# Child Loop BB7_17 Depth 3
# Child Loop BB7_9 Depth 2
# Child Loop BB7_11 Depth 3
# Child Loop BB7_13 Depth 4
# Child Loop BB7_23 Depth 2
movq %r9, 88(%rsp) # 8-byte Spill
movq 72(%rsp), %rax # 8-byte Reload
movq %rcx, 80(%rsp) # 8-byte Spill
movq (%rax,%rcx,8), %rdi
movq %rsi, %r15
callq _Z17fourbitEncodeReadPci
movq %rax, %r14
movq 64(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
cmpl $2, %r15d
jl .LBB7_7
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB7_2 Depth=1
movzbl (%r14), %ecx
xorl %r15d, %r15d
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_4 Depth=2
movl %ecx, %r13d
movq 24(%rsp), %rbp # 8-byte Reload
.LBB7_6: # %._crit_edge.i.i
# in Loop: Header=BB7_4 Depth=2
orb %al, %r13b
movb %r13b, (%r14)
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %rax, %rdi
movq %r14, %rsi
movq %rbp, %rdx
callq memcpy@PLT
movq 8(%rsp), %rax # 8-byte Reload
movq %r12, (%rax,%r15,8)
incq %r15
movl %r13d, %ecx
cmpq 96(%rsp), %r15 # 8-byte Folded Reload
je .LBB7_7
.LBB7_4: # Parent Loop BB7_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_17 Depth 3
movl %ecx, %eax
shrb $4, %al
shlb $4, %cl
movb %al, (%r14)
cmpl $2, 16(%rsp) # 4-byte Folded Reload
je .LBB7_5
# %bb.16: # %.lr.ph.i.i.preheader
# in Loop: Header=BB7_4 Depth=2
movl $1, %edx
movq 24(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB7_17: # %.lr.ph.i.i
# Parent Loop BB7_2 Depth=1
# Parent Loop BB7_4 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%r14,%rdx), %r13d
movl %r13d, %esi
shrb $4, %sil
orb %cl, %sil
movb %sil, (%r14,%rdx)
incq %rdx
shlb $4, %r13b
movl %r13d, %ecx
cmpq %rdx, %rbp
jne .LBB7_17
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_7: # %_Z16generateSuffixesPci.exit
# in Loop: Header=BB7_2 Depth=1
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq 8(%rsp), %r10 # 8-byte Reload
movq %rax, 104(%rsp) # 8-byte Spill
movq 40(%rsp), %rsi # 8-byte Reload
cmpl $2, %esi
jl .LBB7_21
# %bb.8: # %.preheader.i.preheader
# in Loop: Header=BB7_2 Depth=1
xorl %eax, %eax
movl (%rsp), %ecx # 4-byte Reload
movl %ecx, 4(%rsp) # 4-byte Spill
jmp .LBB7_9
.p2align 4, 0x90
.LBB7_20: # %._crit_edge.i
# in Loop: Header=BB7_9 Depth=2
movl 20(%rsp), %eax # 4-byte Reload
incl %eax
decl 4(%rsp) # 4-byte Folded Spill
cmpl (%rsp), %eax # 4-byte Folded Reload
je .LBB7_21
.LBB7_9: # %.preheader.i
# Parent Loop BB7_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_11 Depth 3
# Child Loop BB7_13 Depth 4
movl %eax, 20(%rsp) # 4-byte Spill
subl %esi, %eax
cmpl $-2, %eax
jg .LBB7_20
# %bb.10: # %.lr.ph.preheader.i
# in Loop: Header=BB7_9 Depth=2
movl 4(%rsp), %edi # 4-byte Reload
xorl %r15d, %r15d
movq %rdi, 112(%rsp) # 8-byte Spill
jmp .LBB7_11
.p2align 4, 0x90
.LBB7_18: # %_Z12compSuffixesPcS_i.exit.i
# in Loop: Header=BB7_11 Depth=3
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %r13, %rsi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
callq memcpy@PLT
movq %r13, %rdi
movq %r12, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %r12, %rdi
movq %rbp, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq 112(%rsp), %rdi # 8-byte Reload
movq 8(%rsp), %r10 # 8-byte Reload
movq 40(%rsp), %rsi # 8-byte Reload
.LBB7_19: # %.critedge.i
# in Loop: Header=BB7_11 Depth=3
incq %r15
cmpq %rdi, %r15
je .LBB7_20
.LBB7_11: # %.lr.ph.i23
# Parent Loop BB7_2 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB7_13 Depth 4
cmpl $2, %esi
jl .LBB7_19
# %bb.12: # %.lr.ph.i.i27.preheader
# in Loop: Header=BB7_11 Depth=3
movq (%r10,%r15,8), %r13
movq 8(%r10,%r15,8), %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_13: # %.lr.ph.i.i27
# Parent Loop BB7_2 Depth=1
# Parent Loop BB7_9 Depth=2
# Parent Loop BB7_11 Depth=3
# => This Inner Loop Header: Depth=4
movzbl (%r13,%rax), %ecx
movzbl (%r12,%rax), %edx
cmpb %dl, %cl
jg .LBB7_18
# %bb.14: # in Loop: Header=BB7_13 Depth=4
jl .LBB7_19
# %bb.15: # in Loop: Header=BB7_13 Depth=4
leaq 1(%rax), %rcx
cmpq %rax, %rbx
movq %rcx, %rax
jne .LBB7_13
jmp .LBB7_19
.p2align 4, 0x90
.LBB7_21: # %_Z21sort_fourbit_suffixesPPcii.exit
# in Loop: Header=BB7_2 Depth=1
testl %esi, %esi
movq 48(%rsp), %r8 # 8-byte Reload
movq 88(%rsp), %r9 # 8-byte Reload
jle .LBB7_24
# %bb.22: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
movl %r9d, %eax
shlq $3, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_23: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r10,%rcx,8), %rdx
movq fourbit_sorted_suffixes_original(%rip), %rdi
addq %rax, %rdi
movq %rdx, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %r8
jne .LBB7_23
jmp .LBB7_24
.LBB7_25: # %._crit_edge35
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z8pipelinePPcii, .Lfunc_end7-_Z8pipelinePPcii
.cfi_endproc
# -- End function
.globl _Z26mergeAllSorted4bitSuffixesPPcii # -- Begin function _Z26mergeAllSorted4bitSuffixesPPcii
.p2align 4, 0x90
.type _Z26mergeAllSorted4bitSuffixesPPcii,@function
_Z26mergeAllSorted4bitSuffixesPPcii: # @_Z26mergeAllSorted4bitSuffixesPPcii
.cfi_startproc
# %bb.0:
retq
.Lfunc_end8:
.size _Z26mergeAllSorted4bitSuffixesPPcii, .Lfunc_end8-_Z26mergeAllSorted4bitSuffixesPPcii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq 8(%rsi), %rdi
movl $read_count, %esi
movl $read_length, %edx
callq _Z10inputReadsPcPiS0_
movq %rax, %rbx
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl read_length(%rip), %esi
movl read_count(%rip), %edx
movq %rbx, %rdi
callq _Z8pipelinePPcii
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rsi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 8(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 16(%rsp), %rcx
addq %rax, %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB9_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB9_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB9_4
.LBB9_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB9_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorpd %xmm0, %xmm0
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB9_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i8
cmpb $0, 56(%rbx)
je .LBB9_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB9_8
.LBB9_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB9_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit11
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB9_9:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.type fourbit_sorted_suffixes_student,@object # @fourbit_sorted_suffixes_student
.bss
.globl fourbit_sorted_suffixes_student
.p2align 3, 0x0
fourbit_sorted_suffixes_student:
.quad 0
.size fourbit_sorted_suffixes_student, 8
.type read_count,@object # @read_count
.globl read_count
.p2align 2, 0x0
read_count:
.long 0 # 0x0
.size read_count, 4
.type read_length,@object # @read_length
.globl read_length
.p2align 2, 0x0
read_length:
.long 0 # 0x0
.size read_length, 4
.type fourbit_sorted_suffixes_original,@object # @fourbit_sorted_suffixes_original
.globl fourbit_sorted_suffixes_original
.p2align 3, 0x0
fourbit_sorted_suffixes_original:
.quad 0
.size fourbit_sorted_suffixes_original, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Speedup="
.size .L.str.1, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym read_count
.addrsig_sym read_length
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006cde_00000000-6_FMIndex.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4051:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4051:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.text
.globl _Z10inputReadsPcPiS0_
.type _Z10inputReadsPcPiS0_, @function
_Z10inputReadsPcPiS0_:
.LFB4039:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %rbx
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %r12d
jmp .L7
.L23:
addl $1, %r12d
.L7:
movq %rbp, %rdi
call fgetc@PLT
cmpl $10, %eax
je .L23
cmpl $-1, %eax
jne .L7
movq %rbp, %rdi
call rewind@PLT
movslq %r12d, %rax
leaq 0(,%rax,8), %r14
movq %r14, 8(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
movl %r12d, (%rbx)
movq $0, 16(%rsp)
testl %r12d, %r12d
jle .L8
movq %rax, %rbx
addq %rax, %r14
leaq 16(%rsp), %r13
.L9:
movq $0, (%rbx)
movq $0, 16(%rsp)
movq %rbp, %rcx
movl $10, %edx
movq %r13, %rsi
movq %rbx, %rdi
call __getdelim@PLT
addq $8, %rbx
cmpq %r14, %rbx
jne .L9
movq %rbp, %rdi
call fclose@PLT
movq (%r15), %rcx
cmpb $10, (%rcx)
je .L10
.L14:
movl $1, %eax
.L11:
movq %rax, %rdx
addq $1, %rax
cmpb $10, -1(%rcx,%rax)
jne .L11
leal 1(%rdx), %eax
movq (%rsp), %rsi
movl %eax, (%rsi)
testl %r12d, %r12d
jle .L3
.L16:
movq %r15, %rax
movq 8(%rsp), %rsi
addq %r15, %rsi
.L13:
movq (%rax), %rcx
movb $36, (%rcx,%rdx)
addq $8, %rax
cmpq %rsi, %rax
jne .L13
.L3:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L24
movq %r15, %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movq %rbp, %rdi
call fclose@PLT
movq (%r15), %rcx
cmpb $10, (%rcx)
jne .L14
movq (%rsp), %rax
movl $1, (%rax)
jmp .L3
.L10:
movq (%rsp), %rax
movl $1, (%rax)
movl $0, %edx
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4039:
.size _Z10inputReadsPcPiS0_, .-_Z10inputReadsPcPiS0_
.globl _Z7checkerv
.type _Z7checkerv, @function
_Z7checkerv:
.LFB4040:
.cfi_startproc
endbr64
movl read_length(%rip), %r11d
movl %r11d, %eax
imull read_count(%rip), %eax
testl %eax, %eax
jle .L32
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %r11d, %edi
shrl $31, %edi
addl %r11d, %edi
sarl %edi
movq fourbit_sorted_suffixes_student(%rip), %rbp
movq fourbit_sorted_suffixes_original(%rip), %rbx
cltq
leaq 0(,%rax,8), %r10
movl $0, %r9d
movl $1, %edx
movl $0, %r8d
jmp .L27
.L30:
movq 0(%rbp,%r9), %rsi
movq (%rbx,%r9), %rcx
movl $0, %eax
.L29:
movzbl (%rcx,%rax), %r14d
cmpb %r14b, (%rsi,%rax)
cmovne %r8d, %edx
addq $1, %rax
cmpl %eax, %edi
jg .L29
.L31:
addq $8, %r9
cmpq %r10, %r9
je .L25
.L27:
cmpl $1, %r11d
jg .L30
jmp .L31
.L32:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 14
movl $1, %edx
movl %edx, %eax
ret
.L25:
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
.cfi_offset 6, -24
.cfi_offset 14, -16
movl %edx, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4040:
.size _Z7checkerv, .-_Z7checkerv
.globl _Z10rotateReadPci
.type _Z10rotateReadPci, @function
_Z10rotateReadPci:
.LFB4041:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
movzbl (%rdi), %eax
movl %eax, %esi
sall $4, %esi
shrb $4, %al
movb %al, (%rdi)
cmpl $1, %ebp
jle .L40
leaq 1(%rdi), %rax
leal -2(%rbp), %edx
leaq 2(%rdi,%rdx), %rdi
.L41:
movzbl (%rax), %ecx
movl %ecx, %edx
shrb $4, %dl
orl %esi, %edx
movl %ecx, %esi
sall $4, %esi
movb %dl, (%rax)
addq $1, %rax
cmpq %rdi, %rax
jne .L41
orb %sil, (%rbx)
movslq %ebp, %r12
movq %r12, %rdi
call malloc@PLT
.L45:
movl $0, %edx
.L44:
movzbl (%rbx,%rdx), %ecx
movb %cl, (%rax,%rdx)
addq $1, %rdx
cmpq %rdx, %r12
jne .L44
.L39:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
orb %sil, (%rdi)
movslq %ebp, %r12
movq %r12, %rdi
call malloc@PLT
testl %ebp, %ebp
jle .L39
jmp .L45
.cfi_endproc
.LFE4041:
.size _Z10rotateReadPci, .-_Z10rotateReadPci
.globl _Z16generateSuffixesPci
.type _Z16generateSuffixesPci, @function
_Z16generateSuffixesPci:
.LFB4042:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebp
leal (%rsi,%rsi), %ebx
movslq %ebx, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L50
movq %rax, %rbx
leal -1(%rbp,%rbp), %eax
leaq 8(%r14,%rax,8), %r13
.L52:
movl %ebp, %esi
movq %r12, %rdi
call _Z10rotateReadPci
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L52
.L50:
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4042:
.size _Z16generateSuffixesPci, .-_Z16generateSuffixesPci
.globl _Z12compSuffixesPcS_i
.type _Z12compSuffixesPcS_i, @function
_Z12compSuffixesPcS_i:
.LFB4043:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L58
movslq %edx, %rdx
movl $0, %eax
.L57:
movzbl (%rdi,%rax), %r8d
movzbl (%rsi,%rax), %ecx
cmpb %cl, %r8b
jg .L59
jl .L60
addq $1, %rax
cmpq %rdx, %rax
jne .L57
movl $0, %eax
ret
.L58:
movl $0, %eax
ret
.L59:
movl $1, %eax
ret
.L60:
movl $-1, %eax
ret
.cfi_endproc
.LFE4043:
.size _Z12compSuffixesPcS_i, .-_Z12compSuffixesPcS_i
.globl _Z17fourbitEncodeReadPci
.type _Z17fourbitEncodeReadPci, @function
_Z17fourbitEncodeReadPci:
.LFB4044:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
movl %esi, %edi
shrl $31, %edi
addl %esi, %edi
sarl %edi
movslq %edi, %rdi
movl $1, %esi
call calloc@PLT
movq %rax, %rdi
testl %ebp, %ebp
jle .L62
movslq %ebp, %r8
movl $0, %ecx
movl $2, %r10d
movl $0, %r9d
jmp .L67
.L65:
cmpb $71, %al
setne %dl
addl $3, %edx
.L64:
movl %edx, %eax
sall $4, %eax
testb $1, %sil
cmove %eax, %edx
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
cltq
orb %dl, (%rdi,%rax)
addq $1, %rcx
cmpq %r8, %rcx
je .L62
.L67:
movl %ecx, %esi
movzbl (%rbx,%rcx), %eax
cmpb $67, %al
je .L68
jg .L65
movl %r9d, %edx
cmpb $36, %al
je .L64
cmpb $65, %al
setne %dl
leal 1(%rdx,%rdx,2), %edx
jmp .L64
.L68:
movl %r10d, %edx
jmp .L64
.L62:
movq %rdi, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4044:
.size _Z17fourbitEncodeReadPci, .-_Z17fourbitEncodeReadPci
.globl _Z21sort_fourbit_suffixesPPcii
.type _Z21sort_fourbit_suffixesPPcii, @function
_Z21sort_fourbit_suffixesPPcii:
.LFB4045:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %edx, %r15d
movslq %edx, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, (%rsp)
cmpl $1, %ebx
jle .L74
movl %ebx, 12(%rsp)
leaq 16(%r14), %rax
movq %rax, 24(%rsp)
jmp .L76
.L77:
addq $8, %rbx
cmpq %r14, %rbx
je .L84
.L78:
movq (%rbx), %r12
movq -8(%rbx), %rbp
movl %r15d, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z12compSuffixesPcS_i
testl %eax, %eax
jle .L77
movq %r13, %rcx
movq %r13, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call __memcpy_chk@PLT
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call memcpy@PLT
movq (%rbx), %rdi
movq %r13, %rdx
movq (%rsp), %rsi
call memcpy@PLT
jmp .L77
.L84:
subl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl $1, %eax
je .L74
.L76:
cmpl $1, 12(%rsp)
jle .L85
movq 16(%rsp), %rax
leaq 8(%rax), %rbx
movl 12(%rsp), %eax
leal -2(%rax), %eax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,8), %r14
jmp .L78
.L85:
subl $1, 12(%rsp)
jmp .L76
.L74:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _Z21sort_fourbit_suffixesPPcii, .-_Z21sort_fourbit_suffixesPPcii
.globl _Z8pipelinePPcii
.type _Z8pipelinePPcii, @function
_Z8pipelinePPcii:
.LFB4046:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %ebx
movl %esi, %edi
imull %edx, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, fourbit_sorted_suffixes_original(%rip)
testl %ebx, %ebx
jle .L86
movl %ebp, %r14d
shrl $31, %r14d
addl %ebp, %r14d
sarl %r14d
movq %r13, %r12
movslq %ebx, %rbx
leaq 0(%r13,%rbx,8), %r15
movl $0, %r13d
movslq %ebp, %rax
movq %rax, 8(%rsp)
.L90:
movq (%r12), %rdi
movl %ebp, %esi
call _Z17fourbitEncodeReadPci
movq %rax, %rdi
movl %r14d, %esi
call _Z16generateSuffixesPci
movq %rax, %rbx
movl %r14d, %edx
movl %ebp, %esi
movq %rax, %rdi
call _Z21sort_fourbit_suffixesPPcii
testl %ebp, %ebp
jle .L88
movslq %r13d, %rdx
leaq 0(,%rdx,8), %rax
movq 8(%rsp), %rsi
addq %rdx, %rsi
salq $3, %rsi
negq %rdx
leaq (%rbx,%rdx,8), %rdi
.L89:
movq (%rdi,%rax), %rcx
movq fourbit_sorted_suffixes_original(%rip), %rdx
movq %rcx, (%rdx,%rax)
addq $8, %rax
cmpq %rsi, %rax
jne .L89
.L88:
addq $8, %r12
addl %ebp, %r13d
cmpq %r15, %r12
jne .L90
.L86:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4046:
.size _Z8pipelinePPcii, .-_Z8pipelinePPcii
.globl _Z26mergeAllSorted4bitSuffixesPPcii
.type _Z26mergeAllSorted4bitSuffixesPPcii, @function
_Z26mergeAllSorted4bitSuffixesPPcii:
.LFB4047:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE4047:
.size _Z26mergeAllSorted4bitSuffixesPPcii, .-_Z26mergeAllSorted4bitSuffixesPPcii
.section .rodata.str1.1
.LC2:
.string "Speedup="
.text
.globl main
.type main, @function
main:
.LFB4048:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
leaq read_length(%rip), %rdx
leaq read_count(%rip), %rsi
call _Z10inputReadsPcPiS0_
movq %rax, %r12
movq %rsp, %rbp
leaq 16(%rsp), %rbx
movq %rbp, %rsi
movq %rbx, %rdi
call gettimeofday@PLT
movl read_count(%rip), %edx
movl read_length(%rip), %esi
movq %r12, %rdi
call _Z8pipelinePPcii
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
call gettimeofday@PLT
imulq $1000000, 32(%rsp), %rax
addq 40(%rsp), %rax
imulq $1000000, 16(%rsp), %rdx
addq 24(%rsp), %rdx
subq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call gettimeofday@PLT
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L98
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4048:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4074:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl fourbit_sorted_suffixes_original
.bss
.align 8
.type fourbit_sorted_suffixes_original, @object
.size fourbit_sorted_suffixes_original, 8
fourbit_sorted_suffixes_original:
.zero 8
.globl read_length
.align 4
.type read_length, @object
.size read_length, 4
read_length:
.zero 4
.globl read_count
.align 4
.type read_count, @object
.size read_count, 4
read_count:
.zero 4
.globl fourbit_sorted_suffixes_student
.align 8
.type fourbit_sorted_suffixes_student, @object
.size fourbit_sorted_suffixes_student, 8
fourbit_sorted_suffixes_student:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "FMIndex.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10inputReadsPcPiS0_ # -- Begin function _Z10inputReadsPcPiS0_
.p2align 4, 0x90
.type _Z10inputReadsPcPiS0_,@function
_Z10inputReadsPcPiS0_: # @_Z10inputReadsPcPiS0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, %rbx
movl $.L.str, %esi
callq fopen
movq %rax, %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq fgetc
xorl %ecx, %ecx
cmpl $10, %eax
sete %cl
addl %ecx, %ebp
cmpl $-1, %eax
jne .LBB0_1
# %bb.2:
movq %r15, %rdi
callq rewind
movl %ebp, %r12d
leaq (,%r12,8), %rdi
callq malloc
movq %rax, %r14
movl %ebp, (%rbx)
movq $0, 8(%rsp)
testl %ebp, %ebp
je .LBB0_5
# %bb.3: # %.lr.ph.preheader
movq %r12, %rbx
movq %r14, %r13
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq $0, (%r13)
movq $0, 8(%rsp)
movq %r13, %rdi
leaq 8(%rsp), %rsi
movl $10, %edx
movq %r15, %rcx
callq __getdelim
addq $8, %r13
decq %rbx
jne .LBB0_4
.LBB0_5: # %._crit_edge
movq %r15, %rdi
callq fclose
movq (%r14), %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_6: # =>This Inner Loop Header: Depth=1
cmpb $10, (%rcx,%rax)
leaq 1(%rax), %rax
jne .LBB0_6
# %bb.7:
movq 16(%rsp), %rcx # 8-byte Reload
movl %eax, (%rcx)
testl %ebp, %ebp
je .LBB0_10
# %bb.8: # %.lr.ph36.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_9: # %.lr.ph36
# =>This Inner Loop Header: Depth=1
movq (%r14,%rcx,8), %rdx
movb $36, -1(%rdx,%rax)
incq %rcx
cmpq %rcx, %r12
jne .LBB0_9
.LBB0_10: # %._crit_edge37
movq %r14, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10inputReadsPcPiS0_, .Lfunc_end0-_Z10inputReadsPcPiS0_
.cfi_endproc
# -- End function
.globl _Z7checkerv # -- Begin function _Z7checkerv
.p2align 4, 0x90
.type _Z7checkerv,@function
_Z7checkerv: # @_Z7checkerv
.cfi_startproc
# %bb.0:
movl read_length(%rip), %ecx
movl read_count(%rip), %eax
imull %ecx, %eax
testl %eax, %eax
jle .LBB1_1
# %bb.3: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
movq fourbit_sorted_suffixes_student(%rip), %rsi
movq fourbit_sorted_suffixes_original(%rip), %rdi
movl %eax, %r8d
movl $1, %eax
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=1
incq %r10
cmpq %r8, %r10
je .LBB1_8
.LBB1_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
cmpl $2, %ecx
jl .LBB1_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movq (%rsi,%r10,8), %r11
movq (%rdi,%r10,8), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r11,%r14), %ebp
cmpb (%rbx,%r14), %bpl
cmovnel %r9d, %eax
incq %r14
cmpq %r14, %rdx
jne .LBB1_6
jmp .LBB1_7
.LBB1_8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %rbp
retq
.LBB1_1:
movl $1, %eax
retq
.Lfunc_end1:
.size _Z7checkerv, .Lfunc_end1-_Z7checkerv
.cfi_endproc
# -- End function
.globl _Z10rotateReadPci # -- Begin function _Z10rotateReadPci
.p2align 4, 0x90
.type _Z10rotateReadPci,@function
_Z10rotateReadPci: # @_Z10rotateReadPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movzbl (%rdi), %ecx
movl %ecx, %eax
shrb $4, %al
movb %al, (%rdi)
shlb $4, %cl
movl %esi, %r14d
cmpl $2, %esi
jl .LBB2_1
# %bb.5: # %.lr.ph.preheader
movl $1, %edx
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rdx), %esi
movl %esi, %edi
shrb $4, %dil
orb %cl, %dil
movb %dil, (%rbx,%rdx)
incq %rdx
shlb $4, %sil
movl %esi, %ecx
cmpq %rdx, %r14
jne .LBB2_6
jmp .LBB2_2
.LBB2_1:
movl %ecx, %esi
.LBB2_2: # %._crit_edge
orb %al, %sil
movb %sil, (%rbx)
movslq %ebp, %rdi
callq malloc
testl %ebp, %ebp
jle .LBB2_4
# %bb.3: # %.lr.ph33.preheader
movq %rax, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movq %rax, %rbx
callq memcpy@PLT
movq %rbx, %rax
.LBB2_4: # %._crit_edge34
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10rotateReadPci, .Lfunc_end2-_Z10rotateReadPci
.cfi_endproc
# -- End function
.globl _Z16generateSuffixesPci # -- Begin function _Z16generateSuffixesPci
.p2align 4, 0x90
.type _Z16generateSuffixesPci,@function
_Z16generateSuffixesPci: # @_Z16generateSuffixesPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r15d
movq %rdi, %r14
leal (%r15,%r15), %ebx
movslq %ebx, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r15, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB3_5
# %bb.1: # %.lr.ph
movl 8(%rsp), %r12d # 4-byte Reload
movzbl (%r14), %eax
cmpl $2, %ebx
movl $1, %ebp
cmovgel %ebx, %ebp
xorl %ebx, %ebx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_3: # in Loop: Header=BB3_2 Depth=1
movl %eax, %r15d
.LBB3_4: # %._crit_edge.i
# in Loop: Header=BB3_2 Depth=1
orb %cl, %r15b
movb %r15b, (%r14)
movq %r12, %rdi
callq malloc
movq %rax, %r13
movq %rax, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq memcpy@PLT
movq 16(%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbx,8)
incq %rbx
movl %r15d, %eax
cmpq %rbp, %rbx
je .LBB3_5
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
movl %eax, %ecx
shrb $4, %cl
shlb $4, %al
movb %cl, (%r14)
cmpl $1, 8(%rsp) # 4-byte Folded Reload
je .LBB3_3
# %bb.6: # %.lr.ph.i.preheader
# in Loop: Header=BB3_2 Depth=1
movl $1, %edx
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r14,%rdx), %r15d
movl %r15d, %esi
shrb $4, %sil
orb %al, %sil
movb %sil, (%r14,%rdx)
incq %rdx
shlb $4, %r15b
movl %r15d, %eax
cmpq %rdx, %r12
jne .LBB3_7
jmp .LBB3_4
.LBB3_5: # %._crit_edge
movq 16(%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16generateSuffixesPci, .Lfunc_end3-_Z16generateSuffixesPci
.cfi_endproc
# -- End function
.globl _Z12compSuffixesPcS_i # -- Begin function _Z12compSuffixesPcS_i
.p2align 4, 0x90
.type _Z12compSuffixesPcS_i,@function
_Z12compSuffixesPcS_i: # @_Z12compSuffixesPcS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rsi,%rcx), %edx
cmpb %dl, (%rdi,%rcx)
jg .LBB4_7
# %bb.3: # in Loop: Header=BB4_2 Depth=1
jl .LBB4_8
# %bb.4: # in Loop: Header=BB4_2 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB4_2
.LBB4_6:
xorl %eax, %eax
retq
.LBB4_7:
movl $1, %eax
retq
.LBB4_8:
movl $-1, %eax
retq
.Lfunc_end4:
.size _Z12compSuffixesPcS_i, .Lfunc_end4-_Z12compSuffixesPcS_i
.cfi_endproc
# -- End function
.globl _Z17fourbitEncodeReadPci # -- Begin function _Z17fourbitEncodeReadPci
.p2align 4, 0x90
.type _Z17fourbitEncodeReadPci,@function
_Z17fourbitEncodeReadPci: # @_Z17fourbitEncodeReadPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
sarl %eax
movslq %eax, %rdi
movl $1, %esi
callq calloc
testl %ebp, %ebp
jle .LBB5_9
# %bb.1: # %.lr.ph.preheader
movl %ebp, %ecx
xorl %edx, %edx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_2 Depth=1
movl $2, %esi
.LBB5_8: # in Loop: Header=BB5_2 Depth=1
movl %esi, %edi
shll $4, %edi
movl %edx, %r8d
shrl %r8d
testb $1, %dl
cmovnel %esi, %edi
orb %dil, (%rax,%r8)
incq %rdx
cmpq %rdx, %rcx
je .LBB5_9
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movzbl (%rbx,%rdx), %edi
addl $-36, %edi
cmpl $35, %edi
ja .LBB5_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
xorl %esi, %esi
jmpq *.LJTI5_0(,%rdi,8)
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
movl $1, %esi
jmp .LBB5_8
.LBB5_6: # in Loop: Header=BB5_2 Depth=1
movl $3, %esi
jmp .LBB5_8
.LBB5_7: # in Loop: Header=BB5_2 Depth=1
movl $4, %esi
jmp .LBB5_8
.LBB5_9: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z17fourbitEncodeReadPci, .Lfunc_end5-_Z17fourbitEncodeReadPci
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI5_0:
.quad .LBB5_8
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_4
.quad .LBB5_7
.quad .LBB5_5
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_7
.quad .LBB5_6
# -- End function
.text
.globl _Z21sort_fourbit_suffixesPPcii # -- Begin function _Z21sort_fourbit_suffixesPPcii
.p2align 4, 0x90
.type _Z21sort_fourbit_suffixesPPcii,@function
_Z21sort_fourbit_suffixesPPcii: # @_Z21sort_fourbit_suffixesPPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %r14d
movq %rdi, 32(%rsp) # 8-byte Spill
movslq %edx, %rdi
movq %rdi, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movq %r14, 24(%rsp) # 8-byte Spill
cmpl $2, %r14d
jl .LBB6_10
# %bb.1: # %.preheader.lr.ph
movl %ebx, %esi
movq 24(%rsp), %rax # 8-byte Reload
decl %eax
movl %ebx, %r13d
decq %r13
xorl %ecx, %ecx
movl %eax, 16(%rsp) # 4-byte Spill
movl %eax, 12(%rsp) # 4-byte Spill
movl %ebx, 20(%rsp) # 4-byte Spill
movq 48(%rsp), %r12 # 8-byte Reload
movq 56(%rsp), %r15 # 8-byte Reload
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_9: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
movq 40(%rsp), %rcx # 8-byte Reload
incl %ecx
decl 12(%rsp) # 4-byte Folded Spill
cmpl 16(%rsp), %ecx # 4-byte Folded Reload
je .LBB6_10
.LBB6_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
# Child Loop BB6_6 Depth 3
movq %rcx, 40(%rsp) # 8-byte Spill
movl %ecx, %eax
subl 24(%rsp), %eax # 4-byte Folded Reload
cmpl $-2, %eax
jg .LBB6_9
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB6_2 Depth=1
movl 12(%rsp), %edi # 4-byte Reload
xorl %ebx, %ebx
movq %rdi, 64(%rsp) # 8-byte Spill
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_11: # %_Z12compSuffixesPcS_i.exit
# in Loop: Header=BB6_4 Depth=2
movq %r12, %rdi
movq %rbp, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq %rbp, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq 32(%rsp), %rax # 8-byte Reload
movq (%rax,%rbx,8), %rdi
movq %r12, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq 64(%rsp), %rdi # 8-byte Reload
movl 20(%rsp), %esi # 4-byte Reload
.LBB6_12: # %.critedge
# in Loop: Header=BB6_4 Depth=2
cmpq %rdi, %rbx
je .LBB6_9
.LBB6_4: # %.lr.ph
# Parent Loop BB6_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_6 Depth 3
movq %rbx, %rax
incq %rbx
testl %esi, %esi
jle .LBB6_12
# %bb.5: # %.lr.ph.i.preheader
# in Loop: Header=BB6_4 Depth=2
movq 32(%rsp), %rcx # 8-byte Reload
movq (%rcx,%rax,8), %rbp
movq 8(%rcx,%rax,8), %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_6: # %.lr.ph.i
# Parent Loop BB6_2 Depth=1
# Parent Loop BB6_4 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%rbp,%rax), %ecx
movzbl (%r14,%rax), %edx
cmpb %dl, %cl
jg .LBB6_11
# %bb.7: # in Loop: Header=BB6_6 Depth=3
jl .LBB6_12
# %bb.8: # in Loop: Header=BB6_6 Depth=3
leaq 1(%rax), %rcx
cmpq %rax, %r13
movq %rcx, %rax
jne .LBB6_6
jmp .LBB6_12
.LBB6_10: # %._crit_edge28
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z21sort_fourbit_suffixesPPcii, .Lfunc_end6-_Z21sort_fourbit_suffixesPPcii
.cfi_endproc
# -- End function
.globl _Z8pipelinePPcii # -- Begin function _Z8pipelinePPcii
.p2align 4, 0x90
.type _Z8pipelinePPcii,@function
_Z8pipelinePPcii: # @_Z8pipelinePPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %ebx
movq %rdi, 72(%rsp) # 8-byte Spill
movl %edx, %eax
imull %esi, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, fourbit_sorted_suffixes_original(%rip)
testl %ebp, %ebp
jle .LBB7_25
# %bb.1: # %.lr.ph34
movq %rbx, %rsi
movl %esi, %eax
shrl $31, %eax
addl %esi, %eax
movl %eax, %ecx
sarl %ecx
andl $-2, %eax
cltq
movl %esi, %edx
andl $2147483646, %edx # imm = 0x7FFFFFFE
movl %edx, 16(%rsp) # 4-byte Spill
cmpl $2, %eax
movl $1, %edx
cmovgel %eax, %edx
movq %rdx, 96(%rsp) # 8-byte Spill
leaq (,%rax,8), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movslq %ecx, %rax
movq %rax, 32(%rsp) # 8-byte Spill
leal -1(%rbx), %edx
movl %edx, (%rsp) # 4-byte Spill
movl %ebp, %edx
movq %rdx, 56(%rsp) # 8-byte Spill
movl %esi, %r8d
movq %rcx, 24(%rsp) # 8-byte Spill
leaq -1(%rcx), %rbx
xorl %r9d, %r9d
xorl %ecx, %ecx
movq %rsi, 40(%rsp) # 8-byte Spill
movq %r8, 48(%rsp) # 8-byte Spill
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_24: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movq 80(%rsp), %rcx # 8-byte Reload
incq %rcx
addl %esi, %r9d
cmpq 56(%rsp), %rcx # 8-byte Folded Reload
je .LBB7_25
.LBB7_2: # =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
# Child Loop BB7_17 Depth 3
# Child Loop BB7_9 Depth 2
# Child Loop BB7_11 Depth 3
# Child Loop BB7_13 Depth 4
# Child Loop BB7_23 Depth 2
movq %r9, 88(%rsp) # 8-byte Spill
movq 72(%rsp), %rax # 8-byte Reload
movq %rcx, 80(%rsp) # 8-byte Spill
movq (%rax,%rcx,8), %rdi
movq %rsi, %r15
callq _Z17fourbitEncodeReadPci
movq %rax, %r14
movq 64(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
cmpl $2, %r15d
jl .LBB7_7
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB7_2 Depth=1
movzbl (%r14), %ecx
xorl %r15d, %r15d
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_5: # in Loop: Header=BB7_4 Depth=2
movl %ecx, %r13d
movq 24(%rsp), %rbp # 8-byte Reload
.LBB7_6: # %._crit_edge.i.i
# in Loop: Header=BB7_4 Depth=2
orb %al, %r13b
movb %r13b, (%r14)
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %rax, %rdi
movq %r14, %rsi
movq %rbp, %rdx
callq memcpy@PLT
movq 8(%rsp), %rax # 8-byte Reload
movq %r12, (%rax,%r15,8)
incq %r15
movl %r13d, %ecx
cmpq 96(%rsp), %r15 # 8-byte Folded Reload
je .LBB7_7
.LBB7_4: # Parent Loop BB7_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_17 Depth 3
movl %ecx, %eax
shrb $4, %al
shlb $4, %cl
movb %al, (%r14)
cmpl $2, 16(%rsp) # 4-byte Folded Reload
je .LBB7_5
# %bb.16: # %.lr.ph.i.i.preheader
# in Loop: Header=BB7_4 Depth=2
movl $1, %edx
movq 24(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB7_17: # %.lr.ph.i.i
# Parent Loop BB7_2 Depth=1
# Parent Loop BB7_4 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%r14,%rdx), %r13d
movl %r13d, %esi
shrb $4, %sil
orb %cl, %sil
movb %sil, (%r14,%rdx)
incq %rdx
shlb $4, %r13b
movl %r13d, %ecx
cmpq %rdx, %rbp
jne .LBB7_17
jmp .LBB7_6
.p2align 4, 0x90
.LBB7_7: # %_Z16generateSuffixesPci.exit
# in Loop: Header=BB7_2 Depth=1
movq 32(%rsp), %rdi # 8-byte Reload
callq malloc
movq 8(%rsp), %r10 # 8-byte Reload
movq %rax, 104(%rsp) # 8-byte Spill
movq 40(%rsp), %rsi # 8-byte Reload
cmpl $2, %esi
jl .LBB7_21
# %bb.8: # %.preheader.i.preheader
# in Loop: Header=BB7_2 Depth=1
xorl %eax, %eax
movl (%rsp), %ecx # 4-byte Reload
movl %ecx, 4(%rsp) # 4-byte Spill
jmp .LBB7_9
.p2align 4, 0x90
.LBB7_20: # %._crit_edge.i
# in Loop: Header=BB7_9 Depth=2
movl 20(%rsp), %eax # 4-byte Reload
incl %eax
decl 4(%rsp) # 4-byte Folded Spill
cmpl (%rsp), %eax # 4-byte Folded Reload
je .LBB7_21
.LBB7_9: # %.preheader.i
# Parent Loop BB7_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_11 Depth 3
# Child Loop BB7_13 Depth 4
movl %eax, 20(%rsp) # 4-byte Spill
subl %esi, %eax
cmpl $-2, %eax
jg .LBB7_20
# %bb.10: # %.lr.ph.preheader.i
# in Loop: Header=BB7_9 Depth=2
movl 4(%rsp), %edi # 4-byte Reload
xorl %r15d, %r15d
movq %rdi, 112(%rsp) # 8-byte Spill
jmp .LBB7_11
.p2align 4, 0x90
.LBB7_18: # %_Z12compSuffixesPcS_i.exit.i
# in Loop: Header=BB7_11 Depth=3
movq 104(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movq %r13, %rsi
movq 32(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
callq memcpy@PLT
movq %r13, %rdi
movq %r12, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %r12, %rdi
movq %rbp, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq 112(%rsp), %rdi # 8-byte Reload
movq 8(%rsp), %r10 # 8-byte Reload
movq 40(%rsp), %rsi # 8-byte Reload
.LBB7_19: # %.critedge.i
# in Loop: Header=BB7_11 Depth=3
incq %r15
cmpq %rdi, %r15
je .LBB7_20
.LBB7_11: # %.lr.ph.i23
# Parent Loop BB7_2 Depth=1
# Parent Loop BB7_9 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB7_13 Depth 4
cmpl $2, %esi
jl .LBB7_19
# %bb.12: # %.lr.ph.i.i27.preheader
# in Loop: Header=BB7_11 Depth=3
movq (%r10,%r15,8), %r13
movq 8(%r10,%r15,8), %r12
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_13: # %.lr.ph.i.i27
# Parent Loop BB7_2 Depth=1
# Parent Loop BB7_9 Depth=2
# Parent Loop BB7_11 Depth=3
# => This Inner Loop Header: Depth=4
movzbl (%r13,%rax), %ecx
movzbl (%r12,%rax), %edx
cmpb %dl, %cl
jg .LBB7_18
# %bb.14: # in Loop: Header=BB7_13 Depth=4
jl .LBB7_19
# %bb.15: # in Loop: Header=BB7_13 Depth=4
leaq 1(%rax), %rcx
cmpq %rax, %rbx
movq %rcx, %rax
jne .LBB7_13
jmp .LBB7_19
.p2align 4, 0x90
.LBB7_21: # %_Z21sort_fourbit_suffixesPPcii.exit
# in Loop: Header=BB7_2 Depth=1
testl %esi, %esi
movq 48(%rsp), %r8 # 8-byte Reload
movq 88(%rsp), %r9 # 8-byte Reload
jle .LBB7_24
# %bb.22: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
movl %r9d, %eax
shlq $3, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_23: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r10,%rcx,8), %rdx
movq fourbit_sorted_suffixes_original(%rip), %rdi
addq %rax, %rdi
movq %rdx, (%rdi,%rcx,8)
incq %rcx
cmpq %rcx, %r8
jne .LBB7_23
jmp .LBB7_24
.LBB7_25: # %._crit_edge35
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z8pipelinePPcii, .Lfunc_end7-_Z8pipelinePPcii
.cfi_endproc
# -- End function
.globl _Z26mergeAllSorted4bitSuffixesPPcii # -- Begin function _Z26mergeAllSorted4bitSuffixesPPcii
.p2align 4, 0x90
.type _Z26mergeAllSorted4bitSuffixesPPcii,@function
_Z26mergeAllSorted4bitSuffixesPPcii: # @_Z26mergeAllSorted4bitSuffixesPPcii
.cfi_startproc
# %bb.0:
retq
.Lfunc_end8:
.size _Z26mergeAllSorted4bitSuffixesPPcii, .Lfunc_end8-_Z26mergeAllSorted4bitSuffixesPPcii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI9_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq 8(%rsi), %rdi
movl $read_count, %esi
movl $read_length, %edx
callq _Z10inputReadsPcPiS0_
movq %rax, %rbx
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl read_length(%rip), %esi
movl read_count(%rip), %edx
movq %rbx, %rdi
callq _Z8pipelinePPcii
leaq 32(%rsp), %rdi
leaq 48(%rsp), %rsi
callq gettimeofday
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 8(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 16(%rsp), %rcx
addq %rax, %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI9_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB9_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB9_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB9_4
.LBB9_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB9_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorpd %xmm0, %xmm0
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB9_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i8
cmpb $0, 56(%rbx)
je .LBB9_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB9_8
.LBB9_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB9_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit11
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB9_9:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.type fourbit_sorted_suffixes_student,@object # @fourbit_sorted_suffixes_student
.bss
.globl fourbit_sorted_suffixes_student
.p2align 3, 0x0
fourbit_sorted_suffixes_student:
.quad 0
.size fourbit_sorted_suffixes_student, 8
.type read_count,@object # @read_count
.globl read_count
.p2align 2, 0x0
read_count:
.long 0 # 0x0
.size read_count, 4
.type read_length,@object # @read_length
.globl read_length
.p2align 2, 0x0
read_length:
.long 0 # 0x0
.size read_length, 4
.type fourbit_sorted_suffixes_original,@object # @fourbit_sorted_suffixes_original
.globl fourbit_sorted_suffixes_original
.p2align 3, 0x0
fourbit_sorted_suffixes_original:
.quad 0
.size fourbit_sorted_suffixes_original, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Speedup="
.size .L.str.1, 9
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym read_count
.addrsig_sym read_length
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#include <cuda_profiler_api.h>
// function to add the elements of two arrays
void add_cpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_cpu(){
std::cout << "Running on cpu." << std::endl;
int N = 1<<20; // 1M elements
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
add_cpu(N, x, y);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
}
__global__
void add_gpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_gpu()
{
cudaProfilerStart();
std::cout << "Running on gpu." << std::endl;
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add_gpu<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
cudaDeviceReset();
cudaProfilerStop();
}
int main(void)
{
on_cpu();
on_gpu();
return 0;
} | code for sm_80
Function : _Z7add_gpuiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xaa0 ; /* 0x00000a0000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fd60000000f00 */
/*0110*/ @!P0 BRA 0x8f0 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x610 ; /* 0x000004c000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0190*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*01b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*01d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*01e0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*0200*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0220*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0230*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*0240*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0260*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*0270*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0280*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0290*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0003e8000c10190a */
/*02b0*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ea8000c1e1900 */
/*02c0*/ LDG.E R7, [R4.64+0x20] ; /* 0x0000200a04077981 */
/* 0x002ee2000c1e1900 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*02e0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0001e8000c10190a */
/*0300*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0320*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0330*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0340*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0360*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x000fe8000c10190a */
/*0370*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000ee4000c1e1900 */
/*0380*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0390*/ LDG.E R8, [R4.64+0x24] ; /* 0x0000240a04087981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0003e8000c10190a */
/*03b0*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240a02097981 */
/* 0x001ea8000c1e1900 */
/*03c0*/ LDG.E R7, [R4.64+0x30] ; /* 0x0000300a04077981 */
/* 0x002ee2000c1e1900 */
/*03d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*03e0*/ LDG.E R8, [R4.64+0x28] ; /* 0x0000280a04087981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0001e8000c10190a */
/*0400*/ LDG.E R11, [R2.64+0x28] ; /* 0x0000280a020b7981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0420*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0430*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0003e8000c10190a */
/*0440*/ LDG.E R13, [R2.64+0x2c] ; /* 0x00002c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0460*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0005e8000c10190a */
/*0470*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000ee4000c1e1900 */
/*0480*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0490*/ LDG.E R8, [R4.64+0x34] ; /* 0x0000340a04087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0009e8000c10190a */
/*04b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340a02097981 */
/* 0x001ee4000c1e1900 */
/*04c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*04d0*/ LDG.E R8, [R4.64+0x38] ; /* 0x0000380a04087981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ STG.E [R4.64+0x34], R9 ; /* 0x0000340904007986 */
/* 0x000fe8000c10190a */
/*04f0*/ LDG.E R11, [R2.64+0x38] ; /* 0x0000380a020b7981 */
/* 0x002ee2000c1e1900 */
/*0500*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0510*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*0520*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0a04087981 */
/* 0x000ee8000c1e1900 */
/*0530*/ STG.E [R4.64+0x38], R11 ; /* 0x0000380b04007986 */
/* 0x000fe8000c10190a */
/*0540*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0550*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0560*/ IADD3 R7, P3, R4, 0x40, RZ ; /* 0x0000004004077810 */
/* 0x010fe20007f7e0ff */
/*0570*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0580*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*0590*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x001fe400017fe4ff */
/*05a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*05b0*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe40000000000 */
/*05c0*/ IMAD.X R8, RZ, RZ, R5, P3 ; /* 0x000000ffff087224 */
/* 0x000fc600018e0605 */
/*05d0*/ STG.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007986 */
/* 0x0001e4000c10190a */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*05f0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0600*/ @P1 BRA 0x160 ; /* 0xfffffb5000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x8d0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0650*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0660*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0670*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0680*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*06a0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*06b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*06d0*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*06f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0700*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c10190a */
/*0710*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0730*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0005e8000c10190a */
/*0740*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0750*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0760*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ee8000c1e1900 */
/*0770*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0009e8000c10190a */
/*0780*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ee4000c1e1900 */
/*0790*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*07a0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c10190a */
/*07c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x002ee4000c1e1900 */
/*07d0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*07e0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0800*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0810*/ IADD3 R7, P2, R4, 0x20, RZ ; /* 0x0000002004077810 */
/* 0x010fe40007f5e0ff */
/*0820*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc40007f3e0ff */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0840*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0850*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0870*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0880*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe20000000000 */
/*0890*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*08a0*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0001e4000c10190a */
/*08b0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x001fe20000000f00 */
/*08c0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0008 */
/*08d0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0xaa0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0910*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0920*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0930*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0940*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*0960*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*0970*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*0980*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*09b0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*09d0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x0002a2000c1e1900 */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*09f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0a00*/ IADD3 R7, P2, R4, 0x10, RZ ; /* 0x0000001004077810 */
/* 0x001fc40007f5e0ff */
/*0a10*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc80007f3e0ff */
/*0a20*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*0a30*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0a40*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fe40000000000 */
/*0a50*/ IMAD.X R8, RZ, RZ, R5, P2 ; /* 0x000000ffff087224 */
/* 0x000fc600010e0605 */
/*0a60*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e4000c10190a */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*0a80*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0a90*/ @P0 BRA 0x8f0 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ab0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ac0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0ad0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0ae0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0af0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0b00*/ UIMAD.WIDE UR4, UR4, UR5, UR8 ; /* 0x00000005040472a5 */
/* 0x000fe4000f8e0208 */
/*0b10*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe2000f8e00ff */
/*0b20*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe20008000f00 */
/*0b30*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b40*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0b60*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fc40000000f00 */
/*0b70*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0b80*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b90*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x001fe20000000f00 */
/*0ba0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0006 */
/*0bb0*/ LDG.E R5, [R4.64] ; /* 0x0000000a04057981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0bf0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0c00*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0c10*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fe20000000000 */
/*0c20*/ IADD3 R6, P1, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007f3e0ff */
/*0c30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c10190a */
/*0c40*/ IADD3.X R9, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff097210 */
/* 0x000fe20000ffe4ff */
/*0c50*/ @P0 BRA 0xb70 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0c60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#include <cuda_profiler_api.h>
// function to add the elements of two arrays
void add_cpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_cpu(){
std::cout << "Running on cpu." << std::endl;
int N = 1<<20; // 1M elements
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
add_cpu(N, x, y);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
}
__global__
void add_gpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_gpu()
{
cudaProfilerStart();
std::cout << "Running on gpu." << std::endl;
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add_gpu<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
cudaDeviceReset();
cudaProfilerStop();
}
int main(void)
{
on_cpu();
on_gpu();
return 0;
} | .file "tmpxft_00193d1d_00000000-6_vectoradd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7add_cpuiPfS_
.type _Z7add_cpuiPfS_, @function
_Z7add_cpuiPfS_:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movss (%rdx,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z7add_cpuiPfS_, .-_Z7add_cpuiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Running on cpu."
.LC6:
.string "Max error: "
.text
.globl _Z6on_cpuv
.type _Z6on_cpuv, @function
_Z6on_cpuv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl $15, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L19
cmpb $0, 56(%rbx)
je .L9
movzbl 67(%rbx), %eax
.L10:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L11:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L11
movq %rbp, %rdx
movq %r12, %rsi
movl $1048576, %edi
call _Z7add_cpuiPfS_
movq %rbp, %rbx
leaq 4194304(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L12:
movss (%rbx), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %r13
jne .L12
movl $11, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L20
cmpb $0, 56(%r13)
je .L14
movzbl 67(%r13), %eax
.L15:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L9:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L10
.L20:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L15
.cfi_endproc
.LFE3670:
.size _Z6on_cpuv, .-_Z6on_cpuv
.globl _Z29__device_stub__Z7add_gpuiPfS_iPfS_
.type _Z29__device_stub__Z7add_gpuiPfS_iPfS_, @function
_Z29__device_stub__Z7add_gpuiPfS_iPfS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7add_gpuiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z29__device_stub__Z7add_gpuiPfS_iPfS_, .-_Z29__device_stub__Z7add_gpuiPfS_iPfS_
.globl _Z7add_gpuiPfS_
.type _Z7add_gpuiPfS_, @function
_Z7add_gpuiPfS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7add_gpuiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7add_gpuiPfS_, .-_Z7add_gpuiPfS_
.section .rodata.str1.1
.LC7:
.string "Running on gpu."
.text
.globl _Z6on_gpuv
.type _Z6on_gpuv, @function
_Z6on_gpuv:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaProfilerStart@PLT
movl $15, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L45
cmpb $0, 56(%rbx)
je .L32
movzbl 67(%rbx), %eax
.L33:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L34:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L34
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L35:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L36:
movss (%rbx), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L36
movl $11, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L47
cmpb $0, 56(%rbp)
je .L39
movzbl 67(%rbp), %eax
.L40:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
call cudaProfilerStop@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L32:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L33
.L46:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z29__device_stub__Z7add_gpuiPfS_iPfS_
jmp .L35
.L47:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L39:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L40
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z6on_gpuv, .-_Z6on_gpuv
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z6on_cpuv
call _Z6on_gpuv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7add_gpuiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_gpuiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <cuda_profiler_api.h>
// function to add the elements of two arrays
void add_cpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_cpu(){
std::cout << "Running on cpu." << std::endl;
int N = 1<<20; // 1M elements
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
add_cpu(N, x, y);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
}
__global__
void add_gpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_gpu()
{
cudaProfilerStart();
std::cout << "Running on gpu." << std::endl;
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add_gpu<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
cudaDeviceReset();
cudaProfilerStop();
}
int main(void)
{
on_cpu();
on_gpu();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <hip/hip_runtime_api.h>
// function to add the elements of two arrays
void add_cpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_cpu(){
std::cout << "Running on cpu." << std::endl;
int N = 1<<20; // 1M elements
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
add_cpu(N, x, y);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
}
__global__
void add_gpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_gpu()
{
hipProfilerStart();
std::cout << "Running on gpu." << std::endl;
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add_gpu<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
hipDeviceReset();
hipProfilerStop();
}
int main(void)
{
on_cpu();
on_gpu();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <hip/hip_runtime_api.h>
// function to add the elements of two arrays
void add_cpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_cpu(){
std::cout << "Running on cpu." << std::endl;
int N = 1<<20; // 1M elements
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
add_cpu(N, x, y);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
}
__global__
void add_gpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_gpu()
{
hipProfilerStart();
std::cout << "Running on gpu." << std::endl;
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add_gpu<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
hipDeviceReset();
hipProfilerStop();
}
int main(void)
{
on_cpu();
on_gpu();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_gpuiPfS_
.globl _Z7add_gpuiPfS_
.p2align 8
.type _Z7add_gpuiPfS_,@function
_Z7add_gpuiPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_gpuiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_gpuiPfS_, .Lfunc_end0-_Z7add_gpuiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_gpuiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z7add_gpuiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <hip/hip_runtime_api.h>
// function to add the elements of two arrays
void add_cpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_cpu(){
std::cout << "Running on cpu." << std::endl;
int N = 1<<20; // 1M elements
float *x = new float[N];
float *y = new float[N];
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the CPU
add_cpu(N, x, y);
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
delete [] x;
delete [] y;
}
__global__
void add_gpu(int n, float *x, float *y)
{
for (int i = 0; i < n; i++)
y[i] = x[i] + y[i];
}
void on_gpu()
{
hipProfilerStart();
std::cout << "Running on gpu." << std::endl;
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add_gpu<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
hipDeviceReset();
hipProfilerStop();
}
int main(void)
{
on_cpu();
on_gpu();
return 0;
} | .text
.file "vectoradd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7add_cpuiPfS_ # -- Begin function _Z7add_cpuiPfS_
.p2align 4, 0x90
.type _Z7add_cpuiPfS_,@function
_Z7add_cpuiPfS_: # @_Z7add_cpuiPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7add_cpuiPfS_, .Lfunc_end0-_Z7add_cpuiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6on_cpuv
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z6on_cpuv
.p2align 4, 0x90
.type _Z6on_cpuv,@function
_Z6on_cpuv: # @_Z6on_cpuv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_7
# %bb.8: # %_Z7add_cpuiPfS_.exit.preheader
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_9: # %_Z7add_cpuiPfS_.exit
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, (%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps (%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.12:
movzbl 67(%r15), %ecx
jmp .LBB1_14
.LBB1_13:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.LBB1_15:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z6on_cpuv, .Lfunc_end1-_Z6on_cpuv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__add_gpuiPfS_ # -- Begin function _Z22__device_stub__add_gpuiPfS_
.p2align 4, 0x90
.type _Z22__device_stub__add_gpuiPfS_,@function
_Z22__device_stub__add_gpuiPfS_: # @_Z22__device_stub__add_gpuiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7add_gpuiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__add_gpuiPfS_, .Lfunc_end2-_Z22__device_stub__add_gpuiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6on_gpuv
.LCPI3_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z6on_gpuv
.p2align 4, 0x90
.type _Z6on_gpuv,@function
_Z6on_gpuv: # @_Z6on_gpuv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq hipProfilerStart
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB3_5
# %bb.6:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7add_gpuiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI3_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB3_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB3_14
.LBB3_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
callq hipProfilerStop
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z6on_gpuv, .Lfunc_end3-_Z6on_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z6on_cpuv
callq _Z6on_gpuv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_gpuiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running on cpu."
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type _Z7add_gpuiPfS_,@object # @_Z7add_gpuiPfS_
.section .rodata,"a",@progbits
.globl _Z7add_gpuiPfS_
.p2align 3, 0x0
_Z7add_gpuiPfS_:
.quad _Z22__device_stub__add_gpuiPfS_
.size _Z7add_gpuiPfS_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Running on gpu."
.size .L.str.2, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7add_gpuiPfS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_gpuiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7add_gpuiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7add_gpuiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xaa0 ; /* 0x00000a0000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fd60000000f00 */
/*0110*/ @!P0 BRA 0x8f0 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x610 ; /* 0x000004c000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0190*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*01b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*01d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*01e0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*0200*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0220*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0230*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*0240*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0260*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*0270*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0280*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0290*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0003e8000c10190a */
/*02b0*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ea8000c1e1900 */
/*02c0*/ LDG.E R7, [R4.64+0x20] ; /* 0x0000200a04077981 */
/* 0x002ee2000c1e1900 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*02e0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0001e8000c10190a */
/*0300*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0320*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0330*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0340*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0360*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x000fe8000c10190a */
/*0370*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000ee4000c1e1900 */
/*0380*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0390*/ LDG.E R8, [R4.64+0x24] ; /* 0x0000240a04087981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0003e8000c10190a */
/*03b0*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240a02097981 */
/* 0x001ea8000c1e1900 */
/*03c0*/ LDG.E R7, [R4.64+0x30] ; /* 0x0000300a04077981 */
/* 0x002ee2000c1e1900 */
/*03d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*03e0*/ LDG.E R8, [R4.64+0x28] ; /* 0x0000280a04087981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0001e8000c10190a */
/*0400*/ LDG.E R11, [R2.64+0x28] ; /* 0x0000280a020b7981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0420*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0430*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0003e8000c10190a */
/*0440*/ LDG.E R13, [R2.64+0x2c] ; /* 0x00002c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0460*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0005e8000c10190a */
/*0470*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000ee4000c1e1900 */
/*0480*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0490*/ LDG.E R8, [R4.64+0x34] ; /* 0x0000340a04087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0009e8000c10190a */
/*04b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340a02097981 */
/* 0x001ee4000c1e1900 */
/*04c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*04d0*/ LDG.E R8, [R4.64+0x38] ; /* 0x0000380a04087981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ STG.E [R4.64+0x34], R9 ; /* 0x0000340904007986 */
/* 0x000fe8000c10190a */
/*04f0*/ LDG.E R11, [R2.64+0x38] ; /* 0x0000380a020b7981 */
/* 0x002ee2000c1e1900 */
/*0500*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0510*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*0520*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0a04087981 */
/* 0x000ee8000c1e1900 */
/*0530*/ STG.E [R4.64+0x38], R11 ; /* 0x0000380b04007986 */
/* 0x000fe8000c10190a */
/*0540*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0550*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0560*/ IADD3 R7, P3, R4, 0x40, RZ ; /* 0x0000004004077810 */
/* 0x010fe20007f7e0ff */
/*0570*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0580*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*0590*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x001fe400017fe4ff */
/*05a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*05b0*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe40000000000 */
/*05c0*/ IMAD.X R8, RZ, RZ, R5, P3 ; /* 0x000000ffff087224 */
/* 0x000fc600018e0605 */
/*05d0*/ STG.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007986 */
/* 0x0001e4000c10190a */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*05f0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0600*/ @P1 BRA 0x160 ; /* 0xfffffb5000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x8d0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0650*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0660*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0670*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0680*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*06a0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*06b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*06d0*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*06f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0700*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c10190a */
/*0710*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0730*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0005e8000c10190a */
/*0740*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0750*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0760*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ee8000c1e1900 */
/*0770*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0009e8000c10190a */
/*0780*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ee4000c1e1900 */
/*0790*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*07a0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c10190a */
/*07c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x002ee4000c1e1900 */
/*07d0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*07e0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0800*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0810*/ IADD3 R7, P2, R4, 0x20, RZ ; /* 0x0000002004077810 */
/* 0x010fe40007f5e0ff */
/*0820*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc40007f3e0ff */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0840*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0850*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0870*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0880*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe20000000000 */
/*0890*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*08a0*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0001e4000c10190a */
/*08b0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x001fe20000000f00 */
/*08c0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0008 */
/*08d0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0xaa0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0910*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0920*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0930*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0940*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*0960*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*0970*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*0980*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*09b0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*09d0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x0002a2000c1e1900 */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*09f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0a00*/ IADD3 R7, P2, R4, 0x10, RZ ; /* 0x0000001004077810 */
/* 0x001fc40007f5e0ff */
/*0a10*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc80007f3e0ff */
/*0a20*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*0a30*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0a40*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fe40000000000 */
/*0a50*/ IMAD.X R8, RZ, RZ, R5, P2 ; /* 0x000000ffff087224 */
/* 0x000fc600010e0605 */
/*0a60*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e4000c10190a */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*0a80*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0a90*/ @P0 BRA 0x8f0 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ab0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ac0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0ad0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0ae0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0af0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0b00*/ UIMAD.WIDE UR4, UR4, UR5, UR8 ; /* 0x00000005040472a5 */
/* 0x000fe4000f8e0208 */
/*0b10*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe2000f8e00ff */
/*0b20*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe20008000f00 */
/*0b30*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b40*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0b60*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fc40000000f00 */
/*0b70*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0b80*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b90*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x001fe20000000f00 */
/*0ba0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0006 */
/*0bb0*/ LDG.E R5, [R4.64] ; /* 0x0000000a04057981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0bf0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0c00*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0c10*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fe20000000000 */
/*0c20*/ IADD3 R6, P1, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007f3e0ff */
/*0c30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c10190a */
/*0c40*/ IADD3.X R9, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff097210 */
/* 0x000fe20000ffe4ff */
/*0c50*/ @P0 BRA 0xb70 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0c60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7add_gpuiPfS_
.globl _Z7add_gpuiPfS_
.p2align 8
.type _Z7add_gpuiPfS_,@function
_Z7add_gpuiPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7add_gpuiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7add_gpuiPfS_, .Lfunc_end0-_Z7add_gpuiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7add_gpuiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z7add_gpuiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193d1d_00000000-6_vectoradd.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7add_cpuiPfS_
.type _Z7add_cpuiPfS_, @function
_Z7add_cpuiPfS_:
.LFB3669:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movss (%rdx,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z7add_cpuiPfS_, .-_Z7add_cpuiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Running on cpu."
.LC6:
.string "Max error: "
.text
.globl _Z6on_cpuv
.type _Z6on_cpuv, @function
_Z6on_cpuv:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl $15, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L19
cmpb $0, 56(%rbx)
je .L9
movzbl 67(%rbx), %eax
.L10:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L11:
movss %xmm1, (%r12,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L11
movq %rbp, %rdx
movq %r12, %rsi
movl $1048576, %edi
call _Z7add_cpuiPfS_
movq %rbp, %rbx
leaq 4194304(%rbp), %r13
movl $0x00000000, 12(%rsp)
.L12:
movss (%rbx), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %r13
jne .L12
movl $11, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L20
cmpb $0, 56(%r13)
je .L14
movzbl 67(%r13), %eax
.L15:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L9:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L10
.L20:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L15
.cfi_endproc
.LFE3670:
.size _Z6on_cpuv, .-_Z6on_cpuv
.globl _Z29__device_stub__Z7add_gpuiPfS_iPfS_
.type _Z29__device_stub__Z7add_gpuiPfS_iPfS_, @function
_Z29__device_stub__Z7add_gpuiPfS_iPfS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7add_gpuiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z29__device_stub__Z7add_gpuiPfS_iPfS_, .-_Z29__device_stub__Z7add_gpuiPfS_iPfS_
.globl _Z7add_gpuiPfS_
.type _Z7add_gpuiPfS_, @function
_Z7add_gpuiPfS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7add_gpuiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7add_gpuiPfS_, .-_Z7add_gpuiPfS_
.section .rodata.str1.1
.LC7:
.string "Running on gpu."
.text
.globl _Z6on_gpuv
.type _Z6on_gpuv, @function
_Z6on_gpuv:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call cudaProfilerStart@PLT
movl $15, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L45
cmpb $0, 56(%rbx)
je .L32
movzbl 67(%rbx), %eax
.L33:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L34:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L34
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L35:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L36:
movss (%rbx), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L36
movl $11, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L47
cmpb $0, 56(%rbp)
je .L39
movzbl 67(%rbp), %eax
.L40:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
call cudaProfilerStop@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L32:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L33
.L46:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z29__device_stub__Z7add_gpuiPfS_iPfS_
jmp .L35
.L47:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L50
call _ZSt16__throw_bad_castv@PLT
.L50:
call __stack_chk_fail@PLT
.L39:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L40
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z6on_gpuv, .-_Z6on_gpuv
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z6on_cpuv
call _Z6on_gpuv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z7add_gpuiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z7add_gpuiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectoradd.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z7add_cpuiPfS_ # -- Begin function _Z7add_cpuiPfS_
.p2align 4, 0x90
.type _Z7add_cpuiPfS_,@function
_Z7add_cpuiPfS_: # @_Z7add_cpuiPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rdx,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z7add_cpuiPfS_, .Lfunc_end0-_Z7add_cpuiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6on_cpuv
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z6on_cpuv
.p2align 4, 0x90
.type _Z6on_cpuv,@function
_Z6on_cpuv: # @_Z6on_cpuv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_7
# %bb.8: # %_Z7add_cpuiPfS_.exit.preheader
xorps %xmm2, %xmm2
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_9: # %_Z7add_cpuiPfS_.exit
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, (%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps (%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.12:
movzbl 67(%r15), %ecx
jmp .LBB1_14
.LBB1_13:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit26
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.LBB1_15:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z6on_cpuv, .Lfunc_end1-_Z6on_cpuv
.cfi_endproc
# -- End function
.globl _Z22__device_stub__add_gpuiPfS_ # -- Begin function _Z22__device_stub__add_gpuiPfS_
.p2align 4, 0x90
.type _Z22__device_stub__add_gpuiPfS_,@function
_Z22__device_stub__add_gpuiPfS_: # @_Z22__device_stub__add_gpuiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7add_gpuiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__add_gpuiPfS_, .Lfunc_end2-_Z22__device_stub__add_gpuiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6on_gpuv
.LCPI3_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl _Z6on_gpuv
.p2align 4, 0x90
.type _Z6on_gpuv,@function
_Z6on_gpuv: # @_Z6on_gpuv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq hipProfilerStart
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_15
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB3_4
.LBB3_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB3_5
# %bb.6:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7add_gpuiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_8:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI3_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB3_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
je .LBB3_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB3_14
.LBB3_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit21
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq hipDeviceReset
callq hipProfilerStop
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_15:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z6on_gpuv, .Lfunc_end3-_Z6on_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z6on_cpuv
callq _Z6on_gpuv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7add_gpuiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Running on cpu."
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: "
.size .L.str.1, 12
.type _Z7add_gpuiPfS_,@object # @_Z7add_gpuiPfS_
.section .rodata,"a",@progbits
.globl _Z7add_gpuiPfS_
.p2align 3, 0x0
_Z7add_gpuiPfS_:
.quad _Z22__device_stub__add_gpuiPfS_
.size _Z7add_gpuiPfS_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Running on gpu."
.size .L.str.2, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7add_gpuiPfS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__add_gpuiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7add_gpuiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void exclusivePrefixAdd(unsigned int* d_in, unsigned int* d_out)
{
//Belloch implementation
//NOTE: this is set up specifically for 1 block of 1024 threads
int thread_x = threadIdx.x;
d_out[thread_x] = d_in[thread_x];
__syncthreads();
//first, do the reduce:
for (unsigned int i = 2; i <= blockDim.x; i <<= 1)
{
if ((thread_x + 1) % i == 0)
{
d_out[thread_x] = d_out[thread_x] + d_out[thread_x - i / 2];
}
__syncthreads();
}
//now do the downsweep part:
if (thread_x == blockDim.x - 1)
{
d_out[thread_x] = 0;
}
//maybe need a syncthreads() here because of that write above? it's only 1 thread so idk if it affects it
for (unsigned int i = blockDim.x; i >= 2; i >>= 1)
{
if ((thread_x + 1) % i == 0)
{
unsigned int temp = d_out[thread_x - (i / 2)];
//the "left" copy
d_out[thread_x - (i / 2)] = d_out[thread_x];
//and the "right" operation
d_out[thread_x] = temp + d_out[thread_x];
}
__syncthreads();
}
} | code for sm_80
Function : _Z18exclusivePrefixAddPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R6, R0, R3, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x001fcc00078e0203 */
/*0050*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0203 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f06070 */
/*0090*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101906 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*00b0*/ @!P0 BRA 0x2f0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R8, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff087435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fd00007ffe0ff */
/*00e0*/ I2F.U32.RP R9, R8 ; /* 0x0000000800097306 */
/* 0x001e620000209000 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45070 */
/*0100*/ BSSY B0, 0x2b0 ; /* 0x000001a000007945 */
/* 0x000fec0003800000 */
/*0110*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e640000001000 */
/*0120*/ IADD3 R6, R9, 0xffffffe, RZ ; /* 0x0ffffffe09067810 */
/* 0x002fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x001064000021f000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0160*/ IMAD R11, R11, R8, RZ ; /* 0x000000080b0b7224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fcc00078e0006 */
/*0180*/ IMAD.HI.U32 R10, R10, R5, RZ ; /* 0x000000050a0a7227 */
/* 0x000fca00078e00ff */
/*0190*/ IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0a7210 */
/* 0x000fca0007ffe1ff */
/*01a0*/ IMAD R7, R8, R10, R5 ; /* 0x0000000a08077224 */
/* 0x000fca00078e0205 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IMAD.IADD R7, R7, 0x1, -R8 ; /* 0x0000000107071824 */
/* 0x000fca00078e0a08 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IMAD.IADD R7, R7, 0x1, -R8 ; /* 0x0000000107071824 */
/* 0x000fe200078e0a08 */
/*01f0*/ @!P2 LOP3.LUT R7, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff07a212 */
/* 0x000fc800078e33ff */
/*0200*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f25270 */
/*0210*/ @P1 BRA 0x2a0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R7, RZ, 0x1, R8 ; /* 0x00000001ff077819 */
/* 0x000fe20000011608 */
/*0230*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fc800078e0a07 */
/*0260*/ IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0006 */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.IADD R9, R9, 0x1, R6 ; /* 0x0000000109097824 */
/* 0x004fca00078e0206 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101906 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fe200000006ff */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f24070 */
/*02e0*/ @!P1 BRA 0xe0 ; /* 0xfffffdf000009947 */
/* 0x000fea000383ffff */
/*02f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0300*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0310*/ ISETP.NE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf25270 */
/*0320*/ @!P1 STG.E [R2.64], RZ ; /* 0x000000ff02009986 */
/* 0x0003e2000c101906 */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R10, R0, 0x1, RZ ; /* 0x00000001000a7810 */
/* 0x000fe40007ffe0ff */
/*0350*/ I2F.U32.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x001ea20000209000 */
/*0360*/ ISETP.NE.U32.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25070 */
/*0370*/ BSSY B0, 0x540 ; /* 0x000001c000007945 */
/* 0x000fec0003800000 */
/*0380*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x004ea40000001000 */
/*0390*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x004fcc0007ffe0ff */
/*03a0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0010a4000021f000 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*03c0*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x004fc800078e0a07 */
/*03d0*/ IMAD R9, R9, R4, RZ ; /* 0x0000000409097224 */
/* 0x000fc800078e02ff */
/*03e0*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*03f0*/ IMAD.HI.U32 R7, R7, R10, RZ ; /* 0x0000000a07077227 */
/* 0x000fca00078e00ff */
/*0400*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fca0007ffe1ff */
/*0410*/ IMAD R7, R4, R7, R10 ; /* 0x0000000704077224 */
/* 0x000fca00078e020a */
/*0420*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06070 */
/*0430*/ @P0 IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107070824 */
/* 0x000fca00078e0a04 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06070 */
/*0450*/ @P0 IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a04 */
/*0460*/ @!P1 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff079212 */
/* 0x000fc800078e33ff */
/*0470*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0480*/ @P0 BRA 0x530 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*04b0*/ SHF.R.U32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fca0000011604 */
/*04c0*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0a05 */
/*04d0*/ IMAD.WIDE.U32 R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fca00078e0006 */
/*04e0*/ LDG.E R5, [R6.64] ; /* 0x0000000606057981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0041e8000c101906 */
/*0500*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ee4000c1e1900 */
/*0510*/ IADD3 R5, R5, R8, RZ ; /* 0x0000000805057210 */
/* 0x008fca0007ffe0ff */
/*0520*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101906 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0550*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f04070 */
/*0560*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fd60000011604 */
/*0570*/ @P0 BRA 0x350 ; /* 0xfffffdd000000947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void exclusivePrefixAdd(unsigned int* d_in, unsigned int* d_out)
{
//Belloch implementation
//NOTE: this is set up specifically for 1 block of 1024 threads
int thread_x = threadIdx.x;
d_out[thread_x] = d_in[thread_x];
__syncthreads();
//first, do the reduce:
for (unsigned int i = 2; i <= blockDim.x; i <<= 1)
{
if ((thread_x + 1) % i == 0)
{
d_out[thread_x] = d_out[thread_x] + d_out[thread_x - i / 2];
}
__syncthreads();
}
//now do the downsweep part:
if (thread_x == blockDim.x - 1)
{
d_out[thread_x] = 0;
}
//maybe need a syncthreads() here because of that write above? it's only 1 thread so idk if it affects it
for (unsigned int i = blockDim.x; i >= 2; i >>= 1)
{
if ((thread_x + 1) % i == 0)
{
unsigned int temp = d_out[thread_x - (i / 2)];
//the "left" copy
d_out[thread_x - (i / 2)] = d_out[thread_x];
//and the "right" operation
d_out[thread_x] = temp + d_out[thread_x];
}
__syncthreads();
}
} | .file "tmpxft_0000f73f_00000000-6_exclusivePrefixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_
.type _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_, @function
_Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18exclusivePrefixAddPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_, .-_Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_
.globl _Z18exclusivePrefixAddPjS_
.type _Z18exclusivePrefixAddPjS_, @function
_Z18exclusivePrefixAddPjS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18exclusivePrefixAddPjS_, .-_Z18exclusivePrefixAddPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18exclusivePrefixAddPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18exclusivePrefixAddPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void exclusivePrefixAdd(unsigned int* d_in, unsigned int* d_out)
{
//Belloch implementation
//NOTE: this is set up specifically for 1 block of 1024 threads
int thread_x = threadIdx.x;
d_out[thread_x] = d_in[thread_x];
__syncthreads();
//first, do the reduce:
for (unsigned int i = 2; i <= blockDim.x; i <<= 1)
{
if ((thread_x + 1) % i == 0)
{
d_out[thread_x] = d_out[thread_x] + d_out[thread_x - i / 2];
}
__syncthreads();
}
//now do the downsweep part:
if (thread_x == blockDim.x - 1)
{
d_out[thread_x] = 0;
}
//maybe need a syncthreads() here because of that write above? it's only 1 thread so idk if it affects it
for (unsigned int i = blockDim.x; i >= 2; i >>= 1)
{
if ((thread_x + 1) % i == 0)
{
unsigned int temp = d_out[thread_x - (i / 2)];
//the "left" copy
d_out[thread_x - (i / 2)] = d_out[thread_x];
//and the "right" operation
d_out[thread_x] = temp + d_out[thread_x];
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void exclusivePrefixAdd(unsigned int* d_in, unsigned int* d_out)
{
//Belloch implementation
//NOTE: this is set up specifically for 1 block of 1024 threads
int thread_x = threadIdx.x;
d_out[thread_x] = d_in[thread_x];
__syncthreads();
//first, do the reduce:
for (unsigned int i = 2; i <= blockDim.x; i <<= 1)
{
if ((thread_x + 1) % i == 0)
{
d_out[thread_x] = d_out[thread_x] + d_out[thread_x - i / 2];
}
__syncthreads();
}
//now do the downsweep part:
if (thread_x == blockDim.x - 1)
{
d_out[thread_x] = 0;
}
//maybe need a syncthreads() here because of that write above? it's only 1 thread so idk if it affects it
for (unsigned int i = blockDim.x; i >= 2; i >>= 1)
{
if ((thread_x + 1) % i == 0)
{
unsigned int temp = d_out[thread_x - (i / 2)];
//the "left" copy
d_out[thread_x - (i / 2)] = d_out[thread_x];
//and the "right" operation
d_out[thread_x] = temp + d_out[thread_x];
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void exclusivePrefixAdd(unsigned int* d_in, unsigned int* d_out)
{
//Belloch implementation
//NOTE: this is set up specifically for 1 block of 1024 threads
int thread_x = threadIdx.x;
d_out[thread_x] = d_in[thread_x];
__syncthreads();
//first, do the reduce:
for (unsigned int i = 2; i <= blockDim.x; i <<= 1)
{
if ((thread_x + 1) % i == 0)
{
d_out[thread_x] = d_out[thread_x] + d_out[thread_x - i / 2];
}
__syncthreads();
}
//now do the downsweep part:
if (thread_x == blockDim.x - 1)
{
d_out[thread_x] = 0;
}
//maybe need a syncthreads() here because of that write above? it's only 1 thread so idk if it affects it
for (unsigned int i = blockDim.x; i >= 2; i >>= 1)
{
if ((thread_x + 1) % i == 0)
{
unsigned int temp = d_out[thread_x - (i / 2)];
//the "left" copy
d_out[thread_x - (i / 2)] = d_out[thread_x];
//and the "right" operation
d_out[thread_x] = temp + d_out[thread_x];
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18exclusivePrefixAddPjS_
.globl _Z18exclusivePrefixAddPjS_
.p2align 8
.type _Z18exclusivePrefixAddPjS_,@function
_Z18exclusivePrefixAddPjS_:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_load_b32 s0, s[0:1], 0x1c
s_mov_b32 s1, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v3, s[4:5]
v_add_co_u32 v1, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, null, s7, 0, s2
s_and_b32 s0, s0, 0xffff
s_cmp_lt_u32 s0, 2
s_waitcnt vmcnt(0)
global_store_b32 v3, v5, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
v_add_nc_u32_e32 v5, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s1, s1, 1
s_waitcnt_vscnt null, 0x0
s_cmp_gt_u32 s1, s0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_add_i32 s2, s1, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_b32_e32 v3, s2, v5
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_2
s_lshr_b32 s3, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s3, v0
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_clause 0x1
global_load_b32 v3, v[1:2], off
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v6, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_add_i32 s1, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s1, v0
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v3, 0
global_store_b32 v[1:2], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_u32 s0, 2
s_cbranch_scc1 .LBB0_12
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_u32_e32 v6, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_lt_u32 s0, 4
s_mov_b32 s0, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
.LBB0_10:
v_cvt_f32_u32_e32 v3, s0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v7, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, v6, v7
v_trunc_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v7, v3, v6
v_cvt_u32_f32_e32 v7, v7
v_cmp_ge_f32_e64 vcc_lo, |v8|, |v3|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v5, v3
v_and_b32_e32 v3, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_9
global_load_b32 v9, v[1:2], off
s_lshr_b32 s2, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s2, v0
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v3, v[7:8], off
s_waitcnt vmcnt(1)
global_store_b32 v[7:8], v9, off
global_load_b32 v7, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v7, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18exclusivePrefixAddPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18exclusivePrefixAddPjS_, .Lfunc_end0-_Z18exclusivePrefixAddPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18exclusivePrefixAddPjS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z18exclusivePrefixAddPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void exclusivePrefixAdd(unsigned int* d_in, unsigned int* d_out)
{
//Belloch implementation
//NOTE: this is set up specifically for 1 block of 1024 threads
int thread_x = threadIdx.x;
d_out[thread_x] = d_in[thread_x];
__syncthreads();
//first, do the reduce:
for (unsigned int i = 2; i <= blockDim.x; i <<= 1)
{
if ((thread_x + 1) % i == 0)
{
d_out[thread_x] = d_out[thread_x] + d_out[thread_x - i / 2];
}
__syncthreads();
}
//now do the downsweep part:
if (thread_x == blockDim.x - 1)
{
d_out[thread_x] = 0;
}
//maybe need a syncthreads() here because of that write above? it's only 1 thread so idk if it affects it
for (unsigned int i = blockDim.x; i >= 2; i >>= 1)
{
if ((thread_x + 1) % i == 0)
{
unsigned int temp = d_out[thread_x - (i / 2)];
//the "left" copy
d_out[thread_x - (i / 2)] = d_out[thread_x];
//and the "right" operation
d_out[thread_x] = temp + d_out[thread_x];
}
__syncthreads();
}
} | .text
.file "exclusivePrefixAdd.hip"
.globl _Z33__device_stub__exclusivePrefixAddPjS_ # -- Begin function _Z33__device_stub__exclusivePrefixAddPjS_
.p2align 4, 0x90
.type _Z33__device_stub__exclusivePrefixAddPjS_,@function
_Z33__device_stub__exclusivePrefixAddPjS_: # @_Z33__device_stub__exclusivePrefixAddPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18exclusivePrefixAddPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__exclusivePrefixAddPjS_, .Lfunc_end0-_Z33__device_stub__exclusivePrefixAddPjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18exclusivePrefixAddPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18exclusivePrefixAddPjS_,@object # @_Z18exclusivePrefixAddPjS_
.section .rodata,"a",@progbits
.globl _Z18exclusivePrefixAddPjS_
.p2align 3, 0x0
_Z18exclusivePrefixAddPjS_:
.quad _Z33__device_stub__exclusivePrefixAddPjS_
.size _Z18exclusivePrefixAddPjS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18exclusivePrefixAddPjS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__exclusivePrefixAddPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18exclusivePrefixAddPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18exclusivePrefixAddPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R6, R0, R3, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x001fcc00078e0203 */
/*0050*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe400078e00ff */
/*0070*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0203 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fe40003f06070 */
/*0090*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0041e8000c101906 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fee0000010000 */
/*00b0*/ @!P0 BRA 0x2f0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R8, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff087435 */
/* 0x000fe200000001ff */
/*00d0*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fd00007ffe0ff */
/*00e0*/ I2F.U32.RP R9, R8 ; /* 0x0000000800097306 */
/* 0x001e620000209000 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45070 */
/*0100*/ BSSY B0, 0x2b0 ; /* 0x000001a000007945 */
/* 0x000fec0003800000 */
/*0110*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x002e640000001000 */
/*0120*/ IADD3 R6, R9, 0xffffffe, RZ ; /* 0x0ffffffe09067810 */
/* 0x002fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x001064000021f000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0160*/ IMAD R11, R11, R8, RZ ; /* 0x000000080b0b7224 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R10, R7, R11, R6 ; /* 0x0000000b070a7227 */
/* 0x000fcc00078e0006 */
/*0180*/ IMAD.HI.U32 R10, R10, R5, RZ ; /* 0x000000050a0a7227 */
/* 0x000fca00078e00ff */
/*0190*/ IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0a7210 */
/* 0x000fca0007ffe1ff */
/*01a0*/ IMAD R7, R8, R10, R5 ; /* 0x0000000a08077224 */
/* 0x000fca00078e0205 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IMAD.IADD R7, R7, 0x1, -R8 ; /* 0x0000000107071824 */
/* 0x000fca00078e0a08 */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IMAD.IADD R7, R7, 0x1, -R8 ; /* 0x0000000107071824 */
/* 0x000fe200078e0a08 */
/*01f0*/ @!P2 LOP3.LUT R7, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff07a212 */
/* 0x000fc800078e33ff */
/*0200*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f25270 */
/*0210*/ @P1 BRA 0x2a0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0220*/ SHF.R.U32.HI R7, RZ, 0x1, R8 ; /* 0x00000001ff077819 */
/* 0x000fe20000011608 */
/*0230*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.IADD R7, R0, 0x1, -R7 ; /* 0x0000000100077824 */
/* 0x000fc800078e0a07 */
/*0260*/ IMAD.WIDE.U32 R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0006 */
/*0270*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea4000c1e1900 */
/*0280*/ IMAD.IADD R9, R9, 0x1, R6 ; /* 0x0000000109097824 */
/* 0x004fca00078e0206 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101906 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fe200000006ff */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*02d0*/ ISETP.GT.U32.AND P1, PT, R8, c[0x0][0x0], PT ; /* 0x0000000008007a0c */
/* 0x000fda0003f24070 */
/*02e0*/ @!P1 BRA 0xe0 ; /* 0xfffffdf000009947 */
/* 0x000fea000383ffff */
/*02f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0300*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0310*/ ISETP.NE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf25270 */
/*0320*/ @!P1 STG.E [R2.64], RZ ; /* 0x000000ff02009986 */
/* 0x0003e2000c101906 */
/*0330*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R10, R0, 0x1, RZ ; /* 0x00000001000a7810 */
/* 0x000fe40007ffe0ff */
/*0350*/ I2F.U32.RP R5, R4 ; /* 0x0000000400057306 */
/* 0x001ea20000209000 */
/*0360*/ ISETP.NE.U32.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25070 */
/*0370*/ BSSY B0, 0x540 ; /* 0x000001c000007945 */
/* 0x000fec0003800000 */
/*0380*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x004ea40000001000 */
/*0390*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x004fcc0007ffe0ff */
/*03a0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0010a4000021f000 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*03c0*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x004fc800078e0a07 */
/*03d0*/ IMAD R9, R9, R4, RZ ; /* 0x0000000409097224 */
/* 0x000fc800078e02ff */
/*03e0*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*03f0*/ IMAD.HI.U32 R7, R7, R10, RZ ; /* 0x0000000a07077227 */
/* 0x000fca00078e00ff */
/*0400*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fca0007ffe1ff */
/*0410*/ IMAD R7, R4, R7, R10 ; /* 0x0000000704077224 */
/* 0x000fca00078e020a */
/*0420*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06070 */
/*0430*/ @P0 IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107070824 */
/* 0x000fca00078e0a04 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f06070 */
/*0450*/ @P0 IMAD.IADD R7, R7, 0x1, -R4 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a04 */
/*0460*/ @!P1 LOP3.LUT R7, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff079212 */
/* 0x000fc800078e33ff */
/*0470*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0480*/ @P0 BRA 0x530 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0490*/ LDG.E R9, [R2.64] ; /* 0x0000000602097981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*04b0*/ SHF.R.U32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fca0000011604 */
/*04c0*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0a05 */
/*04d0*/ IMAD.WIDE.U32 R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fca00078e0006 */
/*04e0*/ LDG.E R5, [R6.64] ; /* 0x0000000606057981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0041e8000c101906 */
/*0500*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ee4000c1e1900 */
/*0510*/ IADD3 R5, R5, R8, RZ ; /* 0x0000000805057210 */
/* 0x008fca0007ffe0ff */
/*0520*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101906 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0550*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f04070 */
/*0560*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fd60000011604 */
/*0570*/ @P0 BRA 0x350 ; /* 0xfffffdd000000947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18exclusivePrefixAddPjS_
.globl _Z18exclusivePrefixAddPjS_
.p2align 8
.type _Z18exclusivePrefixAddPjS_,@function
_Z18exclusivePrefixAddPjS_:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v3, 2, v0
s_load_b32 s0, s[0:1], 0x1c
s_mov_b32 s1, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v3, s[4:5]
v_add_co_u32 v1, s2, s6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v2, null, s7, 0, s2
s_and_b32 s0, s0, 0xffff
s_cmp_lt_u32 s0, 2
s_waitcnt vmcnt(0)
global_store_b32 v3, v5, s[6:7]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
v_add_nc_u32_e32 v5, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_lshl_b32 s1, s1, 1
s_waitcnt_vscnt null, 0x0
s_cmp_gt_u32 s1, s0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_add_i32 s2, s1, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_b32_e32 v3, s2, v5
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_2
s_lshr_b32 s3, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s3, v0
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_clause 0x1
global_load_b32 v3, v[1:2], off
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v6, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_add_i32 s1, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s1, v0
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v3, 0
global_store_b32 v[1:2], v3, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_lt_u32 s0, 2
s_cbranch_scc1 .LBB0_12
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_u32_e32 v6, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_lt_u32 s0, 4
s_mov_b32 s0, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
.LBB0_10:
v_cvt_f32_u32_e32 v3, s0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v7, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, v6, v7
v_trunc_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v8, -v7, v3, v6
v_cvt_u32_f32_e32 v7, v7
v_cmp_ge_f32_e64 vcc_lo, |v8|, |v3|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v5, v3
v_and_b32_e32 v3, 0xffff, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_9
global_load_b32 v9, v[1:2], off
s_lshr_b32 s2, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s2, v0
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v3, v[7:8], off
s_waitcnt vmcnt(1)
global_store_b32 v[7:8], v9, off
global_load_b32 v7, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v7, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18exclusivePrefixAddPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18exclusivePrefixAddPjS_, .Lfunc_end0-_Z18exclusivePrefixAddPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18exclusivePrefixAddPjS_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z18exclusivePrefixAddPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000f73f_00000000-6_exclusivePrefixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_
.type _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_, @function
_Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18exclusivePrefixAddPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_, .-_Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_
.globl _Z18exclusivePrefixAddPjS_
.type _Z18exclusivePrefixAddPjS_, @function
_Z18exclusivePrefixAddPjS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18exclusivePrefixAddPjS_PjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18exclusivePrefixAddPjS_, .-_Z18exclusivePrefixAddPjS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18exclusivePrefixAddPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18exclusivePrefixAddPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exclusivePrefixAdd.hip"
.globl _Z33__device_stub__exclusivePrefixAddPjS_ # -- Begin function _Z33__device_stub__exclusivePrefixAddPjS_
.p2align 4, 0x90
.type _Z33__device_stub__exclusivePrefixAddPjS_,@function
_Z33__device_stub__exclusivePrefixAddPjS_: # @_Z33__device_stub__exclusivePrefixAddPjS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18exclusivePrefixAddPjS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z33__device_stub__exclusivePrefixAddPjS_, .Lfunc_end0-_Z33__device_stub__exclusivePrefixAddPjS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18exclusivePrefixAddPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18exclusivePrefixAddPjS_,@object # @_Z18exclusivePrefixAddPjS_
.section .rodata,"a",@progbits
.globl _Z18exclusivePrefixAddPjS_
.p2align 3, 0x0
_Z18exclusivePrefixAddPjS_:
.quad _Z33__device_stub__exclusivePrefixAddPjS_
.size _Z18exclusivePrefixAddPjS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18exclusivePrefixAddPjS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__exclusivePrefixAddPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18exclusivePrefixAddPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ unsigned int mulhilo32(
unsigned int a,
unsigned int b,
unsigned int* result_high) {
*result_high = __umulhi(a, b);
return a * b;
}
__device__ uint4 single_round(uint4 ctr, uint2 key) {
constexpr unsigned long kPhiloxSA = 0xD2511F53;
constexpr unsigned long kPhiloxSB = 0xCD9E8D57;
unsigned int hi0;
unsigned int hi1;
unsigned int lo0 = mulhilo32(kPhiloxSA, ctr.x, &hi0);
unsigned int lo1 = mulhilo32(kPhiloxSB, ctr.z, &hi1);
uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0};
return ret;
}
__device__ uint4 philox(
unsigned long long seed,
unsigned long long subsequence,
unsigned long long offset) {
constexpr unsigned long kPhilox10A = 0x9E3779B9;
constexpr unsigned long kPhilox10B = 0xBB67AE85;
uint2 key = {};
key.x = (unsigned int)seed;
key.y = (unsigned int)(seed >> 32);
uint4 counter = make_uint4(0, 0, 0, 0);
counter.x = (unsigned int)(offset);
counter.y = (unsigned int)(offset >> 32);
counter.z = (unsigned int)(subsequence);
counter.w = (unsigned int)(subsequence >> 32);
uint4 output = {};
uint2 key_ = key;
uint4 counter_ = counter;
for (int i = 0; i < 9; i++) {
counter_ = single_round(counter_, key_);
key_.x += (kPhilox10A);
key_.y += (kPhilox10B);
}
output = single_round(counter_, key_);
return output;
}
__device__ float uniformf(unsigned int x) {
constexpr float kRanInvM32 = 2.3283064e-10f; // Inverse of 2^32.
float result = x * kRanInvM32 + kRanInvM32 / 2.0f;
return result == 1 ? 0.0f : result;
}
__device__ double uniform(unsigned int x, unsigned int y) {
constexpr double kRan2Pow53Inv = 1.1102230246251565e-16;
const unsigned long long z =
(unsigned long long)x ^ ((unsigned long long)y << (53 - 32));
double result = z * kRan2Pow53Inv + (kRan2Pow53Inv / 2.0);
return result == 1 ? 0.0 : result;
}
__device__ double rng_uniform(const uint4& rng_result, int rng_component) {
return uniform(
(&rng_result.x)[rng_component * 2],
(&rng_result.x)[rng_component * 2 + 1]);
}
__device__ float rng_uniformf(const uint4& rng_result, int rng_component) {
return uniformf((&rng_result.x)[rng_component]);
}
__device__ double rng_uniform_range(
const uint4& rng_result,
int rng_component,
double from,
double to) {
auto range = to - from;
auto uniform01 = rng_uniform(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float rng_uniform_rangef(
const uint4& rng_result,
int rng_component,
float from,
float to) {
auto range = to - from;
auto uniform01 = rng_uniformf(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float normalf(unsigned int x, unsigned int y, int rng_component) {
float u = uniformf(x);
float v = uniformf(y) * 6.2831855f;
if (rng_component % 2 == 0) {
return sqrtf(-2.0f * logf(u)) * sinf(v);
} else {
return sqrtf(-2.0f * logf(u)) * cosf(v);
}
}
__device__ double normal(
unsigned int x0,
unsigned int x1,
unsigned int y0,
unsigned int y1,
int rng_component) {
double u = uniform(x0, x1);
double v = uniform(y0, y1) * 6.2831853071795860;
if (rng_component % 2 == 0) {
return sqrt(-2.0 * log(u)) * sin(v);
} else {
return sqrt(-2.0 * log(u)) * cos(v);
}
}
__device__ double rng_normal_standard(
const uint4& rng_result,
int rng_component) {
return normal(
rng_result.x, rng_result.y, rng_result.z, rng_result.w, rng_component);
}
__device__ float rng_normal_standardf(
const uint4& rng_result,
int rng_component) {
return normalf(
(&rng_result.x)[rng_component / 2 * 2],
(&rng_result.y)[rng_component / 2 * 2],
rng_component);
}
__device__ double rng_normal_general(
const uint4& rng_result,
int rng_component,
double mean,
double std) {
auto normal01 = rng_normal_standard(rng_result, rng_component);
return normal01 * std + mean;
}
__device__ float rng_normal_generalf(
const uint4& rng_result,
int rng_component,
float mean,
float std) {
auto normal01 = rng_normal_standardf(rng_result, rng_component);
return normal01 * std + mean;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ unsigned int mulhilo32(
unsigned int a,
unsigned int b,
unsigned int* result_high) {
*result_high = __umulhi(a, b);
return a * b;
}
__device__ uint4 single_round(uint4 ctr, uint2 key) {
constexpr unsigned long kPhiloxSA = 0xD2511F53;
constexpr unsigned long kPhiloxSB = 0xCD9E8D57;
unsigned int hi0;
unsigned int hi1;
unsigned int lo0 = mulhilo32(kPhiloxSA, ctr.x, &hi0);
unsigned int lo1 = mulhilo32(kPhiloxSB, ctr.z, &hi1);
uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0};
return ret;
}
__device__ uint4 philox(
unsigned long long seed,
unsigned long long subsequence,
unsigned long long offset) {
constexpr unsigned long kPhilox10A = 0x9E3779B9;
constexpr unsigned long kPhilox10B = 0xBB67AE85;
uint2 key = {};
key.x = (unsigned int)seed;
key.y = (unsigned int)(seed >> 32);
uint4 counter = make_uint4(0, 0, 0, 0);
counter.x = (unsigned int)(offset);
counter.y = (unsigned int)(offset >> 32);
counter.z = (unsigned int)(subsequence);
counter.w = (unsigned int)(subsequence >> 32);
uint4 output = {};
uint2 key_ = key;
uint4 counter_ = counter;
for (int i = 0; i < 9; i++) {
counter_ = single_round(counter_, key_);
key_.x += (kPhilox10A);
key_.y += (kPhilox10B);
}
output = single_round(counter_, key_);
return output;
}
__device__ float uniformf(unsigned int x) {
constexpr float kRanInvM32 = 2.3283064e-10f; // Inverse of 2^32.
float result = x * kRanInvM32 + kRanInvM32 / 2.0f;
return result == 1 ? 0.0f : result;
}
__device__ double uniform(unsigned int x, unsigned int y) {
constexpr double kRan2Pow53Inv = 1.1102230246251565e-16;
const unsigned long long z =
(unsigned long long)x ^ ((unsigned long long)y << (53 - 32));
double result = z * kRan2Pow53Inv + (kRan2Pow53Inv / 2.0);
return result == 1 ? 0.0 : result;
}
__device__ double rng_uniform(const uint4& rng_result, int rng_component) {
return uniform(
(&rng_result.x)[rng_component * 2],
(&rng_result.x)[rng_component * 2 + 1]);
}
__device__ float rng_uniformf(const uint4& rng_result, int rng_component) {
return uniformf((&rng_result.x)[rng_component]);
}
__device__ double rng_uniform_range(
const uint4& rng_result,
int rng_component,
double from,
double to) {
auto range = to - from;
auto uniform01 = rng_uniform(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float rng_uniform_rangef(
const uint4& rng_result,
int rng_component,
float from,
float to) {
auto range = to - from;
auto uniform01 = rng_uniformf(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float normalf(unsigned int x, unsigned int y, int rng_component) {
float u = uniformf(x);
float v = uniformf(y) * 6.2831855f;
if (rng_component % 2 == 0) {
return sqrtf(-2.0f * logf(u)) * sinf(v);
} else {
return sqrtf(-2.0f * logf(u)) * cosf(v);
}
}
__device__ double normal(
unsigned int x0,
unsigned int x1,
unsigned int y0,
unsigned int y1,
int rng_component) {
double u = uniform(x0, x1);
double v = uniform(y0, y1) * 6.2831853071795860;
if (rng_component % 2 == 0) {
return sqrt(-2.0 * log(u)) * sin(v);
} else {
return sqrt(-2.0 * log(u)) * cos(v);
}
}
__device__ double rng_normal_standard(
const uint4& rng_result,
int rng_component) {
return normal(
rng_result.x, rng_result.y, rng_result.z, rng_result.w, rng_component);
}
__device__ float rng_normal_standardf(
const uint4& rng_result,
int rng_component) {
return normalf(
(&rng_result.x)[rng_component / 2 * 2],
(&rng_result.y)[rng_component / 2 * 2],
rng_component);
}
__device__ double rng_normal_general(
const uint4& rng_result,
int rng_component,
double mean,
double std) {
auto normal01 = rng_normal_standard(rng_result, rng_component);
return normal01 * std + mean;
}
__device__ float rng_normal_generalf(
const uint4& rng_result,
int rng_component,
float mean,
float std) {
auto normal01 = rng_normal_standardf(rng_result, rng_component);
return normal01 * std + mean;
} | .file "tmpxft_000d5fe7_00000000-6_random_numbers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2044:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2044:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9mulhilo32jjPj
.type _Z9mulhilo32jjPj, @function
_Z9mulhilo32jjPj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9mulhilo32jjPj, .-_Z9mulhilo32jjPj
.globl _Z12single_round5uint45uint2
.type _Z12single_round5uint45uint2, @function
_Z12single_round5uint45uint2:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z12single_round5uint45uint2, .-_Z12single_round5uint45uint2
.globl _Z6philoxyyy
.type _Z6philoxyyy, @function
_Z6philoxyyy:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z6philoxyyy, .-_Z6philoxyyy
.globl _Z8uniformfj
.type _Z8uniformfj, @function
_Z8uniformfj:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z8uniformfj, .-_Z8uniformfj
.globl _Z7uniformjj
.type _Z7uniformjj, @function
_Z7uniformjj:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z7uniformjj, .-_Z7uniformjj
.globl _Z11rng_uniformRK5uint4i
.type _Z11rng_uniformRK5uint4i, @function
_Z11rng_uniformRK5uint4i:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z11rng_uniformRK5uint4i, .-_Z11rng_uniformRK5uint4i
.globl _Z12rng_uniformfRK5uint4i
.type _Z12rng_uniformfRK5uint4i, @function
_Z12rng_uniformfRK5uint4i:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z12rng_uniformfRK5uint4i, .-_Z12rng_uniformfRK5uint4i
.globl _Z17rng_uniform_rangeRK5uint4idd
.type _Z17rng_uniform_rangeRK5uint4idd, @function
_Z17rng_uniform_rangeRK5uint4idd:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z17rng_uniform_rangeRK5uint4idd, .-_Z17rng_uniform_rangeRK5uint4idd
.globl _Z18rng_uniform_rangefRK5uint4iff
.type _Z18rng_uniform_rangefRK5uint4iff, @function
_Z18rng_uniform_rangefRK5uint4iff:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z18rng_uniform_rangefRK5uint4iff, .-_Z18rng_uniform_rangefRK5uint4iff
.globl _Z7normalfjji
.type _Z7normalfjji, @function
_Z7normalfjji:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z7normalfjji, .-_Z7normalfjji
.globl _Z6normaljjjji
.type _Z6normaljjjji, @function
_Z6normaljjjji:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z6normaljjjji, .-_Z6normaljjjji
.globl _Z19rng_normal_standardRK5uint4i
.type _Z19rng_normal_standardRK5uint4i, @function
_Z19rng_normal_standardRK5uint4i:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Z19rng_normal_standardRK5uint4i, .-_Z19rng_normal_standardRK5uint4i
.globl _Z20rng_normal_standardfRK5uint4i
.type _Z20rng_normal_standardfRK5uint4i, @function
_Z20rng_normal_standardfRK5uint4i:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _Z20rng_normal_standardfRK5uint4i, .-_Z20rng_normal_standardfRK5uint4i
.globl _Z18rng_normal_generalRK5uint4idd
.type _Z18rng_normal_generalRK5uint4idd, @function
_Z18rng_normal_generalRK5uint4idd:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _Z18rng_normal_generalRK5uint4idd, .-_Z18rng_normal_generalRK5uint4idd
.globl _Z19rng_normal_generalfRK5uint4iff
.type _Z19rng_normal_generalfRK5uint4iff, @function
_Z19rng_normal_generalfRK5uint4iff:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _Z19rng_normal_generalfRK5uint4iff, .-_Z19rng_normal_generalfRK5uint4iff
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ unsigned int mulhilo32(
unsigned int a,
unsigned int b,
unsigned int* result_high) {
*result_high = __umulhi(a, b);
return a * b;
}
__device__ uint4 single_round(uint4 ctr, uint2 key) {
constexpr unsigned long kPhiloxSA = 0xD2511F53;
constexpr unsigned long kPhiloxSB = 0xCD9E8D57;
unsigned int hi0;
unsigned int hi1;
unsigned int lo0 = mulhilo32(kPhiloxSA, ctr.x, &hi0);
unsigned int lo1 = mulhilo32(kPhiloxSB, ctr.z, &hi1);
uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0};
return ret;
}
__device__ uint4 philox(
unsigned long long seed,
unsigned long long subsequence,
unsigned long long offset) {
constexpr unsigned long kPhilox10A = 0x9E3779B9;
constexpr unsigned long kPhilox10B = 0xBB67AE85;
uint2 key = {};
key.x = (unsigned int)seed;
key.y = (unsigned int)(seed >> 32);
uint4 counter = make_uint4(0, 0, 0, 0);
counter.x = (unsigned int)(offset);
counter.y = (unsigned int)(offset >> 32);
counter.z = (unsigned int)(subsequence);
counter.w = (unsigned int)(subsequence >> 32);
uint4 output = {};
uint2 key_ = key;
uint4 counter_ = counter;
for (int i = 0; i < 9; i++) {
counter_ = single_round(counter_, key_);
key_.x += (kPhilox10A);
key_.y += (kPhilox10B);
}
output = single_round(counter_, key_);
return output;
}
__device__ float uniformf(unsigned int x) {
constexpr float kRanInvM32 = 2.3283064e-10f; // Inverse of 2^32.
float result = x * kRanInvM32 + kRanInvM32 / 2.0f;
return result == 1 ? 0.0f : result;
}
__device__ double uniform(unsigned int x, unsigned int y) {
constexpr double kRan2Pow53Inv = 1.1102230246251565e-16;
const unsigned long long z =
(unsigned long long)x ^ ((unsigned long long)y << (53 - 32));
double result = z * kRan2Pow53Inv + (kRan2Pow53Inv / 2.0);
return result == 1 ? 0.0 : result;
}
__device__ double rng_uniform(const uint4& rng_result, int rng_component) {
return uniform(
(&rng_result.x)[rng_component * 2],
(&rng_result.x)[rng_component * 2 + 1]);
}
__device__ float rng_uniformf(const uint4& rng_result, int rng_component) {
return uniformf((&rng_result.x)[rng_component]);
}
__device__ double rng_uniform_range(
const uint4& rng_result,
int rng_component,
double from,
double to) {
auto range = to - from;
auto uniform01 = rng_uniform(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float rng_uniform_rangef(
const uint4& rng_result,
int rng_component,
float from,
float to) {
auto range = to - from;
auto uniform01 = rng_uniformf(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float normalf(unsigned int x, unsigned int y, int rng_component) {
float u = uniformf(x);
float v = uniformf(y) * 6.2831855f;
if (rng_component % 2 == 0) {
return sqrtf(-2.0f * logf(u)) * sinf(v);
} else {
return sqrtf(-2.0f * logf(u)) * cosf(v);
}
}
__device__ double normal(
unsigned int x0,
unsigned int x1,
unsigned int y0,
unsigned int y1,
int rng_component) {
double u = uniform(x0, x1);
double v = uniform(y0, y1) * 6.2831853071795860;
if (rng_component % 2 == 0) {
return sqrt(-2.0 * log(u)) * sin(v);
} else {
return sqrt(-2.0 * log(u)) * cos(v);
}
}
__device__ double rng_normal_standard(
const uint4& rng_result,
int rng_component) {
return normal(
rng_result.x, rng_result.y, rng_result.z, rng_result.w, rng_component);
}
__device__ float rng_normal_standardf(
const uint4& rng_result,
int rng_component) {
return normalf(
(&rng_result.x)[rng_component / 2 * 2],
(&rng_result.y)[rng_component / 2 * 2],
rng_component);
}
__device__ double rng_normal_general(
const uint4& rng_result,
int rng_component,
double mean,
double std) {
auto normal01 = rng_normal_standard(rng_result, rng_component);
return normal01 * std + mean;
}
__device__ float rng_normal_generalf(
const uint4& rng_result,
int rng_component,
float mean,
float std) {
auto normal01 = rng_normal_standardf(rng_result, rng_component);
return normal01 * std + mean;
} | #include <hip/hip_runtime.h>
__device__ unsigned int mulhilo32(
unsigned int a,
unsigned int b,
unsigned int* result_high) {
*result_high = __umulhi(a, b);
return a * b;
}
__device__ uint4 single_round(uint4 ctr, uint2 key) {
constexpr unsigned long kPhiloxSA = 0xD2511F53;
constexpr unsigned long kPhiloxSB = 0xCD9E8D57;
unsigned int hi0;
unsigned int hi1;
unsigned int lo0 = mulhilo32(kPhiloxSA, ctr.x, &hi0);
unsigned int lo1 = mulhilo32(kPhiloxSB, ctr.z, &hi1);
uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0};
return ret;
}
__device__ uint4 philox(
unsigned long long seed,
unsigned long long subsequence,
unsigned long long offset) {
constexpr unsigned long kPhilox10A = 0x9E3779B9;
constexpr unsigned long kPhilox10B = 0xBB67AE85;
uint2 key = {};
key.x = (unsigned int)seed;
key.y = (unsigned int)(seed >> 32);
uint4 counter = make_uint4(0, 0, 0, 0);
counter.x = (unsigned int)(offset);
counter.y = (unsigned int)(offset >> 32);
counter.z = (unsigned int)(subsequence);
counter.w = (unsigned int)(subsequence >> 32);
uint4 output = {};
uint2 key_ = key;
uint4 counter_ = counter;
for (int i = 0; i < 9; i++) {
counter_ = single_round(counter_, key_);
key_.x += (kPhilox10A);
key_.y += (kPhilox10B);
}
output = single_round(counter_, key_);
return output;
}
__device__ float uniformf(unsigned int x) {
constexpr float kRanInvM32 = 2.3283064e-10f; // Inverse of 2^32.
float result = x * kRanInvM32 + kRanInvM32 / 2.0f;
return result == 1 ? 0.0f : result;
}
__device__ double uniform(unsigned int x, unsigned int y) {
constexpr double kRan2Pow53Inv = 1.1102230246251565e-16;
const unsigned long long z =
(unsigned long long)x ^ ((unsigned long long)y << (53 - 32));
double result = z * kRan2Pow53Inv + (kRan2Pow53Inv / 2.0);
return result == 1 ? 0.0 : result;
}
__device__ double rng_uniform(const uint4& rng_result, int rng_component) {
return uniform(
(&rng_result.x)[rng_component * 2],
(&rng_result.x)[rng_component * 2 + 1]);
}
__device__ float rng_uniformf(const uint4& rng_result, int rng_component) {
return uniformf((&rng_result.x)[rng_component]);
}
__device__ double rng_uniform_range(
const uint4& rng_result,
int rng_component,
double from,
double to) {
auto range = to - from;
auto uniform01 = rng_uniform(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float rng_uniform_rangef(
const uint4& rng_result,
int rng_component,
float from,
float to) {
auto range = to - from;
auto uniform01 = rng_uniformf(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float normalf(unsigned int x, unsigned int y, int rng_component) {
float u = uniformf(x);
float v = uniformf(y) * 6.2831855f;
if (rng_component % 2 == 0) {
return sqrtf(-2.0f * logf(u)) * sinf(v);
} else {
return sqrtf(-2.0f * logf(u)) * cosf(v);
}
}
__device__ double normal(
unsigned int x0,
unsigned int x1,
unsigned int y0,
unsigned int y1,
int rng_component) {
double u = uniform(x0, x1);
double v = uniform(y0, y1) * 6.2831853071795860;
if (rng_component % 2 == 0) {
return sqrt(-2.0 * log(u)) * sin(v);
} else {
return sqrt(-2.0 * log(u)) * cos(v);
}
}
__device__ double rng_normal_standard(
const uint4& rng_result,
int rng_component) {
return normal(
rng_result.x, rng_result.y, rng_result.z, rng_result.w, rng_component);
}
__device__ float rng_normal_standardf(
const uint4& rng_result,
int rng_component) {
return normalf(
(&rng_result.x)[rng_component / 2 * 2],
(&rng_result.y)[rng_component / 2 * 2],
rng_component);
}
__device__ double rng_normal_general(
const uint4& rng_result,
int rng_component,
double mean,
double std) {
auto normal01 = rng_normal_standard(rng_result, rng_component);
return normal01 * std + mean;
}
__device__ float rng_normal_generalf(
const uint4& rng_result,
int rng_component,
float mean,
float std) {
auto normal01 = rng_normal_standardf(rng_result, rng_component);
return normal01 * std + mean;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ unsigned int mulhilo32(
unsigned int a,
unsigned int b,
unsigned int* result_high) {
*result_high = __umulhi(a, b);
return a * b;
}
__device__ uint4 single_round(uint4 ctr, uint2 key) {
constexpr unsigned long kPhiloxSA = 0xD2511F53;
constexpr unsigned long kPhiloxSB = 0xCD9E8D57;
unsigned int hi0;
unsigned int hi1;
unsigned int lo0 = mulhilo32(kPhiloxSA, ctr.x, &hi0);
unsigned int lo1 = mulhilo32(kPhiloxSB, ctr.z, &hi1);
uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0};
return ret;
}
__device__ uint4 philox(
unsigned long long seed,
unsigned long long subsequence,
unsigned long long offset) {
constexpr unsigned long kPhilox10A = 0x9E3779B9;
constexpr unsigned long kPhilox10B = 0xBB67AE85;
uint2 key = {};
key.x = (unsigned int)seed;
key.y = (unsigned int)(seed >> 32);
uint4 counter = make_uint4(0, 0, 0, 0);
counter.x = (unsigned int)(offset);
counter.y = (unsigned int)(offset >> 32);
counter.z = (unsigned int)(subsequence);
counter.w = (unsigned int)(subsequence >> 32);
uint4 output = {};
uint2 key_ = key;
uint4 counter_ = counter;
for (int i = 0; i < 9; i++) {
counter_ = single_round(counter_, key_);
key_.x += (kPhilox10A);
key_.y += (kPhilox10B);
}
output = single_round(counter_, key_);
return output;
}
__device__ float uniformf(unsigned int x) {
constexpr float kRanInvM32 = 2.3283064e-10f; // Inverse of 2^32.
float result = x * kRanInvM32 + kRanInvM32 / 2.0f;
return result == 1 ? 0.0f : result;
}
__device__ double uniform(unsigned int x, unsigned int y) {
constexpr double kRan2Pow53Inv = 1.1102230246251565e-16;
const unsigned long long z =
(unsigned long long)x ^ ((unsigned long long)y << (53 - 32));
double result = z * kRan2Pow53Inv + (kRan2Pow53Inv / 2.0);
return result == 1 ? 0.0 : result;
}
__device__ double rng_uniform(const uint4& rng_result, int rng_component) {
return uniform(
(&rng_result.x)[rng_component * 2],
(&rng_result.x)[rng_component * 2 + 1]);
}
__device__ float rng_uniformf(const uint4& rng_result, int rng_component) {
return uniformf((&rng_result.x)[rng_component]);
}
__device__ double rng_uniform_range(
const uint4& rng_result,
int rng_component,
double from,
double to) {
auto range = to - from;
auto uniform01 = rng_uniform(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float rng_uniform_rangef(
const uint4& rng_result,
int rng_component,
float from,
float to) {
auto range = to - from;
auto uniform01 = rng_uniformf(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float normalf(unsigned int x, unsigned int y, int rng_component) {
float u = uniformf(x);
float v = uniformf(y) * 6.2831855f;
if (rng_component % 2 == 0) {
return sqrtf(-2.0f * logf(u)) * sinf(v);
} else {
return sqrtf(-2.0f * logf(u)) * cosf(v);
}
}
__device__ double normal(
unsigned int x0,
unsigned int x1,
unsigned int y0,
unsigned int y1,
int rng_component) {
double u = uniform(x0, x1);
double v = uniform(y0, y1) * 6.2831853071795860;
if (rng_component % 2 == 0) {
return sqrt(-2.0 * log(u)) * sin(v);
} else {
return sqrt(-2.0 * log(u)) * cos(v);
}
}
__device__ double rng_normal_standard(
const uint4& rng_result,
int rng_component) {
return normal(
rng_result.x, rng_result.y, rng_result.z, rng_result.w, rng_component);
}
__device__ float rng_normal_standardf(
const uint4& rng_result,
int rng_component) {
return normalf(
(&rng_result.x)[rng_component / 2 * 2],
(&rng_result.y)[rng_component / 2 * 2],
rng_component);
}
__device__ double rng_normal_general(
const uint4& rng_result,
int rng_component,
double mean,
double std) {
auto normal01 = rng_normal_standard(rng_result, rng_component);
return normal01 * std + mean;
}
__device__ float rng_normal_generalf(
const uint4& rng_result,
int rng_component,
float mean,
float std) {
auto normal01 = rng_normal_standardf(rng_result, rng_component);
return normal01 * std + mean;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ unsigned int mulhilo32(
unsigned int a,
unsigned int b,
unsigned int* result_high) {
*result_high = __umulhi(a, b);
return a * b;
}
__device__ uint4 single_round(uint4 ctr, uint2 key) {
constexpr unsigned long kPhiloxSA = 0xD2511F53;
constexpr unsigned long kPhiloxSB = 0xCD9E8D57;
unsigned int hi0;
unsigned int hi1;
unsigned int lo0 = mulhilo32(kPhiloxSA, ctr.x, &hi0);
unsigned int lo1 = mulhilo32(kPhiloxSB, ctr.z, &hi1);
uint4 ret = {hi1 ^ ctr.y ^ key.x, lo1, hi0 ^ ctr.w ^ key.y, lo0};
return ret;
}
__device__ uint4 philox(
unsigned long long seed,
unsigned long long subsequence,
unsigned long long offset) {
constexpr unsigned long kPhilox10A = 0x9E3779B9;
constexpr unsigned long kPhilox10B = 0xBB67AE85;
uint2 key = {};
key.x = (unsigned int)seed;
key.y = (unsigned int)(seed >> 32);
uint4 counter = make_uint4(0, 0, 0, 0);
counter.x = (unsigned int)(offset);
counter.y = (unsigned int)(offset >> 32);
counter.z = (unsigned int)(subsequence);
counter.w = (unsigned int)(subsequence >> 32);
uint4 output = {};
uint2 key_ = key;
uint4 counter_ = counter;
for (int i = 0; i < 9; i++) {
counter_ = single_round(counter_, key_);
key_.x += (kPhilox10A);
key_.y += (kPhilox10B);
}
output = single_round(counter_, key_);
return output;
}
__device__ float uniformf(unsigned int x) {
constexpr float kRanInvM32 = 2.3283064e-10f; // Inverse of 2^32.
float result = x * kRanInvM32 + kRanInvM32 / 2.0f;
return result == 1 ? 0.0f : result;
}
__device__ double uniform(unsigned int x, unsigned int y) {
constexpr double kRan2Pow53Inv = 1.1102230246251565e-16;
const unsigned long long z =
(unsigned long long)x ^ ((unsigned long long)y << (53 - 32));
double result = z * kRan2Pow53Inv + (kRan2Pow53Inv / 2.0);
return result == 1 ? 0.0 : result;
}
__device__ double rng_uniform(const uint4& rng_result, int rng_component) {
return uniform(
(&rng_result.x)[rng_component * 2],
(&rng_result.x)[rng_component * 2 + 1]);
}
__device__ float rng_uniformf(const uint4& rng_result, int rng_component) {
return uniformf((&rng_result.x)[rng_component]);
}
__device__ double rng_uniform_range(
const uint4& rng_result,
int rng_component,
double from,
double to) {
auto range = to - from;
auto uniform01 = rng_uniform(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float rng_uniform_rangef(
const uint4& rng_result,
int rng_component,
float from,
float to) {
auto range = to - from;
auto uniform01 = rng_uniformf(rng_result, rng_component);
return from + range * uniform01;
}
__device__ float normalf(unsigned int x, unsigned int y, int rng_component) {
float u = uniformf(x);
float v = uniformf(y) * 6.2831855f;
if (rng_component % 2 == 0) {
return sqrtf(-2.0f * logf(u)) * sinf(v);
} else {
return sqrtf(-2.0f * logf(u)) * cosf(v);
}
}
__device__ double normal(
unsigned int x0,
unsigned int x1,
unsigned int y0,
unsigned int y1,
int rng_component) {
double u = uniform(x0, x1);
double v = uniform(y0, y1) * 6.2831853071795860;
if (rng_component % 2 == 0) {
return sqrt(-2.0 * log(u)) * sin(v);
} else {
return sqrt(-2.0 * log(u)) * cos(v);
}
}
__device__ double rng_normal_standard(
const uint4& rng_result,
int rng_component) {
return normal(
rng_result.x, rng_result.y, rng_result.z, rng_result.w, rng_component);
}
__device__ float rng_normal_standardf(
const uint4& rng_result,
int rng_component) {
return normalf(
(&rng_result.x)[rng_component / 2 * 2],
(&rng_result.y)[rng_component / 2 * 2],
rng_component);
}
__device__ double rng_normal_general(
const uint4& rng_result,
int rng_component,
double mean,
double std) {
auto normal01 = rng_normal_standard(rng_result, rng_component);
return normal01 * std + mean;
}
__device__ float rng_normal_generalf(
const uint4& rng_result,
int rng_component,
float mean,
float std) {
auto normal01 = rng_normal_standardf(rng_result, rng_component);
return normal01 * std + mean;
} | .text
.file "random_numbers.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5fe7_00000000-6_random_numbers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2044:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2044:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9mulhilo32jjPj
.type _Z9mulhilo32jjPj, @function
_Z9mulhilo32jjPj:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z9mulhilo32jjPj, .-_Z9mulhilo32jjPj
.globl _Z12single_round5uint45uint2
.type _Z12single_round5uint45uint2, @function
_Z12single_round5uint45uint2:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z12single_round5uint45uint2, .-_Z12single_round5uint45uint2
.globl _Z6philoxyyy
.type _Z6philoxyyy, @function
_Z6philoxyyy:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z6philoxyyy, .-_Z6philoxyyy
.globl _Z8uniformfj
.type _Z8uniformfj, @function
_Z8uniformfj:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z8uniformfj, .-_Z8uniformfj
.globl _Z7uniformjj
.type _Z7uniformjj, @function
_Z7uniformjj:
.LFB2031:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2031:
.size _Z7uniformjj, .-_Z7uniformjj
.globl _Z11rng_uniformRK5uint4i
.type _Z11rng_uniformRK5uint4i, @function
_Z11rng_uniformRK5uint4i:
.LFB2032:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2032:
.size _Z11rng_uniformRK5uint4i, .-_Z11rng_uniformRK5uint4i
.globl _Z12rng_uniformfRK5uint4i
.type _Z12rng_uniformfRK5uint4i, @function
_Z12rng_uniformfRK5uint4i:
.LFB2033:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2033:
.size _Z12rng_uniformfRK5uint4i, .-_Z12rng_uniformfRK5uint4i
.globl _Z17rng_uniform_rangeRK5uint4idd
.type _Z17rng_uniform_rangeRK5uint4idd, @function
_Z17rng_uniform_rangeRK5uint4idd:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _Z17rng_uniform_rangeRK5uint4idd, .-_Z17rng_uniform_rangeRK5uint4idd
.globl _Z18rng_uniform_rangefRK5uint4iff
.type _Z18rng_uniform_rangefRK5uint4iff, @function
_Z18rng_uniform_rangefRK5uint4iff:
.LFB2035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2035:
.size _Z18rng_uniform_rangefRK5uint4iff, .-_Z18rng_uniform_rangefRK5uint4iff
.globl _Z7normalfjji
.type _Z7normalfjji, @function
_Z7normalfjji:
.LFB2036:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2036:
.size _Z7normalfjji, .-_Z7normalfjji
.globl _Z6normaljjjji
.type _Z6normaljjjji, @function
_Z6normaljjjji:
.LFB2037:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2037:
.size _Z6normaljjjji, .-_Z6normaljjjji
.globl _Z19rng_normal_standardRK5uint4i
.type _Z19rng_normal_standardRK5uint4i, @function
_Z19rng_normal_standardRK5uint4i:
.LFB2038:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2038:
.size _Z19rng_normal_standardRK5uint4i, .-_Z19rng_normal_standardRK5uint4i
.globl _Z20rng_normal_standardfRK5uint4i
.type _Z20rng_normal_standardfRK5uint4i, @function
_Z20rng_normal_standardfRK5uint4i:
.LFB2039:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2039:
.size _Z20rng_normal_standardfRK5uint4i, .-_Z20rng_normal_standardfRK5uint4i
.globl _Z18rng_normal_generalRK5uint4idd
.type _Z18rng_normal_generalRK5uint4idd, @function
_Z18rng_normal_generalRK5uint4idd:
.LFB2040:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2040:
.size _Z18rng_normal_generalRK5uint4idd, .-_Z18rng_normal_generalRK5uint4idd
.globl _Z19rng_normal_generalfRK5uint4iff
.type _Z19rng_normal_generalfRK5uint4iff, @function
_Z19rng_normal_generalfRK5uint4iff:
.LFB2041:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2041:
.size _Z19rng_normal_generalfRK5uint4iff, .-_Z19rng_normal_generalfRK5uint4iff
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "random_numbers.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*!
* @file CudaHelpers.cu
* @author Zdenek Travnicek
* @date 15.2.2012
* @date 16.2.2013
* @copyright Institute of Intermedia, CTU in Prague, 2012 - 2013
* Distributed under modified BSD Licence, details in file doc/LICENSE
*
*/
#include <cuda.h>
namespace yuri {
namespace cuda {
void* map_array(cudaArray *array)
{
//texture<uchar4, cudaTextureType2D, cudaReadModeElementType> texRef;
//cudaBindTextureToArray(&texRef,array);
return 0;
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*!
* @file CudaHelpers.cu
* @author Zdenek Travnicek
* @date 15.2.2012
* @date 16.2.2013
* @copyright Institute of Intermedia, CTU in Prague, 2012 - 2013
* Distributed under modified BSD Licence, details in file doc/LICENSE
*
*/
#include <cuda.h>
namespace yuri {
namespace cuda {
void* map_array(cudaArray *array)
{
//texture<uchar4, cudaTextureType2D, cudaReadModeElementType> texRef;
//cudaBindTextureToArray(&texRef,array);
return 0;
}
}
} | .file "tmpxft_00094740_00000000-6_CudaHelpers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN4yuri4cuda9map_arrayEP9cudaArray
.type _ZN4yuri4cuda9map_arrayEP9cudaArray, @function
_ZN4yuri4cuda9map_arrayEP9cudaArray:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size _ZN4yuri4cuda9map_arrayEP9cudaArray, .-_ZN4yuri4cuda9map_arrayEP9cudaArray
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*!
* @file CudaHelpers.cu
* @author Zdenek Travnicek
* @date 15.2.2012
* @date 16.2.2013
* @copyright Institute of Intermedia, CTU in Prague, 2012 - 2013
* Distributed under modified BSD Licence, details in file doc/LICENSE
*
*/
#include <cuda.h>
namespace yuri {
namespace cuda {
void* map_array(cudaArray *array)
{
//texture<uchar4, cudaTextureType2D, cudaReadModeElementType> texRef;
//cudaBindTextureToArray(&texRef,array);
return 0;
}
}
} | /*!
* @file CudaHelpers.cu
* @author Zdenek Travnicek
* @date 15.2.2012
* @date 16.2.2013
* @copyright Institute of Intermedia, CTU in Prague, 2012 - 2013
* Distributed under modified BSD Licence, details in file doc/LICENSE
*
*/
#include <hip/hip_runtime.h>
namespace yuri {
namespace cuda {
void* map_array(hipArray *array)
{
//texture<uchar4, cudaTextureType2D, cudaReadModeElementType> texRef;
//cudaBindTextureToArray(&texRef,array);
return 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*!
* @file CudaHelpers.cu
* @author Zdenek Travnicek
* @date 15.2.2012
* @date 16.2.2013
* @copyright Institute of Intermedia, CTU in Prague, 2012 - 2013
* Distributed under modified BSD Licence, details in file doc/LICENSE
*
*/
#include <hip/hip_runtime.h>
namespace yuri {
namespace cuda {
void* map_array(hipArray *array)
{
//texture<uchar4, cudaTextureType2D, cudaReadModeElementType> texRef;
//cudaBindTextureToArray(&texRef,array);
return 0;
}
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*!
* @file CudaHelpers.cu
* @author Zdenek Travnicek
* @date 15.2.2012
* @date 16.2.2013
* @copyright Institute of Intermedia, CTU in Prague, 2012 - 2013
* Distributed under modified BSD Licence, details in file doc/LICENSE
*
*/
#include <hip/hip_runtime.h>
namespace yuri {
namespace cuda {
void* map_array(hipArray *array)
{
//texture<uchar4, cudaTextureType2D, cudaReadModeElementType> texRef;
//cudaBindTextureToArray(&texRef,array);
return 0;
}
}
} | .text
.file "CudaHelpers.hip"
.globl _ZN4yuri4cuda9map_arrayEP8hipArray # -- Begin function _ZN4yuri4cuda9map_arrayEP8hipArray
.p2align 4, 0x90
.type _ZN4yuri4cuda9map_arrayEP8hipArray,@function
_ZN4yuri4cuda9map_arrayEP8hipArray: # @_ZN4yuri4cuda9map_arrayEP8hipArray
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _ZN4yuri4cuda9map_arrayEP8hipArray, .Lfunc_end0-_ZN4yuri4cuda9map_arrayEP8hipArray
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094740_00000000-6_CudaHelpers.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN4yuri4cuda9map_arrayEP9cudaArray
.type _ZN4yuri4cuda9map_arrayEP9cudaArray, @function
_ZN4yuri4cuda9map_arrayEP9cudaArray:
.LFB2027:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2027:
.size _ZN4yuri4cuda9map_arrayEP9cudaArray, .-_ZN4yuri4cuda9map_arrayEP9cudaArray
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CudaHelpers.hip"
.globl _ZN4yuri4cuda9map_arrayEP8hipArray # -- Begin function _ZN4yuri4cuda9map_arrayEP8hipArray
.p2align 4, 0x90
.type _ZN4yuri4cuda9map_arrayEP8hipArray,@function
_ZN4yuri4cuda9map_arrayEP8hipArray: # @_ZN4yuri4cuda9map_arrayEP8hipArray
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size _ZN4yuri4cuda9map_arrayEP8hipArray, .Lfunc_end0-_ZN4yuri4cuda9map_arrayEP8hipArray
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cufft.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
#ifndef PI
#define PI 3.14159265359
#endif
extern "C"
__global__
void Shear(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, cufftComplex * input_fk // input
, cufftComplex * sheared_fk // sheared
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
float sz = 0;
float dz = 1.0f / nz;
cufftComplex kernel;
for (int i = 0,kz=0; i < nz; i++, k_1 += nx*ny,kz++)
{
sz += dz;
kernel.x = cosf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
kernel.y = -sinf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
sheared_fk[k_1].x = ldg(&input_fk[k_1].x)*kernel.x - ldg(&input_fk[k_1].y)*kernel.y;
sheared_fk[k_1].y = ldg(&input_fk[k_1].x)*kernel.y + ldg(&input_fk[k_1].y)*kernel.x;
}
}
}
extern "C"
__global__
void ShearTimeDomain(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, float * input // input
, float * sheared // sheared
)
{
int kz = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kz < nz && ky+1 < ny && ky)
{
float sz = (float)(kz) / (nz);
int k = nx*ny*kz + nx*ky;
float w0, w1, _w0, _w1, w00, w01, w10, w11;
float X, Y;
for (int i = 0, kx = 0; i+1 < nx; i++, kx++)
{
X = kx + sz*shift_x + center_shift_x;
Y = ky + sz*shift_y + center_shift_y;
w0 = X - (int)X; w1 = Y - (int)Y;
_w0 = 1 - w0; _w1 = 1 - w1;
//w0 *= w0;w1 *= w1;w0 *= w0;w1 *= w1;
//_w0 *= _w0;_w1 *= _w1;_w0 *= _w0;_w1 *= _w1;
//s0 = 1.0f / (w0 + _w0);s1 = 1.0f / (w1 + _w1);
//w0 *= s0;w1 *= s1;_w0 *= s0;_w1 *= s1;
w00 = _w0*_w1; w01 = _w0*w1; w10 = w0*_w1; w11 = w0*w1;
sheared[k + i] = w00*ldg(&input[k + i]) + w10*ldg(&input[k + i + 1]) + w01*ldg(&input[k + i + nx]) + w11*ldg(&input[k + i + 1 + nx]);
}
}
} | .file "tmpxft_000e3a81_00000000-6_cu_shear.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_
.type _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_, @function
_Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_:
.LFB2105:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq Shear(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_, .-_Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_
.globl Shear
.type Shear, @function
Shear:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z5ShearffffiiiP6float2S0_ffffiiiP6float2S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size Shear, .-Shear
.globl _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_
.type _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_, @function
_Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_:
.LFB2107:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq ShearTimeDomain(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_, .-_Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_
.globl ShearTimeDomain
.type ShearTimeDomain, @function
ShearTimeDomain:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z15ShearTimeDomainffffiiiPfS_ffffiiiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size ShearTimeDomain, .-ShearTimeDomain
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ShearTimeDomain"
.LC1:
.string "Shear"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ShearTimeDomain(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq Shear(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cufft.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
#ifndef PI
#define PI 3.14159265359
#endif
extern "C"
__global__
void Shear(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, cufftComplex * input_fk // input
, cufftComplex * sheared_fk // sheared
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
float sz = 0;
float dz = 1.0f / nz;
cufftComplex kernel;
for (int i = 0,kz=0; i < nz; i++, k_1 += nx*ny,kz++)
{
sz += dz;
kernel.x = cosf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
kernel.y = -sinf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
sheared_fk[k_1].x = ldg(&input_fk[k_1].x)*kernel.x - ldg(&input_fk[k_1].y)*kernel.y;
sheared_fk[k_1].y = ldg(&input_fk[k_1].x)*kernel.y + ldg(&input_fk[k_1].y)*kernel.x;
}
}
}
extern "C"
__global__
void ShearTimeDomain(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, float * input // input
, float * sheared // sheared
)
{
int kz = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kz < nz && ky+1 < ny && ky)
{
float sz = (float)(kz) / (nz);
int k = nx*ny*kz + nx*ky;
float w0, w1, _w0, _w1, w00, w01, w10, w11;
float X, Y;
for (int i = 0, kx = 0; i+1 < nx; i++, kx++)
{
X = kx + sz*shift_x + center_shift_x;
Y = ky + sz*shift_y + center_shift_y;
w0 = X - (int)X; w1 = Y - (int)Y;
_w0 = 1 - w0; _w1 = 1 - w1;
//w0 *= w0;w1 *= w1;w0 *= w0;w1 *= w1;
//_w0 *= _w0;_w1 *= _w1;_w0 *= _w0;_w1 *= _w1;
//s0 = 1.0f / (w0 + _w0);s1 = 1.0f / (w1 + _w1);
//w0 *= s0;w1 *= s1;_w0 *= s0;_w1 *= s1;
w00 = _w0*_w1; w01 = _w0*w1; w10 = w0*_w1; w11 = w0*w1;
sheared[k + i] = w00*ldg(&input[k + i]) + w10*ldg(&input[k + i + 1]) + w01*ldg(&input[k + i + nx]) + w11*ldg(&input[k + i + 1 + nx]);
}
}
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
#ifndef PI
#define PI 3.14159265359
#endif
extern "C"
__global__
void Shear(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, hipfftComplex * input_fk // input
, hipfftComplex * sheared_fk // sheared
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
float sz = 0;
float dz = 1.0f / nz;
hipfftComplex kernel;
for (int i = 0,kz=0; i < nz; i++, k_1 += nx*ny,kz++)
{
sz += dz;
kernel.x = cosf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
kernel.y = -sinf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
sheared_fk[k_1].x = ldg(&input_fk[k_1].x)*kernel.x - ldg(&input_fk[k_1].y)*kernel.y;
sheared_fk[k_1].y = ldg(&input_fk[k_1].x)*kernel.y + ldg(&input_fk[k_1].y)*kernel.x;
}
}
}
extern "C"
__global__
void ShearTimeDomain(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, float * input // input
, float * sheared // sheared
)
{
int kz = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kz < nz && ky+1 < ny && ky)
{
float sz = (float)(kz) / (nz);
int k = nx*ny*kz + nx*ky;
float w0, w1, _w0, _w1, w00, w01, w10, w11;
float X, Y;
for (int i = 0, kx = 0; i+1 < nx; i++, kx++)
{
X = kx + sz*shift_x + center_shift_x;
Y = ky + sz*shift_y + center_shift_y;
w0 = X - (int)X; w1 = Y - (int)Y;
_w0 = 1 - w0; _w1 = 1 - w1;
//w0 *= w0;w1 *= w1;w0 *= w0;w1 *= w1;
//_w0 *= _w0;_w1 *= _w1;_w0 *= _w0;_w1 *= _w1;
//s0 = 1.0f / (w0 + _w0);s1 = 1.0f / (w1 + _w1);
//w0 *= s0;w1 *= s1;_w0 *= s0;_w1 *= s1;
w00 = _w0*_w1; w01 = _w0*w1; w10 = w0*_w1; w11 = w0*w1;
sheared[k + i] = w00*ldg(&input[k + i]) + w10*ldg(&input[k + i + 1]) + w01*ldg(&input[k + i + nx]) + w11*ldg(&input[k + i + 1 + nx]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
#ifndef PI
#define PI 3.14159265359
#endif
extern "C"
__global__
void Shear(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, hipfftComplex * input_fk // input
, hipfftComplex * sheared_fk // sheared
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
float sz = 0;
float dz = 1.0f / nz;
hipfftComplex kernel;
for (int i = 0,kz=0; i < nz; i++, k_1 += nx*ny,kz++)
{
sz += dz;
kernel.x = cosf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
kernel.y = -sinf((2 * PI*(kx*(center_shift_x + sz*shift_x) + ky*(center_shift_y + sz*shift_y))) * dz);
sheared_fk[k_1].x = ldg(&input_fk[k_1].x)*kernel.x - ldg(&input_fk[k_1].y)*kernel.y;
sheared_fk[k_1].y = ldg(&input_fk[k_1].x)*kernel.y + ldg(&input_fk[k_1].y)*kernel.x;
}
}
}
extern "C"
__global__
void ShearTimeDomain(
float center_shift_y
, float center_shift_x
, float shift_y
, float shift_x
, int nz
, int ny
, int nx
, float * input // input
, float * sheared // sheared
)
{
int kz = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kz < nz && ky+1 < ny && ky)
{
float sz = (float)(kz) / (nz);
int k = nx*ny*kz + nx*ky;
float w0, w1, _w0, _w1, w00, w01, w10, w11;
float X, Y;
for (int i = 0, kx = 0; i+1 < nx; i++, kx++)
{
X = kx + sz*shift_x + center_shift_x;
Y = ky + sz*shift_y + center_shift_y;
w0 = X - (int)X; w1 = Y - (int)Y;
_w0 = 1 - w0; _w1 = 1 - w1;
//w0 *= w0;w1 *= w1;w0 *= w0;w1 *= w1;
//_w0 *= _w0;_w1 *= _w1;_w0 *= _w0;_w1 *= _w1;
//s0 = 1.0f / (w0 + _w0);s1 = 1.0f / (w1 + _w1);
//w0 *= s0;w1 *= s1;_w0 *= s0;_w1 *= s1;
w00 = _w0*_w1; w01 = _w0*w1; w10 = w0*_w1; w11 = w0*w1;
sheared[k + i] = w00*ldg(&input[k + i]) + w10*ldg(&input[k + i + 1]) + w01*ldg(&input[k + i + nx]) + w11*ldg(&input[k + i + 1 + nx]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected Shear
.globl Shear
.p2align 8
.type Shear,@function
Shear:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[12:13], s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[4:5], null, s14, s3, v[1:2]
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s13, v4
v_cmp_gt_i32_e64 s2, s12, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b32 s14, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_12
v_cvt_f32_i32_e32 v0, s14
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b128 s[8:11], s[0:1], 0x20
s_mul_i32 s0, s13, s12
s_mov_b32 s12, 0x54442eea
s_ashr_i32 s1, s0, 31
v_div_scale_f32 v1, null, v0, v0, 1.0
s_lshl_b64 s[2:3], s[0:1], 3
s_mov_b32 s15, 0x7fffff
s_mov_b32 s16, 0xb94c1982
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v1
s_mov_b32 s17, 0x37d75334
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v1, v3, 1.0
v_fmac_f32_e32 v3, v5, v3
v_div_scale_f32 v5, vcc_lo, 1.0, v0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v3
v_fma_f32 v7, -v1, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v3
v_fma_f32 v1, -v1, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v1, v1, v3, v6
v_cvt_f32_i32_e32 v6, v2
v_div_fixup_f32 v5, v1, v0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[0:1], v5
v_mad_u64_u32 v[7:8], null, v2, s13, v[4:5]
v_cvt_f32_i32_e32 v4, v4
s_mov_b32 s13, 0x401921fb
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[7:8]
v_mov_b32_e32 v7, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v14, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v3, vcc_lo
v_dual_mul_f32 v18, v10, v10 :: v_dual_and_b32 v19, 1, v11
v_dual_mul_f32 v20, v12, v12 :: v_dual_lshlrev_b32 v11, 30, v11
s_clause 0x1
global_load_b32 v16, v[14:15], off offset:4
global_load_b32 v17, v[14:15], off
v_dual_fmaak_f32 v22, s16, v18, 0x3c0881c4 :: v_dual_and_b32 v21, 1, v13
v_dual_fmaak_f32 v24, s16, v20, 0x3c0881c4 :: v_dual_lshlrev_b32 v13, 30, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v19
v_xor_b32_e32 v9, v9, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmaak_f32 v22, v18, v22, 0xbe2aaa9d
v_fmaak_f32 v25, s17, v20, 0xbab64f3b
v_fmaak_f32 v24, v20, v24, 0xbe2aaa9d
v_fmaak_f32 v23, s17, v18, 0xbab64f3b
v_dual_mul_f32 v22, v18, v22 :: v_dual_and_b32 v13, 0x80000000, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v25, v20, v25, 0x3d2aabf7
v_dual_mul_f32 v24, v20, v24 :: v_dual_fmaak_f32 v23, v18, v23, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v10, v10, v22 :: v_dual_and_b32 v11, 0x80000000, v11
v_fmaak_f32 v25, v20, v25, 0xbf000004
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_fmac_f32_e32 v12, v12, v24
s_add_i32 s14, s14, -1
s_cmp_lg_u32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v20, v20, v25, 1.0
v_fmaak_f32 v23, v18, v23, 0xbf000004
v_fma_f32 v18, v18, v23, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, -v10, v18, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v21
v_xor_b32_e32 v10, v11, v10
v_cndmask_b32_e32 v12, v20, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor3_b32 v9, v9, v13, v12
v_cndmask_b32_e32 v10, 0x7fc00000, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v11, 0x7fc00000, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(1)
v_mul_f32_e32 v12, v16, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v12, v10, v17
global_store_b32 v[8:9], v12, off
s_clause 0x1
global_load_b32 v12, v[14:15], off
global_load_b32 v13, v[14:15], off offset:4
s_waitcnt vmcnt(1)
v_mul_f32_e32 v11, v12, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v10, v10, v13, -v11
global_store_b32 v[8:9], v10, off offset:4
s_cbranch_scc0 .LBB0_12
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v5, v7
s_waitcnt lgkmcnt(0)
v_fma_f32 v8, v7, s6, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v6
v_fma_f32 v9, v7, s7, s5
v_fmac_f32_e32 v8, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[8:9], v8
v_mul_f64 v[8:9], v[8:9], s[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[8:9], v[0:1]
v_cvt_f32_f64_e32 v8, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v9, 0x7fffffff, v8
v_cmp_ngt_f32_e64 s18, 0x48000000, |v8|
s_and_saveexec_b32 s0, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s19, exec_lo, s0
s_cbranch_execz .LBB0_6
v_and_or_b32 v20, v9, s15, 0x800000
v_mov_b32_e32 v12, 0
v_lshrrev_b32_e32 v17, 23, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v20, 0xfe5163ab, 0
v_add_nc_u32_e32 v18, 0xffffff88, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v18
v_mad_u64_u32 v[13:14], null, v20, 0x3c439041, v[11:12]
v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v14
v_add_nc_u32_e32 v19, v19, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[14:15], null, v20, 0xdb629599, v[11:12]
v_cmp_lt_u32_e64 s0, 31, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v21, 0, 0xffffffe0, s0
v_dual_mov_b32 v11, v15 :: v_dual_cndmask_b32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v21, v21, v19
v_mad_u64_u32 v[15:16], null, v20, 0xf534ddc0, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v21
v_mov_b32_e32 v11, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v13, v15, v13, vcc_lo
v_mad_u64_u32 v[16:17], null, v20, 0xfc2757d1, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, v13, v10, s0
v_mov_b32_e32 v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[17:18], null, v20, 0x4e441529, v[11:12]
v_mov_b32_e32 v11, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[18:19], null, v20, 0xa2f9836e, v[11:12]
v_cndmask_b32_e64 v11, 0, 0xffffffe0, s1
v_dual_cndmask_b32 v12, v17, v15 :: v_dual_add_nc_u32 v11, v11, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v18, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
v_cndmask_b32_e32 v16, v16, v14, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v15, v18, v12, s0
v_cndmask_b32_e64 v17, v17, v18, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v16, s0
v_sub_nc_u32_e32 v18, 32, v11
v_cndmask_b32_e64 v16, v16, v13, s0
v_cndmask_b32_e64 v17, v17, v15, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, v15, v12, s1
v_cndmask_b32_e64 v12, v12, v16, s1
v_cndmask_b32_e64 v10, v16, v10, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v19, v17, v15, v18
v_alignbit_b32 v14, v15, v12, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v11, v19, v17, vcc_lo
v_alignbit_b32 v17, v12, v10, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v15, vcc_lo
v_bfe_u32 v14, v11, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v12, v17, v12, vcc_lo
v_alignbit_b32 v15, v11, v13, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v16, 0, v14
v_alignbit_b32 v13, v13, v12, 30
v_alignbit_b32 v10, v12, v10, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v15, v15, v16
v_xor_b32_e32 v12, v13, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v10, v16
v_clz_i32_u32_e32 v17, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v17, 32, v17
v_sub_nc_u32_e32 v13, 31, v17
v_lshlrev_b32_e32 v19, 23, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_alignbit_b32 v15, v15, v12, v13
v_alignbit_b32 v10, v12, v10, v13
v_lshrrev_b32_e32 v13, 29, v11
v_lshrrev_b32_e32 v11, 30, v11
v_alignbit_b32 v12, v15, v10, 9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v13, 31, v13
v_lshrrev_b32_e32 v15, 9, v15
v_add_nc_u32_e32 v11, v14, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_clz_i32_u32_e32 v16, v12
v_or_b32_e32 v18, 0.5, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v16, 32, v16
v_sub_nc_u32_e32 v18, v18, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v20, 31, v16
v_alignbit_b32 v10, v12, v10, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v12, v15, v18
v_add_lshl_u32 v15, v16, v17, 23
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v16, 0x3fc90fda, v12
v_sub_nc_u32_e32 v10, v10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, v12, 0x3fc90fda, -v16
v_add_nc_u32_e32 v10, 0x33000000, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v15, 0x33a22168, v12
v_or_b32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, 0x3fc90fda, v10
v_add_f32_e32 v10, v16, v15
.LBB0_6:
s_and_not1_saveexec_b32 s0, s19
v_mul_f32_e64 v10, 0x3f22f983, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v11, v10
v_fma_f32 v10, v11, 0xbfc90fda, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, 0xb3a22168, v11
v_fmac_f32_e32 v10, 0xa7c234c4, v11
v_cvt_i32_f32_e32 v11, v11
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s18, exec_lo, s0
s_cbranch_execz .LBB0_10
v_and_or_b32 v22, v9, s15, 0x800000
v_mov_b32_e32 v14, 0
v_lshrrev_b32_e32 v19, 23, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v22, 0xfe5163ab, 0
v_add_nc_u32_e32 v20, 0xffffff88, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v20
v_mad_u64_u32 v[15:16], null, v22, 0x3c439041, v[13:14]
v_cndmask_b32_e64 v21, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v13, v16
v_add_nc_u32_e32 v21, v21, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[16:17], null, v22, 0xdb629599, v[13:14]
v_cmp_lt_u32_e64 s0, 31, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v23, 0, 0xffffffe0, s0
v_dual_mov_b32 v13, v17 :: v_dual_cndmask_b32 v12, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v23, v23, v21
v_mad_u64_u32 v[17:18], null, v22, 0xf534ddc0, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v23
v_mov_b32_e32 v13, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v17, v15, vcc_lo
v_mad_u64_u32 v[18:19], null, v22, 0xfc2757d1, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, v15, v12, s0
v_mov_b32_e32 v13, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[19:20], null, v22, 0x4e441529, v[13:14]
v_mov_b32_e32 v13, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[20:21], null, v22, 0xa2f9836e, v[13:14]
v_cndmask_b32_e64 v13, 0, 0xffffffe0, s1
v_dual_cndmask_b32 v14, v19, v17 :: v_dual_add_nc_u32 v13, v13, v23
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v20, v20, v18 :: v_dual_cndmask_b32 v19, v21, v19
v_cndmask_b32_e32 v18, v18, v16, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v17, v20, v14, s0
v_cndmask_b32_e64 v19, v19, v20, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v14, v14, v18, s0
v_sub_nc_u32_e32 v20, 32, v13
v_cndmask_b32_e64 v18, v18, v15, s0
v_cndmask_b32_e64 v19, v19, v17, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v17, v17, v14, s1
v_cndmask_b32_e64 v14, v14, v18, s1
v_cndmask_b32_e64 v12, v18, v12, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v21, v19, v17, v20
v_alignbit_b32 v16, v17, v14, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v13, v21, v19, vcc_lo
v_alignbit_b32 v19, v14, v12, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v15, v16, v17, vcc_lo
v_bfe_u32 v16, v13, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v14, v19, v14, vcc_lo
v_alignbit_b32 v17, v13, v15, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v18, 0, v16
v_alignbit_b32 v15, v15, v14, 30
v_alignbit_b32 v12, v14, v12, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v17, v17, v18
v_xor_b32_e32 v14, v15, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v12, v12, v18
v_clz_i32_u32_e32 v19, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v19, 32, v19
v_sub_nc_u32_e32 v15, 31, v19
v_lshlrev_b32_e32 v21, 23, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_alignbit_b32 v17, v17, v14, v15
v_alignbit_b32 v12, v14, v12, v15
v_lshrrev_b32_e32 v15, 29, v13
v_lshrrev_b32_e32 v13, 30, v13
v_alignbit_b32 v14, v17, v12, 9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v15, 31, v15
v_lshrrev_b32_e32 v17, 9, v17
v_add_nc_u32_e32 v13, v16, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_clz_i32_u32_e32 v18, v14
v_or_b32_e32 v20, 0.5, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v18, 32, v18
v_sub_nc_u32_e32 v20, v20, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v22, 31, v18
v_alignbit_b32 v12, v14, v12, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v14, v17, v20
v_add_lshl_u32 v17, v18, v19, 23
v_lshrrev_b32_e32 v12, 9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v18, 0x3fc90fda, v14
v_sub_nc_u32_e32 v12, v12, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, v14, 0x3fc90fda, -v18
v_add_nc_u32_e32 v12, 0x33000000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, 0x33a22168, v14
v_or_b32_e32 v12, v12, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, 0x3fc90fda, v12
v_add_f32_e32 v12, v18, v17
.LBB0_10:
s_and_not1_saveexec_b32 s0, s18
s_cbranch_execz .LBB0_3
v_mul_f32_e64 v12, 0x3f22f983, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v13, v12
v_fma_f32 v12, v13, 0xbfc90fda, |v8|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, 0xb3a22168, v13
v_fmac_f32_e32 v12, 0xa7c234c4, v13
v_cvt_i32_f32_e32 v13, v13
s_branch .LBB0_3
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel Shear
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size Shear, .Lfunc_end0-Shear
.section .AMDGPU.csdata,"",@progbits
.text
.protected ShearTimeDomain
.globl ShearTimeDomain
.p2align 8
.type ShearTimeDomain,@function
ShearTimeDomain:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_4
s_load_b32 s2, s[2:3], 0xc
s_load_b64 s[8:9], s[0:1], 0x14
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v2, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v2
v_cmp_ne_u32_e64 s2, 0, v2
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_cmp_gt_i32 s9, 1
s_cselect_b32 s3, -1, 0
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB1_4
v_cvt_f32_i32_e32 v3, v1
v_cvt_f32_i32_e32 v4, s4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v1, v1, s8
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v4, v4, v3
v_div_scale_f32 v8, vcc_lo, v3, v4, v3
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
v_cvt_f32_i32_e32 v6, v2
v_add_nc_u32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v4, v5, v4, v3
v_mul_lo_u32 v2, v2, s9
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, s6, v4
v_add_f32_e32 v3, s4, v6
v_add3_u32 v6, v0, v1, s15
s_mov_b32 s4, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v5, v3
v_mad_u64_u32 v[0:1], null, s9, v6, s[4:5]
v_mul_f32_e32 v1, s7, v4
s_add_i32 s4, s9, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v5, v5
v_sub_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v4, 1.0, v3
.LBB1_3:
v_add_nc_u32_e32 v5, s10, v2
v_add_nc_u32_e32 v7, s10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v9, 1, v5
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v11, 1, v7
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v13, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v14, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v7, vcc_lo, s0, v7
s_clause 0x1
global_load_b32 v13, v[13:14], off
global_load_b32 v14, v[9:10], off
v_lshlrev_b64 v[9:10], 2, v[11:12]
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[9:10], off
v_cvt_f32_i32_e32 v9, s10
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_add_i32 s10, s10, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v1, v9
s_cmp_lg_u32 s4, s10
v_add_f32_e32 v9, s5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v10, v9
v_cvt_f32_i32_e32 v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v9, v10
v_sub_f32_e32 v10, 1.0, v9
v_mul_f32_e32 v11, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v9, v3, v9 :: v_dual_mul_f32 v12, v4, v10
v_mul_f32_e32 v10, v3, v10
s_waitcnt vmcnt(2)
v_mul_f32_e32 v11, v11, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v12, v13
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v11, v10, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v11, v9, v8
global_store_b32 v[5:6], v11, off
s_cbranch_scc1 .LBB1_3
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel ShearTimeDomain
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size ShearTimeDomain, .Lfunc_end1-ShearTimeDomain
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: Shear
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: Shear.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: ShearTimeDomain
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: ShearTimeDomain.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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